drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll gen4_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 111 {
 112         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 113
 114         return intel_dig_port->base.base.dev;
 115 }
 116
 117 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 118 {
 119         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 120 }
 121
 122 static void intel_dp_link_down(struct intel_encoder *encoder,
 123                                const struct intel_crtc_state *old_crtc_state);
 124 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 125 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 126 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 127                                            const struct intel_crtc_state *crtc_state);
 128 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 129                                       enum pipe pipe);
 130 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 131
 132 /* update sink rates from dpcd */
 133 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 134 {
 135         static const int dp_rates[] = {
 136                 162000, 270000, 540000, 810000
 137         };
 138         int i, max_rate;
 139
 140         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 141
 142         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 143                 if (dp_rates[i] > max_rate)
 144                         break;
 145                 intel_dp->sink_rates[i] = dp_rates[i];
 146         }
 147
 148         intel_dp->num_sink_rates = i;
 149 }
 150
 151 /* Get length of rates array potentially limited by max_rate. */
 152 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 153 {
 154         int i;
 155
 156         /* Limit results by potentially reduced max rate */
 157         for (i = 0; i < len; i++) {
 158                 if (rates[len - i - 1] <= max_rate)
 159                         return len - i;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /* Get length of common rates array potentially limited by max_rate. */
 166 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 167                                           int max_rate)
 168 {
 169         return intel_dp_rate_limit_len(intel_dp->common_rates,
 170                                        intel_dp->num_common_rates, max_rate);
 171 }
 172
 173 /* Theoretical max between source and sink */
 174 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 175 {
 176         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 177 }
 178
 179 /* Theoretical max between source and sink */
 180 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 181 {
 182         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 183         int source_max = intel_dig_port->max_lanes;
 184         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 185
 186         return min(source_max, sink_max);
 187 }
 188
 189 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 190 {
 191         return intel_dp->max_link_lane_count;
 192 }
 193
 194 int
 195 intel_dp_link_required(int pixel_clock, int bpp)
 196 {
 197         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 198         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 199 }
 200
 201 int
 202 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 203 {
 204         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 205          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 206          * is transmitted every LS_Clk per lane, there is no need to account for
 207          * the channel encoding that is done in the PHY layer here.
 208          */
 209
 210         return max_link_clock * max_lanes;
 211 }
 212
 213 static int
 214 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 215 {
 216         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 217         struct intel_encoder *encoder = &intel_dig_port->base;
 218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 219         int max_dotclk = dev_priv->max_dotclk_freq;
 220         int ds_max_dotclk;
 221
 222         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 223
 224         if (type != DP_DS_PORT_TYPE_VGA)
 225                 return max_dotclk;
 226
 227         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 228                                                     intel_dp->downstream_ports);
 229
 230         if (ds_max_dotclk != 0)
 231                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 232
 233         return max_dotclk;
 234 }
 235
 236 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 237 {
 238         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 239         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 240         enum port port = dig_port->base.port;
 241
 242         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 243
 244         /* Low voltage SKUs are limited to max of 5.4G */
 245         if (voltage == VOLTAGE_INFO_0_85V)
 246                 return 540000;
 247
 248         /* For this SKU 8.1G is supported in all ports */
 249         if (IS_CNL_WITH_PORT_F(dev_priv))
 250                 return 810000;
 251
 252         /* For other SKUs, max rate on ports A and D is 5.4G */
 253         if (port == PORT_A || port == PORT_D)
 254                 return 540000;
 255
 256         return 810000;
 257 }
 258
 259 static void
 260 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 261 {
 262         /* The values must be in increasing order */
 263         static const int cnl_rates[] = {
 264                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 265         };
 266         static const int bxt_rates[] = {
 267                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 268         };
 269         static const int skl_rates[] = {
 270                 162000, 216000, 270000, 324000, 432000, 540000
 271         };
 272         static const int hsw_rates[] = {
 273                 162000, 270000, 540000
 274         };
 275         static const int g4x_rates[] = {
 276                 162000, 270000
 277         };
 278         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 279         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 280         const struct ddi_vbt_port_info *info =
 281                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 282         const int *source_rates;
 283         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 284
 285         /* This should only be done once */
 286         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 287
 288         if (IS_CANNONLAKE(dev_priv)) {
 289                 source_rates = cnl_rates;
 290                 size = ARRAY_SIZE(cnl_rates);
 291                 max_rate = cnl_max_source_rate(intel_dp);
 292         } else if (IS_GEN9_LP(dev_priv)) {
 293                 source_rates = bxt_rates;
 294                 size = ARRAY_SIZE(bxt_rates);
 295         } else if (IS_GEN9_BC(dev_priv)) {
 296                 source_rates = skl_rates;
 297                 size = ARRAY_SIZE(skl_rates);
 298         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 299                    IS_BROADWELL(dev_priv)) {
 300                 source_rates = hsw_rates;
 301                 size = ARRAY_SIZE(hsw_rates);
 302         } else {
 303                 source_rates = g4x_rates;
 304                 size = ARRAY_SIZE(g4x_rates);
 305         }
 306
 307         if (max_rate && vbt_max_rate)
 308                 max_rate = min(max_rate, vbt_max_rate);
 309         else if (vbt_max_rate)
 310                 max_rate = vbt_max_rate;
 311
 312         if (max_rate)
 313                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 314
 315         intel_dp->source_rates = source_rates;
 316         intel_dp->num_source_rates = size;
 317 }
 318
 319 static int intersect_rates(const int *source_rates, int source_len,
 320                            const int *sink_rates, int sink_len,
 321                            int *common_rates)
 322 {
 323         int i = 0, j = 0, k = 0;
 324
 325         while (i < source_len && j < sink_len) {
 326                 if (source_rates[i] == sink_rates[j]) {
 327                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 328                                 return k;
 329                         common_rates[k] = source_rates[i];
 330                         ++k;
 331                         ++i;
 332                         ++j;
 333                 } else if (source_rates[i] < sink_rates[j]) {
 334                         ++i;
 335                 } else {
 336                         ++j;
 337                 }
 338         }
 339         return k;
 340 }
 341
 342 /* return index of rate in rates array, or -1 if not found */
 343 static int intel_dp_rate_index(const int *rates, int len, int rate)
 344 {
 345         int i;
 346
 347         for (i = 0; i < len; i++)
 348                 if (rate == rates[i])
 349                         return i;
 350
 351         return -1;
 352 }
 353
 354 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 355 {
 356         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 357
 358         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 359                                                      intel_dp->num_source_rates,
 360                                                      intel_dp->sink_rates,
 361                                                      intel_dp->num_sink_rates,
 362                                                      intel_dp->common_rates);
 363
 364         /* Paranoia, there should always be something in common. */
 365         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 366                 intel_dp->common_rates[0] = 162000;
 367                 intel_dp->num_common_rates = 1;
 368         }
 369 }
 370
 371 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 372                                        uint8_t lane_count)
 373 {
 374         /*
 375          * FIXME: we need to synchronize the current link parameters with
 376          * hardware readout. Currently fast link training doesn't work on
 377          * boot-up.
 378          */
 379         if (link_rate == 0 ||
 380             link_rate > intel_dp->max_link_rate)
 381                 return false;
 382
 383         if (lane_count == 0 ||
 384             lane_count > intel_dp_max_lane_count(intel_dp))
 385                 return false;
 386
 387         return true;
 388 }
 389
 390 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 391                                             int link_rate, uint8_t lane_count)
 392 {
 393         int index;
 394
 395         index = intel_dp_rate_index(intel_dp->common_rates,
 396                                     intel_dp->num_common_rates,
 397                                     link_rate);
 398         if (index > 0) {
 399                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 400                 intel_dp->max_link_lane_count = lane_count;
 401         } else if (lane_count > 1) {
 402                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 403                 intel_dp->max_link_lane_count = lane_count >> 1;
 404         } else {
 405                 DRM_ERROR("Link Training Unsuccessful\n");
 406                 return -1;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static enum drm_mode_status
 413 intel_dp_mode_valid(struct drm_connector *connector,
 414                     struct drm_display_mode *mode)
 415 {
 416         struct intel_dp *intel_dp = intel_attached_dp(connector);
 417         struct intel_connector *intel_connector = to_intel_connector(connector);
 418         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 419         int target_clock = mode->clock;
 420         int max_rate, mode_rate, max_lanes, max_link_clock;
 421         int max_dotclk;
 422
 423         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 424
 425         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 426                 if (mode->hdisplay > fixed_mode->hdisplay)
 427                         return MODE_PANEL;
 428
 429                 if (mode->vdisplay > fixed_mode->vdisplay)
 430                         return MODE_PANEL;
 431
 432                 target_clock = fixed_mode->clock;
 433         }
 434
 435         max_link_clock = intel_dp_max_link_rate(intel_dp);
 436         max_lanes = intel_dp_max_lane_count(intel_dp);
 437
 438         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 439         mode_rate = intel_dp_link_required(target_clock, 18);
 440
 441         if (mode_rate > max_rate || target_clock > max_dotclk)
 442                 return MODE_CLOCK_HIGH;
 443
 444         if (mode->clock < 10000)
 445                 return MODE_CLOCK_LOW;
 446
 447         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 448                 return MODE_H_ILLEGAL;
 449
 450         return MODE_OK;
 451 }
 452
 453 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 454 {
 455         int     i;
 456         uint32_t v = 0;
 457
 458         if (src_bytes > 4)
 459                 src_bytes = 4;
 460         for (i = 0; i < src_bytes; i++)
 461                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 462         return v;
 463 }
 464
 465 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 466 {
 467         int i;
 468         if (dst_bytes > 4)
 469                 dst_bytes = 4;
 470         for (i = 0; i < dst_bytes; i++)
 471                 dst[i] = src >> ((3-i) * 8);
 472 }
 473
 474 static void
 475 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 476 static void
 477 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 478                                               bool force_disable_vdd);
 479 static void
 480 intel_dp_pps_init(struct intel_dp *intel_dp);
 481
 482 static void pps_lock(struct intel_dp *intel_dp)
 483 {
 484         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 485
 486         /*
 487          * See intel_power_sequencer_reset() why we need
 488          * a power domain reference here.
 489          */
 490         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 491
 492         mutex_lock(&dev_priv->pps_mutex);
 493 }
 494
 495 static void pps_unlock(struct intel_dp *intel_dp)
 496 {
 497         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 498
 499         mutex_unlock(&dev_priv->pps_mutex);
 500
 501         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 502 }
 503
 504 static void
 505 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 506 {
 507         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 508         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 509         enum pipe pipe = intel_dp->pps_pipe;
 510         bool pll_enabled, release_cl_override = false;
 511         enum dpio_phy phy = DPIO_PHY(pipe);
 512         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 513         uint32_t DP;
 514
 515         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 516                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 517                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 518                 return;
 519
 520         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 521                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 522
 523         /* Preserve the BIOS-computed detected bit. This is
 524          * supposed to be read-only.
 525          */
 526         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 527         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 528         DP |= DP_PORT_WIDTH(1);
 529         DP |= DP_LINK_TRAIN_PAT_1;
 530
 531         if (IS_CHERRYVIEW(dev_priv))
 532                 DP |= DP_PIPE_SELECT_CHV(pipe);
 533         else if (pipe == PIPE_B)
 534                 DP |= DP_PIPEB_SELECT;
 535
 536         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 537
 538         /*
 539          * The DPLL for the pipe must be enabled for this to work.
 540          * So enable temporarily it if it's not already enabled.
 541          */
 542         if (!pll_enabled) {
 543                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 544                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 545
 546                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 547                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 548                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 549                                   pipe_name(pipe));
 550                         return;
 551                 }
 552         }
 553
 554         /*
 555          * Similar magic as in intel_dp_enable_port().
 556          * We _must_ do this port enable + disable trick
 557          * to make this power seqeuencer lock onto the port.
 558          * Otherwise even VDD force bit won't work.
 559          */
 560         I915_WRITE(intel_dp->output_reg, DP);
 561         POSTING_READ(intel_dp->output_reg);
 562
 563         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 564         POSTING_READ(intel_dp->output_reg);
 565
 566         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 567         POSTING_READ(intel_dp->output_reg);
 568
 569         if (!pll_enabled) {
 570                 vlv_force_pll_off(dev_priv, pipe);
 571
 572                 if (release_cl_override)
 573                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 574         }
 575 }
 576
 577 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 578 {
 579         struct intel_encoder *encoder;
 580         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 581
 582         /*
 583          * We don't have power sequencer currently.
 584          * Pick one that's not used by other ports.
 585          */
 586         for_each_intel_encoder(&dev_priv->drm, encoder) {
 587                 struct intel_dp *intel_dp;
 588
 589                 if (encoder->type != INTEL_OUTPUT_DP &&
 590                     encoder->type != INTEL_OUTPUT_EDP)
 591                         continue;
 592
 593                 intel_dp = enc_to_intel_dp(&encoder->base);
 594
 595                 if (encoder->type == INTEL_OUTPUT_EDP) {
 596                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 597                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 598
 599                         if (intel_dp->pps_pipe != INVALID_PIPE)
 600                                 pipes &= ~(1 << intel_dp->pps_pipe);
 601                 } else {
 602                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 603
 604                         if (intel_dp->active_pipe != INVALID_PIPE)
 605                                 pipes &= ~(1 << intel_dp->active_pipe);
 606                 }
 607         }
 608
 609         if (pipes == 0)
 610                 return INVALID_PIPE;
 611
 612         return ffs(pipes) - 1;
 613 }
 614
 615 static enum pipe
 616 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 617 {
 618         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 619         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 620         enum pipe pipe;
 621
 622         lockdep_assert_held(&dev_priv->pps_mutex);
 623
 624         /* We should never land here with regular DP ports */
 625         WARN_ON(!intel_dp_is_edp(intel_dp));
 626
 627         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 628                 intel_dp->active_pipe != intel_dp->pps_pipe);
 629
 630         if (intel_dp->pps_pipe != INVALID_PIPE)
 631                 return intel_dp->pps_pipe;
 632
 633         pipe = vlv_find_free_pps(dev_priv);
 634
 635         /*
 636          * Didn't find one. This should not happen since there
 637          * are two power sequencers and up to two eDP ports.
 638          */
 639         if (WARN_ON(pipe == INVALID_PIPE))
 640                 pipe = PIPE_A;
 641
 642         vlv_steal_power_sequencer(dev_priv, pipe);
 643         intel_dp->pps_pipe = pipe;
 644
 645         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 646                       pipe_name(intel_dp->pps_pipe),
 647                       port_name(intel_dig_port->base.port));
 648
 649         /* init power sequencer on this pipe and port */
 650         intel_dp_init_panel_power_sequencer(intel_dp);
 651         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 652
 653         /*
 654          * Even vdd force doesn't work until we've made
 655          * the power sequencer lock in on the port.
 656          */
 657         vlv_power_sequencer_kick(intel_dp);
 658
 659         return intel_dp->pps_pipe;
 660 }
 661
 662 static int
 663 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 664 {
 665         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 666         int backlight_controller = dev_priv->vbt.backlight.controller;
 667
 668         lockdep_assert_held(&dev_priv->pps_mutex);
 669
 670         /* We should never land here with regular DP ports */
 671         WARN_ON(!intel_dp_is_edp(intel_dp));
 672
 673         if (!intel_dp->pps_reset)
 674                 return backlight_controller;
 675
 676         intel_dp->pps_reset = false;
 677
 678         /*
 679          * Only the HW needs to be reprogrammed, the SW state is fixed and
 680          * has been setup during connector init.
 681          */
 682         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 683
 684         return backlight_controller;
 685 }
 686
 687 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 688                                enum pipe pipe);
 689
 690 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 691                                enum pipe pipe)
 692 {
 693         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 694 }
 695
 696 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 697                                 enum pipe pipe)
 698 {
 699         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 700 }
 701
 702 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 703                          enum pipe pipe)
 704 {
 705         return true;
 706 }
 707
 708 static enum pipe
 709 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 710                      enum port port,
 711                      vlv_pipe_check pipe_check)
 712 {
 713         enum pipe pipe;
 714
 715         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 716                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 717                         PANEL_PORT_SELECT_MASK;
 718
 719                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 720                         continue;
 721
 722                 if (!pipe_check(dev_priv, pipe))
 723                         continue;
 724
 725                 return pipe;
 726         }
 727
 728         return INVALID_PIPE;
 729 }
 730
 731 static void
 732 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 733 {
 734         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 735         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 736         enum port port = intel_dig_port->base.port;
 737
 738         lockdep_assert_held(&dev_priv->pps_mutex);
 739
 740         /* try to find a pipe with this port selected */
 741         /* first pick one where the panel is on */
 742         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 743                                                   vlv_pipe_has_pp_on);
 744         /* didn't find one? pick one where vdd is on */
 745         if (intel_dp->pps_pipe == INVALID_PIPE)
 746                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 747                                                           vlv_pipe_has_vdd_on);
 748         /* didn't find one? pick one with just the correct port */
 749         if (intel_dp->pps_pipe == INVALID_PIPE)
 750                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 751                                                           vlv_pipe_any);
 752
 753         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 754         if (intel_dp->pps_pipe == INVALID_PIPE) {
 755                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 756                               port_name(port));
 757                 return;
 758         }
 759
 760         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 761                       port_name(port), pipe_name(intel_dp->pps_pipe));
 762
 763         intel_dp_init_panel_power_sequencer(intel_dp);
 764         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 765 }
 766
 767 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 768 {
 769         struct intel_encoder *encoder;
 770
 771         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 772                     !IS_GEN9_LP(dev_priv)))
 773                 return;
 774
 775         /*
 776          * We can't grab pps_mutex here due to deadlock with power_domain
 777          * mutex when power_domain functions are called while holding pps_mutex.
 778          * That also means that in order to use pps_pipe the code needs to
 779          * hold both a power domain reference and pps_mutex, and the power domain
 780          * reference get/put must be done while _not_ holding pps_mutex.
 781          * pps_{lock,unlock}() do these steps in the correct order, so one
 782          * should use them always.
 783          */
 784
 785         for_each_intel_encoder(&dev_priv->drm, encoder) {
 786                 struct intel_dp *intel_dp;
 787
 788                 if (encoder->type != INTEL_OUTPUT_DP &&
 789                     encoder->type != INTEL_OUTPUT_EDP &&
 790                     encoder->type != INTEL_OUTPUT_DDI)
 791                         continue;
 792
 793                 intel_dp = enc_to_intel_dp(&encoder->base);
 794
 795                 /* Skip pure DVI/HDMI DDI encoders */
 796                 if (!i915_mmio_reg_valid(intel_dp->output_reg))
 797                         continue;
 798
 799                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 800
 801                 if (encoder->type != INTEL_OUTPUT_EDP)
 802                         continue;
 803
 804                 if (IS_GEN9_LP(dev_priv))
 805                         intel_dp->pps_reset = true;
 806                 else
 807                         intel_dp->pps_pipe = INVALID_PIPE;
 808         }
 809 }
 810
 811 struct pps_registers {
 812         i915_reg_t pp_ctrl;
 813         i915_reg_t pp_stat;
 814         i915_reg_t pp_on;
 815         i915_reg_t pp_off;
 816         i915_reg_t pp_div;
 817 };
 818
 819 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 820                                     struct pps_registers *regs)
 821 {
 822         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 823         int pps_idx = 0;
 824
 825         memset(regs, 0, sizeof(*regs));
 826
 827         if (IS_GEN9_LP(dev_priv))
 828                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 829         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 830                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 831
 832         regs->pp_ctrl = PP_CONTROL(pps_idx);
 833         regs->pp_stat = PP_STATUS(pps_idx);
 834         regs->pp_on = PP_ON_DELAYS(pps_idx);
 835         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 836         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 837             !HAS_PCH_ICP(dev_priv))
 838                 regs->pp_div = PP_DIVISOR(pps_idx);
 839 }
 840
 841 static i915_reg_t
 842 _pp_ctrl_reg(struct intel_dp *intel_dp)
 843 {
 844         struct pps_registers regs;
 845
 846         intel_pps_get_registers(intel_dp, &regs);
 847
 848         return regs.pp_ctrl;
 849 }
 850
 851 static i915_reg_t
 852 _pp_stat_reg(struct intel_dp *intel_dp)
 853 {
 854         struct pps_registers regs;
 855
 856         intel_pps_get_registers(intel_dp, &regs);
 857
 858         return regs.pp_stat;
 859 }
 860
 861 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 862    This function only applicable when panel PM state is not to be tracked */
 863 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 864                               void *unused)
 865 {
 866         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 867                                                  edp_notifier);
 868         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 869
 870         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 871                 return 0;
 872
 873         pps_lock(intel_dp);
 874
 875         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 876                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 877                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 878                 u32 pp_div;
 879
 880                 pp_ctrl_reg = PP_CONTROL(pipe);
 881                 pp_div_reg  = PP_DIVISOR(pipe);
 882                 pp_div = I915_READ(pp_div_reg);
 883                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 884
 885                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 886                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 887                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 888                 msleep(intel_dp->panel_power_cycle_delay);
 889         }
 890
 891         pps_unlock(intel_dp);
 892
 893         return 0;
 894 }
 895
 896 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 897 {
 898         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 899
 900         lockdep_assert_held(&dev_priv->pps_mutex);
 901
 902         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 903             intel_dp->pps_pipe == INVALID_PIPE)
 904                 return false;
 905
 906         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 907 }
 908
 909 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 910 {
 911         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 912
 913         lockdep_assert_held(&dev_priv->pps_mutex);
 914
 915         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 916             intel_dp->pps_pipe == INVALID_PIPE)
 917                 return false;
 918
 919         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 920 }
 921
 922 static void
 923 intel_dp_check_edp(struct intel_dp *intel_dp)
 924 {
 925         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 926
 927         if (!intel_dp_is_edp(intel_dp))
 928                 return;
 929
 930         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 931                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 932                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 933                               I915_READ(_pp_stat_reg(intel_dp)),
 934                               I915_READ(_pp_ctrl_reg(intel_dp)));
 935         }
 936 }
 937
 938 static uint32_t
 939 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 940 {
 941         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 942         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
 943         uint32_t status;
 944         bool done;
 945
 946 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 947         if (has_aux_irq)
 948                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 949                                           msecs_to_jiffies_timeout(10));
 950         else
 951                 done = wait_for(C, 10) == 0;
 952         if (!done)
 953                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 954                           has_aux_irq);
 955 #undef C
 956
 957         return status;
 958 }
 959
 960 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 961 {
 962         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 963
 964         if (index)
 965                 return 0;
 966
 967         /*
 968          * The clock divider is based off the hrawclk, and would like to run at
 969          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 970          */
 971         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 972 }
 973
 974 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 975 {
 976         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 977
 978         if (index)
 979                 return 0;
 980
 981         /*
 982          * The clock divider is based off the cdclk or PCH rawclk, and would
 983          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 984          * divide by 2000 and use that
 985          */
 986         if (intel_dp->aux_ch == AUX_CH_A)
 987                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 988         else
 989                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 990 }
 991
 992 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 993 {
 994         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 995
 996         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
 997                 /* Workaround for non-ULT HSW */
 998                 switch (index) {
 999                 case 0: return 63;
1000                 case 1: return 72;
1001                 default: return 0;
1002                 }
1003         }
1004
1005         return ilk_get_aux_clock_divider(intel_dp, index);
1006 }
1007
1008 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1009 {
1010         /*
1011          * SKL doesn't need us to program the AUX clock divider (Hardware will
1012          * derive the clock from CDCLK automatically). We still implement the
1013          * get_aux_clock_divider vfunc to plug-in into the existing code.
1014          */
1015         return index ? 0 : 1;
1016 }
1017
1018 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1019                                      bool has_aux_irq,
1020                                      int send_bytes,
1021                                      uint32_t aux_clock_divider)
1022 {
1023         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1024         struct drm_i915_private *dev_priv =
1025                         to_i915(intel_dig_port->base.base.dev);
1026         uint32_t precharge, timeout;
1027
1028         if (IS_GEN6(dev_priv))
1029                 precharge = 3;
1030         else
1031                 precharge = 5;
1032
1033         if (IS_BROADWELL(dev_priv))
1034                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1035         else
1036                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1037
1038         return DP_AUX_CH_CTL_SEND_BUSY |
1039                DP_AUX_CH_CTL_DONE |
1040                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1041                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1042                timeout |
1043                DP_AUX_CH_CTL_RECEIVE_ERROR |
1044                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1045                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1046                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1047 }
1048
1049 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1050                                       bool has_aux_irq,
1051                                       int send_bytes,
1052                                       uint32_t unused)
1053 {
1054         return DP_AUX_CH_CTL_SEND_BUSY |
1055                DP_AUX_CH_CTL_DONE |
1056                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1057                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1058                DP_AUX_CH_CTL_TIME_OUT_MAX |
1059                DP_AUX_CH_CTL_RECEIVE_ERROR |
1060                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1061                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1062                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1063 }
1064
1065 static int
1066 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1067                   const uint8_t *send, int send_bytes,
1068                   uint8_t *recv, int recv_size,
1069                   u32 aux_send_ctl_flags)
1070 {
1071         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1072         struct drm_i915_private *dev_priv =
1073                         to_i915(intel_dig_port->base.base.dev);
1074         i915_reg_t ch_ctl, ch_data[5];
1075         uint32_t aux_clock_divider;
1076         int i, ret, recv_bytes;
1077         uint32_t status;
1078         int try, clock = 0;
1079         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1080         bool vdd;
1081
1082         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1083         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1084                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1085
1086         pps_lock(intel_dp);
1087
1088         /*
1089          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1090          * In such cases we want to leave VDD enabled and it's up to upper layers
1091          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1092          * ourselves.
1093          */
1094         vdd = edp_panel_vdd_on(intel_dp);
1095
1096         /* dp aux is extremely sensitive to irq latency, hence request the
1097          * lowest possible wakeup latency and so prevent the cpu from going into
1098          * deep sleep states.
1099          */
1100         pm_qos_update_request(&dev_priv->pm_qos, 0);
1101
1102         intel_dp_check_edp(intel_dp);
1103
1104         /* Try to wait for any previous AUX channel activity */
1105         for (try = 0; try < 3; try++) {
1106                 status = I915_READ_NOTRACE(ch_ctl);
1107                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1108                         break;
1109                 msleep(1);
1110         }
1111
1112         if (try == 3) {
1113                 static u32 last_status = -1;
1114                 const u32 status = I915_READ(ch_ctl);
1115
1116                 if (status != last_status) {
1117                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1118                              status);
1119                         last_status = status;
1120                 }
1121
1122                 ret = -EBUSY;
1123                 goto out;
1124         }
1125
1126         /* Only 5 data registers! */
1127         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1128                 ret = -E2BIG;
1129                 goto out;
1130         }
1131
1132         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1133                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1134                                                           has_aux_irq,
1135                                                           send_bytes,
1136                                                           aux_clock_divider);
1137
1138                 send_ctl |= aux_send_ctl_flags;
1139
1140                 /* Must try at least 3 times according to DP spec */
1141                 for (try = 0; try < 5; try++) {
1142                         /* Load the send data into the aux channel data registers */
1143                         for (i = 0; i < send_bytes; i += 4)
1144                                 I915_WRITE(ch_data[i >> 2],
1145                                            intel_dp_pack_aux(send + i,
1146                                                              send_bytes - i));
1147
1148                         /* Send the command and wait for it to complete */
1149                         I915_WRITE(ch_ctl, send_ctl);
1150
1151                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1152
1153                         /* Clear done status and any errors */
1154                         I915_WRITE(ch_ctl,
1155                                    status |
1156                                    DP_AUX_CH_CTL_DONE |
1157                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1158                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1159
1160                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1161                          *   400us delay required for errors and timeouts
1162                          *   Timeout errors from the HW already meet this
1163                          *   requirement so skip to next iteration
1164                          */
1165                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1166                                 continue;
1167
1168                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1169                                 usleep_range(400, 500);
1170                                 continue;
1171                         }
1172                         if (status & DP_AUX_CH_CTL_DONE)
1173                                 goto done;
1174                 }
1175         }
1176
1177         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1178                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1179                 ret = -EBUSY;
1180                 goto out;
1181         }
1182
1183 done:
1184         /* Check for timeout or receive error.
1185          * Timeouts occur when the sink is not connected
1186          */
1187         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1188                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1189                 ret = -EIO;
1190                 goto out;
1191         }
1192
1193         /* Timeouts occur when the device isn't connected, so they're
1194          * "normal" -- don't fill the kernel log with these */
1195         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1196                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1197                 ret = -ETIMEDOUT;
1198                 goto out;
1199         }
1200
1201         /* Unload any bytes sent back from the other side */
1202         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1203                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1204
1205         /*
1206          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1207          * We have no idea of what happened so we return -EBUSY so
1208          * drm layer takes care for the necessary retries.
1209          */
1210         if (recv_bytes == 0 || recv_bytes > 20) {
1211                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1212                               recv_bytes);
1213                 ret = -EBUSY;
1214                 goto out;
1215         }
1216
1217         if (recv_bytes > recv_size)
1218                 recv_bytes = recv_size;
1219
1220         for (i = 0; i < recv_bytes; i += 4)
1221                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1222                                     recv + i, recv_bytes - i);
1223
1224         ret = recv_bytes;
1225 out:
1226         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1227
1228         if (vdd)
1229                 edp_panel_vdd_off(intel_dp, false);
1230
1231         pps_unlock(intel_dp);
1232
1233         return ret;
1234 }
1235
1236 #define BARE_ADDRESS_SIZE       3
1237 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1238
1239 static void
1240 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1241                     const struct drm_dp_aux_msg *msg)
1242 {
1243         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1244         txbuf[1] = (msg->address >> 8) & 0xff;
1245         txbuf[2] = msg->address & 0xff;
1246         txbuf[3] = msg->size - 1;
1247 }
1248
1249 static ssize_t
1250 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1251 {
1252         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1253         uint8_t txbuf[20], rxbuf[20];
1254         size_t txsize, rxsize;
1255         int ret;
1256
1257         intel_dp_aux_header(txbuf, msg);
1258
1259         switch (msg->request & ~DP_AUX_I2C_MOT) {
1260         case DP_AUX_NATIVE_WRITE:
1261         case DP_AUX_I2C_WRITE:
1262         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1263                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1264                 rxsize = 2; /* 0 or 1 data bytes */
1265
1266                 if (WARN_ON(txsize > 20))
1267                         return -E2BIG;
1268
1269                 WARN_ON(!msg->buffer != !msg->size);
1270
1271                 if (msg->buffer)
1272                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1273
1274                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1275                                         rxbuf, rxsize, 0);
1276                 if (ret > 0) {
1277                         msg->reply = rxbuf[0] >> 4;
1278
1279                         if (ret > 1) {
1280                                 /* Number of bytes written in a short write. */
1281                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1282                         } else {
1283                                 /* Return payload size. */
1284                                 ret = msg->size;
1285                         }
1286                 }
1287                 break;
1288
1289         case DP_AUX_NATIVE_READ:
1290         case DP_AUX_I2C_READ:
1291                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1292                 rxsize = msg->size + 1;
1293
1294                 if (WARN_ON(rxsize > 20))
1295                         return -E2BIG;
1296
1297                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1298                                         rxbuf, rxsize, 0);
1299                 if (ret > 0) {
1300                         msg->reply = rxbuf[0] >> 4;
1301                         /*
1302                          * Assume happy day, and copy the data. The caller is
1303                          * expected to check msg->reply before touching it.
1304                          *
1305                          * Return payload size.
1306                          */
1307                         ret--;
1308                         memcpy(msg->buffer, rxbuf + 1, ret);
1309                 }
1310                 break;
1311
1312         default:
1313                 ret = -EINVAL;
1314                 break;
1315         }
1316
1317         return ret;
1318 }
1319
1320 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1321 {
1322         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1323         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1324         enum port port = encoder->port;
1325         const struct ddi_vbt_port_info *info =
1326                 &dev_priv->vbt.ddi_port_info[port];
1327         enum aux_ch aux_ch;
1328
1329         if (!info->alternate_aux_channel) {
1330                 aux_ch = (enum aux_ch) port;
1331
1332                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1333                               aux_ch_name(aux_ch), port_name(port));
1334                 return aux_ch;
1335         }
1336
1337         switch (info->alternate_aux_channel) {
1338         case DP_AUX_A:
1339                 aux_ch = AUX_CH_A;
1340                 break;
1341         case DP_AUX_B:
1342                 aux_ch = AUX_CH_B;
1343                 break;
1344         case DP_AUX_C:
1345                 aux_ch = AUX_CH_C;
1346                 break;
1347         case DP_AUX_D:
1348                 aux_ch = AUX_CH_D;
1349                 break;
1350         case DP_AUX_F:
1351                 aux_ch = AUX_CH_F;
1352                 break;
1353         default:
1354                 MISSING_CASE(info->alternate_aux_channel);
1355                 aux_ch = AUX_CH_A;
1356                 break;
1357         }
1358
1359         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1360                       aux_ch_name(aux_ch), port_name(port));
1361
1362         return aux_ch;
1363 }
1364
1365 static enum intel_display_power_domain
1366 intel_aux_power_domain(struct intel_dp *intel_dp)
1367 {
1368         switch (intel_dp->aux_ch) {
1369         case AUX_CH_A:
1370                 return POWER_DOMAIN_AUX_A;
1371         case AUX_CH_B:
1372                 return POWER_DOMAIN_AUX_B;
1373         case AUX_CH_C:
1374                 return POWER_DOMAIN_AUX_C;
1375         case AUX_CH_D:
1376                 return POWER_DOMAIN_AUX_D;
1377         case AUX_CH_F:
1378                 return POWER_DOMAIN_AUX_F;
1379         default:
1380                 MISSING_CASE(intel_dp->aux_ch);
1381                 return POWER_DOMAIN_AUX_A;
1382         }
1383 }
1384
1385 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1386 {
1387         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1388         enum aux_ch aux_ch = intel_dp->aux_ch;
1389
1390         switch (aux_ch) {
1391         case AUX_CH_B:
1392         case AUX_CH_C:
1393         case AUX_CH_D:
1394                 return DP_AUX_CH_CTL(aux_ch);
1395         default:
1396                 MISSING_CASE(aux_ch);
1397                 return DP_AUX_CH_CTL(AUX_CH_B);
1398         }
1399 }
1400
1401 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1402 {
1403         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1404         enum aux_ch aux_ch = intel_dp->aux_ch;
1405
1406         switch (aux_ch) {
1407         case AUX_CH_B:
1408         case AUX_CH_C:
1409         case AUX_CH_D:
1410                 return DP_AUX_CH_DATA(aux_ch, index);
1411         default:
1412                 MISSING_CASE(aux_ch);
1413                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1414         }
1415 }
1416
1417 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1418 {
1419         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1420         enum aux_ch aux_ch = intel_dp->aux_ch;
1421
1422         switch (aux_ch) {
1423         case AUX_CH_A:
1424                 return DP_AUX_CH_CTL(aux_ch);
1425         case AUX_CH_B:
1426         case AUX_CH_C:
1427         case AUX_CH_D:
1428                 return PCH_DP_AUX_CH_CTL(aux_ch);
1429         default:
1430                 MISSING_CASE(aux_ch);
1431                 return DP_AUX_CH_CTL(AUX_CH_A);
1432         }
1433 }
1434
1435 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1436 {
1437         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1438         enum aux_ch aux_ch = intel_dp->aux_ch;
1439
1440         switch (aux_ch) {
1441         case AUX_CH_A:
1442                 return DP_AUX_CH_DATA(aux_ch, index);
1443         case AUX_CH_B:
1444         case AUX_CH_C:
1445         case AUX_CH_D:
1446                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1447         default:
1448                 MISSING_CASE(aux_ch);
1449                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1450         }
1451 }
1452
1453 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1456         enum aux_ch aux_ch = intel_dp->aux_ch;
1457
1458         switch (aux_ch) {
1459         case AUX_CH_A:
1460         case AUX_CH_B:
1461         case AUX_CH_C:
1462         case AUX_CH_D:
1463         case AUX_CH_F:
1464                 return DP_AUX_CH_CTL(aux_ch);
1465         default:
1466                 MISSING_CASE(aux_ch);
1467                 return DP_AUX_CH_CTL(AUX_CH_A);
1468         }
1469 }
1470
1471 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1474         enum aux_ch aux_ch = intel_dp->aux_ch;
1475
1476         switch (aux_ch) {
1477         case AUX_CH_A:
1478         case AUX_CH_B:
1479         case AUX_CH_C:
1480         case AUX_CH_D:
1481         case AUX_CH_F:
1482                 return DP_AUX_CH_DATA(aux_ch, index);
1483         default:
1484                 MISSING_CASE(aux_ch);
1485                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1486         }
1487 }
1488
1489 static void
1490 intel_dp_aux_fini(struct intel_dp *intel_dp)
1491 {
1492         kfree(intel_dp->aux.name);
1493 }
1494
1495 static void
1496 intel_dp_aux_init(struct intel_dp *intel_dp)
1497 {
1498         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1499         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1500
1501         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1502         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1503
1504         if (INTEL_GEN(dev_priv) >= 9) {
1505                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1506                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1507         } else if (HAS_PCH_SPLIT(dev_priv)) {
1508                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1509                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1510         } else {
1511                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1512                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1513         }
1514
1515         if (INTEL_GEN(dev_priv) >= 9)
1516                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1517         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1518                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1519         else if (HAS_PCH_SPLIT(dev_priv))
1520                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1521         else
1522                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1523
1524         if (INTEL_GEN(dev_priv) >= 9)
1525                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1526         else
1527                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1528
1529         drm_dp_aux_init(&intel_dp->aux);
1530
1531         /* Failure to allocate our preferred name is not critical */
1532         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1533                                        port_name(encoder->port));
1534         intel_dp->aux.transfer = intel_dp_aux_transfer;
1535 }
1536
1537 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1538 {
1539         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1540
1541         return max_rate >= 540000;
1542 }
1543
1544 static void
1545 intel_dp_set_clock(struct intel_encoder *encoder,
1546                    struct intel_crtc_state *pipe_config)
1547 {
1548         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1549         const struct dp_link_dpll *divisor = NULL;
1550         int i, count = 0;
1551
1552         if (IS_G4X(dev_priv)) {
1553                 divisor = gen4_dpll;
1554                 count = ARRAY_SIZE(gen4_dpll);
1555         } else if (HAS_PCH_SPLIT(dev_priv)) {
1556                 divisor = pch_dpll;
1557                 count = ARRAY_SIZE(pch_dpll);
1558         } else if (IS_CHERRYVIEW(dev_priv)) {
1559                 divisor = chv_dpll;
1560                 count = ARRAY_SIZE(chv_dpll);
1561         } else if (IS_VALLEYVIEW(dev_priv)) {
1562                 divisor = vlv_dpll;
1563                 count = ARRAY_SIZE(vlv_dpll);
1564         }
1565
1566         if (divisor && count) {
1567                 for (i = 0; i < count; i++) {
1568                         if (pipe_config->port_clock == divisor[i].clock) {
1569                                 pipe_config->dpll = divisor[i].dpll;
1570                                 pipe_config->clock_set = true;
1571                                 break;
1572                         }
1573                 }
1574         }
1575 }
1576
1577 static void snprintf_int_array(char *str, size_t len,
1578                                const int *array, int nelem)
1579 {
1580         int i;
1581
1582         str[0] = '\0';
1583
1584         for (i = 0; i < nelem; i++) {
1585                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1586                 if (r >= len)
1587                         return;
1588                 str += r;
1589                 len -= r;
1590         }
1591 }
1592
1593 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1594 {
1595         char str[128]; /* FIXME: too big for stack? */
1596
1597         if ((drm_debug & DRM_UT_KMS) == 0)
1598                 return;
1599
1600         snprintf_int_array(str, sizeof(str),
1601                            intel_dp->source_rates, intel_dp->num_source_rates);
1602         DRM_DEBUG_KMS("source rates: %s\n", str);
1603
1604         snprintf_int_array(str, sizeof(str),
1605                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1606         DRM_DEBUG_KMS("sink rates: %s\n", str);
1607
1608         snprintf_int_array(str, sizeof(str),
1609                            intel_dp->common_rates, intel_dp->num_common_rates);
1610         DRM_DEBUG_KMS("common rates: %s\n", str);
1611 }
1612
1613 int
1614 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1615 {
1616         int len;
1617
1618         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1619         if (WARN_ON(len <= 0))
1620                 return 162000;
1621
1622         return intel_dp->common_rates[len - 1];
1623 }
1624
1625 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1626 {
1627         int i = intel_dp_rate_index(intel_dp->sink_rates,
1628                                     intel_dp->num_sink_rates, rate);
1629
1630         if (WARN_ON(i < 0))
1631                 i = 0;
1632
1633         return i;
1634 }
1635
1636 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1637                            uint8_t *link_bw, uint8_t *rate_select)
1638 {
1639         /* eDP 1.4 rate select method. */
1640         if (intel_dp->use_rate_select) {
1641                 *link_bw = 0;
1642                 *rate_select =
1643                         intel_dp_rate_select(intel_dp, port_clock);
1644         } else {
1645                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1646                 *rate_select = 0;
1647         }
1648 }
1649
1650 struct link_config_limits {
1651         int min_clock, max_clock;
1652         int min_lane_count, max_lane_count;
1653         int min_bpp, max_bpp;
1654 };
1655
1656 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1657                                 struct intel_crtc_state *pipe_config)
1658 {
1659         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1660         struct intel_connector *intel_connector = intel_dp->attached_connector;
1661         int bpp, bpc;
1662
1663         bpp = pipe_config->pipe_bpp;
1664         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1665
1666         if (bpc > 0)
1667                 bpp = min(bpp, 3*bpc);
1668
1669         if (intel_dp_is_edp(intel_dp)) {
1670                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1671                 if (intel_connector->base.display_info.bpc == 0 &&
1672                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1673                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1674                                       dev_priv->vbt.edp.bpp);
1675                         bpp = dev_priv->vbt.edp.bpp;
1676                 }
1677         }
1678
1679         return bpp;
1680 }
1681
1682 /* Adjust link config limits based on compliance test requests. */
1683 static void
1684 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1685                                   struct intel_crtc_state *pipe_config,
1686                                   struct link_config_limits *limits)
1687 {
1688         /* For DP Compliance we override the computed bpp for the pipe */
1689         if (intel_dp->compliance.test_data.bpc != 0) {
1690                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1691
1692                 limits->min_bpp = limits->max_bpp = bpp;
1693                 pipe_config->dither_force_disable = bpp == 6 * 3;
1694
1695                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1696         }
1697
1698         /* Use values requested by Compliance Test Request */
1699         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1700                 int index;
1701
1702                 /* Validate the compliance test data since max values
1703                  * might have changed due to link train fallback.
1704                  */
1705                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1706                                                intel_dp->compliance.test_lane_count)) {
1707                         index = intel_dp_rate_index(intel_dp->common_rates,
1708                                                     intel_dp->num_common_rates,
1709                                                     intel_dp->compliance.test_link_rate);
1710                         if (index >= 0)
1711                                 limits->min_clock = limits->max_clock = index;
1712                         limits->min_lane_count = limits->max_lane_count =
1713                                 intel_dp->compliance.test_lane_count;
1714                 }
1715         }
1716 }
1717
1718 /* Optimize link config in order: max bpp, min clock, min lanes */
1719 static bool
1720 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1721                                   struct intel_crtc_state *pipe_config,
1722                                   const struct link_config_limits *limits)
1723 {
1724         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1725         int bpp, clock, lane_count;
1726         int mode_rate, link_clock, link_avail;
1727
1728         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1729                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1730                                                    bpp);
1731
1732                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1733                         for (lane_count = limits->min_lane_count;
1734                              lane_count <= limits->max_lane_count;
1735                              lane_count <<= 1) {
1736                                 link_clock = intel_dp->common_rates[clock];
1737                                 link_avail = intel_dp_max_data_rate(link_clock,
1738                                                                     lane_count);
1739
1740                                 if (mode_rate <= link_avail) {
1741                                         pipe_config->lane_count = lane_count;
1742                                         pipe_config->pipe_bpp = bpp;
1743                                         pipe_config->port_clock = link_clock;
1744
1745                                         return true;
1746                                 }
1747                         }
1748                 }
1749         }
1750
1751         return false;
1752 }
1753
1754 static bool
1755 intel_dp_compute_link_config(struct intel_encoder *encoder,
1756                              struct intel_crtc_state *pipe_config)
1757 {
1758         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1759         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1760         struct link_config_limits limits;
1761         int common_len;
1762
1763         common_len = intel_dp_common_len_rate_limit(intel_dp,
1764                                                     intel_dp->max_link_rate);
1765
1766         /* No common link rates between source and sink */
1767         WARN_ON(common_len <= 0);
1768
1769         limits.min_clock = 0;
1770         limits.max_clock = common_len - 1;
1771
1772         limits.min_lane_count = 1;
1773         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1774
1775         limits.min_bpp = 6 * 3;
1776         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1777
1778         if (intel_dp_is_edp(intel_dp)) {
1779                 /*
1780                  * Use the maximum clock and number of lanes the eDP panel
1781                  * advertizes being capable of. The panels are generally
1782                  * designed to support only a single clock and lane
1783                  * configuration, and typically these values correspond to the
1784                  * native resolution of the panel.
1785                  */
1786                 limits.min_lane_count = limits.max_lane_count;
1787                 limits.min_clock = limits.max_clock;
1788         }
1789
1790         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1791
1792         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1793                       "max rate %d max bpp %d pixel clock %iKHz\n",
1794                       limits.max_lane_count,
1795                       intel_dp->common_rates[limits.max_clock],
1796                       limits.max_bpp, adjusted_mode->crtc_clock);
1797
1798         /*
1799          * Optimize for slow and wide. This is the place to add alternative
1800          * optimization policy.
1801          */
1802         if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
1803                 return false;
1804
1805         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1806                       pipe_config->lane_count, pipe_config->port_clock,
1807                       pipe_config->pipe_bpp);
1808
1809         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1810                       intel_dp_link_required(adjusted_mode->crtc_clock,
1811                                              pipe_config->pipe_bpp),
1812                       intel_dp_max_data_rate(pipe_config->port_clock,
1813                                              pipe_config->lane_count));
1814
1815         return true;
1816 }
1817
1818 bool
1819 intel_dp_compute_config(struct intel_encoder *encoder,
1820                         struct intel_crtc_state *pipe_config,
1821                         struct drm_connector_state *conn_state)
1822 {
1823         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1824         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1825         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1826         enum port port = encoder->port;
1827         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1828         struct intel_connector *intel_connector = intel_dp->attached_connector;
1829         struct intel_digital_connector_state *intel_conn_state =
1830                 to_intel_digital_connector_state(conn_state);
1831         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1832                                            DP_DPCD_QUIRK_LIMITED_M_N);
1833
1834         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1835                 pipe_config->has_pch_encoder = true;
1836
1837         pipe_config->has_drrs = false;
1838         if (IS_G4X(dev_priv) || port == PORT_A)
1839                 pipe_config->has_audio = false;
1840         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1841                 pipe_config->has_audio = intel_dp->has_audio;
1842         else
1843                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1844
1845         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1846                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1847                                        adjusted_mode);
1848
1849                 if (INTEL_GEN(dev_priv) >= 9) {
1850                         int ret;
1851
1852                         ret = skl_update_scaler_crtc(pipe_config);
1853                         if (ret)
1854                                 return ret;
1855                 }
1856
1857                 if (HAS_GMCH_DISPLAY(dev_priv))
1858                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1859                                                  conn_state->scaling_mode);
1860                 else
1861                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1862                                                 conn_state->scaling_mode);
1863         }
1864
1865         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1866             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1867                 return false;
1868
1869         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1870                 return false;
1871
1872         if (!intel_dp_compute_link_config(encoder, pipe_config))
1873                 return false;
1874
1875         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1876                 /*
1877                  * See:
1878                  * CEA-861-E - 5.1 Default Encoding Parameters
1879                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1880                  */
1881                 pipe_config->limited_color_range =
1882                         pipe_config->pipe_bpp != 18 &&
1883                         drm_default_rgb_quant_range(adjusted_mode) ==
1884                         HDMI_QUANTIZATION_RANGE_LIMITED;
1885         } else {
1886                 pipe_config->limited_color_range =
1887                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1888         }
1889
1890         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
1891                                adjusted_mode->crtc_clock,
1892                                pipe_config->port_clock,
1893                                &pipe_config->dp_m_n,
1894                                reduce_m_n);
1895
1896         if (intel_connector->panel.downclock_mode != NULL &&
1897                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1898                         pipe_config->has_drrs = true;
1899                         intel_link_compute_m_n(pipe_config->pipe_bpp,
1900                                                pipe_config->lane_count,
1901                                                intel_connector->panel.downclock_mode->clock,
1902                                                pipe_config->port_clock,
1903                                                &pipe_config->dp_m2_n2,
1904                                                reduce_m_n);
1905         }
1906
1907         if (!HAS_DDI(dev_priv))
1908                 intel_dp_set_clock(encoder, pipe_config);
1909
1910         intel_psr_compute_config(intel_dp, pipe_config);
1911
1912         return true;
1913 }
1914
1915 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1916                               int link_rate, uint8_t lane_count,
1917                               bool link_mst)
1918 {
1919         intel_dp->link_trained = false;
1920         intel_dp->link_rate = link_rate;
1921         intel_dp->lane_count = lane_count;
1922         intel_dp->link_mst = link_mst;
1923 }
1924
1925 static void intel_dp_prepare(struct intel_encoder *encoder,
1926                              const struct intel_crtc_state *pipe_config)
1927 {
1928         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1929         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1930         enum port port = encoder->port;
1931         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1932         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1933
1934         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1935                                  pipe_config->lane_count,
1936                                  intel_crtc_has_type(pipe_config,
1937                                                      INTEL_OUTPUT_DP_MST));
1938
1939         /*
1940          * There are four kinds of DP registers:
1941          *
1942          *      IBX PCH
1943          *      SNB CPU
1944          *      IVB CPU
1945          *      CPT PCH
1946          *
1947          * IBX PCH and CPU are the same for almost everything,
1948          * except that the CPU DP PLL is configured in this
1949          * register
1950          *
1951          * CPT PCH is quite different, having many bits moved
1952          * to the TRANS_DP_CTL register instead. That
1953          * configuration happens (oddly) in ironlake_pch_enable
1954          */
1955
1956         /* Preserve the BIOS-computed detected bit. This is
1957          * supposed to be read-only.
1958          */
1959         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1960
1961         /* Handle DP bits in common between all three register formats */
1962         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1963         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1964
1965         /* Split out the IBX/CPU vs CPT settings */
1966
1967         if (IS_GEN7(dev_priv) && port == PORT_A) {
1968                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1969                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1970                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1971                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1972                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1973
1974                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1975                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1976
1977                 intel_dp->DP |= crtc->pipe << 29;
1978         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1979                 u32 trans_dp;
1980
1981                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1982
1983                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1984                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1985                         trans_dp |= TRANS_DP_ENH_FRAMING;
1986                 else
1987                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1988                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1989         } else {
1990                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1991                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1992
1993                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1994                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1995                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1996                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1997                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1998
1999                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2000                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2001
2002                 if (IS_CHERRYVIEW(dev_priv))
2003                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
2004                 else if (crtc->pipe == PIPE_B)
2005                         intel_dp->DP |= DP_PIPEB_SELECT;
2006         }
2007 }
2008
2009 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2010 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2011
2012 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2013 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2014
2015 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2016 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2017
2018 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2019
2020 static void wait_panel_status(struct intel_dp *intel_dp,
2021                                        u32 mask,
2022                                        u32 value)
2023 {
2024         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2025         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2026
2027         lockdep_assert_held(&dev_priv->pps_mutex);
2028
2029         intel_pps_verify_state(intel_dp);
2030
2031         pp_stat_reg = _pp_stat_reg(intel_dp);
2032         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2033
2034         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2035                         mask, value,
2036                         I915_READ(pp_stat_reg),
2037                         I915_READ(pp_ctrl_reg));
2038
2039         if (intel_wait_for_register(dev_priv,
2040                                     pp_stat_reg, mask, value,
2041                                     5000))
2042                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2043                                 I915_READ(pp_stat_reg),
2044                                 I915_READ(pp_ctrl_reg));
2045
2046         DRM_DEBUG_KMS("Wait complete\n");
2047 }
2048
2049 static void wait_panel_on(struct intel_dp *intel_dp)
2050 {
2051         DRM_DEBUG_KMS("Wait for panel power on\n");
2052         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2053 }
2054
2055 static void wait_panel_off(struct intel_dp *intel_dp)
2056 {
2057         DRM_DEBUG_KMS("Wait for panel power off time\n");
2058         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2059 }
2060
2061 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2062 {
2063         ktime_t panel_power_on_time;
2064         s64 panel_power_off_duration;
2065
2066         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2067
2068         /* take the difference of currrent time and panel power off time
2069          * and then make panel wait for t11_t12 if needed. */
2070         panel_power_on_time = ktime_get_boottime();
2071         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2072
2073         /* When we disable the VDD override bit last we have to do the manual
2074          * wait. */
2075         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2076                 wait_remaining_ms_from_jiffies(jiffies,
2077                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2078
2079         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2080 }
2081
2082 static void wait_backlight_on(struct intel_dp *intel_dp)
2083 {
2084         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2085                                        intel_dp->backlight_on_delay);
2086 }
2087
2088 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2089 {
2090         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2091                                        intel_dp->backlight_off_delay);
2092 }
2093
2094 /* Read the current pp_control value, unlocking the register if it
2095  * is locked
2096  */
2097
2098 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2099 {
2100         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2101         u32 control;
2102
2103         lockdep_assert_held(&dev_priv->pps_mutex);
2104
2105         control = I915_READ(_pp_ctrl_reg(intel_dp));
2106         if (WARN_ON(!HAS_DDI(dev_priv) &&
2107                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2108                 control &= ~PANEL_UNLOCK_MASK;
2109                 control |= PANEL_UNLOCK_REGS;
2110         }
2111         return control;
2112 }
2113
2114 /*
2115  * Must be paired with edp_panel_vdd_off().
2116  * Must hold pps_mutex around the whole on/off sequence.
2117  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2118  */
2119 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2120 {
2121         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2122         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2123         u32 pp;
2124         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2125         bool need_to_disable = !intel_dp->want_panel_vdd;
2126
2127         lockdep_assert_held(&dev_priv->pps_mutex);
2128
2129         if (!intel_dp_is_edp(intel_dp))
2130                 return false;
2131
2132         cancel_delayed_work(&intel_dp->panel_vdd_work);
2133         intel_dp->want_panel_vdd = true;
2134
2135         if (edp_have_panel_vdd(intel_dp))
2136                 return need_to_disable;
2137
2138         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2139
2140         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2141                       port_name(intel_dig_port->base.port));
2142
2143         if (!edp_have_panel_power(intel_dp))
2144                 wait_panel_power_cycle(intel_dp);
2145
2146         pp = ironlake_get_pp_control(intel_dp);
2147         pp |= EDP_FORCE_VDD;
2148
2149         pp_stat_reg = _pp_stat_reg(intel_dp);
2150         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2151
2152         I915_WRITE(pp_ctrl_reg, pp);
2153         POSTING_READ(pp_ctrl_reg);
2154         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2155                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2156         /*
2157          * If the panel wasn't on, delay before accessing aux channel
2158          */
2159         if (!edp_have_panel_power(intel_dp)) {
2160                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2161                               port_name(intel_dig_port->base.port));
2162                 msleep(intel_dp->panel_power_up_delay);
2163         }
2164
2165         return need_to_disable;
2166 }
2167
2168 /*
2169  * Must be paired with intel_edp_panel_vdd_off() or
2170  * intel_edp_panel_off().
2171  * Nested calls to these functions are not allowed since
2172  * we drop the lock. Caller must use some higher level
2173  * locking to prevent nested calls from other threads.
2174  */
2175 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2176 {
2177         bool vdd;
2178
2179         if (!intel_dp_is_edp(intel_dp))
2180                 return;
2181
2182         pps_lock(intel_dp);
2183         vdd = edp_panel_vdd_on(intel_dp);
2184         pps_unlock(intel_dp);
2185
2186         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2187              port_name(dp_to_dig_port(intel_dp)->base.port));
2188 }
2189
2190 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2191 {
2192         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2193         struct intel_digital_port *intel_dig_port =
2194                 dp_to_dig_port(intel_dp);
2195         u32 pp;
2196         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2197
2198         lockdep_assert_held(&dev_priv->pps_mutex);
2199
2200         WARN_ON(intel_dp->want_panel_vdd);
2201
2202         if (!edp_have_panel_vdd(intel_dp))
2203                 return;
2204
2205         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2206                       port_name(intel_dig_port->base.port));
2207
2208         pp = ironlake_get_pp_control(intel_dp);
2209         pp &= ~EDP_FORCE_VDD;
2210
2211         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2212         pp_stat_reg = _pp_stat_reg(intel_dp);
2213
2214         I915_WRITE(pp_ctrl_reg, pp);
2215         POSTING_READ(pp_ctrl_reg);
2216
2217         /* Make sure sequencer is idle before allowing subsequent activity */
2218         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2219         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2220
2221         if ((pp & PANEL_POWER_ON) == 0)
2222                 intel_dp->panel_power_off_time = ktime_get_boottime();
2223
2224         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2225 }
2226
2227 static void edp_panel_vdd_work(struct work_struct *__work)
2228 {
2229         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2230                                                  struct intel_dp, panel_vdd_work);
2231
2232         pps_lock(intel_dp);
2233         if (!intel_dp->want_panel_vdd)
2234                 edp_panel_vdd_off_sync(intel_dp);
2235         pps_unlock(intel_dp);
2236 }
2237
2238 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2239 {
2240         unsigned long delay;
2241
2242         /*
2243          * Queue the timer to fire a long time from now (relative to the power
2244          * down delay) to keep the panel power up across a sequence of
2245          * operations.
2246          */
2247         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2248         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2249 }
2250
2251 /*
2252  * Must be paired with edp_panel_vdd_on().
2253  * Must hold pps_mutex around the whole on/off sequence.
2254  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2255  */
2256 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2257 {
2258         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2259
2260         lockdep_assert_held(&dev_priv->pps_mutex);
2261
2262         if (!intel_dp_is_edp(intel_dp))
2263                 return;
2264
2265         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2266              port_name(dp_to_dig_port(intel_dp)->base.port));
2267
2268         intel_dp->want_panel_vdd = false;
2269
2270         if (sync)
2271                 edp_panel_vdd_off_sync(intel_dp);
2272         else
2273                 edp_panel_vdd_schedule_off(intel_dp);
2274 }
2275
2276 static void edp_panel_on(struct intel_dp *intel_dp)
2277 {
2278         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2279         u32 pp;
2280         i915_reg_t pp_ctrl_reg;
2281
2282         lockdep_assert_held(&dev_priv->pps_mutex);
2283
2284         if (!intel_dp_is_edp(intel_dp))
2285                 return;
2286
2287         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2288                       port_name(dp_to_dig_port(intel_dp)->base.port));
2289
2290         if (WARN(edp_have_panel_power(intel_dp),
2291                  "eDP port %c panel power already on\n",
2292                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2293                 return;
2294
2295         wait_panel_power_cycle(intel_dp);
2296
2297         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2298         pp = ironlake_get_pp_control(intel_dp);
2299         if (IS_GEN5(dev_priv)) {
2300                 /* ILK workaround: disable reset around power sequence */
2301                 pp &= ~PANEL_POWER_RESET;
2302                 I915_WRITE(pp_ctrl_reg, pp);
2303                 POSTING_READ(pp_ctrl_reg);
2304         }
2305
2306         pp |= PANEL_POWER_ON;
2307         if (!IS_GEN5(dev_priv))
2308                 pp |= PANEL_POWER_RESET;
2309
2310         I915_WRITE(pp_ctrl_reg, pp);
2311         POSTING_READ(pp_ctrl_reg);
2312
2313         wait_panel_on(intel_dp);
2314         intel_dp->last_power_on = jiffies;
2315
2316         if (IS_GEN5(dev_priv)) {
2317                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2318                 I915_WRITE(pp_ctrl_reg, pp);
2319                 POSTING_READ(pp_ctrl_reg);
2320         }
2321 }
2322
2323 void intel_edp_panel_on(struct intel_dp *intel_dp)
2324 {
2325         if (!intel_dp_is_edp(intel_dp))
2326                 return;
2327
2328         pps_lock(intel_dp);
2329         edp_panel_on(intel_dp);
2330         pps_unlock(intel_dp);
2331 }
2332
2333
2334 static void edp_panel_off(struct intel_dp *intel_dp)
2335 {
2336         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2337         u32 pp;
2338         i915_reg_t pp_ctrl_reg;
2339
2340         lockdep_assert_held(&dev_priv->pps_mutex);
2341
2342         if (!intel_dp_is_edp(intel_dp))
2343                 return;
2344
2345         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2346                       port_name(dp_to_dig_port(intel_dp)->base.port));
2347
2348         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2349              port_name(dp_to_dig_port(intel_dp)->base.port));
2350
2351         pp = ironlake_get_pp_control(intel_dp);
2352         /* We need to switch off panel power _and_ force vdd, for otherwise some
2353          * panels get very unhappy and cease to work. */
2354         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2355                 EDP_BLC_ENABLE);
2356
2357         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2358
2359         intel_dp->want_panel_vdd = false;
2360
2361         I915_WRITE(pp_ctrl_reg, pp);
2362         POSTING_READ(pp_ctrl_reg);
2363
2364         wait_panel_off(intel_dp);
2365         intel_dp->panel_power_off_time = ktime_get_boottime();
2366
2367         /* We got a reference when we enabled the VDD. */
2368         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2369 }
2370
2371 void intel_edp_panel_off(struct intel_dp *intel_dp)
2372 {
2373         if (!intel_dp_is_edp(intel_dp))
2374                 return;
2375
2376         pps_lock(intel_dp);
2377         edp_panel_off(intel_dp);
2378         pps_unlock(intel_dp);
2379 }
2380
2381 /* Enable backlight in the panel power control. */
2382 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2383 {
2384         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2385         u32 pp;
2386         i915_reg_t pp_ctrl_reg;
2387
2388         /*
2389          * If we enable the backlight right away following a panel power
2390          * on, we may see slight flicker as the panel syncs with the eDP
2391          * link.  So delay a bit to make sure the image is solid before
2392          * allowing it to appear.
2393          */
2394         wait_backlight_on(intel_dp);
2395
2396         pps_lock(intel_dp);
2397
2398         pp = ironlake_get_pp_control(intel_dp);
2399         pp |= EDP_BLC_ENABLE;
2400
2401         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2402
2403         I915_WRITE(pp_ctrl_reg, pp);
2404         POSTING_READ(pp_ctrl_reg);
2405
2406         pps_unlock(intel_dp);
2407 }
2408
2409 /* Enable backlight PWM and backlight PP control. */
2410 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2411                             const struct drm_connector_state *conn_state)
2412 {
2413         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2414
2415         if (!intel_dp_is_edp(intel_dp))
2416                 return;
2417
2418         DRM_DEBUG_KMS("\n");
2419
2420         intel_panel_enable_backlight(crtc_state, conn_state);
2421         _intel_edp_backlight_on(intel_dp);
2422 }
2423
2424 /* Disable backlight in the panel power control. */
2425 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2426 {
2427         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2428         u32 pp;
2429         i915_reg_t pp_ctrl_reg;
2430
2431         if (!intel_dp_is_edp(intel_dp))
2432                 return;
2433
2434         pps_lock(intel_dp);
2435
2436         pp = ironlake_get_pp_control(intel_dp);
2437         pp &= ~EDP_BLC_ENABLE;
2438
2439         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2440
2441         I915_WRITE(pp_ctrl_reg, pp);
2442         POSTING_READ(pp_ctrl_reg);
2443
2444         pps_unlock(intel_dp);
2445
2446         intel_dp->last_backlight_off = jiffies;
2447         edp_wait_backlight_off(intel_dp);
2448 }
2449
2450 /* Disable backlight PP control and backlight PWM. */
2451 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2452 {
2453         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2454
2455         if (!intel_dp_is_edp(intel_dp))
2456                 return;
2457
2458         DRM_DEBUG_KMS("\n");
2459
2460         _intel_edp_backlight_off(intel_dp);
2461         intel_panel_disable_backlight(old_conn_state);
2462 }
2463
2464 /*
2465  * Hook for controlling the panel power control backlight through the bl_power
2466  * sysfs attribute. Take care to handle multiple calls.
2467  */
2468 static void intel_edp_backlight_power(struct intel_connector *connector,
2469                                       bool enable)
2470 {
2471         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2472         bool is_enabled;
2473
2474         pps_lock(intel_dp);
2475         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2476         pps_unlock(intel_dp);
2477
2478         if (is_enabled == enable)
2479                 return;
2480
2481         DRM_DEBUG_KMS("panel power control backlight %s\n",
2482                       enable ? "enable" : "disable");
2483
2484         if (enable)
2485                 _intel_edp_backlight_on(intel_dp);
2486         else
2487                 _intel_edp_backlight_off(intel_dp);
2488 }
2489
2490 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2491 {
2492         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2493         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2494         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2495
2496         I915_STATE_WARN(cur_state != state,
2497                         "DP port %c state assertion failure (expected %s, current %s)\n",
2498                         port_name(dig_port->base.port),
2499                         onoff(state), onoff(cur_state));
2500 }
2501 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2502
2503 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2504 {
2505         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2506
2507         I915_STATE_WARN(cur_state != state,
2508                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2509                         onoff(state), onoff(cur_state));
2510 }
2511 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2512 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2513
2514 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2515                                 const struct intel_crtc_state *pipe_config)
2516 {
2517         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2518         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2519
2520         assert_pipe_disabled(dev_priv, crtc->pipe);
2521         assert_dp_port_disabled(intel_dp);
2522         assert_edp_pll_disabled(dev_priv);
2523
2524         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2525                       pipe_config->port_clock);
2526
2527         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2528
2529         if (pipe_config->port_clock == 162000)
2530                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2531         else
2532                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2533
2534         I915_WRITE(DP_A, intel_dp->DP);
2535         POSTING_READ(DP_A);
2536         udelay(500);
2537
2538         /*
2539          * [DevILK] Work around required when enabling DP PLL
2540          * while a pipe is enabled going to FDI:
2541          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2542          * 2. Program DP PLL enable
2543          */
2544         if (IS_GEN5(dev_priv))
2545                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2546
2547         intel_dp->DP |= DP_PLL_ENABLE;
2548
2549         I915_WRITE(DP_A, intel_dp->DP);
2550         POSTING_READ(DP_A);
2551         udelay(200);
2552 }
2553
2554 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2555                                  const struct intel_crtc_state *old_crtc_state)
2556 {
2557         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2558         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2559
2560         assert_pipe_disabled(dev_priv, crtc->pipe);
2561         assert_dp_port_disabled(intel_dp);
2562         assert_edp_pll_enabled(dev_priv);
2563
2564         DRM_DEBUG_KMS("disabling eDP PLL\n");
2565
2566         intel_dp->DP &= ~DP_PLL_ENABLE;
2567
2568         I915_WRITE(DP_A, intel_dp->DP);
2569         POSTING_READ(DP_A);
2570         udelay(200);
2571 }
2572
2573 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2574 {
2575         /*
2576          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2577          * be capable of signalling downstream hpd with a long pulse.
2578          * Whether or not that means D3 is safe to use is not clear,
2579          * but let's assume so until proven otherwise.
2580          *
2581          * FIXME should really check all downstream ports...
2582          */
2583         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2584                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2585                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2586 }
2587
2588 /* If the sink supports it, try to set the power state appropriately */
2589 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2590 {
2591         int ret, i;
2592
2593         /* Should have a valid DPCD by this point */
2594         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2595                 return;
2596
2597         if (mode != DRM_MODE_DPMS_ON) {
2598                 if (downstream_hpd_needs_d0(intel_dp))
2599                         return;
2600
2601                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2602                                          DP_SET_POWER_D3);
2603         } else {
2604                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2605
2606                 /*
2607                  * When turning on, we need to retry for 1ms to give the sink
2608                  * time to wake up.
2609                  */
2610                 for (i = 0; i < 3; i++) {
2611                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2612                                                  DP_SET_POWER_D0);
2613                         if (ret == 1)
2614                                 break;
2615                         msleep(1);
2616                 }
2617
2618                 if (ret == 1 && lspcon->active)
2619                         lspcon_wait_pcon_mode(lspcon);
2620         }
2621
2622         if (ret != 1)
2623                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2624                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2625 }
2626
2627 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2628                                   enum pipe *pipe)
2629 {
2630         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2631         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2632         enum port port = encoder->port;
2633         u32 tmp;
2634         bool ret;
2635
2636         if (!intel_display_power_get_if_enabled(dev_priv,
2637                                                 encoder->power_domain))
2638                 return false;
2639
2640         ret = false;
2641
2642         tmp = I915_READ(intel_dp->output_reg);
2643
2644         if (!(tmp & DP_PORT_EN))
2645                 goto out;
2646
2647         if (IS_GEN7(dev_priv) && port == PORT_A) {
2648                 *pipe = PORT_TO_PIPE_CPT(tmp);
2649         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2650                 enum pipe p;
2651
2652                 for_each_pipe(dev_priv, p) {
2653                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2654                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2655                                 *pipe = p;
2656                                 ret = true;
2657
2658                                 goto out;
2659                         }
2660                 }
2661
2662                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2663                               i915_mmio_reg_offset(intel_dp->output_reg));
2664         } else if (IS_CHERRYVIEW(dev_priv)) {
2665                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2666         } else {
2667                 *pipe = PORT_TO_PIPE(tmp);
2668         }
2669
2670         ret = true;
2671
2672 out:
2673         intel_display_power_put(dev_priv, encoder->power_domain);
2674
2675         return ret;
2676 }
2677
2678 static void intel_dp_get_config(struct intel_encoder *encoder,
2679                                 struct intel_crtc_state *pipe_config)
2680 {
2681         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2682         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2683         u32 tmp, flags = 0;
2684         enum port port = encoder->port;
2685         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2686
2687         if (encoder->type == INTEL_OUTPUT_EDP)
2688                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2689         else
2690                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2691
2692         tmp = I915_READ(intel_dp->output_reg);
2693
2694         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2695
2696         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2697                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2698
2699                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2700                         flags |= DRM_MODE_FLAG_PHSYNC;
2701                 else
2702                         flags |= DRM_MODE_FLAG_NHSYNC;
2703
2704                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2705                         flags |= DRM_MODE_FLAG_PVSYNC;
2706                 else
2707                         flags |= DRM_MODE_FLAG_NVSYNC;
2708         } else {
2709                 if (tmp & DP_SYNC_HS_HIGH)
2710                         flags |= DRM_MODE_FLAG_PHSYNC;
2711                 else
2712                         flags |= DRM_MODE_FLAG_NHSYNC;
2713
2714                 if (tmp & DP_SYNC_VS_HIGH)
2715                         flags |= DRM_MODE_FLAG_PVSYNC;
2716                 else
2717                         flags |= DRM_MODE_FLAG_NVSYNC;
2718         }
2719
2720         pipe_config->base.adjusted_mode.flags |= flags;
2721
2722         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2723                 pipe_config->limited_color_range = true;
2724
2725         pipe_config->lane_count =
2726                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2727
2728         intel_dp_get_m_n(crtc, pipe_config);
2729
2730         if (port == PORT_A) {
2731                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2732                         pipe_config->port_clock = 162000;
2733                 else
2734                         pipe_config->port_clock = 270000;
2735         }
2736
2737         pipe_config->base.adjusted_mode.crtc_clock =
2738                 intel_dotclock_calculate(pipe_config->port_clock,
2739                                          &pipe_config->dp_m_n);
2740
2741         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2742             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2743                 /*
2744                  * This is a big fat ugly hack.
2745                  *
2746                  * Some machines in UEFI boot mode provide us a VBT that has 18
2747                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2748                  * unknown we fail to light up. Yet the same BIOS boots up with
2749                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2750                  * max, not what it tells us to use.
2751                  *
2752                  * Note: This will still be broken if the eDP panel is not lit
2753                  * up by the BIOS, and thus we can't get the mode at module
2754                  * load.
2755                  */
2756                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2757                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2758                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2759         }
2760 }
2761
2762 static void intel_disable_dp(struct intel_encoder *encoder,
2763                              const struct intel_crtc_state *old_crtc_state,
2764                              const struct drm_connector_state *old_conn_state)
2765 {
2766         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2767
2768         intel_dp->link_trained = false;
2769
2770         if (old_crtc_state->has_audio)
2771                 intel_audio_codec_disable(encoder,
2772                                           old_crtc_state, old_conn_state);
2773
2774         /* Make sure the panel is off before trying to change the mode. But also
2775          * ensure that we have vdd while we switch off the panel. */
2776         intel_edp_panel_vdd_on(intel_dp);
2777         intel_edp_backlight_off(old_conn_state);
2778         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2779         intel_edp_panel_off(intel_dp);
2780 }
2781
2782 static void g4x_disable_dp(struct intel_encoder *encoder,
2783                            const struct intel_crtc_state *old_crtc_state,
2784                            const struct drm_connector_state *old_conn_state)
2785 {
2786         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2787
2788         /* disable the port before the pipe on g4x */
2789         intel_dp_link_down(encoder, old_crtc_state);
2790 }
2791
2792 static void ilk_disable_dp(struct intel_encoder *encoder,
2793                            const struct intel_crtc_state *old_crtc_state,
2794                            const struct drm_connector_state *old_conn_state)
2795 {
2796         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2797 }
2798
2799 static void vlv_disable_dp(struct intel_encoder *encoder,
2800                            const struct intel_crtc_state *old_crtc_state,
2801                            const struct drm_connector_state *old_conn_state)
2802 {
2803         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2804
2805         intel_psr_disable(intel_dp, old_crtc_state);
2806
2807         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2808 }
2809
2810 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2811                                 const struct intel_crtc_state *old_crtc_state,
2812                                 const struct drm_connector_state *old_conn_state)
2813 {
2814         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2815         enum port port = encoder->port;
2816
2817         intel_dp_link_down(encoder, old_crtc_state);
2818
2819         /* Only ilk+ has port A */
2820         if (port == PORT_A)
2821                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2822 }
2823
2824 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2825                                 const struct intel_crtc_state *old_crtc_state,
2826                                 const struct drm_connector_state *old_conn_state)
2827 {
2828         intel_dp_link_down(encoder, old_crtc_state);
2829 }
2830
2831 static void chv_post_disable_dp(struct intel_encoder *encoder,
2832                                 const struct intel_crtc_state *old_crtc_state,
2833                                 const struct drm_connector_state *old_conn_state)
2834 {
2835         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2836
2837         intel_dp_link_down(encoder, old_crtc_state);
2838
2839         mutex_lock(&dev_priv->sb_lock);
2840
2841         /* Assert data lane reset */
2842         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2843
2844         mutex_unlock(&dev_priv->sb_lock);
2845 }
2846
2847 static void
2848 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2849                          uint32_t *DP,
2850                          uint8_t dp_train_pat)
2851 {
2852         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2853         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2854         enum port port = intel_dig_port->base.port;
2855
2856         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2857                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2858                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2859
2860         if (HAS_DDI(dev_priv)) {
2861                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2862
2863                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2864                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2865                 else
2866                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2867
2868                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2869                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2870                 case DP_TRAINING_PATTERN_DISABLE:
2871                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2872
2873                         break;
2874                 case DP_TRAINING_PATTERN_1:
2875                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2876                         break;
2877                 case DP_TRAINING_PATTERN_2:
2878                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2879                         break;
2880                 case DP_TRAINING_PATTERN_3:
2881                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2882                         break;
2883                 }
2884                 I915_WRITE(DP_TP_CTL(port), temp);
2885
2886         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2887                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2888                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2889
2890                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2891                 case DP_TRAINING_PATTERN_DISABLE:
2892                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2893                         break;
2894                 case DP_TRAINING_PATTERN_1:
2895                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2896                         break;
2897                 case DP_TRAINING_PATTERN_2:
2898                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2899                         break;
2900                 case DP_TRAINING_PATTERN_3:
2901                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2902                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2903                         break;
2904                 }
2905
2906         } else {
2907                 *DP &= ~DP_LINK_TRAIN_MASK;
2908
2909                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2910                 case DP_TRAINING_PATTERN_DISABLE:
2911                         *DP |= DP_LINK_TRAIN_OFF;
2912                         break;
2913                 case DP_TRAINING_PATTERN_1:
2914                         *DP |= DP_LINK_TRAIN_PAT_1;
2915                         break;
2916                 case DP_TRAINING_PATTERN_2:
2917                         *DP |= DP_LINK_TRAIN_PAT_2;
2918                         break;
2919                 case DP_TRAINING_PATTERN_3:
2920                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2921                         *DP |= DP_LINK_TRAIN_PAT_2;
2922                         break;
2923                 }
2924         }
2925 }
2926
2927 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2928                                  const struct intel_crtc_state *old_crtc_state)
2929 {
2930         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2931
2932         /* enable with pattern 1 (as per spec) */
2933
2934         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2935
2936         /*
2937          * Magic for VLV/CHV. We _must_ first set up the register
2938          * without actually enabling the port, and then do another
2939          * write to enable the port. Otherwise link training will
2940          * fail when the power sequencer is freshly used for this port.
2941          */
2942         intel_dp->DP |= DP_PORT_EN;
2943         if (old_crtc_state->has_audio)
2944                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2945
2946         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2947         POSTING_READ(intel_dp->output_reg);
2948 }
2949
2950 static void intel_enable_dp(struct intel_encoder *encoder,
2951                             const struct intel_crtc_state *pipe_config,
2952                             const struct drm_connector_state *conn_state)
2953 {
2954         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2955         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2956         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2957         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2958         enum pipe pipe = crtc->pipe;
2959
2960         if (WARN_ON(dp_reg & DP_PORT_EN))
2961                 return;
2962
2963         pps_lock(intel_dp);
2964
2965         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2966                 vlv_init_panel_power_sequencer(encoder, pipe_config);
2967
2968         intel_dp_enable_port(intel_dp, pipe_config);
2969
2970         edp_panel_vdd_on(intel_dp);
2971         edp_panel_on(intel_dp);
2972         edp_panel_vdd_off(intel_dp, true);
2973
2974         pps_unlock(intel_dp);
2975
2976         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2977                 unsigned int lane_mask = 0x0;
2978
2979                 if (IS_CHERRYVIEW(dev_priv))
2980                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2981
2982                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2983                                     lane_mask);
2984         }
2985
2986         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2987         intel_dp_start_link_train(intel_dp);
2988         intel_dp_stop_link_train(intel_dp);
2989
2990         if (pipe_config->has_audio) {
2991                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2992                                  pipe_name(pipe));
2993                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2994         }
2995 }
2996
2997 static void g4x_enable_dp(struct intel_encoder *encoder,
2998                           const struct intel_crtc_state *pipe_config,
2999                           const struct drm_connector_state *conn_state)
3000 {
3001         intel_enable_dp(encoder, pipe_config, conn_state);
3002         intel_edp_backlight_on(pipe_config, conn_state);
3003 }
3004
3005 static void vlv_enable_dp(struct intel_encoder *encoder,
3006                           const struct intel_crtc_state *pipe_config,
3007                           const struct drm_connector_state *conn_state)
3008 {
3009         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3010
3011         intel_edp_backlight_on(pipe_config, conn_state);
3012         intel_psr_enable(intel_dp, pipe_config);
3013 }
3014
3015 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3016                               const struct intel_crtc_state *pipe_config,
3017                               const struct drm_connector_state *conn_state)
3018 {
3019         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3020         enum port port = encoder->port;
3021
3022         intel_dp_prepare(encoder, pipe_config);
3023
3024         /* Only ilk+ has port A */
3025         if (port == PORT_A)
3026                 ironlake_edp_pll_on(intel_dp, pipe_config);
3027 }
3028
3029 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3030 {
3031         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3032         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3033         enum pipe pipe = intel_dp->pps_pipe;
3034         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3035
3036         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3037
3038         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3039                 return;
3040
3041         edp_panel_vdd_off_sync(intel_dp);
3042
3043         /*
3044          * VLV seems to get confused when multiple power seqeuencers
3045          * have the same port selected (even if only one has power/vdd
3046          * enabled). The failure manifests as vlv_wait_port_ready() failing
3047          * CHV on the other hand doesn't seem to mind having the same port
3048          * selected in multiple power seqeuencers, but let's clear the
3049          * port select always when logically disconnecting a power sequencer
3050          * from a port.
3051          */
3052         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3053                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3054         I915_WRITE(pp_on_reg, 0);
3055         POSTING_READ(pp_on_reg);
3056
3057         intel_dp->pps_pipe = INVALID_PIPE;
3058 }
3059
3060 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3061                                       enum pipe pipe)
3062 {
3063         struct intel_encoder *encoder;
3064
3065         lockdep_assert_held(&dev_priv->pps_mutex);
3066
3067         for_each_intel_encoder(&dev_priv->drm, encoder) {
3068                 struct intel_dp *intel_dp;
3069                 enum port port;
3070
3071                 if (encoder->type != INTEL_OUTPUT_DP &&
3072                     encoder->type != INTEL_OUTPUT_EDP)
3073                         continue;
3074
3075                 intel_dp = enc_to_intel_dp(&encoder->base);
3076                 port = dp_to_dig_port(intel_dp)->base.port;
3077
3078                 WARN(intel_dp->active_pipe == pipe,
3079                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3080                      pipe_name(pipe), port_name(port));
3081
3082                 if (intel_dp->pps_pipe != pipe)
3083                         continue;
3084
3085                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3086                               pipe_name(pipe), port_name(port));
3087
3088                 /* make sure vdd is off before we steal it */
3089                 vlv_detach_power_sequencer(intel_dp);
3090         }
3091 }
3092
3093 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3094                                            const struct intel_crtc_state *crtc_state)
3095 {
3096         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3097         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3098         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3099
3100         lockdep_assert_held(&dev_priv->pps_mutex);
3101
3102         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3103
3104         if (intel_dp->pps_pipe != INVALID_PIPE &&
3105             intel_dp->pps_pipe != crtc->pipe) {
3106                 /*
3107                  * If another power sequencer was being used on this
3108                  * port previously make sure to turn off vdd there while
3109                  * we still have control of it.
3110                  */
3111                 vlv_detach_power_sequencer(intel_dp);
3112         }
3113
3114         /*
3115          * We may be stealing the power
3116          * sequencer from another port.
3117          */
3118         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3119
3120         intel_dp->active_pipe = crtc->pipe;
3121
3122         if (!intel_dp_is_edp(intel_dp))
3123                 return;
3124
3125         /* now it's all ours */
3126         intel_dp->pps_pipe = crtc->pipe;
3127
3128         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3129                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3130
3131         /* init power sequencer on this pipe and port */
3132         intel_dp_init_panel_power_sequencer(intel_dp);
3133         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3134 }
3135
3136 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3137                               const struct intel_crtc_state *pipe_config,
3138                               const struct drm_connector_state *conn_state)
3139 {
3140         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3141
3142         intel_enable_dp(encoder, pipe_config, conn_state);
3143 }
3144
3145 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3146                                   const struct intel_crtc_state *pipe_config,
3147                                   const struct drm_connector_state *conn_state)
3148 {
3149         intel_dp_prepare(encoder, pipe_config);
3150
3151         vlv_phy_pre_pll_enable(encoder, pipe_config);
3152 }
3153
3154 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3155                               const struct intel_crtc_state *pipe_config,
3156                               const struct drm_connector_state *conn_state)
3157 {
3158         chv_phy_pre_encoder_enable(encoder, pipe_config);
3159
3160         intel_enable_dp(encoder, pipe_config, conn_state);
3161
3162         /* Second common lane will stay alive on its own now */
3163         chv_phy_release_cl2_override(encoder);
3164 }
3165
3166 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3167                                   const struct intel_crtc_state *pipe_config,
3168                                   const struct drm_connector_state *conn_state)
3169 {
3170         intel_dp_prepare(encoder, pipe_config);
3171
3172         chv_phy_pre_pll_enable(encoder, pipe_config);
3173 }
3174
3175 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3176                                     const struct intel_crtc_state *old_crtc_state,
3177                                     const struct drm_connector_state *old_conn_state)
3178 {
3179         chv_phy_post_pll_disable(encoder, old_crtc_state);
3180 }
3181
3182 /*
3183  * Fetch AUX CH registers 0x202 - 0x207 which contain
3184  * link status information
3185  */
3186 bool
3187 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3188 {
3189         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3190                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3191 }
3192
3193 /* These are source-specific values. */
3194 uint8_t
3195 intel_dp_voltage_max(struct intel_dp *intel_dp)
3196 {
3197         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3198         enum port port = dp_to_dig_port(intel_dp)->base.port;
3199
3200         if (INTEL_GEN(dev_priv) >= 9) {
3201                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3202                 return intel_ddi_dp_voltage_max(encoder);
3203         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3204                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3205         else if (IS_GEN7(dev_priv) && port == PORT_A)
3206                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3207         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3208                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3209         else
3210                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3211 }
3212
3213 uint8_t
3214 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3215 {
3216         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3217         enum port port = dp_to_dig_port(intel_dp)->base.port;
3218
3219         if (INTEL_GEN(dev_priv) >= 9) {
3220                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3221                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3222                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3223                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3224                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3225                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3226                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3227                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3228                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3229                 default:
3230                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3231                 }
3232         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3233                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3234                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3235                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3236                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3237                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3238                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3239                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3240                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3241                 default:
3242                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3243                 }
3244         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3245                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3246                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3247                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3248                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3249                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3250                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3251                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3252                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3253                 default:
3254                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3255                 }
3256         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3257                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3258                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3259                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3260                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3261                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3262                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3263                 default:
3264                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3265                 }
3266         } else {
3267                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3268                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3269                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3270                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3271                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3272                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3273                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3274                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3275                 default:
3276                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3277                 }
3278         }
3279 }
3280
3281 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3282 {
3283         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3284         unsigned long demph_reg_value, preemph_reg_value,
3285                 uniqtranscale_reg_value;
3286         uint8_t train_set = intel_dp->train_set[0];
3287
3288         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3289         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3290                 preemph_reg_value = 0x0004000;
3291                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3292                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3293                         demph_reg_value = 0x2B405555;
3294                         uniqtranscale_reg_value = 0x552AB83A;
3295                         break;
3296                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3297                         demph_reg_value = 0x2B404040;
3298                         uniqtranscale_reg_value = 0x5548B83A;
3299                         break;
3300                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3301                         demph_reg_value = 0x2B245555;
3302                         uniqtranscale_reg_value = 0x5560B83A;
3303                         break;
3304                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3305                         demph_reg_value = 0x2B405555;
3306                         uniqtranscale_reg_value = 0x5598DA3A;
3307                         break;
3308                 default:
3309                         return 0;
3310                 }
3311                 break;
3312         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3313                 preemph_reg_value = 0x0002000;
3314                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3315                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3316                         demph_reg_value = 0x2B404040;
3317                         uniqtranscale_reg_value = 0x5552B83A;
3318                         break;
3319                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3320                         demph_reg_value = 0x2B404848;
3321                         uniqtranscale_reg_value = 0x5580B83A;
3322                         break;
3323                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3324                         demph_reg_value = 0x2B404040;
3325                         uniqtranscale_reg_value = 0x55ADDA3A;
3326                         break;
3327                 default:
3328                         return 0;
3329                 }
3330                 break;
3331         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3332                 preemph_reg_value = 0x0000000;
3333                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3334                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3335                         demph_reg_value = 0x2B305555;
3336                         uniqtranscale_reg_value = 0x5570B83A;
3337                         break;
3338                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3339                         demph_reg_value = 0x2B2B4040;
3340                         uniqtranscale_reg_value = 0x55ADDA3A;
3341                         break;
3342                 default:
3343                         return 0;
3344                 }
3345                 break;
3346         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3347                 preemph_reg_value = 0x0006000;
3348                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3349                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3350                         demph_reg_value = 0x1B405555;
3351                         uniqtranscale_reg_value = 0x55ADDA3A;
3352                         break;
3353                 default:
3354                         return 0;
3355                 }
3356                 break;
3357         default:
3358                 return 0;
3359         }
3360
3361         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3362                                  uniqtranscale_reg_value, 0);
3363
3364         return 0;
3365 }
3366
3367 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3368 {
3369         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3370         u32 deemph_reg_value, margin_reg_value;
3371         bool uniq_trans_scale = false;
3372         uint8_t train_set = intel_dp->train_set[0];
3373
3374         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3375         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3376                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3377                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3378                         deemph_reg_value = 128;
3379                         margin_reg_value = 52;
3380                         break;
3381                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3382                         deemph_reg_value = 128;
3383                         margin_reg_value = 77;
3384                         break;
3385                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3386                         deemph_reg_value = 128;
3387                         margin_reg_value = 102;
3388                         break;
3389                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3390                         deemph_reg_value = 128;
3391                         margin_reg_value = 154;
3392                         uniq_trans_scale = true;
3393                         break;
3394                 default:
3395                         return 0;
3396                 }
3397                 break;
3398         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3399                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3400                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3401                         deemph_reg_value = 85;
3402                         margin_reg_value = 78;
3403                         break;
3404                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3405                         deemph_reg_value = 85;
3406                         margin_reg_value = 116;
3407                         break;
3408                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3409                         deemph_reg_value = 85;
3410                         margin_reg_value = 154;
3411                         break;
3412                 default:
3413                         return 0;
3414                 }
3415                 break;
3416         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3417                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3418                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3419                         deemph_reg_value = 64;
3420                         margin_reg_value = 104;
3421                         break;
3422                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3423                         deemph_reg_value = 64;
3424                         margin_reg_value = 154;
3425                         break;
3426                 default:
3427                         return 0;
3428                 }
3429                 break;
3430         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3431                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3432                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3433                         deemph_reg_value = 43;
3434                         margin_reg_value = 154;
3435                         break;
3436                 default:
3437                         return 0;
3438                 }
3439                 break;
3440         default:
3441                 return 0;
3442         }
3443
3444         chv_set_phy_signal_level(encoder, deemph_reg_value,
3445                                  margin_reg_value, uniq_trans_scale);
3446
3447         return 0;
3448 }
3449
3450 static uint32_t
3451 gen4_signal_levels(uint8_t train_set)
3452 {
3453         uint32_t        signal_levels = 0;
3454
3455         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3456         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3457         default:
3458                 signal_levels |= DP_VOLTAGE_0_4;
3459                 break;
3460         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3461                 signal_levels |= DP_VOLTAGE_0_6;
3462                 break;
3463         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3464                 signal_levels |= DP_VOLTAGE_0_8;
3465                 break;
3466         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3467                 signal_levels |= DP_VOLTAGE_1_2;
3468                 break;
3469         }
3470         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3471         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3472         default:
3473                 signal_levels |= DP_PRE_EMPHASIS_0;
3474                 break;
3475         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3476                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3477                 break;
3478         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3479                 signal_levels |= DP_PRE_EMPHASIS_6;
3480                 break;
3481         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3482                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3483                 break;
3484         }
3485         return signal_levels;
3486 }
3487
3488 /* Gen6's DP voltage swing and pre-emphasis control */
3489 static uint32_t
3490 gen6_edp_signal_levels(uint8_t train_set)
3491 {
3492         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3493                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3494         switch (signal_levels) {
3495         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3496         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3497                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3498         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3499                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3500         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3501         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3502                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3503         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3504         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3505                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3506         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3507         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3508                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3509         default:
3510                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3511                               "0x%x\n", signal_levels);
3512                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3513         }
3514 }
3515
3516 /* Gen7's DP voltage swing and pre-emphasis control */
3517 static uint32_t
3518 gen7_edp_signal_levels(uint8_t train_set)
3519 {
3520         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3521                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3522         switch (signal_levels) {
3523         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3524                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3525         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3526                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3527         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3528                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3529
3530         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3531                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3532         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3533                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3534
3535         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3536                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3537         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3538                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3539
3540         default:
3541                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3542                               "0x%x\n", signal_levels);
3543                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3544         }
3545 }
3546
3547 void
3548 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3549 {
3550         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3551         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3552         enum port port = intel_dig_port->base.port;
3553         uint32_t signal_levels, mask = 0;
3554         uint8_t train_set = intel_dp->train_set[0];
3555
3556         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3557                 signal_levels = bxt_signal_levels(intel_dp);
3558         } else if (HAS_DDI(dev_priv)) {
3559                 signal_levels = ddi_signal_levels(intel_dp);
3560                 mask = DDI_BUF_EMP_MASK;
3561         } else if (IS_CHERRYVIEW(dev_priv)) {
3562                 signal_levels = chv_signal_levels(intel_dp);
3563         } else if (IS_VALLEYVIEW(dev_priv)) {
3564                 signal_levels = vlv_signal_levels(intel_dp);
3565         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3566                 signal_levels = gen7_edp_signal_levels(train_set);
3567                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3568         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3569                 signal_levels = gen6_edp_signal_levels(train_set);
3570                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3571         } else {
3572                 signal_levels = gen4_signal_levels(train_set);
3573                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3574         }
3575
3576         if (mask)
3577                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3578
3579         DRM_DEBUG_KMS("Using vswing level %d\n",
3580                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3581         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3582                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3583                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3584
3585         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3586
3587         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3588         POSTING_READ(intel_dp->output_reg);
3589 }
3590
3591 void
3592 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3593                                        uint8_t dp_train_pat)
3594 {
3595         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3596         struct drm_i915_private *dev_priv =
3597                 to_i915(intel_dig_port->base.base.dev);
3598
3599         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3600
3601         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3602         POSTING_READ(intel_dp->output_reg);
3603 }
3604
3605 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3606 {
3607         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3608         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3609         enum port port = intel_dig_port->base.port;
3610         uint32_t val;
3611
3612         if (!HAS_DDI(dev_priv))
3613                 return;
3614
3615         val = I915_READ(DP_TP_CTL(port));
3616         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3617         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3618         I915_WRITE(DP_TP_CTL(port), val);
3619
3620         /*
3621          * On PORT_A we can have only eDP in SST mode. There the only reason
3622          * we need to set idle transmission mode is to work around a HW issue
3623          * where we enable the pipe while not in idle link-training mode.
3624          * In this case there is requirement to wait for a minimum number of
3625          * idle patterns to be sent.
3626          */
3627         if (port == PORT_A)
3628                 return;
3629
3630         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3631                                     DP_TP_STATUS_IDLE_DONE,
3632                                     DP_TP_STATUS_IDLE_DONE,
3633                                     1))
3634                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3635 }
3636
3637 static void
3638 intel_dp_link_down(struct intel_encoder *encoder,
3639                    const struct intel_crtc_state *old_crtc_state)
3640 {
3641         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3642         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3643         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3644         enum port port = encoder->port;
3645         uint32_t DP = intel_dp->DP;
3646
3647         if (WARN_ON(HAS_DDI(dev_priv)))
3648                 return;
3649
3650         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3651                 return;
3652
3653         DRM_DEBUG_KMS("\n");
3654
3655         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3656             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3657                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3658                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3659         } else {
3660                 DP &= ~DP_LINK_TRAIN_MASK;
3661                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3662         }
3663         I915_WRITE(intel_dp->output_reg, DP);
3664         POSTING_READ(intel_dp->output_reg);
3665
3666         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3667         I915_WRITE(intel_dp->output_reg, DP);
3668         POSTING_READ(intel_dp->output_reg);
3669
3670         /*
3671          * HW workaround for IBX, we need to move the port
3672          * to transcoder A after disabling it to allow the
3673          * matching HDMI port to be enabled on transcoder A.
3674          */
3675         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3676                 /*
3677                  * We get CPU/PCH FIFO underruns on the other pipe when
3678                  * doing the workaround. Sweep them under the rug.
3679                  */
3680                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3681                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3682
3683                 /* always enable with pattern 1 (as per spec) */
3684                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3685                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3686                 I915_WRITE(intel_dp->output_reg, DP);
3687                 POSTING_READ(intel_dp->output_reg);
3688
3689                 DP &= ~DP_PORT_EN;
3690                 I915_WRITE(intel_dp->output_reg, DP);
3691                 POSTING_READ(intel_dp->output_reg);
3692
3693                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3694                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3695                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3696         }
3697
3698         msleep(intel_dp->panel_power_down_delay);
3699
3700         intel_dp->DP = DP;
3701
3702         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3703                 pps_lock(intel_dp);
3704                 intel_dp->active_pipe = INVALID_PIPE;
3705                 pps_unlock(intel_dp);
3706         }
3707 }
3708
3709 bool
3710 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3711 {
3712         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3713                              sizeof(intel_dp->dpcd)) < 0)
3714                 return false; /* aux transfer failed */
3715
3716         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3717
3718         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3719 }
3720
3721 static bool
3722 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3723 {
3724         struct drm_i915_private *dev_priv =
3725                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3726
3727         /* this function is meant to be called only once */
3728         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3729
3730         if (!intel_dp_read_dpcd(intel_dp))
3731                 return false;
3732
3733         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3734                          drm_dp_is_branch(intel_dp->dpcd));
3735
3736         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3737                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3738                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3739
3740         intel_psr_init_dpcd(intel_dp);
3741
3742         /*
3743          * Read the eDP display control registers.
3744          *
3745          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3746          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3747          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3748          * method). The display control registers should read zero if they're
3749          * not supported anyway.
3750          */
3751         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3752                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3753                              sizeof(intel_dp->edp_dpcd))
3754                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3755                               intel_dp->edp_dpcd);
3756
3757         /* Read the eDP 1.4+ supported link rates. */
3758         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3759                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3760                 int i;
3761
3762                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3763                                 sink_rates, sizeof(sink_rates));
3764
3765                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3766                         int val = le16_to_cpu(sink_rates[i]);
3767
3768                         if (val == 0)
3769                                 break;
3770
3771                         /* Value read multiplied by 200kHz gives the per-lane
3772                          * link rate in kHz. The source rates are, however,
3773                          * stored in terms of LS_Clk kHz. The full conversion
3774                          * back to symbols is
3775                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3776                          */
3777                         intel_dp->sink_rates[i] = (val * 200) / 10;
3778                 }
3779                 intel_dp->num_sink_rates = i;
3780         }
3781
3782         /*
3783          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3784          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3785          */
3786         if (intel_dp->num_sink_rates)
3787                 intel_dp->use_rate_select = true;
3788         else
3789                 intel_dp_set_sink_rates(intel_dp);
3790
3791         intel_dp_set_common_rates(intel_dp);
3792
3793         return true;
3794 }
3795
3796
3797 static bool
3798 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3799 {
3800         u8 sink_count;
3801
3802         if (!intel_dp_read_dpcd(intel_dp))
3803                 return false;
3804
3805         /* Don't clobber cached eDP rates. */
3806         if (!intel_dp_is_edp(intel_dp)) {
3807                 intel_dp_set_sink_rates(intel_dp);
3808                 intel_dp_set_common_rates(intel_dp);
3809         }
3810
3811         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3812                 return false;
3813
3814         /*
3815          * Sink count can change between short pulse hpd hence
3816          * a member variable in intel_dp will track any changes
3817          * between short pulse interrupts.
3818          */
3819         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3820
3821         /*
3822          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3823          * a dongle is present but no display. Unless we require to know
3824          * if a dongle is present or not, we don't need to update
3825          * downstream port information. So, an early return here saves
3826          * time from performing other operations which are not required.
3827          */
3828         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3829                 return false;
3830
3831         if (!drm_dp_is_branch(intel_dp->dpcd))
3832                 return true; /* native DP sink */
3833
3834         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3835                 return true; /* no per-port downstream info */
3836
3837         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3838                              intel_dp->downstream_ports,
3839                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3840                 return false; /* downstream port status fetch failed */
3841
3842         return true;
3843 }
3844
3845 static bool
3846 intel_dp_can_mst(struct intel_dp *intel_dp)
3847 {
3848         u8 mstm_cap;
3849
3850         if (!i915_modparams.enable_dp_mst)
3851                 return false;
3852
3853         if (!intel_dp->can_mst)
3854                 return false;
3855
3856         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3857                 return false;
3858
3859         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3860                 return false;
3861
3862         return mstm_cap & DP_MST_CAP;
3863 }
3864
3865 static void
3866 intel_dp_configure_mst(struct intel_dp *intel_dp)
3867 {
3868         if (!i915_modparams.enable_dp_mst)
3869                 return;
3870
3871         if (!intel_dp->can_mst)
3872                 return;
3873
3874         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3875
3876         if (intel_dp->is_mst)
3877                 DRM_DEBUG_KMS("Sink is MST capable\n");
3878         else
3879                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3880
3881         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3882                                         intel_dp->is_mst);
3883 }
3884
3885 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp,
3886                                   struct intel_crtc_state *crtc_state, bool disable_wa)
3887 {
3888         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3889         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3891         u8 buf;
3892         int ret = 0;
3893         int count = 0;
3894         int attempts = 10;
3895
3896         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3897                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3898                 ret = -EIO;
3899                 goto out;
3900         }
3901
3902         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3903                                buf & ~DP_TEST_SINK_START) < 0) {
3904                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3905                 ret = -EIO;
3906                 goto out;
3907         }
3908
3909         do {
3910                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3911
3912                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3913                                       DP_TEST_SINK_MISC, &buf) < 0) {
3914                         ret = -EIO;
3915                         goto out;
3916                 }
3917                 count = buf & DP_TEST_COUNT_MASK;
3918         } while (--attempts && count);
3919
3920         if (attempts == 0) {
3921                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3922                 ret = -ETIMEDOUT;
3923         }
3924
3925  out:
3926         if (disable_wa)
3927                 hsw_enable_ips(crtc_state);
3928         return ret;
3929 }
3930
3931 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp,
3932                                    struct intel_crtc_state *crtc_state)
3933 {
3934         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3935         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3937         u8 buf;
3938         int ret;
3939
3940         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3941                 return -EIO;
3942
3943         if (!(buf & DP_TEST_CRC_SUPPORTED))
3944                 return -ENOTTY;
3945
3946         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3947                 return -EIO;
3948
3949         if (buf & DP_TEST_SINK_START) {
3950                 ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false);
3951                 if (ret)
3952                         return ret;
3953         }
3954
3955         hsw_disable_ips(crtc_state);
3956
3957         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3958                                buf | DP_TEST_SINK_START) < 0) {
3959                 hsw_enable_ips(crtc_state);
3960                 return -EIO;
3961         }
3962
3963         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3964         return 0;
3965 }
3966
3967 int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc)
3968 {
3969         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3970         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3972         u8 buf;
3973         int count, ret;
3974         int attempts = 6;
3975
3976         ret = intel_dp_sink_crc_start(intel_dp, crtc_state);
3977         if (ret)
3978                 return ret;
3979
3980         do {
3981                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3982
3983                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3984                                       DP_TEST_SINK_MISC, &buf) < 0) {
3985                         ret = -EIO;
3986                         goto stop;
3987                 }
3988                 count = buf & DP_TEST_COUNT_MASK;
3989
3990         } while (--attempts && count == 0);
3991
3992         if (attempts == 0) {
3993                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3994                 ret = -ETIMEDOUT;
3995                 goto stop;
3996         }
3997
3998         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3999                 ret = -EIO;
4000                 goto stop;
4001         }
4002
4003 stop:
4004         intel_dp_sink_crc_stop(intel_dp, crtc_state, true);
4005         return ret;
4006 }
4007
4008 static bool
4009 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4010 {
4011         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4012                                  sink_irq_vector) == 1;
4013 }
4014
4015 static bool
4016 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4017 {
4018         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4019                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4020                 DP_DPRX_ESI_LEN;
4021 }
4022
4023 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4024 {
4025         int status = 0;
4026         int test_link_rate;
4027         uint8_t test_lane_count, test_link_bw;
4028         /* (DP CTS 1.2)
4029          * 4.3.1.11
4030          */
4031         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4032         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4033                                    &test_lane_count);
4034
4035         if (status <= 0) {
4036                 DRM_DEBUG_KMS("Lane count read failed\n");
4037                 return DP_TEST_NAK;
4038         }
4039         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4040
4041         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4042                                    &test_link_bw);
4043         if (status <= 0) {
4044                 DRM_DEBUG_KMS("Link Rate read failed\n");
4045                 return DP_TEST_NAK;
4046         }
4047         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4048
4049         /* Validate the requested link rate and lane count */
4050         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4051                                         test_lane_count))
4052                 return DP_TEST_NAK;
4053
4054         intel_dp->compliance.test_lane_count = test_lane_count;
4055         intel_dp->compliance.test_link_rate = test_link_rate;
4056
4057         return DP_TEST_ACK;
4058 }
4059
4060 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4061 {
4062         uint8_t test_pattern;
4063         uint8_t test_misc;
4064         __be16 h_width, v_height;
4065         int status = 0;
4066
4067         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4068         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4069                                    &test_pattern);
4070         if (status <= 0) {
4071                 DRM_DEBUG_KMS("Test pattern read failed\n");
4072                 return DP_TEST_NAK;
4073         }
4074         if (test_pattern != DP_COLOR_RAMP)
4075                 return DP_TEST_NAK;
4076
4077         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4078                                   &h_width, 2);
4079         if (status <= 0) {
4080                 DRM_DEBUG_KMS("H Width read failed\n");
4081                 return DP_TEST_NAK;
4082         }
4083
4084         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4085                                   &v_height, 2);
4086         if (status <= 0) {
4087                 DRM_DEBUG_KMS("V Height read failed\n");
4088                 return DP_TEST_NAK;
4089         }
4090
4091         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4092                                    &test_misc);
4093         if (status <= 0) {
4094                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4095                 return DP_TEST_NAK;
4096         }
4097         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4098                 return DP_TEST_NAK;
4099         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4100                 return DP_TEST_NAK;
4101         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4102         case DP_TEST_BIT_DEPTH_6:
4103                 intel_dp->compliance.test_data.bpc = 6;
4104                 break;
4105         case DP_TEST_BIT_DEPTH_8:
4106                 intel_dp->compliance.test_data.bpc = 8;
4107                 break;
4108         default:
4109                 return DP_TEST_NAK;
4110         }
4111
4112         intel_dp->compliance.test_data.video_pattern = test_pattern;
4113         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4114         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4115         /* Set test active flag here so userspace doesn't interrupt things */
4116         intel_dp->compliance.test_active = 1;
4117
4118         return DP_TEST_ACK;
4119 }
4120
4121 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4122 {
4123         uint8_t test_result = DP_TEST_ACK;
4124         struct intel_connector *intel_connector = intel_dp->attached_connector;
4125         struct drm_connector *connector = &intel_connector->base;
4126
4127         if (intel_connector->detect_edid == NULL ||
4128             connector->edid_corrupt ||
4129             intel_dp->aux.i2c_defer_count > 6) {
4130                 /* Check EDID read for NACKs, DEFERs and corruption
4131                  * (DP CTS 1.2 Core r1.1)
4132                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4133                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4134                  *    4.2.2.6 : EDID corruption detected
4135                  * Use failsafe mode for all cases
4136                  */
4137                 if (intel_dp->aux.i2c_nack_count > 0 ||
4138                         intel_dp->aux.i2c_defer_count > 0)
4139                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4140                                       intel_dp->aux.i2c_nack_count,
4141                                       intel_dp->aux.i2c_defer_count);
4142                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4143         } else {
4144                 struct edid *block = intel_connector->detect_edid;
4145
4146                 /* We have to write the checksum
4147                  * of the last block read
4148                  */
4149                 block += intel_connector->detect_edid->extensions;
4150
4151                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4152                                        block->checksum) <= 0)
4153                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4154
4155                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4156                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4157         }
4158
4159         /* Set test active flag here so userspace doesn't interrupt things */
4160         intel_dp->compliance.test_active = 1;
4161
4162         return test_result;
4163 }
4164
4165 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4166 {
4167         uint8_t test_result = DP_TEST_NAK;
4168         return test_result;
4169 }
4170
4171 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4172 {
4173         uint8_t response = DP_TEST_NAK;
4174         uint8_t request = 0;
4175         int status;
4176
4177         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4178         if (status <= 0) {
4179                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4180                 goto update_status;
4181         }
4182
4183         switch (request) {
4184         case DP_TEST_LINK_TRAINING:
4185                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4186                 response = intel_dp_autotest_link_training(intel_dp);
4187                 break;
4188         case DP_TEST_LINK_VIDEO_PATTERN:
4189                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4190                 response = intel_dp_autotest_video_pattern(intel_dp);
4191                 break;
4192         case DP_TEST_LINK_EDID_READ:
4193                 DRM_DEBUG_KMS("EDID test requested\n");
4194                 response = intel_dp_autotest_edid(intel_dp);
4195                 break;
4196         case DP_TEST_LINK_PHY_TEST_PATTERN:
4197                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4198                 response = intel_dp_autotest_phy_pattern(intel_dp);
4199                 break;
4200         default:
4201                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4202                 break;
4203         }
4204
4205         if (response & DP_TEST_ACK)
4206                 intel_dp->compliance.test_type = request;
4207
4208 update_status:
4209         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4210         if (status <= 0)
4211                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4212 }
4213
4214 static int
4215 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4216 {
4217         bool bret;
4218
4219         if (intel_dp->is_mst) {
4220                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4221                 int ret = 0;
4222                 int retry;
4223                 bool handled;
4224                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4225 go_again:
4226                 if (bret == true) {
4227
4228                         /* check link status - esi[10] = 0x200c */
4229                         if (intel_dp->active_mst_links &&
4230                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4231                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4232                                 intel_dp_start_link_train(intel_dp);
4233                                 intel_dp_stop_link_train(intel_dp);
4234                         }
4235
4236                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4237                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4238
4239                         if (handled) {
4240                                 for (retry = 0; retry < 3; retry++) {
4241                                         int wret;
4242                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4243                                                                  DP_SINK_COUNT_ESI+1,
4244                                                                  &esi[1], 3);
4245                                         if (wret == 3) {
4246                                                 break;
4247                                         }
4248                                 }
4249
4250                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4251                                 if (bret == true) {
4252                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4253                                         goto go_again;
4254                                 }
4255                         } else
4256                                 ret = 0;
4257
4258                         return ret;
4259                 } else {
4260                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4261                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4262                         intel_dp->is_mst = false;
4263                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4264                         /* send a hotplug event */
4265                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4266                 }
4267         }
4268         return -EINVAL;
4269 }
4270
4271 static bool
4272 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4273 {
4274         u8 link_status[DP_LINK_STATUS_SIZE];
4275
4276         if (!intel_dp->link_trained)
4277                 return false;
4278
4279         if (!intel_dp_get_link_status(intel_dp, link_status))
4280                 return false;
4281
4282         /*
4283          * Validate the cached values of intel_dp->link_rate and
4284          * intel_dp->lane_count before attempting to retrain.
4285          */
4286         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4287                                         intel_dp->lane_count))
4288                 return false;
4289
4290         /* Retrain if Channel EQ or CR not ok */
4291         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4292 }
4293
4294 /*
4295  * If display is now connected check links status,
4296  * there has been known issues of link loss triggering
4297  * long pulse.
4298  *
4299  * Some sinks (eg. ASUS PB287Q) seem to perform some
4300  * weird HPD ping pong during modesets. So we can apparently
4301  * end up with HPD going low during a modeset, and then
4302  * going back up soon after. And once that happens we must
4303  * retrain the link to get a picture. That's in case no
4304  * userspace component reacted to intermittent HPD dip.
4305  */
4306 int intel_dp_retrain_link(struct intel_encoder *encoder,
4307                           struct drm_modeset_acquire_ctx *ctx)
4308 {
4309         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4310         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4311         struct intel_connector *connector = intel_dp->attached_connector;
4312         struct drm_connector_state *conn_state;
4313         struct intel_crtc_state *crtc_state;
4314         struct intel_crtc *crtc;
4315         int ret;
4316
4317         /* FIXME handle the MST connectors as well */
4318
4319         if (!connector || connector->base.status != connector_status_connected)
4320                 return 0;
4321
4322         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4323                                ctx);
4324         if (ret)
4325                 return ret;
4326
4327         conn_state = connector->base.state;
4328
4329         crtc = to_intel_crtc(conn_state->crtc);
4330         if (!crtc)
4331                 return 0;
4332
4333         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4334         if (ret)
4335                 return ret;
4336
4337         crtc_state = to_intel_crtc_state(crtc->base.state);
4338
4339         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4340
4341         if (!crtc_state->base.active)
4342                 return 0;
4343
4344         if (conn_state->commit &&
4345             !try_wait_for_completion(&conn_state->commit->hw_done))
4346                 return 0;
4347
4348         if (!intel_dp_needs_link_retrain(intel_dp))
4349                 return 0;
4350
4351         /* Suppress underruns caused by re-training */
4352         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4353         if (crtc->config->has_pch_encoder)
4354                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4355                                                       intel_crtc_pch_transcoder(crtc), false);
4356
4357         intel_dp_start_link_train(intel_dp);
4358         intel_dp_stop_link_train(intel_dp);
4359
4360         /* Keep underrun reporting disabled until things are stable */
4361         intel_wait_for_vblank(dev_priv, crtc->pipe);
4362
4363         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4364         if (crtc->config->has_pch_encoder)
4365                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4366                                                       intel_crtc_pch_transcoder(crtc), true);
4367
4368         return 0;
4369 }
4370
4371 /*
4372  * If display is now connected check links status,
4373  * there has been known issues of link loss triggering
4374  * long pulse.
4375  *
4376  * Some sinks (eg. ASUS PB287Q) seem to perform some
4377  * weird HPD ping pong during modesets. So we can apparently
4378  * end up with HPD going low during a modeset, and then
4379  * going back up soon after. And once that happens we must
4380  * retrain the link to get a picture. That's in case no
4381  * userspace component reacted to intermittent HPD dip.
4382  */
4383 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4384                              struct intel_connector *connector)
4385 {
4386         struct drm_modeset_acquire_ctx ctx;
4387         bool changed;
4388         int ret;
4389
4390         changed = intel_encoder_hotplug(encoder, connector);
4391
4392         drm_modeset_acquire_init(&ctx, 0);
4393
4394         for (;;) {
4395                 ret = intel_dp_retrain_link(encoder, &ctx);
4396
4397                 if (ret == -EDEADLK) {
4398                         drm_modeset_backoff(&ctx);
4399                         continue;
4400                 }
4401
4402                 break;
4403         }
4404
4405         drm_modeset_drop_locks(&ctx);
4406         drm_modeset_acquire_fini(&ctx);
4407         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4408
4409         return changed;
4410 }
4411
4412 /*
4413  * According to DP spec
4414  * 5.1.2:
4415  *  1. Read DPCD
4416  *  2. Configure link according to Receiver Capabilities
4417  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4418  *  4. Check link status on receipt of hot-plug interrupt
4419  *
4420  * intel_dp_short_pulse -  handles short pulse interrupts
4421  * when full detection is not required.
4422  * Returns %true if short pulse is handled and full detection
4423  * is NOT required and %false otherwise.
4424  */
4425 static bool
4426 intel_dp_short_pulse(struct intel_dp *intel_dp)
4427 {
4428         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4429         u8 sink_irq_vector = 0;
4430         u8 old_sink_count = intel_dp->sink_count;
4431         bool ret;
4432
4433         /*
4434          * Clearing compliance test variables to allow capturing
4435          * of values for next automated test request.
4436          */
4437         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4438
4439         /*
4440          * Now read the DPCD to see if it's actually running
4441          * If the current value of sink count doesn't match with
4442          * the value that was stored earlier or dpcd read failed
4443          * we need to do full detection
4444          */
4445         ret = intel_dp_get_dpcd(intel_dp);
4446
4447         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4448                 /* No need to proceed if we are going to do full detect */
4449                 return false;
4450         }
4451
4452         /* Try to read the source of the interrupt */
4453         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4454             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4455             sink_irq_vector != 0) {
4456                 /* Clear interrupt source */
4457                 drm_dp_dpcd_writeb(&intel_dp->aux,
4458                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4459                                    sink_irq_vector);
4460
4461                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4462                         intel_dp_handle_test_request(intel_dp);
4463                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4464                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4465         }
4466
4467         /* defer to the hotplug work for link retraining if needed */
4468         if (intel_dp_needs_link_retrain(intel_dp))
4469                 return false;
4470
4471         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4472                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4473                 /* Send a Hotplug Uevent to userspace to start modeset */
4474                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4475         }
4476
4477         return true;
4478 }
4479
4480 /* XXX this is probably wrong for multiple downstream ports */
4481 static enum drm_connector_status
4482 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4483 {
4484         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4485         uint8_t *dpcd = intel_dp->dpcd;
4486         uint8_t type;
4487
4488         if (lspcon->active)
4489                 lspcon_resume(lspcon);
4490
4491         if (!intel_dp_get_dpcd(intel_dp))
4492                 return connector_status_disconnected;
4493
4494         if (intel_dp_is_edp(intel_dp))
4495                 return connector_status_connected;
4496
4497         /* if there's no downstream port, we're done */
4498         if (!drm_dp_is_branch(dpcd))
4499                 return connector_status_connected;
4500
4501         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4502         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4503             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4504
4505                 return intel_dp->sink_count ?
4506                 connector_status_connected : connector_status_disconnected;
4507         }
4508
4509         if (intel_dp_can_mst(intel_dp))
4510                 return connector_status_connected;
4511
4512         /* If no HPD, poke DDC gently */
4513         if (drm_probe_ddc(&intel_dp->aux.ddc))
4514                 return connector_status_connected;
4515
4516         /* Well we tried, say unknown for unreliable port types */
4517         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4518                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4519                 if (type == DP_DS_PORT_TYPE_VGA ||
4520                     type == DP_DS_PORT_TYPE_NON_EDID)
4521                         return connector_status_unknown;
4522         } else {
4523                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4524                         DP_DWN_STRM_PORT_TYPE_MASK;
4525                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4526                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4527                         return connector_status_unknown;
4528         }
4529
4530         /* Anything else is out of spec, warn and ignore */
4531         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4532         return connector_status_disconnected;
4533 }
4534
4535 static enum drm_connector_status
4536 edp_detect(struct intel_dp *intel_dp)
4537 {
4538         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4539         enum drm_connector_status status;
4540
4541         status = intel_panel_detect(dev_priv);
4542         if (status == connector_status_unknown)
4543                 status = connector_status_connected;
4544
4545         return status;
4546 }
4547
4548 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4549 {
4550         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4551         u32 bit;
4552
4553         switch (encoder->hpd_pin) {
4554         case HPD_PORT_B:
4555                 bit = SDE_PORTB_HOTPLUG;
4556                 break;
4557         case HPD_PORT_C:
4558                 bit = SDE_PORTC_HOTPLUG;
4559                 break;
4560         case HPD_PORT_D:
4561                 bit = SDE_PORTD_HOTPLUG;
4562                 break;
4563         default:
4564                 MISSING_CASE(encoder->hpd_pin);
4565                 return false;
4566         }
4567
4568         return I915_READ(SDEISR) & bit;
4569 }
4570
4571 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4572 {
4573         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4574         u32 bit;
4575
4576         switch (encoder->hpd_pin) {
4577         case HPD_PORT_B:
4578                 bit = SDE_PORTB_HOTPLUG_CPT;
4579                 break;
4580         case HPD_PORT_C:
4581                 bit = SDE_PORTC_HOTPLUG_CPT;
4582                 break;
4583         case HPD_PORT_D:
4584                 bit = SDE_PORTD_HOTPLUG_CPT;
4585                 break;
4586         default:
4587                 MISSING_CASE(encoder->hpd_pin);
4588                 return false;
4589         }
4590
4591         return I915_READ(SDEISR) & bit;
4592 }
4593
4594 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4595 {
4596         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4597         u32 bit;
4598
4599         switch (encoder->hpd_pin) {
4600         case HPD_PORT_A:
4601                 bit = SDE_PORTA_HOTPLUG_SPT;
4602                 break;
4603         case HPD_PORT_E:
4604                 bit = SDE_PORTE_HOTPLUG_SPT;
4605                 break;
4606         default:
4607                 return cpt_digital_port_connected(encoder);
4608         }
4609
4610         return I915_READ(SDEISR) & bit;
4611 }
4612
4613 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4614 {
4615         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4616         u32 bit;
4617
4618         switch (encoder->hpd_pin) {
4619         case HPD_PORT_B:
4620                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4621                 break;
4622         case HPD_PORT_C:
4623                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4624                 break;
4625         case HPD_PORT_D:
4626                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4627                 break;
4628         default:
4629                 MISSING_CASE(encoder->hpd_pin);
4630                 return false;
4631         }
4632
4633         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4634 }
4635
4636 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4637 {
4638         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4639         u32 bit;
4640
4641         switch (encoder->hpd_pin) {
4642         case HPD_PORT_B:
4643                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4644                 break;
4645         case HPD_PORT_C:
4646                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4647                 break;
4648         case HPD_PORT_D:
4649                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4650                 break;
4651         default:
4652                 MISSING_CASE(encoder->hpd_pin);
4653                 return false;
4654         }
4655
4656         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4657 }
4658
4659 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4660 {
4661         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4662
4663         if (encoder->hpd_pin == HPD_PORT_A)
4664                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4665         else
4666                 return ibx_digital_port_connected(encoder);
4667 }
4668
4669 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4670 {
4671         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4672
4673         if (encoder->hpd_pin == HPD_PORT_A)
4674                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4675         else
4676                 return cpt_digital_port_connected(encoder);
4677 }
4678
4679 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4680 {
4681         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4682
4683         if (encoder->hpd_pin == HPD_PORT_A)
4684                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4685         else
4686                 return cpt_digital_port_connected(encoder);
4687 }
4688
4689 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4690 {
4691         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4692
4693         if (encoder->hpd_pin == HPD_PORT_A)
4694                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4695         else
4696                 return cpt_digital_port_connected(encoder);
4697 }
4698
4699 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4700 {
4701         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4702         u32 bit;
4703
4704         switch (encoder->hpd_pin) {
4705         case HPD_PORT_A:
4706                 bit = BXT_DE_PORT_HP_DDIA;
4707                 break;
4708         case HPD_PORT_B:
4709                 bit = BXT_DE_PORT_HP_DDIB;
4710                 break;
4711         case HPD_PORT_C:
4712                 bit = BXT_DE_PORT_HP_DDIC;
4713                 break;
4714         default:
4715                 MISSING_CASE(encoder->hpd_pin);
4716                 return false;
4717         }
4718
4719         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4720 }
4721
4722 /*
4723  * intel_digital_port_connected - is the specified port connected?
4724  * @encoder: intel_encoder
4725  *
4726  * Return %true if port is connected, %false otherwise.
4727  */
4728 bool intel_digital_port_connected(struct intel_encoder *encoder)
4729 {
4730         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4731
4732         if (HAS_GMCH_DISPLAY(dev_priv)) {
4733                 if (IS_GM45(dev_priv))
4734                         return gm45_digital_port_connected(encoder);
4735                 else
4736                         return g4x_digital_port_connected(encoder);
4737         }
4738
4739         if (IS_GEN5(dev_priv))
4740                 return ilk_digital_port_connected(encoder);
4741         else if (IS_GEN6(dev_priv))
4742                 return snb_digital_port_connected(encoder);
4743         else if (IS_GEN7(dev_priv))
4744                 return ivb_digital_port_connected(encoder);
4745         else if (IS_GEN8(dev_priv))
4746                 return bdw_digital_port_connected(encoder);
4747         else if (IS_GEN9_LP(dev_priv))
4748                 return bxt_digital_port_connected(encoder);
4749         else
4750                 return spt_digital_port_connected(encoder);
4751 }
4752
4753 static struct edid *
4754 intel_dp_get_edid(struct intel_dp *intel_dp)
4755 {
4756         struct intel_connector *intel_connector = intel_dp->attached_connector;
4757
4758         /* use cached edid if we have one */
4759         if (intel_connector->edid) {
4760                 /* invalid edid */
4761                 if (IS_ERR(intel_connector->edid))
4762                         return NULL;
4763
4764                 return drm_edid_duplicate(intel_connector->edid);
4765         } else
4766                 return drm_get_edid(&intel_connector->base,
4767                                     &intel_dp->aux.ddc);
4768 }
4769
4770 static void
4771 intel_dp_set_edid(struct intel_dp *intel_dp)
4772 {
4773         struct intel_connector *intel_connector = intel_dp->attached_connector;
4774         struct edid *edid;
4775
4776         intel_dp_unset_edid(intel_dp);
4777         edid = intel_dp_get_edid(intel_dp);
4778         intel_connector->detect_edid = edid;
4779
4780         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4781 }
4782
4783 static void
4784 intel_dp_unset_edid(struct intel_dp *intel_dp)
4785 {
4786         struct intel_connector *intel_connector = intel_dp->attached_connector;
4787
4788         kfree(intel_connector->detect_edid);
4789         intel_connector->detect_edid = NULL;
4790
4791         intel_dp->has_audio = false;
4792 }
4793
4794 static int
4795 intel_dp_long_pulse(struct intel_connector *connector)
4796 {
4797         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4798         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4799         enum drm_connector_status status;
4800         u8 sink_irq_vector = 0;
4801
4802         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4803
4804         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4805
4806         /* Can't disconnect eDP, but you can close the lid... */
4807         if (intel_dp_is_edp(intel_dp))
4808                 status = edp_detect(intel_dp);
4809         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4810                 status = intel_dp_detect_dpcd(intel_dp);
4811         else
4812                 status = connector_status_disconnected;
4813
4814         if (status == connector_status_disconnected) {
4815                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4816
4817                 if (intel_dp->is_mst) {
4818                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4819                                       intel_dp->is_mst,
4820                                       intel_dp->mst_mgr.mst_state);
4821                         intel_dp->is_mst = false;
4822                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4823                                                         intel_dp->is_mst);
4824                 }
4825
4826                 goto out;
4827         }
4828
4829         if (intel_dp->reset_link_params) {
4830                 /* Initial max link lane count */
4831                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4832
4833                 /* Initial max link rate */
4834                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4835
4836                 intel_dp->reset_link_params = false;
4837         }
4838
4839         intel_dp_print_rates(intel_dp);
4840
4841         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4842                          drm_dp_is_branch(intel_dp->dpcd));
4843
4844         intel_dp_configure_mst(intel_dp);
4845
4846         if (intel_dp->is_mst) {
4847                 /*
4848                  * If we are in MST mode then this connector
4849                  * won't appear connected or have anything
4850                  * with EDID on it
4851                  */
4852                 status = connector_status_disconnected;
4853                 goto out;
4854         }
4855
4856         /*
4857          * Clearing NACK and defer counts to get their exact values
4858          * while reading EDID which are required by Compliance tests
4859          * 4.2.2.4 and 4.2.2.5
4860          */
4861         intel_dp->aux.i2c_nack_count = 0;
4862         intel_dp->aux.i2c_defer_count = 0;
4863
4864         intel_dp_set_edid(intel_dp);
4865         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4866                 status = connector_status_connected;
4867         intel_dp->detect_done = true;
4868
4869         /* Try to read the source of the interrupt */
4870         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4871             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4872             sink_irq_vector != 0) {
4873                 /* Clear interrupt source */
4874                 drm_dp_dpcd_writeb(&intel_dp->aux,
4875                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4876                                    sink_irq_vector);
4877
4878                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4879                         intel_dp_handle_test_request(intel_dp);
4880                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4881                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4882         }
4883
4884 out:
4885         if (status != connector_status_connected && !intel_dp->is_mst)
4886                 intel_dp_unset_edid(intel_dp);
4887
4888         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4889         return status;
4890 }
4891
4892 static int
4893 intel_dp_detect(struct drm_connector *connector,
4894                 struct drm_modeset_acquire_ctx *ctx,
4895                 bool force)
4896 {
4897         struct intel_dp *intel_dp = intel_attached_dp(connector);
4898         int status = connector->status;
4899
4900         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4901                       connector->base.id, connector->name);
4902
4903         /* If full detect is not performed yet, do a full detect */
4904         if (!intel_dp->detect_done) {
4905                 struct drm_crtc *crtc;
4906                 int ret;
4907
4908                 crtc = connector->state->crtc;
4909                 if (crtc) {
4910                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4911                         if (ret)
4912                                 return ret;
4913                 }
4914
4915                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4916         }
4917
4918         intel_dp->detect_done = false;
4919
4920         return status;
4921 }
4922
4923 static void
4924 intel_dp_force(struct drm_connector *connector)
4925 {
4926         struct intel_dp *intel_dp = intel_attached_dp(connector);
4927         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4928         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4929
4930         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4931                       connector->base.id, connector->name);
4932         intel_dp_unset_edid(intel_dp);
4933
4934         if (connector->status != connector_status_connected)
4935                 return;
4936
4937         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4938
4939         intel_dp_set_edid(intel_dp);
4940
4941         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4942 }
4943
4944 static int intel_dp_get_modes(struct drm_connector *connector)
4945 {
4946         struct intel_connector *intel_connector = to_intel_connector(connector);
4947         struct edid *edid;
4948
4949         edid = intel_connector->detect_edid;
4950         if (edid) {
4951                 int ret = intel_connector_update_modes(connector, edid);
4952                 if (ret)
4953                         return ret;
4954         }
4955
4956         /* if eDP has no EDID, fall back to fixed mode */
4957         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4958             intel_connector->panel.fixed_mode) {
4959                 struct drm_display_mode *mode;
4960
4961                 mode = drm_mode_duplicate(connector->dev,
4962                                           intel_connector->panel.fixed_mode);
4963                 if (mode) {
4964                         drm_mode_probed_add(connector, mode);
4965                         return 1;
4966                 }
4967         }
4968
4969         return 0;
4970 }
4971
4972 static int
4973 intel_dp_connector_register(struct drm_connector *connector)
4974 {
4975         struct intel_dp *intel_dp = intel_attached_dp(connector);
4976         int ret;
4977
4978         ret = intel_connector_register(connector);
4979         if (ret)
4980                 return ret;
4981
4982         i915_debugfs_connector_add(connector);
4983
4984         DRM_DEBUG_KMS("registering %s bus for %s\n",
4985                       intel_dp->aux.name, connector->kdev->kobj.name);
4986
4987         intel_dp->aux.dev = connector->kdev;
4988         return drm_dp_aux_register(&intel_dp->aux);
4989 }
4990
4991 static void
4992 intel_dp_connector_unregister(struct drm_connector *connector)
4993 {
4994         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4995         intel_connector_unregister(connector);
4996 }
4997
4998 static void
4999 intel_dp_connector_destroy(struct drm_connector *connector)
5000 {
5001         struct intel_connector *intel_connector = to_intel_connector(connector);
5002
5003         kfree(intel_connector->detect_edid);
5004
5005         if (!IS_ERR_OR_NULL(intel_connector->edid))
5006                 kfree(intel_connector->edid);
5007
5008         /*
5009          * Can't call intel_dp_is_edp() since the encoder may have been
5010          * destroyed already.
5011          */
5012         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5013                 intel_panel_fini(&intel_connector->panel);
5014
5015         drm_connector_cleanup(connector);
5016         kfree(connector);
5017 }
5018
5019 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5020 {
5021         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5022         struct intel_dp *intel_dp = &intel_dig_port->dp;
5023
5024         intel_dp_mst_encoder_cleanup(intel_dig_port);
5025         if (intel_dp_is_edp(intel_dp)) {
5026                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5027                 /*
5028                  * vdd might still be enabled do to the delayed vdd off.
5029                  * Make sure vdd is actually turned off here.
5030                  */
5031                 pps_lock(intel_dp);
5032                 edp_panel_vdd_off_sync(intel_dp);
5033                 pps_unlock(intel_dp);
5034
5035                 if (intel_dp->edp_notifier.notifier_call) {
5036                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5037                         intel_dp->edp_notifier.notifier_call = NULL;
5038                 }
5039         }
5040
5041         intel_dp_aux_fini(intel_dp);
5042
5043         drm_encoder_cleanup(encoder);
5044         kfree(intel_dig_port);
5045 }
5046
5047 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5048 {
5049         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5050
5051         if (!intel_dp_is_edp(intel_dp))
5052                 return;
5053
5054         /*
5055          * vdd might still be enabled do to the delayed vdd off.
5056          * Make sure vdd is actually turned off here.
5057          */
5058         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5059         pps_lock(intel_dp);
5060         edp_panel_vdd_off_sync(intel_dp);
5061         pps_unlock(intel_dp);
5062 }
5063
5064 static
5065 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5066                                 u8 *an)
5067 {
5068         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5069         static const struct drm_dp_aux_msg msg = {
5070                 .request = DP_AUX_NATIVE_WRITE,
5071                 .address = DP_AUX_HDCP_AKSV,
5072                 .size = DRM_HDCP_KSV_LEN,
5073         };
5074         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5075         ssize_t dpcd_ret;
5076         int ret;
5077
5078         /* Output An first, that's easy */
5079         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5080                                      an, DRM_HDCP_AN_LEN);
5081         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5082                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5083                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5084         }
5085
5086         /*
5087          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5088          * order to get it on the wire, we need to create the AUX header as if
5089          * we were writing the data, and then tickle the hardware to output the
5090          * data once the header is sent out.
5091          */
5092         intel_dp_aux_header(txbuf, &msg);
5093
5094         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5095                                 rxbuf, sizeof(rxbuf),
5096                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5097         if (ret < 0) {
5098                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5099                 return ret;
5100         } else if (ret == 0) {
5101                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5102                 return -EIO;
5103         }
5104
5105         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5106         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5107 }
5108
5109 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5110                                    u8 *bksv)
5111 {
5112         ssize_t ret;
5113         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5114                                DRM_HDCP_KSV_LEN);
5115         if (ret != DRM_HDCP_KSV_LEN) {
5116                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5117                 return ret >= 0 ? -EIO : ret;
5118         }
5119         return 0;
5120 }
5121
5122 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5123                                       u8 *bstatus)
5124 {
5125         ssize_t ret;
5126         /*
5127          * For some reason the HDMI and DP HDCP specs call this register
5128          * definition by different names. In the HDMI spec, it's called BSTATUS,
5129          * but in DP it's called BINFO.
5130          */
5131         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5132                                bstatus, DRM_HDCP_BSTATUS_LEN);
5133         if (ret != DRM_HDCP_BSTATUS_LEN) {
5134                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5135                 return ret >= 0 ? -EIO : ret;
5136         }
5137         return 0;
5138 }
5139
5140 static
5141 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5142                              u8 *bcaps)
5143 {
5144         ssize_t ret;
5145
5146         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5147                                bcaps, 1);
5148         if (ret != 1) {
5149                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5150                 return ret >= 0 ? -EIO : ret;
5151         }
5152
5153         return 0;
5154 }
5155
5156 static
5157 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5158                                    bool *repeater_present)
5159 {
5160         ssize_t ret;
5161         u8 bcaps;
5162
5163         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5164         if (ret)
5165                 return ret;
5166
5167         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5168         return 0;
5169 }
5170
5171 static
5172 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5173                                 u8 *ri_prime)
5174 {
5175         ssize_t ret;
5176         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5177                                ri_prime, DRM_HDCP_RI_LEN);
5178         if (ret != DRM_HDCP_RI_LEN) {
5179                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5180                 return ret >= 0 ? -EIO : ret;
5181         }
5182         return 0;
5183 }
5184
5185 static
5186 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5187                                  bool *ksv_ready)
5188 {
5189         ssize_t ret;
5190         u8 bstatus;
5191         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5192                                &bstatus, 1);
5193         if (ret != 1) {
5194                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5195                 return ret >= 0 ? -EIO : ret;
5196         }
5197         *ksv_ready = bstatus & DP_BSTATUS_READY;
5198         return 0;
5199 }
5200
5201 static
5202 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5203                                 int num_downstream, u8 *ksv_fifo)
5204 {
5205         ssize_t ret;
5206         int i;
5207
5208         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5209         for (i = 0; i < num_downstream; i += 3) {
5210                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5211                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5212                                        DP_AUX_HDCP_KSV_FIFO,
5213                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5214                                        len);
5215                 if (ret != len) {
5216                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5217                                   ret);
5218                         return ret >= 0 ? -EIO : ret;
5219                 }
5220         }
5221         return 0;
5222 }
5223
5224 static
5225 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5226                                     int i, u32 *part)
5227 {
5228         ssize_t ret;
5229
5230         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5231                 return -EINVAL;
5232
5233         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5234                                DP_AUX_HDCP_V_PRIME(i), part,
5235                                DRM_HDCP_V_PRIME_PART_LEN);
5236         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5237                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5238                 return ret >= 0 ? -EIO : ret;
5239         }
5240         return 0;
5241 }
5242
5243 static
5244 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5245                                     bool enable)
5246 {
5247         /* Not used for single stream DisplayPort setups */
5248         return 0;
5249 }
5250
5251 static
5252 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5253 {
5254         ssize_t ret;
5255         u8 bstatus;
5256
5257         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5258                                &bstatus, 1);
5259         if (ret != 1) {
5260                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5261                 return false;
5262         }
5263
5264         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5265 }
5266
5267 static
5268 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5269                           bool *hdcp_capable)
5270 {
5271         ssize_t ret;
5272         u8 bcaps;
5273
5274         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5275         if (ret)
5276                 return ret;
5277
5278         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5279         return 0;
5280 }
5281
5282 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5283         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5284         .read_bksv = intel_dp_hdcp_read_bksv,
5285         .read_bstatus = intel_dp_hdcp_read_bstatus,
5286         .repeater_present = intel_dp_hdcp_repeater_present,
5287         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5288         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5289         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5290         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5291         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5292         .check_link = intel_dp_hdcp_check_link,
5293         .hdcp_capable = intel_dp_hdcp_capable,
5294 };
5295
5296 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5297 {
5298         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5299
5300         lockdep_assert_held(&dev_priv->pps_mutex);
5301
5302         if (!edp_have_panel_vdd(intel_dp))
5303                 return;
5304
5305         /*
5306          * The VDD bit needs a power domain reference, so if the bit is
5307          * already enabled when we boot or resume, grab this reference and
5308          * schedule a vdd off, so we don't hold on to the reference
5309          * indefinitely.
5310          */
5311         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5312         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5313
5314         edp_panel_vdd_schedule_off(intel_dp);
5315 }
5316
5317 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5318 {
5319         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5320
5321         if ((intel_dp->DP & DP_PORT_EN) == 0)
5322                 return INVALID_PIPE;
5323
5324         if (IS_CHERRYVIEW(dev_priv))
5325                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5326         else
5327                 return PORT_TO_PIPE(intel_dp->DP);
5328 }
5329
5330 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5331 {
5332         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5333         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5334         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5335
5336         if (!HAS_DDI(dev_priv))
5337                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5338
5339         if (lspcon->active)
5340                 lspcon_resume(lspcon);
5341
5342         intel_dp->reset_link_params = true;
5343
5344         pps_lock(intel_dp);
5345
5346         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5347                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5348
5349         if (intel_dp_is_edp(intel_dp)) {
5350                 /* Reinit the power sequencer, in case BIOS did something with it. */
5351                 intel_dp_pps_init(intel_dp);
5352                 intel_edp_panel_vdd_sanitize(intel_dp);
5353         }
5354
5355         pps_unlock(intel_dp);
5356 }
5357
5358 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5359         .force = intel_dp_force,
5360         .fill_modes = drm_helper_probe_single_connector_modes,
5361         .atomic_get_property = intel_digital_connector_atomic_get_property,
5362         .atomic_set_property = intel_digital_connector_atomic_set_property,
5363         .late_register = intel_dp_connector_register,
5364         .early_unregister = intel_dp_connector_unregister,
5365         .destroy = intel_dp_connector_destroy,
5366         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5367         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5368 };
5369
5370 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5371         .detect_ctx = intel_dp_detect,
5372         .get_modes = intel_dp_get_modes,
5373         .mode_valid = intel_dp_mode_valid,
5374         .atomic_check = intel_digital_connector_atomic_check,
5375 };
5376
5377 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5378         .reset = intel_dp_encoder_reset,
5379         .destroy = intel_dp_encoder_destroy,
5380 };
5381
5382 enum irqreturn
5383 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5384 {
5385         struct intel_dp *intel_dp = &intel_dig_port->dp;
5386         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5387         enum irqreturn ret = IRQ_NONE;
5388
5389         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5390                 /*
5391                  * vdd off can generate a long pulse on eDP which
5392                  * would require vdd on to handle it, and thus we
5393                  * would end up in an endless cycle of
5394                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5395                  */
5396                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5397                               port_name(intel_dig_port->base.port));
5398                 return IRQ_HANDLED;
5399         }
5400
5401         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5402                       port_name(intel_dig_port->base.port),
5403                       long_hpd ? "long" : "short");
5404
5405         if (long_hpd) {
5406                 intel_dp->reset_link_params = true;
5407                 intel_dp->detect_done = false;
5408                 return IRQ_NONE;
5409         }
5410
5411         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5412
5413         if (intel_dp->is_mst) {
5414                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5415                         /*
5416                          * If we were in MST mode, and device is not
5417                          * there, get out of MST mode
5418                          */
5419                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5420                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5421                         intel_dp->is_mst = false;
5422                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5423                                                         intel_dp->is_mst);
5424                         intel_dp->detect_done = false;
5425                         goto put_power;
5426                 }
5427         }
5428
5429         if (!intel_dp->is_mst) {
5430                 bool handled;
5431
5432                 handled = intel_dp_short_pulse(intel_dp);
5433
5434                 /* Short pulse can signify loss of hdcp authentication */
5435                 intel_hdcp_check_link(intel_dp->attached_connector);
5436
5437                 if (!handled) {
5438                         intel_dp->detect_done = false;
5439                         goto put_power;
5440                 }
5441         }
5442
5443         ret = IRQ_HANDLED;
5444
5445 put_power:
5446         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5447
5448         return ret;
5449 }
5450
5451 /* check the VBT to see whether the eDP is on another port */
5452 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5453 {
5454         /*
5455          * eDP not supported on g4x. so bail out early just
5456          * for a bit extra safety in case the VBT is bonkers.
5457          */
5458         if (INTEL_GEN(dev_priv) < 5)
5459                 return false;
5460
5461         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5462                 return true;
5463
5464         return intel_bios_is_port_edp(dev_priv, port);
5465 }
5466
5467 static void
5468 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5469 {
5470         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5471         enum port port = dp_to_dig_port(intel_dp)->base.port;
5472
5473         if (!IS_G4X(dev_priv) && port != PORT_A)
5474                 intel_attach_force_audio_property(connector);
5475
5476         intel_attach_broadcast_rgb_property(connector);
5477
5478         if (intel_dp_is_edp(intel_dp)) {
5479                 u32 allowed_scalers;
5480
5481                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5482                 if (!HAS_GMCH_DISPLAY(dev_priv))
5483                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5484
5485                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5486
5487                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5488
5489         }
5490 }
5491
5492 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5493 {
5494         intel_dp->panel_power_off_time = ktime_get_boottime();
5495         intel_dp->last_power_on = jiffies;
5496         intel_dp->last_backlight_off = jiffies;
5497 }
5498
5499 static void
5500 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5501 {
5502         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5503         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5504         struct pps_registers regs;
5505
5506         intel_pps_get_registers(intel_dp, &regs);
5507
5508         /* Workaround: Need to write PP_CONTROL with the unlock key as
5509          * the very first thing. */
5510         pp_ctl = ironlake_get_pp_control(intel_dp);
5511
5512         pp_on = I915_READ(regs.pp_on);
5513         pp_off = I915_READ(regs.pp_off);
5514         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5515             !HAS_PCH_ICP(dev_priv)) {
5516                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5517                 pp_div = I915_READ(regs.pp_div);
5518         }
5519
5520         /* Pull timing values out of registers */
5521         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5522                      PANEL_POWER_UP_DELAY_SHIFT;
5523
5524         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5525                   PANEL_LIGHT_ON_DELAY_SHIFT;
5526
5527         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5528                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5529
5530         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5531                    PANEL_POWER_DOWN_DELAY_SHIFT;
5532
5533         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5534             HAS_PCH_ICP(dev_priv)) {
5535                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5536                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5537         } else {
5538                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5539                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5540         }
5541 }
5542
5543 static void
5544 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5545 {
5546         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5547                       state_name,
5548                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5549 }
5550
5551 static void
5552 intel_pps_verify_state(struct intel_dp *intel_dp)
5553 {
5554         struct edp_power_seq hw;
5555         struct edp_power_seq *sw = &intel_dp->pps_delays;
5556
5557         intel_pps_readout_hw_state(intel_dp, &hw);
5558
5559         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5560             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5561                 DRM_ERROR("PPS state mismatch\n");
5562                 intel_pps_dump_state("sw", sw);
5563                 intel_pps_dump_state("hw", &hw);
5564         }
5565 }
5566
5567 static void
5568 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5569 {
5570         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5571         struct edp_power_seq cur, vbt, spec,
5572                 *final = &intel_dp->pps_delays;
5573
5574         lockdep_assert_held(&dev_priv->pps_mutex);
5575
5576         /* already initialized? */
5577         if (final->t11_t12 != 0)
5578                 return;
5579
5580         intel_pps_readout_hw_state(intel_dp, &cur);
5581
5582         intel_pps_dump_state("cur", &cur);
5583
5584         vbt = dev_priv->vbt.edp.pps;
5585         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5586          * of 500ms appears to be too short. Ocassionally the panel
5587          * just fails to power back on. Increasing the delay to 800ms
5588          * seems sufficient to avoid this problem.
5589          */
5590         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5591                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5592                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5593                               vbt.t11_t12);
5594         }
5595         /* T11_T12 delay is special and actually in units of 100ms, but zero
5596          * based in the hw (so we need to add 100 ms). But the sw vbt
5597          * table multiplies it with 1000 to make it in units of 100usec,
5598          * too. */
5599         vbt.t11_t12 += 100 * 10;
5600
5601         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5602          * our hw here, which are all in 100usec. */
5603         spec.t1_t3 = 210 * 10;
5604         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5605         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5606         spec.t10 = 500 * 10;
5607         /* This one is special and actually in units of 100ms, but zero
5608          * based in the hw (so we need to add 100 ms). But the sw vbt
5609          * table multiplies it with 1000 to make it in units of 100usec,
5610          * too. */
5611         spec.t11_t12 = (510 + 100) * 10;
5612
5613         intel_pps_dump_state("vbt", &vbt);
5614
5615         /* Use the max of the register settings and vbt. If both are
5616          * unset, fall back to the spec limits. */
5617 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5618                                        spec.field : \
5619                                        max(cur.field, vbt.field))
5620         assign_final(t1_t3);
5621         assign_final(t8);
5622         assign_final(t9);
5623         assign_final(t10);
5624         assign_final(t11_t12);
5625 #undef assign_final
5626
5627 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5628         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5629         intel_dp->backlight_on_delay = get_delay(t8);
5630         intel_dp->backlight_off_delay = get_delay(t9);
5631         intel_dp->panel_power_down_delay = get_delay(t10);
5632         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5633 #undef get_delay
5634
5635         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5636                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5637                       intel_dp->panel_power_cycle_delay);
5638
5639         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5640                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5641
5642         /*
5643          * We override the HW backlight delays to 1 because we do manual waits
5644          * on them. For T8, even BSpec recommends doing it. For T9, if we
5645          * don't do this, we'll end up waiting for the backlight off delay
5646          * twice: once when we do the manual sleep, and once when we disable
5647          * the panel and wait for the PP_STATUS bit to become zero.
5648          */
5649         final->t8 = 1;
5650         final->t9 = 1;
5651
5652         /*
5653          * HW has only a 100msec granularity for t11_t12 so round it up
5654          * accordingly.
5655          */
5656         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5657 }
5658
5659 static void
5660 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5661                                               bool force_disable_vdd)
5662 {
5663         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5664         u32 pp_on, pp_off, pp_div, port_sel = 0;
5665         int div = dev_priv->rawclk_freq / 1000;
5666         struct pps_registers regs;
5667         enum port port = dp_to_dig_port(intel_dp)->base.port;
5668         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5669
5670         lockdep_assert_held(&dev_priv->pps_mutex);
5671
5672         intel_pps_get_registers(intel_dp, &regs);
5673
5674         /*
5675          * On some VLV machines the BIOS can leave the VDD
5676          * enabled even on power seqeuencers which aren't
5677          * hooked up to any port. This would mess up the
5678          * power domain tracking the first time we pick
5679          * one of these power sequencers for use since
5680          * edp_panel_vdd_on() would notice that the VDD was
5681          * already on and therefore wouldn't grab the power
5682          * domain reference. Disable VDD first to avoid this.
5683          * This also avoids spuriously turning the VDD on as
5684          * soon as the new power seqeuencer gets initialized.
5685          */
5686         if (force_disable_vdd) {
5687                 u32 pp = ironlake_get_pp_control(intel_dp);
5688
5689                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5690
5691                 if (pp & EDP_FORCE_VDD)
5692                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5693
5694                 pp &= ~EDP_FORCE_VDD;
5695
5696                 I915_WRITE(regs.pp_ctrl, pp);
5697         }
5698
5699         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5700                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5701         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5702                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5703         /* Compute the divisor for the pp clock, simply match the Bspec
5704          * formula. */
5705         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5706             HAS_PCH_ICP(dev_priv)) {
5707                 pp_div = I915_READ(regs.pp_ctrl);
5708                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5709                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5710                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5711         } else {
5712                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5713                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5714                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5715         }
5716
5717         /* Haswell doesn't have any port selection bits for the panel
5718          * power sequencer any more. */
5719         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5720                 port_sel = PANEL_PORT_SELECT_VLV(port);
5721         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5722                 if (port == PORT_A)
5723                         port_sel = PANEL_PORT_SELECT_DPA;
5724                 else
5725                         port_sel = PANEL_PORT_SELECT_DPD;
5726         }
5727
5728         pp_on |= port_sel;
5729
5730         I915_WRITE(regs.pp_on, pp_on);
5731         I915_WRITE(regs.pp_off, pp_off);
5732         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5733             HAS_PCH_ICP(dev_priv))
5734                 I915_WRITE(regs.pp_ctrl, pp_div);
5735         else
5736                 I915_WRITE(regs.pp_div, pp_div);
5737
5738         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5739                       I915_READ(regs.pp_on),
5740                       I915_READ(regs.pp_off),
5741                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5742                        HAS_PCH_ICP(dev_priv)) ?
5743                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5744                       I915_READ(regs.pp_div));
5745 }
5746
5747 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5748 {
5749         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5750
5751         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5752                 vlv_initial_power_sequencer_setup(intel_dp);
5753         } else {
5754                 intel_dp_init_panel_power_sequencer(intel_dp);
5755                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5756         }
5757 }
5758
5759 /**
5760  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5761  * @dev_priv: i915 device
5762  * @crtc_state: a pointer to the active intel_crtc_state
5763  * @refresh_rate: RR to be programmed
5764  *
5765  * This function gets called when refresh rate (RR) has to be changed from
5766  * one frequency to another. Switches can be between high and low RR
5767  * supported by the panel or to any other RR based on media playback (in
5768  * this case, RR value needs to be passed from user space).
5769  *
5770  * The caller of this function needs to take a lock on dev_priv->drrs.
5771  */
5772 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5773                                     const struct intel_crtc_state *crtc_state,
5774                                     int refresh_rate)
5775 {
5776         struct intel_encoder *encoder;
5777         struct intel_digital_port *dig_port = NULL;
5778         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5780         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5781
5782         if (refresh_rate <= 0) {
5783                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5784                 return;
5785         }
5786
5787         if (intel_dp == NULL) {
5788                 DRM_DEBUG_KMS("DRRS not supported.\n");
5789                 return;
5790         }
5791
5792         dig_port = dp_to_dig_port(intel_dp);
5793         encoder = &dig_port->base;
5794
5795         if (!intel_crtc) {
5796                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5797                 return;
5798         }
5799
5800         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5801                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5802                 return;
5803         }
5804
5805         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5806                         refresh_rate)
5807                 index = DRRS_LOW_RR;
5808
5809         if (index == dev_priv->drrs.refresh_rate_type) {
5810                 DRM_DEBUG_KMS(
5811                         "DRRS requested for previously set RR...ignoring\n");
5812                 return;
5813         }
5814
5815         if (!crtc_state->base.active) {
5816                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5817                 return;
5818         }
5819
5820         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5821                 switch (index) {
5822                 case DRRS_HIGH_RR:
5823                         intel_dp_set_m_n(intel_crtc, M1_N1);
5824                         break;
5825                 case DRRS_LOW_RR:
5826                         intel_dp_set_m_n(intel_crtc, M2_N2);
5827                         break;
5828                 case DRRS_MAX_RR:
5829                 default:
5830                         DRM_ERROR("Unsupported refreshrate type\n");
5831                 }
5832         } else if (INTEL_GEN(dev_priv) > 6) {
5833                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5834                 u32 val;
5835
5836                 val = I915_READ(reg);
5837                 if (index > DRRS_HIGH_RR) {
5838                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5839                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5840                         else
5841                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5842                 } else {
5843                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5844                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5845                         else
5846                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5847                 }
5848                 I915_WRITE(reg, val);
5849         }
5850
5851         dev_priv->drrs.refresh_rate_type = index;
5852
5853         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5854 }
5855
5856 /**
5857  * intel_edp_drrs_enable - init drrs struct if supported
5858  * @intel_dp: DP struct
5859  * @crtc_state: A pointer to the active crtc state.
5860  *
5861  * Initializes frontbuffer_bits and drrs.dp
5862  */
5863 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5864                            const struct intel_crtc_state *crtc_state)
5865 {
5866         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5867
5868         if (!crtc_state->has_drrs) {
5869                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5870                 return;
5871         }
5872
5873         if (dev_priv->psr.enabled) {
5874                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5875                 return;
5876         }
5877
5878         mutex_lock(&dev_priv->drrs.mutex);
5879         if (WARN_ON(dev_priv->drrs.dp)) {
5880                 DRM_ERROR("DRRS already enabled\n");
5881                 goto unlock;
5882         }
5883
5884         dev_priv->drrs.busy_frontbuffer_bits = 0;
5885
5886         dev_priv->drrs.dp = intel_dp;
5887
5888 unlock:
5889         mutex_unlock(&dev_priv->drrs.mutex);
5890 }
5891
5892 /**
5893  * intel_edp_drrs_disable - Disable DRRS
5894  * @intel_dp: DP struct
5895  * @old_crtc_state: Pointer to old crtc_state.
5896  *
5897  */
5898 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5899                             const struct intel_crtc_state *old_crtc_state)
5900 {
5901         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5902
5903         if (!old_crtc_state->has_drrs)
5904                 return;
5905
5906         mutex_lock(&dev_priv->drrs.mutex);
5907         if (!dev_priv->drrs.dp) {
5908                 mutex_unlock(&dev_priv->drrs.mutex);
5909                 return;
5910         }
5911
5912         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5913                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5914                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5915
5916         dev_priv->drrs.dp = NULL;
5917         mutex_unlock(&dev_priv->drrs.mutex);
5918
5919         cancel_delayed_work_sync(&dev_priv->drrs.work);
5920 }
5921
5922 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5923 {
5924         struct drm_i915_private *dev_priv =
5925                 container_of(work, typeof(*dev_priv), drrs.work.work);
5926         struct intel_dp *intel_dp;
5927
5928         mutex_lock(&dev_priv->drrs.mutex);
5929
5930         intel_dp = dev_priv->drrs.dp;
5931
5932         if (!intel_dp)
5933                 goto unlock;
5934
5935         /*
5936          * The delayed work can race with an invalidate hence we need to
5937          * recheck.
5938          */
5939
5940         if (dev_priv->drrs.busy_frontbuffer_bits)
5941                 goto unlock;
5942
5943         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5944                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5945
5946                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5947                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5948         }
5949
5950 unlock:
5951         mutex_unlock(&dev_priv->drrs.mutex);
5952 }
5953
5954 /**
5955  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5956  * @dev_priv: i915 device
5957  * @frontbuffer_bits: frontbuffer plane tracking bits
5958  *
5959  * This function gets called everytime rendering on the given planes start.
5960  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5961  *
5962  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5963  */
5964 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5965                                unsigned int frontbuffer_bits)
5966 {
5967         struct drm_crtc *crtc;
5968         enum pipe pipe;
5969
5970         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5971                 return;
5972
5973         cancel_delayed_work(&dev_priv->drrs.work);
5974
5975         mutex_lock(&dev_priv->drrs.mutex);
5976         if (!dev_priv->drrs.dp) {
5977                 mutex_unlock(&dev_priv->drrs.mutex);
5978                 return;
5979         }
5980
5981         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5982         pipe = to_intel_crtc(crtc)->pipe;
5983
5984         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5985         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5986
5987         /* invalidate means busy screen hence upclock */
5988         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5989                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5990                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5991
5992         mutex_unlock(&dev_priv->drrs.mutex);
5993 }
5994
5995 /**
5996  * intel_edp_drrs_flush - Restart Idleness DRRS
5997  * @dev_priv: i915 device
5998  * @frontbuffer_bits: frontbuffer plane tracking bits
5999  *
6000  * This function gets called every time rendering on the given planes has
6001  * completed or flip on a crtc is completed. So DRRS should be upclocked
6002  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6003  * if no other planes are dirty.
6004  *
6005  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6006  */
6007 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6008                           unsigned int frontbuffer_bits)
6009 {
6010         struct drm_crtc *crtc;
6011         enum pipe pipe;
6012
6013         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6014                 return;
6015
6016         cancel_delayed_work(&dev_priv->drrs.work);
6017
6018         mutex_lock(&dev_priv->drrs.mutex);
6019         if (!dev_priv->drrs.dp) {
6020                 mutex_unlock(&dev_priv->drrs.mutex);
6021                 return;
6022         }
6023
6024         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6025         pipe = to_intel_crtc(crtc)->pipe;
6026
6027         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6028         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6029
6030         /* flush means busy screen hence upclock */
6031         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6032                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6033                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6034
6035         /*
6036          * flush also means no more activity hence schedule downclock, if all
6037          * other fbs are quiescent too
6038          */
6039         if (!dev_priv->drrs.busy_frontbuffer_bits)
6040                 schedule_delayed_work(&dev_priv->drrs.work,
6041                                 msecs_to_jiffies(1000));
6042         mutex_unlock(&dev_priv->drrs.mutex);
6043 }
6044
6045 /**
6046  * DOC: Display Refresh Rate Switching (DRRS)
6047  *
6048  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6049  * which enables swtching between low and high refresh rates,
6050  * dynamically, based on the usage scenario. This feature is applicable
6051  * for internal panels.
6052  *
6053  * Indication that the panel supports DRRS is given by the panel EDID, which
6054  * would list multiple refresh rates for one resolution.
6055  *
6056  * DRRS is of 2 types - static and seamless.
6057  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6058  * (may appear as a blink on screen) and is used in dock-undock scenario.
6059  * Seamless DRRS involves changing RR without any visual effect to the user
6060  * and can be used during normal system usage. This is done by programming
6061  * certain registers.
6062  *
6063  * Support for static/seamless DRRS may be indicated in the VBT based on
6064  * inputs from the panel spec.
6065  *
6066  * DRRS saves power by switching to low RR based on usage scenarios.
6067  *
6068  * The implementation is based on frontbuffer tracking implementation.  When
6069  * there is a disturbance on the screen triggered by user activity or a periodic
6070  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6071  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6072  * made.
6073  *
6074  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6075  * and intel_edp_drrs_flush() are called.
6076  *
6077  * DRRS can be further extended to support other internal panels and also
6078  * the scenario of video playback wherein RR is set based on the rate
6079  * requested by userspace.
6080  */
6081
6082 /**
6083  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6084  * @connector: eDP connector
6085  * @fixed_mode: preferred mode of panel
6086  *
6087  * This function is  called only once at driver load to initialize basic
6088  * DRRS stuff.
6089  *
6090  * Returns:
6091  * Downclock mode if panel supports it, else return NULL.
6092  * DRRS support is determined by the presence of downclock mode (apart
6093  * from VBT setting).
6094  */
6095 static struct drm_display_mode *
6096 intel_dp_drrs_init(struct intel_connector *connector,
6097                    struct drm_display_mode *fixed_mode)
6098 {
6099         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6100         struct drm_display_mode *downclock_mode = NULL;
6101
6102         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6103         mutex_init(&dev_priv->drrs.mutex);
6104
6105         if (INTEL_GEN(dev_priv) <= 6) {
6106                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6107                 return NULL;
6108         }
6109
6110         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6111                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6112                 return NULL;
6113         }
6114
6115         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6116                                                     &connector->base);
6117
6118         if (!downclock_mode) {
6119                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6120                 return NULL;
6121         }
6122
6123         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6124
6125         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6126         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6127         return downclock_mode;
6128 }
6129
6130 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6131                                      struct intel_connector *intel_connector)
6132 {
6133         struct drm_device *dev = intel_dp_to_dev(intel_dp);
6134         struct drm_i915_private *dev_priv = to_i915(dev);
6135         struct drm_connector *connector = &intel_connector->base;
6136         struct drm_display_mode *fixed_mode = NULL;
6137         struct drm_display_mode *downclock_mode = NULL;
6138         bool has_dpcd;
6139         struct drm_display_mode *scan;
6140         struct edid *edid;
6141         enum pipe pipe = INVALID_PIPE;
6142
6143         if (!intel_dp_is_edp(intel_dp))
6144                 return true;
6145
6146         /*
6147          * On IBX/CPT we may get here with LVDS already registered. Since the
6148          * driver uses the only internal power sequencer available for both
6149          * eDP and LVDS bail out early in this case to prevent interfering
6150          * with an already powered-on LVDS power sequencer.
6151          */
6152         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6153                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6154                 DRM_INFO("LVDS was detected, not registering eDP\n");
6155
6156                 return false;
6157         }
6158
6159         pps_lock(intel_dp);
6160
6161         intel_dp_init_panel_power_timestamps(intel_dp);
6162         intel_dp_pps_init(intel_dp);
6163         intel_edp_panel_vdd_sanitize(intel_dp);
6164
6165         pps_unlock(intel_dp);
6166
6167         /* Cache DPCD and EDID for edp. */
6168         has_dpcd = intel_edp_init_dpcd(intel_dp);
6169
6170         if (!has_dpcd) {
6171                 /* if this fails, presume the device is a ghost */
6172                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6173                 goto out_vdd_off;
6174         }
6175
6176         mutex_lock(&dev->mode_config.mutex);
6177         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6178         if (edid) {
6179                 if (drm_add_edid_modes(connector, edid)) {
6180                         drm_mode_connector_update_edid_property(connector,
6181                                                                 edid);
6182                 } else {
6183                         kfree(edid);
6184                         edid = ERR_PTR(-EINVAL);
6185                 }
6186         } else {
6187                 edid = ERR_PTR(-ENOENT);
6188         }
6189         intel_connector->edid = edid;
6190
6191         /* prefer fixed mode from EDID if available */
6192         list_for_each_entry(scan, &connector->probed_modes, head) {
6193                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6194                         fixed_mode = drm_mode_duplicate(dev, scan);
6195                         downclock_mode = intel_dp_drrs_init(
6196                                                 intel_connector, fixed_mode);
6197                         break;
6198                 }
6199         }
6200
6201         /* fallback to VBT if available for eDP */
6202         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6203                 fixed_mode = drm_mode_duplicate(dev,
6204                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6205                 if (fixed_mode) {
6206                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6207                         connector->display_info.width_mm = fixed_mode->width_mm;
6208                         connector->display_info.height_mm = fixed_mode->height_mm;
6209                 }
6210         }
6211         mutex_unlock(&dev->mode_config.mutex);
6212
6213         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6214                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6215                 register_reboot_notifier(&intel_dp->edp_notifier);
6216
6217                 /*
6218                  * Figure out the current pipe for the initial backlight setup.
6219                  * If the current pipe isn't valid, try the PPS pipe, and if that
6220                  * fails just assume pipe A.
6221                  */
6222                 pipe = vlv_active_pipe(intel_dp);
6223
6224                 if (pipe != PIPE_A && pipe != PIPE_B)
6225                         pipe = intel_dp->pps_pipe;
6226
6227                 if (pipe != PIPE_A && pipe != PIPE_B)
6228                         pipe = PIPE_A;
6229
6230                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6231                               pipe_name(pipe));
6232         }
6233
6234         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6235         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6236         intel_panel_setup_backlight(connector, pipe);
6237
6238         return true;
6239
6240 out_vdd_off:
6241         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6242         /*
6243          * vdd might still be enabled do to the delayed vdd off.
6244          * Make sure vdd is actually turned off here.
6245          */
6246         pps_lock(intel_dp);
6247         edp_panel_vdd_off_sync(intel_dp);
6248         pps_unlock(intel_dp);
6249
6250         return false;
6251 }
6252
6253 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6254 {
6255         struct intel_connector *intel_connector;
6256         struct drm_connector *connector;
6257
6258         intel_connector = container_of(work, typeof(*intel_connector),
6259                                        modeset_retry_work);
6260         connector = &intel_connector->base;
6261         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6262                       connector->name);
6263
6264         /* Grab the locks before changing connector property*/
6265         mutex_lock(&connector->dev->mode_config.mutex);
6266         /* Set connector link status to BAD and send a Uevent to notify
6267          * userspace to do a modeset.
6268          */
6269         drm_mode_connector_set_link_status_property(connector,
6270                                                     DRM_MODE_LINK_STATUS_BAD);
6271         mutex_unlock(&connector->dev->mode_config.mutex);
6272         /* Send Hotplug uevent so userspace can reprobe */
6273         drm_kms_helper_hotplug_event(connector->dev);
6274 }
6275
6276 bool
6277 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6278                         struct intel_connector *intel_connector)
6279 {
6280         struct drm_connector *connector = &intel_connector->base;
6281         struct intel_dp *intel_dp = &intel_dig_port->dp;
6282         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6283         struct drm_device *dev = intel_encoder->base.dev;
6284         struct drm_i915_private *dev_priv = to_i915(dev);
6285         enum port port = intel_encoder->port;
6286         int type;
6287
6288         /* Initialize the work for modeset in case of link train failure */
6289         INIT_WORK(&intel_connector->modeset_retry_work,
6290                   intel_dp_modeset_retry_work_fn);
6291
6292         if (WARN(intel_dig_port->max_lanes < 1,
6293                  "Not enough lanes (%d) for DP on port %c\n",
6294                  intel_dig_port->max_lanes, port_name(port)))
6295                 return false;
6296
6297         intel_dp_set_source_rates(intel_dp);
6298
6299         intel_dp->reset_link_params = true;
6300         intel_dp->pps_pipe = INVALID_PIPE;
6301         intel_dp->active_pipe = INVALID_PIPE;
6302
6303         /* intel_dp vfuncs */
6304         if (HAS_DDI(dev_priv))
6305                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6306
6307         /* Preserve the current hw state. */
6308         intel_dp->DP = I915_READ(intel_dp->output_reg);
6309         intel_dp->attached_connector = intel_connector;
6310
6311         if (intel_dp_is_port_edp(dev_priv, port))
6312                 type = DRM_MODE_CONNECTOR_eDP;
6313         else
6314                 type = DRM_MODE_CONNECTOR_DisplayPort;
6315
6316         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6317                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6318
6319         /*
6320          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6321          * for DP the encoder type can be set by the caller to
6322          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6323          */
6324         if (type == DRM_MODE_CONNECTOR_eDP)
6325                 intel_encoder->type = INTEL_OUTPUT_EDP;
6326
6327         /* eDP only on port B and/or C on vlv/chv */
6328         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6329                     intel_dp_is_edp(intel_dp) &&
6330                     port != PORT_B && port != PORT_C))
6331                 return false;
6332
6333         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6334                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6335                         port_name(port));
6336
6337         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6338         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6339
6340         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6341                 connector->interlace_allowed = true;
6342         connector->doublescan_allowed = 0;
6343
6344         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6345
6346         intel_dp_aux_init(intel_dp);
6347
6348         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6349                           edp_panel_vdd_work);
6350
6351         intel_connector_attach_encoder(intel_connector, intel_encoder);
6352
6353         if (HAS_DDI(dev_priv))
6354                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6355         else
6356                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6357
6358         /* init MST on ports that can support it */
6359         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6360             (port == PORT_B || port == PORT_C ||
6361              port == PORT_D || port == PORT_F))
6362                 intel_dp_mst_encoder_init(intel_dig_port,
6363                                           intel_connector->base.base.id);
6364
6365         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6366                 intel_dp_aux_fini(intel_dp);
6367                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6368                 goto fail;
6369         }
6370
6371         intel_dp_add_properties(intel_dp, connector);
6372
6373         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6374                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6375                 if (ret)
6376                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6377         }
6378
6379         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6380          * 0xd.  Failure to do so will result in spurious interrupts being
6381          * generated on the port when a cable is not attached.
6382          */
6383         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6384                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6385                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6386         }
6387
6388         return true;
6389
6390 fail:
6391         drm_connector_cleanup(connector);
6392
6393         return false;
6394 }
6395
6396 bool intel_dp_init(struct drm_i915_private *dev_priv,
6397                    i915_reg_t output_reg,
6398                    enum port port)
6399 {
6400         struct intel_digital_port *intel_dig_port;
6401         struct intel_encoder *intel_encoder;
6402         struct drm_encoder *encoder;
6403         struct intel_connector *intel_connector;
6404
6405         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6406         if (!intel_dig_port)
6407                 return false;
6408
6409         intel_connector = intel_connector_alloc();
6410         if (!intel_connector)
6411                 goto err_connector_alloc;
6412
6413         intel_encoder = &intel_dig_port->base;
6414         encoder = &intel_encoder->base;
6415
6416         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6417                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6418                              "DP %c", port_name(port)))
6419                 goto err_encoder_init;
6420
6421         intel_encoder->hotplug = intel_dp_hotplug;
6422         intel_encoder->compute_config = intel_dp_compute_config;
6423         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6424         intel_encoder->get_config = intel_dp_get_config;
6425         intel_encoder->suspend = intel_dp_encoder_suspend;
6426         if (IS_CHERRYVIEW(dev_priv)) {
6427                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6428                 intel_encoder->pre_enable = chv_pre_enable_dp;
6429                 intel_encoder->enable = vlv_enable_dp;
6430                 intel_encoder->disable = vlv_disable_dp;
6431                 intel_encoder->post_disable = chv_post_disable_dp;
6432                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6433         } else if (IS_VALLEYVIEW(dev_priv)) {
6434                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6435                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6436                 intel_encoder->enable = vlv_enable_dp;
6437                 intel_encoder->disable = vlv_disable_dp;
6438                 intel_encoder->post_disable = vlv_post_disable_dp;
6439         } else if (INTEL_GEN(dev_priv) >= 5) {
6440                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6441                 intel_encoder->enable = g4x_enable_dp;
6442                 intel_encoder->disable = ilk_disable_dp;
6443                 intel_encoder->post_disable = ilk_post_disable_dp;
6444         } else {
6445                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6446                 intel_encoder->enable = g4x_enable_dp;
6447                 intel_encoder->disable = g4x_disable_dp;
6448         }
6449
6450         intel_dig_port->dp.output_reg = output_reg;
6451         intel_dig_port->max_lanes = 4;
6452
6453         intel_encoder->type = INTEL_OUTPUT_DP;
6454         intel_encoder->power_domain = intel_port_to_power_domain(port);
6455         if (IS_CHERRYVIEW(dev_priv)) {
6456                 if (port == PORT_D)
6457                         intel_encoder->crtc_mask = 1 << 2;
6458                 else
6459                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6460         } else {
6461                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6462         }
6463         intel_encoder->cloneable = 0;
6464         intel_encoder->port = port;
6465
6466         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6467         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6468
6469         if (port != PORT_A)
6470                 intel_infoframe_init(intel_dig_port);
6471
6472         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6473                 goto err_init_connector;
6474
6475         return true;
6476
6477 err_init_connector:
6478         drm_encoder_cleanup(encoder);
6479 err_encoder_init:
6480         kfree(intel_connector);
6481 err_connector_alloc:
6482         kfree(intel_dig_port);
6483         return false;
6484 }
6485
6486 void intel_dp_mst_suspend(struct drm_device *dev)
6487 {
6488         struct drm_i915_private *dev_priv = to_i915(dev);
6489         int i;
6490
6491         /* disable MST */
6492         for (i = 0; i < I915_MAX_PORTS; i++) {
6493                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6494
6495                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6496                         continue;
6497
6498                 if (intel_dig_port->dp.is_mst)
6499                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6500         }
6501 }
6502
6503 void intel_dp_mst_resume(struct drm_device *dev)
6504 {
6505         struct drm_i915_private *dev_priv = to_i915(dev);
6506         int i;
6507
6508         for (i = 0; i < I915_MAX_PORTS; i++) {
6509                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6510                 int ret;
6511
6512                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6513                         continue;
6514
6515                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6516                 if (ret)
6517                         intel_dp_check_mst_status(&intel_dig_port->dp);
6518         }
6519 }