drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /**
  45  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  46  * @intel_dp: DP struct
  47  *
  48  * If a CPU or PCH DP output is attached to an eDP panel, this function
  49  * will return true, and false otherwise.
  50  */
  51 static bool is_edp(struct intel_dp *intel_dp)
  52 {
  53         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  54 }
  55
  56 /**
  57  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  58  * @intel_dp: DP struct
  59  *
  60  * Returns true if the given DP struct corresponds to a PCH DP port attached
  61  * to an eDP panel, false otherwise.  Helpful for determining whether we
  62  * may need FDI resources for a given DP output or not.
  63  */
  64 static bool is_pch_edp(struct intel_dp *intel_dp)
  65 {
  66         return intel_dp->is_pch_edp;
  67 }
  68
  69 /**
  70  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  71  * @intel_dp: DP struct
  72  *
  73  * Returns true if the given DP struct corresponds to a CPU eDP port.
  74  */
  75 static bool is_cpu_edp(struct intel_dp *intel_dp)
  76 {
  77         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  78 }
  79
  80 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  81 {
  82         return container_of(intel_attached_encoder(connector),
  83                             struct intel_dp, base);
  84 }
  85
  86 /**
  87  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  88  * @encoder: DRM encoder
  89  *
  90  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  91  * by intel_display.c.
  92  */
  93 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  94 {
  95         struct intel_dp *intel_dp;
  96
  97         if (!encoder)
  98                 return false;
  99
 100         intel_dp = enc_to_intel_dp(encoder);
 101
 102         return is_pch_edp(intel_dp);
 103 }
 104
 105 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 106 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 107 static void intel_dp_link_down(struct intel_dp *intel_dp);
 108
 109 void
 110 intel_edp_link_config(struct intel_encoder *intel_encoder,
 111                        int *lane_num, int *link_bw)
 112 {
 113         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 114
 115         *lane_num = intel_dp->lane_count;
 116         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 117                 *link_bw = 162000;
 118         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 119                 *link_bw = 270000;
 120 }
 121
 122 int
 123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 124                        struct drm_display_mode *mode)
 125 {
 126         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 127
 128         if (intel_dp->panel_fixed_mode)
 129                 return intel_dp->panel_fixed_mode->clock;
 130         else
 131                 return mode->clock;
 132 }
 133
 134 static int
 135 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 136 {
 137         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 138         switch (max_lane_count) {
 139         case 1: case 2: case 4:
 140                 break;
 141         default:
 142                 max_lane_count = 4;
 143         }
 144         return max_lane_count;
 145 }
 146
 147 static int
 148 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 149 {
 150         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 151
 152         switch (max_link_bw) {
 153         case DP_LINK_BW_1_62:
 154         case DP_LINK_BW_2_7:
 155                 break;
 156         default:
 157                 max_link_bw = DP_LINK_BW_1_62;
 158                 break;
 159         }
 160         return max_link_bw;
 161 }
 162
 163 static int
 164 intel_dp_link_clock(uint8_t link_bw)
 165 {
 166         if (link_bw == DP_LINK_BW_2_7)
 167                 return 270000;
 168         else
 169                 return 162000;
 170 }
 171
 172 /*
 173  * The units on the numbers in the next two are... bizarre.  Examples will
 174  * make it clearer; this one parallels an example in the eDP spec.
 175  *
 176  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 177  *
 178  *     270000 * 1 * 8 / 10 == 216000
 179  *
 180  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 181  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 182  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 183  * 119000.  At 18bpp that's 2142000 kilobits per second.
 184  *
 185  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 186  * get the result in decakilobits instead of kilobits.
 187  */
 188
 189 static int
 190 intel_dp_link_required(int pixel_clock, int bpp)
 191 {
 192         return (pixel_clock * bpp + 9) / 10;
 193 }
 194
 195 static int
 196 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 197 {
 198         return (max_link_clock * max_lanes * 8) / 10;
 199 }
 200
 201 static bool
 202 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 203                           struct drm_display_mode *mode,
 204                           bool adjust_mode)
 205 {
 206         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 207         int max_lanes = intel_dp_max_lane_count(intel_dp);
 208         int max_rate, mode_rate;
 209
 210         mode_rate = intel_dp_link_required(mode->clock, 24);
 211         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 212
 213         if (mode_rate > max_rate) {
 214                 mode_rate = intel_dp_link_required(mode->clock, 18);
 215                 if (mode_rate > max_rate)
 216                         return false;
 217
 218                 if (adjust_mode)
 219                         mode->private_flags
 220                                 |= INTEL_MODE_DP_FORCE_6BPC;
 221
 222                 return true;
 223         }
 224
 225         return true;
 226 }
 227
 228 static int
 229 intel_dp_mode_valid(struct drm_connector *connector,
 230                     struct drm_display_mode *mode)
 231 {
 232         struct intel_dp *intel_dp = intel_attached_dp(connector);
 233
 234         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 235                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 236                         return MODE_PANEL;
 237
 238                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 239                         return MODE_PANEL;
 240         }
 241
 242         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 243                 return MODE_CLOCK_HIGH;
 244
 245         if (mode->clock < 10000)
 246                 return MODE_CLOCK_LOW;
 247
 248         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 249                 return MODE_H_ILLEGAL;
 250
 251         return MODE_OK;
 252 }
 253
 254 static uint32_t
 255 pack_aux(uint8_t *src, int src_bytes)
 256 {
 257         int     i;
 258         uint32_t v = 0;
 259
 260         if (src_bytes > 4)
 261                 src_bytes = 4;
 262         for (i = 0; i < src_bytes; i++)
 263                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 264         return v;
 265 }
 266
 267 static void
 268 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 269 {
 270         int i;
 271         if (dst_bytes > 4)
 272                 dst_bytes = 4;
 273         for (i = 0; i < dst_bytes; i++)
 274                 dst[i] = src >> ((3-i) * 8);
 275 }
 276
 277 /* hrawclock is 1/4 the FSB frequency */
 278 static int
 279 intel_hrawclk(struct drm_device *dev)
 280 {
 281         struct drm_i915_private *dev_priv = dev->dev_private;
 282         uint32_t clkcfg;
 283
 284         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 285         if (IS_VALLEYVIEW(dev))
 286                 return 200;
 287
 288         clkcfg = I915_READ(CLKCFG);
 289         switch (clkcfg & CLKCFG_FSB_MASK) {
 290         case CLKCFG_FSB_400:
 291                 return 100;
 292         case CLKCFG_FSB_533:
 293                 return 133;
 294         case CLKCFG_FSB_667:
 295                 return 166;
 296         case CLKCFG_FSB_800:
 297                 return 200;
 298         case CLKCFG_FSB_1067:
 299                 return 266;
 300         case CLKCFG_FSB_1333:
 301                 return 333;
 302         /* these two are just a guess; one of them might be right */
 303         case CLKCFG_FSB_1600:
 304         case CLKCFG_FSB_1600_ALT:
 305                 return 400;
 306         default:
 307                 return 133;
 308         }
 309 }
 310
 311 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 312 {
 313         struct drm_device *dev = intel_dp->base.base.dev;
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315
 316         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 317 }
 318
 319 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 320 {
 321         struct drm_device *dev = intel_dp->base.base.dev;
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 325 }
 326
 327 static void
 328 intel_dp_check_edp(struct intel_dp *intel_dp)
 329 {
 330         struct drm_device *dev = intel_dp->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332
 333         if (!is_edp(intel_dp))
 334                 return;
 335         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 336                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 337                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 338                               I915_READ(PCH_PP_STATUS),
 339                               I915_READ(PCH_PP_CONTROL));
 340         }
 341 }
 342
 343 static int
 344 intel_dp_aux_ch(struct intel_dp *intel_dp,
 345                 uint8_t *send, int send_bytes,
 346                 uint8_t *recv, int recv_size)
 347 {
 348         uint32_t output_reg = intel_dp->output_reg;
 349         struct drm_device *dev = intel_dp->base.base.dev;
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351         uint32_t ch_ctl = output_reg + 0x10;
 352         uint32_t ch_data = ch_ctl + 4;
 353         int i;
 354         int recv_bytes;
 355         uint32_t status;
 356         uint32_t aux_clock_divider;
 357         int try, precharge;
 358
 359         intel_dp_check_edp(intel_dp);
 360         /* The clock divider is based off the hrawclk,
 361          * and would like to run at 2MHz. So, take the
 362          * hrawclk value and divide by 2 and use that
 363          *
 364          * Note that PCH attached eDP panels should use a 125MHz input
 365          * clock divider.
 366          */
 367         if (is_cpu_edp(intel_dp)) {
 368                 if (IS_VALLEYVIEW(dev))
 369                         aux_clock_divider = 100;
 370                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 371                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 372                 else
 373                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 374         } else if (HAS_PCH_SPLIT(dev))
 375                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 376         else
 377                 aux_clock_divider = intel_hrawclk(dev) / 2;
 378
 379         if (IS_GEN6(dev))
 380                 precharge = 3;
 381         else
 382                 precharge = 5;
 383
 384         /* Try to wait for any previous AUX channel activity */
 385         for (try = 0; try < 3; try++) {
 386                 status = I915_READ(ch_ctl);
 387                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 388                         break;
 389                 msleep(1);
 390         }
 391
 392         if (try == 3) {
 393                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 394                      I915_READ(ch_ctl));
 395                 return -EBUSY;
 396         }
 397
 398         /* Must try at least 3 times according to DP spec */
 399         for (try = 0; try < 5; try++) {
 400                 /* Load the send data into the aux channel data registers */
 401                 for (i = 0; i < send_bytes; i += 4)
 402                         I915_WRITE(ch_data + i,
 403                                    pack_aux(send + i, send_bytes - i));
 404
 405                 /* Send the command and wait for it to complete */
 406                 I915_WRITE(ch_ctl,
 407                            DP_AUX_CH_CTL_SEND_BUSY |
 408                            DP_AUX_CH_CTL_TIME_OUT_400us |
 409                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 410                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 411                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 412                            DP_AUX_CH_CTL_DONE |
 413                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 414                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 415                 for (;;) {
 416                         status = I915_READ(ch_ctl);
 417                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 418                                 break;
 419                         udelay(100);
 420                 }
 421
 422                 /* Clear done status and any errors */
 423                 I915_WRITE(ch_ctl,
 424                            status |
 425                            DP_AUX_CH_CTL_DONE |
 426                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 427                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 428
 429                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 430                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 431                         continue;
 432                 if (status & DP_AUX_CH_CTL_DONE)
 433                         break;
 434         }
 435
 436         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 437                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 438                 return -EBUSY;
 439         }
 440
 441         /* Check for timeout or receive error.
 442          * Timeouts occur when the sink is not connected
 443          */
 444         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 445                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 446                 return -EIO;
 447         }
 448
 449         /* Timeouts occur when the device isn't connected, so they're
 450          * "normal" -- don't fill the kernel log with these */
 451         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 452                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 453                 return -ETIMEDOUT;
 454         }
 455
 456         /* Unload any bytes sent back from the other side */
 457         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 458                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 459         if (recv_bytes > recv_size)
 460                 recv_bytes = recv_size;
 461
 462         for (i = 0; i < recv_bytes; i += 4)
 463                 unpack_aux(I915_READ(ch_data + i),
 464                            recv + i, recv_bytes - i);
 465
 466         return recv_bytes;
 467 }
 468
 469 /* Write data to the aux channel in native mode */
 470 static int
 471 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 472                           uint16_t address, uint8_t *send, int send_bytes)
 473 {
 474         int ret;
 475         uint8_t msg[20];
 476         int msg_bytes;
 477         uint8_t ack;
 478
 479         intel_dp_check_edp(intel_dp);
 480         if (send_bytes > 16)
 481                 return -1;
 482         msg[0] = AUX_NATIVE_WRITE << 4;
 483         msg[1] = address >> 8;
 484         msg[2] = address & 0xff;
 485         msg[3] = send_bytes - 1;
 486         memcpy(&msg[4], send, send_bytes);
 487         msg_bytes = send_bytes + 4;
 488         for (;;) {
 489                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 490                 if (ret < 0)
 491                         return ret;
 492                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 493                         break;
 494                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 495                         udelay(100);
 496                 else
 497                         return -EIO;
 498         }
 499         return send_bytes;
 500 }
 501
 502 /* Write a single byte to the aux channel in native mode */
 503 static int
 504 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 505                             uint16_t address, uint8_t byte)
 506 {
 507         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 508 }
 509
 510 /* read bytes from a native aux channel */
 511 static int
 512 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 513                          uint16_t address, uint8_t *recv, int recv_bytes)
 514 {
 515         uint8_t msg[4];
 516         int msg_bytes;
 517         uint8_t reply[20];
 518         int reply_bytes;
 519         uint8_t ack;
 520         int ret;
 521
 522         intel_dp_check_edp(intel_dp);
 523         msg[0] = AUX_NATIVE_READ << 4;
 524         msg[1] = address >> 8;
 525         msg[2] = address & 0xff;
 526         msg[3] = recv_bytes - 1;
 527
 528         msg_bytes = 4;
 529         reply_bytes = recv_bytes + 1;
 530
 531         for (;;) {
 532                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 533                                       reply, reply_bytes);
 534                 if (ret == 0)
 535                         return -EPROTO;
 536                 if (ret < 0)
 537                         return ret;
 538                 ack = reply[0];
 539                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 540                         memcpy(recv, reply + 1, ret - 1);
 541                         return ret - 1;
 542                 }
 543                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 544                         udelay(100);
 545                 else
 546                         return -EIO;
 547         }
 548 }
 549
 550 static int
 551 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 552                     uint8_t write_byte, uint8_t *read_byte)
 553 {
 554         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 555         struct intel_dp *intel_dp = container_of(adapter,
 556                                                 struct intel_dp,
 557                                                 adapter);
 558         uint16_t address = algo_data->address;
 559         uint8_t msg[5];
 560         uint8_t reply[2];
 561         unsigned retry;
 562         int msg_bytes;
 563         int reply_bytes;
 564         int ret;
 565
 566         intel_dp_check_edp(intel_dp);
 567         /* Set up the command byte */
 568         if (mode & MODE_I2C_READ)
 569                 msg[0] = AUX_I2C_READ << 4;
 570         else
 571                 msg[0] = AUX_I2C_WRITE << 4;
 572
 573         if (!(mode & MODE_I2C_STOP))
 574                 msg[0] |= AUX_I2C_MOT << 4;
 575
 576         msg[1] = address >> 8;
 577         msg[2] = address;
 578
 579         switch (mode) {
 580         case MODE_I2C_WRITE:
 581                 msg[3] = 0;
 582                 msg[4] = write_byte;
 583                 msg_bytes = 5;
 584                 reply_bytes = 1;
 585                 break;
 586         case MODE_I2C_READ:
 587                 msg[3] = 0;
 588                 msg_bytes = 4;
 589                 reply_bytes = 2;
 590                 break;
 591         default:
 592                 msg_bytes = 3;
 593                 reply_bytes = 1;
 594                 break;
 595         }
 596
 597         for (retry = 0; retry < 5; retry++) {
 598                 ret = intel_dp_aux_ch(intel_dp,
 599                                       msg, msg_bytes,
 600                                       reply, reply_bytes);
 601                 if (ret < 0) {
 602                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 603                         return ret;
 604                 }
 605
 606                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 607                 case AUX_NATIVE_REPLY_ACK:
 608                         /* I2C-over-AUX Reply field is only valid
 609                          * when paired with AUX ACK.
 610                          */
 611                         break;
 612                 case AUX_NATIVE_REPLY_NACK:
 613                         DRM_DEBUG_KMS("aux_ch native nack\n");
 614                         return -EREMOTEIO;
 615                 case AUX_NATIVE_REPLY_DEFER:
 616                         udelay(100);
 617                         continue;
 618                 default:
 619                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 620                                   reply[0]);
 621                         return -EREMOTEIO;
 622                 }
 623
 624                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 625                 case AUX_I2C_REPLY_ACK:
 626                         if (mode == MODE_I2C_READ) {
 627                                 *read_byte = reply[1];
 628                         }
 629                         return reply_bytes - 1;
 630                 case AUX_I2C_REPLY_NACK:
 631                         DRM_DEBUG_KMS("aux_i2c nack\n");
 632                         return -EREMOTEIO;
 633                 case AUX_I2C_REPLY_DEFER:
 634                         DRM_DEBUG_KMS("aux_i2c defer\n");
 635                         udelay(100);
 636                         break;
 637                 default:
 638                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 639                         return -EREMOTEIO;
 640                 }
 641         }
 642
 643         DRM_ERROR("too many retries, giving up\n");
 644         return -EREMOTEIO;
 645 }
 646
 647 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 648 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 649
 650 static int
 651 intel_dp_i2c_init(struct intel_dp *intel_dp,
 652                   struct intel_connector *intel_connector, const char *name)
 653 {
 654         int     ret;
 655
 656         DRM_DEBUG_KMS("i2c_init %s\n", name);
 657         intel_dp->algo.running = false;
 658         intel_dp->algo.address = 0;
 659         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 660
 661         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 662         intel_dp->adapter.owner = THIS_MODULE;
 663         intel_dp->adapter.class = I2C_CLASS_DDC;
 664         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 665         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 666         intel_dp->adapter.algo_data = &intel_dp->algo;
 667         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 668
 669         ironlake_edp_panel_vdd_on(intel_dp);
 670         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 671         ironlake_edp_panel_vdd_off(intel_dp, false);
 672         return ret;
 673 }
 674
 675 static bool
 676 intel_dp_mode_fixup(struct drm_encoder *encoder,
 677                     const struct drm_display_mode *mode,
 678                     struct drm_display_mode *adjusted_mode)
 679 {
 680         struct drm_device *dev = encoder->dev;
 681         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 682         int lane_count, clock;
 683         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 684         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 685         int bpp, mode_rate;
 686         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 687
 688         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 689                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 690                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 691                                         mode, adjusted_mode);
 692         }
 693
 694         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 695                 return false;
 696
 697         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 698                       "max bw %02x pixel clock %iKHz\n",
 699                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 700
 701         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 702                 return false;
 703
 704         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 705         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 706
 707         for (clock = 0; clock <= max_clock; clock++) {
 708                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 709                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 710
 711                         if (mode_rate <= link_avail) {
 712                                 intel_dp->link_bw = bws[clock];
 713                                 intel_dp->lane_count = lane_count;
 714                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 715                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 716                                                 "count %d clock %d bpp %d\n",
 717                                        intel_dp->link_bw, intel_dp->lane_count,
 718                                        adjusted_mode->clock, bpp);
 719                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 720                                               mode_rate, link_avail);
 721                                 return true;
 722                         }
 723                 }
 724         }
 725
 726         return false;
 727 }
 728
 729 struct intel_dp_m_n {
 730         uint32_t        tu;
 731         uint32_t        gmch_m;
 732         uint32_t        gmch_n;
 733         uint32_t        link_m;
 734         uint32_t        link_n;
 735 };
 736
 737 static void
 738 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 739 {
 740         while (*num > 0xffffff || *den > 0xffffff) {
 741                 *num >>= 1;
 742                 *den >>= 1;
 743         }
 744 }
 745
 746 static void
 747 intel_dp_compute_m_n(int bpp,
 748                      int nlanes,
 749                      int pixel_clock,
 750                      int link_clock,
 751                      struct intel_dp_m_n *m_n)
 752 {
 753         m_n->tu = 64;
 754         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 755         m_n->gmch_n = link_clock * nlanes;
 756         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 757         m_n->link_m = pixel_clock;
 758         m_n->link_n = link_clock;
 759         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 760 }
 761
 762 void
 763 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 764                  struct drm_display_mode *adjusted_mode)
 765 {
 766         struct drm_device *dev = crtc->dev;
 767         struct intel_encoder *encoder;
 768         struct drm_i915_private *dev_priv = dev->dev_private;
 769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 770         int lane_count = 4;
 771         struct intel_dp_m_n m_n;
 772         int pipe = intel_crtc->pipe;
 773
 774         /*
 775          * Find the lane count in the intel_encoder private
 776          */
 777         for_each_encoder_on_crtc(dev, crtc, encoder) {
 778                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 779
 780                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 781                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 782                 {
 783                         lane_count = intel_dp->lane_count;
 784                         break;
 785                 }
 786         }
 787
 788         /*
 789          * Compute the GMCH and Link ratios. The '3' here is
 790          * the number of bytes_per_pixel post-LUT, which we always
 791          * set up for 8-bits of R/G/B, or 3 bytes total.
 792          */
 793         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 794                              mode->clock, adjusted_mode->clock, &m_n);
 795
 796         if (HAS_PCH_SPLIT(dev)) {
 797                 I915_WRITE(TRANSDATA_M1(pipe),
 798                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 799                            m_n.gmch_m);
 800                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 801                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 802                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 803         } else if (IS_VALLEYVIEW(dev)) {
 804                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 805                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 806                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 807                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 808         } else {
 809                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 810                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 811                            m_n.gmch_m);
 812                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 813                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 814                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 815         }
 816 }
 817
 818 static void
 819 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 820                   struct drm_display_mode *adjusted_mode)
 821 {
 822         struct drm_device *dev = encoder->dev;
 823         struct drm_i915_private *dev_priv = dev->dev_private;
 824         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 825         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 827
 828         /*
 829          * There are four kinds of DP registers:
 830          *
 831          *      IBX PCH
 832          *      SNB CPU
 833          *      IVB CPU
 834          *      CPT PCH
 835          *
 836          * IBX PCH and CPU are the same for almost everything,
 837          * except that the CPU DP PLL is configured in this
 838          * register
 839          *
 840          * CPT PCH is quite different, having many bits moved
 841          * to the TRANS_DP_CTL register instead. That
 842          * configuration happens (oddly) in ironlake_pch_enable
 843          */
 844
 845         /* Preserve the BIOS-computed detected bit. This is
 846          * supposed to be read-only.
 847          */
 848         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 849
 850         /* Handle DP bits in common between all three register formats */
 851         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 852
 853         switch (intel_dp->lane_count) {
 854         case 1:
 855                 intel_dp->DP |= DP_PORT_WIDTH_1;
 856                 break;
 857         case 2:
 858                 intel_dp->DP |= DP_PORT_WIDTH_2;
 859                 break;
 860         case 4:
 861                 intel_dp->DP |= DP_PORT_WIDTH_4;
 862                 break;
 863         }
 864         if (intel_dp->has_audio) {
 865                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 866                                  pipe_name(intel_crtc->pipe));
 867                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 868                 intel_write_eld(encoder, adjusted_mode);
 869         }
 870         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 871         intel_dp->link_configuration[0] = intel_dp->link_bw;
 872         intel_dp->link_configuration[1] = intel_dp->lane_count;
 873         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 874         /*
 875          * Check for DPCD version > 1.1 and enhanced framing support
 876          */
 877         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 878             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 879                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 880         }
 881
 882         /* Split out the IBX/CPU vs CPT settings */
 883
 884         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 885                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 886                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 887                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 888                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 889                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 890
 891                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 892                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 893
 894                 intel_dp->DP |= intel_crtc->pipe << 29;
 895
 896                 /* don't miss out required setting for eDP */
 897                 if (adjusted_mode->clock < 200000)
 898                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 899                 else
 900                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 901         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 902                 intel_dp->DP |= intel_dp->color_range;
 903
 904                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 905                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 906                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 907                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 908                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 909
 910                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 911                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 912
 913                 if (intel_crtc->pipe == 1)
 914                         intel_dp->DP |= DP_PIPEB_SELECT;
 915
 916                 if (is_cpu_edp(intel_dp)) {
 917                         /* don't miss out required setting for eDP */
 918                         if (adjusted_mode->clock < 200000)
 919                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 920                         else
 921                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 922                 }
 923         } else {
 924                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 925         }
 926 }
 927
 928 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 929 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 930
 931 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 932 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 933
 934 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 935 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 936
 937 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 938                                        u32 mask,
 939                                        u32 value)
 940 {
 941         struct drm_device *dev = intel_dp->base.base.dev;
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943
 944         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 945                       mask, value,
 946                       I915_READ(PCH_PP_STATUS),
 947                       I915_READ(PCH_PP_CONTROL));
 948
 949         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 950                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 951                           I915_READ(PCH_PP_STATUS),
 952                           I915_READ(PCH_PP_CONTROL));
 953         }
 954 }
 955
 956 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 957 {
 958         DRM_DEBUG_KMS("Wait for panel power on\n");
 959         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 960 }
 961
 962 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 963 {
 964         DRM_DEBUG_KMS("Wait for panel power off time\n");
 965         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 966 }
 967
 968 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 969 {
 970         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 971         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 972 }
 973
 974
 975 /* Read the current pp_control value, unlocking the register if it
 976  * is locked
 977  */
 978
 979 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 980 {
 981         u32     control = I915_READ(PCH_PP_CONTROL);
 982
 983         control &= ~PANEL_UNLOCK_MASK;
 984         control |= PANEL_UNLOCK_REGS;
 985         return control;
 986 }
 987
 988 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 989 {
 990         struct drm_device *dev = intel_dp->base.base.dev;
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         u32 pp;
 993
 994         if (!is_edp(intel_dp))
 995                 return;
 996         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 997
 998         WARN(intel_dp->want_panel_vdd,
 999              "eDP VDD already requested on\n");
1000
1001         intel_dp->want_panel_vdd = true;
1002
1003         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1004                 DRM_DEBUG_KMS("eDP VDD already on\n");
1005                 return;
1006         }
1007
1008         if (!ironlake_edp_have_panel_power(intel_dp))
1009                 ironlake_wait_panel_power_cycle(intel_dp);
1010
1011         pp = ironlake_get_pp_control(dev_priv);
1012         pp |= EDP_FORCE_VDD;
1013         I915_WRITE(PCH_PP_CONTROL, pp);
1014         POSTING_READ(PCH_PP_CONTROL);
1015         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1016                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1017
1018         /*
1019          * If the panel wasn't on, delay before accessing aux channel
1020          */
1021         if (!ironlake_edp_have_panel_power(intel_dp)) {
1022                 DRM_DEBUG_KMS("eDP was not running\n");
1023                 msleep(intel_dp->panel_power_up_delay);
1024         }
1025 }
1026
1027 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1028 {
1029         struct drm_device *dev = intel_dp->base.base.dev;
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031         u32 pp;
1032
1033         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1034                 pp = ironlake_get_pp_control(dev_priv);
1035                 pp &= ~EDP_FORCE_VDD;
1036                 I915_WRITE(PCH_PP_CONTROL, pp);
1037                 POSTING_READ(PCH_PP_CONTROL);
1038
1039                 /* Make sure sequencer is idle before allowing subsequent activity */
1040                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1041                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1042
1043                 msleep(intel_dp->panel_power_down_delay);
1044         }
1045 }
1046
1047 static void ironlake_panel_vdd_work(struct work_struct *__work)
1048 {
1049         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1050                                                  struct intel_dp, panel_vdd_work);
1051         struct drm_device *dev = intel_dp->base.base.dev;
1052
1053         mutex_lock(&dev->mode_config.mutex);
1054         ironlake_panel_vdd_off_sync(intel_dp);
1055         mutex_unlock(&dev->mode_config.mutex);
1056 }
1057
1058 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1059 {
1060         if (!is_edp(intel_dp))
1061                 return;
1062
1063         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1064         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1065
1066         intel_dp->want_panel_vdd = false;
1067
1068         if (sync) {
1069                 ironlake_panel_vdd_off_sync(intel_dp);
1070         } else {
1071                 /*
1072                  * Queue the timer to fire a long
1073                  * time from now (relative to the power down delay)
1074                  * to keep the panel power up across a sequence of operations
1075                  */
1076                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1077                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1078         }
1079 }
1080
1081 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1082 {
1083         struct drm_device *dev = intel_dp->base.base.dev;
1084         struct drm_i915_private *dev_priv = dev->dev_private;
1085         u32 pp;
1086
1087         if (!is_edp(intel_dp))
1088                 return;
1089
1090         DRM_DEBUG_KMS("Turn eDP power on\n");
1091
1092         if (ironlake_edp_have_panel_power(intel_dp)) {
1093                 DRM_DEBUG_KMS("eDP power already on\n");
1094                 return;
1095         }
1096
1097         ironlake_wait_panel_power_cycle(intel_dp);
1098
1099         pp = ironlake_get_pp_control(dev_priv);
1100         if (IS_GEN5(dev)) {
1101                 /* ILK workaround: disable reset around power sequence */
1102                 pp &= ~PANEL_POWER_RESET;
1103                 I915_WRITE(PCH_PP_CONTROL, pp);
1104                 POSTING_READ(PCH_PP_CONTROL);
1105         }
1106
1107         pp |= POWER_TARGET_ON;
1108         if (!IS_GEN5(dev))
1109                 pp |= PANEL_POWER_RESET;
1110
1111         I915_WRITE(PCH_PP_CONTROL, pp);
1112         POSTING_READ(PCH_PP_CONTROL);
1113
1114         ironlake_wait_panel_on(intel_dp);
1115
1116         if (IS_GEN5(dev)) {
1117                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1118                 I915_WRITE(PCH_PP_CONTROL, pp);
1119                 POSTING_READ(PCH_PP_CONTROL);
1120         }
1121 }
1122
1123 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1124 {
1125         struct drm_device *dev = intel_dp->base.base.dev;
1126         struct drm_i915_private *dev_priv = dev->dev_private;
1127         u32 pp;
1128
1129         if (!is_edp(intel_dp))
1130                 return;
1131
1132         DRM_DEBUG_KMS("Turn eDP power off\n");
1133
1134         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1135
1136         pp = ironlake_get_pp_control(dev_priv);
1137         /* We need to switch off panel power _and_ force vdd, for otherwise some
1138          * panels get very unhappy and cease to work. */
1139         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1140         I915_WRITE(PCH_PP_CONTROL, pp);
1141         POSTING_READ(PCH_PP_CONTROL);
1142
1143         intel_dp->want_panel_vdd = false;
1144
1145         ironlake_wait_panel_off(intel_dp);
1146 }
1147
1148 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1149 {
1150         struct drm_device *dev = intel_dp->base.base.dev;
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         u32 pp;
1153
1154         if (!is_edp(intel_dp))
1155                 return;
1156
1157         DRM_DEBUG_KMS("\n");
1158         /*
1159          * If we enable the backlight right away following a panel power
1160          * on, we may see slight flicker as the panel syncs with the eDP
1161          * link.  So delay a bit to make sure the image is solid before
1162          * allowing it to appear.
1163          */
1164         msleep(intel_dp->backlight_on_delay);
1165         pp = ironlake_get_pp_control(dev_priv);
1166         pp |= EDP_BLC_ENABLE;
1167         I915_WRITE(PCH_PP_CONTROL, pp);
1168         POSTING_READ(PCH_PP_CONTROL);
1169 }
1170
1171 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1172 {
1173         struct drm_device *dev = intel_dp->base.base.dev;
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         u32 pp;
1176
1177         if (!is_edp(intel_dp))
1178                 return;
1179
1180         DRM_DEBUG_KMS("\n");
1181         pp = ironlake_get_pp_control(dev_priv);
1182         pp &= ~EDP_BLC_ENABLE;
1183         I915_WRITE(PCH_PP_CONTROL, pp);
1184         POSTING_READ(PCH_PP_CONTROL);
1185         msleep(intel_dp->backlight_off_delay);
1186 }
1187
1188 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1189 {
1190         struct drm_device *dev = intel_dp->base.base.dev;
1191         struct drm_crtc *crtc = intel_dp->base.base.crtc;
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193         u32 dpa_ctl;
1194
1195         assert_pipe_disabled(dev_priv,
1196                              to_intel_crtc(crtc)->pipe);
1197
1198         DRM_DEBUG_KMS("\n");
1199         dpa_ctl = I915_READ(DP_A);
1200         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1201         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1202
1203         /* We don't adjust intel_dp->DP while tearing down the link, to
1204          * facilitate link retraining (e.g. after hotplug). Hence clear all
1205          * enable bits here to ensure that we don't enable too much. */
1206         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1207         intel_dp->DP |= DP_PLL_ENABLE;
1208         I915_WRITE(DP_A, intel_dp->DP);
1209         POSTING_READ(DP_A);
1210         udelay(200);
1211 }
1212
1213 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1214 {
1215         struct drm_device *dev = intel_dp->base.base.dev;
1216         struct drm_crtc *crtc = intel_dp->base.base.crtc;
1217         struct drm_i915_private *dev_priv = dev->dev_private;
1218         u32 dpa_ctl;
1219
1220         assert_pipe_disabled(dev_priv,
1221                              to_intel_crtc(crtc)->pipe);
1222
1223         dpa_ctl = I915_READ(DP_A);
1224         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1225              "dp pll off, should be on\n");
1226         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1227
1228         /* We can't rely on the value tracked for the DP register in
1229          * intel_dp->DP because link_down must not change that (otherwise link
1230          * re-training will fail. */
1231         dpa_ctl &= ~DP_PLL_ENABLE;
1232         I915_WRITE(DP_A, dpa_ctl);
1233         POSTING_READ(DP_A);
1234         udelay(200);
1235 }
1236
1237 /* If the sink supports it, try to set the power state appropriately */
1238 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1239 {
1240         int ret, i;
1241
1242         /* Should have a valid DPCD by this point */
1243         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1244                 return;
1245
1246         if (mode != DRM_MODE_DPMS_ON) {
1247                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1248                                                   DP_SET_POWER_D3);
1249                 if (ret != 1)
1250                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1251         } else {
1252                 /*
1253                  * When turning on, we need to retry for 1ms to give the sink
1254                  * time to wake up.
1255                  */
1256                 for (i = 0; i < 3; i++) {
1257                         ret = intel_dp_aux_native_write_1(intel_dp,
1258                                                           DP_SET_POWER,
1259                                                           DP_SET_POWER_D0);
1260                         if (ret == 1)
1261                                 break;
1262                         msleep(1);
1263                 }
1264         }
1265 }
1266
1267 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1268                                   enum pipe *pipe)
1269 {
1270         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1271         struct drm_device *dev = encoder->base.dev;
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 tmp = I915_READ(intel_dp->output_reg);
1274
1275         if (!(tmp & DP_PORT_EN))
1276                 return false;
1277
1278         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1279                 *pipe = PORT_TO_PIPE_CPT(tmp);
1280         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1281                 *pipe = PORT_TO_PIPE(tmp);
1282         } else {
1283                 u32 trans_sel;
1284                 u32 trans_dp;
1285                 int i;
1286
1287                 switch (intel_dp->output_reg) {
1288                 case PCH_DP_B:
1289                         trans_sel = TRANS_DP_PORT_SEL_B;
1290                         break;
1291                 case PCH_DP_C:
1292                         trans_sel = TRANS_DP_PORT_SEL_C;
1293                         break;
1294                 case PCH_DP_D:
1295                         trans_sel = TRANS_DP_PORT_SEL_D;
1296                         break;
1297                 default:
1298                         return true;
1299                 }
1300
1301                 for_each_pipe(i) {
1302                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1303                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1304                                 *pipe = i;
1305                                 return true;
1306                         }
1307                 }
1308         }
1309
1310         DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1311
1312         return true;
1313 }
1314
1315 static void intel_disable_dp(struct intel_encoder *encoder)
1316 {
1317         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1318
1319         /* Make sure the panel is off before trying to change the mode. But also
1320          * ensure that we have vdd while we switch off the panel. */
1321         ironlake_edp_panel_vdd_on(intel_dp);
1322         ironlake_edp_backlight_off(intel_dp);
1323         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1324         ironlake_edp_panel_off(intel_dp);
1325
1326         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1327         if (!is_cpu_edp(intel_dp))
1328                 intel_dp_link_down(intel_dp);
1329 }
1330
1331 static void intel_post_disable_dp(struct intel_encoder *encoder)
1332 {
1333         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1334
1335         if (is_cpu_edp(intel_dp)) {
1336                 intel_dp_link_down(intel_dp);
1337                 ironlake_edp_pll_off(intel_dp);
1338         }
1339 }
1340
1341 static void intel_enable_dp(struct intel_encoder *encoder)
1342 {
1343         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1344         struct drm_device *dev = encoder->base.dev;
1345         struct drm_i915_private *dev_priv = dev->dev_private;
1346         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1347
1348         if (WARN_ON(dp_reg & DP_PORT_EN))
1349                 return;
1350
1351         ironlake_edp_panel_vdd_on(intel_dp);
1352         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1353         intel_dp_start_link_train(intel_dp);
1354         ironlake_edp_panel_on(intel_dp);
1355         ironlake_edp_panel_vdd_off(intel_dp, true);
1356         intel_dp_complete_link_train(intel_dp);
1357         ironlake_edp_backlight_on(intel_dp);
1358 }
1359
1360 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1361 {
1362         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1363
1364         if (is_cpu_edp(intel_dp))
1365                 ironlake_edp_pll_on(intel_dp);
1366 }
1367
1368 /*
1369  * Native read with retry for link status and receiver capability reads for
1370  * cases where the sink may still be asleep.
1371  */
1372 static bool
1373 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1374                                uint8_t *recv, int recv_bytes)
1375 {
1376         int ret, i;
1377
1378         /*
1379          * Sinks are *supposed* to come up within 1ms from an off state,
1380          * but we're also supposed to retry 3 times per the spec.
1381          */
1382         for (i = 0; i < 3; i++) {
1383                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1384                                                recv_bytes);
1385                 if (ret == recv_bytes)
1386                         return true;
1387                 msleep(1);
1388         }
1389
1390         return false;
1391 }
1392
1393 /*
1394  * Fetch AUX CH registers 0x202 - 0x207 which contain
1395  * link status information
1396  */
1397 static bool
1398 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1399 {
1400         return intel_dp_aux_native_read_retry(intel_dp,
1401                                               DP_LANE0_1_STATUS,
1402                                               link_status,
1403                                               DP_LINK_STATUS_SIZE);
1404 }
1405
1406 static uint8_t
1407 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1408                      int r)
1409 {
1410         return link_status[r - DP_LANE0_1_STATUS];
1411 }
1412
1413 static uint8_t
1414 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1415                                  int lane)
1416 {
1417         int         s = ((lane & 1) ?
1418                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1419                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1420         uint8_t l = adjust_request[lane>>1];
1421
1422         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1423 }
1424
1425 static uint8_t
1426 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1427                                       int lane)
1428 {
1429         int         s = ((lane & 1) ?
1430                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1431                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1432         uint8_t l = adjust_request[lane>>1];
1433
1434         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1435 }
1436
1437
1438 #if 0
1439 static char     *voltage_names[] = {
1440         "0.4V", "0.6V", "0.8V", "1.2V"
1441 };
1442 static char     *pre_emph_names[] = {
1443         "0dB", "3.5dB", "6dB", "9.5dB"
1444 };
1445 static char     *link_train_names[] = {
1446         "pattern 1", "pattern 2", "idle", "off"
1447 };
1448 #endif
1449
1450 /*
1451  * These are source-specific values; current Intel hardware supports
1452  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1453  */
1454
1455 static uint8_t
1456 intel_dp_voltage_max(struct intel_dp *intel_dp)
1457 {
1458         struct drm_device *dev = intel_dp->base.base.dev;
1459
1460         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1461                 return DP_TRAIN_VOLTAGE_SWING_800;
1462         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1463                 return DP_TRAIN_VOLTAGE_SWING_1200;
1464         else
1465                 return DP_TRAIN_VOLTAGE_SWING_800;
1466 }
1467
1468 static uint8_t
1469 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1470 {
1471         struct drm_device *dev = intel_dp->base.base.dev;
1472
1473         if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1474                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1475                 case DP_TRAIN_VOLTAGE_SWING_400:
1476                         return DP_TRAIN_PRE_EMPHASIS_6;
1477                 case DP_TRAIN_VOLTAGE_SWING_600:
1478                 case DP_TRAIN_VOLTAGE_SWING_800:
1479                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1480                 default:
1481                         return DP_TRAIN_PRE_EMPHASIS_0;
1482                 }
1483         } else {
1484                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1485                 case DP_TRAIN_VOLTAGE_SWING_400:
1486                         return DP_TRAIN_PRE_EMPHASIS_6;
1487                 case DP_TRAIN_VOLTAGE_SWING_600:
1488                         return DP_TRAIN_PRE_EMPHASIS_6;
1489                 case DP_TRAIN_VOLTAGE_SWING_800:
1490                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1491                 case DP_TRAIN_VOLTAGE_SWING_1200:
1492                 default:
1493                         return DP_TRAIN_PRE_EMPHASIS_0;
1494                 }
1495         }
1496 }
1497
1498 static void
1499 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1500 {
1501         uint8_t v = 0;
1502         uint8_t p = 0;
1503         int lane;
1504         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1505         uint8_t voltage_max;
1506         uint8_t preemph_max;
1507
1508         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1509                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1510                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1511
1512                 if (this_v > v)
1513                         v = this_v;
1514                 if (this_p > p)
1515                         p = this_p;
1516         }
1517
1518         voltage_max = intel_dp_voltage_max(intel_dp);
1519         if (v >= voltage_max)
1520                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1521
1522         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1523         if (p >= preemph_max)
1524                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1525
1526         for (lane = 0; lane < 4; lane++)
1527                 intel_dp->train_set[lane] = v | p;
1528 }
1529
1530 static uint32_t
1531 intel_dp_signal_levels(uint8_t train_set)
1532 {
1533         uint32_t        signal_levels = 0;
1534
1535         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1536         case DP_TRAIN_VOLTAGE_SWING_400:
1537         default:
1538                 signal_levels |= DP_VOLTAGE_0_4;
1539                 break;
1540         case DP_TRAIN_VOLTAGE_SWING_600:
1541                 signal_levels |= DP_VOLTAGE_0_6;
1542                 break;
1543         case DP_TRAIN_VOLTAGE_SWING_800:
1544                 signal_levels |= DP_VOLTAGE_0_8;
1545                 break;
1546         case DP_TRAIN_VOLTAGE_SWING_1200:
1547                 signal_levels |= DP_VOLTAGE_1_2;
1548                 break;
1549         }
1550         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1551         case DP_TRAIN_PRE_EMPHASIS_0:
1552         default:
1553                 signal_levels |= DP_PRE_EMPHASIS_0;
1554                 break;
1555         case DP_TRAIN_PRE_EMPHASIS_3_5:
1556                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1557                 break;
1558         case DP_TRAIN_PRE_EMPHASIS_6:
1559                 signal_levels |= DP_PRE_EMPHASIS_6;
1560                 break;
1561         case DP_TRAIN_PRE_EMPHASIS_9_5:
1562                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1563                 break;
1564         }
1565         return signal_levels;
1566 }
1567
1568 /* Gen6's DP voltage swing and pre-emphasis control */
1569 static uint32_t
1570 intel_gen6_edp_signal_levels(uint8_t train_set)
1571 {
1572         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1573                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1574         switch (signal_levels) {
1575         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1576         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1577                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1578         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1579                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1580         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1581         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1582                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1583         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1584         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1585                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1586         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1587         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1588                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1589         default:
1590                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1591                               "0x%x\n", signal_levels);
1592                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1593         }
1594 }
1595
1596 /* Gen7's DP voltage swing and pre-emphasis control */
1597 static uint32_t
1598 intel_gen7_edp_signal_levels(uint8_t train_set)
1599 {
1600         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1601                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1602         switch (signal_levels) {
1603         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1604                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1605         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1606                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1607         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1608                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1609
1610         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1611                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1612         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1613                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1614
1615         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1616                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1617         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1618                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1619
1620         default:
1621                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1622                               "0x%x\n", signal_levels);
1623                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1624         }
1625 }
1626
1627 static uint8_t
1628 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1629                       int lane)
1630 {
1631         int s = (lane & 1) * 4;
1632         uint8_t l = link_status[lane>>1];
1633
1634         return (l >> s) & 0xf;
1635 }
1636
1637 /* Check for clock recovery is done on all channels */
1638 static bool
1639 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1640 {
1641         int lane;
1642         uint8_t lane_status;
1643
1644         for (lane = 0; lane < lane_count; lane++) {
1645                 lane_status = intel_get_lane_status(link_status, lane);
1646                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1647                         return false;
1648         }
1649         return true;
1650 }
1651
1652 /* Check to see if channel eq is done on all channels */
1653 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1654                          DP_LANE_CHANNEL_EQ_DONE|\
1655                          DP_LANE_SYMBOL_LOCKED)
1656 static bool
1657 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1658 {
1659         uint8_t lane_align;
1660         uint8_t lane_status;
1661         int lane;
1662
1663         lane_align = intel_dp_link_status(link_status,
1664                                           DP_LANE_ALIGN_STATUS_UPDATED);
1665         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1666                 return false;
1667         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1668                 lane_status = intel_get_lane_status(link_status, lane);
1669                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1670                         return false;
1671         }
1672         return true;
1673 }
1674
1675 static bool
1676 intel_dp_set_link_train(struct intel_dp *intel_dp,
1677                         uint32_t dp_reg_value,
1678                         uint8_t dp_train_pat)
1679 {
1680         struct drm_device *dev = intel_dp->base.base.dev;
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682         int ret;
1683
1684         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1685                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1686
1687                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1688                 case DP_TRAINING_PATTERN_DISABLE:
1689                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1690                         break;
1691                 case DP_TRAINING_PATTERN_1:
1692                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1693                         break;
1694                 case DP_TRAINING_PATTERN_2:
1695                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1696                         break;
1697                 case DP_TRAINING_PATTERN_3:
1698                         DRM_ERROR("DP training pattern 3 not supported\n");
1699                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1700                         break;
1701                 }
1702
1703         } else {
1704                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1705
1706                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1707                 case DP_TRAINING_PATTERN_DISABLE:
1708                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1709                         break;
1710                 case DP_TRAINING_PATTERN_1:
1711                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1712                         break;
1713                 case DP_TRAINING_PATTERN_2:
1714                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1715                         break;
1716                 case DP_TRAINING_PATTERN_3:
1717                         DRM_ERROR("DP training pattern 3 not supported\n");
1718                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1719                         break;
1720                 }
1721         }
1722
1723         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1724         POSTING_READ(intel_dp->output_reg);
1725
1726         intel_dp_aux_native_write_1(intel_dp,
1727                                     DP_TRAINING_PATTERN_SET,
1728                                     dp_train_pat);
1729
1730         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1731             DP_TRAINING_PATTERN_DISABLE) {
1732                 ret = intel_dp_aux_native_write(intel_dp,
1733                                                 DP_TRAINING_LANE0_SET,
1734                                                 intel_dp->train_set,
1735                                                 intel_dp->lane_count);
1736                 if (ret != intel_dp->lane_count)
1737                         return false;
1738         }
1739
1740         return true;
1741 }
1742
1743 /* Enable corresponding port and start training pattern 1 */
1744 static void
1745 intel_dp_start_link_train(struct intel_dp *intel_dp)
1746 {
1747         struct drm_device *dev = intel_dp->base.base.dev;
1748         int i;
1749         uint8_t voltage;
1750         bool clock_recovery = false;
1751         int voltage_tries, loop_tries;
1752         uint32_t DP = intel_dp->DP;
1753
1754         /* Write the link configuration data */
1755         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1756                                   intel_dp->link_configuration,
1757                                   DP_LINK_CONFIGURATION_SIZE);
1758
1759         DP |= DP_PORT_EN;
1760
1761         memset(intel_dp->train_set, 0, 4);
1762         voltage = 0xff;
1763         voltage_tries = 0;
1764         loop_tries = 0;
1765         clock_recovery = false;
1766         for (;;) {
1767                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1768                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1769                 uint32_t    signal_levels;
1770
1771
1772                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1773                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1774                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1775                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1776                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1777                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1778                 } else {
1779                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1780                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1781                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1782                 }
1783
1784                 if (!intel_dp_set_link_train(intel_dp, DP,
1785                                              DP_TRAINING_PATTERN_1 |
1786                                              DP_LINK_SCRAMBLING_DISABLE))
1787                         break;
1788                 /* Set training pattern 1 */
1789
1790                 udelay(100);
1791                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1792                         DRM_ERROR("failed to get link status\n");
1793                         break;
1794                 }
1795
1796                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1797                         DRM_DEBUG_KMS("clock recovery OK\n");
1798                         clock_recovery = true;
1799                         break;
1800                 }
1801
1802                 /* Check to see if we've tried the max voltage */
1803                 for (i = 0; i < intel_dp->lane_count; i++)
1804                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1805                                 break;
1806                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1807                         ++loop_tries;
1808                         if (loop_tries == 5) {
1809                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1810                                 break;
1811                         }
1812                         memset(intel_dp->train_set, 0, 4);
1813                         voltage_tries = 0;
1814                         continue;
1815                 }
1816
1817                 /* Check to see if we've tried the same voltage 5 times */
1818                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1819                         ++voltage_tries;
1820                         if (voltage_tries == 5) {
1821                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1822                                 break;
1823                         }
1824                 } else
1825                         voltage_tries = 0;
1826                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1827
1828                 /* Compute new intel_dp->train_set as requested by target */
1829                 intel_get_adjust_train(intel_dp, link_status);
1830         }
1831
1832         intel_dp->DP = DP;
1833 }
1834
1835 static void
1836 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1837 {
1838         struct drm_device *dev = intel_dp->base.base.dev;
1839         bool channel_eq = false;
1840         int tries, cr_tries;
1841         uint32_t DP = intel_dp->DP;
1842
1843         /* channel equalization */
1844         tries = 0;
1845         cr_tries = 0;
1846         channel_eq = false;
1847         for (;;) {
1848                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1849                 uint32_t    signal_levels;
1850                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1851
1852                 if (cr_tries > 5) {
1853                         DRM_ERROR("failed to train DP, aborting\n");
1854                         intel_dp_link_down(intel_dp);
1855                         break;
1856                 }
1857
1858                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1859                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1860                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1861                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1862                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1863                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1864                 } else {
1865                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1866                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1867                 }
1868
1869                 /* channel eq pattern */
1870                 if (!intel_dp_set_link_train(intel_dp, DP,
1871                                              DP_TRAINING_PATTERN_2 |
1872                                              DP_LINK_SCRAMBLING_DISABLE))
1873                         break;
1874
1875                 udelay(400);
1876                 if (!intel_dp_get_link_status(intel_dp, link_status))
1877                         break;
1878
1879                 /* Make sure clock is still ok */
1880                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1881                         intel_dp_start_link_train(intel_dp);
1882                         cr_tries++;
1883                         continue;
1884                 }
1885
1886                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1887                         channel_eq = true;
1888                         break;
1889                 }
1890
1891                 /* Try 5 times, then try clock recovery if that fails */
1892                 if (tries > 5) {
1893                         intel_dp_link_down(intel_dp);
1894                         intel_dp_start_link_train(intel_dp);
1895                         tries = 0;
1896                         cr_tries++;
1897                         continue;
1898                 }
1899
1900                 /* Compute new intel_dp->train_set as requested by target */
1901                 intel_get_adjust_train(intel_dp, link_status);
1902                 ++tries;
1903         }
1904
1905         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1906 }
1907
1908 static void
1909 intel_dp_link_down(struct intel_dp *intel_dp)
1910 {
1911         struct drm_device *dev = intel_dp->base.base.dev;
1912         struct drm_i915_private *dev_priv = dev->dev_private;
1913         uint32_t DP = intel_dp->DP;
1914
1915         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1916                 return;
1917
1918         DRM_DEBUG_KMS("\n");
1919
1920         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1921                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1922                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1923         } else {
1924                 DP &= ~DP_LINK_TRAIN_MASK;
1925                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1926         }
1927         POSTING_READ(intel_dp->output_reg);
1928
1929         msleep(17);
1930
1931         if (HAS_PCH_IBX(dev) &&
1932             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1933                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1934
1935                 /* Hardware workaround: leaving our transcoder select
1936                  * set to transcoder B while it's off will prevent the
1937                  * corresponding HDMI output on transcoder A.
1938                  *
1939                  * Combine this with another hardware workaround:
1940                  * transcoder select bit can only be cleared while the
1941                  * port is enabled.
1942                  */
1943                 DP &= ~DP_PIPEB_SELECT;
1944                 I915_WRITE(intel_dp->output_reg, DP);
1945
1946                 /* Changes to enable or select take place the vblank
1947                  * after being written.
1948                  */
1949                 if (crtc == NULL) {
1950                         /* We can arrive here never having been attached
1951                          * to a CRTC, for instance, due to inheriting
1952                          * random state from the BIOS.
1953                          *
1954                          * If the pipe is not running, play safe and
1955                          * wait for the clocks to stabilise before
1956                          * continuing.
1957                          */
1958                         POSTING_READ(intel_dp->output_reg);
1959                         msleep(50);
1960                 } else
1961                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1962         }
1963
1964         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1965         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1966         POSTING_READ(intel_dp->output_reg);
1967         msleep(intel_dp->panel_power_down_delay);
1968 }
1969
1970 static bool
1971 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1972 {
1973         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1974                                            sizeof(intel_dp->dpcd)) == 0)
1975                 return false; /* aux transfer failed */
1976
1977         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1978                 return false; /* DPCD not present */
1979
1980         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1981               DP_DWN_STRM_PORT_PRESENT))
1982                 return true; /* native DP sink */
1983
1984         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
1985                 return true; /* no per-port downstream info */
1986
1987         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
1988                                            intel_dp->downstream_ports,
1989                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
1990                 return false; /* downstream port status fetch failed */
1991
1992         return true;
1993 }
1994
1995 static void
1996 intel_dp_probe_oui(struct intel_dp *intel_dp)
1997 {
1998         u8 buf[3];
1999
2000         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2001                 return;
2002
2003         ironlake_edp_panel_vdd_on(intel_dp);
2004
2005         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2006                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2007                               buf[0], buf[1], buf[2]);
2008
2009         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2010                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2011                               buf[0], buf[1], buf[2]);
2012
2013         ironlake_edp_panel_vdd_off(intel_dp, false);
2014 }
2015
2016 static bool
2017 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2018 {
2019         int ret;
2020
2021         ret = intel_dp_aux_native_read_retry(intel_dp,
2022                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2023                                              sink_irq_vector, 1);
2024         if (!ret)
2025                 return false;
2026
2027         return true;
2028 }
2029
2030 static void
2031 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2032 {
2033         /* NAK by default */
2034         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2035 }
2036
2037 /*
2038  * According to DP spec
2039  * 5.1.2:
2040  *  1. Read DPCD
2041  *  2. Configure link according to Receiver Capabilities
2042  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2043  *  4. Check link status on receipt of hot-plug interrupt
2044  */
2045
2046 static void
2047 intel_dp_check_link_status(struct intel_dp *intel_dp)
2048 {
2049         u8 sink_irq_vector;
2050         u8 link_status[DP_LINK_STATUS_SIZE];
2051
2052         if (!intel_dp->base.connectors_active)
2053                 return;
2054
2055         if (WARN_ON(!intel_dp->base.base.crtc))
2056                 return;
2057
2058         /* Try to read receiver status if the link appears to be up */
2059         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2060                 intel_dp_link_down(intel_dp);
2061                 return;
2062         }
2063
2064         /* Now read the DPCD to see if it's actually running */
2065         if (!intel_dp_get_dpcd(intel_dp)) {
2066                 intel_dp_link_down(intel_dp);
2067                 return;
2068         }
2069
2070         /* Try to read the source of the interrupt */
2071         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2072             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2073                 /* Clear interrupt source */
2074                 intel_dp_aux_native_write_1(intel_dp,
2075                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2076                                             sink_irq_vector);
2077
2078                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2079                         intel_dp_handle_test_request(intel_dp);
2080                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2081                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2082         }
2083
2084         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2085                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2086                               drm_get_encoder_name(&intel_dp->base.base));
2087                 intel_dp_start_link_train(intel_dp);
2088                 intel_dp_complete_link_train(intel_dp);
2089         }
2090 }
2091
2092 /* XXX this is probably wrong for multiple downstream ports */
2093 static enum drm_connector_status
2094 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2095 {
2096         uint8_t *dpcd = intel_dp->dpcd;
2097         bool hpd;
2098         uint8_t type;
2099
2100         if (!intel_dp_get_dpcd(intel_dp))
2101                 return connector_status_disconnected;
2102
2103         /* if there's no downstream port, we're done */
2104         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2105                 return connector_status_connected;
2106
2107         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2108         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2109         if (hpd) {
2110                 uint8_t reg;
2111                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2112                                                     &reg, 1))
2113                         return connector_status_unknown;
2114                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2115                                               : connector_status_disconnected;
2116         }
2117
2118         /* If no HPD, poke DDC gently */
2119         if (drm_probe_ddc(&intel_dp->adapter))
2120                 return connector_status_connected;
2121
2122         /* Well we tried, say unknown for unreliable port types */
2123         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2124         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2125                 return connector_status_unknown;
2126
2127         /* Anything else is out of spec, warn and ignore */
2128         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2129         return connector_status_disconnected;
2130 }
2131
2132 static enum drm_connector_status
2133 ironlake_dp_detect(struct intel_dp *intel_dp)
2134 {
2135         enum drm_connector_status status;
2136
2137         /* Can't disconnect eDP, but you can close the lid... */
2138         if (is_edp(intel_dp)) {
2139                 status = intel_panel_detect(intel_dp->base.base.dev);
2140                 if (status == connector_status_unknown)
2141                         status = connector_status_connected;
2142                 return status;
2143         }
2144
2145         return intel_dp_detect_dpcd(intel_dp);
2146 }
2147
2148 static enum drm_connector_status
2149 g4x_dp_detect(struct intel_dp *intel_dp)
2150 {
2151         struct drm_device *dev = intel_dp->base.base.dev;
2152         struct drm_i915_private *dev_priv = dev->dev_private;
2153         uint32_t bit;
2154
2155         switch (intel_dp->output_reg) {
2156         case DP_B:
2157                 bit = DPB_HOTPLUG_LIVE_STATUS;
2158                 break;
2159         case DP_C:
2160                 bit = DPC_HOTPLUG_LIVE_STATUS;
2161                 break;
2162         case DP_D:
2163                 bit = DPD_HOTPLUG_LIVE_STATUS;
2164                 break;
2165         default:
2166                 return connector_status_unknown;
2167         }
2168
2169         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2170                 return connector_status_disconnected;
2171
2172         return intel_dp_detect_dpcd(intel_dp);
2173 }
2174
2175 static struct edid *
2176 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2177 {
2178         struct intel_dp *intel_dp = intel_attached_dp(connector);
2179         struct edid     *edid;
2180         int size;
2181
2182         if (is_edp(intel_dp)) {
2183                 if (!intel_dp->edid)
2184                         return NULL;
2185
2186                 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2187                 edid = kmalloc(size, GFP_KERNEL);
2188                 if (!edid)
2189                         return NULL;
2190
2191                 memcpy(edid, intel_dp->edid, size);
2192                 return edid;
2193         }
2194
2195         edid = drm_get_edid(connector, adapter);
2196         return edid;
2197 }
2198
2199 static int
2200 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2201 {
2202         struct intel_dp *intel_dp = intel_attached_dp(connector);
2203         int     ret;
2204
2205         if (is_edp(intel_dp)) {
2206                 drm_mode_connector_update_edid_property(connector,
2207                                                         intel_dp->edid);
2208                 ret = drm_add_edid_modes(connector, intel_dp->edid);
2209                 drm_edid_to_eld(connector,
2210                                 intel_dp->edid);
2211                 return intel_dp->edid_mode_count;
2212         }
2213
2214         ret = intel_ddc_get_modes(connector, adapter);
2215         return ret;
2216 }
2217
2218
2219 /**
2220  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2221  *
2222  * \return true if DP port is connected.
2223  * \return false if DP port is disconnected.
2224  */
2225 static enum drm_connector_status
2226 intel_dp_detect(struct drm_connector *connector, bool force)
2227 {
2228         struct intel_dp *intel_dp = intel_attached_dp(connector);
2229         struct drm_device *dev = intel_dp->base.base.dev;
2230         enum drm_connector_status status;
2231         struct edid *edid = NULL;
2232
2233         intel_dp->has_audio = false;
2234
2235         if (HAS_PCH_SPLIT(dev))
2236                 status = ironlake_dp_detect(intel_dp);
2237         else
2238                 status = g4x_dp_detect(intel_dp);
2239
2240         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2241                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2242                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2243                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2244
2245         if (status != connector_status_connected)
2246                 return status;
2247
2248         intel_dp_probe_oui(intel_dp);
2249
2250         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2251                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2252         } else {
2253                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2254                 if (edid) {
2255                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2256                         kfree(edid);
2257                 }
2258         }
2259
2260         return connector_status_connected;
2261 }
2262
2263 static int intel_dp_get_modes(struct drm_connector *connector)
2264 {
2265         struct intel_dp *intel_dp = intel_attached_dp(connector);
2266         struct drm_device *dev = intel_dp->base.base.dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         int ret;
2269
2270         /* We should parse the EDID data and find out if it has an audio sink
2271          */
2272
2273         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2274         if (ret) {
2275                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2276                         struct drm_display_mode *newmode;
2277                         list_for_each_entry(newmode, &connector->probed_modes,
2278                                             head) {
2279                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2280                                         intel_dp->panel_fixed_mode =
2281                                                 drm_mode_duplicate(dev, newmode);
2282                                         break;
2283                                 }
2284                         }
2285                 }
2286                 return ret;
2287         }
2288
2289         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2290         if (is_edp(intel_dp)) {
2291                 /* initialize panel mode from VBT if available for eDP */
2292                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2293                         intel_dp->panel_fixed_mode =
2294                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2295                         if (intel_dp->panel_fixed_mode) {
2296                                 intel_dp->panel_fixed_mode->type |=
2297                                         DRM_MODE_TYPE_PREFERRED;
2298                         }
2299                 }
2300                 if (intel_dp->panel_fixed_mode) {
2301                         struct drm_display_mode *mode;
2302                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2303                         drm_mode_probed_add(connector, mode);
2304                         return 1;
2305                 }
2306         }
2307         return 0;
2308 }
2309
2310 static bool
2311 intel_dp_detect_audio(struct drm_connector *connector)
2312 {
2313         struct intel_dp *intel_dp = intel_attached_dp(connector);
2314         struct edid *edid;
2315         bool has_audio = false;
2316
2317         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2318         if (edid) {
2319                 has_audio = drm_detect_monitor_audio(edid);
2320                 kfree(edid);
2321         }
2322
2323         return has_audio;
2324 }
2325
2326 static int
2327 intel_dp_set_property(struct drm_connector *connector,
2328                       struct drm_property *property,
2329                       uint64_t val)
2330 {
2331         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2332         struct intel_dp *intel_dp = intel_attached_dp(connector);
2333         int ret;
2334
2335         ret = drm_connector_property_set_value(connector, property, val);
2336         if (ret)
2337                 return ret;
2338
2339         if (property == dev_priv->force_audio_property) {
2340                 int i = val;
2341                 bool has_audio;
2342
2343                 if (i == intel_dp->force_audio)
2344                         return 0;
2345
2346                 intel_dp->force_audio = i;
2347
2348                 if (i == HDMI_AUDIO_AUTO)
2349                         has_audio = intel_dp_detect_audio(connector);
2350                 else
2351                         has_audio = (i == HDMI_AUDIO_ON);
2352
2353                 if (has_audio == intel_dp->has_audio)
2354                         return 0;
2355
2356                 intel_dp->has_audio = has_audio;
2357                 goto done;
2358         }
2359
2360         if (property == dev_priv->broadcast_rgb_property) {
2361                 if (val == !!intel_dp->color_range)
2362                         return 0;
2363
2364                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2365                 goto done;
2366         }
2367
2368         return -EINVAL;
2369
2370 done:
2371         if (intel_dp->base.base.crtc) {
2372                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2373                 intel_set_mode(crtc, &crtc->mode,
2374                                crtc->x, crtc->y, crtc->fb);
2375         }
2376
2377         return 0;
2378 }
2379
2380 static void
2381 intel_dp_destroy(struct drm_connector *connector)
2382 {
2383         struct drm_device *dev = connector->dev;
2384
2385         if (intel_dpd_is_edp(dev))
2386                 intel_panel_destroy_backlight(dev);
2387
2388         drm_sysfs_connector_remove(connector);
2389         drm_connector_cleanup(connector);
2390         kfree(connector);
2391 }
2392
2393 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2394 {
2395         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2396
2397         i2c_del_adapter(&intel_dp->adapter);
2398         drm_encoder_cleanup(encoder);
2399         if (is_edp(intel_dp)) {
2400                 kfree(intel_dp->edid);
2401                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2402                 ironlake_panel_vdd_off_sync(intel_dp);
2403         }
2404         kfree(intel_dp);
2405 }
2406
2407 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2408         .mode_fixup = intel_dp_mode_fixup,
2409         .mode_set = intel_dp_mode_set,
2410         .disable = intel_encoder_noop,
2411 };
2412
2413 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2414         .dpms = intel_connector_dpms,
2415         .detect = intel_dp_detect,
2416         .fill_modes = drm_helper_probe_single_connector_modes,
2417         .set_property = intel_dp_set_property,
2418         .destroy = intel_dp_destroy,
2419 };
2420
2421 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2422         .get_modes = intel_dp_get_modes,
2423         .mode_valid = intel_dp_mode_valid,
2424         .best_encoder = intel_best_encoder,
2425 };
2426
2427 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2428         .destroy = intel_dp_encoder_destroy,
2429 };
2430
2431 static void
2432 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2433 {
2434         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2435
2436         intel_dp_check_link_status(intel_dp);
2437 }
2438
2439 /* Return which DP Port should be selected for Transcoder DP control */
2440 int
2441 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2442 {
2443         struct drm_device *dev = crtc->dev;
2444         struct intel_encoder *encoder;
2445
2446         for_each_encoder_on_crtc(dev, crtc, encoder) {
2447                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2448
2449                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2450                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2451                         return intel_dp->output_reg;
2452         }
2453
2454         return -1;
2455 }
2456
2457 /* check the VBT to see whether the eDP is on DP-D port */
2458 bool intel_dpd_is_edp(struct drm_device *dev)
2459 {
2460         struct drm_i915_private *dev_priv = dev->dev_private;
2461         struct child_device_config *p_child;
2462         int i;
2463
2464         if (!dev_priv->child_dev_num)
2465                 return false;
2466
2467         for (i = 0; i < dev_priv->child_dev_num; i++) {
2468                 p_child = dev_priv->child_dev + i;
2469
2470                 if (p_child->dvo_port == PORT_IDPD &&
2471                     p_child->device_type == DEVICE_TYPE_eDP)
2472                         return true;
2473         }
2474         return false;
2475 }
2476
2477 static void
2478 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2479 {
2480         intel_attach_force_audio_property(connector);
2481         intel_attach_broadcast_rgb_property(connector);
2482 }
2483
2484 void
2485 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2486 {
2487         struct drm_i915_private *dev_priv = dev->dev_private;
2488         struct drm_connector *connector;
2489         struct intel_dp *intel_dp;
2490         struct intel_encoder *intel_encoder;
2491         struct intel_connector *intel_connector;
2492         const char *name = NULL;
2493         int type;
2494
2495         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2496         if (!intel_dp)
2497                 return;
2498
2499         intel_dp->output_reg = output_reg;
2500         intel_dp->port = port;
2501         /* Preserve the current hw state. */
2502         intel_dp->DP = I915_READ(intel_dp->output_reg);
2503
2504         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2505         if (!intel_connector) {
2506                 kfree(intel_dp);
2507                 return;
2508         }
2509         intel_encoder = &intel_dp->base;
2510
2511         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2512                 if (intel_dpd_is_edp(dev))
2513                         intel_dp->is_pch_edp = true;
2514
2515         /*
2516          * FIXME : We need to initialize built-in panels before external panels.
2517          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2518          */
2519         if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2520                 type = DRM_MODE_CONNECTOR_eDP;
2521                 intel_encoder->type = INTEL_OUTPUT_EDP;
2522         } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2523                 type = DRM_MODE_CONNECTOR_eDP;
2524                 intel_encoder->type = INTEL_OUTPUT_EDP;
2525         } else {
2526                 type = DRM_MODE_CONNECTOR_DisplayPort;
2527                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2528         }
2529
2530         connector = &intel_connector->base;
2531         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2532         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2533
2534         connector->polled = DRM_CONNECTOR_POLL_HPD;
2535
2536         intel_encoder->cloneable = false;
2537
2538         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2539                           ironlake_panel_vdd_work);
2540
2541         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2542
2543         connector->interlace_allowed = true;
2544         connector->doublescan_allowed = 0;
2545
2546         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2547                          DRM_MODE_ENCODER_TMDS);
2548         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2549
2550         intel_connector_attach_encoder(intel_connector, intel_encoder);
2551         drm_sysfs_connector_add(connector);
2552
2553         intel_encoder->enable = intel_enable_dp;
2554         intel_encoder->pre_enable = intel_pre_enable_dp;
2555         intel_encoder->disable = intel_disable_dp;
2556         intel_encoder->post_disable = intel_post_disable_dp;
2557         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2558         intel_connector->get_hw_state = intel_connector_get_hw_state;
2559
2560         /* Set up the DDC bus. */
2561         switch (port) {
2562         case PORT_A:
2563                 name = "DPDDC-A";
2564                 break;
2565         case PORT_B:
2566                 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2567                 name = "DPDDC-B";
2568                 break;
2569         case PORT_C:
2570                 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2571                 name = "DPDDC-C";
2572                 break;
2573         case PORT_D:
2574                 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2575                 name = "DPDDC-D";
2576                 break;
2577         default:
2578                 WARN(1, "Invalid port %c\n", port_name(port));
2579                 break;
2580         }
2581
2582         /* Cache some DPCD data in the eDP case */
2583         if (is_edp(intel_dp)) {
2584                 struct edp_power_seq    cur, vbt;
2585                 u32 pp_on, pp_off, pp_div;
2586
2587                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2588                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2589                 pp_div = I915_READ(PCH_PP_DIVISOR);
2590
2591                 if (!pp_on || !pp_off || !pp_div) {
2592                         DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2593                         intel_dp_encoder_destroy(&intel_dp->base.base);
2594                         intel_dp_destroy(&intel_connector->base);
2595                         return;
2596                 }
2597
2598                 /* Pull timing values out of registers */
2599                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2600                         PANEL_POWER_UP_DELAY_SHIFT;
2601
2602                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2603                         PANEL_LIGHT_ON_DELAY_SHIFT;
2604
2605                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2606                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2607
2608                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2609                         PANEL_POWER_DOWN_DELAY_SHIFT;
2610
2611                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2612                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2613
2614                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2615                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2616
2617                 vbt = dev_priv->edp.pps;
2618
2619                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2620                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2621
2622 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2623
2624                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2625                 intel_dp->backlight_on_delay = get_delay(t8);
2626                 intel_dp->backlight_off_delay = get_delay(t9);
2627                 intel_dp->panel_power_down_delay = get_delay(t10);
2628                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2629
2630                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2631                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2632                               intel_dp->panel_power_cycle_delay);
2633
2634                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2635                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2636         }
2637
2638         intel_dp_i2c_init(intel_dp, intel_connector, name);
2639
2640         if (is_edp(intel_dp)) {
2641                 bool ret;
2642                 struct edid *edid;
2643
2644                 ironlake_edp_panel_vdd_on(intel_dp);
2645                 ret = intel_dp_get_dpcd(intel_dp);
2646                 ironlake_edp_panel_vdd_off(intel_dp, false);
2647
2648                 if (ret) {
2649                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2650                                 dev_priv->no_aux_handshake =
2651                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2652                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2653                 } else {
2654                         /* if this fails, presume the device is a ghost */
2655                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2656                         intel_dp_encoder_destroy(&intel_dp->base.base);
2657                         intel_dp_destroy(&intel_connector->base);
2658                         return;
2659                 }
2660
2661                 ironlake_edp_panel_vdd_on(intel_dp);
2662                 edid = drm_get_edid(connector, &intel_dp->adapter);
2663                 if (edid) {
2664                         drm_mode_connector_update_edid_property(connector,
2665                                                                 edid);
2666                         intel_dp->edid_mode_count =
2667                                 drm_add_edid_modes(connector, edid);
2668                         drm_edid_to_eld(connector, edid);
2669                         intel_dp->edid = edid;
2670                 }
2671                 ironlake_edp_panel_vdd_off(intel_dp, false);
2672         }
2673
2674         intel_encoder->hot_plug = intel_dp_hot_plug;
2675
2676         if (is_edp(intel_dp)) {
2677                 dev_priv->int_edp_connector = connector;
2678                 intel_panel_setup_backlight(dev);
2679         }
2680
2681         intel_dp_add_properties(intel_dp, connector);
2682
2683         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2684          * 0xd.  Failure to do so will result in spurious interrupts being
2685          * generated on the port when a cable is not attached.
2686          */
2687         if (IS_G4X(dev) && !IS_GM45(dev)) {
2688                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2689                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2690         }
2691 }