2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp *intel_dp)
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
85 return intel_dig_port->base.base.dev;
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
110 max_link_bw = DP_LINK_BW_1_62;
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
122 * 270000 * 1 * 8 / 10 == 216000
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
134 intel_dp_link_required(int pixel_clock, int bpp)
136 return (pixel_clock * bpp + 9) / 10;
140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
142 return (max_link_clock * max_lanes * 8) / 10;
146 intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
149 struct intel_dp *intel_dp = intel_attached_dp(connector);
150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
159 if (mode->vdisplay > fixed_mode->vdisplay)
162 target_clock = fixed_mode->clock;
165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
171 if (mode_rate > max_rate)
172 return MODE_CLOCK_HIGH;
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
184 pack_aux(uint8_t *src, int src_bytes)
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
206 /* hrawclock is 1/4 the FSB frequency */
208 intel_hrawclk(struct drm_device *dev)
210 struct drm_i915_private *dev_priv = dev->dev_private;
213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
227 case CLKCFG_FSB_1067:
229 case CLKCFG_FSB_1333:
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
259 /* modeset should have pipe */
261 return to_intel_crtc(crtc)->pipe;
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
300 struct drm_i915_private *dev_priv = dev->dev_private;
302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
308 struct drm_i915_private *dev_priv = dev->dev_private;
310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
314 intel_dp_check_edp(struct intel_dp *intel_dp)
316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
317 struct drm_i915_private *dev_priv = dev->dev_private;
319 if (!is_edp(intel_dp))
322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
343 msecs_to_jiffies_timeout(10));
345 done = wait_for_atomic(C, 10) == 0;
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
365 * Note that PCH attached eDP panels should use a 125MHz input
368 if (IS_VALLEYVIEW(dev)) {
369 return index ? 0 : 100;
370 } else if (intel_dig_port->port == PORT_A) {
374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
386 } else if (HAS_PCH_SPLIT(dev)) {
387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 return index ? 0 :intel_hrawclk(dev) / 2;
394 intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
403 uint32_t aux_clock_divider;
404 int i, ret, recv_bytes;
406 int try, precharge, clock = 0;
407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
410 /* dp aux is extremely sensitive to irq latency, hence request the
411 * lowest possible wakeup latency and so prevent the cpu from going into
414 pm_qos_update_request(&dev_priv->pm_qos, 0);
416 intel_dp_check_edp(intel_dp);
423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
428 intel_aux_display_runtime_get(dev_priv);
430 /* Try to wait for any previous AUX channel activity */
431 for (try = 0; try < 3; try++) {
432 status = I915_READ_NOTRACE(ch_ctl);
433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
439 WARN(1, "dp_aux_ch not started status 0x%08x\n",
445 /* Only 5 data registers! */
446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
452 /* Must try at least 3 times according to DP spec */
453 for (try = 0; try < 5; try++) {
454 /* Load the send data into the aux channel data registers */
455 for (i = 0; i < send_bytes; i += 4)
456 I915_WRITE(ch_data + i,
457 pack_aux(send + i, send_bytes - i));
459 /* Send the command and wait for it to complete */
461 DP_AUX_CH_CTL_SEND_BUSY |
462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
468 DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR);
471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
473 /* Clear done status and any errors */
477 DP_AUX_CH_CTL_TIME_OUT_ERROR |
478 DP_AUX_CH_CTL_RECEIVE_ERROR);
480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR))
483 if (status & DP_AUX_CH_CTL_DONE)
486 if (status & DP_AUX_CH_CTL_DONE)
490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526 intel_aux_display_runtime_put(dev_priv);
531 /* Write data to the aux channel in native mode */
533 intel_dp_aux_native_write(struct intel_dp *intel_dp,
534 uint16_t address, uint8_t *send, int send_bytes)
541 if (WARN_ON(send_bytes > 16))
544 intel_dp_check_edp(intel_dp);
545 msg[0] = AUX_NATIVE_WRITE << 4;
546 msg[1] = address >> 8;
547 msg[2] = address & 0xff;
548 msg[3] = send_bytes - 1;
549 memcpy(&msg[4], send, send_bytes);
550 msg_bytes = send_bytes + 4;
552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
555 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
557 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
565 /* Write a single byte to the aux channel in native mode */
567 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
568 uint16_t address, uint8_t byte)
570 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
573 /* read bytes from a native aux channel */
575 intel_dp_aux_native_read(struct intel_dp *intel_dp,
576 uint16_t address, uint8_t *recv, int recv_bytes)
585 if (WARN_ON(recv_bytes > 19))
588 intel_dp_check_edp(intel_dp);
589 msg[0] = AUX_NATIVE_READ << 4;
590 msg[1] = address >> 8;
591 msg[2] = address & 0xff;
592 msg[3] = recv_bytes - 1;
595 reply_bytes = recv_bytes + 1;
598 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
605 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
606 memcpy(recv, reply + 1, ret - 1);
609 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
617 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
618 uint8_t write_byte, uint8_t *read_byte)
620 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
621 struct intel_dp *intel_dp = container_of(adapter,
624 uint16_t address = algo_data->address;
632 ironlake_edp_panel_vdd_on(intel_dp);
633 intel_dp_check_edp(intel_dp);
634 /* Set up the command byte */
635 if (mode & MODE_I2C_READ)
636 msg[0] = AUX_I2C_READ << 4;
638 msg[0] = AUX_I2C_WRITE << 4;
640 if (!(mode & MODE_I2C_STOP))
641 msg[0] |= AUX_I2C_MOT << 4;
643 msg[1] = address >> 8;
665 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
666 * required to retry at least seven times upon receiving AUX_DEFER
667 * before giving up the AUX transaction.
669 for (retry = 0; retry < 7; retry++) {
670 ret = intel_dp_aux_ch(intel_dp,
674 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
678 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
679 case AUX_NATIVE_REPLY_ACK:
680 /* I2C-over-AUX Reply field is only valid
681 * when paired with AUX ACK.
684 case AUX_NATIVE_REPLY_NACK:
685 DRM_DEBUG_KMS("aux_ch native nack\n");
688 case AUX_NATIVE_REPLY_DEFER:
690 * For now, just give more slack to branch devices. We
691 * could check the DPCD for I2C bit rate capabilities,
692 * and if available, adjust the interval. We could also
693 * be more careful with DP-to-Legacy adapters where a
694 * long legacy cable may force very low I2C bit rates.
696 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
697 DP_DWN_STRM_PORT_PRESENT)
698 usleep_range(500, 600);
700 usleep_range(300, 400);
703 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
709 switch (reply[0] & AUX_I2C_REPLY_MASK) {
710 case AUX_I2C_REPLY_ACK:
711 if (mode == MODE_I2C_READ) {
712 *read_byte = reply[1];
714 ret = reply_bytes - 1;
716 case AUX_I2C_REPLY_NACK:
717 DRM_DEBUG_KMS("aux_i2c nack\n");
720 case AUX_I2C_REPLY_DEFER:
721 DRM_DEBUG_KMS("aux_i2c defer\n");
725 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
731 DRM_ERROR("too many retries, giving up\n");
735 ironlake_edp_panel_vdd_off(intel_dp, false);
740 intel_dp_i2c_init(struct intel_dp *intel_dp,
741 struct intel_connector *intel_connector, const char *name)
745 DRM_DEBUG_KMS("i2c_init %s\n", name);
746 intel_dp->algo.running = false;
747 intel_dp->algo.address = 0;
748 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
750 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
751 intel_dp->adapter.owner = THIS_MODULE;
752 intel_dp->adapter.class = I2C_CLASS_DDC;
753 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
754 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
755 intel_dp->adapter.algo_data = &intel_dp->algo;
756 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
758 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
763 intel_dp_set_clock(struct intel_encoder *encoder,
764 struct intel_crtc_config *pipe_config, int link_bw)
766 struct drm_device *dev = encoder->base.dev;
767 const struct dp_link_dpll *divisor = NULL;
772 count = ARRAY_SIZE(gen4_dpll);
773 } else if (IS_HASWELL(dev)) {
774 /* Haswell has special-purpose DP DDI clocks. */
775 } else if (HAS_PCH_SPLIT(dev)) {
777 count = ARRAY_SIZE(pch_dpll);
778 } else if (IS_VALLEYVIEW(dev)) {
780 count = ARRAY_SIZE(vlv_dpll);
783 if (divisor && count) {
784 for (i = 0; i < count; i++) {
785 if (link_bw == divisor[i].link_bw) {
786 pipe_config->dpll = divisor[i].dpll;
787 pipe_config->clock_set = true;
795 intel_dp_compute_config(struct intel_encoder *encoder,
796 struct intel_crtc_config *pipe_config)
798 struct drm_device *dev = encoder->base.dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
800 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
802 enum port port = dp_to_dig_port(intel_dp)->port;
803 struct intel_crtc *intel_crtc = encoder->new_crtc;
804 struct intel_connector *intel_connector = intel_dp->attached_connector;
805 int lane_count, clock;
806 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
807 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
809 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
810 int link_avail, link_clock;
812 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
813 pipe_config->has_pch_encoder = true;
815 pipe_config->has_dp_encoder = true;
817 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
818 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
820 if (!HAS_PCH_SPLIT(dev))
821 intel_gmch_panel_fitting(intel_crtc, pipe_config,
822 intel_connector->panel.fitting_mode);
824 intel_pch_panel_fitting(intel_crtc, pipe_config,
825 intel_connector->panel.fitting_mode);
828 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
831 DRM_DEBUG_KMS("DP link computation with max lane count %i "
832 "max bw %02x pixel clock %iKHz\n",
833 max_lane_count, bws[max_clock],
834 adjusted_mode->crtc_clock);
836 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
838 bpp = pipe_config->pipe_bpp;
839 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
840 dev_priv->vbt.edp_bpp < bpp) {
841 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
842 dev_priv->vbt.edp_bpp);
843 bpp = dev_priv->vbt.edp_bpp;
846 for (; bpp >= 6*3; bpp -= 2*3) {
847 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
850 for (clock = 0; clock <= max_clock; clock++) {
851 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
852 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
853 link_avail = intel_dp_max_data_rate(link_clock,
856 if (mode_rate <= link_avail) {
866 if (intel_dp->color_range_auto) {
869 * CEA-861-E - 5.1 Default Encoding Parameters
870 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
872 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
873 intel_dp->color_range = DP_COLOR_RANGE_16_235;
875 intel_dp->color_range = 0;
878 if (intel_dp->color_range)
879 pipe_config->limited_color_range = true;
881 intel_dp->link_bw = bws[clock];
882 intel_dp->lane_count = lane_count;
883 pipe_config->pipe_bpp = bpp;
884 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
886 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
887 intel_dp->link_bw, intel_dp->lane_count,
888 pipe_config->port_clock, bpp);
889 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
890 mode_rate, link_avail);
892 intel_link_compute_m_n(bpp, lane_count,
893 adjusted_mode->crtc_clock,
894 pipe_config->port_clock,
895 &pipe_config->dp_m_n);
897 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
902 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
904 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
905 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
906 struct drm_device *dev = crtc->base.dev;
907 struct drm_i915_private *dev_priv = dev->dev_private;
910 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
911 dpa_ctl = I915_READ(DP_A);
912 dpa_ctl &= ~DP_PLL_FREQ_MASK;
914 if (crtc->config.port_clock == 162000) {
915 /* For a long time we've carried around a ILK-DevA w/a for the
916 * 160MHz clock. If we're really unlucky, it's still required.
918 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
919 dpa_ctl |= DP_PLL_FREQ_160MHZ;
920 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
922 dpa_ctl |= DP_PLL_FREQ_270MHZ;
923 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
926 I915_WRITE(DP_A, dpa_ctl);
932 static void intel_dp_mode_set(struct intel_encoder *encoder)
934 struct drm_device *dev = encoder->base.dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
936 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
937 enum port port = dp_to_dig_port(intel_dp)->port;
938 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
939 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
942 * There are four kinds of DP registers:
949 * IBX PCH and CPU are the same for almost everything,
950 * except that the CPU DP PLL is configured in this
953 * CPT PCH is quite different, having many bits moved
954 * to the TRANS_DP_CTL register instead. That
955 * configuration happens (oddly) in ironlake_pch_enable
958 /* Preserve the BIOS-computed detected bit. This is
959 * supposed to be read-only.
961 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
963 /* Handle DP bits in common between all three register formats */
964 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
965 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
967 if (intel_dp->has_audio) {
968 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
969 pipe_name(crtc->pipe));
970 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
971 intel_write_eld(&encoder->base, adjusted_mode);
974 /* Split out the IBX/CPU vs CPT settings */
976 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
977 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
978 intel_dp->DP |= DP_SYNC_HS_HIGH;
979 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
980 intel_dp->DP |= DP_SYNC_VS_HIGH;
981 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
983 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
984 intel_dp->DP |= DP_ENHANCED_FRAMING;
986 intel_dp->DP |= crtc->pipe << 29;
987 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
988 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
989 intel_dp->DP |= intel_dp->color_range;
991 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
992 intel_dp->DP |= DP_SYNC_HS_HIGH;
993 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
994 intel_dp->DP |= DP_SYNC_VS_HIGH;
995 intel_dp->DP |= DP_LINK_TRAIN_OFF;
997 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
998 intel_dp->DP |= DP_ENHANCED_FRAMING;
1000 if (crtc->pipe == 1)
1001 intel_dp->DP |= DP_PIPEB_SELECT;
1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1006 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1007 ironlake_set_pll_cpu_edp(intel_dp);
1010 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1011 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1013 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1014 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1016 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1017 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1019 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 u32 pp_stat_reg, pp_ctrl_reg;
1027 pp_stat_reg = _pp_stat_reg(intel_dp);
1028 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1030 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1032 I915_READ(pp_stat_reg),
1033 I915_READ(pp_ctrl_reg));
1035 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1036 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1037 I915_READ(pp_stat_reg),
1038 I915_READ(pp_ctrl_reg));
1042 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1044 DRM_DEBUG_KMS("Wait for panel power on\n");
1045 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1048 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1050 DRM_DEBUG_KMS("Wait for panel power off time\n");
1051 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1054 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1056 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1057 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061 /* Read the current pp_control value, unlocking the register if it
1065 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1067 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1071 control = I915_READ(_pp_ctrl_reg(intel_dp));
1072 control &= ~PANEL_UNLOCK_MASK;
1073 control |= PANEL_UNLOCK_REGS;
1077 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1082 u32 pp_stat_reg, pp_ctrl_reg;
1084 if (!is_edp(intel_dp))
1087 WARN(intel_dp->want_panel_vdd,
1088 "eDP VDD already requested on\n");
1090 intel_dp->want_panel_vdd = true;
1092 if (ironlake_edp_have_panel_vdd(intel_dp))
1095 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1097 if (!ironlake_edp_have_panel_power(intel_dp))
1098 ironlake_wait_panel_power_cycle(intel_dp);
1100 pp = ironlake_get_pp_control(intel_dp);
1101 pp |= EDP_FORCE_VDD;
1103 pp_stat_reg = _pp_stat_reg(intel_dp);
1104 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1106 I915_WRITE(pp_ctrl_reg, pp);
1107 POSTING_READ(pp_ctrl_reg);
1108 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1109 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1111 * If the panel wasn't on, delay before accessing aux channel
1113 if (!ironlake_edp_have_panel_power(intel_dp)) {
1114 DRM_DEBUG_KMS("eDP was not running\n");
1115 msleep(intel_dp->panel_power_up_delay);
1119 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1124 u32 pp_stat_reg, pp_ctrl_reg;
1126 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1128 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1129 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1131 pp = ironlake_get_pp_control(intel_dp);
1132 pp &= ~EDP_FORCE_VDD;
1134 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1135 pp_stat_reg = _pp_stat_reg(intel_dp);
1137 I915_WRITE(pp_ctrl_reg, pp);
1138 POSTING_READ(pp_ctrl_reg);
1140 /* Make sure sequencer is idle before allowing subsequent activity */
1141 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1142 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1143 msleep(intel_dp->panel_power_down_delay);
1147 static void ironlake_panel_vdd_work(struct work_struct *__work)
1149 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1150 struct intel_dp, panel_vdd_work);
1151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1153 mutex_lock(&dev->mode_config.mutex);
1154 ironlake_panel_vdd_off_sync(intel_dp);
1155 mutex_unlock(&dev->mode_config.mutex);
1158 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1160 if (!is_edp(intel_dp))
1163 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1165 intel_dp->want_panel_vdd = false;
1168 ironlake_panel_vdd_off_sync(intel_dp);
1171 * Queue the timer to fire a long
1172 * time from now (relative to the power down delay)
1173 * to keep the panel power up across a sequence of operations
1175 schedule_delayed_work(&intel_dp->panel_vdd_work,
1176 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1180 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1182 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1187 if (!is_edp(intel_dp))
1190 DRM_DEBUG_KMS("Turn eDP power on\n");
1192 if (ironlake_edp_have_panel_power(intel_dp)) {
1193 DRM_DEBUG_KMS("eDP power already on\n");
1197 ironlake_wait_panel_power_cycle(intel_dp);
1199 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1200 pp = ironlake_get_pp_control(intel_dp);
1202 /* ILK workaround: disable reset around power sequence */
1203 pp &= ~PANEL_POWER_RESET;
1204 I915_WRITE(pp_ctrl_reg, pp);
1205 POSTING_READ(pp_ctrl_reg);
1208 pp |= POWER_TARGET_ON;
1210 pp |= PANEL_POWER_RESET;
1212 I915_WRITE(pp_ctrl_reg, pp);
1213 POSTING_READ(pp_ctrl_reg);
1215 ironlake_wait_panel_on(intel_dp);
1218 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1219 I915_WRITE(pp_ctrl_reg, pp);
1220 POSTING_READ(pp_ctrl_reg);
1224 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1227 struct drm_i915_private *dev_priv = dev->dev_private;
1231 if (!is_edp(intel_dp))
1234 DRM_DEBUG_KMS("Turn eDP power off\n");
1236 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1238 pp = ironlake_get_pp_control(intel_dp);
1239 /* We need to switch off panel power _and_ force vdd, for otherwise some
1240 * panels get very unhappy and cease to work. */
1241 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1243 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
1248 intel_dp->want_panel_vdd = false;
1250 ironlake_wait_panel_off(intel_dp);
1253 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1256 struct drm_device *dev = intel_dig_port->base.base.dev;
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1261 if (!is_edp(intel_dp))
1264 DRM_DEBUG_KMS("\n");
1266 * If we enable the backlight right away following a panel power
1267 * on, we may see slight flicker as the panel syncs with the eDP
1268 * link. So delay a bit to make sure the image is solid before
1269 * allowing it to appear.
1271 msleep(intel_dp->backlight_on_delay);
1272 pp = ironlake_get_pp_control(intel_dp);
1273 pp |= EDP_BLC_ENABLE;
1275 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1277 I915_WRITE(pp_ctrl_reg, pp);
1278 POSTING_READ(pp_ctrl_reg);
1280 intel_panel_enable_backlight(intel_dp->attached_connector);
1283 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1290 if (!is_edp(intel_dp))
1293 intel_panel_disable_backlight(intel_dp->attached_connector);
1295 DRM_DEBUG_KMS("\n");
1296 pp = ironlake_get_pp_control(intel_dp);
1297 pp &= ~EDP_BLC_ENABLE;
1299 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1301 I915_WRITE(pp_ctrl_reg, pp);
1302 POSTING_READ(pp_ctrl_reg);
1303 msleep(intel_dp->backlight_off_delay);
1306 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1310 struct drm_device *dev = crtc->dev;
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1314 assert_pipe_disabled(dev_priv,
1315 to_intel_crtc(crtc)->pipe);
1317 DRM_DEBUG_KMS("\n");
1318 dpa_ctl = I915_READ(DP_A);
1319 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1320 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1322 /* We don't adjust intel_dp->DP while tearing down the link, to
1323 * facilitate link retraining (e.g. after hotplug). Hence clear all
1324 * enable bits here to ensure that we don't enable too much. */
1325 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1326 intel_dp->DP |= DP_PLL_ENABLE;
1327 I915_WRITE(DP_A, intel_dp->DP);
1332 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1335 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1336 struct drm_device *dev = crtc->dev;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1340 assert_pipe_disabled(dev_priv,
1341 to_intel_crtc(crtc)->pipe);
1343 dpa_ctl = I915_READ(DP_A);
1344 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1345 "dp pll off, should be on\n");
1346 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1348 /* We can't rely on the value tracked for the DP register in
1349 * intel_dp->DP because link_down must not change that (otherwise link
1350 * re-training will fail. */
1351 dpa_ctl &= ~DP_PLL_ENABLE;
1352 I915_WRITE(DP_A, dpa_ctl);
1357 /* If the sink supports it, try to set the power state appropriately */
1358 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1362 /* Should have a valid DPCD by this point */
1363 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1366 if (mode != DRM_MODE_DPMS_ON) {
1367 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1370 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1373 * When turning on, we need to retry for 1ms to give the sink
1376 for (i = 0; i < 3; i++) {
1377 ret = intel_dp_aux_native_write_1(intel_dp,
1387 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1390 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1391 enum port port = dp_to_dig_port(intel_dp)->port;
1392 struct drm_device *dev = encoder->base.dev;
1393 struct drm_i915_private *dev_priv = dev->dev_private;
1394 u32 tmp = I915_READ(intel_dp->output_reg);
1396 if (!(tmp & DP_PORT_EN))
1399 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1400 *pipe = PORT_TO_PIPE_CPT(tmp);
1401 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1402 *pipe = PORT_TO_PIPE(tmp);
1408 switch (intel_dp->output_reg) {
1410 trans_sel = TRANS_DP_PORT_SEL_B;
1413 trans_sel = TRANS_DP_PORT_SEL_C;
1416 trans_sel = TRANS_DP_PORT_SEL_D;
1423 trans_dp = I915_READ(TRANS_DP_CTL(i));
1424 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1430 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1431 intel_dp->output_reg);
1437 static void intel_dp_get_config(struct intel_encoder *encoder,
1438 struct intel_crtc_config *pipe_config)
1440 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1442 struct drm_device *dev = encoder->base.dev;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 enum port port = dp_to_dig_port(intel_dp)->port;
1445 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1448 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1449 tmp = I915_READ(intel_dp->output_reg);
1450 if (tmp & DP_SYNC_HS_HIGH)
1451 flags |= DRM_MODE_FLAG_PHSYNC;
1453 flags |= DRM_MODE_FLAG_NHSYNC;
1455 if (tmp & DP_SYNC_VS_HIGH)
1456 flags |= DRM_MODE_FLAG_PVSYNC;
1458 flags |= DRM_MODE_FLAG_NVSYNC;
1460 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1461 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1462 flags |= DRM_MODE_FLAG_PHSYNC;
1464 flags |= DRM_MODE_FLAG_NHSYNC;
1466 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1467 flags |= DRM_MODE_FLAG_PVSYNC;
1469 flags |= DRM_MODE_FLAG_NVSYNC;
1472 pipe_config->adjusted_mode.flags |= flags;
1474 pipe_config->has_dp_encoder = true;
1476 intel_dp_get_m_n(crtc, pipe_config);
1478 if (port == PORT_A) {
1479 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1480 pipe_config->port_clock = 162000;
1482 pipe_config->port_clock = 270000;
1485 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1486 &pipe_config->dp_m_n);
1488 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1489 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1491 pipe_config->adjusted_mode.crtc_clock = dotclock;
1493 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1494 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1496 * This is a big fat ugly hack.
1498 * Some machines in UEFI boot mode provide us a VBT that has 18
1499 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1500 * unknown we fail to light up. Yet the same BIOS boots up with
1501 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1502 * max, not what it tells us to use.
1504 * Note: This will still be broken if the eDP panel is not lit
1505 * up by the BIOS, and thus we can't get the mode at module
1508 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1509 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1510 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1514 static bool is_edp_psr(struct drm_device *dev)
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1518 return dev_priv->psr.sink_support;
1521 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1528 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1531 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1532 struct edp_vsc_psr *vsc_psr)
1534 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1535 struct drm_device *dev = dig_port->base.base.dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1538 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1539 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1540 uint32_t *data = (uint32_t *) vsc_psr;
1543 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1544 the video DIP being updated before program video DIP data buffer
1545 registers for DIP being updated. */
1546 I915_WRITE(ctl_reg, 0);
1547 POSTING_READ(ctl_reg);
1549 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1550 if (i < sizeof(struct edp_vsc_psr))
1551 I915_WRITE(data_reg + i, *data++);
1553 I915_WRITE(data_reg + i, 0);
1556 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1557 POSTING_READ(ctl_reg);
1560 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1562 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 struct edp_vsc_psr psr_vsc;
1566 if (intel_dp->psr_setup_done)
1569 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1570 memset(&psr_vsc, 0, sizeof(psr_vsc));
1571 psr_vsc.sdp_header.HB0 = 0;
1572 psr_vsc.sdp_header.HB1 = 0x7;
1573 psr_vsc.sdp_header.HB2 = 0x2;
1574 psr_vsc.sdp_header.HB3 = 0x8;
1575 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1577 /* Avoid continuous PSR exit by masking memup and hpd */
1578 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1579 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1581 intel_dp->psr_setup_done = true;
1584 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1586 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1589 int precharge = 0x3;
1590 int msg_size = 5; /* Header(4) + Message(1) */
1592 /* Enable PSR in sink */
1593 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1594 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1596 ~DP_PSR_MAIN_LINK_ACTIVE);
1598 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1600 DP_PSR_MAIN_LINK_ACTIVE);
1602 /* Setup AUX registers */
1603 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1604 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1605 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1606 DP_AUX_CH_CTL_TIME_OUT_400us |
1607 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1608 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1609 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1612 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1614 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 uint32_t max_sleep_time = 0x1f;
1617 uint32_t idle_frames = 1;
1619 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1621 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1622 val |= EDP_PSR_LINK_STANDBY;
1623 val |= EDP_PSR_TP2_TP3_TIME_0us;
1624 val |= EDP_PSR_TP1_TIME_0us;
1625 val |= EDP_PSR_SKIP_AUX_EXIT;
1627 val |= EDP_PSR_LINK_DISABLE;
1629 I915_WRITE(EDP_PSR_CTL(dev), val |
1630 IS_BROADWELL(dev) ? 0 : link_entry_time |
1631 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1632 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1636 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1638 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1639 struct drm_device *dev = dig_port->base.base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 struct drm_crtc *crtc = dig_port->base.base.crtc;
1642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1643 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1644 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1646 dev_priv->psr.source_ok = false;
1648 if (!HAS_PSR(dev)) {
1649 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1653 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1654 (dig_port->port != PORT_A)) {
1655 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1659 if (!i915_enable_psr) {
1660 DRM_DEBUG_KMS("PSR disable by flag\n");
1664 crtc = dig_port->base.base.crtc;
1666 DRM_DEBUG_KMS("crtc not active for PSR\n");
1670 intel_crtc = to_intel_crtc(crtc);
1671 if (!intel_crtc_active(crtc)) {
1672 DRM_DEBUG_KMS("crtc not active for PSR\n");
1676 obj = to_intel_framebuffer(crtc->fb)->obj;
1677 if (obj->tiling_mode != I915_TILING_X ||
1678 obj->fence_reg == I915_FENCE_REG_NONE) {
1679 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1683 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1684 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1688 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1690 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1694 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1695 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1699 dev_priv->psr.source_ok = true;
1703 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1705 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1707 if (!intel_edp_psr_match_conditions(intel_dp) ||
1708 intel_edp_is_psr_enabled(dev))
1711 /* Setup PSR once */
1712 intel_edp_psr_setup(intel_dp);
1714 /* Enable PSR on the panel */
1715 intel_edp_psr_enable_sink(intel_dp);
1717 /* Enable PSR on the host */
1718 intel_edp_psr_enable_source(intel_dp);
1721 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1723 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1725 if (intel_edp_psr_match_conditions(intel_dp) &&
1726 !intel_edp_is_psr_enabled(dev))
1727 intel_edp_psr_do_enable(intel_dp);
1730 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1732 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1735 if (!intel_edp_is_psr_enabled(dev))
1738 I915_WRITE(EDP_PSR_CTL(dev),
1739 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1741 /* Wait till PSR is idle */
1742 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1743 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1744 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1747 void intel_edp_psr_update(struct drm_device *dev)
1749 struct intel_encoder *encoder;
1750 struct intel_dp *intel_dp = NULL;
1752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1753 if (encoder->type == INTEL_OUTPUT_EDP) {
1754 intel_dp = enc_to_intel_dp(&encoder->base);
1756 if (!is_edp_psr(dev))
1759 if (!intel_edp_psr_match_conditions(intel_dp))
1760 intel_edp_psr_disable(intel_dp);
1762 if (!intel_edp_is_psr_enabled(dev))
1763 intel_edp_psr_do_enable(intel_dp);
1767 static void intel_disable_dp(struct intel_encoder *encoder)
1769 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1770 enum port port = dp_to_dig_port(intel_dp)->port;
1771 struct drm_device *dev = encoder->base.dev;
1773 /* Make sure the panel is off before trying to change the mode. But also
1774 * ensure that we have vdd while we switch off the panel. */
1775 ironlake_edp_panel_vdd_on(intel_dp);
1776 ironlake_edp_backlight_off(intel_dp);
1777 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1778 ironlake_edp_panel_off(intel_dp);
1780 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1781 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1782 intel_dp_link_down(intel_dp);
1785 static void intel_post_disable_dp(struct intel_encoder *encoder)
1787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1788 enum port port = dp_to_dig_port(intel_dp)->port;
1789 struct drm_device *dev = encoder->base.dev;
1791 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1792 intel_dp_link_down(intel_dp);
1793 if (!IS_VALLEYVIEW(dev))
1794 ironlake_edp_pll_off(intel_dp);
1798 static void intel_enable_dp(struct intel_encoder *encoder)
1800 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1801 struct drm_device *dev = encoder->base.dev;
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1805 if (WARN_ON(dp_reg & DP_PORT_EN))
1808 ironlake_edp_panel_vdd_on(intel_dp);
1809 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1810 intel_dp_start_link_train(intel_dp);
1811 ironlake_edp_panel_on(intel_dp);
1812 ironlake_edp_panel_vdd_off(intel_dp, true);
1813 intel_dp_complete_link_train(intel_dp);
1814 intel_dp_stop_link_train(intel_dp);
1817 static void g4x_enable_dp(struct intel_encoder *encoder)
1819 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1821 intel_enable_dp(encoder);
1822 ironlake_edp_backlight_on(intel_dp);
1825 static void vlv_enable_dp(struct intel_encoder *encoder)
1827 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829 ironlake_edp_backlight_on(intel_dp);
1832 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1834 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1835 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1837 if (dport->port == PORT_A)
1838 ironlake_edp_pll_on(intel_dp);
1841 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1844 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1845 struct drm_device *dev = encoder->base.dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
1847 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1848 int port = vlv_dport_to_channel(dport);
1849 int pipe = intel_crtc->pipe;
1850 struct edp_power_seq power_seq;
1853 mutex_lock(&dev_priv->dpio_lock);
1855 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
1862 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1863 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1864 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1866 mutex_unlock(&dev_priv->dpio_lock);
1868 /* init power sequencer on this pipe and port */
1869 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1870 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1873 intel_enable_dp(encoder);
1875 vlv_wait_port_ready(dev_priv, port);
1878 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1880 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1881 struct drm_device *dev = encoder->base.dev;
1882 struct drm_i915_private *dev_priv = dev->dev_private;
1883 struct intel_crtc *intel_crtc =
1884 to_intel_crtc(encoder->base.crtc);
1885 int port = vlv_dport_to_channel(dport);
1886 int pipe = intel_crtc->pipe;
1888 /* Program Tx lane resets to default */
1889 mutex_lock(&dev_priv->dpio_lock);
1890 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
1891 DPIO_PCS_TX_LANE2_RESET |
1892 DPIO_PCS_TX_LANE1_RESET);
1893 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
1894 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1895 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1896 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1897 DPIO_PCS_CLK_SOFT_RESET);
1899 /* Fix up inter-pair skew failure */
1900 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1901 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1902 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
1903 mutex_unlock(&dev_priv->dpio_lock);
1907 * Native read with retry for link status and receiver capability reads for
1908 * cases where the sink may still be asleep.
1911 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1912 uint8_t *recv, int recv_bytes)
1917 * Sinks are *supposed* to come up within 1ms from an off state,
1918 * but we're also supposed to retry 3 times per the spec.
1920 for (i = 0; i < 3; i++) {
1921 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1923 if (ret == recv_bytes)
1932 * Fetch AUX CH registers 0x202 - 0x207 which contain
1933 * link status information
1936 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1938 return intel_dp_aux_native_read_retry(intel_dp,
1941 DP_LINK_STATUS_SIZE);
1945 static char *voltage_names[] = {
1946 "0.4V", "0.6V", "0.8V", "1.2V"
1948 static char *pre_emph_names[] = {
1949 "0dB", "3.5dB", "6dB", "9.5dB"
1951 static char *link_train_names[] = {
1952 "pattern 1", "pattern 2", "idle", "off"
1957 * These are source-specific values; current Intel hardware supports
1958 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1962 intel_dp_voltage_max(struct intel_dp *intel_dp)
1964 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1965 enum port port = dp_to_dig_port(intel_dp)->port;
1967 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1968 return DP_TRAIN_VOLTAGE_SWING_1200;
1969 else if (IS_GEN7(dev) && port == PORT_A)
1970 return DP_TRAIN_VOLTAGE_SWING_800;
1971 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1972 return DP_TRAIN_VOLTAGE_SWING_1200;
1974 return DP_TRAIN_VOLTAGE_SWING_800;
1978 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1980 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1981 enum port port = dp_to_dig_port(intel_dp)->port;
1983 if (IS_BROADWELL(dev)) {
1984 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1985 case DP_TRAIN_VOLTAGE_SWING_400:
1986 case DP_TRAIN_VOLTAGE_SWING_600:
1987 return DP_TRAIN_PRE_EMPHASIS_6;
1988 case DP_TRAIN_VOLTAGE_SWING_800:
1989 return DP_TRAIN_PRE_EMPHASIS_3_5;
1990 case DP_TRAIN_VOLTAGE_SWING_1200:
1992 return DP_TRAIN_PRE_EMPHASIS_0;
1994 } else if (IS_HASWELL(dev)) {
1995 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1996 case DP_TRAIN_VOLTAGE_SWING_400:
1997 return DP_TRAIN_PRE_EMPHASIS_9_5;
1998 case DP_TRAIN_VOLTAGE_SWING_600:
1999 return DP_TRAIN_PRE_EMPHASIS_6;
2000 case DP_TRAIN_VOLTAGE_SWING_800:
2001 return DP_TRAIN_PRE_EMPHASIS_3_5;
2002 case DP_TRAIN_VOLTAGE_SWING_1200:
2004 return DP_TRAIN_PRE_EMPHASIS_0;
2006 } else if (IS_VALLEYVIEW(dev)) {
2007 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2008 case DP_TRAIN_VOLTAGE_SWING_400:
2009 return DP_TRAIN_PRE_EMPHASIS_9_5;
2010 case DP_TRAIN_VOLTAGE_SWING_600:
2011 return DP_TRAIN_PRE_EMPHASIS_6;
2012 case DP_TRAIN_VOLTAGE_SWING_800:
2013 return DP_TRAIN_PRE_EMPHASIS_3_5;
2014 case DP_TRAIN_VOLTAGE_SWING_1200:
2016 return DP_TRAIN_PRE_EMPHASIS_0;
2018 } else if (IS_GEN7(dev) && port == PORT_A) {
2019 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2020 case DP_TRAIN_VOLTAGE_SWING_400:
2021 return DP_TRAIN_PRE_EMPHASIS_6;
2022 case DP_TRAIN_VOLTAGE_SWING_600:
2023 case DP_TRAIN_VOLTAGE_SWING_800:
2024 return DP_TRAIN_PRE_EMPHASIS_3_5;
2026 return DP_TRAIN_PRE_EMPHASIS_0;
2029 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2030 case DP_TRAIN_VOLTAGE_SWING_400:
2031 return DP_TRAIN_PRE_EMPHASIS_6;
2032 case DP_TRAIN_VOLTAGE_SWING_600:
2033 return DP_TRAIN_PRE_EMPHASIS_6;
2034 case DP_TRAIN_VOLTAGE_SWING_800:
2035 return DP_TRAIN_PRE_EMPHASIS_3_5;
2036 case DP_TRAIN_VOLTAGE_SWING_1200:
2038 return DP_TRAIN_PRE_EMPHASIS_0;
2043 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2048 struct intel_crtc *intel_crtc =
2049 to_intel_crtc(dport->base.base.crtc);
2050 unsigned long demph_reg_value, preemph_reg_value,
2051 uniqtranscale_reg_value;
2052 uint8_t train_set = intel_dp->train_set[0];
2053 int port = vlv_dport_to_channel(dport);
2054 int pipe = intel_crtc->pipe;
2056 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2057 case DP_TRAIN_PRE_EMPHASIS_0:
2058 preemph_reg_value = 0x0004000;
2059 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2060 case DP_TRAIN_VOLTAGE_SWING_400:
2061 demph_reg_value = 0x2B405555;
2062 uniqtranscale_reg_value = 0x552AB83A;
2064 case DP_TRAIN_VOLTAGE_SWING_600:
2065 demph_reg_value = 0x2B404040;
2066 uniqtranscale_reg_value = 0x5548B83A;
2068 case DP_TRAIN_VOLTAGE_SWING_800:
2069 demph_reg_value = 0x2B245555;
2070 uniqtranscale_reg_value = 0x5560B83A;
2072 case DP_TRAIN_VOLTAGE_SWING_1200:
2073 demph_reg_value = 0x2B405555;
2074 uniqtranscale_reg_value = 0x5598DA3A;
2080 case DP_TRAIN_PRE_EMPHASIS_3_5:
2081 preemph_reg_value = 0x0002000;
2082 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2083 case DP_TRAIN_VOLTAGE_SWING_400:
2084 demph_reg_value = 0x2B404040;
2085 uniqtranscale_reg_value = 0x5552B83A;
2087 case DP_TRAIN_VOLTAGE_SWING_600:
2088 demph_reg_value = 0x2B404848;
2089 uniqtranscale_reg_value = 0x5580B83A;
2091 case DP_TRAIN_VOLTAGE_SWING_800:
2092 demph_reg_value = 0x2B404040;
2093 uniqtranscale_reg_value = 0x55ADDA3A;
2099 case DP_TRAIN_PRE_EMPHASIS_6:
2100 preemph_reg_value = 0x0000000;
2101 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2102 case DP_TRAIN_VOLTAGE_SWING_400:
2103 demph_reg_value = 0x2B305555;
2104 uniqtranscale_reg_value = 0x5570B83A;
2106 case DP_TRAIN_VOLTAGE_SWING_600:
2107 demph_reg_value = 0x2B2B4040;
2108 uniqtranscale_reg_value = 0x55ADDA3A;
2114 case DP_TRAIN_PRE_EMPHASIS_9_5:
2115 preemph_reg_value = 0x0006000;
2116 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2117 case DP_TRAIN_VOLTAGE_SWING_400:
2118 demph_reg_value = 0x1B405555;
2119 uniqtranscale_reg_value = 0x55ADDA3A;
2129 mutex_lock(&dev_priv->dpio_lock);
2130 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2131 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2132 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
2133 uniqtranscale_reg_value);
2134 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2135 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2136 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2137 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
2138 mutex_unlock(&dev_priv->dpio_lock);
2144 intel_get_adjust_train(struct intel_dp *intel_dp,
2145 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2150 uint8_t voltage_max;
2151 uint8_t preemph_max;
2153 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2154 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2155 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2163 voltage_max = intel_dp_voltage_max(intel_dp);
2164 if (v >= voltage_max)
2165 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2167 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2168 if (p >= preemph_max)
2169 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2171 for (lane = 0; lane < 4; lane++)
2172 intel_dp->train_set[lane] = v | p;
2176 intel_gen4_signal_levels(uint8_t train_set)
2178 uint32_t signal_levels = 0;
2180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2181 case DP_TRAIN_VOLTAGE_SWING_400:
2183 signal_levels |= DP_VOLTAGE_0_4;
2185 case DP_TRAIN_VOLTAGE_SWING_600:
2186 signal_levels |= DP_VOLTAGE_0_6;
2188 case DP_TRAIN_VOLTAGE_SWING_800:
2189 signal_levels |= DP_VOLTAGE_0_8;
2191 case DP_TRAIN_VOLTAGE_SWING_1200:
2192 signal_levels |= DP_VOLTAGE_1_2;
2195 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2196 case DP_TRAIN_PRE_EMPHASIS_0:
2198 signal_levels |= DP_PRE_EMPHASIS_0;
2200 case DP_TRAIN_PRE_EMPHASIS_3_5:
2201 signal_levels |= DP_PRE_EMPHASIS_3_5;
2203 case DP_TRAIN_PRE_EMPHASIS_6:
2204 signal_levels |= DP_PRE_EMPHASIS_6;
2206 case DP_TRAIN_PRE_EMPHASIS_9_5:
2207 signal_levels |= DP_PRE_EMPHASIS_9_5;
2210 return signal_levels;
2213 /* Gen6's DP voltage swing and pre-emphasis control */
2215 intel_gen6_edp_signal_levels(uint8_t train_set)
2217 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2218 DP_TRAIN_PRE_EMPHASIS_MASK);
2219 switch (signal_levels) {
2220 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2221 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2222 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2223 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2224 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2225 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2226 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2227 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2229 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2230 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2231 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2232 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2233 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2235 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2236 "0x%x\n", signal_levels);
2237 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2241 /* Gen7's DP voltage swing and pre-emphasis control */
2243 intel_gen7_edp_signal_levels(uint8_t train_set)
2245 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2246 DP_TRAIN_PRE_EMPHASIS_MASK);
2247 switch (signal_levels) {
2248 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2249 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2250 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2251 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2252 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2253 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2255 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2256 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2257 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2258 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2260 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2261 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2262 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2263 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2266 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2267 "0x%x\n", signal_levels);
2268 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2272 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2274 intel_hsw_signal_levels(uint8_t train_set)
2276 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2277 DP_TRAIN_PRE_EMPHASIS_MASK);
2278 switch (signal_levels) {
2279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2280 return DDI_BUF_EMP_400MV_0DB_HSW;
2281 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2282 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2284 return DDI_BUF_EMP_400MV_6DB_HSW;
2285 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2286 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2288 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2289 return DDI_BUF_EMP_600MV_0DB_HSW;
2290 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2291 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2292 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2293 return DDI_BUF_EMP_600MV_6DB_HSW;
2295 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2296 return DDI_BUF_EMP_800MV_0DB_HSW;
2297 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2298 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2300 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2301 "0x%x\n", signal_levels);
2302 return DDI_BUF_EMP_400MV_0DB_HSW;
2307 intel_bdw_signal_levels(uint8_t train_set)
2309 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2310 DP_TRAIN_PRE_EMPHASIS_MASK);
2311 switch (signal_levels) {
2312 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2313 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2314 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2315 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2316 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2317 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2320 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2321 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2322 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2323 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2324 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2326 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2327 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2328 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2329 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2331 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2332 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2335 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2336 "0x%x\n", signal_levels);
2337 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2341 /* Properly updates "DP" with the correct signal levels. */
2343 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2345 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2346 enum port port = intel_dig_port->port;
2347 struct drm_device *dev = intel_dig_port->base.base.dev;
2348 uint32_t signal_levels, mask;
2349 uint8_t train_set = intel_dp->train_set[0];
2351 if (IS_BROADWELL(dev)) {
2352 signal_levels = intel_bdw_signal_levels(train_set);
2353 mask = DDI_BUF_EMP_MASK;
2354 } else if (IS_HASWELL(dev)) {
2355 signal_levels = intel_hsw_signal_levels(train_set);
2356 mask = DDI_BUF_EMP_MASK;
2357 } else if (IS_VALLEYVIEW(dev)) {
2358 signal_levels = intel_vlv_signal_levels(intel_dp);
2360 } else if (IS_GEN7(dev) && port == PORT_A) {
2361 signal_levels = intel_gen7_edp_signal_levels(train_set);
2362 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2363 } else if (IS_GEN6(dev) && port == PORT_A) {
2364 signal_levels = intel_gen6_edp_signal_levels(train_set);
2365 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2367 signal_levels = intel_gen4_signal_levels(train_set);
2368 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2371 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2373 *DP = (*DP & ~mask) | signal_levels;
2377 intel_dp_set_link_train(struct intel_dp *intel_dp,
2379 uint8_t dp_train_pat)
2381 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2382 struct drm_device *dev = intel_dig_port->base.base.dev;
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 enum port port = intel_dig_port->port;
2385 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2389 uint32_t temp = I915_READ(DP_TP_CTL(port));
2391 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2392 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2394 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2396 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2397 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2398 case DP_TRAINING_PATTERN_DISABLE:
2399 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2402 case DP_TRAINING_PATTERN_1:
2403 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2405 case DP_TRAINING_PATTERN_2:
2406 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2408 case DP_TRAINING_PATTERN_3:
2409 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2412 I915_WRITE(DP_TP_CTL(port), temp);
2414 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2415 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2417 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2418 case DP_TRAINING_PATTERN_DISABLE:
2419 *DP |= DP_LINK_TRAIN_OFF_CPT;
2421 case DP_TRAINING_PATTERN_1:
2422 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2424 case DP_TRAINING_PATTERN_2:
2425 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2427 case DP_TRAINING_PATTERN_3:
2428 DRM_ERROR("DP training pattern 3 not supported\n");
2429 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2434 *DP &= ~DP_LINK_TRAIN_MASK;
2436 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2437 case DP_TRAINING_PATTERN_DISABLE:
2438 *DP |= DP_LINK_TRAIN_OFF;
2440 case DP_TRAINING_PATTERN_1:
2441 *DP |= DP_LINK_TRAIN_PAT_1;
2443 case DP_TRAINING_PATTERN_2:
2444 *DP |= DP_LINK_TRAIN_PAT_2;
2446 case DP_TRAINING_PATTERN_3:
2447 DRM_ERROR("DP training pattern 3 not supported\n");
2448 *DP |= DP_LINK_TRAIN_PAT_2;
2453 I915_WRITE(intel_dp->output_reg, *DP);
2454 POSTING_READ(intel_dp->output_reg);
2456 buf[0] = dp_train_pat;
2457 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2458 DP_TRAINING_PATTERN_DISABLE) {
2459 /* don't write DP_TRAINING_LANEx_SET on disable */
2462 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2463 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2464 len = intel_dp->lane_count + 1;
2467 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2474 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2475 uint8_t dp_train_pat)
2477 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2478 intel_dp_set_signal_levels(intel_dp, DP);
2479 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2483 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2484 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2486 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2487 struct drm_device *dev = intel_dig_port->base.base.dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2491 intel_get_adjust_train(intel_dp, link_status);
2492 intel_dp_set_signal_levels(intel_dp, DP);
2494 I915_WRITE(intel_dp->output_reg, *DP);
2495 POSTING_READ(intel_dp->output_reg);
2497 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2498 intel_dp->train_set,
2499 intel_dp->lane_count);
2501 return ret == intel_dp->lane_count;
2504 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2506 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2507 struct drm_device *dev = intel_dig_port->base.base.dev;
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509 enum port port = intel_dig_port->port;
2515 val = I915_READ(DP_TP_CTL(port));
2516 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2517 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2518 I915_WRITE(DP_TP_CTL(port), val);
2521 * On PORT_A we can have only eDP in SST mode. There the only reason
2522 * we need to set idle transmission mode is to work around a HW issue
2523 * where we enable the pipe while not in idle link-training mode.
2524 * In this case there is requirement to wait for a minimum number of
2525 * idle patterns to be sent.
2530 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2532 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2535 /* Enable corresponding port and start training pattern 1 */
2537 intel_dp_start_link_train(struct intel_dp *intel_dp)
2539 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2540 struct drm_device *dev = encoder->dev;
2543 int voltage_tries, loop_tries;
2544 uint32_t DP = intel_dp->DP;
2545 uint8_t link_config[2];
2548 intel_ddi_prepare_link_retrain(encoder);
2550 /* Write the link configuration data */
2551 link_config[0] = intel_dp->link_bw;
2552 link_config[1] = intel_dp->lane_count;
2553 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2554 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2555 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2558 link_config[1] = DP_SET_ANSI_8B10B;
2559 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2563 /* clock recovery */
2564 if (!intel_dp_reset_link_train(intel_dp, &DP,
2565 DP_TRAINING_PATTERN_1 |
2566 DP_LINK_SCRAMBLING_DISABLE)) {
2567 DRM_ERROR("failed to enable link training\n");
2575 uint8_t link_status[DP_LINK_STATUS_SIZE];
2577 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2578 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2579 DRM_ERROR("failed to get link status\n");
2583 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2584 DRM_DEBUG_KMS("clock recovery OK\n");
2588 /* Check to see if we've tried the max voltage */
2589 for (i = 0; i < intel_dp->lane_count; i++)
2590 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2592 if (i == intel_dp->lane_count) {
2594 if (loop_tries == 5) {
2595 DRM_ERROR("too many full retries, give up\n");
2598 intel_dp_reset_link_train(intel_dp, &DP,
2599 DP_TRAINING_PATTERN_1 |
2600 DP_LINK_SCRAMBLING_DISABLE);
2605 /* Check to see if we've tried the same voltage 5 times */
2606 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2608 if (voltage_tries == 5) {
2609 DRM_ERROR("too many voltage retries, give up\n");
2614 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2616 /* Update training set as requested by target */
2617 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2618 DRM_ERROR("failed to update link training\n");
2627 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2629 bool channel_eq = false;
2630 int tries, cr_tries;
2631 uint32_t DP = intel_dp->DP;
2633 /* channel equalization */
2634 if (!intel_dp_set_link_train(intel_dp, &DP,
2635 DP_TRAINING_PATTERN_2 |
2636 DP_LINK_SCRAMBLING_DISABLE)) {
2637 DRM_ERROR("failed to start channel equalization\n");
2645 uint8_t link_status[DP_LINK_STATUS_SIZE];
2648 DRM_ERROR("failed to train DP, aborting\n");
2649 intel_dp_link_down(intel_dp);
2653 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2654 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2655 DRM_ERROR("failed to get link status\n");
2659 /* Make sure clock is still ok */
2660 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2661 intel_dp_start_link_train(intel_dp);
2662 intel_dp_set_link_train(intel_dp, &DP,
2663 DP_TRAINING_PATTERN_2 |
2664 DP_LINK_SCRAMBLING_DISABLE);
2669 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2674 /* Try 5 times, then try clock recovery if that fails */
2676 intel_dp_link_down(intel_dp);
2677 intel_dp_start_link_train(intel_dp);
2678 intel_dp_set_link_train(intel_dp, &DP,
2679 DP_TRAINING_PATTERN_2 |
2680 DP_LINK_SCRAMBLING_DISABLE);
2686 /* Update training set as requested by target */
2687 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2688 DRM_ERROR("failed to update link training\n");
2694 intel_dp_set_idle_link_train(intel_dp);
2699 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2703 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2705 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2706 DP_TRAINING_PATTERN_DISABLE);
2710 intel_dp_link_down(struct intel_dp *intel_dp)
2712 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2713 enum port port = intel_dig_port->port;
2714 struct drm_device *dev = intel_dig_port->base.base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 struct intel_crtc *intel_crtc =
2717 to_intel_crtc(intel_dig_port->base.base.crtc);
2718 uint32_t DP = intel_dp->DP;
2721 * DDI code has a strict mode set sequence and we should try to respect
2722 * it, otherwise we might hang the machine in many different ways. So we
2723 * really should be disabling the port only on a complete crtc_disable
2724 * sequence. This function is just called under two conditions on DDI
2726 * - Link train failed while doing crtc_enable, and on this case we
2727 * really should respect the mode set sequence and wait for a
2729 * - Someone turned the monitor off and intel_dp_check_link_status
2730 * called us. We don't need to disable the whole port on this case, so
2731 * when someone turns the monitor on again,
2732 * intel_ddi_prepare_link_retrain will take care of redoing the link
2738 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2741 DRM_DEBUG_KMS("\n");
2743 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2744 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2745 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2747 DP &= ~DP_LINK_TRAIN_MASK;
2748 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2750 POSTING_READ(intel_dp->output_reg);
2752 /* We don't really know why we're doing this */
2753 intel_wait_for_vblank(dev, intel_crtc->pipe);
2755 if (HAS_PCH_IBX(dev) &&
2756 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2757 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2759 /* Hardware workaround: leaving our transcoder select
2760 * set to transcoder B while it's off will prevent the
2761 * corresponding HDMI output on transcoder A.
2763 * Combine this with another hardware workaround:
2764 * transcoder select bit can only be cleared while the
2767 DP &= ~DP_PIPEB_SELECT;
2768 I915_WRITE(intel_dp->output_reg, DP);
2770 /* Changes to enable or select take place the vblank
2771 * after being written.
2773 if (WARN_ON(crtc == NULL)) {
2774 /* We should never try to disable a port without a crtc
2775 * attached. For paranoia keep the code around for a
2777 POSTING_READ(intel_dp->output_reg);
2780 intel_wait_for_vblank(dev, intel_crtc->pipe);
2783 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2784 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2785 POSTING_READ(intel_dp->output_reg);
2786 msleep(intel_dp->panel_power_down_delay);
2790 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2792 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2793 struct drm_device *dev = dig_port->base.base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2796 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2798 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2799 sizeof(intel_dp->dpcd)) == 0)
2800 return false; /* aux transfer failed */
2802 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2803 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2804 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2806 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2807 return false; /* DPCD not present */
2809 /* Check if the panel supports PSR */
2810 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2811 if (is_edp(intel_dp)) {
2812 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2814 sizeof(intel_dp->psr_dpcd));
2815 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2816 dev_priv->psr.sink_support = true;
2817 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2821 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2822 DP_DWN_STRM_PORT_PRESENT))
2823 return true; /* native DP sink */
2825 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2826 return true; /* no per-port downstream info */
2828 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2829 intel_dp->downstream_ports,
2830 DP_MAX_DOWNSTREAM_PORTS) == 0)
2831 return false; /* downstream port status fetch failed */
2837 intel_dp_probe_oui(struct intel_dp *intel_dp)
2841 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2844 ironlake_edp_panel_vdd_on(intel_dp);
2846 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2847 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2848 buf[0], buf[1], buf[2]);
2850 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2851 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2852 buf[0], buf[1], buf[2]);
2854 ironlake_edp_panel_vdd_off(intel_dp, false);
2858 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2862 ret = intel_dp_aux_native_read_retry(intel_dp,
2863 DP_DEVICE_SERVICE_IRQ_VECTOR,
2864 sink_irq_vector, 1);
2872 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2874 /* NAK by default */
2875 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2879 * According to DP spec
2882 * 2. Configure link according to Receiver Capabilities
2883 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2884 * 4. Check link status on receipt of hot-plug interrupt
2888 intel_dp_check_link_status(struct intel_dp *intel_dp)
2890 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2892 u8 link_status[DP_LINK_STATUS_SIZE];
2894 if (!intel_encoder->connectors_active)
2897 if (WARN_ON(!intel_encoder->base.crtc))
2900 /* Try to read receiver status if the link appears to be up */
2901 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2902 intel_dp_link_down(intel_dp);
2906 /* Now read the DPCD to see if it's actually running */
2907 if (!intel_dp_get_dpcd(intel_dp)) {
2908 intel_dp_link_down(intel_dp);
2912 /* Try to read the source of the interrupt */
2913 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2914 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2915 /* Clear interrupt source */
2916 intel_dp_aux_native_write_1(intel_dp,
2917 DP_DEVICE_SERVICE_IRQ_VECTOR,
2920 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2921 intel_dp_handle_test_request(intel_dp);
2922 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2923 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2926 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2927 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2928 drm_get_encoder_name(&intel_encoder->base));
2929 intel_dp_start_link_train(intel_dp);
2930 intel_dp_complete_link_train(intel_dp);
2931 intel_dp_stop_link_train(intel_dp);
2935 /* XXX this is probably wrong for multiple downstream ports */
2936 static enum drm_connector_status
2937 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2939 uint8_t *dpcd = intel_dp->dpcd;
2942 if (!intel_dp_get_dpcd(intel_dp))
2943 return connector_status_disconnected;
2945 /* if there's no downstream port, we're done */
2946 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2947 return connector_status_connected;
2949 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2950 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2951 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2953 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2955 return connector_status_unknown;
2956 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2957 : connector_status_disconnected;
2960 /* If no HPD, poke DDC gently */
2961 if (drm_probe_ddc(&intel_dp->adapter))
2962 return connector_status_connected;
2964 /* Well we tried, say unknown for unreliable port types */
2965 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2966 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2967 if (type == DP_DS_PORT_TYPE_VGA ||
2968 type == DP_DS_PORT_TYPE_NON_EDID)
2969 return connector_status_unknown;
2971 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2972 DP_DWN_STRM_PORT_TYPE_MASK;
2973 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2974 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2975 return connector_status_unknown;
2978 /* Anything else is out of spec, warn and ignore */
2979 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2980 return connector_status_disconnected;
2983 static enum drm_connector_status
2984 ironlake_dp_detect(struct intel_dp *intel_dp)
2986 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2989 enum drm_connector_status status;
2991 /* Can't disconnect eDP, but you can close the lid... */
2992 if (is_edp(intel_dp)) {
2993 status = intel_panel_detect(dev);
2994 if (status == connector_status_unknown)
2995 status = connector_status_connected;
2999 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3000 return connector_status_disconnected;
3002 return intel_dp_detect_dpcd(intel_dp);
3005 static enum drm_connector_status
3006 g4x_dp_detect(struct intel_dp *intel_dp)
3008 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3013 /* Can't disconnect eDP, but you can close the lid... */
3014 if (is_edp(intel_dp)) {
3015 enum drm_connector_status status;
3017 status = intel_panel_detect(dev);
3018 if (status == connector_status_unknown)
3019 status = connector_status_connected;
3023 switch (intel_dig_port->port) {
3025 bit = PORTB_HOTPLUG_LIVE_STATUS;
3028 bit = PORTC_HOTPLUG_LIVE_STATUS;
3031 bit = PORTD_HOTPLUG_LIVE_STATUS;
3034 return connector_status_unknown;
3037 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3038 return connector_status_disconnected;
3040 return intel_dp_detect_dpcd(intel_dp);
3043 static struct edid *
3044 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3046 struct intel_connector *intel_connector = to_intel_connector(connector);
3048 /* use cached edid if we have one */
3049 if (intel_connector->edid) {
3051 if (IS_ERR(intel_connector->edid))
3054 return drm_edid_duplicate(intel_connector->edid);
3057 return drm_get_edid(connector, adapter);
3061 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3063 struct intel_connector *intel_connector = to_intel_connector(connector);
3065 /* use cached edid if we have one */
3066 if (intel_connector->edid) {
3068 if (IS_ERR(intel_connector->edid))
3071 return intel_connector_update_modes(connector,
3072 intel_connector->edid);
3075 return intel_ddc_get_modes(connector, adapter);
3078 static enum drm_connector_status
3079 intel_dp_detect(struct drm_connector *connector, bool force)
3081 struct intel_dp *intel_dp = intel_attached_dp(connector);
3082 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3083 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3084 struct drm_device *dev = connector->dev;
3085 enum drm_connector_status status;
3086 struct edid *edid = NULL;
3088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3089 connector->base.id, drm_get_connector_name(connector));
3091 intel_dp->has_audio = false;
3093 if (HAS_PCH_SPLIT(dev))
3094 status = ironlake_dp_detect(intel_dp);
3096 status = g4x_dp_detect(intel_dp);
3098 if (status != connector_status_connected)
3101 intel_dp_probe_oui(intel_dp);
3103 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3104 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3106 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3108 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3113 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3114 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3115 return connector_status_connected;
3118 static int intel_dp_get_modes(struct drm_connector *connector)
3120 struct intel_dp *intel_dp = intel_attached_dp(connector);
3121 struct intel_connector *intel_connector = to_intel_connector(connector);
3122 struct drm_device *dev = connector->dev;
3125 /* We should parse the EDID data and find out if it has an audio sink
3128 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3132 /* if eDP has no EDID, fall back to fixed mode */
3133 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3134 struct drm_display_mode *mode;
3135 mode = drm_mode_duplicate(dev,
3136 intel_connector->panel.fixed_mode);
3138 drm_mode_probed_add(connector, mode);
3146 intel_dp_detect_audio(struct drm_connector *connector)
3148 struct intel_dp *intel_dp = intel_attached_dp(connector);
3150 bool has_audio = false;
3152 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3154 has_audio = drm_detect_monitor_audio(edid);
3162 intel_dp_set_property(struct drm_connector *connector,
3163 struct drm_property *property,
3166 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3167 struct intel_connector *intel_connector = to_intel_connector(connector);
3168 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3169 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3172 ret = drm_object_property_set_value(&connector->base, property, val);
3176 if (property == dev_priv->force_audio_property) {
3180 if (i == intel_dp->force_audio)
3183 intel_dp->force_audio = i;
3185 if (i == HDMI_AUDIO_AUTO)
3186 has_audio = intel_dp_detect_audio(connector);
3188 has_audio = (i == HDMI_AUDIO_ON);
3190 if (has_audio == intel_dp->has_audio)
3193 intel_dp->has_audio = has_audio;
3197 if (property == dev_priv->broadcast_rgb_property) {
3198 bool old_auto = intel_dp->color_range_auto;
3199 uint32_t old_range = intel_dp->color_range;
3202 case INTEL_BROADCAST_RGB_AUTO:
3203 intel_dp->color_range_auto = true;
3205 case INTEL_BROADCAST_RGB_FULL:
3206 intel_dp->color_range_auto = false;
3207 intel_dp->color_range = 0;
3209 case INTEL_BROADCAST_RGB_LIMITED:
3210 intel_dp->color_range_auto = false;
3211 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3217 if (old_auto == intel_dp->color_range_auto &&
3218 old_range == intel_dp->color_range)
3224 if (is_edp(intel_dp) &&
3225 property == connector->dev->mode_config.scaling_mode_property) {
3226 if (val == DRM_MODE_SCALE_NONE) {
3227 DRM_DEBUG_KMS("no scaling not supported\n");
3231 if (intel_connector->panel.fitting_mode == val) {
3232 /* the eDP scaling property is not changed */
3235 intel_connector->panel.fitting_mode = val;
3243 if (intel_encoder->base.crtc)
3244 intel_crtc_restore_mode(intel_encoder->base.crtc);
3250 intel_dp_connector_destroy(struct drm_connector *connector)
3252 struct intel_connector *intel_connector = to_intel_connector(connector);
3254 if (!IS_ERR_OR_NULL(intel_connector->edid))
3255 kfree(intel_connector->edid);
3257 /* Can't call is_edp() since the encoder may have been destroyed
3259 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3260 intel_panel_fini(&intel_connector->panel);
3262 drm_connector_cleanup(connector);
3266 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3268 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3269 struct intel_dp *intel_dp = &intel_dig_port->dp;
3270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3272 i2c_del_adapter(&intel_dp->adapter);
3273 drm_encoder_cleanup(encoder);
3274 if (is_edp(intel_dp)) {
3275 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3276 mutex_lock(&dev->mode_config.mutex);
3277 ironlake_panel_vdd_off_sync(intel_dp);
3278 mutex_unlock(&dev->mode_config.mutex);
3280 kfree(intel_dig_port);
3283 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3284 .dpms = intel_connector_dpms,
3285 .detect = intel_dp_detect,
3286 .fill_modes = drm_helper_probe_single_connector_modes,
3287 .set_property = intel_dp_set_property,
3288 .destroy = intel_dp_connector_destroy,
3291 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3292 .get_modes = intel_dp_get_modes,
3293 .mode_valid = intel_dp_mode_valid,
3294 .best_encoder = intel_best_encoder,
3297 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3298 .destroy = intel_dp_encoder_destroy,
3302 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3304 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3306 intel_dp_check_link_status(intel_dp);
3309 /* Return which DP Port should be selected for Transcoder DP control */
3311 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3313 struct drm_device *dev = crtc->dev;
3314 struct intel_encoder *intel_encoder;
3315 struct intel_dp *intel_dp;
3317 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3318 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3320 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3321 intel_encoder->type == INTEL_OUTPUT_EDP)
3322 return intel_dp->output_reg;
3328 /* check the VBT to see whether the eDP is on DP-D port */
3329 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332 union child_device_config *p_child;
3334 static const short port_mapping[] = {
3335 [PORT_B] = PORT_IDPB,
3336 [PORT_C] = PORT_IDPC,
3337 [PORT_D] = PORT_IDPD,
3343 if (!dev_priv->vbt.child_dev_num)
3346 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3347 p_child = dev_priv->vbt.child_dev + i;
3349 if (p_child->common.dvo_port == port_mapping[port] &&
3350 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3351 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3358 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3360 struct intel_connector *intel_connector = to_intel_connector(connector);
3362 intel_attach_force_audio_property(connector);
3363 intel_attach_broadcast_rgb_property(connector);
3364 intel_dp->color_range_auto = true;
3366 if (is_edp(intel_dp)) {
3367 drm_mode_create_scaling_mode_property(connector->dev);
3368 drm_object_attach_property(
3370 connector->dev->mode_config.scaling_mode_property,
3371 DRM_MODE_SCALE_ASPECT);
3372 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3377 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3378 struct intel_dp *intel_dp,
3379 struct edp_power_seq *out)
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct edp_power_seq cur, vbt, spec, final;
3383 u32 pp_on, pp_off, pp_div, pp;
3384 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3386 if (HAS_PCH_SPLIT(dev)) {
3387 pp_ctrl_reg = PCH_PP_CONTROL;
3388 pp_on_reg = PCH_PP_ON_DELAYS;
3389 pp_off_reg = PCH_PP_OFF_DELAYS;
3390 pp_div_reg = PCH_PP_DIVISOR;
3392 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3394 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3395 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3396 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3397 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3400 /* Workaround: Need to write PP_CONTROL with the unlock key as
3401 * the very first thing. */
3402 pp = ironlake_get_pp_control(intel_dp);
3403 I915_WRITE(pp_ctrl_reg, pp);
3405 pp_on = I915_READ(pp_on_reg);
3406 pp_off = I915_READ(pp_off_reg);
3407 pp_div = I915_READ(pp_div_reg);
3409 /* Pull timing values out of registers */
3410 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3411 PANEL_POWER_UP_DELAY_SHIFT;
3413 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3414 PANEL_LIGHT_ON_DELAY_SHIFT;
3416 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3417 PANEL_LIGHT_OFF_DELAY_SHIFT;
3419 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3420 PANEL_POWER_DOWN_DELAY_SHIFT;
3422 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3423 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3425 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3426 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3428 vbt = dev_priv->vbt.edp_pps;
3430 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3431 * our hw here, which are all in 100usec. */
3432 spec.t1_t3 = 210 * 10;
3433 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3434 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3435 spec.t10 = 500 * 10;
3436 /* This one is special and actually in units of 100ms, but zero
3437 * based in the hw (so we need to add 100 ms). But the sw vbt
3438 * table multiplies it with 1000 to make it in units of 100usec,
3440 spec.t11_t12 = (510 + 100) * 10;
3442 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3443 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3445 /* Use the max of the register settings and vbt. If both are
3446 * unset, fall back to the spec limits. */
3447 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3449 max(cur.field, vbt.field))
3450 assign_final(t1_t3);
3454 assign_final(t11_t12);
3457 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3458 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3459 intel_dp->backlight_on_delay = get_delay(t8);
3460 intel_dp->backlight_off_delay = get_delay(t9);
3461 intel_dp->panel_power_down_delay = get_delay(t10);
3462 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3465 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3466 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3467 intel_dp->panel_power_cycle_delay);
3469 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3470 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3477 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3478 struct intel_dp *intel_dp,
3479 struct edp_power_seq *seq)
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 u32 pp_on, pp_off, pp_div, port_sel = 0;
3483 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3484 int pp_on_reg, pp_off_reg, pp_div_reg;
3486 if (HAS_PCH_SPLIT(dev)) {
3487 pp_on_reg = PCH_PP_ON_DELAYS;
3488 pp_off_reg = PCH_PP_OFF_DELAYS;
3489 pp_div_reg = PCH_PP_DIVISOR;
3491 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3493 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3494 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3495 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3498 /* And finally store the new values in the power sequencer. */
3499 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3500 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3501 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3502 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3503 /* Compute the divisor for the pp clock, simply match the Bspec
3505 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3506 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3507 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3509 /* Haswell doesn't have any port selection bits for the panel
3510 * power sequencer any more. */
3511 if (IS_VALLEYVIEW(dev)) {
3512 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3513 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3515 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3516 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3517 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3518 port_sel = PANEL_PORT_SELECT_DPA;
3520 port_sel = PANEL_PORT_SELECT_DPD;
3525 I915_WRITE(pp_on_reg, pp_on);
3526 I915_WRITE(pp_off_reg, pp_off);
3527 I915_WRITE(pp_div_reg, pp_div);
3529 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3530 I915_READ(pp_on_reg),
3531 I915_READ(pp_off_reg),
3532 I915_READ(pp_div_reg));
3535 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3536 struct intel_connector *intel_connector)
3538 struct drm_connector *connector = &intel_connector->base;
3539 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3540 struct drm_device *dev = intel_dig_port->base.base.dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 struct drm_display_mode *fixed_mode = NULL;
3543 struct edp_power_seq power_seq = { 0 };
3545 struct drm_display_mode *scan;
3548 if (!is_edp(intel_dp))
3551 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3553 /* Cache DPCD and EDID for edp. */
3554 ironlake_edp_panel_vdd_on(intel_dp);
3555 has_dpcd = intel_dp_get_dpcd(intel_dp);
3556 ironlake_edp_panel_vdd_off(intel_dp, false);
3559 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3560 dev_priv->no_aux_handshake =
3561 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3562 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3564 /* if this fails, presume the device is a ghost */
3565 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3569 /* We now know it's not a ghost, init power sequence regs. */
3570 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3573 edid = drm_get_edid(connector, &intel_dp->adapter);
3575 if (drm_add_edid_modes(connector, edid)) {
3576 drm_mode_connector_update_edid_property(connector,
3578 drm_edid_to_eld(connector, edid);
3581 edid = ERR_PTR(-EINVAL);
3584 edid = ERR_PTR(-ENOENT);
3586 intel_connector->edid = edid;
3588 /* prefer fixed mode from EDID if available */
3589 list_for_each_entry(scan, &connector->probed_modes, head) {
3590 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3591 fixed_mode = drm_mode_duplicate(dev, scan);
3596 /* fallback to VBT if available for eDP */
3597 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3598 fixed_mode = drm_mode_duplicate(dev,
3599 dev_priv->vbt.lfp_lvds_vbt_mode);
3601 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3604 intel_panel_init(&intel_connector->panel, fixed_mode);
3605 intel_panel_setup_backlight(connector);
3611 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3612 struct intel_connector *intel_connector)
3614 struct drm_connector *connector = &intel_connector->base;
3615 struct intel_dp *intel_dp = &intel_dig_port->dp;
3616 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3617 struct drm_device *dev = intel_encoder->base.dev;
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 enum port port = intel_dig_port->port;
3620 const char *name = NULL;
3623 /* Preserve the current hw state. */
3624 intel_dp->DP = I915_READ(intel_dp->output_reg);
3625 intel_dp->attached_connector = intel_connector;
3627 if (intel_dp_is_edp(dev, port))
3628 type = DRM_MODE_CONNECTOR_eDP;
3630 type = DRM_MODE_CONNECTOR_DisplayPort;
3633 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3634 * for DP the encoder type can be set by the caller to
3635 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3637 if (type == DRM_MODE_CONNECTOR_eDP)
3638 intel_encoder->type = INTEL_OUTPUT_EDP;
3640 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3641 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3644 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3645 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3647 connector->interlace_allowed = true;
3648 connector->doublescan_allowed = 0;
3650 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3651 ironlake_panel_vdd_work);
3653 intel_connector_attach_encoder(intel_connector, intel_encoder);
3654 drm_sysfs_connector_add(connector);
3657 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3659 intel_connector->get_hw_state = intel_connector_get_hw_state;
3661 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3663 switch (intel_dig_port->port) {
3665 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3668 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3671 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3674 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3681 /* Set up the DDC bus. */
3684 intel_encoder->hpd_pin = HPD_PORT_A;
3688 intel_encoder->hpd_pin = HPD_PORT_B;
3692 intel_encoder->hpd_pin = HPD_PORT_C;
3696 intel_encoder->hpd_pin = HPD_PORT_D;
3703 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3704 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3705 error, port_name(port));
3707 intel_dp->psr_setup_done = false;
3709 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3710 i2c_del_adapter(&intel_dp->adapter);
3711 if (is_edp(intel_dp)) {
3712 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3713 mutex_lock(&dev->mode_config.mutex);
3714 ironlake_panel_vdd_off_sync(intel_dp);
3715 mutex_unlock(&dev->mode_config.mutex);
3717 drm_sysfs_connector_remove(connector);
3718 drm_connector_cleanup(connector);
3722 intel_dp_add_properties(intel_dp, connector);
3724 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3725 * 0xd. Failure to do so will result in spurious interrupts being
3726 * generated on the port when a cable is not attached.
3728 if (IS_G4X(dev) && !IS_GM45(dev)) {
3729 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3730 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3737 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3739 struct intel_digital_port *intel_dig_port;
3740 struct intel_encoder *intel_encoder;
3741 struct drm_encoder *encoder;
3742 struct intel_connector *intel_connector;
3744 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3745 if (!intel_dig_port)
3748 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3749 if (!intel_connector) {
3750 kfree(intel_dig_port);
3754 intel_encoder = &intel_dig_port->base;
3755 encoder = &intel_encoder->base;
3757 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3758 DRM_MODE_ENCODER_TMDS);
3760 intel_encoder->compute_config = intel_dp_compute_config;
3761 intel_encoder->mode_set = intel_dp_mode_set;
3762 intel_encoder->disable = intel_disable_dp;
3763 intel_encoder->post_disable = intel_post_disable_dp;
3764 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3765 intel_encoder->get_config = intel_dp_get_config;
3766 if (IS_VALLEYVIEW(dev)) {
3767 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3768 intel_encoder->pre_enable = vlv_pre_enable_dp;
3769 intel_encoder->enable = vlv_enable_dp;
3771 intel_encoder->pre_enable = g4x_pre_enable_dp;
3772 intel_encoder->enable = g4x_enable_dp;
3775 intel_dig_port->port = port;
3776 intel_dig_port->dp.output_reg = output_reg;
3778 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3779 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3780 intel_encoder->cloneable = false;
3781 intel_encoder->hot_plug = intel_dp_hot_plug;
3783 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3784 drm_encoder_cleanup(encoder);
3785 kfree(intel_dig_port);
3786 kfree(intel_connector);