drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll gen4_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 111 {
 112         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 113
 114         return intel_dig_port->base.base.dev;
 115 }
 116
 117 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 118 {
 119         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 120 }
 121
 122 static void intel_dp_link_down(struct intel_encoder *encoder,
 123                                const struct intel_crtc_state *old_crtc_state);
 124 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 125 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 126 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 127                                            const struct intel_crtc_state *crtc_state);
 128 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 129                                       enum pipe pipe);
 130 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 131
 132 /* update sink rates from dpcd */
 133 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 134 {
 135         static const int dp_rates[] = {
 136                 162000, 270000, 540000, 810000
 137         };
 138         int i, max_rate;
 139
 140         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 141
 142         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 143                 if (dp_rates[i] > max_rate)
 144                         break;
 145                 intel_dp->sink_rates[i] = dp_rates[i];
 146         }
 147
 148         intel_dp->num_sink_rates = i;
 149 }
 150
 151 /* Get length of rates array potentially limited by max_rate. */
 152 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 153 {
 154         int i;
 155
 156         /* Limit results by potentially reduced max rate */
 157         for (i = 0; i < len; i++) {
 158                 if (rates[len - i - 1] <= max_rate)
 159                         return len - i;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /* Get length of common rates array potentially limited by max_rate. */
 166 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 167                                           int max_rate)
 168 {
 169         return intel_dp_rate_limit_len(intel_dp->common_rates,
 170                                        intel_dp->num_common_rates, max_rate);
 171 }
 172
 173 /* Theoretical max between source and sink */
 174 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 175 {
 176         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 177 }
 178
 179 /* Theoretical max between source and sink */
 180 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 181 {
 182         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 183         int source_max = intel_dig_port->max_lanes;
 184         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 185
 186         return min(source_max, sink_max);
 187 }
 188
 189 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 190 {
 191         return intel_dp->max_link_lane_count;
 192 }
 193
 194 int
 195 intel_dp_link_required(int pixel_clock, int bpp)
 196 {
 197         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 198         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 199 }
 200
 201 int
 202 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 203 {
 204         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 205          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 206          * is transmitted every LS_Clk per lane, there is no need to account for
 207          * the channel encoding that is done in the PHY layer here.
 208          */
 209
 210         return max_link_clock * max_lanes;
 211 }
 212
 213 static int
 214 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 215 {
 216         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 217         struct intel_encoder *encoder = &intel_dig_port->base;
 218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 219         int max_dotclk = dev_priv->max_dotclk_freq;
 220         int ds_max_dotclk;
 221
 222         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 223
 224         if (type != DP_DS_PORT_TYPE_VGA)
 225                 return max_dotclk;
 226
 227         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 228                                                     intel_dp->downstream_ports);
 229
 230         if (ds_max_dotclk != 0)
 231                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 232
 233         return max_dotclk;
 234 }
 235
 236 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 237 {
 238         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 239         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 240         enum port port = dig_port->base.port;
 241
 242         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 243
 244         /* Low voltage SKUs are limited to max of 5.4G */
 245         if (voltage == VOLTAGE_INFO_0_85V)
 246                 return 540000;
 247
 248         /* For this SKU 8.1G is supported in all ports */
 249         if (IS_CNL_WITH_PORT_F(dev_priv))
 250                 return 810000;
 251
 252         /* For other SKUs, max rate on ports A and D is 5.4G */
 253         if (port == PORT_A || port == PORT_D)
 254                 return 540000;
 255
 256         return 810000;
 257 }
 258
 259 static void
 260 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 261 {
 262         /* The values must be in increasing order */
 263         static const int cnl_rates[] = {
 264                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 265         };
 266         static const int bxt_rates[] = {
 267                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 268         };
 269         static const int skl_rates[] = {
 270                 162000, 216000, 270000, 324000, 432000, 540000
 271         };
 272         static const int hsw_rates[] = {
 273                 162000, 270000, 540000
 274         };
 275         static const int g4x_rates[] = {
 276                 162000, 270000
 277         };
 278         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 279         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 280         const struct ddi_vbt_port_info *info =
 281                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 282         const int *source_rates;
 283         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 284
 285         /* This should only be done once */
 286         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 287
 288         if (IS_CANNONLAKE(dev_priv)) {
 289                 source_rates = cnl_rates;
 290                 size = ARRAY_SIZE(cnl_rates);
 291                 max_rate = cnl_max_source_rate(intel_dp);
 292         } else if (IS_GEN9_LP(dev_priv)) {
 293                 source_rates = bxt_rates;
 294                 size = ARRAY_SIZE(bxt_rates);
 295         } else if (IS_GEN9_BC(dev_priv)) {
 296                 source_rates = skl_rates;
 297                 size = ARRAY_SIZE(skl_rates);
 298         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 299                    IS_BROADWELL(dev_priv)) {
 300                 source_rates = hsw_rates;
 301                 size = ARRAY_SIZE(hsw_rates);
 302         } else {
 303                 source_rates = g4x_rates;
 304                 size = ARRAY_SIZE(g4x_rates);
 305         }
 306
 307         if (max_rate && vbt_max_rate)
 308                 max_rate = min(max_rate, vbt_max_rate);
 309         else if (vbt_max_rate)
 310                 max_rate = vbt_max_rate;
 311
 312         if (max_rate)
 313                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 314
 315         intel_dp->source_rates = source_rates;
 316         intel_dp->num_source_rates = size;
 317 }
 318
 319 static int intersect_rates(const int *source_rates, int source_len,
 320                            const int *sink_rates, int sink_len,
 321                            int *common_rates)
 322 {
 323         int i = 0, j = 0, k = 0;
 324
 325         while (i < source_len && j < sink_len) {
 326                 if (source_rates[i] == sink_rates[j]) {
 327                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 328                                 return k;
 329                         common_rates[k] = source_rates[i];
 330                         ++k;
 331                         ++i;
 332                         ++j;
 333                 } else if (source_rates[i] < sink_rates[j]) {
 334                         ++i;
 335                 } else {
 336                         ++j;
 337                 }
 338         }
 339         return k;
 340 }
 341
 342 /* return index of rate in rates array, or -1 if not found */
 343 static int intel_dp_rate_index(const int *rates, int len, int rate)
 344 {
 345         int i;
 346
 347         for (i = 0; i < len; i++)
 348                 if (rate == rates[i])
 349                         return i;
 350
 351         return -1;
 352 }
 353
 354 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 355 {
 356         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 357
 358         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 359                                                      intel_dp->num_source_rates,
 360                                                      intel_dp->sink_rates,
 361                                                      intel_dp->num_sink_rates,
 362                                                      intel_dp->common_rates);
 363
 364         /* Paranoia, there should always be something in common. */
 365         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 366                 intel_dp->common_rates[0] = 162000;
 367                 intel_dp->num_common_rates = 1;
 368         }
 369 }
 370
 371 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 372                                        uint8_t lane_count)
 373 {
 374         /*
 375          * FIXME: we need to synchronize the current link parameters with
 376          * hardware readout. Currently fast link training doesn't work on
 377          * boot-up.
 378          */
 379         if (link_rate == 0 ||
 380             link_rate > intel_dp->max_link_rate)
 381                 return false;
 382
 383         if (lane_count == 0 ||
 384             lane_count > intel_dp_max_lane_count(intel_dp))
 385                 return false;
 386
 387         return true;
 388 }
 389
 390 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 391                                             int link_rate, uint8_t lane_count)
 392 {
 393         int index;
 394
 395         index = intel_dp_rate_index(intel_dp->common_rates,
 396                                     intel_dp->num_common_rates,
 397                                     link_rate);
 398         if (index > 0) {
 399                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 400                 intel_dp->max_link_lane_count = lane_count;
 401         } else if (lane_count > 1) {
 402                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 403                 intel_dp->max_link_lane_count = lane_count >> 1;
 404         } else {
 405                 DRM_ERROR("Link Training Unsuccessful\n");
 406                 return -1;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static enum drm_mode_status
 413 intel_dp_mode_valid(struct drm_connector *connector,
 414                     struct drm_display_mode *mode)
 415 {
 416         struct intel_dp *intel_dp = intel_attached_dp(connector);
 417         struct intel_connector *intel_connector = to_intel_connector(connector);
 418         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 419         int target_clock = mode->clock;
 420         int max_rate, mode_rate, max_lanes, max_link_clock;
 421         int max_dotclk;
 422
 423         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 424                 return MODE_NO_DBLESCAN;
 425
 426         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 427
 428         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 429                 if (mode->hdisplay > fixed_mode->hdisplay)
 430                         return MODE_PANEL;
 431
 432                 if (mode->vdisplay > fixed_mode->vdisplay)
 433                         return MODE_PANEL;
 434
 435                 target_clock = fixed_mode->clock;
 436         }
 437
 438         max_link_clock = intel_dp_max_link_rate(intel_dp);
 439         max_lanes = intel_dp_max_lane_count(intel_dp);
 440
 441         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 442         mode_rate = intel_dp_link_required(target_clock, 18);
 443
 444         if (mode_rate > max_rate || target_clock > max_dotclk)
 445                 return MODE_CLOCK_HIGH;
 446
 447         if (mode->clock < 10000)
 448                 return MODE_CLOCK_LOW;
 449
 450         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 451                 return MODE_H_ILLEGAL;
 452
 453         return MODE_OK;
 454 }
 455
 456 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 457 {
 458         int     i;
 459         uint32_t v = 0;
 460
 461         if (src_bytes > 4)
 462                 src_bytes = 4;
 463         for (i = 0; i < src_bytes; i++)
 464                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 465         return v;
 466 }
 467
 468 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 469 {
 470         int i;
 471         if (dst_bytes > 4)
 472                 dst_bytes = 4;
 473         for (i = 0; i < dst_bytes; i++)
 474                 dst[i] = src >> ((3-i) * 8);
 475 }
 476
 477 static void
 478 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 479 static void
 480 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 481                                               bool force_disable_vdd);
 482 static void
 483 intel_dp_pps_init(struct intel_dp *intel_dp);
 484
 485 static void pps_lock(struct intel_dp *intel_dp)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 488
 489         /*
 490          * See intel_power_sequencer_reset() why we need
 491          * a power domain reference here.
 492          */
 493         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 494
 495         mutex_lock(&dev_priv->pps_mutex);
 496 }
 497
 498 static void pps_unlock(struct intel_dp *intel_dp)
 499 {
 500         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 501
 502         mutex_unlock(&dev_priv->pps_mutex);
 503
 504         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 505 }
 506
 507 static void
 508 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 509 {
 510         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 511         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 512         enum pipe pipe = intel_dp->pps_pipe;
 513         bool pll_enabled, release_cl_override = false;
 514         enum dpio_phy phy = DPIO_PHY(pipe);
 515         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 516         uint32_t DP;
 517
 518         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 519                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 520                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 521                 return;
 522
 523         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 524                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 525
 526         /* Preserve the BIOS-computed detected bit. This is
 527          * supposed to be read-only.
 528          */
 529         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 530         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 531         DP |= DP_PORT_WIDTH(1);
 532         DP |= DP_LINK_TRAIN_PAT_1;
 533
 534         if (IS_CHERRYVIEW(dev_priv))
 535                 DP |= DP_PIPE_SELECT_CHV(pipe);
 536         else if (pipe == PIPE_B)
 537                 DP |= DP_PIPEB_SELECT;
 538
 539         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 540
 541         /*
 542          * The DPLL for the pipe must be enabled for this to work.
 543          * So enable temporarily it if it's not already enabled.
 544          */
 545         if (!pll_enabled) {
 546                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 547                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 548
 549                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 550                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 551                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 552                                   pipe_name(pipe));
 553                         return;
 554                 }
 555         }
 556
 557         /*
 558          * Similar magic as in intel_dp_enable_port().
 559          * We _must_ do this port enable + disable trick
 560          * to make this power seqeuencer lock onto the port.
 561          * Otherwise even VDD force bit won't work.
 562          */
 563         I915_WRITE(intel_dp->output_reg, DP);
 564         POSTING_READ(intel_dp->output_reg);
 565
 566         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 567         POSTING_READ(intel_dp->output_reg);
 568
 569         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 570         POSTING_READ(intel_dp->output_reg);
 571
 572         if (!pll_enabled) {
 573                 vlv_force_pll_off(dev_priv, pipe);
 574
 575                 if (release_cl_override)
 576                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 577         }
 578 }
 579
 580 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 581 {
 582         struct intel_encoder *encoder;
 583         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 584
 585         /*
 586          * We don't have power sequencer currently.
 587          * Pick one that's not used by other ports.
 588          */
 589         for_each_intel_encoder(&dev_priv->drm, encoder) {
 590                 struct intel_dp *intel_dp;
 591
 592                 if (encoder->type != INTEL_OUTPUT_DP &&
 593                     encoder->type != INTEL_OUTPUT_EDP)
 594                         continue;
 595
 596                 intel_dp = enc_to_intel_dp(&encoder->base);
 597
 598                 if (encoder->type == INTEL_OUTPUT_EDP) {
 599                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 600                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 601
 602                         if (intel_dp->pps_pipe != INVALID_PIPE)
 603                                 pipes &= ~(1 << intel_dp->pps_pipe);
 604                 } else {
 605                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 606
 607                         if (intel_dp->active_pipe != INVALID_PIPE)
 608                                 pipes &= ~(1 << intel_dp->active_pipe);
 609                 }
 610         }
 611
 612         if (pipes == 0)
 613                 return INVALID_PIPE;
 614
 615         return ffs(pipes) - 1;
 616 }
 617
 618 static enum pipe
 619 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 620 {
 621         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 622         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 623         enum pipe pipe;
 624
 625         lockdep_assert_held(&dev_priv->pps_mutex);
 626
 627         /* We should never land here with regular DP ports */
 628         WARN_ON(!intel_dp_is_edp(intel_dp));
 629
 630         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 631                 intel_dp->active_pipe != intel_dp->pps_pipe);
 632
 633         if (intel_dp->pps_pipe != INVALID_PIPE)
 634                 return intel_dp->pps_pipe;
 635
 636         pipe = vlv_find_free_pps(dev_priv);
 637
 638         /*
 639          * Didn't find one. This should not happen since there
 640          * are two power sequencers and up to two eDP ports.
 641          */
 642         if (WARN_ON(pipe == INVALID_PIPE))
 643                 pipe = PIPE_A;
 644
 645         vlv_steal_power_sequencer(dev_priv, pipe);
 646         intel_dp->pps_pipe = pipe;
 647
 648         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 649                       pipe_name(intel_dp->pps_pipe),
 650                       port_name(intel_dig_port->base.port));
 651
 652         /* init power sequencer on this pipe and port */
 653         intel_dp_init_panel_power_sequencer(intel_dp);
 654         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 655
 656         /*
 657          * Even vdd force doesn't work until we've made
 658          * the power sequencer lock in on the port.
 659          */
 660         vlv_power_sequencer_kick(intel_dp);
 661
 662         return intel_dp->pps_pipe;
 663 }
 664
 665 static int
 666 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 667 {
 668         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 669         int backlight_controller = dev_priv->vbt.backlight.controller;
 670
 671         lockdep_assert_held(&dev_priv->pps_mutex);
 672
 673         /* We should never land here with regular DP ports */
 674         WARN_ON(!intel_dp_is_edp(intel_dp));
 675
 676         if (!intel_dp->pps_reset)
 677                 return backlight_controller;
 678
 679         intel_dp->pps_reset = false;
 680
 681         /*
 682          * Only the HW needs to be reprogrammed, the SW state is fixed and
 683          * has been setup during connector init.
 684          */
 685         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 686
 687         return backlight_controller;
 688 }
 689
 690 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 691                                enum pipe pipe);
 692
 693 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 694                                enum pipe pipe)
 695 {
 696         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 697 }
 698
 699 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 700                                 enum pipe pipe)
 701 {
 702         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 703 }
 704
 705 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 706                          enum pipe pipe)
 707 {
 708         return true;
 709 }
 710
 711 static enum pipe
 712 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 713                      enum port port,
 714                      vlv_pipe_check pipe_check)
 715 {
 716         enum pipe pipe;
 717
 718         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 719                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 720                         PANEL_PORT_SELECT_MASK;
 721
 722                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 723                         continue;
 724
 725                 if (!pipe_check(dev_priv, pipe))
 726                         continue;
 727
 728                 return pipe;
 729         }
 730
 731         return INVALID_PIPE;
 732 }
 733
 734 static void
 735 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 736 {
 737         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 738         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 739         enum port port = intel_dig_port->base.port;
 740
 741         lockdep_assert_held(&dev_priv->pps_mutex);
 742
 743         /* try to find a pipe with this port selected */
 744         /* first pick one where the panel is on */
 745         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 746                                                   vlv_pipe_has_pp_on);
 747         /* didn't find one? pick one where vdd is on */
 748         if (intel_dp->pps_pipe == INVALID_PIPE)
 749                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 750                                                           vlv_pipe_has_vdd_on);
 751         /* didn't find one? pick one with just the correct port */
 752         if (intel_dp->pps_pipe == INVALID_PIPE)
 753                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 754                                                           vlv_pipe_any);
 755
 756         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 757         if (intel_dp->pps_pipe == INVALID_PIPE) {
 758                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 759                               port_name(port));
 760                 return;
 761         }
 762
 763         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 764                       port_name(port), pipe_name(intel_dp->pps_pipe));
 765
 766         intel_dp_init_panel_power_sequencer(intel_dp);
 767         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 768 }
 769
 770 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 771 {
 772         struct intel_encoder *encoder;
 773
 774         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 775                     !IS_GEN9_LP(dev_priv)))
 776                 return;
 777
 778         /*
 779          * We can't grab pps_mutex here due to deadlock with power_domain
 780          * mutex when power_domain functions are called while holding pps_mutex.
 781          * That also means that in order to use pps_pipe the code needs to
 782          * hold both a power domain reference and pps_mutex, and the power domain
 783          * reference get/put must be done while _not_ holding pps_mutex.
 784          * pps_{lock,unlock}() do these steps in the correct order, so one
 785          * should use them always.
 786          */
 787
 788         for_each_intel_encoder(&dev_priv->drm, encoder) {
 789                 struct intel_dp *intel_dp;
 790
 791                 if (encoder->type != INTEL_OUTPUT_DP &&
 792                     encoder->type != INTEL_OUTPUT_EDP &&
 793                     encoder->type != INTEL_OUTPUT_DDI)
 794                         continue;
 795
 796                 intel_dp = enc_to_intel_dp(&encoder->base);
 797
 798                 /* Skip pure DVI/HDMI DDI encoders */
 799                 if (!i915_mmio_reg_valid(intel_dp->output_reg))
 800                         continue;
 801
 802                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 803
 804                 if (encoder->type != INTEL_OUTPUT_EDP)
 805                         continue;
 806
 807                 if (IS_GEN9_LP(dev_priv))
 808                         intel_dp->pps_reset = true;
 809                 else
 810                         intel_dp->pps_pipe = INVALID_PIPE;
 811         }
 812 }
 813
 814 struct pps_registers {
 815         i915_reg_t pp_ctrl;
 816         i915_reg_t pp_stat;
 817         i915_reg_t pp_on;
 818         i915_reg_t pp_off;
 819         i915_reg_t pp_div;
 820 };
 821
 822 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 823                                     struct pps_registers *regs)
 824 {
 825         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 826         int pps_idx = 0;
 827
 828         memset(regs, 0, sizeof(*regs));
 829
 830         if (IS_GEN9_LP(dev_priv))
 831                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 832         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 833                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 834
 835         regs->pp_ctrl = PP_CONTROL(pps_idx);
 836         regs->pp_stat = PP_STATUS(pps_idx);
 837         regs->pp_on = PP_ON_DELAYS(pps_idx);
 838         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 839         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 840             !HAS_PCH_ICP(dev_priv))
 841                 regs->pp_div = PP_DIVISOR(pps_idx);
 842 }
 843
 844 static i915_reg_t
 845 _pp_ctrl_reg(struct intel_dp *intel_dp)
 846 {
 847         struct pps_registers regs;
 848
 849         intel_pps_get_registers(intel_dp, &regs);
 850
 851         return regs.pp_ctrl;
 852 }
 853
 854 static i915_reg_t
 855 _pp_stat_reg(struct intel_dp *intel_dp)
 856 {
 857         struct pps_registers regs;
 858
 859         intel_pps_get_registers(intel_dp, &regs);
 860
 861         return regs.pp_stat;
 862 }
 863
 864 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 865    This function only applicable when panel PM state is not to be tracked */
 866 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 867                               void *unused)
 868 {
 869         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 870                                                  edp_notifier);
 871         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 872
 873         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 874                 return 0;
 875
 876         pps_lock(intel_dp);
 877
 878         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 879                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 880                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 881                 u32 pp_div;
 882
 883                 pp_ctrl_reg = PP_CONTROL(pipe);
 884                 pp_div_reg  = PP_DIVISOR(pipe);
 885                 pp_div = I915_READ(pp_div_reg);
 886                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 887
 888                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 889                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 890                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 891                 msleep(intel_dp->panel_power_cycle_delay);
 892         }
 893
 894         pps_unlock(intel_dp);
 895
 896         return 0;
 897 }
 898
 899 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 902
 903         lockdep_assert_held(&dev_priv->pps_mutex);
 904
 905         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 906             intel_dp->pps_pipe == INVALID_PIPE)
 907                 return false;
 908
 909         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 910 }
 911
 912 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 913 {
 914         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 915
 916         lockdep_assert_held(&dev_priv->pps_mutex);
 917
 918         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 919             intel_dp->pps_pipe == INVALID_PIPE)
 920                 return false;
 921
 922         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 923 }
 924
 925 static void
 926 intel_dp_check_edp(struct intel_dp *intel_dp)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 929
 930         if (!intel_dp_is_edp(intel_dp))
 931                 return;
 932
 933         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 934                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 935                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 936                               I915_READ(_pp_stat_reg(intel_dp)),
 937                               I915_READ(_pp_ctrl_reg(intel_dp)));
 938         }
 939 }
 940
 941 static uint32_t
 942 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 943 {
 944         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 945         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
 946         uint32_t status;
 947         bool done;
 948
 949 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 950         if (has_aux_irq)
 951                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 952                                           msecs_to_jiffies_timeout(10));
 953         else
 954                 done = wait_for(C, 10) == 0;
 955         if (!done)
 956                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 957                           has_aux_irq);
 958 #undef C
 959
 960         return status;
 961 }
 962
 963 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 966
 967         if (index)
 968                 return 0;
 969
 970         /*
 971          * The clock divider is based off the hrawclk, and would like to run at
 972          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 973          */
 974         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 975 }
 976
 977 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 978 {
 979         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 980
 981         if (index)
 982                 return 0;
 983
 984         /*
 985          * The clock divider is based off the cdclk or PCH rawclk, and would
 986          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 987          * divide by 2000 and use that
 988          */
 989         if (intel_dp->aux_ch == AUX_CH_A)
 990                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 991         else
 992                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 993 }
 994
 995 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 996 {
 997         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 998
 999         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1000                 /* Workaround for non-ULT HSW */
1001                 switch (index) {
1002                 case 0: return 63;
1003                 case 1: return 72;
1004                 default: return 0;
1005                 }
1006         }
1007
1008         return ilk_get_aux_clock_divider(intel_dp, index);
1009 }
1010
1011 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1012 {
1013         /*
1014          * SKL doesn't need us to program the AUX clock divider (Hardware will
1015          * derive the clock from CDCLK automatically). We still implement the
1016          * get_aux_clock_divider vfunc to plug-in into the existing code.
1017          */
1018         return index ? 0 : 1;
1019 }
1020
1021 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1022                                      bool has_aux_irq,
1023                                      int send_bytes,
1024                                      uint32_t aux_clock_divider)
1025 {
1026         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1027         struct drm_i915_private *dev_priv =
1028                         to_i915(intel_dig_port->base.base.dev);
1029         uint32_t precharge, timeout;
1030
1031         if (IS_GEN6(dev_priv))
1032                 precharge = 3;
1033         else
1034                 precharge = 5;
1035
1036         if (IS_BROADWELL(dev_priv))
1037                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1038         else
1039                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1040
1041         return DP_AUX_CH_CTL_SEND_BUSY |
1042                DP_AUX_CH_CTL_DONE |
1043                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1044                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1045                timeout |
1046                DP_AUX_CH_CTL_RECEIVE_ERROR |
1047                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1048                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1049                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1050 }
1051
1052 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1053                                       bool has_aux_irq,
1054                                       int send_bytes,
1055                                       uint32_t unused)
1056 {
1057         return DP_AUX_CH_CTL_SEND_BUSY |
1058                DP_AUX_CH_CTL_DONE |
1059                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1060                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1061                DP_AUX_CH_CTL_TIME_OUT_MAX |
1062                DP_AUX_CH_CTL_RECEIVE_ERROR |
1063                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1064                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1065                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1066 }
1067
1068 static int
1069 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1070                   const uint8_t *send, int send_bytes,
1071                   uint8_t *recv, int recv_size,
1072                   u32 aux_send_ctl_flags)
1073 {
1074         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1075         struct drm_i915_private *dev_priv =
1076                         to_i915(intel_dig_port->base.base.dev);
1077         i915_reg_t ch_ctl, ch_data[5];
1078         uint32_t aux_clock_divider;
1079         int i, ret, recv_bytes;
1080         uint32_t status;
1081         int try, clock = 0;
1082         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1083         bool vdd;
1084
1085         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1086         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1087                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1088
1089         pps_lock(intel_dp);
1090
1091         /*
1092          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1093          * In such cases we want to leave VDD enabled and it's up to upper layers
1094          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1095          * ourselves.
1096          */
1097         vdd = edp_panel_vdd_on(intel_dp);
1098
1099         /* dp aux is extremely sensitive to irq latency, hence request the
1100          * lowest possible wakeup latency and so prevent the cpu from going into
1101          * deep sleep states.
1102          */
1103         pm_qos_update_request(&dev_priv->pm_qos, 0);
1104
1105         intel_dp_check_edp(intel_dp);
1106
1107         /* Try to wait for any previous AUX channel activity */
1108         for (try = 0; try < 3; try++) {
1109                 status = I915_READ_NOTRACE(ch_ctl);
1110                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1111                         break;
1112                 msleep(1);
1113         }
1114
1115         if (try == 3) {
1116                 static u32 last_status = -1;
1117                 const u32 status = I915_READ(ch_ctl);
1118
1119                 if (status != last_status) {
1120                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1121                              status);
1122                         last_status = status;
1123                 }
1124
1125                 ret = -EBUSY;
1126                 goto out;
1127         }
1128
1129         /* Only 5 data registers! */
1130         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1131                 ret = -E2BIG;
1132                 goto out;
1133         }
1134
1135         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1136                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1137                                                           has_aux_irq,
1138                                                           send_bytes,
1139                                                           aux_clock_divider);
1140
1141                 send_ctl |= aux_send_ctl_flags;
1142
1143                 /* Must try at least 3 times according to DP spec */
1144                 for (try = 0; try < 5; try++) {
1145                         /* Load the send data into the aux channel data registers */
1146                         for (i = 0; i < send_bytes; i += 4)
1147                                 I915_WRITE(ch_data[i >> 2],
1148                                            intel_dp_pack_aux(send + i,
1149                                                              send_bytes - i));
1150
1151                         /* Send the command and wait for it to complete */
1152                         I915_WRITE(ch_ctl, send_ctl);
1153
1154                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1155
1156                         /* Clear done status and any errors */
1157                         I915_WRITE(ch_ctl,
1158                                    status |
1159                                    DP_AUX_CH_CTL_DONE |
1160                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1161                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1162
1163                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1164                          *   400us delay required for errors and timeouts
1165                          *   Timeout errors from the HW already meet this
1166                          *   requirement so skip to next iteration
1167                          */
1168                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1169                                 continue;
1170
1171                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1172                                 usleep_range(400, 500);
1173                                 continue;
1174                         }
1175                         if (status & DP_AUX_CH_CTL_DONE)
1176                                 goto done;
1177                 }
1178         }
1179
1180         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1181                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1182                 ret = -EBUSY;
1183                 goto out;
1184         }
1185
1186 done:
1187         /* Check for timeout or receive error.
1188          * Timeouts occur when the sink is not connected
1189          */
1190         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1191                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1192                 ret = -EIO;
1193                 goto out;
1194         }
1195
1196         /* Timeouts occur when the device isn't connected, so they're
1197          * "normal" -- don't fill the kernel log with these */
1198         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1199                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1200                 ret = -ETIMEDOUT;
1201                 goto out;
1202         }
1203
1204         /* Unload any bytes sent back from the other side */
1205         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1206                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1207
1208         /*
1209          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1210          * We have no idea of what happened so we return -EBUSY so
1211          * drm layer takes care for the necessary retries.
1212          */
1213         if (recv_bytes == 0 || recv_bytes > 20) {
1214                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1215                               recv_bytes);
1216                 ret = -EBUSY;
1217                 goto out;
1218         }
1219
1220         if (recv_bytes > recv_size)
1221                 recv_bytes = recv_size;
1222
1223         for (i = 0; i < recv_bytes; i += 4)
1224                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1225                                     recv + i, recv_bytes - i);
1226
1227         ret = recv_bytes;
1228 out:
1229         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1230
1231         if (vdd)
1232                 edp_panel_vdd_off(intel_dp, false);
1233
1234         pps_unlock(intel_dp);
1235
1236         return ret;
1237 }
1238
1239 #define BARE_ADDRESS_SIZE       3
1240 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1241
1242 static void
1243 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1244                     const struct drm_dp_aux_msg *msg)
1245 {
1246         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1247         txbuf[1] = (msg->address >> 8) & 0xff;
1248         txbuf[2] = msg->address & 0xff;
1249         txbuf[3] = msg->size - 1;
1250 }
1251
1252 static ssize_t
1253 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1254 {
1255         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1256         uint8_t txbuf[20], rxbuf[20];
1257         size_t txsize, rxsize;
1258         int ret;
1259
1260         intel_dp_aux_header(txbuf, msg);
1261
1262         switch (msg->request & ~DP_AUX_I2C_MOT) {
1263         case DP_AUX_NATIVE_WRITE:
1264         case DP_AUX_I2C_WRITE:
1265         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1266                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1267                 rxsize = 2; /* 0 or 1 data bytes */
1268
1269                 if (WARN_ON(txsize > 20))
1270                         return -E2BIG;
1271
1272                 WARN_ON(!msg->buffer != !msg->size);
1273
1274                 if (msg->buffer)
1275                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1276
1277                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1278                                         rxbuf, rxsize, 0);
1279                 if (ret > 0) {
1280                         msg->reply = rxbuf[0] >> 4;
1281
1282                         if (ret > 1) {
1283                                 /* Number of bytes written in a short write. */
1284                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1285                         } else {
1286                                 /* Return payload size. */
1287                                 ret = msg->size;
1288                         }
1289                 }
1290                 break;
1291
1292         case DP_AUX_NATIVE_READ:
1293         case DP_AUX_I2C_READ:
1294                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1295                 rxsize = msg->size + 1;
1296
1297                 if (WARN_ON(rxsize > 20))
1298                         return -E2BIG;
1299
1300                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1301                                         rxbuf, rxsize, 0);
1302                 if (ret > 0) {
1303                         msg->reply = rxbuf[0] >> 4;
1304                         /*
1305                          * Assume happy day, and copy the data. The caller is
1306                          * expected to check msg->reply before touching it.
1307                          *
1308                          * Return payload size.
1309                          */
1310                         ret--;
1311                         memcpy(msg->buffer, rxbuf + 1, ret);
1312                 }
1313                 break;
1314
1315         default:
1316                 ret = -EINVAL;
1317                 break;
1318         }
1319
1320         return ret;
1321 }
1322
1323 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1324 {
1325         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1327         enum port port = encoder->port;
1328         const struct ddi_vbt_port_info *info =
1329                 &dev_priv->vbt.ddi_port_info[port];
1330         enum aux_ch aux_ch;
1331
1332         if (!info->alternate_aux_channel) {
1333                 aux_ch = (enum aux_ch) port;
1334
1335                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1336                               aux_ch_name(aux_ch), port_name(port));
1337                 return aux_ch;
1338         }
1339
1340         switch (info->alternate_aux_channel) {
1341         case DP_AUX_A:
1342                 aux_ch = AUX_CH_A;
1343                 break;
1344         case DP_AUX_B:
1345                 aux_ch = AUX_CH_B;
1346                 break;
1347         case DP_AUX_C:
1348                 aux_ch = AUX_CH_C;
1349                 break;
1350         case DP_AUX_D:
1351                 aux_ch = AUX_CH_D;
1352                 break;
1353         case DP_AUX_F:
1354                 aux_ch = AUX_CH_F;
1355                 break;
1356         default:
1357                 MISSING_CASE(info->alternate_aux_channel);
1358                 aux_ch = AUX_CH_A;
1359                 break;
1360         }
1361
1362         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1363                       aux_ch_name(aux_ch), port_name(port));
1364
1365         return aux_ch;
1366 }
1367
1368 static enum intel_display_power_domain
1369 intel_aux_power_domain(struct intel_dp *intel_dp)
1370 {
1371         switch (intel_dp->aux_ch) {
1372         case AUX_CH_A:
1373                 return POWER_DOMAIN_AUX_A;
1374         case AUX_CH_B:
1375                 return POWER_DOMAIN_AUX_B;
1376         case AUX_CH_C:
1377                 return POWER_DOMAIN_AUX_C;
1378         case AUX_CH_D:
1379                 return POWER_DOMAIN_AUX_D;
1380         case AUX_CH_F:
1381                 return POWER_DOMAIN_AUX_F;
1382         default:
1383                 MISSING_CASE(intel_dp->aux_ch);
1384                 return POWER_DOMAIN_AUX_A;
1385         }
1386 }
1387
1388 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1389 {
1390         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1391         enum aux_ch aux_ch = intel_dp->aux_ch;
1392
1393         switch (aux_ch) {
1394         case AUX_CH_B:
1395         case AUX_CH_C:
1396         case AUX_CH_D:
1397                 return DP_AUX_CH_CTL(aux_ch);
1398         default:
1399                 MISSING_CASE(aux_ch);
1400                 return DP_AUX_CH_CTL(AUX_CH_B);
1401         }
1402 }
1403
1404 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1405 {
1406         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1407         enum aux_ch aux_ch = intel_dp->aux_ch;
1408
1409         switch (aux_ch) {
1410         case AUX_CH_B:
1411         case AUX_CH_C:
1412         case AUX_CH_D:
1413                 return DP_AUX_CH_DATA(aux_ch, index);
1414         default:
1415                 MISSING_CASE(aux_ch);
1416                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1417         }
1418 }
1419
1420 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1421 {
1422         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1423         enum aux_ch aux_ch = intel_dp->aux_ch;
1424
1425         switch (aux_ch) {
1426         case AUX_CH_A:
1427                 return DP_AUX_CH_CTL(aux_ch);
1428         case AUX_CH_B:
1429         case AUX_CH_C:
1430         case AUX_CH_D:
1431                 return PCH_DP_AUX_CH_CTL(aux_ch);
1432         default:
1433                 MISSING_CASE(aux_ch);
1434                 return DP_AUX_CH_CTL(AUX_CH_A);
1435         }
1436 }
1437
1438 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1439 {
1440         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1441         enum aux_ch aux_ch = intel_dp->aux_ch;
1442
1443         switch (aux_ch) {
1444         case AUX_CH_A:
1445                 return DP_AUX_CH_DATA(aux_ch, index);
1446         case AUX_CH_B:
1447         case AUX_CH_C:
1448         case AUX_CH_D:
1449                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1450         default:
1451                 MISSING_CASE(aux_ch);
1452                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1453         }
1454 }
1455
1456 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1457 {
1458         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1459         enum aux_ch aux_ch = intel_dp->aux_ch;
1460
1461         switch (aux_ch) {
1462         case AUX_CH_A:
1463         case AUX_CH_B:
1464         case AUX_CH_C:
1465         case AUX_CH_D:
1466         case AUX_CH_F:
1467                 return DP_AUX_CH_CTL(aux_ch);
1468         default:
1469                 MISSING_CASE(aux_ch);
1470                 return DP_AUX_CH_CTL(AUX_CH_A);
1471         }
1472 }
1473
1474 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1475 {
1476         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1477         enum aux_ch aux_ch = intel_dp->aux_ch;
1478
1479         switch (aux_ch) {
1480         case AUX_CH_A:
1481         case AUX_CH_B:
1482         case AUX_CH_C:
1483         case AUX_CH_D:
1484         case AUX_CH_F:
1485                 return DP_AUX_CH_DATA(aux_ch, index);
1486         default:
1487                 MISSING_CASE(aux_ch);
1488                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1489         }
1490 }
1491
1492 static void
1493 intel_dp_aux_fini(struct intel_dp *intel_dp)
1494 {
1495         kfree(intel_dp->aux.name);
1496 }
1497
1498 static void
1499 intel_dp_aux_init(struct intel_dp *intel_dp)
1500 {
1501         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1502         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1503
1504         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1505         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1506
1507         if (INTEL_GEN(dev_priv) >= 9) {
1508                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1509                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1510         } else if (HAS_PCH_SPLIT(dev_priv)) {
1511                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1512                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1513         } else {
1514                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1515                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1516         }
1517
1518         if (INTEL_GEN(dev_priv) >= 9)
1519                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1520         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1521                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1522         else if (HAS_PCH_SPLIT(dev_priv))
1523                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1524         else
1525                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1526
1527         if (INTEL_GEN(dev_priv) >= 9)
1528                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1529         else
1530                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1531
1532         drm_dp_aux_init(&intel_dp->aux);
1533
1534         /* Failure to allocate our preferred name is not critical */
1535         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1536                                        port_name(encoder->port));
1537         intel_dp->aux.transfer = intel_dp_aux_transfer;
1538 }
1539
1540 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1541 {
1542         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1543
1544         return max_rate >= 540000;
1545 }
1546
1547 static void
1548 intel_dp_set_clock(struct intel_encoder *encoder,
1549                    struct intel_crtc_state *pipe_config)
1550 {
1551         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1552         const struct dp_link_dpll *divisor = NULL;
1553         int i, count = 0;
1554
1555         if (IS_G4X(dev_priv)) {
1556                 divisor = gen4_dpll;
1557                 count = ARRAY_SIZE(gen4_dpll);
1558         } else if (HAS_PCH_SPLIT(dev_priv)) {
1559                 divisor = pch_dpll;
1560                 count = ARRAY_SIZE(pch_dpll);
1561         } else if (IS_CHERRYVIEW(dev_priv)) {
1562                 divisor = chv_dpll;
1563                 count = ARRAY_SIZE(chv_dpll);
1564         } else if (IS_VALLEYVIEW(dev_priv)) {
1565                 divisor = vlv_dpll;
1566                 count = ARRAY_SIZE(vlv_dpll);
1567         }
1568
1569         if (divisor && count) {
1570                 for (i = 0; i < count; i++) {
1571                         if (pipe_config->port_clock == divisor[i].clock) {
1572                                 pipe_config->dpll = divisor[i].dpll;
1573                                 pipe_config->clock_set = true;
1574                                 break;
1575                         }
1576                 }
1577         }
1578 }
1579
1580 static void snprintf_int_array(char *str, size_t len,
1581                                const int *array, int nelem)
1582 {
1583         int i;
1584
1585         str[0] = '\0';
1586
1587         for (i = 0; i < nelem; i++) {
1588                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1589                 if (r >= len)
1590                         return;
1591                 str += r;
1592                 len -= r;
1593         }
1594 }
1595
1596 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1597 {
1598         char str[128]; /* FIXME: too big for stack? */
1599
1600         if ((drm_debug & DRM_UT_KMS) == 0)
1601                 return;
1602
1603         snprintf_int_array(str, sizeof(str),
1604                            intel_dp->source_rates, intel_dp->num_source_rates);
1605         DRM_DEBUG_KMS("source rates: %s\n", str);
1606
1607         snprintf_int_array(str, sizeof(str),
1608                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1609         DRM_DEBUG_KMS("sink rates: %s\n", str);
1610
1611         snprintf_int_array(str, sizeof(str),
1612                            intel_dp->common_rates, intel_dp->num_common_rates);
1613         DRM_DEBUG_KMS("common rates: %s\n", str);
1614 }
1615
1616 int
1617 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1618 {
1619         int len;
1620
1621         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1622         if (WARN_ON(len <= 0))
1623                 return 162000;
1624
1625         return intel_dp->common_rates[len - 1];
1626 }
1627
1628 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1629 {
1630         int i = intel_dp_rate_index(intel_dp->sink_rates,
1631                                     intel_dp->num_sink_rates, rate);
1632
1633         if (WARN_ON(i < 0))
1634                 i = 0;
1635
1636         return i;
1637 }
1638
1639 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1640                            uint8_t *link_bw, uint8_t *rate_select)
1641 {
1642         /* eDP 1.4 rate select method. */
1643         if (intel_dp->use_rate_select) {
1644                 *link_bw = 0;
1645                 *rate_select =
1646                         intel_dp_rate_select(intel_dp, port_clock);
1647         } else {
1648                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1649                 *rate_select = 0;
1650         }
1651 }
1652
1653 struct link_config_limits {
1654         int min_clock, max_clock;
1655         int min_lane_count, max_lane_count;
1656         int min_bpp, max_bpp;
1657 };
1658
1659 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1660                                 struct intel_crtc_state *pipe_config)
1661 {
1662         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1663         struct intel_connector *intel_connector = intel_dp->attached_connector;
1664         int bpp, bpc;
1665
1666         bpp = pipe_config->pipe_bpp;
1667         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1668
1669         if (bpc > 0)
1670                 bpp = min(bpp, 3*bpc);
1671
1672         if (intel_dp_is_edp(intel_dp)) {
1673                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1674                 if (intel_connector->base.display_info.bpc == 0 &&
1675                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1676                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1677                                       dev_priv->vbt.edp.bpp);
1678                         bpp = dev_priv->vbt.edp.bpp;
1679                 }
1680         }
1681
1682         return bpp;
1683 }
1684
1685 /* Adjust link config limits based on compliance test requests. */
1686 static void
1687 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1688                                   struct intel_crtc_state *pipe_config,
1689                                   struct link_config_limits *limits)
1690 {
1691         /* For DP Compliance we override the computed bpp for the pipe */
1692         if (intel_dp->compliance.test_data.bpc != 0) {
1693                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1694
1695                 limits->min_bpp = limits->max_bpp = bpp;
1696                 pipe_config->dither_force_disable = bpp == 6 * 3;
1697
1698                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1699         }
1700
1701         /* Use values requested by Compliance Test Request */
1702         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1703                 int index;
1704
1705                 /* Validate the compliance test data since max values
1706                  * might have changed due to link train fallback.
1707                  */
1708                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1709                                                intel_dp->compliance.test_lane_count)) {
1710                         index = intel_dp_rate_index(intel_dp->common_rates,
1711                                                     intel_dp->num_common_rates,
1712                                                     intel_dp->compliance.test_link_rate);
1713                         if (index >= 0)
1714                                 limits->min_clock = limits->max_clock = index;
1715                         limits->min_lane_count = limits->max_lane_count =
1716                                 intel_dp->compliance.test_lane_count;
1717                 }
1718         }
1719 }
1720
1721 /* Optimize link config in order: max bpp, min clock, min lanes */
1722 static bool
1723 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1724                                   struct intel_crtc_state *pipe_config,
1725                                   const struct link_config_limits *limits)
1726 {
1727         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1728         int bpp, clock, lane_count;
1729         int mode_rate, link_clock, link_avail;
1730
1731         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1732                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1733                                                    bpp);
1734
1735                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1736                         for (lane_count = limits->min_lane_count;
1737                              lane_count <= limits->max_lane_count;
1738                              lane_count <<= 1) {
1739                                 link_clock = intel_dp->common_rates[clock];
1740                                 link_avail = intel_dp_max_data_rate(link_clock,
1741                                                                     lane_count);
1742
1743                                 if (mode_rate <= link_avail) {
1744                                         pipe_config->lane_count = lane_count;
1745                                         pipe_config->pipe_bpp = bpp;
1746                                         pipe_config->port_clock = link_clock;
1747
1748                                         return true;
1749                                 }
1750                         }
1751                 }
1752         }
1753
1754         return false;
1755 }
1756
1757 static bool
1758 intel_dp_compute_link_config(struct intel_encoder *encoder,
1759                              struct intel_crtc_state *pipe_config)
1760 {
1761         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1762         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1763         struct link_config_limits limits;
1764         int common_len;
1765
1766         common_len = intel_dp_common_len_rate_limit(intel_dp,
1767                                                     intel_dp->max_link_rate);
1768
1769         /* No common link rates between source and sink */
1770         WARN_ON(common_len <= 0);
1771
1772         limits.min_clock = 0;
1773         limits.max_clock = common_len - 1;
1774
1775         limits.min_lane_count = 1;
1776         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1777
1778         limits.min_bpp = 6 * 3;
1779         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1780
1781         if (intel_dp_is_edp(intel_dp)) {
1782                 /*
1783                  * Use the maximum clock and number of lanes the eDP panel
1784                  * advertizes being capable of. The panels are generally
1785                  * designed to support only a single clock and lane
1786                  * configuration, and typically these values correspond to the
1787                  * native resolution of the panel.
1788                  */
1789                 limits.min_lane_count = limits.max_lane_count;
1790                 limits.min_clock = limits.max_clock;
1791         }
1792
1793         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1794
1795         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1796                       "max rate %d max bpp %d pixel clock %iKHz\n",
1797                       limits.max_lane_count,
1798                       intel_dp->common_rates[limits.max_clock],
1799                       limits.max_bpp, adjusted_mode->crtc_clock);
1800
1801         /*
1802          * Optimize for slow and wide. This is the place to add alternative
1803          * optimization policy.
1804          */
1805         if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
1806                 return false;
1807
1808         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1809                       pipe_config->lane_count, pipe_config->port_clock,
1810                       pipe_config->pipe_bpp);
1811
1812         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1813                       intel_dp_link_required(adjusted_mode->crtc_clock,
1814                                              pipe_config->pipe_bpp),
1815                       intel_dp_max_data_rate(pipe_config->port_clock,
1816                                              pipe_config->lane_count));
1817
1818         return true;
1819 }
1820
1821 bool
1822 intel_dp_compute_config(struct intel_encoder *encoder,
1823                         struct intel_crtc_state *pipe_config,
1824                         struct drm_connector_state *conn_state)
1825 {
1826         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1827         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1828         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829         enum port port = encoder->port;
1830         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1831         struct intel_connector *intel_connector = intel_dp->attached_connector;
1832         struct intel_digital_connector_state *intel_conn_state =
1833                 to_intel_digital_connector_state(conn_state);
1834         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1835                                            DP_DPCD_QUIRK_LIMITED_M_N);
1836
1837         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1838                 pipe_config->has_pch_encoder = true;
1839
1840         pipe_config->has_drrs = false;
1841         if (IS_G4X(dev_priv) || port == PORT_A)
1842                 pipe_config->has_audio = false;
1843         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1844                 pipe_config->has_audio = intel_dp->has_audio;
1845         else
1846                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1847
1848         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1849                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1850                                        adjusted_mode);
1851
1852                 if (INTEL_GEN(dev_priv) >= 9) {
1853                         int ret;
1854
1855                         ret = skl_update_scaler_crtc(pipe_config);
1856                         if (ret)
1857                                 return ret;
1858                 }
1859
1860                 if (HAS_GMCH_DISPLAY(dev_priv))
1861                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1862                                                  conn_state->scaling_mode);
1863                 else
1864                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1865                                                 conn_state->scaling_mode);
1866         }
1867
1868         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1869                 return false;
1870
1871         if (HAS_GMCH_DISPLAY(dev_priv) &&
1872             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1873                 return false;
1874
1875         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1876                 return false;
1877
1878         if (!intel_dp_compute_link_config(encoder, pipe_config))
1879                 return false;
1880
1881         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1882                 /*
1883                  * See:
1884                  * CEA-861-E - 5.1 Default Encoding Parameters
1885                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1886                  */
1887                 pipe_config->limited_color_range =
1888                         pipe_config->pipe_bpp != 18 &&
1889                         drm_default_rgb_quant_range(adjusted_mode) ==
1890                         HDMI_QUANTIZATION_RANGE_LIMITED;
1891         } else {
1892                 pipe_config->limited_color_range =
1893                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1894         }
1895
1896         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
1897                                adjusted_mode->crtc_clock,
1898                                pipe_config->port_clock,
1899                                &pipe_config->dp_m_n,
1900                                reduce_m_n);
1901
1902         if (intel_connector->panel.downclock_mode != NULL &&
1903                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1904                         pipe_config->has_drrs = true;
1905                         intel_link_compute_m_n(pipe_config->pipe_bpp,
1906                                                pipe_config->lane_count,
1907                                                intel_connector->panel.downclock_mode->clock,
1908                                                pipe_config->port_clock,
1909                                                &pipe_config->dp_m2_n2,
1910                                                reduce_m_n);
1911         }
1912
1913         if (!HAS_DDI(dev_priv))
1914                 intel_dp_set_clock(encoder, pipe_config);
1915
1916         intel_psr_compute_config(intel_dp, pipe_config);
1917
1918         return true;
1919 }
1920
1921 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1922                               int link_rate, uint8_t lane_count,
1923                               bool link_mst)
1924 {
1925         intel_dp->link_trained = false;
1926         intel_dp->link_rate = link_rate;
1927         intel_dp->lane_count = lane_count;
1928         intel_dp->link_mst = link_mst;
1929 }
1930
1931 static void intel_dp_prepare(struct intel_encoder *encoder,
1932                              const struct intel_crtc_state *pipe_config)
1933 {
1934         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1935         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1936         enum port port = encoder->port;
1937         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1938         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1939
1940         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1941                                  pipe_config->lane_count,
1942                                  intel_crtc_has_type(pipe_config,
1943                                                      INTEL_OUTPUT_DP_MST));
1944
1945         /*
1946          * There are four kinds of DP registers:
1947          *
1948          *      IBX PCH
1949          *      SNB CPU
1950          *      IVB CPU
1951          *      CPT PCH
1952          *
1953          * IBX PCH and CPU are the same for almost everything,
1954          * except that the CPU DP PLL is configured in this
1955          * register
1956          *
1957          * CPT PCH is quite different, having many bits moved
1958          * to the TRANS_DP_CTL register instead. That
1959          * configuration happens (oddly) in ironlake_pch_enable
1960          */
1961
1962         /* Preserve the BIOS-computed detected bit. This is
1963          * supposed to be read-only.
1964          */
1965         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1966
1967         /* Handle DP bits in common between all three register formats */
1968         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1969         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1970
1971         /* Split out the IBX/CPU vs CPT settings */
1972
1973         if (IS_GEN7(dev_priv) && port == PORT_A) {
1974                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1975                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1976                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1977                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1978                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1979
1980                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1981                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1982
1983                 intel_dp->DP |= crtc->pipe << 29;
1984         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1985                 u32 trans_dp;
1986
1987                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1988
1989                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1990                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1991                         trans_dp |= TRANS_DP_ENH_FRAMING;
1992                 else
1993                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1994                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1995         } else {
1996                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1997                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1998
1999                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2000                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2001                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2002                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2003                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2004
2005                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2006                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2007
2008                 if (IS_CHERRYVIEW(dev_priv))
2009                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
2010                 else if (crtc->pipe == PIPE_B)
2011                         intel_dp->DP |= DP_PIPEB_SELECT;
2012         }
2013 }
2014
2015 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2016 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2017
2018 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2019 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2020
2021 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2022 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2023
2024 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2025
2026 static void wait_panel_status(struct intel_dp *intel_dp,
2027                                        u32 mask,
2028                                        u32 value)
2029 {
2030         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2031         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2032
2033         lockdep_assert_held(&dev_priv->pps_mutex);
2034
2035         intel_pps_verify_state(intel_dp);
2036
2037         pp_stat_reg = _pp_stat_reg(intel_dp);
2038         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2039
2040         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2041                         mask, value,
2042                         I915_READ(pp_stat_reg),
2043                         I915_READ(pp_ctrl_reg));
2044
2045         if (intel_wait_for_register(dev_priv,
2046                                     pp_stat_reg, mask, value,
2047                                     5000))
2048                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2049                                 I915_READ(pp_stat_reg),
2050                                 I915_READ(pp_ctrl_reg));
2051
2052         DRM_DEBUG_KMS("Wait complete\n");
2053 }
2054
2055 static void wait_panel_on(struct intel_dp *intel_dp)
2056 {
2057         DRM_DEBUG_KMS("Wait for panel power on\n");
2058         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2059 }
2060
2061 static void wait_panel_off(struct intel_dp *intel_dp)
2062 {
2063         DRM_DEBUG_KMS("Wait for panel power off time\n");
2064         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2065 }
2066
2067 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2068 {
2069         ktime_t panel_power_on_time;
2070         s64 panel_power_off_duration;
2071
2072         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2073
2074         /* take the difference of currrent time and panel power off time
2075          * and then make panel wait for t11_t12 if needed. */
2076         panel_power_on_time = ktime_get_boottime();
2077         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2078
2079         /* When we disable the VDD override bit last we have to do the manual
2080          * wait. */
2081         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2082                 wait_remaining_ms_from_jiffies(jiffies,
2083                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2084
2085         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2086 }
2087
2088 static void wait_backlight_on(struct intel_dp *intel_dp)
2089 {
2090         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2091                                        intel_dp->backlight_on_delay);
2092 }
2093
2094 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2095 {
2096         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2097                                        intel_dp->backlight_off_delay);
2098 }
2099
2100 /* Read the current pp_control value, unlocking the register if it
2101  * is locked
2102  */
2103
2104 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2105 {
2106         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2107         u32 control;
2108
2109         lockdep_assert_held(&dev_priv->pps_mutex);
2110
2111         control = I915_READ(_pp_ctrl_reg(intel_dp));
2112         if (WARN_ON(!HAS_DDI(dev_priv) &&
2113                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2114                 control &= ~PANEL_UNLOCK_MASK;
2115                 control |= PANEL_UNLOCK_REGS;
2116         }
2117         return control;
2118 }
2119
2120 /*
2121  * Must be paired with edp_panel_vdd_off().
2122  * Must hold pps_mutex around the whole on/off sequence.
2123  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2124  */
2125 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2126 {
2127         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2128         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2129         u32 pp;
2130         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2131         bool need_to_disable = !intel_dp->want_panel_vdd;
2132
2133         lockdep_assert_held(&dev_priv->pps_mutex);
2134
2135         if (!intel_dp_is_edp(intel_dp))
2136                 return false;
2137
2138         cancel_delayed_work(&intel_dp->panel_vdd_work);
2139         intel_dp->want_panel_vdd = true;
2140
2141         if (edp_have_panel_vdd(intel_dp))
2142                 return need_to_disable;
2143
2144         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2145
2146         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2147                       port_name(intel_dig_port->base.port));
2148
2149         if (!edp_have_panel_power(intel_dp))
2150                 wait_panel_power_cycle(intel_dp);
2151
2152         pp = ironlake_get_pp_control(intel_dp);
2153         pp |= EDP_FORCE_VDD;
2154
2155         pp_stat_reg = _pp_stat_reg(intel_dp);
2156         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2157
2158         I915_WRITE(pp_ctrl_reg, pp);
2159         POSTING_READ(pp_ctrl_reg);
2160         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2161                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2162         /*
2163          * If the panel wasn't on, delay before accessing aux channel
2164          */
2165         if (!edp_have_panel_power(intel_dp)) {
2166                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2167                               port_name(intel_dig_port->base.port));
2168                 msleep(intel_dp->panel_power_up_delay);
2169         }
2170
2171         return need_to_disable;
2172 }
2173
2174 /*
2175  * Must be paired with intel_edp_panel_vdd_off() or
2176  * intel_edp_panel_off().
2177  * Nested calls to these functions are not allowed since
2178  * we drop the lock. Caller must use some higher level
2179  * locking to prevent nested calls from other threads.
2180  */
2181 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2182 {
2183         bool vdd;
2184
2185         if (!intel_dp_is_edp(intel_dp))
2186                 return;
2187
2188         pps_lock(intel_dp);
2189         vdd = edp_panel_vdd_on(intel_dp);
2190         pps_unlock(intel_dp);
2191
2192         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2193              port_name(dp_to_dig_port(intel_dp)->base.port));
2194 }
2195
2196 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2197 {
2198         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2199         struct intel_digital_port *intel_dig_port =
2200                 dp_to_dig_port(intel_dp);
2201         u32 pp;
2202         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2203
2204         lockdep_assert_held(&dev_priv->pps_mutex);
2205
2206         WARN_ON(intel_dp->want_panel_vdd);
2207
2208         if (!edp_have_panel_vdd(intel_dp))
2209                 return;
2210
2211         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2212                       port_name(intel_dig_port->base.port));
2213
2214         pp = ironlake_get_pp_control(intel_dp);
2215         pp &= ~EDP_FORCE_VDD;
2216
2217         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2218         pp_stat_reg = _pp_stat_reg(intel_dp);
2219
2220         I915_WRITE(pp_ctrl_reg, pp);
2221         POSTING_READ(pp_ctrl_reg);
2222
2223         /* Make sure sequencer is idle before allowing subsequent activity */
2224         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2225         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2226
2227         if ((pp & PANEL_POWER_ON) == 0)
2228                 intel_dp->panel_power_off_time = ktime_get_boottime();
2229
2230         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2231 }
2232
2233 static void edp_panel_vdd_work(struct work_struct *__work)
2234 {
2235         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2236                                                  struct intel_dp, panel_vdd_work);
2237
2238         pps_lock(intel_dp);
2239         if (!intel_dp->want_panel_vdd)
2240                 edp_panel_vdd_off_sync(intel_dp);
2241         pps_unlock(intel_dp);
2242 }
2243
2244 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2245 {
2246         unsigned long delay;
2247
2248         /*
2249          * Queue the timer to fire a long time from now (relative to the power
2250          * down delay) to keep the panel power up across a sequence of
2251          * operations.
2252          */
2253         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2254         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2255 }
2256
2257 /*
2258  * Must be paired with edp_panel_vdd_on().
2259  * Must hold pps_mutex around the whole on/off sequence.
2260  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2261  */
2262 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2263 {
2264         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2265
2266         lockdep_assert_held(&dev_priv->pps_mutex);
2267
2268         if (!intel_dp_is_edp(intel_dp))
2269                 return;
2270
2271         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2272              port_name(dp_to_dig_port(intel_dp)->base.port));
2273
2274         intel_dp->want_panel_vdd = false;
2275
2276         if (sync)
2277                 edp_panel_vdd_off_sync(intel_dp);
2278         else
2279                 edp_panel_vdd_schedule_off(intel_dp);
2280 }
2281
2282 static void edp_panel_on(struct intel_dp *intel_dp)
2283 {
2284         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2285         u32 pp;
2286         i915_reg_t pp_ctrl_reg;
2287
2288         lockdep_assert_held(&dev_priv->pps_mutex);
2289
2290         if (!intel_dp_is_edp(intel_dp))
2291                 return;
2292
2293         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2294                       port_name(dp_to_dig_port(intel_dp)->base.port));
2295
2296         if (WARN(edp_have_panel_power(intel_dp),
2297                  "eDP port %c panel power already on\n",
2298                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2299                 return;
2300
2301         wait_panel_power_cycle(intel_dp);
2302
2303         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2304         pp = ironlake_get_pp_control(intel_dp);
2305         if (IS_GEN5(dev_priv)) {
2306                 /* ILK workaround: disable reset around power sequence */
2307                 pp &= ~PANEL_POWER_RESET;
2308                 I915_WRITE(pp_ctrl_reg, pp);
2309                 POSTING_READ(pp_ctrl_reg);
2310         }
2311
2312         pp |= PANEL_POWER_ON;
2313         if (!IS_GEN5(dev_priv))
2314                 pp |= PANEL_POWER_RESET;
2315
2316         I915_WRITE(pp_ctrl_reg, pp);
2317         POSTING_READ(pp_ctrl_reg);
2318
2319         wait_panel_on(intel_dp);
2320         intel_dp->last_power_on = jiffies;
2321
2322         if (IS_GEN5(dev_priv)) {
2323                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2324                 I915_WRITE(pp_ctrl_reg, pp);
2325                 POSTING_READ(pp_ctrl_reg);
2326         }
2327 }
2328
2329 void intel_edp_panel_on(struct intel_dp *intel_dp)
2330 {
2331         if (!intel_dp_is_edp(intel_dp))
2332                 return;
2333
2334         pps_lock(intel_dp);
2335         edp_panel_on(intel_dp);
2336         pps_unlock(intel_dp);
2337 }
2338
2339
2340 static void edp_panel_off(struct intel_dp *intel_dp)
2341 {
2342         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2343         u32 pp;
2344         i915_reg_t pp_ctrl_reg;
2345
2346         lockdep_assert_held(&dev_priv->pps_mutex);
2347
2348         if (!intel_dp_is_edp(intel_dp))
2349                 return;
2350
2351         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2352                       port_name(dp_to_dig_port(intel_dp)->base.port));
2353
2354         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2355              port_name(dp_to_dig_port(intel_dp)->base.port));
2356
2357         pp = ironlake_get_pp_control(intel_dp);
2358         /* We need to switch off panel power _and_ force vdd, for otherwise some
2359          * panels get very unhappy and cease to work. */
2360         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2361                 EDP_BLC_ENABLE);
2362
2363         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2364
2365         intel_dp->want_panel_vdd = false;
2366
2367         I915_WRITE(pp_ctrl_reg, pp);
2368         POSTING_READ(pp_ctrl_reg);
2369
2370         wait_panel_off(intel_dp);
2371         intel_dp->panel_power_off_time = ktime_get_boottime();
2372
2373         /* We got a reference when we enabled the VDD. */
2374         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2375 }
2376
2377 void intel_edp_panel_off(struct intel_dp *intel_dp)
2378 {
2379         if (!intel_dp_is_edp(intel_dp))
2380                 return;
2381
2382         pps_lock(intel_dp);
2383         edp_panel_off(intel_dp);
2384         pps_unlock(intel_dp);
2385 }
2386
2387 /* Enable backlight in the panel power control. */
2388 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2389 {
2390         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2391         u32 pp;
2392         i915_reg_t pp_ctrl_reg;
2393
2394         /*
2395          * If we enable the backlight right away following a panel power
2396          * on, we may see slight flicker as the panel syncs with the eDP
2397          * link.  So delay a bit to make sure the image is solid before
2398          * allowing it to appear.
2399          */
2400         wait_backlight_on(intel_dp);
2401
2402         pps_lock(intel_dp);
2403
2404         pp = ironlake_get_pp_control(intel_dp);
2405         pp |= EDP_BLC_ENABLE;
2406
2407         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2408
2409         I915_WRITE(pp_ctrl_reg, pp);
2410         POSTING_READ(pp_ctrl_reg);
2411
2412         pps_unlock(intel_dp);
2413 }
2414
2415 /* Enable backlight PWM and backlight PP control. */
2416 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2417                             const struct drm_connector_state *conn_state)
2418 {
2419         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2420
2421         if (!intel_dp_is_edp(intel_dp))
2422                 return;
2423
2424         DRM_DEBUG_KMS("\n");
2425
2426         intel_panel_enable_backlight(crtc_state, conn_state);
2427         _intel_edp_backlight_on(intel_dp);
2428 }
2429
2430 /* Disable backlight in the panel power control. */
2431 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2432 {
2433         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2434         u32 pp;
2435         i915_reg_t pp_ctrl_reg;
2436
2437         if (!intel_dp_is_edp(intel_dp))
2438                 return;
2439
2440         pps_lock(intel_dp);
2441
2442         pp = ironlake_get_pp_control(intel_dp);
2443         pp &= ~EDP_BLC_ENABLE;
2444
2445         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2446
2447         I915_WRITE(pp_ctrl_reg, pp);
2448         POSTING_READ(pp_ctrl_reg);
2449
2450         pps_unlock(intel_dp);
2451
2452         intel_dp->last_backlight_off = jiffies;
2453         edp_wait_backlight_off(intel_dp);
2454 }
2455
2456 /* Disable backlight PP control and backlight PWM. */
2457 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2458 {
2459         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2460
2461         if (!intel_dp_is_edp(intel_dp))
2462                 return;
2463
2464         DRM_DEBUG_KMS("\n");
2465
2466         _intel_edp_backlight_off(intel_dp);
2467         intel_panel_disable_backlight(old_conn_state);
2468 }
2469
2470 /*
2471  * Hook for controlling the panel power control backlight through the bl_power
2472  * sysfs attribute. Take care to handle multiple calls.
2473  */
2474 static void intel_edp_backlight_power(struct intel_connector *connector,
2475                                       bool enable)
2476 {
2477         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2478         bool is_enabled;
2479
2480         pps_lock(intel_dp);
2481         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2482         pps_unlock(intel_dp);
2483
2484         if (is_enabled == enable)
2485                 return;
2486
2487         DRM_DEBUG_KMS("panel power control backlight %s\n",
2488                       enable ? "enable" : "disable");
2489
2490         if (enable)
2491                 _intel_edp_backlight_on(intel_dp);
2492         else
2493                 _intel_edp_backlight_off(intel_dp);
2494 }
2495
2496 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2497 {
2498         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2499         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2500         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2501
2502         I915_STATE_WARN(cur_state != state,
2503                         "DP port %c state assertion failure (expected %s, current %s)\n",
2504                         port_name(dig_port->base.port),
2505                         onoff(state), onoff(cur_state));
2506 }
2507 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2508
2509 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2510 {
2511         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2512
2513         I915_STATE_WARN(cur_state != state,
2514                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2515                         onoff(state), onoff(cur_state));
2516 }
2517 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2518 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2519
2520 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2521                                 const struct intel_crtc_state *pipe_config)
2522 {
2523         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2524         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2525
2526         assert_pipe_disabled(dev_priv, crtc->pipe);
2527         assert_dp_port_disabled(intel_dp);
2528         assert_edp_pll_disabled(dev_priv);
2529
2530         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2531                       pipe_config->port_clock);
2532
2533         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2534
2535         if (pipe_config->port_clock == 162000)
2536                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2537         else
2538                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2539
2540         I915_WRITE(DP_A, intel_dp->DP);
2541         POSTING_READ(DP_A);
2542         udelay(500);
2543
2544         /*
2545          * [DevILK] Work around required when enabling DP PLL
2546          * while a pipe is enabled going to FDI:
2547          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2548          * 2. Program DP PLL enable
2549          */
2550         if (IS_GEN5(dev_priv))
2551                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2552
2553         intel_dp->DP |= DP_PLL_ENABLE;
2554
2555         I915_WRITE(DP_A, intel_dp->DP);
2556         POSTING_READ(DP_A);
2557         udelay(200);
2558 }
2559
2560 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2561                                  const struct intel_crtc_state *old_crtc_state)
2562 {
2563         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2564         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2565
2566         assert_pipe_disabled(dev_priv, crtc->pipe);
2567         assert_dp_port_disabled(intel_dp);
2568         assert_edp_pll_enabled(dev_priv);
2569
2570         DRM_DEBUG_KMS("disabling eDP PLL\n");
2571
2572         intel_dp->DP &= ~DP_PLL_ENABLE;
2573
2574         I915_WRITE(DP_A, intel_dp->DP);
2575         POSTING_READ(DP_A);
2576         udelay(200);
2577 }
2578
2579 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2580 {
2581         /*
2582          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2583          * be capable of signalling downstream hpd with a long pulse.
2584          * Whether or not that means D3 is safe to use is not clear,
2585          * but let's assume so until proven otherwise.
2586          *
2587          * FIXME should really check all downstream ports...
2588          */
2589         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2590                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2591                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2592 }
2593
2594 /* If the sink supports it, try to set the power state appropriately */
2595 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2596 {
2597         int ret, i;
2598
2599         /* Should have a valid DPCD by this point */
2600         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2601                 return;
2602
2603         if (mode != DRM_MODE_DPMS_ON) {
2604                 if (downstream_hpd_needs_d0(intel_dp))
2605                         return;
2606
2607                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2608                                          DP_SET_POWER_D3);
2609         } else {
2610                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2611
2612                 /*
2613                  * When turning on, we need to retry for 1ms to give the sink
2614                  * time to wake up.
2615                  */
2616                 for (i = 0; i < 3; i++) {
2617                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2618                                                  DP_SET_POWER_D0);
2619                         if (ret == 1)
2620                                 break;
2621                         msleep(1);
2622                 }
2623
2624                 if (ret == 1 && lspcon->active)
2625                         lspcon_wait_pcon_mode(lspcon);
2626         }
2627
2628         if (ret != 1)
2629                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2630                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2631 }
2632
2633 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2634                                   enum pipe *pipe)
2635 {
2636         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2637         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2638         enum port port = encoder->port;
2639         u32 tmp;
2640         bool ret;
2641
2642         if (!intel_display_power_get_if_enabled(dev_priv,
2643                                                 encoder->power_domain))
2644                 return false;
2645
2646         ret = false;
2647
2648         tmp = I915_READ(intel_dp->output_reg);
2649
2650         if (!(tmp & DP_PORT_EN))
2651                 goto out;
2652
2653         if (IS_GEN7(dev_priv) && port == PORT_A) {
2654                 *pipe = PORT_TO_PIPE_CPT(tmp);
2655         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2656                 enum pipe p;
2657
2658                 for_each_pipe(dev_priv, p) {
2659                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2660                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2661                                 *pipe = p;
2662                                 ret = true;
2663
2664                                 goto out;
2665                         }
2666                 }
2667
2668                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2669                               i915_mmio_reg_offset(intel_dp->output_reg));
2670         } else if (IS_CHERRYVIEW(dev_priv)) {
2671                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2672         } else {
2673                 *pipe = PORT_TO_PIPE(tmp);
2674         }
2675
2676         ret = true;
2677
2678 out:
2679         intel_display_power_put(dev_priv, encoder->power_domain);
2680
2681         return ret;
2682 }
2683
2684 static void intel_dp_get_config(struct intel_encoder *encoder,
2685                                 struct intel_crtc_state *pipe_config)
2686 {
2687         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2688         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2689         u32 tmp, flags = 0;
2690         enum port port = encoder->port;
2691         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2692
2693         if (encoder->type == INTEL_OUTPUT_EDP)
2694                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2695         else
2696                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2697
2698         tmp = I915_READ(intel_dp->output_reg);
2699
2700         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2701
2702         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2703                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2704
2705                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2706                         flags |= DRM_MODE_FLAG_PHSYNC;
2707                 else
2708                         flags |= DRM_MODE_FLAG_NHSYNC;
2709
2710                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2711                         flags |= DRM_MODE_FLAG_PVSYNC;
2712                 else
2713                         flags |= DRM_MODE_FLAG_NVSYNC;
2714         } else {
2715                 if (tmp & DP_SYNC_HS_HIGH)
2716                         flags |= DRM_MODE_FLAG_PHSYNC;
2717                 else
2718                         flags |= DRM_MODE_FLAG_NHSYNC;
2719
2720                 if (tmp & DP_SYNC_VS_HIGH)
2721                         flags |= DRM_MODE_FLAG_PVSYNC;
2722                 else
2723                         flags |= DRM_MODE_FLAG_NVSYNC;
2724         }
2725
2726         pipe_config->base.adjusted_mode.flags |= flags;
2727
2728         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2729                 pipe_config->limited_color_range = true;
2730
2731         pipe_config->lane_count =
2732                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2733
2734         intel_dp_get_m_n(crtc, pipe_config);
2735
2736         if (port == PORT_A) {
2737                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2738                         pipe_config->port_clock = 162000;
2739                 else
2740                         pipe_config->port_clock = 270000;
2741         }
2742
2743         pipe_config->base.adjusted_mode.crtc_clock =
2744                 intel_dotclock_calculate(pipe_config->port_clock,
2745                                          &pipe_config->dp_m_n);
2746
2747         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2748             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2749                 /*
2750                  * This is a big fat ugly hack.
2751                  *
2752                  * Some machines in UEFI boot mode provide us a VBT that has 18
2753                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2754                  * unknown we fail to light up. Yet the same BIOS boots up with
2755                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2756                  * max, not what it tells us to use.
2757                  *
2758                  * Note: This will still be broken if the eDP panel is not lit
2759                  * up by the BIOS, and thus we can't get the mode at module
2760                  * load.
2761                  */
2762                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2763                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2764                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2765         }
2766 }
2767
2768 static void intel_disable_dp(struct intel_encoder *encoder,
2769                              const struct intel_crtc_state *old_crtc_state,
2770                              const struct drm_connector_state *old_conn_state)
2771 {
2772         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2773
2774         intel_dp->link_trained = false;
2775
2776         if (old_crtc_state->has_audio)
2777                 intel_audio_codec_disable(encoder,
2778                                           old_crtc_state, old_conn_state);
2779
2780         /* Make sure the panel is off before trying to change the mode. But also
2781          * ensure that we have vdd while we switch off the panel. */
2782         intel_edp_panel_vdd_on(intel_dp);
2783         intel_edp_backlight_off(old_conn_state);
2784         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2785         intel_edp_panel_off(intel_dp);
2786 }
2787
2788 static void g4x_disable_dp(struct intel_encoder *encoder,
2789                            const struct intel_crtc_state *old_crtc_state,
2790                            const struct drm_connector_state *old_conn_state)
2791 {
2792         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2793 }
2794
2795 static void vlv_disable_dp(struct intel_encoder *encoder,
2796                            const struct intel_crtc_state *old_crtc_state,
2797                            const struct drm_connector_state *old_conn_state)
2798 {
2799         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2800
2801         intel_psr_disable(intel_dp, old_crtc_state);
2802
2803         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2804 }
2805
2806 static void g4x_post_disable_dp(struct intel_encoder *encoder,
2807                                 const struct intel_crtc_state *old_crtc_state,
2808                                 const struct drm_connector_state *old_conn_state)
2809 {
2810         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2811         enum port port = encoder->port;
2812
2813         /*
2814          * Bspec does not list a specific disable sequence for g4x DP.
2815          * Follow the ilk+ sequence (disable pipe before the port) for
2816          * g4x DP as it does not suffer from underruns like the normal
2817          * g4x modeset sequence (disable pipe after the port).
2818          */
2819         intel_dp_link_down(encoder, old_crtc_state);
2820
2821         /* Only ilk+ has port A */
2822         if (port == PORT_A)
2823                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2824 }
2825
2826 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2827                                 const struct intel_crtc_state *old_crtc_state,
2828                                 const struct drm_connector_state *old_conn_state)
2829 {
2830         intel_dp_link_down(encoder, old_crtc_state);
2831 }
2832
2833 static void chv_post_disable_dp(struct intel_encoder *encoder,
2834                                 const struct intel_crtc_state *old_crtc_state,
2835                                 const struct drm_connector_state *old_conn_state)
2836 {
2837         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2838
2839         intel_dp_link_down(encoder, old_crtc_state);
2840
2841         mutex_lock(&dev_priv->sb_lock);
2842
2843         /* Assert data lane reset */
2844         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2845
2846         mutex_unlock(&dev_priv->sb_lock);
2847 }
2848
2849 static void
2850 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2851                          uint32_t *DP,
2852                          uint8_t dp_train_pat)
2853 {
2854         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2855         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2856         enum port port = intel_dig_port->base.port;
2857
2858         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2859                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2860                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2861
2862         if (HAS_DDI(dev_priv)) {
2863                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2864
2865                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2866                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2867                 else
2868                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2869
2870                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2871                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2872                 case DP_TRAINING_PATTERN_DISABLE:
2873                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2874
2875                         break;
2876                 case DP_TRAINING_PATTERN_1:
2877                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2878                         break;
2879                 case DP_TRAINING_PATTERN_2:
2880                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2881                         break;
2882                 case DP_TRAINING_PATTERN_3:
2883                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2884                         break;
2885                 }
2886                 I915_WRITE(DP_TP_CTL(port), temp);
2887
2888         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2889                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2890                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2891
2892                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2893                 case DP_TRAINING_PATTERN_DISABLE:
2894                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2895                         break;
2896                 case DP_TRAINING_PATTERN_1:
2897                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2898                         break;
2899                 case DP_TRAINING_PATTERN_2:
2900                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2901                         break;
2902                 case DP_TRAINING_PATTERN_3:
2903                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2904                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2905                         break;
2906                 }
2907
2908         } else {
2909                 *DP &= ~DP_LINK_TRAIN_MASK;
2910
2911                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2912                 case DP_TRAINING_PATTERN_DISABLE:
2913                         *DP |= DP_LINK_TRAIN_OFF;
2914                         break;
2915                 case DP_TRAINING_PATTERN_1:
2916                         *DP |= DP_LINK_TRAIN_PAT_1;
2917                         break;
2918                 case DP_TRAINING_PATTERN_2:
2919                         *DP |= DP_LINK_TRAIN_PAT_2;
2920                         break;
2921                 case DP_TRAINING_PATTERN_3:
2922                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2923                         *DP |= DP_LINK_TRAIN_PAT_2;
2924                         break;
2925                 }
2926         }
2927 }
2928
2929 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2930                                  const struct intel_crtc_state *old_crtc_state)
2931 {
2932         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2933
2934         /* enable with pattern 1 (as per spec) */
2935
2936         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2937
2938         /*
2939          * Magic for VLV/CHV. We _must_ first set up the register
2940          * without actually enabling the port, and then do another
2941          * write to enable the port. Otherwise link training will
2942          * fail when the power sequencer is freshly used for this port.
2943          */
2944         intel_dp->DP |= DP_PORT_EN;
2945         if (old_crtc_state->has_audio)
2946                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2947
2948         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2949         POSTING_READ(intel_dp->output_reg);
2950 }
2951
2952 static void intel_enable_dp(struct intel_encoder *encoder,
2953                             const struct intel_crtc_state *pipe_config,
2954                             const struct drm_connector_state *conn_state)
2955 {
2956         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2957         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2958         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2959         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2960         enum pipe pipe = crtc->pipe;
2961
2962         if (WARN_ON(dp_reg & DP_PORT_EN))
2963                 return;
2964
2965         pps_lock(intel_dp);
2966
2967         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2968                 vlv_init_panel_power_sequencer(encoder, pipe_config);
2969
2970         intel_dp_enable_port(intel_dp, pipe_config);
2971
2972         edp_panel_vdd_on(intel_dp);
2973         edp_panel_on(intel_dp);
2974         edp_panel_vdd_off(intel_dp, true);
2975
2976         pps_unlock(intel_dp);
2977
2978         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2979                 unsigned int lane_mask = 0x0;
2980
2981                 if (IS_CHERRYVIEW(dev_priv))
2982                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2983
2984                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2985                                     lane_mask);
2986         }
2987
2988         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2989         intel_dp_start_link_train(intel_dp);
2990         intel_dp_stop_link_train(intel_dp);
2991
2992         if (pipe_config->has_audio) {
2993                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2994                                  pipe_name(pipe));
2995                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2996         }
2997 }
2998
2999 static void g4x_enable_dp(struct intel_encoder *encoder,
3000                           const struct intel_crtc_state *pipe_config,
3001                           const struct drm_connector_state *conn_state)
3002 {
3003         intel_enable_dp(encoder, pipe_config, conn_state);
3004         intel_edp_backlight_on(pipe_config, conn_state);
3005 }
3006
3007 static void vlv_enable_dp(struct intel_encoder *encoder,
3008                           const struct intel_crtc_state *pipe_config,
3009                           const struct drm_connector_state *conn_state)
3010 {
3011         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3012
3013         intel_edp_backlight_on(pipe_config, conn_state);
3014         intel_psr_enable(intel_dp, pipe_config);
3015 }
3016
3017 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3018                               const struct intel_crtc_state *pipe_config,
3019                               const struct drm_connector_state *conn_state)
3020 {
3021         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3022         enum port port = encoder->port;
3023
3024         intel_dp_prepare(encoder, pipe_config);
3025
3026         /* Only ilk+ has port A */
3027         if (port == PORT_A)
3028                 ironlake_edp_pll_on(intel_dp, pipe_config);
3029 }
3030
3031 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3032 {
3033         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3034         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3035         enum pipe pipe = intel_dp->pps_pipe;
3036         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3037
3038         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3039
3040         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3041                 return;
3042
3043         edp_panel_vdd_off_sync(intel_dp);
3044
3045         /*
3046          * VLV seems to get confused when multiple power seqeuencers
3047          * have the same port selected (even if only one has power/vdd
3048          * enabled). The failure manifests as vlv_wait_port_ready() failing
3049          * CHV on the other hand doesn't seem to mind having the same port
3050          * selected in multiple power seqeuencers, but let's clear the
3051          * port select always when logically disconnecting a power sequencer
3052          * from a port.
3053          */
3054         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3055                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3056         I915_WRITE(pp_on_reg, 0);
3057         POSTING_READ(pp_on_reg);
3058
3059         intel_dp->pps_pipe = INVALID_PIPE;
3060 }
3061
3062 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3063                                       enum pipe pipe)
3064 {
3065         struct intel_encoder *encoder;
3066
3067         lockdep_assert_held(&dev_priv->pps_mutex);
3068
3069         for_each_intel_encoder(&dev_priv->drm, encoder) {
3070                 struct intel_dp *intel_dp;
3071                 enum port port;
3072
3073                 if (encoder->type != INTEL_OUTPUT_DP &&
3074                     encoder->type != INTEL_OUTPUT_EDP)
3075                         continue;
3076
3077                 intel_dp = enc_to_intel_dp(&encoder->base);
3078                 port = dp_to_dig_port(intel_dp)->base.port;
3079
3080                 WARN(intel_dp->active_pipe == pipe,
3081                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3082                      pipe_name(pipe), port_name(port));
3083
3084                 if (intel_dp->pps_pipe != pipe)
3085                         continue;
3086
3087                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3088                               pipe_name(pipe), port_name(port));
3089
3090                 /* make sure vdd is off before we steal it */
3091                 vlv_detach_power_sequencer(intel_dp);
3092         }
3093 }
3094
3095 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3096                                            const struct intel_crtc_state *crtc_state)
3097 {
3098         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3099         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3100         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3101
3102         lockdep_assert_held(&dev_priv->pps_mutex);
3103
3104         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3105
3106         if (intel_dp->pps_pipe != INVALID_PIPE &&
3107             intel_dp->pps_pipe != crtc->pipe) {
3108                 /*
3109                  * If another power sequencer was being used on this
3110                  * port previously make sure to turn off vdd there while
3111                  * we still have control of it.
3112                  */
3113                 vlv_detach_power_sequencer(intel_dp);
3114         }
3115
3116         /*
3117          * We may be stealing the power
3118          * sequencer from another port.
3119          */
3120         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3121
3122         intel_dp->active_pipe = crtc->pipe;
3123
3124         if (!intel_dp_is_edp(intel_dp))
3125                 return;
3126
3127         /* now it's all ours */
3128         intel_dp->pps_pipe = crtc->pipe;
3129
3130         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3131                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3132
3133         /* init power sequencer on this pipe and port */
3134         intel_dp_init_panel_power_sequencer(intel_dp);
3135         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3136 }
3137
3138 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3139                               const struct intel_crtc_state *pipe_config,
3140                               const struct drm_connector_state *conn_state)
3141 {
3142         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3143
3144         intel_enable_dp(encoder, pipe_config, conn_state);
3145 }
3146
3147 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3148                                   const struct intel_crtc_state *pipe_config,
3149                                   const struct drm_connector_state *conn_state)
3150 {
3151         intel_dp_prepare(encoder, pipe_config);
3152
3153         vlv_phy_pre_pll_enable(encoder, pipe_config);
3154 }
3155
3156 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3157                               const struct intel_crtc_state *pipe_config,
3158                               const struct drm_connector_state *conn_state)
3159 {
3160         chv_phy_pre_encoder_enable(encoder, pipe_config);
3161
3162         intel_enable_dp(encoder, pipe_config, conn_state);
3163
3164         /* Second common lane will stay alive on its own now */
3165         chv_phy_release_cl2_override(encoder);
3166 }
3167
3168 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3169                                   const struct intel_crtc_state *pipe_config,
3170                                   const struct drm_connector_state *conn_state)
3171 {
3172         intel_dp_prepare(encoder, pipe_config);
3173
3174         chv_phy_pre_pll_enable(encoder, pipe_config);
3175 }
3176
3177 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3178                                     const struct intel_crtc_state *old_crtc_state,
3179                                     const struct drm_connector_state *old_conn_state)
3180 {
3181         chv_phy_post_pll_disable(encoder, old_crtc_state);
3182 }
3183
3184 /*
3185  * Fetch AUX CH registers 0x202 - 0x207 which contain
3186  * link status information
3187  */
3188 bool
3189 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3190 {
3191         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3192                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3193 }
3194
3195 /* These are source-specific values. */
3196 uint8_t
3197 intel_dp_voltage_max(struct intel_dp *intel_dp)
3198 {
3199         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3200         enum port port = dp_to_dig_port(intel_dp)->base.port;
3201
3202         if (INTEL_GEN(dev_priv) >= 9) {
3203                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3204                 return intel_ddi_dp_voltage_max(encoder);
3205         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3206                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3207         else if (IS_GEN7(dev_priv) && port == PORT_A)
3208                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3209         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3210                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3211         else
3212                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3213 }
3214
3215 uint8_t
3216 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3217 {
3218         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3219         enum port port = dp_to_dig_port(intel_dp)->base.port;
3220
3221         if (INTEL_GEN(dev_priv) >= 9) {
3222                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3223                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3224                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3225                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3226                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3227                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3228                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3229                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3230                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3231                 default:
3232                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3233                 }
3234         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3235                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3236                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3237                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3238                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3239                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3240                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3241                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3242                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3243                 default:
3244                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3245                 }
3246         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3247                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3248                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3249                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3250                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3251                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3252                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3253                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3254                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3255                 default:
3256                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3257                 }
3258         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3259                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3260                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3261                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3262                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3263                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3264                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3265                 default:
3266                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3267                 }
3268         } else {
3269                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3270                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3271                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3272                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3273                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3274                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3275                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3276                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3277                 default:
3278                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3279                 }
3280         }
3281 }
3282
3283 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3284 {
3285         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3286         unsigned long demph_reg_value, preemph_reg_value,
3287                 uniqtranscale_reg_value;
3288         uint8_t train_set = intel_dp->train_set[0];
3289
3290         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3291         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3292                 preemph_reg_value = 0x0004000;
3293                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3294                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3295                         demph_reg_value = 0x2B405555;
3296                         uniqtranscale_reg_value = 0x552AB83A;
3297                         break;
3298                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3299                         demph_reg_value = 0x2B404040;
3300                         uniqtranscale_reg_value = 0x5548B83A;
3301                         break;
3302                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3303                         demph_reg_value = 0x2B245555;
3304                         uniqtranscale_reg_value = 0x5560B83A;
3305                         break;
3306                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3307                         demph_reg_value = 0x2B405555;
3308                         uniqtranscale_reg_value = 0x5598DA3A;
3309                         break;
3310                 default:
3311                         return 0;
3312                 }
3313                 break;
3314         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3315                 preemph_reg_value = 0x0002000;
3316                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3317                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3318                         demph_reg_value = 0x2B404040;
3319                         uniqtranscale_reg_value = 0x5552B83A;
3320                         break;
3321                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3322                         demph_reg_value = 0x2B404848;
3323                         uniqtranscale_reg_value = 0x5580B83A;
3324                         break;
3325                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3326                         demph_reg_value = 0x2B404040;
3327                         uniqtranscale_reg_value = 0x55ADDA3A;
3328                         break;
3329                 default:
3330                         return 0;
3331                 }
3332                 break;
3333         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3334                 preemph_reg_value = 0x0000000;
3335                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3336                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3337                         demph_reg_value = 0x2B305555;
3338                         uniqtranscale_reg_value = 0x5570B83A;
3339                         break;
3340                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3341                         demph_reg_value = 0x2B2B4040;
3342                         uniqtranscale_reg_value = 0x55ADDA3A;
3343                         break;
3344                 default:
3345                         return 0;
3346                 }
3347                 break;
3348         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3349                 preemph_reg_value = 0x0006000;
3350                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3351                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3352                         demph_reg_value = 0x1B405555;
3353                         uniqtranscale_reg_value = 0x55ADDA3A;
3354                         break;
3355                 default:
3356                         return 0;
3357                 }
3358                 break;
3359         default:
3360                 return 0;
3361         }
3362
3363         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3364                                  uniqtranscale_reg_value, 0);
3365
3366         return 0;
3367 }
3368
3369 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3370 {
3371         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3372         u32 deemph_reg_value, margin_reg_value;
3373         bool uniq_trans_scale = false;
3374         uint8_t train_set = intel_dp->train_set[0];
3375
3376         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3377         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3378                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3379                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3380                         deemph_reg_value = 128;
3381                         margin_reg_value = 52;
3382                         break;
3383                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3384                         deemph_reg_value = 128;
3385                         margin_reg_value = 77;
3386                         break;
3387                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3388                         deemph_reg_value = 128;
3389                         margin_reg_value = 102;
3390                         break;
3391                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3392                         deemph_reg_value = 128;
3393                         margin_reg_value = 154;
3394                         uniq_trans_scale = true;
3395                         break;
3396                 default:
3397                         return 0;
3398                 }
3399                 break;
3400         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3401                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3402                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3403                         deemph_reg_value = 85;
3404                         margin_reg_value = 78;
3405                         break;
3406                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3407                         deemph_reg_value = 85;
3408                         margin_reg_value = 116;
3409                         break;
3410                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3411                         deemph_reg_value = 85;
3412                         margin_reg_value = 154;
3413                         break;
3414                 default:
3415                         return 0;
3416                 }
3417                 break;
3418         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3419                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3420                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3421                         deemph_reg_value = 64;
3422                         margin_reg_value = 104;
3423                         break;
3424                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3425                         deemph_reg_value = 64;
3426                         margin_reg_value = 154;
3427                         break;
3428                 default:
3429                         return 0;
3430                 }
3431                 break;
3432         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3433                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3434                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3435                         deemph_reg_value = 43;
3436                         margin_reg_value = 154;
3437                         break;
3438                 default:
3439                         return 0;
3440                 }
3441                 break;
3442         default:
3443                 return 0;
3444         }
3445
3446         chv_set_phy_signal_level(encoder, deemph_reg_value,
3447                                  margin_reg_value, uniq_trans_scale);
3448
3449         return 0;
3450 }
3451
3452 static uint32_t
3453 gen4_signal_levels(uint8_t train_set)
3454 {
3455         uint32_t        signal_levels = 0;
3456
3457         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3458         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3459         default:
3460                 signal_levels |= DP_VOLTAGE_0_4;
3461                 break;
3462         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3463                 signal_levels |= DP_VOLTAGE_0_6;
3464                 break;
3465         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3466                 signal_levels |= DP_VOLTAGE_0_8;
3467                 break;
3468         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3469                 signal_levels |= DP_VOLTAGE_1_2;
3470                 break;
3471         }
3472         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3473         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3474         default:
3475                 signal_levels |= DP_PRE_EMPHASIS_0;
3476                 break;
3477         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3478                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3479                 break;
3480         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3481                 signal_levels |= DP_PRE_EMPHASIS_6;
3482                 break;
3483         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3484                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3485                 break;
3486         }
3487         return signal_levels;
3488 }
3489
3490 /* Gen6's DP voltage swing and pre-emphasis control */
3491 static uint32_t
3492 gen6_edp_signal_levels(uint8_t train_set)
3493 {
3494         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3495                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3496         switch (signal_levels) {
3497         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3498         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3499                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3500         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3501                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3502         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3503         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3504                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3505         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3506         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3507                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3508         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3509         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3510                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3511         default:
3512                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3513                               "0x%x\n", signal_levels);
3514                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3515         }
3516 }
3517
3518 /* Gen7's DP voltage swing and pre-emphasis control */
3519 static uint32_t
3520 gen7_edp_signal_levels(uint8_t train_set)
3521 {
3522         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3523                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3524         switch (signal_levels) {
3525         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3526                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3527         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3528                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3529         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3530                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3531
3532         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3533                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3534         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3535                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3536
3537         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3538                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3539         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3540                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3541
3542         default:
3543                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3544                               "0x%x\n", signal_levels);
3545                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3546         }
3547 }
3548
3549 void
3550 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3551 {
3552         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3553         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554         enum port port = intel_dig_port->base.port;
3555         uint32_t signal_levels, mask = 0;
3556         uint8_t train_set = intel_dp->train_set[0];
3557
3558         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3559                 signal_levels = bxt_signal_levels(intel_dp);
3560         } else if (HAS_DDI(dev_priv)) {
3561                 signal_levels = ddi_signal_levels(intel_dp);
3562                 mask = DDI_BUF_EMP_MASK;
3563         } else if (IS_CHERRYVIEW(dev_priv)) {
3564                 signal_levels = chv_signal_levels(intel_dp);
3565         } else if (IS_VALLEYVIEW(dev_priv)) {
3566                 signal_levels = vlv_signal_levels(intel_dp);
3567         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3568                 signal_levels = gen7_edp_signal_levels(train_set);
3569                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3570         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3571                 signal_levels = gen6_edp_signal_levels(train_set);
3572                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3573         } else {
3574                 signal_levels = gen4_signal_levels(train_set);
3575                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3576         }
3577
3578         if (mask)
3579                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3580
3581         DRM_DEBUG_KMS("Using vswing level %d\n",
3582                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3583         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3584                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3585                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3586
3587         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3588
3589         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3590         POSTING_READ(intel_dp->output_reg);
3591 }
3592
3593 void
3594 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3595                                        uint8_t dp_train_pat)
3596 {
3597         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3598         struct drm_i915_private *dev_priv =
3599                 to_i915(intel_dig_port->base.base.dev);
3600
3601         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3602
3603         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3604         POSTING_READ(intel_dp->output_reg);
3605 }
3606
3607 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3608 {
3609         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3610         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3611         enum port port = intel_dig_port->base.port;
3612         uint32_t val;
3613
3614         if (!HAS_DDI(dev_priv))
3615                 return;
3616
3617         val = I915_READ(DP_TP_CTL(port));
3618         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3619         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3620         I915_WRITE(DP_TP_CTL(port), val);
3621
3622         /*
3623          * On PORT_A we can have only eDP in SST mode. There the only reason
3624          * we need to set idle transmission mode is to work around a HW issue
3625          * where we enable the pipe while not in idle link-training mode.
3626          * In this case there is requirement to wait for a minimum number of
3627          * idle patterns to be sent.
3628          */
3629         if (port == PORT_A)
3630                 return;
3631
3632         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3633                                     DP_TP_STATUS_IDLE_DONE,
3634                                     DP_TP_STATUS_IDLE_DONE,
3635                                     1))
3636                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3637 }
3638
3639 static void
3640 intel_dp_link_down(struct intel_encoder *encoder,
3641                    const struct intel_crtc_state *old_crtc_state)
3642 {
3643         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3644         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3645         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3646         enum port port = encoder->port;
3647         uint32_t DP = intel_dp->DP;
3648
3649         if (WARN_ON(HAS_DDI(dev_priv)))
3650                 return;
3651
3652         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3653                 return;
3654
3655         DRM_DEBUG_KMS("\n");
3656
3657         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3658             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3659                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3660                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3661         } else {
3662                 DP &= ~DP_LINK_TRAIN_MASK;
3663                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3664         }
3665         I915_WRITE(intel_dp->output_reg, DP);
3666         POSTING_READ(intel_dp->output_reg);
3667
3668         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3669         I915_WRITE(intel_dp->output_reg, DP);
3670         POSTING_READ(intel_dp->output_reg);
3671
3672         /*
3673          * HW workaround for IBX, we need to move the port
3674          * to transcoder A after disabling it to allow the
3675          * matching HDMI port to be enabled on transcoder A.
3676          */
3677         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3678                 /*
3679                  * We get CPU/PCH FIFO underruns on the other pipe when
3680                  * doing the workaround. Sweep them under the rug.
3681                  */
3682                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3683                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3684
3685                 /* always enable with pattern 1 (as per spec) */
3686                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3687                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3688                 I915_WRITE(intel_dp->output_reg, DP);
3689                 POSTING_READ(intel_dp->output_reg);
3690
3691                 DP &= ~DP_PORT_EN;
3692                 I915_WRITE(intel_dp->output_reg, DP);
3693                 POSTING_READ(intel_dp->output_reg);
3694
3695                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3696                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3697                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3698         }
3699
3700         msleep(intel_dp->panel_power_down_delay);
3701
3702         intel_dp->DP = DP;
3703
3704         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3705                 pps_lock(intel_dp);
3706                 intel_dp->active_pipe = INVALID_PIPE;
3707                 pps_unlock(intel_dp);
3708         }
3709 }
3710
3711 bool
3712 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3713 {
3714         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3715                              sizeof(intel_dp->dpcd)) < 0)
3716                 return false; /* aux transfer failed */
3717
3718         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3719
3720         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3721 }
3722
3723 static bool
3724 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3725 {
3726         struct drm_i915_private *dev_priv =
3727                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3728
3729         /* this function is meant to be called only once */
3730         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3731
3732         if (!intel_dp_read_dpcd(intel_dp))
3733                 return false;
3734
3735         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3736                          drm_dp_is_branch(intel_dp->dpcd));
3737
3738         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3739                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3740                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3741
3742         intel_psr_init_dpcd(intel_dp);
3743
3744         /*
3745          * Read the eDP display control registers.
3746          *
3747          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3748          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3749          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3750          * method). The display control registers should read zero if they're
3751          * not supported anyway.
3752          */
3753         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3754                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3755                              sizeof(intel_dp->edp_dpcd))
3756                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3757                               intel_dp->edp_dpcd);
3758
3759         /* Read the eDP 1.4+ supported link rates. */
3760         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3761                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3762                 int i;
3763
3764                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3765                                 sink_rates, sizeof(sink_rates));
3766
3767                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3768                         int val = le16_to_cpu(sink_rates[i]);
3769
3770                         if (val == 0)
3771                                 break;
3772
3773                         /* Value read multiplied by 200kHz gives the per-lane
3774                          * link rate in kHz. The source rates are, however,
3775                          * stored in terms of LS_Clk kHz. The full conversion
3776                          * back to symbols is
3777                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3778                          */
3779                         intel_dp->sink_rates[i] = (val * 200) / 10;
3780                 }
3781                 intel_dp->num_sink_rates = i;
3782         }
3783
3784         /*
3785          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3786          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3787          */
3788         if (intel_dp->num_sink_rates)
3789                 intel_dp->use_rate_select = true;
3790         else
3791                 intel_dp_set_sink_rates(intel_dp);
3792
3793         intel_dp_set_common_rates(intel_dp);
3794
3795         return true;
3796 }
3797
3798
3799 static bool
3800 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3801 {
3802         u8 sink_count;
3803
3804         if (!intel_dp_read_dpcd(intel_dp))
3805                 return false;
3806
3807         /* Don't clobber cached eDP rates. */
3808         if (!intel_dp_is_edp(intel_dp)) {
3809                 intel_dp_set_sink_rates(intel_dp);
3810                 intel_dp_set_common_rates(intel_dp);
3811         }
3812
3813         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3814                 return false;
3815
3816         /*
3817          * Sink count can change between short pulse hpd hence
3818          * a member variable in intel_dp will track any changes
3819          * between short pulse interrupts.
3820          */
3821         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3822
3823         /*
3824          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3825          * a dongle is present but no display. Unless we require to know
3826          * if a dongle is present or not, we don't need to update
3827          * downstream port information. So, an early return here saves
3828          * time from performing other operations which are not required.
3829          */
3830         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3831                 return false;
3832
3833         if (!drm_dp_is_branch(intel_dp->dpcd))
3834                 return true; /* native DP sink */
3835
3836         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3837                 return true; /* no per-port downstream info */
3838
3839         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3840                              intel_dp->downstream_ports,
3841                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3842                 return false; /* downstream port status fetch failed */
3843
3844         return true;
3845 }
3846
3847 static bool
3848 intel_dp_can_mst(struct intel_dp *intel_dp)
3849 {
3850         u8 mstm_cap;
3851
3852         if (!i915_modparams.enable_dp_mst)
3853                 return false;
3854
3855         if (!intel_dp->can_mst)
3856                 return false;
3857
3858         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3859                 return false;
3860
3861         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3862                 return false;
3863
3864         return mstm_cap & DP_MST_CAP;
3865 }
3866
3867 static void
3868 intel_dp_configure_mst(struct intel_dp *intel_dp)
3869 {
3870         if (!i915_modparams.enable_dp_mst)
3871                 return;
3872
3873         if (!intel_dp->can_mst)
3874                 return;
3875
3876         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3877
3878         if (intel_dp->is_mst)
3879                 DRM_DEBUG_KMS("Sink is MST capable\n");
3880         else
3881                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3882
3883         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3884                                         intel_dp->is_mst);
3885 }
3886
3887 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp,
3888                                   struct intel_crtc_state *crtc_state, bool disable_wa)
3889 {
3890         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3891         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3893         u8 buf;
3894         int ret = 0;
3895         int count = 0;
3896         int attempts = 10;
3897
3898         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3899                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3900                 ret = -EIO;
3901                 goto out;
3902         }
3903
3904         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3905                                buf & ~DP_TEST_SINK_START) < 0) {
3906                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3907                 ret = -EIO;
3908                 goto out;
3909         }
3910
3911         do {
3912                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3913
3914                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3915                                       DP_TEST_SINK_MISC, &buf) < 0) {
3916                         ret = -EIO;
3917                         goto out;
3918                 }
3919                 count = buf & DP_TEST_COUNT_MASK;
3920         } while (--attempts && count);
3921
3922         if (attempts == 0) {
3923                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3924                 ret = -ETIMEDOUT;
3925         }
3926
3927  out:
3928         if (disable_wa)
3929                 hsw_enable_ips(crtc_state);
3930         return ret;
3931 }
3932
3933 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp,
3934                                    struct intel_crtc_state *crtc_state)
3935 {
3936         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3937         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3939         u8 buf;
3940         int ret;
3941
3942         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3943                 return -EIO;
3944
3945         if (!(buf & DP_TEST_CRC_SUPPORTED))
3946                 return -ENOTTY;
3947
3948         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3949                 return -EIO;
3950
3951         if (buf & DP_TEST_SINK_START) {
3952                 ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false);
3953                 if (ret)
3954                         return ret;
3955         }
3956
3957         hsw_disable_ips(crtc_state);
3958
3959         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3960                                buf | DP_TEST_SINK_START) < 0) {
3961                 hsw_enable_ips(crtc_state);
3962                 return -EIO;
3963         }
3964
3965         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3966         return 0;
3967 }
3968
3969 int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc)
3970 {
3971         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3972         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3974         u8 buf;
3975         int count, ret;
3976         int attempts = 6;
3977
3978         ret = intel_dp_sink_crc_start(intel_dp, crtc_state);
3979         if (ret)
3980                 return ret;
3981
3982         do {
3983                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3984
3985                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3986                                       DP_TEST_SINK_MISC, &buf) < 0) {
3987                         ret = -EIO;
3988                         goto stop;
3989                 }
3990                 count = buf & DP_TEST_COUNT_MASK;
3991
3992         } while (--attempts && count == 0);
3993
3994         if (attempts == 0) {
3995                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3996                 ret = -ETIMEDOUT;
3997                 goto stop;
3998         }
3999
4000         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4001                 ret = -EIO;
4002                 goto stop;
4003         }
4004
4005 stop:
4006         intel_dp_sink_crc_stop(intel_dp, crtc_state, true);
4007         return ret;
4008 }
4009
4010 static bool
4011 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4012 {
4013         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4014                                  sink_irq_vector) == 1;
4015 }
4016
4017 static bool
4018 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4019 {
4020         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4021                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4022                 DP_DPRX_ESI_LEN;
4023 }
4024
4025 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4026 {
4027         int status = 0;
4028         int test_link_rate;
4029         uint8_t test_lane_count, test_link_bw;
4030         /* (DP CTS 1.2)
4031          * 4.3.1.11
4032          */
4033         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4034         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4035                                    &test_lane_count);
4036
4037         if (status <= 0) {
4038                 DRM_DEBUG_KMS("Lane count read failed\n");
4039                 return DP_TEST_NAK;
4040         }
4041         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4042
4043         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4044                                    &test_link_bw);
4045         if (status <= 0) {
4046                 DRM_DEBUG_KMS("Link Rate read failed\n");
4047                 return DP_TEST_NAK;
4048         }
4049         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4050
4051         /* Validate the requested link rate and lane count */
4052         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4053                                         test_lane_count))
4054                 return DP_TEST_NAK;
4055
4056         intel_dp->compliance.test_lane_count = test_lane_count;
4057         intel_dp->compliance.test_link_rate = test_link_rate;
4058
4059         return DP_TEST_ACK;
4060 }
4061
4062 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4063 {
4064         uint8_t test_pattern;
4065         uint8_t test_misc;
4066         __be16 h_width, v_height;
4067         int status = 0;
4068
4069         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4070         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4071                                    &test_pattern);
4072         if (status <= 0) {
4073                 DRM_DEBUG_KMS("Test pattern read failed\n");
4074                 return DP_TEST_NAK;
4075         }
4076         if (test_pattern != DP_COLOR_RAMP)
4077                 return DP_TEST_NAK;
4078
4079         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4080                                   &h_width, 2);
4081         if (status <= 0) {
4082                 DRM_DEBUG_KMS("H Width read failed\n");
4083                 return DP_TEST_NAK;
4084         }
4085
4086         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4087                                   &v_height, 2);
4088         if (status <= 0) {
4089                 DRM_DEBUG_KMS("V Height read failed\n");
4090                 return DP_TEST_NAK;
4091         }
4092
4093         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4094                                    &test_misc);
4095         if (status <= 0) {
4096                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4097                 return DP_TEST_NAK;
4098         }
4099         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4100                 return DP_TEST_NAK;
4101         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4102                 return DP_TEST_NAK;
4103         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4104         case DP_TEST_BIT_DEPTH_6:
4105                 intel_dp->compliance.test_data.bpc = 6;
4106                 break;
4107         case DP_TEST_BIT_DEPTH_8:
4108                 intel_dp->compliance.test_data.bpc = 8;
4109                 break;
4110         default:
4111                 return DP_TEST_NAK;
4112         }
4113
4114         intel_dp->compliance.test_data.video_pattern = test_pattern;
4115         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4116         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4117         /* Set test active flag here so userspace doesn't interrupt things */
4118         intel_dp->compliance.test_active = 1;
4119
4120         return DP_TEST_ACK;
4121 }
4122
4123 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4124 {
4125         uint8_t test_result = DP_TEST_ACK;
4126         struct intel_connector *intel_connector = intel_dp->attached_connector;
4127         struct drm_connector *connector = &intel_connector->base;
4128
4129         if (intel_connector->detect_edid == NULL ||
4130             connector->edid_corrupt ||
4131             intel_dp->aux.i2c_defer_count > 6) {
4132                 /* Check EDID read for NACKs, DEFERs and corruption
4133                  * (DP CTS 1.2 Core r1.1)
4134                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4135                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4136                  *    4.2.2.6 : EDID corruption detected
4137                  * Use failsafe mode for all cases
4138                  */
4139                 if (intel_dp->aux.i2c_nack_count > 0 ||
4140                         intel_dp->aux.i2c_defer_count > 0)
4141                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4142                                       intel_dp->aux.i2c_nack_count,
4143                                       intel_dp->aux.i2c_defer_count);
4144                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4145         } else {
4146                 struct edid *block = intel_connector->detect_edid;
4147
4148                 /* We have to write the checksum
4149                  * of the last block read
4150                  */
4151                 block += intel_connector->detect_edid->extensions;
4152
4153                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4154                                        block->checksum) <= 0)
4155                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4156
4157                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4158                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4159         }
4160
4161         /* Set test active flag here so userspace doesn't interrupt things */
4162         intel_dp->compliance.test_active = 1;
4163
4164         return test_result;
4165 }
4166
4167 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4168 {
4169         uint8_t test_result = DP_TEST_NAK;
4170         return test_result;
4171 }
4172
4173 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4174 {
4175         uint8_t response = DP_TEST_NAK;
4176         uint8_t request = 0;
4177         int status;
4178
4179         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4180         if (status <= 0) {
4181                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4182                 goto update_status;
4183         }
4184
4185         switch (request) {
4186         case DP_TEST_LINK_TRAINING:
4187                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4188                 response = intel_dp_autotest_link_training(intel_dp);
4189                 break;
4190         case DP_TEST_LINK_VIDEO_PATTERN:
4191                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4192                 response = intel_dp_autotest_video_pattern(intel_dp);
4193                 break;
4194         case DP_TEST_LINK_EDID_READ:
4195                 DRM_DEBUG_KMS("EDID test requested\n");
4196                 response = intel_dp_autotest_edid(intel_dp);
4197                 break;
4198         case DP_TEST_LINK_PHY_TEST_PATTERN:
4199                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4200                 response = intel_dp_autotest_phy_pattern(intel_dp);
4201                 break;
4202         default:
4203                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4204                 break;
4205         }
4206
4207         if (response & DP_TEST_ACK)
4208                 intel_dp->compliance.test_type = request;
4209
4210 update_status:
4211         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4212         if (status <= 0)
4213                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4214 }
4215
4216 static int
4217 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4218 {
4219         bool bret;
4220
4221         if (intel_dp->is_mst) {
4222                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4223                 int ret = 0;
4224                 int retry;
4225                 bool handled;
4226                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4227 go_again:
4228                 if (bret == true) {
4229
4230                         /* check link status - esi[10] = 0x200c */
4231                         if (intel_dp->active_mst_links &&
4232                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4233                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4234                                 intel_dp_start_link_train(intel_dp);
4235                                 intel_dp_stop_link_train(intel_dp);
4236                         }
4237
4238                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4239                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4240
4241                         if (handled) {
4242                                 for (retry = 0; retry < 3; retry++) {
4243                                         int wret;
4244                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4245                                                                  DP_SINK_COUNT_ESI+1,
4246                                                                  &esi[1], 3);
4247                                         if (wret == 3) {
4248                                                 break;
4249                                         }
4250                                 }
4251
4252                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4253                                 if (bret == true) {
4254                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4255                                         goto go_again;
4256                                 }
4257                         } else
4258                                 ret = 0;
4259
4260                         return ret;
4261                 } else {
4262                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4263                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4264                         intel_dp->is_mst = false;
4265                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4266                         /* send a hotplug event */
4267                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4268                 }
4269         }
4270         return -EINVAL;
4271 }
4272
4273 static bool
4274 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4275 {
4276         u8 link_status[DP_LINK_STATUS_SIZE];
4277
4278         if (!intel_dp->link_trained)
4279                 return false;
4280
4281         if (!intel_dp_get_link_status(intel_dp, link_status))
4282                 return false;
4283
4284         /*
4285          * Validate the cached values of intel_dp->link_rate and
4286          * intel_dp->lane_count before attempting to retrain.
4287          */
4288         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4289                                         intel_dp->lane_count))
4290                 return false;
4291
4292         /* Retrain if Channel EQ or CR not ok */
4293         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4294 }
4295
4296 /*
4297  * If display is now connected check links status,
4298  * there has been known issues of link loss triggering
4299  * long pulse.
4300  *
4301  * Some sinks (eg. ASUS PB287Q) seem to perform some
4302  * weird HPD ping pong during modesets. So we can apparently
4303  * end up with HPD going low during a modeset, and then
4304  * going back up soon after. And once that happens we must
4305  * retrain the link to get a picture. That's in case no
4306  * userspace component reacted to intermittent HPD dip.
4307  */
4308 int intel_dp_retrain_link(struct intel_encoder *encoder,
4309                           struct drm_modeset_acquire_ctx *ctx)
4310 {
4311         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4312         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4313         struct intel_connector *connector = intel_dp->attached_connector;
4314         struct drm_connector_state *conn_state;
4315         struct intel_crtc_state *crtc_state;
4316         struct intel_crtc *crtc;
4317         int ret;
4318
4319         /* FIXME handle the MST connectors as well */
4320
4321         if (!connector || connector->base.status != connector_status_connected)
4322                 return 0;
4323
4324         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4325                                ctx);
4326         if (ret)
4327                 return ret;
4328
4329         conn_state = connector->base.state;
4330
4331         crtc = to_intel_crtc(conn_state->crtc);
4332         if (!crtc)
4333                 return 0;
4334
4335         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4336         if (ret)
4337                 return ret;
4338
4339         crtc_state = to_intel_crtc_state(crtc->base.state);
4340
4341         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4342
4343         if (!crtc_state->base.active)
4344                 return 0;
4345
4346         if (conn_state->commit &&
4347             !try_wait_for_completion(&conn_state->commit->hw_done))
4348                 return 0;
4349
4350         if (!intel_dp_needs_link_retrain(intel_dp))
4351                 return 0;
4352
4353         /* Suppress underruns caused by re-training */
4354         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4355         if (crtc->config->has_pch_encoder)
4356                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4357                                                       intel_crtc_pch_transcoder(crtc), false);
4358
4359         intel_dp_start_link_train(intel_dp);
4360         intel_dp_stop_link_train(intel_dp);
4361
4362         /* Keep underrun reporting disabled until things are stable */
4363         intel_wait_for_vblank(dev_priv, crtc->pipe);
4364
4365         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4366         if (crtc->config->has_pch_encoder)
4367                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4368                                                       intel_crtc_pch_transcoder(crtc), true);
4369
4370         return 0;
4371 }
4372
4373 /*
4374  * If display is now connected check links status,
4375  * there has been known issues of link loss triggering
4376  * long pulse.
4377  *
4378  * Some sinks (eg. ASUS PB287Q) seem to perform some
4379  * weird HPD ping pong during modesets. So we can apparently
4380  * end up with HPD going low during a modeset, and then
4381  * going back up soon after. And once that happens we must
4382  * retrain the link to get a picture. That's in case no
4383  * userspace component reacted to intermittent HPD dip.
4384  */
4385 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4386                              struct intel_connector *connector)
4387 {
4388         struct drm_modeset_acquire_ctx ctx;
4389         bool changed;
4390         int ret;
4391
4392         changed = intel_encoder_hotplug(encoder, connector);
4393
4394         drm_modeset_acquire_init(&ctx, 0);
4395
4396         for (;;) {
4397                 ret = intel_dp_retrain_link(encoder, &ctx);
4398
4399                 if (ret == -EDEADLK) {
4400                         drm_modeset_backoff(&ctx);
4401                         continue;
4402                 }
4403
4404                 break;
4405         }
4406
4407         drm_modeset_drop_locks(&ctx);
4408         drm_modeset_acquire_fini(&ctx);
4409         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4410
4411         return changed;
4412 }
4413
4414 /*
4415  * According to DP spec
4416  * 5.1.2:
4417  *  1. Read DPCD
4418  *  2. Configure link according to Receiver Capabilities
4419  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4420  *  4. Check link status on receipt of hot-plug interrupt
4421  *
4422  * intel_dp_short_pulse -  handles short pulse interrupts
4423  * when full detection is not required.
4424  * Returns %true if short pulse is handled and full detection
4425  * is NOT required and %false otherwise.
4426  */
4427 static bool
4428 intel_dp_short_pulse(struct intel_dp *intel_dp)
4429 {
4430         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4431         u8 sink_irq_vector = 0;
4432         u8 old_sink_count = intel_dp->sink_count;
4433         bool ret;
4434
4435         /*
4436          * Clearing compliance test variables to allow capturing
4437          * of values for next automated test request.
4438          */
4439         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4440
4441         /*
4442          * Now read the DPCD to see if it's actually running
4443          * If the current value of sink count doesn't match with
4444          * the value that was stored earlier or dpcd read failed
4445          * we need to do full detection
4446          */
4447         ret = intel_dp_get_dpcd(intel_dp);
4448
4449         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4450                 /* No need to proceed if we are going to do full detect */
4451                 return false;
4452         }
4453
4454         /* Try to read the source of the interrupt */
4455         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4456             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4457             sink_irq_vector != 0) {
4458                 /* Clear interrupt source */
4459                 drm_dp_dpcd_writeb(&intel_dp->aux,
4460                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4461                                    sink_irq_vector);
4462
4463                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4464                         intel_dp_handle_test_request(intel_dp);
4465                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4466                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4467         }
4468
4469         /* defer to the hotplug work for link retraining if needed */
4470         if (intel_dp_needs_link_retrain(intel_dp))
4471                 return false;
4472
4473         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4474                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4475                 /* Send a Hotplug Uevent to userspace to start modeset */
4476                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4477         }
4478
4479         return true;
4480 }
4481
4482 /* XXX this is probably wrong for multiple downstream ports */
4483 static enum drm_connector_status
4484 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4485 {
4486         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4487         uint8_t *dpcd = intel_dp->dpcd;
4488         uint8_t type;
4489
4490         if (lspcon->active)
4491                 lspcon_resume(lspcon);
4492
4493         if (!intel_dp_get_dpcd(intel_dp))
4494                 return connector_status_disconnected;
4495
4496         if (intel_dp_is_edp(intel_dp))
4497                 return connector_status_connected;
4498
4499         /* if there's no downstream port, we're done */
4500         if (!drm_dp_is_branch(dpcd))
4501                 return connector_status_connected;
4502
4503         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4504         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4505             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4506
4507                 return intel_dp->sink_count ?
4508                 connector_status_connected : connector_status_disconnected;
4509         }
4510
4511         if (intel_dp_can_mst(intel_dp))
4512                 return connector_status_connected;
4513
4514         /* If no HPD, poke DDC gently */
4515         if (drm_probe_ddc(&intel_dp->aux.ddc))
4516                 return connector_status_connected;
4517
4518         /* Well we tried, say unknown for unreliable port types */
4519         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4520                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4521                 if (type == DP_DS_PORT_TYPE_VGA ||
4522                     type == DP_DS_PORT_TYPE_NON_EDID)
4523                         return connector_status_unknown;
4524         } else {
4525                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4526                         DP_DWN_STRM_PORT_TYPE_MASK;
4527                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4528                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4529                         return connector_status_unknown;
4530         }
4531
4532         /* Anything else is out of spec, warn and ignore */
4533         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4534         return connector_status_disconnected;
4535 }
4536
4537 static enum drm_connector_status
4538 edp_detect(struct intel_dp *intel_dp)
4539 {
4540         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4541         enum drm_connector_status status;
4542
4543         status = intel_panel_detect(dev_priv);
4544         if (status == connector_status_unknown)
4545                 status = connector_status_connected;
4546
4547         return status;
4548 }
4549
4550 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4551 {
4552         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4553         u32 bit;
4554
4555         switch (encoder->hpd_pin) {
4556         case HPD_PORT_B:
4557                 bit = SDE_PORTB_HOTPLUG;
4558                 break;
4559         case HPD_PORT_C:
4560                 bit = SDE_PORTC_HOTPLUG;
4561                 break;
4562         case HPD_PORT_D:
4563                 bit = SDE_PORTD_HOTPLUG;
4564                 break;
4565         default:
4566                 MISSING_CASE(encoder->hpd_pin);
4567                 return false;
4568         }
4569
4570         return I915_READ(SDEISR) & bit;
4571 }
4572
4573 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4574 {
4575         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4576         u32 bit;
4577
4578         switch (encoder->hpd_pin) {
4579         case HPD_PORT_B:
4580                 bit = SDE_PORTB_HOTPLUG_CPT;
4581                 break;
4582         case HPD_PORT_C:
4583                 bit = SDE_PORTC_HOTPLUG_CPT;
4584                 break;
4585         case HPD_PORT_D:
4586                 bit = SDE_PORTD_HOTPLUG_CPT;
4587                 break;
4588         default:
4589                 MISSING_CASE(encoder->hpd_pin);
4590                 return false;
4591         }
4592
4593         return I915_READ(SDEISR) & bit;
4594 }
4595
4596 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4597 {
4598         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4599         u32 bit;
4600
4601         switch (encoder->hpd_pin) {
4602         case HPD_PORT_A:
4603                 bit = SDE_PORTA_HOTPLUG_SPT;
4604                 break;
4605         case HPD_PORT_E:
4606                 bit = SDE_PORTE_HOTPLUG_SPT;
4607                 break;
4608         default:
4609                 return cpt_digital_port_connected(encoder);
4610         }
4611
4612         return I915_READ(SDEISR) & bit;
4613 }
4614
4615 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4616 {
4617         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4618         u32 bit;
4619
4620         switch (encoder->hpd_pin) {
4621         case HPD_PORT_B:
4622                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4623                 break;
4624         case HPD_PORT_C:
4625                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4626                 break;
4627         case HPD_PORT_D:
4628                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4629                 break;
4630         default:
4631                 MISSING_CASE(encoder->hpd_pin);
4632                 return false;
4633         }
4634
4635         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4636 }
4637
4638 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4639 {
4640         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4641         u32 bit;
4642
4643         switch (encoder->hpd_pin) {
4644         case HPD_PORT_B:
4645                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4646                 break;
4647         case HPD_PORT_C:
4648                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4649                 break;
4650         case HPD_PORT_D:
4651                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4652                 break;
4653         default:
4654                 MISSING_CASE(encoder->hpd_pin);
4655                 return false;
4656         }
4657
4658         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4659 }
4660
4661 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4662 {
4663         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4664
4665         if (encoder->hpd_pin == HPD_PORT_A)
4666                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4667         else
4668                 return ibx_digital_port_connected(encoder);
4669 }
4670
4671 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4672 {
4673         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4674
4675         if (encoder->hpd_pin == HPD_PORT_A)
4676                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4677         else
4678                 return cpt_digital_port_connected(encoder);
4679 }
4680
4681 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4682 {
4683         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4684
4685         if (encoder->hpd_pin == HPD_PORT_A)
4686                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4687         else
4688                 return cpt_digital_port_connected(encoder);
4689 }
4690
4691 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4692 {
4693         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4694
4695         if (encoder->hpd_pin == HPD_PORT_A)
4696                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4697         else
4698                 return cpt_digital_port_connected(encoder);
4699 }
4700
4701 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4702 {
4703         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4704         u32 bit;
4705
4706         switch (encoder->hpd_pin) {
4707         case HPD_PORT_A:
4708                 bit = BXT_DE_PORT_HP_DDIA;
4709                 break;
4710         case HPD_PORT_B:
4711                 bit = BXT_DE_PORT_HP_DDIB;
4712                 break;
4713         case HPD_PORT_C:
4714                 bit = BXT_DE_PORT_HP_DDIC;
4715                 break;
4716         default:
4717                 MISSING_CASE(encoder->hpd_pin);
4718                 return false;
4719         }
4720
4721         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4722 }
4723
4724 /*
4725  * intel_digital_port_connected - is the specified port connected?
4726  * @encoder: intel_encoder
4727  *
4728  * Return %true if port is connected, %false otherwise.
4729  */
4730 bool intel_digital_port_connected(struct intel_encoder *encoder)
4731 {
4732         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4733
4734         if (HAS_GMCH_DISPLAY(dev_priv)) {
4735                 if (IS_GM45(dev_priv))
4736                         return gm45_digital_port_connected(encoder);
4737                 else
4738                         return g4x_digital_port_connected(encoder);
4739         }
4740
4741         if (IS_GEN5(dev_priv))
4742                 return ilk_digital_port_connected(encoder);
4743         else if (IS_GEN6(dev_priv))
4744                 return snb_digital_port_connected(encoder);
4745         else if (IS_GEN7(dev_priv))
4746                 return ivb_digital_port_connected(encoder);
4747         else if (IS_GEN8(dev_priv))
4748                 return bdw_digital_port_connected(encoder);
4749         else if (IS_GEN9_LP(dev_priv))
4750                 return bxt_digital_port_connected(encoder);
4751         else
4752                 return spt_digital_port_connected(encoder);
4753 }
4754
4755 static struct edid *
4756 intel_dp_get_edid(struct intel_dp *intel_dp)
4757 {
4758         struct intel_connector *intel_connector = intel_dp->attached_connector;
4759
4760         /* use cached edid if we have one */
4761         if (intel_connector->edid) {
4762                 /* invalid edid */
4763                 if (IS_ERR(intel_connector->edid))
4764                         return NULL;
4765
4766                 return drm_edid_duplicate(intel_connector->edid);
4767         } else
4768                 return drm_get_edid(&intel_connector->base,
4769                                     &intel_dp->aux.ddc);
4770 }
4771
4772 static void
4773 intel_dp_set_edid(struct intel_dp *intel_dp)
4774 {
4775         struct intel_connector *intel_connector = intel_dp->attached_connector;
4776         struct edid *edid;
4777
4778         intel_dp_unset_edid(intel_dp);
4779         edid = intel_dp_get_edid(intel_dp);
4780         intel_connector->detect_edid = edid;
4781
4782         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4783 }
4784
4785 static void
4786 intel_dp_unset_edid(struct intel_dp *intel_dp)
4787 {
4788         struct intel_connector *intel_connector = intel_dp->attached_connector;
4789
4790         kfree(intel_connector->detect_edid);
4791         intel_connector->detect_edid = NULL;
4792
4793         intel_dp->has_audio = false;
4794 }
4795
4796 static int
4797 intel_dp_long_pulse(struct intel_connector *connector)
4798 {
4799         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4800         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4801         enum drm_connector_status status;
4802         u8 sink_irq_vector = 0;
4803
4804         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4805
4806         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4807
4808         /* Can't disconnect eDP, but you can close the lid... */
4809         if (intel_dp_is_edp(intel_dp))
4810                 status = edp_detect(intel_dp);
4811         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4812                 status = intel_dp_detect_dpcd(intel_dp);
4813         else
4814                 status = connector_status_disconnected;
4815
4816         if (status == connector_status_disconnected) {
4817                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4818
4819                 if (intel_dp->is_mst) {
4820                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4821                                       intel_dp->is_mst,
4822                                       intel_dp->mst_mgr.mst_state);
4823                         intel_dp->is_mst = false;
4824                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4825                                                         intel_dp->is_mst);
4826                 }
4827
4828                 goto out;
4829         }
4830
4831         if (intel_dp->reset_link_params) {
4832                 /* Initial max link lane count */
4833                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4834
4835                 /* Initial max link rate */
4836                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4837
4838                 intel_dp->reset_link_params = false;
4839         }
4840
4841         intel_dp_print_rates(intel_dp);
4842
4843         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4844                          drm_dp_is_branch(intel_dp->dpcd));
4845
4846         intel_dp_configure_mst(intel_dp);
4847
4848         if (intel_dp->is_mst) {
4849                 /*
4850                  * If we are in MST mode then this connector
4851                  * won't appear connected or have anything
4852                  * with EDID on it
4853                  */
4854                 status = connector_status_disconnected;
4855                 goto out;
4856         }
4857
4858         /*
4859          * Clearing NACK and defer counts to get their exact values
4860          * while reading EDID which are required by Compliance tests
4861          * 4.2.2.4 and 4.2.2.5
4862          */
4863         intel_dp->aux.i2c_nack_count = 0;
4864         intel_dp->aux.i2c_defer_count = 0;
4865
4866         intel_dp_set_edid(intel_dp);
4867         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4868                 status = connector_status_connected;
4869         intel_dp->detect_done = true;
4870
4871         /* Try to read the source of the interrupt */
4872         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4873             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4874             sink_irq_vector != 0) {
4875                 /* Clear interrupt source */
4876                 drm_dp_dpcd_writeb(&intel_dp->aux,
4877                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4878                                    sink_irq_vector);
4879
4880                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4881                         intel_dp_handle_test_request(intel_dp);
4882                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4883                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4884         }
4885
4886 out:
4887         if (status != connector_status_connected && !intel_dp->is_mst)
4888                 intel_dp_unset_edid(intel_dp);
4889
4890         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4891         return status;
4892 }
4893
4894 static int
4895 intel_dp_detect(struct drm_connector *connector,
4896                 struct drm_modeset_acquire_ctx *ctx,
4897                 bool force)
4898 {
4899         struct intel_dp *intel_dp = intel_attached_dp(connector);
4900         int status = connector->status;
4901
4902         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4903                       connector->base.id, connector->name);
4904
4905         /* If full detect is not performed yet, do a full detect */
4906         if (!intel_dp->detect_done) {
4907                 struct drm_crtc *crtc;
4908                 int ret;
4909
4910                 crtc = connector->state->crtc;
4911                 if (crtc) {
4912                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4913                         if (ret)
4914                                 return ret;
4915                 }
4916
4917                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4918         }
4919
4920         intel_dp->detect_done = false;
4921
4922         return status;
4923 }
4924
4925 static void
4926 intel_dp_force(struct drm_connector *connector)
4927 {
4928         struct intel_dp *intel_dp = intel_attached_dp(connector);
4929         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4930         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4931
4932         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4933                       connector->base.id, connector->name);
4934         intel_dp_unset_edid(intel_dp);
4935
4936         if (connector->status != connector_status_connected)
4937                 return;
4938
4939         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4940
4941         intel_dp_set_edid(intel_dp);
4942
4943         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4944 }
4945
4946 static int intel_dp_get_modes(struct drm_connector *connector)
4947 {
4948         struct intel_connector *intel_connector = to_intel_connector(connector);
4949         struct edid *edid;
4950
4951         edid = intel_connector->detect_edid;
4952         if (edid) {
4953                 int ret = intel_connector_update_modes(connector, edid);
4954                 if (ret)
4955                         return ret;
4956         }
4957
4958         /* if eDP has no EDID, fall back to fixed mode */
4959         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4960             intel_connector->panel.fixed_mode) {
4961                 struct drm_display_mode *mode;
4962
4963                 mode = drm_mode_duplicate(connector->dev,
4964                                           intel_connector->panel.fixed_mode);
4965                 if (mode) {
4966                         drm_mode_probed_add(connector, mode);
4967                         return 1;
4968                 }
4969         }
4970
4971         return 0;
4972 }
4973
4974 static int
4975 intel_dp_connector_register(struct drm_connector *connector)
4976 {
4977         struct intel_dp *intel_dp = intel_attached_dp(connector);
4978         int ret;
4979
4980         ret = intel_connector_register(connector);
4981         if (ret)
4982                 return ret;
4983
4984         i915_debugfs_connector_add(connector);
4985
4986         DRM_DEBUG_KMS("registering %s bus for %s\n",
4987                       intel_dp->aux.name, connector->kdev->kobj.name);
4988
4989         intel_dp->aux.dev = connector->kdev;
4990         return drm_dp_aux_register(&intel_dp->aux);
4991 }
4992
4993 static void
4994 intel_dp_connector_unregister(struct drm_connector *connector)
4995 {
4996         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4997         intel_connector_unregister(connector);
4998 }
4999
5000 static void
5001 intel_dp_connector_destroy(struct drm_connector *connector)
5002 {
5003         struct intel_connector *intel_connector = to_intel_connector(connector);
5004
5005         kfree(intel_connector->detect_edid);
5006
5007         if (!IS_ERR_OR_NULL(intel_connector->edid))
5008                 kfree(intel_connector->edid);
5009
5010         /*
5011          * Can't call intel_dp_is_edp() since the encoder may have been
5012          * destroyed already.
5013          */
5014         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5015                 intel_panel_fini(&intel_connector->panel);
5016
5017         drm_connector_cleanup(connector);
5018         kfree(connector);
5019 }
5020
5021 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5022 {
5023         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5024         struct intel_dp *intel_dp = &intel_dig_port->dp;
5025
5026         intel_dp_mst_encoder_cleanup(intel_dig_port);
5027         if (intel_dp_is_edp(intel_dp)) {
5028                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5029                 /*
5030                  * vdd might still be enabled do to the delayed vdd off.
5031                  * Make sure vdd is actually turned off here.
5032                  */
5033                 pps_lock(intel_dp);
5034                 edp_panel_vdd_off_sync(intel_dp);
5035                 pps_unlock(intel_dp);
5036
5037                 if (intel_dp->edp_notifier.notifier_call) {
5038                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5039                         intel_dp->edp_notifier.notifier_call = NULL;
5040                 }
5041         }
5042
5043         intel_dp_aux_fini(intel_dp);
5044
5045         drm_encoder_cleanup(encoder);
5046         kfree(intel_dig_port);
5047 }
5048
5049 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5050 {
5051         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5052
5053         if (!intel_dp_is_edp(intel_dp))
5054                 return;
5055
5056         /*
5057          * vdd might still be enabled do to the delayed vdd off.
5058          * Make sure vdd is actually turned off here.
5059          */
5060         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5061         pps_lock(intel_dp);
5062         edp_panel_vdd_off_sync(intel_dp);
5063         pps_unlock(intel_dp);
5064 }
5065
5066 static
5067 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5068                                 u8 *an)
5069 {
5070         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5071         static const struct drm_dp_aux_msg msg = {
5072                 .request = DP_AUX_NATIVE_WRITE,
5073                 .address = DP_AUX_HDCP_AKSV,
5074                 .size = DRM_HDCP_KSV_LEN,
5075         };
5076         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5077         ssize_t dpcd_ret;
5078         int ret;
5079
5080         /* Output An first, that's easy */
5081         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5082                                      an, DRM_HDCP_AN_LEN);
5083         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5084                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5085                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5086         }
5087
5088         /*
5089          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5090          * order to get it on the wire, we need to create the AUX header as if
5091          * we were writing the data, and then tickle the hardware to output the
5092          * data once the header is sent out.
5093          */
5094         intel_dp_aux_header(txbuf, &msg);
5095
5096         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5097                                 rxbuf, sizeof(rxbuf),
5098                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5099         if (ret < 0) {
5100                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5101                 return ret;
5102         } else if (ret == 0) {
5103                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5104                 return -EIO;
5105         }
5106
5107         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5108         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5109 }
5110
5111 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5112                                    u8 *bksv)
5113 {
5114         ssize_t ret;
5115         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5116                                DRM_HDCP_KSV_LEN);
5117         if (ret != DRM_HDCP_KSV_LEN) {
5118                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5119                 return ret >= 0 ? -EIO : ret;
5120         }
5121         return 0;
5122 }
5123
5124 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5125                                       u8 *bstatus)
5126 {
5127         ssize_t ret;
5128         /*
5129          * For some reason the HDMI and DP HDCP specs call this register
5130          * definition by different names. In the HDMI spec, it's called BSTATUS,
5131          * but in DP it's called BINFO.
5132          */
5133         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5134                                bstatus, DRM_HDCP_BSTATUS_LEN);
5135         if (ret != DRM_HDCP_BSTATUS_LEN) {
5136                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5137                 return ret >= 0 ? -EIO : ret;
5138         }
5139         return 0;
5140 }
5141
5142 static
5143 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5144                              u8 *bcaps)
5145 {
5146         ssize_t ret;
5147
5148         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5149                                bcaps, 1);
5150         if (ret != 1) {
5151                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5152                 return ret >= 0 ? -EIO : ret;
5153         }
5154
5155         return 0;
5156 }
5157
5158 static
5159 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5160                                    bool *repeater_present)
5161 {
5162         ssize_t ret;
5163         u8 bcaps;
5164
5165         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5166         if (ret)
5167                 return ret;
5168
5169         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5170         return 0;
5171 }
5172
5173 static
5174 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5175                                 u8 *ri_prime)
5176 {
5177         ssize_t ret;
5178         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5179                                ri_prime, DRM_HDCP_RI_LEN);
5180         if (ret != DRM_HDCP_RI_LEN) {
5181                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5182                 return ret >= 0 ? -EIO : ret;
5183         }
5184         return 0;
5185 }
5186
5187 static
5188 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5189                                  bool *ksv_ready)
5190 {
5191         ssize_t ret;
5192         u8 bstatus;
5193         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5194                                &bstatus, 1);
5195         if (ret != 1) {
5196                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5197                 return ret >= 0 ? -EIO : ret;
5198         }
5199         *ksv_ready = bstatus & DP_BSTATUS_READY;
5200         return 0;
5201 }
5202
5203 static
5204 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5205                                 int num_downstream, u8 *ksv_fifo)
5206 {
5207         ssize_t ret;
5208         int i;
5209
5210         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5211         for (i = 0; i < num_downstream; i += 3) {
5212                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5213                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5214                                        DP_AUX_HDCP_KSV_FIFO,
5215                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5216                                        len);
5217                 if (ret != len) {
5218                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5219                                   ret);
5220                         return ret >= 0 ? -EIO : ret;
5221                 }
5222         }
5223         return 0;
5224 }
5225
5226 static
5227 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5228                                     int i, u32 *part)
5229 {
5230         ssize_t ret;
5231
5232         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5233                 return -EINVAL;
5234
5235         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5236                                DP_AUX_HDCP_V_PRIME(i), part,
5237                                DRM_HDCP_V_PRIME_PART_LEN);
5238         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5239                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5240                 return ret >= 0 ? -EIO : ret;
5241         }
5242         return 0;
5243 }
5244
5245 static
5246 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5247                                     bool enable)
5248 {
5249         /* Not used for single stream DisplayPort setups */
5250         return 0;
5251 }
5252
5253 static
5254 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5255 {
5256         ssize_t ret;
5257         u8 bstatus;
5258
5259         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5260                                &bstatus, 1);
5261         if (ret != 1) {
5262                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5263                 return false;
5264         }
5265
5266         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5267 }
5268
5269 static
5270 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5271                           bool *hdcp_capable)
5272 {
5273         ssize_t ret;
5274         u8 bcaps;
5275
5276         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5277         if (ret)
5278                 return ret;
5279
5280         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5281         return 0;
5282 }
5283
5284 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5285         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5286         .read_bksv = intel_dp_hdcp_read_bksv,
5287         .read_bstatus = intel_dp_hdcp_read_bstatus,
5288         .repeater_present = intel_dp_hdcp_repeater_present,
5289         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5290         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5291         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5292         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5293         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5294         .check_link = intel_dp_hdcp_check_link,
5295         .hdcp_capable = intel_dp_hdcp_capable,
5296 };
5297
5298 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5299 {
5300         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5301
5302         lockdep_assert_held(&dev_priv->pps_mutex);
5303
5304         if (!edp_have_panel_vdd(intel_dp))
5305                 return;
5306
5307         /*
5308          * The VDD bit needs a power domain reference, so if the bit is
5309          * already enabled when we boot or resume, grab this reference and
5310          * schedule a vdd off, so we don't hold on to the reference
5311          * indefinitely.
5312          */
5313         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5314         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5315
5316         edp_panel_vdd_schedule_off(intel_dp);
5317 }
5318
5319 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5320 {
5321         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5322
5323         if ((intel_dp->DP & DP_PORT_EN) == 0)
5324                 return INVALID_PIPE;
5325
5326         if (IS_CHERRYVIEW(dev_priv))
5327                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5328         else
5329                 return PORT_TO_PIPE(intel_dp->DP);
5330 }
5331
5332 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5333 {
5334         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5335         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5336         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5337
5338         if (!HAS_DDI(dev_priv))
5339                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5340
5341         if (lspcon->active)
5342                 lspcon_resume(lspcon);
5343
5344         intel_dp->reset_link_params = true;
5345
5346         pps_lock(intel_dp);
5347
5348         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5349                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5350
5351         if (intel_dp_is_edp(intel_dp)) {
5352                 /* Reinit the power sequencer, in case BIOS did something with it. */
5353                 intel_dp_pps_init(intel_dp);
5354                 intel_edp_panel_vdd_sanitize(intel_dp);
5355         }
5356
5357         pps_unlock(intel_dp);
5358 }
5359
5360 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5361         .force = intel_dp_force,
5362         .fill_modes = drm_helper_probe_single_connector_modes,
5363         .atomic_get_property = intel_digital_connector_atomic_get_property,
5364         .atomic_set_property = intel_digital_connector_atomic_set_property,
5365         .late_register = intel_dp_connector_register,
5366         .early_unregister = intel_dp_connector_unregister,
5367         .destroy = intel_dp_connector_destroy,
5368         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5369         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5370 };
5371
5372 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5373         .detect_ctx = intel_dp_detect,
5374         .get_modes = intel_dp_get_modes,
5375         .mode_valid = intel_dp_mode_valid,
5376         .atomic_check = intel_digital_connector_atomic_check,
5377 };
5378
5379 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5380         .reset = intel_dp_encoder_reset,
5381         .destroy = intel_dp_encoder_destroy,
5382 };
5383
5384 enum irqreturn
5385 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5386 {
5387         struct intel_dp *intel_dp = &intel_dig_port->dp;
5388         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5389         enum irqreturn ret = IRQ_NONE;
5390
5391         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5392                 /*
5393                  * vdd off can generate a long pulse on eDP which
5394                  * would require vdd on to handle it, and thus we
5395                  * would end up in an endless cycle of
5396                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5397                  */
5398                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5399                               port_name(intel_dig_port->base.port));
5400                 return IRQ_HANDLED;
5401         }
5402
5403         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5404                       port_name(intel_dig_port->base.port),
5405                       long_hpd ? "long" : "short");
5406
5407         if (long_hpd) {
5408                 intel_dp->reset_link_params = true;
5409                 intel_dp->detect_done = false;
5410                 return IRQ_NONE;
5411         }
5412
5413         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5414
5415         if (intel_dp->is_mst) {
5416                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5417                         /*
5418                          * If we were in MST mode, and device is not
5419                          * there, get out of MST mode
5420                          */
5421                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5422                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5423                         intel_dp->is_mst = false;
5424                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5425                                                         intel_dp->is_mst);
5426                         intel_dp->detect_done = false;
5427                         goto put_power;
5428                 }
5429         }
5430
5431         if (!intel_dp->is_mst) {
5432                 bool handled;
5433
5434                 handled = intel_dp_short_pulse(intel_dp);
5435
5436                 /* Short pulse can signify loss of hdcp authentication */
5437                 intel_hdcp_check_link(intel_dp->attached_connector);
5438
5439                 if (!handled) {
5440                         intel_dp->detect_done = false;
5441                         goto put_power;
5442                 }
5443         }
5444
5445         ret = IRQ_HANDLED;
5446
5447 put_power:
5448         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5449
5450         return ret;
5451 }
5452
5453 /* check the VBT to see whether the eDP is on another port */
5454 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5455 {
5456         /*
5457          * eDP not supported on g4x. so bail out early just
5458          * for a bit extra safety in case the VBT is bonkers.
5459          */
5460         if (INTEL_GEN(dev_priv) < 5)
5461                 return false;
5462
5463         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5464                 return true;
5465
5466         return intel_bios_is_port_edp(dev_priv, port);
5467 }
5468
5469 static void
5470 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5471 {
5472         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5473         enum port port = dp_to_dig_port(intel_dp)->base.port;
5474
5475         if (!IS_G4X(dev_priv) && port != PORT_A)
5476                 intel_attach_force_audio_property(connector);
5477
5478         intel_attach_broadcast_rgb_property(connector);
5479
5480         if (intel_dp_is_edp(intel_dp)) {
5481                 u32 allowed_scalers;
5482
5483                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5484                 if (!HAS_GMCH_DISPLAY(dev_priv))
5485                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5486
5487                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5488
5489                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5490
5491         }
5492 }
5493
5494 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5495 {
5496         intel_dp->panel_power_off_time = ktime_get_boottime();
5497         intel_dp->last_power_on = jiffies;
5498         intel_dp->last_backlight_off = jiffies;
5499 }
5500
5501 static void
5502 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5503 {
5504         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5505         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5506         struct pps_registers regs;
5507
5508         intel_pps_get_registers(intel_dp, &regs);
5509
5510         /* Workaround: Need to write PP_CONTROL with the unlock key as
5511          * the very first thing. */
5512         pp_ctl = ironlake_get_pp_control(intel_dp);
5513
5514         pp_on = I915_READ(regs.pp_on);
5515         pp_off = I915_READ(regs.pp_off);
5516         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5517             !HAS_PCH_ICP(dev_priv)) {
5518                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5519                 pp_div = I915_READ(regs.pp_div);
5520         }
5521
5522         /* Pull timing values out of registers */
5523         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5524                      PANEL_POWER_UP_DELAY_SHIFT;
5525
5526         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5527                   PANEL_LIGHT_ON_DELAY_SHIFT;
5528
5529         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5530                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5531
5532         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5533                    PANEL_POWER_DOWN_DELAY_SHIFT;
5534
5535         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5536             HAS_PCH_ICP(dev_priv)) {
5537                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5538                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5539         } else {
5540                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5541                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5542         }
5543 }
5544
5545 static void
5546 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5547 {
5548         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5549                       state_name,
5550                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5551 }
5552
5553 static void
5554 intel_pps_verify_state(struct intel_dp *intel_dp)
5555 {
5556         struct edp_power_seq hw;
5557         struct edp_power_seq *sw = &intel_dp->pps_delays;
5558
5559         intel_pps_readout_hw_state(intel_dp, &hw);
5560
5561         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5562             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5563                 DRM_ERROR("PPS state mismatch\n");
5564                 intel_pps_dump_state("sw", sw);
5565                 intel_pps_dump_state("hw", &hw);
5566         }
5567 }
5568
5569 static void
5570 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5571 {
5572         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5573         struct edp_power_seq cur, vbt, spec,
5574                 *final = &intel_dp->pps_delays;
5575
5576         lockdep_assert_held(&dev_priv->pps_mutex);
5577
5578         /* already initialized? */
5579         if (final->t11_t12 != 0)
5580                 return;
5581
5582         intel_pps_readout_hw_state(intel_dp, &cur);
5583
5584         intel_pps_dump_state("cur", &cur);
5585
5586         vbt = dev_priv->vbt.edp.pps;
5587         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5588          * of 500ms appears to be too short. Ocassionally the panel
5589          * just fails to power back on. Increasing the delay to 800ms
5590          * seems sufficient to avoid this problem.
5591          */
5592         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5593                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5594                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5595                               vbt.t11_t12);
5596         }
5597         /* T11_T12 delay is special and actually in units of 100ms, but zero
5598          * based in the hw (so we need to add 100 ms). But the sw vbt
5599          * table multiplies it with 1000 to make it in units of 100usec,
5600          * too. */
5601         vbt.t11_t12 += 100 * 10;
5602
5603         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5604          * our hw here, which are all in 100usec. */
5605         spec.t1_t3 = 210 * 10;
5606         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5607         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5608         spec.t10 = 500 * 10;
5609         /* This one is special and actually in units of 100ms, but zero
5610          * based in the hw (so we need to add 100 ms). But the sw vbt
5611          * table multiplies it with 1000 to make it in units of 100usec,
5612          * too. */
5613         spec.t11_t12 = (510 + 100) * 10;
5614
5615         intel_pps_dump_state("vbt", &vbt);
5616
5617         /* Use the max of the register settings and vbt. If both are
5618          * unset, fall back to the spec limits. */
5619 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5620                                        spec.field : \
5621                                        max(cur.field, vbt.field))
5622         assign_final(t1_t3);
5623         assign_final(t8);
5624         assign_final(t9);
5625         assign_final(t10);
5626         assign_final(t11_t12);
5627 #undef assign_final
5628
5629 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5630         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5631         intel_dp->backlight_on_delay = get_delay(t8);
5632         intel_dp->backlight_off_delay = get_delay(t9);
5633         intel_dp->panel_power_down_delay = get_delay(t10);
5634         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5635 #undef get_delay
5636
5637         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5638                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5639                       intel_dp->panel_power_cycle_delay);
5640
5641         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5642                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5643
5644         /*
5645          * We override the HW backlight delays to 1 because we do manual waits
5646          * on them. For T8, even BSpec recommends doing it. For T9, if we
5647          * don't do this, we'll end up waiting for the backlight off delay
5648          * twice: once when we do the manual sleep, and once when we disable
5649          * the panel and wait for the PP_STATUS bit to become zero.
5650          */
5651         final->t8 = 1;
5652         final->t9 = 1;
5653
5654         /*
5655          * HW has only a 100msec granularity for t11_t12 so round it up
5656          * accordingly.
5657          */
5658         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5659 }
5660
5661 static void
5662 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5663                                               bool force_disable_vdd)
5664 {
5665         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5666         u32 pp_on, pp_off, pp_div, port_sel = 0;
5667         int div = dev_priv->rawclk_freq / 1000;
5668         struct pps_registers regs;
5669         enum port port = dp_to_dig_port(intel_dp)->base.port;
5670         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5671
5672         lockdep_assert_held(&dev_priv->pps_mutex);
5673
5674         intel_pps_get_registers(intel_dp, &regs);
5675
5676         /*
5677          * On some VLV machines the BIOS can leave the VDD
5678          * enabled even on power seqeuencers which aren't
5679          * hooked up to any port. This would mess up the
5680          * power domain tracking the first time we pick
5681          * one of these power sequencers for use since
5682          * edp_panel_vdd_on() would notice that the VDD was
5683          * already on and therefore wouldn't grab the power
5684          * domain reference. Disable VDD first to avoid this.
5685          * This also avoids spuriously turning the VDD on as
5686          * soon as the new power seqeuencer gets initialized.
5687          */
5688         if (force_disable_vdd) {
5689                 u32 pp = ironlake_get_pp_control(intel_dp);
5690
5691                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5692
5693                 if (pp & EDP_FORCE_VDD)
5694                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5695
5696                 pp &= ~EDP_FORCE_VDD;
5697
5698                 I915_WRITE(regs.pp_ctrl, pp);
5699         }
5700
5701         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5702                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5703         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5704                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5705         /* Compute the divisor for the pp clock, simply match the Bspec
5706          * formula. */
5707         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5708             HAS_PCH_ICP(dev_priv)) {
5709                 pp_div = I915_READ(regs.pp_ctrl);
5710                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5711                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5712                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5713         } else {
5714                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5715                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5716                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5717         }
5718
5719         /* Haswell doesn't have any port selection bits for the panel
5720          * power sequencer any more. */
5721         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5722                 port_sel = PANEL_PORT_SELECT_VLV(port);
5723         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5724                 if (port == PORT_A)
5725                         port_sel = PANEL_PORT_SELECT_DPA;
5726                 else
5727                         port_sel = PANEL_PORT_SELECT_DPD;
5728         }
5729
5730         pp_on |= port_sel;
5731
5732         I915_WRITE(regs.pp_on, pp_on);
5733         I915_WRITE(regs.pp_off, pp_off);
5734         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5735             HAS_PCH_ICP(dev_priv))
5736                 I915_WRITE(regs.pp_ctrl, pp_div);
5737         else
5738                 I915_WRITE(regs.pp_div, pp_div);
5739
5740         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5741                       I915_READ(regs.pp_on),
5742                       I915_READ(regs.pp_off),
5743                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5744                        HAS_PCH_ICP(dev_priv)) ?
5745                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5746                       I915_READ(regs.pp_div));
5747 }
5748
5749 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5750 {
5751         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5752
5753         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5754                 vlv_initial_power_sequencer_setup(intel_dp);
5755         } else {
5756                 intel_dp_init_panel_power_sequencer(intel_dp);
5757                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5758         }
5759 }
5760
5761 /**
5762  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5763  * @dev_priv: i915 device
5764  * @crtc_state: a pointer to the active intel_crtc_state
5765  * @refresh_rate: RR to be programmed
5766  *
5767  * This function gets called when refresh rate (RR) has to be changed from
5768  * one frequency to another. Switches can be between high and low RR
5769  * supported by the panel or to any other RR based on media playback (in
5770  * this case, RR value needs to be passed from user space).
5771  *
5772  * The caller of this function needs to take a lock on dev_priv->drrs.
5773  */
5774 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5775                                     const struct intel_crtc_state *crtc_state,
5776                                     int refresh_rate)
5777 {
5778         struct intel_encoder *encoder;
5779         struct intel_digital_port *dig_port = NULL;
5780         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5782         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5783
5784         if (refresh_rate <= 0) {
5785                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5786                 return;
5787         }
5788
5789         if (intel_dp == NULL) {
5790                 DRM_DEBUG_KMS("DRRS not supported.\n");
5791                 return;
5792         }
5793
5794         dig_port = dp_to_dig_port(intel_dp);
5795         encoder = &dig_port->base;
5796
5797         if (!intel_crtc) {
5798                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5799                 return;
5800         }
5801
5802         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5803                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5804                 return;
5805         }
5806
5807         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5808                         refresh_rate)
5809                 index = DRRS_LOW_RR;
5810
5811         if (index == dev_priv->drrs.refresh_rate_type) {
5812                 DRM_DEBUG_KMS(
5813                         "DRRS requested for previously set RR...ignoring\n");
5814                 return;
5815         }
5816
5817         if (!crtc_state->base.active) {
5818                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5819                 return;
5820         }
5821
5822         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5823                 switch (index) {
5824                 case DRRS_HIGH_RR:
5825                         intel_dp_set_m_n(intel_crtc, M1_N1);
5826                         break;
5827                 case DRRS_LOW_RR:
5828                         intel_dp_set_m_n(intel_crtc, M2_N2);
5829                         break;
5830                 case DRRS_MAX_RR:
5831                 default:
5832                         DRM_ERROR("Unsupported refreshrate type\n");
5833                 }
5834         } else if (INTEL_GEN(dev_priv) > 6) {
5835                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5836                 u32 val;
5837
5838                 val = I915_READ(reg);
5839                 if (index > DRRS_HIGH_RR) {
5840                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5841                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5842                         else
5843                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5844                 } else {
5845                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5846                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5847                         else
5848                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5849                 }
5850                 I915_WRITE(reg, val);
5851         }
5852
5853         dev_priv->drrs.refresh_rate_type = index;
5854
5855         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5856 }
5857
5858 /**
5859  * intel_edp_drrs_enable - init drrs struct if supported
5860  * @intel_dp: DP struct
5861  * @crtc_state: A pointer to the active crtc state.
5862  *
5863  * Initializes frontbuffer_bits and drrs.dp
5864  */
5865 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5866                            const struct intel_crtc_state *crtc_state)
5867 {
5868         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5869
5870         if (!crtc_state->has_drrs) {
5871                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5872                 return;
5873         }
5874
5875         if (dev_priv->psr.enabled) {
5876                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5877                 return;
5878         }
5879
5880         mutex_lock(&dev_priv->drrs.mutex);
5881         if (WARN_ON(dev_priv->drrs.dp)) {
5882                 DRM_ERROR("DRRS already enabled\n");
5883                 goto unlock;
5884         }
5885
5886         dev_priv->drrs.busy_frontbuffer_bits = 0;
5887
5888         dev_priv->drrs.dp = intel_dp;
5889
5890 unlock:
5891         mutex_unlock(&dev_priv->drrs.mutex);
5892 }
5893
5894 /**
5895  * intel_edp_drrs_disable - Disable DRRS
5896  * @intel_dp: DP struct
5897  * @old_crtc_state: Pointer to old crtc_state.
5898  *
5899  */
5900 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5901                             const struct intel_crtc_state *old_crtc_state)
5902 {
5903         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5904
5905         if (!old_crtc_state->has_drrs)
5906                 return;
5907
5908         mutex_lock(&dev_priv->drrs.mutex);
5909         if (!dev_priv->drrs.dp) {
5910                 mutex_unlock(&dev_priv->drrs.mutex);
5911                 return;
5912         }
5913
5914         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5915                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5916                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5917
5918         dev_priv->drrs.dp = NULL;
5919         mutex_unlock(&dev_priv->drrs.mutex);
5920
5921         cancel_delayed_work_sync(&dev_priv->drrs.work);
5922 }
5923
5924 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5925 {
5926         struct drm_i915_private *dev_priv =
5927                 container_of(work, typeof(*dev_priv), drrs.work.work);
5928         struct intel_dp *intel_dp;
5929
5930         mutex_lock(&dev_priv->drrs.mutex);
5931
5932         intel_dp = dev_priv->drrs.dp;
5933
5934         if (!intel_dp)
5935                 goto unlock;
5936
5937         /*
5938          * The delayed work can race with an invalidate hence we need to
5939          * recheck.
5940          */
5941
5942         if (dev_priv->drrs.busy_frontbuffer_bits)
5943                 goto unlock;
5944
5945         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5946                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5947
5948                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5949                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5950         }
5951
5952 unlock:
5953         mutex_unlock(&dev_priv->drrs.mutex);
5954 }
5955
5956 /**
5957  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5958  * @dev_priv: i915 device
5959  * @frontbuffer_bits: frontbuffer plane tracking bits
5960  *
5961  * This function gets called everytime rendering on the given planes start.
5962  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5963  *
5964  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5965  */
5966 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5967                                unsigned int frontbuffer_bits)
5968 {
5969         struct drm_crtc *crtc;
5970         enum pipe pipe;
5971
5972         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5973                 return;
5974
5975         cancel_delayed_work(&dev_priv->drrs.work);
5976
5977         mutex_lock(&dev_priv->drrs.mutex);
5978         if (!dev_priv->drrs.dp) {
5979                 mutex_unlock(&dev_priv->drrs.mutex);
5980                 return;
5981         }
5982
5983         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5984         pipe = to_intel_crtc(crtc)->pipe;
5985
5986         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5987         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5988
5989         /* invalidate means busy screen hence upclock */
5990         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5991                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5992                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5993
5994         mutex_unlock(&dev_priv->drrs.mutex);
5995 }
5996
5997 /**
5998  * intel_edp_drrs_flush - Restart Idleness DRRS
5999  * @dev_priv: i915 device
6000  * @frontbuffer_bits: frontbuffer plane tracking bits
6001  *
6002  * This function gets called every time rendering on the given planes has
6003  * completed or flip on a crtc is completed. So DRRS should be upclocked
6004  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6005  * if no other planes are dirty.
6006  *
6007  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6008  */
6009 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6010                           unsigned int frontbuffer_bits)
6011 {
6012         struct drm_crtc *crtc;
6013         enum pipe pipe;
6014
6015         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6016                 return;
6017
6018         cancel_delayed_work(&dev_priv->drrs.work);
6019
6020         mutex_lock(&dev_priv->drrs.mutex);
6021         if (!dev_priv->drrs.dp) {
6022                 mutex_unlock(&dev_priv->drrs.mutex);
6023                 return;
6024         }
6025
6026         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6027         pipe = to_intel_crtc(crtc)->pipe;
6028
6029         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6030         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6031
6032         /* flush means busy screen hence upclock */
6033         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6034                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6035                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6036
6037         /*
6038          * flush also means no more activity hence schedule downclock, if all
6039          * other fbs are quiescent too
6040          */
6041         if (!dev_priv->drrs.busy_frontbuffer_bits)
6042                 schedule_delayed_work(&dev_priv->drrs.work,
6043                                 msecs_to_jiffies(1000));
6044         mutex_unlock(&dev_priv->drrs.mutex);
6045 }
6046
6047 /**
6048  * DOC: Display Refresh Rate Switching (DRRS)
6049  *
6050  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6051  * which enables swtching between low and high refresh rates,
6052  * dynamically, based on the usage scenario. This feature is applicable
6053  * for internal panels.
6054  *
6055  * Indication that the panel supports DRRS is given by the panel EDID, which
6056  * would list multiple refresh rates for one resolution.
6057  *
6058  * DRRS is of 2 types - static and seamless.
6059  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6060  * (may appear as a blink on screen) and is used in dock-undock scenario.
6061  * Seamless DRRS involves changing RR without any visual effect to the user
6062  * and can be used during normal system usage. This is done by programming
6063  * certain registers.
6064  *
6065  * Support for static/seamless DRRS may be indicated in the VBT based on
6066  * inputs from the panel spec.
6067  *
6068  * DRRS saves power by switching to low RR based on usage scenarios.
6069  *
6070  * The implementation is based on frontbuffer tracking implementation.  When
6071  * there is a disturbance on the screen triggered by user activity or a periodic
6072  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6073  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6074  * made.
6075  *
6076  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6077  * and intel_edp_drrs_flush() are called.
6078  *
6079  * DRRS can be further extended to support other internal panels and also
6080  * the scenario of video playback wherein RR is set based on the rate
6081  * requested by userspace.
6082  */
6083
6084 /**
6085  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6086  * @connector: eDP connector
6087  * @fixed_mode: preferred mode of panel
6088  *
6089  * This function is  called only once at driver load to initialize basic
6090  * DRRS stuff.
6091  *
6092  * Returns:
6093  * Downclock mode if panel supports it, else return NULL.
6094  * DRRS support is determined by the presence of downclock mode (apart
6095  * from VBT setting).
6096  */
6097 static struct drm_display_mode *
6098 intel_dp_drrs_init(struct intel_connector *connector,
6099                    struct drm_display_mode *fixed_mode)
6100 {
6101         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6102         struct drm_display_mode *downclock_mode = NULL;
6103
6104         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6105         mutex_init(&dev_priv->drrs.mutex);
6106
6107         if (INTEL_GEN(dev_priv) <= 6) {
6108                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6109                 return NULL;
6110         }
6111
6112         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6113                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6114                 return NULL;
6115         }
6116
6117         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6118                                                     &connector->base);
6119
6120         if (!downclock_mode) {
6121                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6122                 return NULL;
6123         }
6124
6125         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6126
6127         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6128         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6129         return downclock_mode;
6130 }
6131
6132 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6133                                      struct intel_connector *intel_connector)
6134 {
6135         struct drm_device *dev = intel_dp_to_dev(intel_dp);
6136         struct drm_i915_private *dev_priv = to_i915(dev);
6137         struct drm_connector *connector = &intel_connector->base;
6138         struct drm_display_mode *fixed_mode = NULL;
6139         struct drm_display_mode *downclock_mode = NULL;
6140         bool has_dpcd;
6141         struct drm_display_mode *scan;
6142         struct edid *edid;
6143         enum pipe pipe = INVALID_PIPE;
6144
6145         if (!intel_dp_is_edp(intel_dp))
6146                 return true;
6147
6148         /*
6149          * On IBX/CPT we may get here with LVDS already registered. Since the
6150          * driver uses the only internal power sequencer available for both
6151          * eDP and LVDS bail out early in this case to prevent interfering
6152          * with an already powered-on LVDS power sequencer.
6153          */
6154         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6155                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6156                 DRM_INFO("LVDS was detected, not registering eDP\n");
6157
6158                 return false;
6159         }
6160
6161         pps_lock(intel_dp);
6162
6163         intel_dp_init_panel_power_timestamps(intel_dp);
6164         intel_dp_pps_init(intel_dp);
6165         intel_edp_panel_vdd_sanitize(intel_dp);
6166
6167         pps_unlock(intel_dp);
6168
6169         /* Cache DPCD and EDID for edp. */
6170         has_dpcd = intel_edp_init_dpcd(intel_dp);
6171
6172         if (!has_dpcd) {
6173                 /* if this fails, presume the device is a ghost */
6174                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6175                 goto out_vdd_off;
6176         }
6177
6178         mutex_lock(&dev->mode_config.mutex);
6179         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6180         if (edid) {
6181                 if (drm_add_edid_modes(connector, edid)) {
6182                         drm_mode_connector_update_edid_property(connector,
6183                                                                 edid);
6184                 } else {
6185                         kfree(edid);
6186                         edid = ERR_PTR(-EINVAL);
6187                 }
6188         } else {
6189                 edid = ERR_PTR(-ENOENT);
6190         }
6191         intel_connector->edid = edid;
6192
6193         /* prefer fixed mode from EDID if available */
6194         list_for_each_entry(scan, &connector->probed_modes, head) {
6195                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6196                         fixed_mode = drm_mode_duplicate(dev, scan);
6197                         downclock_mode = intel_dp_drrs_init(
6198                                                 intel_connector, fixed_mode);
6199                         break;
6200                 }
6201         }
6202
6203         /* fallback to VBT if available for eDP */
6204         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6205                 fixed_mode = drm_mode_duplicate(dev,
6206                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6207                 if (fixed_mode) {
6208                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6209                         connector->display_info.width_mm = fixed_mode->width_mm;
6210                         connector->display_info.height_mm = fixed_mode->height_mm;
6211                 }
6212         }
6213         mutex_unlock(&dev->mode_config.mutex);
6214
6215         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6216                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6217                 register_reboot_notifier(&intel_dp->edp_notifier);
6218
6219                 /*
6220                  * Figure out the current pipe for the initial backlight setup.
6221                  * If the current pipe isn't valid, try the PPS pipe, and if that
6222                  * fails just assume pipe A.
6223                  */
6224                 pipe = vlv_active_pipe(intel_dp);
6225
6226                 if (pipe != PIPE_A && pipe != PIPE_B)
6227                         pipe = intel_dp->pps_pipe;
6228
6229                 if (pipe != PIPE_A && pipe != PIPE_B)
6230                         pipe = PIPE_A;
6231
6232                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6233                               pipe_name(pipe));
6234         }
6235
6236         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6237         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6238         intel_panel_setup_backlight(connector, pipe);
6239
6240         return true;
6241
6242 out_vdd_off:
6243         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6244         /*
6245          * vdd might still be enabled do to the delayed vdd off.
6246          * Make sure vdd is actually turned off here.
6247          */
6248         pps_lock(intel_dp);
6249         edp_panel_vdd_off_sync(intel_dp);
6250         pps_unlock(intel_dp);
6251
6252         return false;
6253 }
6254
6255 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6256 {
6257         struct intel_connector *intel_connector;
6258         struct drm_connector *connector;
6259
6260         intel_connector = container_of(work, typeof(*intel_connector),
6261                                        modeset_retry_work);
6262         connector = &intel_connector->base;
6263         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6264                       connector->name);
6265
6266         /* Grab the locks before changing connector property*/
6267         mutex_lock(&connector->dev->mode_config.mutex);
6268         /* Set connector link status to BAD and send a Uevent to notify
6269          * userspace to do a modeset.
6270          */
6271         drm_mode_connector_set_link_status_property(connector,
6272                                                     DRM_MODE_LINK_STATUS_BAD);
6273         mutex_unlock(&connector->dev->mode_config.mutex);
6274         /* Send Hotplug uevent so userspace can reprobe */
6275         drm_kms_helper_hotplug_event(connector->dev);
6276 }
6277
6278 bool
6279 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6280                         struct intel_connector *intel_connector)
6281 {
6282         struct drm_connector *connector = &intel_connector->base;
6283         struct intel_dp *intel_dp = &intel_dig_port->dp;
6284         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6285         struct drm_device *dev = intel_encoder->base.dev;
6286         struct drm_i915_private *dev_priv = to_i915(dev);
6287         enum port port = intel_encoder->port;
6288         int type;
6289
6290         /* Initialize the work for modeset in case of link train failure */
6291         INIT_WORK(&intel_connector->modeset_retry_work,
6292                   intel_dp_modeset_retry_work_fn);
6293
6294         if (WARN(intel_dig_port->max_lanes < 1,
6295                  "Not enough lanes (%d) for DP on port %c\n",
6296                  intel_dig_port->max_lanes, port_name(port)))
6297                 return false;
6298
6299         intel_dp_set_source_rates(intel_dp);
6300
6301         intel_dp->reset_link_params = true;
6302         intel_dp->pps_pipe = INVALID_PIPE;
6303         intel_dp->active_pipe = INVALID_PIPE;
6304
6305         /* intel_dp vfuncs */
6306         if (HAS_DDI(dev_priv))
6307                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6308
6309         /* Preserve the current hw state. */
6310         intel_dp->DP = I915_READ(intel_dp->output_reg);
6311         intel_dp->attached_connector = intel_connector;
6312
6313         if (intel_dp_is_port_edp(dev_priv, port))
6314                 type = DRM_MODE_CONNECTOR_eDP;
6315         else
6316                 type = DRM_MODE_CONNECTOR_DisplayPort;
6317
6318         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6319                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6320
6321         /*
6322          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6323          * for DP the encoder type can be set by the caller to
6324          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6325          */
6326         if (type == DRM_MODE_CONNECTOR_eDP)
6327                 intel_encoder->type = INTEL_OUTPUT_EDP;
6328
6329         /* eDP only on port B and/or C on vlv/chv */
6330         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6331                     intel_dp_is_edp(intel_dp) &&
6332                     port != PORT_B && port != PORT_C))
6333                 return false;
6334
6335         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6336                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6337                         port_name(port));
6338
6339         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6340         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6341
6342         if (!HAS_GMCH_DISPLAY(dev_priv))
6343                 connector->interlace_allowed = true;
6344         connector->doublescan_allowed = 0;
6345
6346         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6347
6348         intel_dp_aux_init(intel_dp);
6349
6350         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6351                           edp_panel_vdd_work);
6352
6353         intel_connector_attach_encoder(intel_connector, intel_encoder);
6354
6355         if (HAS_DDI(dev_priv))
6356                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6357         else
6358                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6359
6360         /* init MST on ports that can support it */
6361         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6362             (port == PORT_B || port == PORT_C ||
6363              port == PORT_D || port == PORT_F))
6364                 intel_dp_mst_encoder_init(intel_dig_port,
6365                                           intel_connector->base.base.id);
6366
6367         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6368                 intel_dp_aux_fini(intel_dp);
6369                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6370                 goto fail;
6371         }
6372
6373         intel_dp_add_properties(intel_dp, connector);
6374
6375         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6376                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6377                 if (ret)
6378                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6379         }
6380
6381         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6382          * 0xd.  Failure to do so will result in spurious interrupts being
6383          * generated on the port when a cable is not attached.
6384          */
6385         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6386                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6387                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6388         }
6389
6390         return true;
6391
6392 fail:
6393         drm_connector_cleanup(connector);
6394
6395         return false;
6396 }
6397
6398 bool intel_dp_init(struct drm_i915_private *dev_priv,
6399                    i915_reg_t output_reg,
6400                    enum port port)
6401 {
6402         struct intel_digital_port *intel_dig_port;
6403         struct intel_encoder *intel_encoder;
6404         struct drm_encoder *encoder;
6405         struct intel_connector *intel_connector;
6406
6407         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6408         if (!intel_dig_port)
6409                 return false;
6410
6411         intel_connector = intel_connector_alloc();
6412         if (!intel_connector)
6413                 goto err_connector_alloc;
6414
6415         intel_encoder = &intel_dig_port->base;
6416         encoder = &intel_encoder->base;
6417
6418         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6419                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6420                              "DP %c", port_name(port)))
6421                 goto err_encoder_init;
6422
6423         intel_encoder->hotplug = intel_dp_hotplug;
6424         intel_encoder->compute_config = intel_dp_compute_config;
6425         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6426         intel_encoder->get_config = intel_dp_get_config;
6427         intel_encoder->suspend = intel_dp_encoder_suspend;
6428         if (IS_CHERRYVIEW(dev_priv)) {
6429                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6430                 intel_encoder->pre_enable = chv_pre_enable_dp;
6431                 intel_encoder->enable = vlv_enable_dp;
6432                 intel_encoder->disable = vlv_disable_dp;
6433                 intel_encoder->post_disable = chv_post_disable_dp;
6434                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6435         } else if (IS_VALLEYVIEW(dev_priv)) {
6436                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6437                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6438                 intel_encoder->enable = vlv_enable_dp;
6439                 intel_encoder->disable = vlv_disable_dp;
6440                 intel_encoder->post_disable = vlv_post_disable_dp;
6441         } else {
6442                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6443                 intel_encoder->enable = g4x_enable_dp;
6444                 intel_encoder->disable = g4x_disable_dp;
6445                 intel_encoder->post_disable = g4x_post_disable_dp;
6446         }
6447
6448         intel_dig_port->dp.output_reg = output_reg;
6449         intel_dig_port->max_lanes = 4;
6450
6451         intel_encoder->type = INTEL_OUTPUT_DP;
6452         intel_encoder->power_domain = intel_port_to_power_domain(port);
6453         if (IS_CHERRYVIEW(dev_priv)) {
6454                 if (port == PORT_D)
6455                         intel_encoder->crtc_mask = 1 << 2;
6456                 else
6457                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6458         } else {
6459                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6460         }
6461         intel_encoder->cloneable = 0;
6462         intel_encoder->port = port;
6463
6464         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6465         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6466
6467         if (port != PORT_A)
6468                 intel_infoframe_init(intel_dig_port);
6469
6470         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6471                 goto err_init_connector;
6472
6473         return true;
6474
6475 err_init_connector:
6476         drm_encoder_cleanup(encoder);
6477 err_encoder_init:
6478         kfree(intel_connector);
6479 err_connector_alloc:
6480         kfree(intel_dig_port);
6481         return false;
6482 }
6483
6484 void intel_dp_mst_suspend(struct drm_device *dev)
6485 {
6486         struct drm_i915_private *dev_priv = to_i915(dev);
6487         int i;
6488
6489         /* disable MST */
6490         for (i = 0; i < I915_MAX_PORTS; i++) {
6491                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6492
6493                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6494                         continue;
6495
6496                 if (intel_dig_port->dp.is_mst)
6497                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6498         }
6499 }
6500
6501 void intel_dp_mst_resume(struct drm_device *dev)
6502 {
6503         struct drm_i915_private *dev_priv = to_i915(dev);
6504         int i;
6505
6506         for (i = 0; i < I915_MAX_PORTS; i++) {
6507                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6508                 int ret;
6509
6510                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6511                         continue;
6512
6513                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6514                 if (ret)
6515                         intel_dp_check_mst_status(&intel_dig_port->dp);
6516         }
6517 }