drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /**
  68  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69  * @intel_dp: DP struct
  70  *
  71  * If a CPU or PCH DP output is attached to an eDP panel, this function
  72  * will return true, and false otherwise.
  73  */
  74 static bool is_edp(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77
  78         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  79 }
  80
  81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  82 {
  83         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  84
  85         return intel_dig_port->base.base.dev;
  86 }
  87
  88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static void intel_dp_link_down(struct intel_dp *intel_dp);
  94
  95 static int
  96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  97 {
  98         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  99
 100         switch (max_link_bw) {
 101         case DP_LINK_BW_1_62:
 102         case DP_LINK_BW_2_7:
 103                 break;
 104         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 105                 max_link_bw = DP_LINK_BW_2_7;
 106                 break;
 107         default:
 108                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 109                      max_link_bw);
 110                 max_link_bw = DP_LINK_BW_1_62;
 111                 break;
 112         }
 113         return max_link_bw;
 114 }
 115
 116 /*
 117  * The units on the numbers in the next two are... bizarre.  Examples will
 118  * make it clearer; this one parallels an example in the eDP spec.
 119  *
 120  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 121  *
 122  *     270000 * 1 * 8 / 10 == 216000
 123  *
 124  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 125  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 126  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 127  * 119000.  At 18bpp that's 2142000 kilobits per second.
 128  *
 129  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 130  * get the result in decakilobits instead of kilobits.
 131  */
 132
 133 static int
 134 intel_dp_link_required(int pixel_clock, int bpp)
 135 {
 136         return (pixel_clock * bpp + 9) / 10;
 137 }
 138
 139 static int
 140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 141 {
 142         return (max_link_clock * max_lanes * 8) / 10;
 143 }
 144
 145 static enum drm_mode_status
 146 intel_dp_mode_valid(struct drm_connector *connector,
 147                     struct drm_display_mode *mode)
 148 {
 149         struct intel_dp *intel_dp = intel_attached_dp(connector);
 150         struct intel_connector *intel_connector = to_intel_connector(connector);
 151         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 152         int target_clock = mode->clock;
 153         int max_rate, mode_rate, max_lanes, max_link_clock;
 154
 155         if (is_edp(intel_dp) && fixed_mode) {
 156                 if (mode->hdisplay > fixed_mode->hdisplay)
 157                         return MODE_PANEL;
 158
 159                 if (mode->vdisplay > fixed_mode->vdisplay)
 160                         return MODE_PANEL;
 161
 162                 target_clock = fixed_mode->clock;
 163         }
 164
 165         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 166         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 167
 168         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 169         mode_rate = intel_dp_link_required(target_clock, 18);
 170
 171         if (mode_rate > max_rate)
 172                 return MODE_CLOCK_HIGH;
 173
 174         if (mode->clock < 10000)
 175                 return MODE_CLOCK_LOW;
 176
 177         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 178                 return MODE_H_ILLEGAL;
 179
 180         return MODE_OK;
 181 }
 182
 183 static uint32_t
 184 pack_aux(uint8_t *src, int src_bytes)
 185 {
 186         int     i;
 187         uint32_t v = 0;
 188
 189         if (src_bytes > 4)
 190                 src_bytes = 4;
 191         for (i = 0; i < src_bytes; i++)
 192                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 193         return v;
 194 }
 195
 196 static void
 197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 198 {
 199         int i;
 200         if (dst_bytes > 4)
 201                 dst_bytes = 4;
 202         for (i = 0; i < dst_bytes; i++)
 203                 dst[i] = src >> ((3-i) * 8);
 204 }
 205
 206 /* hrawclock is 1/4 the FSB frequency */
 207 static int
 208 intel_hrawclk(struct drm_device *dev)
 209 {
 210         struct drm_i915_private *dev_priv = dev->dev_private;
 211         uint32_t clkcfg;
 212
 213         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 214         if (IS_VALLEYVIEW(dev))
 215                 return 200;
 216
 217         clkcfg = I915_READ(CLKCFG);
 218         switch (clkcfg & CLKCFG_FSB_MASK) {
 219         case CLKCFG_FSB_400:
 220                 return 100;
 221         case CLKCFG_FSB_533:
 222                 return 133;
 223         case CLKCFG_FSB_667:
 224                 return 166;
 225         case CLKCFG_FSB_800:
 226                 return 200;
 227         case CLKCFG_FSB_1067:
 228                 return 266;
 229         case CLKCFG_FSB_1333:
 230                 return 333;
 231         /* these two are just a guess; one of them might be right */
 232         case CLKCFG_FSB_1600:
 233         case CLKCFG_FSB_1600_ALT:
 234                 return 400;
 235         default:
 236                 return 133;
 237         }
 238 }
 239
 240 static void
 241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 242                                     struct intel_dp *intel_dp,
 243                                     struct edp_power_seq *out);
 244 static void
 245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 246                                               struct intel_dp *intel_dp,
 247                                               struct edp_power_seq *out);
 248
 249 static enum pipe
 250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 251 {
 252         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 253         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 254         struct drm_device *dev = intel_dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         enum port port = intel_dig_port->port;
 257         enum pipe pipe;
 258
 259         /* modeset should have pipe */
 260         if (crtc)
 261                 return to_intel_crtc(crtc)->pipe;
 262
 263         /* init time, try to find a pipe with this port selected */
 264         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 265                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 266                         PANEL_PORT_SELECT_MASK;
 267                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 268                         return pipe;
 269                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 270                         return pipe;
 271         }
 272
 273         /* shrug */
 274         return PIPE_A;
 275 }
 276
 277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 278 {
 279         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 280
 281         if (HAS_PCH_SPLIT(dev))
 282                 return PCH_PP_CONTROL;
 283         else
 284                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 285 }
 286
 287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 288 {
 289         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 290
 291         if (HAS_PCH_SPLIT(dev))
 292                 return PCH_PP_STATUS;
 293         else
 294                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 295 }
 296
 297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 298 {
 299         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 300         struct drm_i915_private *dev_priv = dev->dev_private;
 301
 302         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 303 }
 304
 305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 306 {
 307         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 308         struct drm_i915_private *dev_priv = dev->dev_private;
 309
 310         return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 311 }
 312
 313 static void
 314 intel_dp_check_edp(struct intel_dp *intel_dp)
 315 {
 316         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318
 319         if (!is_edp(intel_dp))
 320                 return;
 321
 322         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 323                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 324                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 325                               I915_READ(_pp_stat_reg(intel_dp)),
 326                               I915_READ(_pp_ctrl_reg(intel_dp)));
 327         }
 328 }
 329
 330 static uint32_t
 331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 332 {
 333         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 334         struct drm_device *dev = intel_dig_port->base.base.dev;
 335         struct drm_i915_private *dev_priv = dev->dev_private;
 336         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 337         uint32_t status;
 338         bool done;
 339
 340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 341         if (has_aux_irq)
 342                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 343                                           msecs_to_jiffies_timeout(10));
 344         else
 345                 done = wait_for_atomic(C, 10) == 0;
 346         if (!done)
 347                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 348                           has_aux_irq);
 349 #undef C
 350
 351         return status;
 352 }
 353
 354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
 355                                       int index)
 356 {
 357         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 358         struct drm_device *dev = intel_dig_port->base.base.dev;
 359         struct drm_i915_private *dev_priv = dev->dev_private;
 360
 361         /* The clock divider is based off the hrawclk,
 362          * and would like to run at 2MHz. So, take the
 363          * hrawclk value and divide by 2 and use that
 364          *
 365          * Note that PCH attached eDP panels should use a 125MHz input
 366          * clock divider.
 367          */
 368         if (IS_VALLEYVIEW(dev)) {
 369                 return index ? 0 : 100;
 370         } else if (intel_dig_port->port == PORT_A) {
 371                 if (index)
 372                         return 0;
 373                 if (HAS_DDI(dev))
 374                         return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 375                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 376                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 377                 else
 378                         return 225; /* eDP input clock at 450Mhz */
 379         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 380                 /* Workaround for non-ULT HSW */
 381                 switch (index) {
 382                 case 0: return 63;
 383                 case 1: return 72;
 384                 default: return 0;
 385                 }
 386         } else if (HAS_PCH_SPLIT(dev)) {
 387                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 388         } else {
 389                 return index ? 0 :intel_hrawclk(dev) / 2;
 390         }
 391 }
 392
 393 static int
 394 intel_dp_aux_ch(struct intel_dp *intel_dp,
 395                 uint8_t *send, int send_bytes,
 396                 uint8_t *recv, int recv_size)
 397 {
 398         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 399         struct drm_device *dev = intel_dig_port->base.base.dev;
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 402         uint32_t ch_data = ch_ctl + 4;
 403         uint32_t aux_clock_divider;
 404         int i, ret, recv_bytes;
 405         uint32_t status;
 406         int try, precharge, clock = 0;
 407         bool has_aux_irq = true;
 408         uint32_t timeout;
 409
 410         /* dp aux is extremely sensitive to irq latency, hence request the
 411          * lowest possible wakeup latency and so prevent the cpu from going into
 412          * deep sleep states.
 413          */
 414         pm_qos_update_request(&dev_priv->pm_qos, 0);
 415
 416         intel_dp_check_edp(intel_dp);
 417
 418         if (IS_GEN6(dev))
 419                 precharge = 3;
 420         else
 421                 precharge = 5;
 422
 423         if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
 424                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 425         else
 426                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 427
 428         intel_aux_display_runtime_get(dev_priv);
 429
 430         /* Try to wait for any previous AUX channel activity */
 431         for (try = 0; try < 3; try++) {
 432                 status = I915_READ_NOTRACE(ch_ctl);
 433                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 434                         break;
 435                 msleep(1);
 436         }
 437
 438         if (try == 3) {
 439                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 440                      I915_READ(ch_ctl));
 441                 ret = -EBUSY;
 442                 goto out;
 443         }
 444
 445         /* Only 5 data registers! */
 446         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 447                 ret = -E2BIG;
 448                 goto out;
 449         }
 450
 451         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
 452                 /* Must try at least 3 times according to DP spec */
 453                 for (try = 0; try < 5; try++) {
 454                         /* Load the send data into the aux channel data registers */
 455                         for (i = 0; i < send_bytes; i += 4)
 456                                 I915_WRITE(ch_data + i,
 457                                            pack_aux(send + i, send_bytes - i));
 458
 459                         /* Send the command and wait for it to complete */
 460                         I915_WRITE(ch_ctl,
 461                                    DP_AUX_CH_CTL_SEND_BUSY |
 462                                    (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 463                                    timeout |
 464                                    (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 465                                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 466                                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 467                                    DP_AUX_CH_CTL_DONE |
 468                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 469                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 470
 471                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 472
 473                         /* Clear done status and any errors */
 474                         I915_WRITE(ch_ctl,
 475                                    status |
 476                                    DP_AUX_CH_CTL_DONE |
 477                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 478                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 479
 480                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 481                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 482                                 continue;
 483                         if (status & DP_AUX_CH_CTL_DONE)
 484                                 break;
 485                 }
 486                 if (status & DP_AUX_CH_CTL_DONE)
 487                         break;
 488         }
 489
 490         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 491                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 492                 ret = -EBUSY;
 493                 goto out;
 494         }
 495
 496         /* Check for timeout or receive error.
 497          * Timeouts occur when the sink is not connected
 498          */
 499         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 500                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 501                 ret = -EIO;
 502                 goto out;
 503         }
 504
 505         /* Timeouts occur when the device isn't connected, so they're
 506          * "normal" -- don't fill the kernel log with these */
 507         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 508                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 509                 ret = -ETIMEDOUT;
 510                 goto out;
 511         }
 512
 513         /* Unload any bytes sent back from the other side */
 514         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 515                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 516         if (recv_bytes > recv_size)
 517                 recv_bytes = recv_size;
 518
 519         for (i = 0; i < recv_bytes; i += 4)
 520                 unpack_aux(I915_READ(ch_data + i),
 521                            recv + i, recv_bytes - i);
 522
 523         ret = recv_bytes;
 524 out:
 525         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 526         intel_aux_display_runtime_put(dev_priv);
 527
 528         return ret;
 529 }
 530
 531 /* Write data to the aux channel in native mode */
 532 static int
 533 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 534                           uint16_t address, uint8_t *send, int send_bytes)
 535 {
 536         int ret;
 537         uint8_t msg[20];
 538         int msg_bytes;
 539         uint8_t ack;
 540
 541         if (WARN_ON(send_bytes > 16))
 542                 return -E2BIG;
 543
 544         intel_dp_check_edp(intel_dp);
 545         msg[0] = AUX_NATIVE_WRITE << 4;
 546         msg[1] = address >> 8;
 547         msg[2] = address & 0xff;
 548         msg[3] = send_bytes - 1;
 549         memcpy(&msg[4], send, send_bytes);
 550         msg_bytes = send_bytes + 4;
 551         for (;;) {
 552                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 553                 if (ret < 0)
 554                         return ret;
 555                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 556                         break;
 557                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 558                         udelay(100);
 559                 else
 560                         return -EIO;
 561         }
 562         return send_bytes;
 563 }
 564
 565 /* Write a single byte to the aux channel in native mode */
 566 static int
 567 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 568                             uint16_t address, uint8_t byte)
 569 {
 570         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 571 }
 572
 573 /* read bytes from a native aux channel */
 574 static int
 575 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 576                          uint16_t address, uint8_t *recv, int recv_bytes)
 577 {
 578         uint8_t msg[4];
 579         int msg_bytes;
 580         uint8_t reply[20];
 581         int reply_bytes;
 582         uint8_t ack;
 583         int ret;
 584
 585         if (WARN_ON(recv_bytes > 19))
 586                 return -E2BIG;
 587
 588         intel_dp_check_edp(intel_dp);
 589         msg[0] = AUX_NATIVE_READ << 4;
 590         msg[1] = address >> 8;
 591         msg[2] = address & 0xff;
 592         msg[3] = recv_bytes - 1;
 593
 594         msg_bytes = 4;
 595         reply_bytes = recv_bytes + 1;
 596
 597         for (;;) {
 598                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 599                                       reply, reply_bytes);
 600                 if (ret == 0)
 601                         return -EPROTO;
 602                 if (ret < 0)
 603                         return ret;
 604                 ack = reply[0];
 605                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 606                         memcpy(recv, reply + 1, ret - 1);
 607                         return ret - 1;
 608                 }
 609                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 610                         udelay(100);
 611                 else
 612                         return -EIO;
 613         }
 614 }
 615
 616 static int
 617 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 618                     uint8_t write_byte, uint8_t *read_byte)
 619 {
 620         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 621         struct intel_dp *intel_dp = container_of(adapter,
 622                                                 struct intel_dp,
 623                                                 adapter);
 624         uint16_t address = algo_data->address;
 625         uint8_t msg[5];
 626         uint8_t reply[2];
 627         unsigned retry;
 628         int msg_bytes;
 629         int reply_bytes;
 630         int ret;
 631
 632         ironlake_edp_panel_vdd_on(intel_dp);
 633         intel_dp_check_edp(intel_dp);
 634         /* Set up the command byte */
 635         if (mode & MODE_I2C_READ)
 636                 msg[0] = AUX_I2C_READ << 4;
 637         else
 638                 msg[0] = AUX_I2C_WRITE << 4;
 639
 640         if (!(mode & MODE_I2C_STOP))
 641                 msg[0] |= AUX_I2C_MOT << 4;
 642
 643         msg[1] = address >> 8;
 644         msg[2] = address;
 645
 646         switch (mode) {
 647         case MODE_I2C_WRITE:
 648                 msg[3] = 0;
 649                 msg[4] = write_byte;
 650                 msg_bytes = 5;
 651                 reply_bytes = 1;
 652                 break;
 653         case MODE_I2C_READ:
 654                 msg[3] = 0;
 655                 msg_bytes = 4;
 656                 reply_bytes = 2;
 657                 break;
 658         default:
 659                 msg_bytes = 3;
 660                 reply_bytes = 1;
 661                 break;
 662         }
 663
 664         /*
 665          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
 666          * required to retry at least seven times upon receiving AUX_DEFER
 667          * before giving up the AUX transaction.
 668          */
 669         for (retry = 0; retry < 7; retry++) {
 670                 ret = intel_dp_aux_ch(intel_dp,
 671                                       msg, msg_bytes,
 672                                       reply, reply_bytes);
 673                 if (ret < 0) {
 674                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 675                         goto out;
 676                 }
 677
 678                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 679                 case AUX_NATIVE_REPLY_ACK:
 680                         /* I2C-over-AUX Reply field is only valid
 681                          * when paired with AUX ACK.
 682                          */
 683                         break;
 684                 case AUX_NATIVE_REPLY_NACK:
 685                         DRM_DEBUG_KMS("aux_ch native nack\n");
 686                         ret = -EREMOTEIO;
 687                         goto out;
 688                 case AUX_NATIVE_REPLY_DEFER:
 689                         /*
 690                          * For now, just give more slack to branch devices. We
 691                          * could check the DPCD for I2C bit rate capabilities,
 692                          * and if available, adjust the interval. We could also
 693                          * be more careful with DP-to-Legacy adapters where a
 694                          * long legacy cable may force very low I2C bit rates.
 695                          */
 696                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 697                             DP_DWN_STRM_PORT_PRESENT)
 698                                 usleep_range(500, 600);
 699                         else
 700                                 usleep_range(300, 400);
 701                         continue;
 702                 default:
 703                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 704                                   reply[0]);
 705                         ret = -EREMOTEIO;
 706                         goto out;
 707                 }
 708
 709                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 710                 case AUX_I2C_REPLY_ACK:
 711                         if (mode == MODE_I2C_READ) {
 712                                 *read_byte = reply[1];
 713                         }
 714                         ret = reply_bytes - 1;
 715                         goto out;
 716                 case AUX_I2C_REPLY_NACK:
 717                         DRM_DEBUG_KMS("aux_i2c nack\n");
 718                         ret = -EREMOTEIO;
 719                         goto out;
 720                 case AUX_I2C_REPLY_DEFER:
 721                         DRM_DEBUG_KMS("aux_i2c defer\n");
 722                         udelay(100);
 723                         break;
 724                 default:
 725                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 726                         ret = -EREMOTEIO;
 727                         goto out;
 728                 }
 729         }
 730
 731         DRM_ERROR("too many retries, giving up\n");
 732         ret = -EREMOTEIO;
 733
 734 out:
 735         ironlake_edp_panel_vdd_off(intel_dp, false);
 736         return ret;
 737 }
 738
 739 static int
 740 intel_dp_i2c_init(struct intel_dp *intel_dp,
 741                   struct intel_connector *intel_connector, const char *name)
 742 {
 743         int     ret;
 744
 745         DRM_DEBUG_KMS("i2c_init %s\n", name);
 746         intel_dp->algo.running = false;
 747         intel_dp->algo.address = 0;
 748         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 749
 750         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 751         intel_dp->adapter.owner = THIS_MODULE;
 752         intel_dp->adapter.class = I2C_CLASS_DDC;
 753         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 754         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 755         intel_dp->adapter.algo_data = &intel_dp->algo;
 756         intel_dp->adapter.dev.parent = intel_connector->base.kdev;
 757
 758         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 759         return ret;
 760 }
 761
 762 static void
 763 intel_dp_set_clock(struct intel_encoder *encoder,
 764                    struct intel_crtc_config *pipe_config, int link_bw)
 765 {
 766         struct drm_device *dev = encoder->base.dev;
 767         const struct dp_link_dpll *divisor = NULL;
 768         int i, count = 0;
 769
 770         if (IS_G4X(dev)) {
 771                 divisor = gen4_dpll;
 772                 count = ARRAY_SIZE(gen4_dpll);
 773         } else if (IS_HASWELL(dev)) {
 774                 /* Haswell has special-purpose DP DDI clocks. */
 775         } else if (HAS_PCH_SPLIT(dev)) {
 776                 divisor = pch_dpll;
 777                 count = ARRAY_SIZE(pch_dpll);
 778         } else if (IS_VALLEYVIEW(dev)) {
 779                 divisor = vlv_dpll;
 780                 count = ARRAY_SIZE(vlv_dpll);
 781         }
 782
 783         if (divisor && count) {
 784                 for (i = 0; i < count; i++) {
 785                         if (link_bw == divisor[i].link_bw) {
 786                                 pipe_config->dpll = divisor[i].dpll;
 787                                 pipe_config->clock_set = true;
 788                                 break;
 789                         }
 790                 }
 791         }
 792 }
 793
 794 bool
 795 intel_dp_compute_config(struct intel_encoder *encoder,
 796                         struct intel_crtc_config *pipe_config)
 797 {
 798         struct drm_device *dev = encoder->base.dev;
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 801         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 802         enum port port = dp_to_dig_port(intel_dp)->port;
 803         struct intel_crtc *intel_crtc = encoder->new_crtc;
 804         struct intel_connector *intel_connector = intel_dp->attached_connector;
 805         int lane_count, clock;
 806         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 807         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 808         int bpp, mode_rate;
 809         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 810         int link_avail, link_clock;
 811
 812         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 813                 pipe_config->has_pch_encoder = true;
 814
 815         pipe_config->has_dp_encoder = true;
 816
 817         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 818                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 819                                        adjusted_mode);
 820                 if (!HAS_PCH_SPLIT(dev))
 821                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 822                                                  intel_connector->panel.fitting_mode);
 823                 else
 824                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 825                                                 intel_connector->panel.fitting_mode);
 826         }
 827
 828         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 829                 return false;
 830
 831         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 832                       "max bw %02x pixel clock %iKHz\n",
 833                       max_lane_count, bws[max_clock],
 834                       adjusted_mode->crtc_clock);
 835
 836         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 837          * bpc in between. */
 838         bpp = pipe_config->pipe_bpp;
 839         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 840             dev_priv->vbt.edp_bpp < bpp) {
 841                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 842                               dev_priv->vbt.edp_bpp);
 843                 bpp = dev_priv->vbt.edp_bpp;
 844         }
 845
 846         for (; bpp >= 6*3; bpp -= 2*3) {
 847                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 848                                                    bpp);
 849
 850                 for (clock = 0; clock <= max_clock; clock++) {
 851                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 852                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 853                                 link_avail = intel_dp_max_data_rate(link_clock,
 854                                                                     lane_count);
 855
 856                                 if (mode_rate <= link_avail) {
 857                                         goto found;
 858                                 }
 859                         }
 860                 }
 861         }
 862
 863         return false;
 864
 865 found:
 866         if (intel_dp->color_range_auto) {
 867                 /*
 868                  * See:
 869                  * CEA-861-E - 5.1 Default Encoding Parameters
 870                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 871                  */
 872                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 873                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 874                 else
 875                         intel_dp->color_range = 0;
 876         }
 877
 878         if (intel_dp->color_range)
 879                 pipe_config->limited_color_range = true;
 880
 881         intel_dp->link_bw = bws[clock];
 882         intel_dp->lane_count = lane_count;
 883         pipe_config->pipe_bpp = bpp;
 884         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 885
 886         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 887                       intel_dp->link_bw, intel_dp->lane_count,
 888                       pipe_config->port_clock, bpp);
 889         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 890                       mode_rate, link_avail);
 891
 892         intel_link_compute_m_n(bpp, lane_count,
 893                                adjusted_mode->crtc_clock,
 894                                pipe_config->port_clock,
 895                                &pipe_config->dp_m_n);
 896
 897         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 898
 899         return true;
 900 }
 901
 902 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 903 {
 904         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 905         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 906         struct drm_device *dev = crtc->base.dev;
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         u32 dpa_ctl;
 909
 910         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 911         dpa_ctl = I915_READ(DP_A);
 912         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 913
 914         if (crtc->config.port_clock == 162000) {
 915                 /* For a long time we've carried around a ILK-DevA w/a for the
 916                  * 160MHz clock. If we're really unlucky, it's still required.
 917                  */
 918                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 919                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 920                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 921         } else {
 922                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 923                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 924         }
 925
 926         I915_WRITE(DP_A, dpa_ctl);
 927
 928         POSTING_READ(DP_A);
 929         udelay(500);
 930 }
 931
 932 static void intel_dp_mode_set(struct intel_encoder *encoder)
 933 {
 934         struct drm_device *dev = encoder->base.dev;
 935         struct drm_i915_private *dev_priv = dev->dev_private;
 936         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 937         enum port port = dp_to_dig_port(intel_dp)->port;
 938         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 939         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 940
 941         /*
 942          * There are four kinds of DP registers:
 943          *
 944          *      IBX PCH
 945          *      SNB CPU
 946          *      IVB CPU
 947          *      CPT PCH
 948          *
 949          * IBX PCH and CPU are the same for almost everything,
 950          * except that the CPU DP PLL is configured in this
 951          * register
 952          *
 953          * CPT PCH is quite different, having many bits moved
 954          * to the TRANS_DP_CTL register instead. That
 955          * configuration happens (oddly) in ironlake_pch_enable
 956          */
 957
 958         /* Preserve the BIOS-computed detected bit. This is
 959          * supposed to be read-only.
 960          */
 961         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 962
 963         /* Handle DP bits in common between all three register formats */
 964         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 965         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 966
 967         if (intel_dp->has_audio) {
 968                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 969                                  pipe_name(crtc->pipe));
 970                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 971                 intel_write_eld(&encoder->base, adjusted_mode);
 972         }
 973
 974         /* Split out the IBX/CPU vs CPT settings */
 975
 976         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 977                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 978                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 979                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 980                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 981                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 982
 983                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 984                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 985
 986                 intel_dp->DP |= crtc->pipe << 29;
 987         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 988                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 989                         intel_dp->DP |= intel_dp->color_range;
 990
 991                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 992                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 993                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 994                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 995                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 996
 997                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 998                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 999
1000                 if (crtc->pipe == 1)
1001                         intel_dp->DP |= DP_PIPEB_SELECT;
1002         } else {
1003                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1004         }
1005
1006         if (port == PORT_A && !IS_VALLEYVIEW(dev))
1007                 ironlake_set_pll_cpu_edp(intel_dp);
1008 }
1009
1010 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1011 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1012
1013 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1014 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1015
1016 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1017 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1018
1019 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1020                                        u32 mask,
1021                                        u32 value)
1022 {
1023         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1024         struct drm_i915_private *dev_priv = dev->dev_private;
1025         u32 pp_stat_reg, pp_ctrl_reg;
1026
1027         pp_stat_reg = _pp_stat_reg(intel_dp);
1028         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1029
1030         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1031                         mask, value,
1032                         I915_READ(pp_stat_reg),
1033                         I915_READ(pp_ctrl_reg));
1034
1035         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1036                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1037                                 I915_READ(pp_stat_reg),
1038                                 I915_READ(pp_ctrl_reg));
1039         }
1040
1041         DRM_DEBUG_KMS("Wait complete\n");
1042 }
1043
1044 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1045 {
1046         DRM_DEBUG_KMS("Wait for panel power on\n");
1047         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1048 }
1049
1050 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1051 {
1052         DRM_DEBUG_KMS("Wait for panel power off time\n");
1053         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1054 }
1055
1056 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1057 {
1058         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1059         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1060 }
1061
1062
1063 /* Read the current pp_control value, unlocking the register if it
1064  * is locked
1065  */
1066
1067 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1068 {
1069         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         u32 control;
1072
1073         control = I915_READ(_pp_ctrl_reg(intel_dp));
1074         control &= ~PANEL_UNLOCK_MASK;
1075         control |= PANEL_UNLOCK_REGS;
1076         return control;
1077 }
1078
1079 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1080 {
1081         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1082         struct drm_i915_private *dev_priv = dev->dev_private;
1083         u32 pp;
1084         u32 pp_stat_reg, pp_ctrl_reg;
1085
1086         if (!is_edp(intel_dp))
1087                 return;
1088
1089         WARN(intel_dp->want_panel_vdd,
1090              "eDP VDD already requested on\n");
1091
1092         intel_dp->want_panel_vdd = true;
1093
1094         if (ironlake_edp_have_panel_vdd(intel_dp))
1095                 return;
1096
1097         intel_runtime_pm_get(dev_priv);
1098
1099         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1100
1101         if (!ironlake_edp_have_panel_power(intel_dp))
1102                 ironlake_wait_panel_power_cycle(intel_dp);
1103
1104         pp = ironlake_get_pp_control(intel_dp);
1105         pp |= EDP_FORCE_VDD;
1106
1107         pp_stat_reg = _pp_stat_reg(intel_dp);
1108         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1109
1110         I915_WRITE(pp_ctrl_reg, pp);
1111         POSTING_READ(pp_ctrl_reg);
1112         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1113                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1114         /*
1115          * If the panel wasn't on, delay before accessing aux channel
1116          */
1117         if (!ironlake_edp_have_panel_power(intel_dp)) {
1118                 DRM_DEBUG_KMS("eDP was not running\n");
1119                 msleep(intel_dp->panel_power_up_delay);
1120         }
1121 }
1122
1123 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1124 {
1125         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1126         struct drm_i915_private *dev_priv = dev->dev_private;
1127         u32 pp;
1128         u32 pp_stat_reg, pp_ctrl_reg;
1129
1130         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1131
1132         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1133                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1134
1135                 pp = ironlake_get_pp_control(intel_dp);
1136                 pp &= ~EDP_FORCE_VDD;
1137
1138                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1139                 pp_stat_reg = _pp_stat_reg(intel_dp);
1140
1141                 I915_WRITE(pp_ctrl_reg, pp);
1142                 POSTING_READ(pp_ctrl_reg);
1143
1144                 /* Make sure sequencer is idle before allowing subsequent activity */
1145                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1146                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1147
1148                 if ((pp & POWER_TARGET_ON) == 0)
1149                         msleep(intel_dp->panel_power_cycle_delay);
1150
1151                 intel_runtime_pm_put(dev_priv);
1152         }
1153 }
1154
1155 static void ironlake_panel_vdd_work(struct work_struct *__work)
1156 {
1157         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1158                                                  struct intel_dp, panel_vdd_work);
1159         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1160
1161         mutex_lock(&dev->mode_config.mutex);
1162         ironlake_panel_vdd_off_sync(intel_dp);
1163         mutex_unlock(&dev->mode_config.mutex);
1164 }
1165
1166 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1167 {
1168         if (!is_edp(intel_dp))
1169                 return;
1170
1171         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1172
1173         intel_dp->want_panel_vdd = false;
1174
1175         if (sync) {
1176                 ironlake_panel_vdd_off_sync(intel_dp);
1177         } else {
1178                 /*
1179                  * Queue the timer to fire a long
1180                  * time from now (relative to the power down delay)
1181                  * to keep the panel power up across a sequence of operations
1182                  */
1183                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1184                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1185         }
1186 }
1187
1188 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1189 {
1190         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1191         struct drm_i915_private *dev_priv = dev->dev_private;
1192         u32 pp;
1193         u32 pp_ctrl_reg;
1194
1195         if (!is_edp(intel_dp))
1196                 return;
1197
1198         DRM_DEBUG_KMS("Turn eDP power on\n");
1199
1200         if (ironlake_edp_have_panel_power(intel_dp)) {
1201                 DRM_DEBUG_KMS("eDP power already on\n");
1202                 return;
1203         }
1204
1205         ironlake_wait_panel_power_cycle(intel_dp);
1206
1207         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1208         pp = ironlake_get_pp_control(intel_dp);
1209         if (IS_GEN5(dev)) {
1210                 /* ILK workaround: disable reset around power sequence */
1211                 pp &= ~PANEL_POWER_RESET;
1212                 I915_WRITE(pp_ctrl_reg, pp);
1213                 POSTING_READ(pp_ctrl_reg);
1214         }
1215
1216         pp |= POWER_TARGET_ON;
1217         if (!IS_GEN5(dev))
1218                 pp |= PANEL_POWER_RESET;
1219
1220         I915_WRITE(pp_ctrl_reg, pp);
1221         POSTING_READ(pp_ctrl_reg);
1222
1223         ironlake_wait_panel_on(intel_dp);
1224
1225         if (IS_GEN5(dev)) {
1226                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1227                 I915_WRITE(pp_ctrl_reg, pp);
1228                 POSTING_READ(pp_ctrl_reg);
1229         }
1230 }
1231
1232 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1233 {
1234         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1235         struct drm_i915_private *dev_priv = dev->dev_private;
1236         u32 pp;
1237         u32 pp_ctrl_reg;
1238
1239         if (!is_edp(intel_dp))
1240                 return;
1241
1242         DRM_DEBUG_KMS("Turn eDP power off\n");
1243
1244         pp = ironlake_get_pp_control(intel_dp);
1245         /* We need to switch off panel power _and_ force vdd, for otherwise some
1246          * panels get very unhappy and cease to work. */
1247         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1248
1249         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1250
1251         I915_WRITE(pp_ctrl_reg, pp);
1252         POSTING_READ(pp_ctrl_reg);
1253
1254         ironlake_wait_panel_off(intel_dp);
1255 }
1256
1257 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1258 {
1259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1260         struct drm_device *dev = intel_dig_port->base.base.dev;
1261         struct drm_i915_private *dev_priv = dev->dev_private;
1262         u32 pp;
1263         u32 pp_ctrl_reg;
1264
1265         if (!is_edp(intel_dp))
1266                 return;
1267
1268         DRM_DEBUG_KMS("\n");
1269         /*
1270          * If we enable the backlight right away following a panel power
1271          * on, we may see slight flicker as the panel syncs with the eDP
1272          * link.  So delay a bit to make sure the image is solid before
1273          * allowing it to appear.
1274          */
1275         msleep(intel_dp->backlight_on_delay);
1276         pp = ironlake_get_pp_control(intel_dp);
1277         pp |= EDP_BLC_ENABLE;
1278
1279         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1280
1281         I915_WRITE(pp_ctrl_reg, pp);
1282         POSTING_READ(pp_ctrl_reg);
1283
1284         intel_panel_enable_backlight(intel_dp->attached_connector);
1285 }
1286
1287 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1288 {
1289         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         u32 pp;
1292         u32 pp_ctrl_reg;
1293
1294         if (!is_edp(intel_dp))
1295                 return;
1296
1297         intel_panel_disable_backlight(intel_dp->attached_connector);
1298
1299         DRM_DEBUG_KMS("\n");
1300         pp = ironlake_get_pp_control(intel_dp);
1301         pp &= ~EDP_BLC_ENABLE;
1302
1303         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1304
1305         I915_WRITE(pp_ctrl_reg, pp);
1306         POSTING_READ(pp_ctrl_reg);
1307         msleep(intel_dp->backlight_off_delay);
1308 }
1309
1310 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1311 {
1312         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1313         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1314         struct drm_device *dev = crtc->dev;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         u32 dpa_ctl;
1317
1318         assert_pipe_disabled(dev_priv,
1319                              to_intel_crtc(crtc)->pipe);
1320
1321         DRM_DEBUG_KMS("\n");
1322         dpa_ctl = I915_READ(DP_A);
1323         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1324         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1325
1326         /* We don't adjust intel_dp->DP while tearing down the link, to
1327          * facilitate link retraining (e.g. after hotplug). Hence clear all
1328          * enable bits here to ensure that we don't enable too much. */
1329         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1330         intel_dp->DP |= DP_PLL_ENABLE;
1331         I915_WRITE(DP_A, intel_dp->DP);
1332         POSTING_READ(DP_A);
1333         udelay(200);
1334 }
1335
1336 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1337 {
1338         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1339         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1340         struct drm_device *dev = crtc->dev;
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342         u32 dpa_ctl;
1343
1344         assert_pipe_disabled(dev_priv,
1345                              to_intel_crtc(crtc)->pipe);
1346
1347         dpa_ctl = I915_READ(DP_A);
1348         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1349              "dp pll off, should be on\n");
1350         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1351
1352         /* We can't rely on the value tracked for the DP register in
1353          * intel_dp->DP because link_down must not change that (otherwise link
1354          * re-training will fail. */
1355         dpa_ctl &= ~DP_PLL_ENABLE;
1356         I915_WRITE(DP_A, dpa_ctl);
1357         POSTING_READ(DP_A);
1358         udelay(200);
1359 }
1360
1361 /* If the sink supports it, try to set the power state appropriately */
1362 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1363 {
1364         int ret, i;
1365
1366         /* Should have a valid DPCD by this point */
1367         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1368                 return;
1369
1370         if (mode != DRM_MODE_DPMS_ON) {
1371                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1372                                                   DP_SET_POWER_D3);
1373                 if (ret != 1)
1374                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1375         } else {
1376                 /*
1377                  * When turning on, we need to retry for 1ms to give the sink
1378                  * time to wake up.
1379                  */
1380                 for (i = 0; i < 3; i++) {
1381                         ret = intel_dp_aux_native_write_1(intel_dp,
1382                                                           DP_SET_POWER,
1383                                                           DP_SET_POWER_D0);
1384                         if (ret == 1)
1385                                 break;
1386                         msleep(1);
1387                 }
1388         }
1389 }
1390
1391 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1392                                   enum pipe *pipe)
1393 {
1394         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1395         enum port port = dp_to_dig_port(intel_dp)->port;
1396         struct drm_device *dev = encoder->base.dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         u32 tmp = I915_READ(intel_dp->output_reg);
1399
1400         if (!(tmp & DP_PORT_EN))
1401                 return false;
1402
1403         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1404                 *pipe = PORT_TO_PIPE_CPT(tmp);
1405         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1406                 *pipe = PORT_TO_PIPE(tmp);
1407         } else {
1408                 u32 trans_sel;
1409                 u32 trans_dp;
1410                 int i;
1411
1412                 switch (intel_dp->output_reg) {
1413                 case PCH_DP_B:
1414                         trans_sel = TRANS_DP_PORT_SEL_B;
1415                         break;
1416                 case PCH_DP_C:
1417                         trans_sel = TRANS_DP_PORT_SEL_C;
1418                         break;
1419                 case PCH_DP_D:
1420                         trans_sel = TRANS_DP_PORT_SEL_D;
1421                         break;
1422                 default:
1423                         return true;
1424                 }
1425
1426                 for_each_pipe(i) {
1427                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1428                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1429                                 *pipe = i;
1430                                 return true;
1431                         }
1432                 }
1433
1434                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1435                               intel_dp->output_reg);
1436         }
1437
1438         return true;
1439 }
1440
1441 static void intel_dp_get_config(struct intel_encoder *encoder,
1442                                 struct intel_crtc_config *pipe_config)
1443 {
1444         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1445         u32 tmp, flags = 0;
1446         struct drm_device *dev = encoder->base.dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         enum port port = dp_to_dig_port(intel_dp)->port;
1449         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1450         int dotclock;
1451
1452         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1453                 tmp = I915_READ(intel_dp->output_reg);
1454                 if (tmp & DP_SYNC_HS_HIGH)
1455                         flags |= DRM_MODE_FLAG_PHSYNC;
1456                 else
1457                         flags |= DRM_MODE_FLAG_NHSYNC;
1458
1459                 if (tmp & DP_SYNC_VS_HIGH)
1460                         flags |= DRM_MODE_FLAG_PVSYNC;
1461                 else
1462                         flags |= DRM_MODE_FLAG_NVSYNC;
1463         } else {
1464                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1465                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1466                         flags |= DRM_MODE_FLAG_PHSYNC;
1467                 else
1468                         flags |= DRM_MODE_FLAG_NHSYNC;
1469
1470                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1471                         flags |= DRM_MODE_FLAG_PVSYNC;
1472                 else
1473                         flags |= DRM_MODE_FLAG_NVSYNC;
1474         }
1475
1476         pipe_config->adjusted_mode.flags |= flags;
1477
1478         pipe_config->has_dp_encoder = true;
1479
1480         intel_dp_get_m_n(crtc, pipe_config);
1481
1482         if (port == PORT_A) {
1483                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1484                         pipe_config->port_clock = 162000;
1485                 else
1486                         pipe_config->port_clock = 270000;
1487         }
1488
1489         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1490                                             &pipe_config->dp_m_n);
1491
1492         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1493                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1494
1495         pipe_config->adjusted_mode.crtc_clock = dotclock;
1496
1497         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1498             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1499                 /*
1500                  * This is a big fat ugly hack.
1501                  *
1502                  * Some machines in UEFI boot mode provide us a VBT that has 18
1503                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1504                  * unknown we fail to light up. Yet the same BIOS boots up with
1505                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1506                  * max, not what it tells us to use.
1507                  *
1508                  * Note: This will still be broken if the eDP panel is not lit
1509                  * up by the BIOS, and thus we can't get the mode at module
1510                  * load.
1511                  */
1512                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1513                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1514                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1515         }
1516 }
1517
1518 static bool is_edp_psr(struct drm_device *dev)
1519 {
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521
1522         return dev_priv->psr.sink_support;
1523 }
1524
1525 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1526 {
1527         struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529         if (!HAS_PSR(dev))
1530                 return false;
1531
1532         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1533 }
1534
1535 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1536                                     struct edp_vsc_psr *vsc_psr)
1537 {
1538         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1539         struct drm_device *dev = dig_port->base.base.dev;
1540         struct drm_i915_private *dev_priv = dev->dev_private;
1541         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1542         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1543         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1544         uint32_t *data = (uint32_t *) vsc_psr;
1545         unsigned int i;
1546
1547         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1548            the video DIP being updated before program video DIP data buffer
1549            registers for DIP being updated. */
1550         I915_WRITE(ctl_reg, 0);
1551         POSTING_READ(ctl_reg);
1552
1553         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1554                 if (i < sizeof(struct edp_vsc_psr))
1555                         I915_WRITE(data_reg + i, *data++);
1556                 else
1557                         I915_WRITE(data_reg + i, 0);
1558         }
1559
1560         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1561         POSTING_READ(ctl_reg);
1562 }
1563
1564 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1565 {
1566         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         struct edp_vsc_psr psr_vsc;
1569
1570         if (intel_dp->psr_setup_done)
1571                 return;
1572
1573         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1574         memset(&psr_vsc, 0, sizeof(psr_vsc));
1575         psr_vsc.sdp_header.HB0 = 0;
1576         psr_vsc.sdp_header.HB1 = 0x7;
1577         psr_vsc.sdp_header.HB2 = 0x2;
1578         psr_vsc.sdp_header.HB3 = 0x8;
1579         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1580
1581         /* Avoid continuous PSR exit by masking memup and hpd */
1582         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1583                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1584
1585         intel_dp->psr_setup_done = true;
1586 }
1587
1588 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1589 {
1590         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1591         struct drm_i915_private *dev_priv = dev->dev_private;
1592         uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1593         int precharge = 0x3;
1594         int msg_size = 5;       /* Header(4) + Message(1) */
1595
1596         /* Enable PSR in sink */
1597         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1598                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1599                                             DP_PSR_ENABLE &
1600                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1601         else
1602                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1603                                             DP_PSR_ENABLE |
1604                                             DP_PSR_MAIN_LINK_ACTIVE);
1605
1606         /* Setup AUX registers */
1607         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1608         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1609         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1610                    DP_AUX_CH_CTL_TIME_OUT_400us |
1611                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1612                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1613                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1614 }
1615
1616 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1617 {
1618         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1619         struct drm_i915_private *dev_priv = dev->dev_private;
1620         uint32_t max_sleep_time = 0x1f;
1621         uint32_t idle_frames = 1;
1622         uint32_t val = 0x0;
1623         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1624
1625         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1626                 val |= EDP_PSR_LINK_STANDBY;
1627                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1628                 val |= EDP_PSR_TP1_TIME_0us;
1629                 val |= EDP_PSR_SKIP_AUX_EXIT;
1630         } else
1631                 val |= EDP_PSR_LINK_DISABLE;
1632
1633         I915_WRITE(EDP_PSR_CTL(dev), val |
1634                    IS_BROADWELL(dev) ? 0 : link_entry_time |
1635                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1636                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1637                    EDP_PSR_ENABLE);
1638 }
1639
1640 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1641 {
1642         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1643         struct drm_device *dev = dig_port->base.base.dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         struct drm_crtc *crtc = dig_port->base.base.crtc;
1646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1647         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1648         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1649
1650         dev_priv->psr.source_ok = false;
1651
1652         if (!HAS_PSR(dev)) {
1653                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1654                 return false;
1655         }
1656
1657         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1658             (dig_port->port != PORT_A)) {
1659                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1660                 return false;
1661         }
1662
1663         if (!i915_enable_psr) {
1664                 DRM_DEBUG_KMS("PSR disable by flag\n");
1665                 return false;
1666         }
1667
1668         crtc = dig_port->base.base.crtc;
1669         if (crtc == NULL) {
1670                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1671                 return false;
1672         }
1673
1674         intel_crtc = to_intel_crtc(crtc);
1675         if (!intel_crtc_active(crtc)) {
1676                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1677                 return false;
1678         }
1679
1680         obj = to_intel_framebuffer(crtc->fb)->obj;
1681         if (obj->tiling_mode != I915_TILING_X ||
1682             obj->fence_reg == I915_FENCE_REG_NONE) {
1683                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1684                 return false;
1685         }
1686
1687         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1688                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1689                 return false;
1690         }
1691
1692         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1693             S3D_ENABLE) {
1694                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1695                 return false;
1696         }
1697
1698         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1699                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1700                 return false;
1701         }
1702
1703         dev_priv->psr.source_ok = true;
1704         return true;
1705 }
1706
1707 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1708 {
1709         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1710
1711         if (!intel_edp_psr_match_conditions(intel_dp) ||
1712             intel_edp_is_psr_enabled(dev))
1713                 return;
1714
1715         /* Setup PSR once */
1716         intel_edp_psr_setup(intel_dp);
1717
1718         /* Enable PSR on the panel */
1719         intel_edp_psr_enable_sink(intel_dp);
1720
1721         /* Enable PSR on the host */
1722         intel_edp_psr_enable_source(intel_dp);
1723 }
1724
1725 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1726 {
1727         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1728
1729         if (intel_edp_psr_match_conditions(intel_dp) &&
1730             !intel_edp_is_psr_enabled(dev))
1731                 intel_edp_psr_do_enable(intel_dp);
1732 }
1733
1734 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1735 {
1736         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1737         struct drm_i915_private *dev_priv = dev->dev_private;
1738
1739         if (!intel_edp_is_psr_enabled(dev))
1740                 return;
1741
1742         I915_WRITE(EDP_PSR_CTL(dev),
1743                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1744
1745         /* Wait till PSR is idle */
1746         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1747                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1748                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1749 }
1750
1751 void intel_edp_psr_update(struct drm_device *dev)
1752 {
1753         struct intel_encoder *encoder;
1754         struct intel_dp *intel_dp = NULL;
1755
1756         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1757                 if (encoder->type == INTEL_OUTPUT_EDP) {
1758                         intel_dp = enc_to_intel_dp(&encoder->base);
1759
1760                         if (!is_edp_psr(dev))
1761                                 return;
1762
1763                         if (!intel_edp_psr_match_conditions(intel_dp))
1764                                 intel_edp_psr_disable(intel_dp);
1765                         else
1766                                 if (!intel_edp_is_psr_enabled(dev))
1767                                         intel_edp_psr_do_enable(intel_dp);
1768                 }
1769 }
1770
1771 static void intel_disable_dp(struct intel_encoder *encoder)
1772 {
1773         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1774         enum port port = dp_to_dig_port(intel_dp)->port;
1775         struct drm_device *dev = encoder->base.dev;
1776
1777         /* Make sure the panel is off before trying to change the mode. But also
1778          * ensure that we have vdd while we switch off the panel. */
1779         ironlake_edp_backlight_off(intel_dp);
1780         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1781         ironlake_edp_panel_off(intel_dp);
1782
1783         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1784         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1785                 intel_dp_link_down(intel_dp);
1786 }
1787
1788 static void intel_post_disable_dp(struct intel_encoder *encoder)
1789 {
1790         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1791         enum port port = dp_to_dig_port(intel_dp)->port;
1792         struct drm_device *dev = encoder->base.dev;
1793
1794         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1795                 intel_dp_link_down(intel_dp);
1796                 if (!IS_VALLEYVIEW(dev))
1797                         ironlake_edp_pll_off(intel_dp);
1798         }
1799 }
1800
1801 static void intel_enable_dp(struct intel_encoder *encoder)
1802 {
1803         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1804         struct drm_device *dev = encoder->base.dev;
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1807
1808         if (WARN_ON(dp_reg & DP_PORT_EN))
1809                 return;
1810
1811         ironlake_edp_panel_vdd_on(intel_dp);
1812         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1813         intel_dp_start_link_train(intel_dp);
1814         ironlake_edp_panel_on(intel_dp);
1815         ironlake_edp_panel_vdd_off(intel_dp, true);
1816         intel_dp_complete_link_train(intel_dp);
1817         intel_dp_stop_link_train(intel_dp);
1818 }
1819
1820 static void g4x_enable_dp(struct intel_encoder *encoder)
1821 {
1822         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1823
1824         intel_enable_dp(encoder);
1825         ironlake_edp_backlight_on(intel_dp);
1826 }
1827
1828 static void vlv_enable_dp(struct intel_encoder *encoder)
1829 {
1830         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1831
1832         ironlake_edp_backlight_on(intel_dp);
1833 }
1834
1835 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1836 {
1837         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1838         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1839
1840         if (dport->port == PORT_A)
1841                 ironlake_edp_pll_on(intel_dp);
1842 }
1843
1844 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1845 {
1846         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1847         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1848         struct drm_device *dev = encoder->base.dev;
1849         struct drm_i915_private *dev_priv = dev->dev_private;
1850         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1851         enum dpio_channel port = vlv_dport_to_channel(dport);
1852         int pipe = intel_crtc->pipe;
1853         struct edp_power_seq power_seq;
1854         u32 val;
1855
1856         mutex_lock(&dev_priv->dpio_lock);
1857
1858         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1859         val = 0;
1860         if (pipe)
1861                 val |= (1<<21);
1862         else
1863                 val &= ~(1<<21);
1864         val |= 0x001000c4;
1865         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1866         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1867         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1868
1869         mutex_unlock(&dev_priv->dpio_lock);
1870
1871         /* init power sequencer on this pipe and port */
1872         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1873         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1874                                                       &power_seq);
1875
1876         intel_enable_dp(encoder);
1877
1878         vlv_wait_port_ready(dev_priv, dport);
1879 }
1880
1881 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1882 {
1883         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1884         struct drm_device *dev = encoder->base.dev;
1885         struct drm_i915_private *dev_priv = dev->dev_private;
1886         struct intel_crtc *intel_crtc =
1887                 to_intel_crtc(encoder->base.crtc);
1888         enum dpio_channel port = vlv_dport_to_channel(dport);
1889         int pipe = intel_crtc->pipe;
1890
1891         /* Program Tx lane resets to default */
1892         mutex_lock(&dev_priv->dpio_lock);
1893         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1894                          DPIO_PCS_TX_LANE2_RESET |
1895                          DPIO_PCS_TX_LANE1_RESET);
1896         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1897                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1898                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1899                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1900                                  DPIO_PCS_CLK_SOFT_RESET);
1901
1902         /* Fix up inter-pair skew failure */
1903         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1904         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1905         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1906         mutex_unlock(&dev_priv->dpio_lock);
1907 }
1908
1909 /*
1910  * Native read with retry for link status and receiver capability reads for
1911  * cases where the sink may still be asleep.
1912  */
1913 static bool
1914 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1915                                uint8_t *recv, int recv_bytes)
1916 {
1917         int ret, i;
1918
1919         /*
1920          * Sinks are *supposed* to come up within 1ms from an off state,
1921          * but we're also supposed to retry 3 times per the spec.
1922          */
1923         for (i = 0; i < 3; i++) {
1924                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1925                                                recv_bytes);
1926                 if (ret == recv_bytes)
1927                         return true;
1928                 msleep(1);
1929         }
1930
1931         return false;
1932 }
1933
1934 /*
1935  * Fetch AUX CH registers 0x202 - 0x207 which contain
1936  * link status information
1937  */
1938 static bool
1939 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1940 {
1941         return intel_dp_aux_native_read_retry(intel_dp,
1942                                               DP_LANE0_1_STATUS,
1943                                               link_status,
1944                                               DP_LINK_STATUS_SIZE);
1945 }
1946
1947 /*
1948  * These are source-specific values; current Intel hardware supports
1949  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1950  */
1951
1952 static uint8_t
1953 intel_dp_voltage_max(struct intel_dp *intel_dp)
1954 {
1955         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1956         enum port port = dp_to_dig_port(intel_dp)->port;
1957
1958         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1959                 return DP_TRAIN_VOLTAGE_SWING_1200;
1960         else if (IS_GEN7(dev) && port == PORT_A)
1961                 return DP_TRAIN_VOLTAGE_SWING_800;
1962         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1963                 return DP_TRAIN_VOLTAGE_SWING_1200;
1964         else
1965                 return DP_TRAIN_VOLTAGE_SWING_800;
1966 }
1967
1968 static uint8_t
1969 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1970 {
1971         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1972         enum port port = dp_to_dig_port(intel_dp)->port;
1973
1974         if (IS_BROADWELL(dev)) {
1975                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1976                 case DP_TRAIN_VOLTAGE_SWING_400:
1977                 case DP_TRAIN_VOLTAGE_SWING_600:
1978                         return DP_TRAIN_PRE_EMPHASIS_6;
1979                 case DP_TRAIN_VOLTAGE_SWING_800:
1980                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1981                 case DP_TRAIN_VOLTAGE_SWING_1200:
1982                 default:
1983                         return DP_TRAIN_PRE_EMPHASIS_0;
1984                 }
1985         } else if (IS_HASWELL(dev)) {
1986                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1987                 case DP_TRAIN_VOLTAGE_SWING_400:
1988                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1989                 case DP_TRAIN_VOLTAGE_SWING_600:
1990                         return DP_TRAIN_PRE_EMPHASIS_6;
1991                 case DP_TRAIN_VOLTAGE_SWING_800:
1992                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1993                 case DP_TRAIN_VOLTAGE_SWING_1200:
1994                 default:
1995                         return DP_TRAIN_PRE_EMPHASIS_0;
1996                 }
1997         } else if (IS_VALLEYVIEW(dev)) {
1998                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1999                 case DP_TRAIN_VOLTAGE_SWING_400:
2000                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2001                 case DP_TRAIN_VOLTAGE_SWING_600:
2002                         return DP_TRAIN_PRE_EMPHASIS_6;
2003                 case DP_TRAIN_VOLTAGE_SWING_800:
2004                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2005                 case DP_TRAIN_VOLTAGE_SWING_1200:
2006                 default:
2007                         return DP_TRAIN_PRE_EMPHASIS_0;
2008                 }
2009         } else if (IS_GEN7(dev) && port == PORT_A) {
2010                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2011                 case DP_TRAIN_VOLTAGE_SWING_400:
2012                         return DP_TRAIN_PRE_EMPHASIS_6;
2013                 case DP_TRAIN_VOLTAGE_SWING_600:
2014                 case DP_TRAIN_VOLTAGE_SWING_800:
2015                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2016                 default:
2017                         return DP_TRAIN_PRE_EMPHASIS_0;
2018                 }
2019         } else {
2020                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2021                 case DP_TRAIN_VOLTAGE_SWING_400:
2022                         return DP_TRAIN_PRE_EMPHASIS_6;
2023                 case DP_TRAIN_VOLTAGE_SWING_600:
2024                         return DP_TRAIN_PRE_EMPHASIS_6;
2025                 case DP_TRAIN_VOLTAGE_SWING_800:
2026                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2027                 case DP_TRAIN_VOLTAGE_SWING_1200:
2028                 default:
2029                         return DP_TRAIN_PRE_EMPHASIS_0;
2030                 }
2031         }
2032 }
2033
2034 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2035 {
2036         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2037         struct drm_i915_private *dev_priv = dev->dev_private;
2038         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2039         struct intel_crtc *intel_crtc =
2040                 to_intel_crtc(dport->base.base.crtc);
2041         unsigned long demph_reg_value, preemph_reg_value,
2042                 uniqtranscale_reg_value;
2043         uint8_t train_set = intel_dp->train_set[0];
2044         enum dpio_channel port = vlv_dport_to_channel(dport);
2045         int pipe = intel_crtc->pipe;
2046
2047         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2048         case DP_TRAIN_PRE_EMPHASIS_0:
2049                 preemph_reg_value = 0x0004000;
2050                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2051                 case DP_TRAIN_VOLTAGE_SWING_400:
2052                         demph_reg_value = 0x2B405555;
2053                         uniqtranscale_reg_value = 0x552AB83A;
2054                         break;
2055                 case DP_TRAIN_VOLTAGE_SWING_600:
2056                         demph_reg_value = 0x2B404040;
2057                         uniqtranscale_reg_value = 0x5548B83A;
2058                         break;
2059                 case DP_TRAIN_VOLTAGE_SWING_800:
2060                         demph_reg_value = 0x2B245555;
2061                         uniqtranscale_reg_value = 0x5560B83A;
2062                         break;
2063                 case DP_TRAIN_VOLTAGE_SWING_1200:
2064                         demph_reg_value = 0x2B405555;
2065                         uniqtranscale_reg_value = 0x5598DA3A;
2066                         break;
2067                 default:
2068                         return 0;
2069                 }
2070                 break;
2071         case DP_TRAIN_PRE_EMPHASIS_3_5:
2072                 preemph_reg_value = 0x0002000;
2073                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2074                 case DP_TRAIN_VOLTAGE_SWING_400:
2075                         demph_reg_value = 0x2B404040;
2076                         uniqtranscale_reg_value = 0x5552B83A;
2077                         break;
2078                 case DP_TRAIN_VOLTAGE_SWING_600:
2079                         demph_reg_value = 0x2B404848;
2080                         uniqtranscale_reg_value = 0x5580B83A;
2081                         break;
2082                 case DP_TRAIN_VOLTAGE_SWING_800:
2083                         demph_reg_value = 0x2B404040;
2084                         uniqtranscale_reg_value = 0x55ADDA3A;
2085                         break;
2086                 default:
2087                         return 0;
2088                 }
2089                 break;
2090         case DP_TRAIN_PRE_EMPHASIS_6:
2091                 preemph_reg_value = 0x0000000;
2092                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2093                 case DP_TRAIN_VOLTAGE_SWING_400:
2094                         demph_reg_value = 0x2B305555;
2095                         uniqtranscale_reg_value = 0x5570B83A;
2096                         break;
2097                 case DP_TRAIN_VOLTAGE_SWING_600:
2098                         demph_reg_value = 0x2B2B4040;
2099                         uniqtranscale_reg_value = 0x55ADDA3A;
2100                         break;
2101                 default:
2102                         return 0;
2103                 }
2104                 break;
2105         case DP_TRAIN_PRE_EMPHASIS_9_5:
2106                 preemph_reg_value = 0x0006000;
2107                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2108                 case DP_TRAIN_VOLTAGE_SWING_400:
2109                         demph_reg_value = 0x1B405555;
2110                         uniqtranscale_reg_value = 0x55ADDA3A;
2111                         break;
2112                 default:
2113                         return 0;
2114                 }
2115                 break;
2116         default:
2117                 return 0;
2118         }
2119
2120         mutex_lock(&dev_priv->dpio_lock);
2121         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2122         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2123         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2124                          uniqtranscale_reg_value);
2125         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2126         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2127         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2128         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2129         mutex_unlock(&dev_priv->dpio_lock);
2130
2131         return 0;
2132 }
2133
2134 static void
2135 intel_get_adjust_train(struct intel_dp *intel_dp,
2136                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2137 {
2138         uint8_t v = 0;
2139         uint8_t p = 0;
2140         int lane;
2141         uint8_t voltage_max;
2142         uint8_t preemph_max;
2143
2144         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2145                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2146                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2147
2148                 if (this_v > v)
2149                         v = this_v;
2150                 if (this_p > p)
2151                         p = this_p;
2152         }
2153
2154         voltage_max = intel_dp_voltage_max(intel_dp);
2155         if (v >= voltage_max)
2156                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2157
2158         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2159         if (p >= preemph_max)
2160                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2161
2162         for (lane = 0; lane < 4; lane++)
2163                 intel_dp->train_set[lane] = v | p;
2164 }
2165
2166 static uint32_t
2167 intel_gen4_signal_levels(uint8_t train_set)
2168 {
2169         uint32_t        signal_levels = 0;
2170
2171         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2172         case DP_TRAIN_VOLTAGE_SWING_400:
2173         default:
2174                 signal_levels |= DP_VOLTAGE_0_4;
2175                 break;
2176         case DP_TRAIN_VOLTAGE_SWING_600:
2177                 signal_levels |= DP_VOLTAGE_0_6;
2178                 break;
2179         case DP_TRAIN_VOLTAGE_SWING_800:
2180                 signal_levels |= DP_VOLTAGE_0_8;
2181                 break;
2182         case DP_TRAIN_VOLTAGE_SWING_1200:
2183                 signal_levels |= DP_VOLTAGE_1_2;
2184                 break;
2185         }
2186         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2187         case DP_TRAIN_PRE_EMPHASIS_0:
2188         default:
2189                 signal_levels |= DP_PRE_EMPHASIS_0;
2190                 break;
2191         case DP_TRAIN_PRE_EMPHASIS_3_5:
2192                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2193                 break;
2194         case DP_TRAIN_PRE_EMPHASIS_6:
2195                 signal_levels |= DP_PRE_EMPHASIS_6;
2196                 break;
2197         case DP_TRAIN_PRE_EMPHASIS_9_5:
2198                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2199                 break;
2200         }
2201         return signal_levels;
2202 }
2203
2204 /* Gen6's DP voltage swing and pre-emphasis control */
2205 static uint32_t
2206 intel_gen6_edp_signal_levels(uint8_t train_set)
2207 {
2208         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2209                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2210         switch (signal_levels) {
2211         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2212         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2213                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2214         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2215                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2216         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2217         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2218                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2219         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2220         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2221                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2222         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2223         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2224                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2225         default:
2226                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2227                               "0x%x\n", signal_levels);
2228                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2229         }
2230 }
2231
2232 /* Gen7's DP voltage swing and pre-emphasis control */
2233 static uint32_t
2234 intel_gen7_edp_signal_levels(uint8_t train_set)
2235 {
2236         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2237                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2238         switch (signal_levels) {
2239         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2240                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2241         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2242                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2243         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2244                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2245
2246         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2247                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2248         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2249                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2250
2251         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2252                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2253         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2254                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2255
2256         default:
2257                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2258                               "0x%x\n", signal_levels);
2259                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2260         }
2261 }
2262
2263 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2264 static uint32_t
2265 intel_hsw_signal_levels(uint8_t train_set)
2266 {
2267         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2268                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2269         switch (signal_levels) {
2270         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2271                 return DDI_BUF_EMP_400MV_0DB_HSW;
2272         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2273                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2274         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2275                 return DDI_BUF_EMP_400MV_6DB_HSW;
2276         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2277                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2278
2279         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2280                 return DDI_BUF_EMP_600MV_0DB_HSW;
2281         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2282                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2283         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2284                 return DDI_BUF_EMP_600MV_6DB_HSW;
2285
2286         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2287                 return DDI_BUF_EMP_800MV_0DB_HSW;
2288         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2289                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2290         default:
2291                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2292                               "0x%x\n", signal_levels);
2293                 return DDI_BUF_EMP_400MV_0DB_HSW;
2294         }
2295 }
2296
2297 static uint32_t
2298 intel_bdw_signal_levels(uint8_t train_set)
2299 {
2300         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2301                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2302         switch (signal_levels) {
2303         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2304                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2305         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2306                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2307         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2308                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2309
2310         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2311                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2312         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2313                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2314         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2315                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2316
2317         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2318                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2319         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2320                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2321
2322         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2323                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2324
2325         default:
2326                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2327                               "0x%x\n", signal_levels);
2328                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2329         }
2330 }
2331
2332 /* Properly updates "DP" with the correct signal levels. */
2333 static void
2334 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2335 {
2336         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2337         enum port port = intel_dig_port->port;
2338         struct drm_device *dev = intel_dig_port->base.base.dev;
2339         uint32_t signal_levels, mask;
2340         uint8_t train_set = intel_dp->train_set[0];
2341
2342         if (IS_BROADWELL(dev)) {
2343                 signal_levels = intel_bdw_signal_levels(train_set);
2344                 mask = DDI_BUF_EMP_MASK;
2345         } else if (IS_HASWELL(dev)) {
2346                 signal_levels = intel_hsw_signal_levels(train_set);
2347                 mask = DDI_BUF_EMP_MASK;
2348         } else if (IS_VALLEYVIEW(dev)) {
2349                 signal_levels = intel_vlv_signal_levels(intel_dp);
2350                 mask = 0;
2351         } else if (IS_GEN7(dev) && port == PORT_A) {
2352                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2353                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2354         } else if (IS_GEN6(dev) && port == PORT_A) {
2355                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2356                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2357         } else {
2358                 signal_levels = intel_gen4_signal_levels(train_set);
2359                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2360         }
2361
2362         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2363
2364         *DP = (*DP & ~mask) | signal_levels;
2365 }
2366
2367 static bool
2368 intel_dp_set_link_train(struct intel_dp *intel_dp,
2369                         uint32_t *DP,
2370                         uint8_t dp_train_pat)
2371 {
2372         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2373         struct drm_device *dev = intel_dig_port->base.base.dev;
2374         struct drm_i915_private *dev_priv = dev->dev_private;
2375         enum port port = intel_dig_port->port;
2376         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2377         int ret, len;
2378
2379         if (HAS_DDI(dev)) {
2380                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2381
2382                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2383                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2384                 else
2385                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2386
2387                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2388                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2389                 case DP_TRAINING_PATTERN_DISABLE:
2390                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2391
2392                         break;
2393                 case DP_TRAINING_PATTERN_1:
2394                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2395                         break;
2396                 case DP_TRAINING_PATTERN_2:
2397                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2398                         break;
2399                 case DP_TRAINING_PATTERN_3:
2400                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2401                         break;
2402                 }
2403                 I915_WRITE(DP_TP_CTL(port), temp);
2404
2405         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2406                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2407
2408                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2409                 case DP_TRAINING_PATTERN_DISABLE:
2410                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2411                         break;
2412                 case DP_TRAINING_PATTERN_1:
2413                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2414                         break;
2415                 case DP_TRAINING_PATTERN_2:
2416                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2417                         break;
2418                 case DP_TRAINING_PATTERN_3:
2419                         DRM_ERROR("DP training pattern 3 not supported\n");
2420                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2421                         break;
2422                 }
2423
2424         } else {
2425                 *DP &= ~DP_LINK_TRAIN_MASK;
2426
2427                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2428                 case DP_TRAINING_PATTERN_DISABLE:
2429                         *DP |= DP_LINK_TRAIN_OFF;
2430                         break;
2431                 case DP_TRAINING_PATTERN_1:
2432                         *DP |= DP_LINK_TRAIN_PAT_1;
2433                         break;
2434                 case DP_TRAINING_PATTERN_2:
2435                         *DP |= DP_LINK_TRAIN_PAT_2;
2436                         break;
2437                 case DP_TRAINING_PATTERN_3:
2438                         DRM_ERROR("DP training pattern 3 not supported\n");
2439                         *DP |= DP_LINK_TRAIN_PAT_2;
2440                         break;
2441                 }
2442         }
2443
2444         I915_WRITE(intel_dp->output_reg, *DP);
2445         POSTING_READ(intel_dp->output_reg);
2446
2447         buf[0] = dp_train_pat;
2448         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2449             DP_TRAINING_PATTERN_DISABLE) {
2450                 /* don't write DP_TRAINING_LANEx_SET on disable */
2451                 len = 1;
2452         } else {
2453                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2454                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2455                 len = intel_dp->lane_count + 1;
2456         }
2457
2458         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2459                                         buf, len);
2460
2461         return ret == len;
2462 }
2463
2464 static bool
2465 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2466                         uint8_t dp_train_pat)
2467 {
2468         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2469         intel_dp_set_signal_levels(intel_dp, DP);
2470         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2471 }
2472
2473 static bool
2474 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2475                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2476 {
2477         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2478         struct drm_device *dev = intel_dig_port->base.base.dev;
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         int ret;
2481
2482         intel_get_adjust_train(intel_dp, link_status);
2483         intel_dp_set_signal_levels(intel_dp, DP);
2484
2485         I915_WRITE(intel_dp->output_reg, *DP);
2486         POSTING_READ(intel_dp->output_reg);
2487
2488         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2489                                         intel_dp->train_set,
2490                                         intel_dp->lane_count);
2491
2492         return ret == intel_dp->lane_count;
2493 }
2494
2495 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2496 {
2497         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2498         struct drm_device *dev = intel_dig_port->base.base.dev;
2499         struct drm_i915_private *dev_priv = dev->dev_private;
2500         enum port port = intel_dig_port->port;
2501         uint32_t val;
2502
2503         if (!HAS_DDI(dev))
2504                 return;
2505
2506         val = I915_READ(DP_TP_CTL(port));
2507         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2508         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2509         I915_WRITE(DP_TP_CTL(port), val);
2510
2511         /*
2512          * On PORT_A we can have only eDP in SST mode. There the only reason
2513          * we need to set idle transmission mode is to work around a HW issue
2514          * where we enable the pipe while not in idle link-training mode.
2515          * In this case there is requirement to wait for a minimum number of
2516          * idle patterns to be sent.
2517          */
2518         if (port == PORT_A)
2519                 return;
2520
2521         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2522                      1))
2523                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2524 }
2525
2526 /* Enable corresponding port and start training pattern 1 */
2527 void
2528 intel_dp_start_link_train(struct intel_dp *intel_dp)
2529 {
2530         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2531         struct drm_device *dev = encoder->dev;
2532         int i;
2533         uint8_t voltage;
2534         int voltage_tries, loop_tries;
2535         uint32_t DP = intel_dp->DP;
2536         uint8_t link_config[2];
2537
2538         if (HAS_DDI(dev))
2539                 intel_ddi_prepare_link_retrain(encoder);
2540
2541         /* Write the link configuration data */
2542         link_config[0] = intel_dp->link_bw;
2543         link_config[1] = intel_dp->lane_count;
2544         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2545                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2546         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2547
2548         link_config[0] = 0;
2549         link_config[1] = DP_SET_ANSI_8B10B;
2550         intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2551
2552         DP |= DP_PORT_EN;
2553
2554         /* clock recovery */
2555         if (!intel_dp_reset_link_train(intel_dp, &DP,
2556                                        DP_TRAINING_PATTERN_1 |
2557                                        DP_LINK_SCRAMBLING_DISABLE)) {
2558                 DRM_ERROR("failed to enable link training\n");
2559                 return;
2560         }
2561
2562         voltage = 0xff;
2563         voltage_tries = 0;
2564         loop_tries = 0;
2565         for (;;) {
2566                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2567
2568                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2569                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2570                         DRM_ERROR("failed to get link status\n");
2571                         break;
2572                 }
2573
2574                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2575                         DRM_DEBUG_KMS("clock recovery OK\n");
2576                         break;
2577                 }
2578
2579                 /* Check to see if we've tried the max voltage */
2580                 for (i = 0; i < intel_dp->lane_count; i++)
2581                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2582                                 break;
2583                 if (i == intel_dp->lane_count) {
2584                         ++loop_tries;
2585                         if (loop_tries == 5) {
2586                                 DRM_ERROR("too many full retries, give up\n");
2587                                 break;
2588                         }
2589                         intel_dp_reset_link_train(intel_dp, &DP,
2590                                                   DP_TRAINING_PATTERN_1 |
2591                                                   DP_LINK_SCRAMBLING_DISABLE);
2592                         voltage_tries = 0;
2593                         continue;
2594                 }
2595
2596                 /* Check to see if we've tried the same voltage 5 times */
2597                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2598                         ++voltage_tries;
2599                         if (voltage_tries == 5) {
2600                                 DRM_ERROR("too many voltage retries, give up\n");
2601                                 break;
2602                         }
2603                 } else
2604                         voltage_tries = 0;
2605                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2606
2607                 /* Update training set as requested by target */
2608                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2609                         DRM_ERROR("failed to update link training\n");
2610                         break;
2611                 }
2612         }
2613
2614         intel_dp->DP = DP;
2615 }
2616
2617 void
2618 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2619 {
2620         bool channel_eq = false;
2621         int tries, cr_tries;
2622         uint32_t DP = intel_dp->DP;
2623
2624         /* channel equalization */
2625         if (!intel_dp_set_link_train(intel_dp, &DP,
2626                                      DP_TRAINING_PATTERN_2 |
2627                                      DP_LINK_SCRAMBLING_DISABLE)) {
2628                 DRM_ERROR("failed to start channel equalization\n");
2629                 return;
2630         }
2631
2632         tries = 0;
2633         cr_tries = 0;
2634         channel_eq = false;
2635         for (;;) {
2636                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2637
2638                 if (cr_tries > 5) {
2639                         DRM_ERROR("failed to train DP, aborting\n");
2640                         intel_dp_link_down(intel_dp);
2641                         break;
2642                 }
2643
2644                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2645                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2646                         DRM_ERROR("failed to get link status\n");
2647                         break;
2648                 }
2649
2650                 /* Make sure clock is still ok */
2651                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2652                         intel_dp_start_link_train(intel_dp);
2653                         intel_dp_set_link_train(intel_dp, &DP,
2654                                                 DP_TRAINING_PATTERN_2 |
2655                                                 DP_LINK_SCRAMBLING_DISABLE);
2656                         cr_tries++;
2657                         continue;
2658                 }
2659
2660                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2661                         channel_eq = true;
2662                         break;
2663                 }
2664
2665                 /* Try 5 times, then try clock recovery if that fails */
2666                 if (tries > 5) {
2667                         intel_dp_link_down(intel_dp);
2668                         intel_dp_start_link_train(intel_dp);
2669                         intel_dp_set_link_train(intel_dp, &DP,
2670                                                 DP_TRAINING_PATTERN_2 |
2671                                                 DP_LINK_SCRAMBLING_DISABLE);
2672                         tries = 0;
2673                         cr_tries++;
2674                         continue;
2675                 }
2676
2677                 /* Update training set as requested by target */
2678                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2679                         DRM_ERROR("failed to update link training\n");
2680                         break;
2681                 }
2682                 ++tries;
2683         }
2684
2685         intel_dp_set_idle_link_train(intel_dp);
2686
2687         intel_dp->DP = DP;
2688
2689         if (channel_eq)
2690                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2691
2692 }
2693
2694 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2695 {
2696         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2697                                 DP_TRAINING_PATTERN_DISABLE);
2698 }
2699
2700 static void
2701 intel_dp_link_down(struct intel_dp *intel_dp)
2702 {
2703         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2704         enum port port = intel_dig_port->port;
2705         struct drm_device *dev = intel_dig_port->base.base.dev;
2706         struct drm_i915_private *dev_priv = dev->dev_private;
2707         struct intel_crtc *intel_crtc =
2708                 to_intel_crtc(intel_dig_port->base.base.crtc);
2709         uint32_t DP = intel_dp->DP;
2710
2711         /*
2712          * DDI code has a strict mode set sequence and we should try to respect
2713          * it, otherwise we might hang the machine in many different ways. So we
2714          * really should be disabling the port only on a complete crtc_disable
2715          * sequence. This function is just called under two conditions on DDI
2716          * code:
2717          * - Link train failed while doing crtc_enable, and on this case we
2718          *   really should respect the mode set sequence and wait for a
2719          *   crtc_disable.
2720          * - Someone turned the monitor off and intel_dp_check_link_status
2721          *   called us. We don't need to disable the whole port on this case, so
2722          *   when someone turns the monitor on again,
2723          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2724          *   train.
2725          */
2726         if (HAS_DDI(dev))
2727                 return;
2728
2729         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2730                 return;
2731
2732         DRM_DEBUG_KMS("\n");
2733
2734         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2735                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2736                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2737         } else {
2738                 DP &= ~DP_LINK_TRAIN_MASK;
2739                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2740         }
2741         POSTING_READ(intel_dp->output_reg);
2742
2743         /* We don't really know why we're doing this */
2744         intel_wait_for_vblank(dev, intel_crtc->pipe);
2745
2746         if (HAS_PCH_IBX(dev) &&
2747             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2748                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2749
2750                 /* Hardware workaround: leaving our transcoder select
2751                  * set to transcoder B while it's off will prevent the
2752                  * corresponding HDMI output on transcoder A.
2753                  *
2754                  * Combine this with another hardware workaround:
2755                  * transcoder select bit can only be cleared while the
2756                  * port is enabled.
2757                  */
2758                 DP &= ~DP_PIPEB_SELECT;
2759                 I915_WRITE(intel_dp->output_reg, DP);
2760
2761                 /* Changes to enable or select take place the vblank
2762                  * after being written.
2763                  */
2764                 if (WARN_ON(crtc == NULL)) {
2765                         /* We should never try to disable a port without a crtc
2766                          * attached. For paranoia keep the code around for a
2767                          * bit. */
2768                         POSTING_READ(intel_dp->output_reg);
2769                         msleep(50);
2770                 } else
2771                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2772         }
2773
2774         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2775         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2776         POSTING_READ(intel_dp->output_reg);
2777         msleep(intel_dp->panel_power_down_delay);
2778 }
2779
2780 static bool
2781 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2782 {
2783         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2784         struct drm_device *dev = dig_port->base.base.dev;
2785         struct drm_i915_private *dev_priv = dev->dev_private;
2786
2787         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2788
2789         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2790                                            sizeof(intel_dp->dpcd)) == 0)
2791                 return false; /* aux transfer failed */
2792
2793         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2794                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2795         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2796
2797         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2798                 return false; /* DPCD not present */
2799
2800         /* Check if the panel supports PSR */
2801         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2802         if (is_edp(intel_dp)) {
2803                 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2804                                                intel_dp->psr_dpcd,
2805                                                sizeof(intel_dp->psr_dpcd));
2806                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2807                         dev_priv->psr.sink_support = true;
2808                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2809                 }
2810         }
2811
2812         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2813               DP_DWN_STRM_PORT_PRESENT))
2814                 return true; /* native DP sink */
2815
2816         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2817                 return true; /* no per-port downstream info */
2818
2819         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2820                                            intel_dp->downstream_ports,
2821                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2822                 return false; /* downstream port status fetch failed */
2823
2824         return true;
2825 }
2826
2827 static void
2828 intel_dp_probe_oui(struct intel_dp *intel_dp)
2829 {
2830         u8 buf[3];
2831
2832         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2833                 return;
2834
2835         ironlake_edp_panel_vdd_on(intel_dp);
2836
2837         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2838                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2839                               buf[0], buf[1], buf[2]);
2840
2841         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2842                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2843                               buf[0], buf[1], buf[2]);
2844
2845         ironlake_edp_panel_vdd_off(intel_dp, false);
2846 }
2847
2848 static bool
2849 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2850 {
2851         int ret;
2852
2853         ret = intel_dp_aux_native_read_retry(intel_dp,
2854                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2855                                              sink_irq_vector, 1);
2856         if (!ret)
2857                 return false;
2858
2859         return true;
2860 }
2861
2862 static void
2863 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2864 {
2865         /* NAK by default */
2866         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2867 }
2868
2869 /*
2870  * According to DP spec
2871  * 5.1.2:
2872  *  1. Read DPCD
2873  *  2. Configure link according to Receiver Capabilities
2874  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2875  *  4. Check link status on receipt of hot-plug interrupt
2876  */
2877
2878 void
2879 intel_dp_check_link_status(struct intel_dp *intel_dp)
2880 {
2881         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2882         u8 sink_irq_vector;
2883         u8 link_status[DP_LINK_STATUS_SIZE];
2884
2885         if (!intel_encoder->connectors_active)
2886                 return;
2887
2888         if (WARN_ON(!intel_encoder->base.crtc))
2889                 return;
2890
2891         /* Try to read receiver status if the link appears to be up */
2892         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2893                 intel_dp_link_down(intel_dp);
2894                 return;
2895         }
2896
2897         /* Now read the DPCD to see if it's actually running */
2898         if (!intel_dp_get_dpcd(intel_dp)) {
2899                 intel_dp_link_down(intel_dp);
2900                 return;
2901         }
2902
2903         /* Try to read the source of the interrupt */
2904         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2905             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2906                 /* Clear interrupt source */
2907                 intel_dp_aux_native_write_1(intel_dp,
2908                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2909                                             sink_irq_vector);
2910
2911                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2912                         intel_dp_handle_test_request(intel_dp);
2913                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2914                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2915         }
2916
2917         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2918                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2919                               drm_get_encoder_name(&intel_encoder->base));
2920                 intel_dp_start_link_train(intel_dp);
2921                 intel_dp_complete_link_train(intel_dp);
2922                 intel_dp_stop_link_train(intel_dp);
2923         }
2924 }
2925
2926 /* XXX this is probably wrong for multiple downstream ports */
2927 static enum drm_connector_status
2928 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2929 {
2930         uint8_t *dpcd = intel_dp->dpcd;
2931         uint8_t type;
2932
2933         if (!intel_dp_get_dpcd(intel_dp))
2934                 return connector_status_disconnected;
2935
2936         /* if there's no downstream port, we're done */
2937         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2938                 return connector_status_connected;
2939
2940         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2941         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2942             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2943                 uint8_t reg;
2944                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2945                                                     &reg, 1))
2946                         return connector_status_unknown;
2947                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2948                                               : connector_status_disconnected;
2949         }
2950
2951         /* If no HPD, poke DDC gently */
2952         if (drm_probe_ddc(&intel_dp->adapter))
2953                 return connector_status_connected;
2954
2955         /* Well we tried, say unknown for unreliable port types */
2956         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2957                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2958                 if (type == DP_DS_PORT_TYPE_VGA ||
2959                     type == DP_DS_PORT_TYPE_NON_EDID)
2960                         return connector_status_unknown;
2961         } else {
2962                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2963                         DP_DWN_STRM_PORT_TYPE_MASK;
2964                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2965                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
2966                         return connector_status_unknown;
2967         }
2968
2969         /* Anything else is out of spec, warn and ignore */
2970         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2971         return connector_status_disconnected;
2972 }
2973
2974 static enum drm_connector_status
2975 ironlake_dp_detect(struct intel_dp *intel_dp)
2976 {
2977         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2978         struct drm_i915_private *dev_priv = dev->dev_private;
2979         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2980         enum drm_connector_status status;
2981
2982         /* Can't disconnect eDP, but you can close the lid... */
2983         if (is_edp(intel_dp)) {
2984                 status = intel_panel_detect(dev);
2985                 if (status == connector_status_unknown)
2986                         status = connector_status_connected;
2987                 return status;
2988         }
2989
2990         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2991                 return connector_status_disconnected;
2992
2993         return intel_dp_detect_dpcd(intel_dp);
2994 }
2995
2996 static enum drm_connector_status
2997 g4x_dp_detect(struct intel_dp *intel_dp)
2998 {
2999         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3000         struct drm_i915_private *dev_priv = dev->dev_private;
3001         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3002         uint32_t bit;
3003
3004         /* Can't disconnect eDP, but you can close the lid... */
3005         if (is_edp(intel_dp)) {
3006                 enum drm_connector_status status;
3007
3008                 status = intel_panel_detect(dev);
3009                 if (status == connector_status_unknown)
3010                         status = connector_status_connected;
3011                 return status;
3012         }
3013
3014         switch (intel_dig_port->port) {
3015         case PORT_B:
3016                 bit = PORTB_HOTPLUG_LIVE_STATUS;
3017                 break;
3018         case PORT_C:
3019                 bit = PORTC_HOTPLUG_LIVE_STATUS;
3020                 break;
3021         case PORT_D:
3022                 bit = PORTD_HOTPLUG_LIVE_STATUS;
3023                 break;
3024         default:
3025                 return connector_status_unknown;
3026         }
3027
3028         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3029                 return connector_status_disconnected;
3030
3031         return intel_dp_detect_dpcd(intel_dp);
3032 }
3033
3034 static struct edid *
3035 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3036 {
3037         struct intel_connector *intel_connector = to_intel_connector(connector);
3038
3039         /* use cached edid if we have one */
3040         if (intel_connector->edid) {
3041                 /* invalid edid */
3042                 if (IS_ERR(intel_connector->edid))
3043                         return NULL;
3044
3045                 return drm_edid_duplicate(intel_connector->edid);
3046         }
3047
3048         return drm_get_edid(connector, adapter);
3049 }
3050
3051 static int
3052 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3053 {
3054         struct intel_connector *intel_connector = to_intel_connector(connector);
3055
3056         /* use cached edid if we have one */
3057         if (intel_connector->edid) {
3058                 /* invalid edid */
3059                 if (IS_ERR(intel_connector->edid))
3060                         return 0;
3061
3062                 return intel_connector_update_modes(connector,
3063                                                     intel_connector->edid);
3064         }
3065
3066         return intel_ddc_get_modes(connector, adapter);
3067 }
3068
3069 static enum drm_connector_status
3070 intel_dp_detect(struct drm_connector *connector, bool force)
3071 {
3072         struct intel_dp *intel_dp = intel_attached_dp(connector);
3073         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3074         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3075         struct drm_device *dev = connector->dev;
3076         struct drm_i915_private *dev_priv = dev->dev_private;
3077         enum drm_connector_status status;
3078         struct edid *edid = NULL;
3079
3080         intel_runtime_pm_get(dev_priv);
3081
3082         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3083                       connector->base.id, drm_get_connector_name(connector));
3084
3085         intel_dp->has_audio = false;
3086
3087         if (HAS_PCH_SPLIT(dev))
3088                 status = ironlake_dp_detect(intel_dp);
3089         else
3090                 status = g4x_dp_detect(intel_dp);
3091
3092         if (status != connector_status_connected)
3093                 goto out;
3094
3095         intel_dp_probe_oui(intel_dp);
3096
3097         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3098                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3099         } else {
3100                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3101                 if (edid) {
3102                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3103                         kfree(edid);
3104                 }
3105         }
3106
3107         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3108                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3109         status = connector_status_connected;
3110
3111 out:
3112         intel_runtime_pm_put(dev_priv);
3113         return status;
3114 }
3115
3116 static int intel_dp_get_modes(struct drm_connector *connector)
3117 {
3118         struct intel_dp *intel_dp = intel_attached_dp(connector);
3119         struct intel_connector *intel_connector = to_intel_connector(connector);
3120         struct drm_device *dev = connector->dev;
3121         int ret;
3122
3123         /* We should parse the EDID data and find out if it has an audio sink
3124          */
3125
3126         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3127         if (ret)
3128                 return ret;
3129
3130         /* if eDP has no EDID, fall back to fixed mode */
3131         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3132                 struct drm_display_mode *mode;
3133                 mode = drm_mode_duplicate(dev,
3134                                           intel_connector->panel.fixed_mode);
3135                 if (mode) {
3136                         drm_mode_probed_add(connector, mode);
3137                         return 1;
3138                 }
3139         }
3140         return 0;
3141 }
3142
3143 static bool
3144 intel_dp_detect_audio(struct drm_connector *connector)
3145 {
3146         struct intel_dp *intel_dp = intel_attached_dp(connector);
3147         struct edid *edid;
3148         bool has_audio = false;
3149
3150         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3151         if (edid) {
3152                 has_audio = drm_detect_monitor_audio(edid);
3153                 kfree(edid);
3154         }
3155
3156         return has_audio;
3157 }
3158
3159 static int
3160 intel_dp_set_property(struct drm_connector *connector,
3161                       struct drm_property *property,
3162                       uint64_t val)
3163 {
3164         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3165         struct intel_connector *intel_connector = to_intel_connector(connector);
3166         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3167         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3168         int ret;
3169
3170         ret = drm_object_property_set_value(&connector->base, property, val);
3171         if (ret)
3172                 return ret;
3173
3174         if (property == dev_priv->force_audio_property) {
3175                 int i = val;
3176                 bool has_audio;
3177
3178                 if (i == intel_dp->force_audio)
3179                         return 0;
3180
3181                 intel_dp->force_audio = i;
3182
3183                 if (i == HDMI_AUDIO_AUTO)
3184                         has_audio = intel_dp_detect_audio(connector);
3185                 else
3186                         has_audio = (i == HDMI_AUDIO_ON);
3187
3188                 if (has_audio == intel_dp->has_audio)
3189                         return 0;
3190
3191                 intel_dp->has_audio = has_audio;
3192                 goto done;
3193         }
3194
3195         if (property == dev_priv->broadcast_rgb_property) {
3196                 bool old_auto = intel_dp->color_range_auto;
3197                 uint32_t old_range = intel_dp->color_range;
3198
3199                 switch (val) {
3200                 case INTEL_BROADCAST_RGB_AUTO:
3201                         intel_dp->color_range_auto = true;
3202                         break;
3203                 case INTEL_BROADCAST_RGB_FULL:
3204                         intel_dp->color_range_auto = false;
3205                         intel_dp->color_range = 0;
3206                         break;
3207                 case INTEL_BROADCAST_RGB_LIMITED:
3208                         intel_dp->color_range_auto = false;
3209                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3210                         break;
3211                 default:
3212                         return -EINVAL;
3213                 }
3214
3215                 if (old_auto == intel_dp->color_range_auto &&
3216                     old_range == intel_dp->color_range)
3217                         return 0;
3218
3219                 goto done;
3220         }
3221
3222         if (is_edp(intel_dp) &&
3223             property == connector->dev->mode_config.scaling_mode_property) {
3224                 if (val == DRM_MODE_SCALE_NONE) {
3225                         DRM_DEBUG_KMS("no scaling not supported\n");
3226                         return -EINVAL;
3227                 }
3228
3229                 if (intel_connector->panel.fitting_mode == val) {
3230                         /* the eDP scaling property is not changed */
3231                         return 0;
3232                 }
3233                 intel_connector->panel.fitting_mode = val;
3234
3235                 goto done;
3236         }
3237
3238         return -EINVAL;
3239
3240 done:
3241         if (intel_encoder->base.crtc)
3242                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3243
3244         return 0;
3245 }
3246
3247 static void
3248 intel_dp_connector_destroy(struct drm_connector *connector)
3249 {
3250         struct intel_connector *intel_connector = to_intel_connector(connector);
3251
3252         if (!IS_ERR_OR_NULL(intel_connector->edid))
3253                 kfree(intel_connector->edid);
3254
3255         /* Can't call is_edp() since the encoder may have been destroyed
3256          * already. */
3257         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3258                 intel_panel_fini(&intel_connector->panel);
3259
3260         drm_connector_cleanup(connector);
3261         kfree(connector);
3262 }
3263
3264 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3265 {
3266         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3267         struct intel_dp *intel_dp = &intel_dig_port->dp;
3268         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3269
3270         i2c_del_adapter(&intel_dp->adapter);
3271         drm_encoder_cleanup(encoder);
3272         if (is_edp(intel_dp)) {
3273                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3274                 mutex_lock(&dev->mode_config.mutex);
3275                 ironlake_panel_vdd_off_sync(intel_dp);
3276                 mutex_unlock(&dev->mode_config.mutex);
3277         }
3278         kfree(intel_dig_port);
3279 }
3280
3281 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3282         .dpms = intel_connector_dpms,
3283         .detect = intel_dp_detect,
3284         .fill_modes = drm_helper_probe_single_connector_modes,
3285         .set_property = intel_dp_set_property,
3286         .destroy = intel_dp_connector_destroy,
3287 };
3288
3289 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3290         .get_modes = intel_dp_get_modes,
3291         .mode_valid = intel_dp_mode_valid,
3292         .best_encoder = intel_best_encoder,
3293 };
3294
3295 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3296         .destroy = intel_dp_encoder_destroy,
3297 };
3298
3299 static void
3300 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3301 {
3302         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3303
3304         intel_dp_check_link_status(intel_dp);
3305 }
3306
3307 /* Return which DP Port should be selected for Transcoder DP control */
3308 int
3309 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3310 {
3311         struct drm_device *dev = crtc->dev;
3312         struct intel_encoder *intel_encoder;
3313         struct intel_dp *intel_dp;
3314
3315         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3316                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3317
3318                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3319                     intel_encoder->type == INTEL_OUTPUT_EDP)
3320                         return intel_dp->output_reg;
3321         }
3322
3323         return -1;
3324 }
3325
3326 /* check the VBT to see whether the eDP is on DP-D port */
3327 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         union child_device_config *p_child;
3331         int i;
3332         static const short port_mapping[] = {
3333                 [PORT_B] = PORT_IDPB,
3334                 [PORT_C] = PORT_IDPC,
3335                 [PORT_D] = PORT_IDPD,
3336         };
3337
3338         if (port == PORT_A)
3339                 return true;
3340
3341         if (!dev_priv->vbt.child_dev_num)
3342                 return false;
3343
3344         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3345                 p_child = dev_priv->vbt.child_dev + i;
3346
3347                 if (p_child->common.dvo_port == port_mapping[port] &&
3348                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3349                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3350                         return true;
3351         }
3352         return false;
3353 }
3354
3355 static void
3356 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3357 {
3358         struct intel_connector *intel_connector = to_intel_connector(connector);
3359
3360         intel_attach_force_audio_property(connector);
3361         intel_attach_broadcast_rgb_property(connector);
3362         intel_dp->color_range_auto = true;
3363
3364         if (is_edp(intel_dp)) {
3365                 drm_mode_create_scaling_mode_property(connector->dev);
3366                 drm_object_attach_property(
3367                         &connector->base,
3368                         connector->dev->mode_config.scaling_mode_property,
3369                         DRM_MODE_SCALE_ASPECT);
3370                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3371         }
3372 }
3373
3374 static void
3375 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3376                                     struct intel_dp *intel_dp,
3377                                     struct edp_power_seq *out)
3378 {
3379         struct drm_i915_private *dev_priv = dev->dev_private;
3380         struct edp_power_seq cur, vbt, spec, final;
3381         u32 pp_on, pp_off, pp_div, pp;
3382         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3383
3384         if (HAS_PCH_SPLIT(dev)) {
3385                 pp_ctrl_reg = PCH_PP_CONTROL;
3386                 pp_on_reg = PCH_PP_ON_DELAYS;
3387                 pp_off_reg = PCH_PP_OFF_DELAYS;
3388                 pp_div_reg = PCH_PP_DIVISOR;
3389         } else {
3390                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3391
3392                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3393                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3394                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3395                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3396         }
3397
3398         /* Workaround: Need to write PP_CONTROL with the unlock key as
3399          * the very first thing. */
3400         pp = ironlake_get_pp_control(intel_dp);
3401         I915_WRITE(pp_ctrl_reg, pp);
3402
3403         pp_on = I915_READ(pp_on_reg);
3404         pp_off = I915_READ(pp_off_reg);
3405         pp_div = I915_READ(pp_div_reg);
3406
3407         /* Pull timing values out of registers */
3408         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3409                 PANEL_POWER_UP_DELAY_SHIFT;
3410
3411         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3412                 PANEL_LIGHT_ON_DELAY_SHIFT;
3413
3414         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3415                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3416
3417         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3418                 PANEL_POWER_DOWN_DELAY_SHIFT;
3419
3420         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3421                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3422
3423         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3424                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3425
3426         vbt = dev_priv->vbt.edp_pps;
3427
3428         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3429          * our hw here, which are all in 100usec. */
3430         spec.t1_t3 = 210 * 10;
3431         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3432         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3433         spec.t10 = 500 * 10;
3434         /* This one is special and actually in units of 100ms, but zero
3435          * based in the hw (so we need to add 100 ms). But the sw vbt
3436          * table multiplies it with 1000 to make it in units of 100usec,
3437          * too. */
3438         spec.t11_t12 = (510 + 100) * 10;
3439
3440         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3441                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3442
3443         /* Use the max of the register settings and vbt. If both are
3444          * unset, fall back to the spec limits. */
3445 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3446                                        spec.field : \
3447                                        max(cur.field, vbt.field))
3448         assign_final(t1_t3);
3449         assign_final(t8);
3450         assign_final(t9);
3451         assign_final(t10);
3452         assign_final(t11_t12);
3453 #undef assign_final
3454
3455 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3456         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3457         intel_dp->backlight_on_delay = get_delay(t8);
3458         intel_dp->backlight_off_delay = get_delay(t9);
3459         intel_dp->panel_power_down_delay = get_delay(t10);
3460         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3461 #undef get_delay
3462
3463         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3464                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3465                       intel_dp->panel_power_cycle_delay);
3466
3467         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3468                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3469
3470         if (out)
3471                 *out = final;
3472 }
3473
3474 static void
3475 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3476                                               struct intel_dp *intel_dp,
3477                                               struct edp_power_seq *seq)
3478 {
3479         struct drm_i915_private *dev_priv = dev->dev_private;
3480         u32 pp_on, pp_off, pp_div, port_sel = 0;
3481         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3482         int pp_on_reg, pp_off_reg, pp_div_reg;
3483
3484         if (HAS_PCH_SPLIT(dev)) {
3485                 pp_on_reg = PCH_PP_ON_DELAYS;
3486                 pp_off_reg = PCH_PP_OFF_DELAYS;
3487                 pp_div_reg = PCH_PP_DIVISOR;
3488         } else {
3489                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3490
3491                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3492                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3493                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3494         }
3495
3496         /* And finally store the new values in the power sequencer. */
3497         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3498                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3499         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3500                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3501         /* Compute the divisor for the pp clock, simply match the Bspec
3502          * formula. */
3503         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3504         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3505                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3506
3507         /* Haswell doesn't have any port selection bits for the panel
3508          * power sequencer any more. */
3509         if (IS_VALLEYVIEW(dev)) {
3510                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3511                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3512                 else
3513                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3514         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3515                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3516                         port_sel = PANEL_PORT_SELECT_DPA;
3517                 else
3518                         port_sel = PANEL_PORT_SELECT_DPD;
3519         }
3520
3521         pp_on |= port_sel;
3522
3523         I915_WRITE(pp_on_reg, pp_on);
3524         I915_WRITE(pp_off_reg, pp_off);
3525         I915_WRITE(pp_div_reg, pp_div);
3526
3527         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3528                       I915_READ(pp_on_reg),
3529                       I915_READ(pp_off_reg),
3530                       I915_READ(pp_div_reg));
3531 }
3532
3533 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3534                                      struct intel_connector *intel_connector)
3535 {
3536         struct drm_connector *connector = &intel_connector->base;
3537         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3538         struct drm_device *dev = intel_dig_port->base.base.dev;
3539         struct drm_i915_private *dev_priv = dev->dev_private;
3540         struct drm_display_mode *fixed_mode = NULL;
3541         struct edp_power_seq power_seq = { 0 };
3542         bool has_dpcd;
3543         struct drm_display_mode *scan;
3544         struct edid *edid;
3545
3546         if (!is_edp(intel_dp))
3547                 return true;
3548
3549         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3550
3551         /* Cache DPCD and EDID for edp. */
3552         ironlake_edp_panel_vdd_on(intel_dp);
3553         has_dpcd = intel_dp_get_dpcd(intel_dp);
3554         ironlake_edp_panel_vdd_off(intel_dp, false);
3555
3556         if (has_dpcd) {
3557                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3558                         dev_priv->no_aux_handshake =
3559                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3560                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3561         } else {
3562                 /* if this fails, presume the device is a ghost */
3563                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3564                 return false;
3565         }
3566
3567         /* We now know it's not a ghost, init power sequence regs. */
3568         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3569                                                       &power_seq);
3570
3571         edid = drm_get_edid(connector, &intel_dp->adapter);
3572         if (edid) {
3573                 if (drm_add_edid_modes(connector, edid)) {
3574                         drm_mode_connector_update_edid_property(connector,
3575                                                                 edid);
3576                         drm_edid_to_eld(connector, edid);
3577                 } else {
3578                         kfree(edid);
3579                         edid = ERR_PTR(-EINVAL);
3580                 }
3581         } else {
3582                 edid = ERR_PTR(-ENOENT);
3583         }
3584         intel_connector->edid = edid;
3585
3586         /* prefer fixed mode from EDID if available */
3587         list_for_each_entry(scan, &connector->probed_modes, head) {
3588                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3589                         fixed_mode = drm_mode_duplicate(dev, scan);
3590                         break;
3591                 }
3592         }
3593
3594         /* fallback to VBT if available for eDP */
3595         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3596                 fixed_mode = drm_mode_duplicate(dev,
3597                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3598                 if (fixed_mode)
3599                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3600         }
3601
3602         intel_panel_init(&intel_connector->panel, fixed_mode);
3603         intel_panel_setup_backlight(connector);
3604
3605         return true;
3606 }
3607
3608 bool
3609 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3610                         struct intel_connector *intel_connector)
3611 {
3612         struct drm_connector *connector = &intel_connector->base;
3613         struct intel_dp *intel_dp = &intel_dig_port->dp;
3614         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3615         struct drm_device *dev = intel_encoder->base.dev;
3616         struct drm_i915_private *dev_priv = dev->dev_private;
3617         enum port port = intel_dig_port->port;
3618         const char *name = NULL;
3619         int type, error;
3620
3621         /* Preserve the current hw state. */
3622         intel_dp->DP = I915_READ(intel_dp->output_reg);
3623         intel_dp->attached_connector = intel_connector;
3624
3625         if (intel_dp_is_edp(dev, port))
3626                 type = DRM_MODE_CONNECTOR_eDP;
3627         else
3628                 type = DRM_MODE_CONNECTOR_DisplayPort;
3629
3630         /*
3631          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3632          * for DP the encoder type can be set by the caller to
3633          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3634          */
3635         if (type == DRM_MODE_CONNECTOR_eDP)
3636                 intel_encoder->type = INTEL_OUTPUT_EDP;
3637
3638         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3639                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3640                         port_name(port));
3641
3642         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3643         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3644
3645         connector->interlace_allowed = true;
3646         connector->doublescan_allowed = 0;
3647
3648         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3649                           ironlake_panel_vdd_work);
3650
3651         intel_connector_attach_encoder(intel_connector, intel_encoder);
3652         drm_sysfs_connector_add(connector);
3653
3654         if (HAS_DDI(dev))
3655                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3656         else
3657                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3658
3659         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3660         if (HAS_DDI(dev)) {
3661                 switch (intel_dig_port->port) {
3662                 case PORT_A:
3663                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3664                         break;
3665                 case PORT_B:
3666                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3667                         break;
3668                 case PORT_C:
3669                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3670                         break;
3671                 case PORT_D:
3672                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3673                         break;
3674                 default:
3675                         BUG();
3676                 }
3677         }
3678
3679         /* Set up the DDC bus. */
3680         switch (port) {
3681         case PORT_A:
3682                 intel_encoder->hpd_pin = HPD_PORT_A;
3683                 name = "DPDDC-A";
3684                 break;
3685         case PORT_B:
3686                 intel_encoder->hpd_pin = HPD_PORT_B;
3687                 name = "DPDDC-B";
3688                 break;
3689         case PORT_C:
3690                 intel_encoder->hpd_pin = HPD_PORT_C;
3691                 name = "DPDDC-C";
3692                 break;
3693         case PORT_D:
3694                 intel_encoder->hpd_pin = HPD_PORT_D;
3695                 name = "DPDDC-D";
3696                 break;
3697         default:
3698                 BUG();
3699         }
3700
3701         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3702         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3703              error, port_name(port));
3704
3705         intel_dp->psr_setup_done = false;
3706
3707         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3708                 i2c_del_adapter(&intel_dp->adapter);
3709                 if (is_edp(intel_dp)) {
3710                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3711                         mutex_lock(&dev->mode_config.mutex);
3712                         ironlake_panel_vdd_off_sync(intel_dp);
3713                         mutex_unlock(&dev->mode_config.mutex);
3714                 }
3715                 drm_sysfs_connector_remove(connector);
3716                 drm_connector_cleanup(connector);
3717                 return false;
3718         }
3719
3720         intel_dp_add_properties(intel_dp, connector);
3721
3722         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3723          * 0xd.  Failure to do so will result in spurious interrupts being
3724          * generated on the port when a cable is not attached.
3725          */
3726         if (IS_G4X(dev) && !IS_GM45(dev)) {
3727                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3728                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3729         }
3730
3731         return true;
3732 }
3733
3734 void
3735 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3736 {
3737         struct intel_digital_port *intel_dig_port;
3738         struct intel_encoder *intel_encoder;
3739         struct drm_encoder *encoder;
3740         struct intel_connector *intel_connector;
3741
3742         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3743         if (!intel_dig_port)
3744                 return;
3745
3746         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3747         if (!intel_connector) {
3748                 kfree(intel_dig_port);
3749                 return;
3750         }
3751
3752         intel_encoder = &intel_dig_port->base;
3753         encoder = &intel_encoder->base;
3754
3755         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3756                          DRM_MODE_ENCODER_TMDS);
3757
3758         intel_encoder->compute_config = intel_dp_compute_config;
3759         intel_encoder->mode_set = intel_dp_mode_set;
3760         intel_encoder->disable = intel_disable_dp;
3761         intel_encoder->post_disable = intel_post_disable_dp;
3762         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3763         intel_encoder->get_config = intel_dp_get_config;
3764         if (IS_VALLEYVIEW(dev)) {
3765                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3766                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3767                 intel_encoder->enable = vlv_enable_dp;
3768         } else {
3769                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3770                 intel_encoder->enable = g4x_enable_dp;
3771         }
3772
3773         intel_dig_port->port = port;
3774         intel_dig_port->dp.output_reg = output_reg;
3775
3776         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3777         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3778         intel_encoder->cloneable = false;
3779         intel_encoder->hot_plug = intel_dp_hot_plug;
3780
3781         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3782                 drm_encoder_cleanup(encoder);
3783                 kfree(intel_dig_port);
3784                 kfree(intel_connector);
3785         }
3786 }