drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 static int
 113 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 114 {
 115         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 116
 117         switch (max_link_bw) {
 118         case DP_LINK_BW_1_62:
 119         case DP_LINK_BW_2_7:
 120                 break;
 121         default:
 122                 max_link_bw = DP_LINK_BW_1_62;
 123                 break;
 124         }
 125         return max_link_bw;
 126 }
 127
 128 /*
 129  * The units on the numbers in the next two are... bizarre.  Examples will
 130  * make it clearer; this one parallels an example in the eDP spec.
 131  *
 132  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 133  *
 134  *     270000 * 1 * 8 / 10 == 216000
 135  *
 136  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 137  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 138  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 139  * 119000.  At 18bpp that's 2142000 kilobits per second.
 140  *
 141  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 142  * get the result in decakilobits instead of kilobits.
 143  */
 144
 145 static int
 146 intel_dp_link_required(int pixel_clock, int bpp)
 147 {
 148         return (pixel_clock * bpp + 9) / 10;
 149 }
 150
 151 static int
 152 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 153 {
 154         return (max_link_clock * max_lanes * 8) / 10;
 155 }
 156
 157 static int
 158 intel_dp_mode_valid(struct drm_connector *connector,
 159                     struct drm_display_mode *mode)
 160 {
 161         struct intel_dp *intel_dp = intel_attached_dp(connector);
 162         struct intel_connector *intel_connector = to_intel_connector(connector);
 163         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 164         int target_clock = mode->clock;
 165         int max_rate, mode_rate, max_lanes, max_link_clock;
 166
 167         if (is_edp(intel_dp) && fixed_mode) {
 168                 if (mode->hdisplay > fixed_mode->hdisplay)
 169                         return MODE_PANEL;
 170
 171                 if (mode->vdisplay > fixed_mode->vdisplay)
 172                         return MODE_PANEL;
 173
 174                 target_clock = fixed_mode->clock;
 175         }
 176
 177         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 178         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 179
 180         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 181         mode_rate = intel_dp_link_required(target_clock, 18);
 182
 183         if (mode_rate > max_rate)
 184                 return MODE_CLOCK_HIGH;
 185
 186         if (mode->clock < 10000)
 187                 return MODE_CLOCK_LOW;
 188
 189         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 190                 return MODE_H_ILLEGAL;
 191
 192         return MODE_OK;
 193 }
 194
 195 static uint32_t
 196 pack_aux(uint8_t *src, int src_bytes)
 197 {
 198         int     i;
 199         uint32_t v = 0;
 200
 201         if (src_bytes > 4)
 202                 src_bytes = 4;
 203         for (i = 0; i < src_bytes; i++)
 204                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 205         return v;
 206 }
 207
 208 static void
 209 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 210 {
 211         int i;
 212         if (dst_bytes > 4)
 213                 dst_bytes = 4;
 214         for (i = 0; i < dst_bytes; i++)
 215                 dst[i] = src >> ((3-i) * 8);
 216 }
 217
 218 /* hrawclock is 1/4 the FSB frequency */
 219 static int
 220 intel_hrawclk(struct drm_device *dev)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         uint32_t clkcfg;
 224
 225         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 226         if (IS_VALLEYVIEW(dev))
 227                 return 200;
 228
 229         clkcfg = I915_READ(CLKCFG);
 230         switch (clkcfg & CLKCFG_FSB_MASK) {
 231         case CLKCFG_FSB_400:
 232                 return 100;
 233         case CLKCFG_FSB_533:
 234                 return 133;
 235         case CLKCFG_FSB_667:
 236                 return 166;
 237         case CLKCFG_FSB_800:
 238                 return 200;
 239         case CLKCFG_FSB_1067:
 240                 return 266;
 241         case CLKCFG_FSB_1333:
 242                 return 333;
 243         /* these two are just a guess; one of them might be right */
 244         case CLKCFG_FSB_1600:
 245         case CLKCFG_FSB_1600_ALT:
 246                 return 400;
 247         default:
 248                 return 133;
 249         }
 250 }
 251
 252 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 253 {
 254         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         u32 pp_stat_reg;
 257
 258         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 259         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 260 }
 261
 262 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 263 {
 264         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 265         struct drm_i915_private *dev_priv = dev->dev_private;
 266         u32 pp_ctrl_reg;
 267
 268         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 269         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 270 }
 271
 272 static void
 273 intel_dp_check_edp(struct intel_dp *intel_dp)
 274 {
 275         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         u32 pp_stat_reg, pp_ctrl_reg;
 278
 279         if (!is_edp(intel_dp))
 280                 return;
 281
 282         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 283         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 284
 285         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 286                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 287                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 288                                 I915_READ(pp_stat_reg),
 289                                 I915_READ(pp_ctrl_reg));
 290         }
 291 }
 292
 293 static uint32_t
 294 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_device *dev = intel_dig_port->base.base.dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 300         uint32_t status;
 301         bool done;
 302
 303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 304         if (has_aux_irq)
 305                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 306                                           msecs_to_jiffies(10));
 307         else
 308                 done = wait_for_atomic(C, 10) == 0;
 309         if (!done)
 310                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 311                           has_aux_irq);
 312 #undef C
 313
 314         return status;
 315 }
 316
 317 static int
 318 intel_dp_aux_ch(struct intel_dp *intel_dp,
 319                 uint8_t *send, int send_bytes,
 320                 uint8_t *recv, int recv_size)
 321 {
 322         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 323         struct drm_device *dev = intel_dig_port->base.base.dev;
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 326         uint32_t ch_data = ch_ctl + 4;
 327         int i, ret, recv_bytes;
 328         uint32_t status;
 329         uint32_t aux_clock_divider;
 330         int try, precharge;
 331         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 332
 333         /* dp aux is extremely sensitive to irq latency, hence request the
 334          * lowest possible wakeup latency and so prevent the cpu from going into
 335          * deep sleep states.
 336          */
 337         pm_qos_update_request(&dev_priv->pm_qos, 0);
 338
 339         intel_dp_check_edp(intel_dp);
 340         /* The clock divider is based off the hrawclk,
 341          * and would like to run at 2MHz. So, take the
 342          * hrawclk value and divide by 2 and use that
 343          *
 344          * Note that PCH attached eDP panels should use a 125MHz input
 345          * clock divider.
 346          */
 347         if (is_cpu_edp(intel_dp)) {
 348                 if (HAS_DDI(dev))
 349                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 350                 else if (IS_VALLEYVIEW(dev))
 351                         aux_clock_divider = 100;
 352                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 353                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 354                 else
 355                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 356         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 357                 /* Workaround for non-ULT HSW */
 358                 aux_clock_divider = 74;
 359         } else if (HAS_PCH_SPLIT(dev)) {
 360                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 361         } else {
 362                 aux_clock_divider = intel_hrawclk(dev) / 2;
 363         }
 364
 365         if (IS_GEN6(dev))
 366                 precharge = 3;
 367         else
 368                 precharge = 5;
 369
 370         /* Try to wait for any previous AUX channel activity */
 371         for (try = 0; try < 3; try++) {
 372                 status = I915_READ_NOTRACE(ch_ctl);
 373                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 374                         break;
 375                 msleep(1);
 376         }
 377
 378         if (try == 3) {
 379                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 380                      I915_READ(ch_ctl));
 381                 ret = -EBUSY;
 382                 goto out;
 383         }
 384
 385         /* Must try at least 3 times according to DP spec */
 386         for (try = 0; try < 5; try++) {
 387                 /* Load the send data into the aux channel data registers */
 388                 for (i = 0; i < send_bytes; i += 4)
 389                         I915_WRITE(ch_data + i,
 390                                    pack_aux(send + i, send_bytes - i));
 391
 392                 /* Send the command and wait for it to complete */
 393                 I915_WRITE(ch_ctl,
 394                            DP_AUX_CH_CTL_SEND_BUSY |
 395                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 396                            DP_AUX_CH_CTL_TIME_OUT_400us |
 397                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 398                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 399                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 400                            DP_AUX_CH_CTL_DONE |
 401                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 402                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 403
 404                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 405
 406                 /* Clear done status and any errors */
 407                 I915_WRITE(ch_ctl,
 408                            status |
 409                            DP_AUX_CH_CTL_DONE |
 410                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 411                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 412
 413                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 414                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 415                         continue;
 416                 if (status & DP_AUX_CH_CTL_DONE)
 417                         break;
 418         }
 419
 420         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 421                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 422                 ret = -EBUSY;
 423                 goto out;
 424         }
 425
 426         /* Check for timeout or receive error.
 427          * Timeouts occur when the sink is not connected
 428          */
 429         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 430                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 431                 ret = -EIO;
 432                 goto out;
 433         }
 434
 435         /* Timeouts occur when the device isn't connected, so they're
 436          * "normal" -- don't fill the kernel log with these */
 437         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 438                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 439                 ret = -ETIMEDOUT;
 440                 goto out;
 441         }
 442
 443         /* Unload any bytes sent back from the other side */
 444         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 445                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 446         if (recv_bytes > recv_size)
 447                 recv_bytes = recv_size;
 448
 449         for (i = 0; i < recv_bytes; i += 4)
 450                 unpack_aux(I915_READ(ch_data + i),
 451                            recv + i, recv_bytes - i);
 452
 453         ret = recv_bytes;
 454 out:
 455         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 456
 457         return ret;
 458 }
 459
 460 /* Write data to the aux channel in native mode */
 461 static int
 462 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 463                           uint16_t address, uint8_t *send, int send_bytes)
 464 {
 465         int ret;
 466         uint8_t msg[20];
 467         int msg_bytes;
 468         uint8_t ack;
 469
 470         intel_dp_check_edp(intel_dp);
 471         if (send_bytes > 16)
 472                 return -1;
 473         msg[0] = AUX_NATIVE_WRITE << 4;
 474         msg[1] = address >> 8;
 475         msg[2] = address & 0xff;
 476         msg[3] = send_bytes - 1;
 477         memcpy(&msg[4], send, send_bytes);
 478         msg_bytes = send_bytes + 4;
 479         for (;;) {
 480                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 481                 if (ret < 0)
 482                         return ret;
 483                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 484                         break;
 485                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 486                         udelay(100);
 487                 else
 488                         return -EIO;
 489         }
 490         return send_bytes;
 491 }
 492
 493 /* Write a single byte to the aux channel in native mode */
 494 static int
 495 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 496                             uint16_t address, uint8_t byte)
 497 {
 498         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 499 }
 500
 501 /* read bytes from a native aux channel */
 502 static int
 503 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 504                          uint16_t address, uint8_t *recv, int recv_bytes)
 505 {
 506         uint8_t msg[4];
 507         int msg_bytes;
 508         uint8_t reply[20];
 509         int reply_bytes;
 510         uint8_t ack;
 511         int ret;
 512
 513         intel_dp_check_edp(intel_dp);
 514         msg[0] = AUX_NATIVE_READ << 4;
 515         msg[1] = address >> 8;
 516         msg[2] = address & 0xff;
 517         msg[3] = recv_bytes - 1;
 518
 519         msg_bytes = 4;
 520         reply_bytes = recv_bytes + 1;
 521
 522         for (;;) {
 523                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 524                                       reply, reply_bytes);
 525                 if (ret == 0)
 526                         return -EPROTO;
 527                 if (ret < 0)
 528                         return ret;
 529                 ack = reply[0];
 530                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 531                         memcpy(recv, reply + 1, ret - 1);
 532                         return ret - 1;
 533                 }
 534                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 535                         udelay(100);
 536                 else
 537                         return -EIO;
 538         }
 539 }
 540
 541 static int
 542 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 543                     uint8_t write_byte, uint8_t *read_byte)
 544 {
 545         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 546         struct intel_dp *intel_dp = container_of(adapter,
 547                                                 struct intel_dp,
 548                                                 adapter);
 549         uint16_t address = algo_data->address;
 550         uint8_t msg[5];
 551         uint8_t reply[2];
 552         unsigned retry;
 553         int msg_bytes;
 554         int reply_bytes;
 555         int ret;
 556
 557         intel_dp_check_edp(intel_dp);
 558         /* Set up the command byte */
 559         if (mode & MODE_I2C_READ)
 560                 msg[0] = AUX_I2C_READ << 4;
 561         else
 562                 msg[0] = AUX_I2C_WRITE << 4;
 563
 564         if (!(mode & MODE_I2C_STOP))
 565                 msg[0] |= AUX_I2C_MOT << 4;
 566
 567         msg[1] = address >> 8;
 568         msg[2] = address;
 569
 570         switch (mode) {
 571         case MODE_I2C_WRITE:
 572                 msg[3] = 0;
 573                 msg[4] = write_byte;
 574                 msg_bytes = 5;
 575                 reply_bytes = 1;
 576                 break;
 577         case MODE_I2C_READ:
 578                 msg[3] = 0;
 579                 msg_bytes = 4;
 580                 reply_bytes = 2;
 581                 break;
 582         default:
 583                 msg_bytes = 3;
 584                 reply_bytes = 1;
 585                 break;
 586         }
 587
 588         for (retry = 0; retry < 5; retry++) {
 589                 ret = intel_dp_aux_ch(intel_dp,
 590                                       msg, msg_bytes,
 591                                       reply, reply_bytes);
 592                 if (ret < 0) {
 593                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 594                         return ret;
 595                 }
 596
 597                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 598                 case AUX_NATIVE_REPLY_ACK:
 599                         /* I2C-over-AUX Reply field is only valid
 600                          * when paired with AUX ACK.
 601                          */
 602                         break;
 603                 case AUX_NATIVE_REPLY_NACK:
 604                         DRM_DEBUG_KMS("aux_ch native nack\n");
 605                         return -EREMOTEIO;
 606                 case AUX_NATIVE_REPLY_DEFER:
 607                         udelay(100);
 608                         continue;
 609                 default:
 610                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 611                                   reply[0]);
 612                         return -EREMOTEIO;
 613                 }
 614
 615                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 616                 case AUX_I2C_REPLY_ACK:
 617                         if (mode == MODE_I2C_READ) {
 618                                 *read_byte = reply[1];
 619                         }
 620                         return reply_bytes - 1;
 621                 case AUX_I2C_REPLY_NACK:
 622                         DRM_DEBUG_KMS("aux_i2c nack\n");
 623                         return -EREMOTEIO;
 624                 case AUX_I2C_REPLY_DEFER:
 625                         DRM_DEBUG_KMS("aux_i2c defer\n");
 626                         udelay(100);
 627                         break;
 628                 default:
 629                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 630                         return -EREMOTEIO;
 631                 }
 632         }
 633
 634         DRM_ERROR("too many retries, giving up\n");
 635         return -EREMOTEIO;
 636 }
 637
 638 static int
 639 intel_dp_i2c_init(struct intel_dp *intel_dp,
 640                   struct intel_connector *intel_connector, const char *name)
 641 {
 642         int     ret;
 643
 644         DRM_DEBUG_KMS("i2c_init %s\n", name);
 645         intel_dp->algo.running = false;
 646         intel_dp->algo.address = 0;
 647         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 648
 649         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 650         intel_dp->adapter.owner = THIS_MODULE;
 651         intel_dp->adapter.class = I2C_CLASS_DDC;
 652         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 653         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 654         intel_dp->adapter.algo_data = &intel_dp->algo;
 655         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 656
 657         ironlake_edp_panel_vdd_on(intel_dp);
 658         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 659         ironlake_edp_panel_vdd_off(intel_dp, false);
 660         return ret;
 661 }
 662
 663 bool
 664 intel_dp_compute_config(struct intel_encoder *encoder,
 665                         struct intel_crtc_config *pipe_config)
 666 {
 667         struct drm_device *dev = encoder->base.dev;
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 670         struct drm_display_mode *mode = &pipe_config->requested_mode;
 671         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 672         struct intel_connector *intel_connector = intel_dp->attached_connector;
 673         int lane_count, clock;
 674         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 675         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 676         int bpp, mode_rate;
 677         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 678         int target_clock, link_avail, link_clock;
 679
 680         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
 681                 pipe_config->has_pch_encoder = true;
 682
 683         pipe_config->has_dp_encoder = true;
 684
 685         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 686                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 687                                        adjusted_mode);
 688                 intel_pch_panel_fitting(dev,
 689                                         intel_connector->panel.fitting_mode,
 690                                         mode, adjusted_mode);
 691         }
 692         /* We need to take the panel's fixed mode into account. */
 693         target_clock = adjusted_mode->clock;
 694
 695         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 696                 return false;
 697
 698         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 699                       "max bw %02x pixel clock %iKHz\n",
 700                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 701
 702         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 703          * bpc in between. */
 704         bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
 705         for (; bpp >= 6*3; bpp -= 2*3) {
 706                 mode_rate = intel_dp_link_required(target_clock, bpp);
 707
 708                 for (clock = 0; clock <= max_clock; clock++) {
 709                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 710                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 711                                 link_avail = intel_dp_max_data_rate(link_clock,
 712                                                                     lane_count);
 713
 714                                 if (mode_rate <= link_avail) {
 715                                         goto found;
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return false;
 722
 723 found:
 724         if (intel_dp->color_range_auto) {
 725                 /*
 726                  * See:
 727                  * CEA-861-E - 5.1 Default Encoding Parameters
 728                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 729                  */
 730                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 731                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 732                 else
 733                         intel_dp->color_range = 0;
 734         }
 735
 736         if (intel_dp->color_range)
 737                 pipe_config->limited_color_range = true;
 738
 739         intel_dp->link_bw = bws[clock];
 740         intel_dp->lane_count = lane_count;
 741         adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 742         pipe_config->pixel_target_clock = target_clock;
 743
 744         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 745                       intel_dp->link_bw, intel_dp->lane_count,
 746                       adjusted_mode->clock, bpp);
 747         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 748                       mode_rate, link_avail);
 749
 750         intel_link_compute_m_n(bpp, lane_count,
 751                                target_clock, adjusted_mode->clock,
 752                                &pipe_config->dp_m_n);
 753
 754         /*
 755          * XXX: We have a strange regression where using the vbt edp bpp value
 756          * for the link bw computation results in black screens, the panel only
 757          * works when we do the computation at the usual 24bpp (but still
 758          * requires us to use 18bpp). Until that's fully debugged, stay
 759          * bug-for-bug compatible with the old code.
 760          */
 761         if (is_edp(intel_dp) && dev_priv->edp.bpp) {
 762                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
 763                               bpp, dev_priv->edp.bpp);
 764                 bpp = min_t(int, bpp, dev_priv->edp.bpp);
 765         }
 766         pipe_config->pipe_bpp = bpp;
 767
 768         return true;
 769 }
 770
 771 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 772 {
 773         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 774         intel_dp->link_configuration[0] = intel_dp->link_bw;
 775         intel_dp->link_configuration[1] = intel_dp->lane_count;
 776         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 777         /*
 778          * Check for DPCD version > 1.1 and enhanced framing support
 779          */
 780         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 781             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 782                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 783         }
 784 }
 785
 786 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 787 {
 788         struct drm_device *dev = crtc->dev;
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         u32 dpa_ctl;
 791
 792         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 793         dpa_ctl = I915_READ(DP_A);
 794         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 795
 796         if (clock < 200000) {
 797                 /* For a long time we've carried around a ILK-DevA w/a for the
 798                  * 160MHz clock. If we're really unlucky, it's still required.
 799                  */
 800                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 801                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 802         } else {
 803                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 804         }
 805
 806         I915_WRITE(DP_A, dpa_ctl);
 807
 808         POSTING_READ(DP_A);
 809         udelay(500);
 810 }
 811
 812 static void
 813 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 814                   struct drm_display_mode *adjusted_mode)
 815 {
 816         struct drm_device *dev = encoder->dev;
 817         struct drm_i915_private *dev_priv = dev->dev_private;
 818         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 819         struct drm_crtc *crtc = encoder->crtc;
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /*
 823          * There are four kinds of DP registers:
 824          *
 825          *      IBX PCH
 826          *      SNB CPU
 827          *      IVB CPU
 828          *      CPT PCH
 829          *
 830          * IBX PCH and CPU are the same for almost everything,
 831          * except that the CPU DP PLL is configured in this
 832          * register
 833          *
 834          * CPT PCH is quite different, having many bits moved
 835          * to the TRANS_DP_CTL register instead. That
 836          * configuration happens (oddly) in ironlake_pch_enable
 837          */
 838
 839         /* Preserve the BIOS-computed detected bit. This is
 840          * supposed to be read-only.
 841          */
 842         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 843
 844         /* Handle DP bits in common between all three register formats */
 845         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 846
 847         switch (intel_dp->lane_count) {
 848         case 1:
 849                 intel_dp->DP |= DP_PORT_WIDTH_1;
 850                 break;
 851         case 2:
 852                 intel_dp->DP |= DP_PORT_WIDTH_2;
 853                 break;
 854         case 4:
 855                 intel_dp->DP |= DP_PORT_WIDTH_4;
 856                 break;
 857         }
 858         if (intel_dp->has_audio) {
 859                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 860                                  pipe_name(intel_crtc->pipe));
 861                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 862                 intel_write_eld(encoder, adjusted_mode);
 863         }
 864
 865         intel_dp_init_link_config(intel_dp);
 866
 867         /* Split out the IBX/CPU vs CPT settings */
 868
 869         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 870                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 871                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 872                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 873                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 874                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 875
 876                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 877                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 878
 879                 intel_dp->DP |= intel_crtc->pipe << 29;
 880
 881                 /* don't miss out required setting for eDP */
 882                 if (adjusted_mode->clock < 200000)
 883                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 884                 else
 885                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 886         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 887                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 888                         intel_dp->DP |= intel_dp->color_range;
 889
 890                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 891                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 892                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 893                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 894                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 895
 896                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 897                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 898
 899                 if (intel_crtc->pipe == 1)
 900                         intel_dp->DP |= DP_PIPEB_SELECT;
 901
 902                 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 903                         /* don't miss out required setting for eDP */
 904                         if (adjusted_mode->clock < 200000)
 905                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 906                         else
 907                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 908                 }
 909         } else {
 910                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 911         }
 912
 913         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 914                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 915 }
 916
 917 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 918 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 919
 920 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 921 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 922
 923 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 924 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 925
 926 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 927                                        u32 mask,
 928                                        u32 value)
 929 {
 930         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932         u32 pp_stat_reg, pp_ctrl_reg;
 933
 934         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 935         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 936
 937         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 938                         mask, value,
 939                         I915_READ(pp_stat_reg),
 940                         I915_READ(pp_ctrl_reg));
 941
 942         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 943                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 944                                 I915_READ(pp_stat_reg),
 945                                 I915_READ(pp_ctrl_reg));
 946         }
 947 }
 948
 949 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 950 {
 951         DRM_DEBUG_KMS("Wait for panel power on\n");
 952         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 953 }
 954
 955 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 956 {
 957         DRM_DEBUG_KMS("Wait for panel power off time\n");
 958         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 959 }
 960
 961 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 962 {
 963         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 964         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 965 }
 966
 967
 968 /* Read the current pp_control value, unlocking the register if it
 969  * is locked
 970  */
 971
 972 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 973 {
 974         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 975         struct drm_i915_private *dev_priv = dev->dev_private;
 976         u32 control;
 977         u32 pp_ctrl_reg;
 978
 979         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 980         control = I915_READ(pp_ctrl_reg);
 981
 982         control &= ~PANEL_UNLOCK_MASK;
 983         control |= PANEL_UNLOCK_REGS;
 984         return control;
 985 }
 986
 987 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 988 {
 989         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         u32 pp;
 992         u32 pp_stat_reg, pp_ctrl_reg;
 993
 994         if (!is_edp(intel_dp))
 995                 return;
 996         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 997
 998         WARN(intel_dp->want_panel_vdd,
 999              "eDP VDD already requested on\n");
1000
1001         intel_dp->want_panel_vdd = true;
1002
1003         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1004                 DRM_DEBUG_KMS("eDP VDD already on\n");
1005                 return;
1006         }
1007
1008         if (!ironlake_edp_have_panel_power(intel_dp))
1009                 ironlake_wait_panel_power_cycle(intel_dp);
1010
1011         pp = ironlake_get_pp_control(intel_dp);
1012         pp |= EDP_FORCE_VDD;
1013
1014         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1015         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1016
1017         I915_WRITE(pp_ctrl_reg, pp);
1018         POSTING_READ(pp_ctrl_reg);
1019         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1020                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1021         /*
1022          * If the panel wasn't on, delay before accessing aux channel
1023          */
1024         if (!ironlake_edp_have_panel_power(intel_dp)) {
1025                 DRM_DEBUG_KMS("eDP was not running\n");
1026                 msleep(intel_dp->panel_power_up_delay);
1027         }
1028 }
1029
1030 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1031 {
1032         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1033         struct drm_i915_private *dev_priv = dev->dev_private;
1034         u32 pp;
1035         u32 pp_stat_reg, pp_ctrl_reg;
1036
1037         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1038
1039         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1040                 pp = ironlake_get_pp_control(intel_dp);
1041                 pp &= ~EDP_FORCE_VDD;
1042
1043                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1044                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1045
1046                 I915_WRITE(pp_ctrl_reg, pp);
1047                 POSTING_READ(pp_ctrl_reg);
1048
1049                 /* Make sure sequencer is idle before allowing subsequent activity */
1050                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1051                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1052                 msleep(intel_dp->panel_power_down_delay);
1053         }
1054 }
1055
1056 static void ironlake_panel_vdd_work(struct work_struct *__work)
1057 {
1058         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1059                                                  struct intel_dp, panel_vdd_work);
1060         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1061
1062         mutex_lock(&dev->mode_config.mutex);
1063         ironlake_panel_vdd_off_sync(intel_dp);
1064         mutex_unlock(&dev->mode_config.mutex);
1065 }
1066
1067 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1068 {
1069         if (!is_edp(intel_dp))
1070                 return;
1071
1072         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1073         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1074
1075         intel_dp->want_panel_vdd = false;
1076
1077         if (sync) {
1078                 ironlake_panel_vdd_off_sync(intel_dp);
1079         } else {
1080                 /*
1081                  * Queue the timer to fire a long
1082                  * time from now (relative to the power down delay)
1083                  * to keep the panel power up across a sequence of operations
1084                  */
1085                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1086                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1087         }
1088 }
1089
1090 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1091 {
1092         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         u32 pp;
1095         u32 pp_ctrl_reg;
1096
1097         if (!is_edp(intel_dp))
1098                 return;
1099
1100         DRM_DEBUG_KMS("Turn eDP power on\n");
1101
1102         if (ironlake_edp_have_panel_power(intel_dp)) {
1103                 DRM_DEBUG_KMS("eDP power already on\n");
1104                 return;
1105         }
1106
1107         ironlake_wait_panel_power_cycle(intel_dp);
1108
1109         pp = ironlake_get_pp_control(intel_dp);
1110         if (IS_GEN5(dev)) {
1111                 /* ILK workaround: disable reset around power sequence */
1112                 pp &= ~PANEL_POWER_RESET;
1113                 I915_WRITE(PCH_PP_CONTROL, pp);
1114                 POSTING_READ(PCH_PP_CONTROL);
1115         }
1116
1117         pp |= POWER_TARGET_ON;
1118         if (!IS_GEN5(dev))
1119                 pp |= PANEL_POWER_RESET;
1120
1121         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1122
1123         I915_WRITE(pp_ctrl_reg, pp);
1124         POSTING_READ(pp_ctrl_reg);
1125
1126         ironlake_wait_panel_on(intel_dp);
1127
1128         if (IS_GEN5(dev)) {
1129                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1130                 I915_WRITE(PCH_PP_CONTROL, pp);
1131                 POSTING_READ(PCH_PP_CONTROL);
1132         }
1133 }
1134
1135 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1136 {
1137         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         u32 pp;
1140         u32 pp_ctrl_reg;
1141
1142         if (!is_edp(intel_dp))
1143                 return;
1144
1145         DRM_DEBUG_KMS("Turn eDP power off\n");
1146
1147         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1148
1149         pp = ironlake_get_pp_control(intel_dp);
1150         /* We need to switch off panel power _and_ force vdd, for otherwise some
1151          * panels get very unhappy and cease to work. */
1152         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1153
1154         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1155
1156         I915_WRITE(pp_ctrl_reg, pp);
1157         POSTING_READ(pp_ctrl_reg);
1158
1159         intel_dp->want_panel_vdd = false;
1160
1161         ironlake_wait_panel_off(intel_dp);
1162 }
1163
1164 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1165 {
1166         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1167         struct drm_device *dev = intel_dig_port->base.base.dev;
1168         struct drm_i915_private *dev_priv = dev->dev_private;
1169         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1170         u32 pp;
1171         u32 pp_ctrl_reg;
1172
1173         if (!is_edp(intel_dp))
1174                 return;
1175
1176         DRM_DEBUG_KMS("\n");
1177         /*
1178          * If we enable the backlight right away following a panel power
1179          * on, we may see slight flicker as the panel syncs with the eDP
1180          * link.  So delay a bit to make sure the image is solid before
1181          * allowing it to appear.
1182          */
1183         msleep(intel_dp->backlight_on_delay);
1184         pp = ironlake_get_pp_control(intel_dp);
1185         pp |= EDP_BLC_ENABLE;
1186
1187         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1188
1189         I915_WRITE(pp_ctrl_reg, pp);
1190         POSTING_READ(pp_ctrl_reg);
1191
1192         intel_panel_enable_backlight(dev, pipe);
1193 }
1194
1195 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1196 {
1197         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 pp;
1200         u32 pp_ctrl_reg;
1201
1202         if (!is_edp(intel_dp))
1203                 return;
1204
1205         intel_panel_disable_backlight(dev);
1206
1207         DRM_DEBUG_KMS("\n");
1208         pp = ironlake_get_pp_control(intel_dp);
1209         pp &= ~EDP_BLC_ENABLE;
1210
1211         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1212
1213         I915_WRITE(pp_ctrl_reg, pp);
1214         POSTING_READ(pp_ctrl_reg);
1215         msleep(intel_dp->backlight_off_delay);
1216 }
1217
1218 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1219 {
1220         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222         struct drm_device *dev = crtc->dev;
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         u32 dpa_ctl;
1225
1226         assert_pipe_disabled(dev_priv,
1227                              to_intel_crtc(crtc)->pipe);
1228
1229         DRM_DEBUG_KMS("\n");
1230         dpa_ctl = I915_READ(DP_A);
1231         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1232         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234         /* We don't adjust intel_dp->DP while tearing down the link, to
1235          * facilitate link retraining (e.g. after hotplug). Hence clear all
1236          * enable bits here to ensure that we don't enable too much. */
1237         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1238         intel_dp->DP |= DP_PLL_ENABLE;
1239         I915_WRITE(DP_A, intel_dp->DP);
1240         POSTING_READ(DP_A);
1241         udelay(200);
1242 }
1243
1244 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1245 {
1246         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1247         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1248         struct drm_device *dev = crtc->dev;
1249         struct drm_i915_private *dev_priv = dev->dev_private;
1250         u32 dpa_ctl;
1251
1252         assert_pipe_disabled(dev_priv,
1253                              to_intel_crtc(crtc)->pipe);
1254
1255         dpa_ctl = I915_READ(DP_A);
1256         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1257              "dp pll off, should be on\n");
1258         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1259
1260         /* We can't rely on the value tracked for the DP register in
1261          * intel_dp->DP because link_down must not change that (otherwise link
1262          * re-training will fail. */
1263         dpa_ctl &= ~DP_PLL_ENABLE;
1264         I915_WRITE(DP_A, dpa_ctl);
1265         POSTING_READ(DP_A);
1266         udelay(200);
1267 }
1268
1269 /* If the sink supports it, try to set the power state appropriately */
1270 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1271 {
1272         int ret, i;
1273
1274         /* Should have a valid DPCD by this point */
1275         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1276                 return;
1277
1278         if (mode != DRM_MODE_DPMS_ON) {
1279                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1280                                                   DP_SET_POWER_D3);
1281                 if (ret != 1)
1282                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1283         } else {
1284                 /*
1285                  * When turning on, we need to retry for 1ms to give the sink
1286                  * time to wake up.
1287                  */
1288                 for (i = 0; i < 3; i++) {
1289                         ret = intel_dp_aux_native_write_1(intel_dp,
1290                                                           DP_SET_POWER,
1291                                                           DP_SET_POWER_D0);
1292                         if (ret == 1)
1293                                 break;
1294                         msleep(1);
1295                 }
1296         }
1297 }
1298
1299 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1300                                   enum pipe *pipe)
1301 {
1302         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1303         struct drm_device *dev = encoder->base.dev;
1304         struct drm_i915_private *dev_priv = dev->dev_private;
1305         u32 tmp = I915_READ(intel_dp->output_reg);
1306
1307         if (!(tmp & DP_PORT_EN))
1308                 return false;
1309
1310         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1311                 *pipe = PORT_TO_PIPE_CPT(tmp);
1312         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1313                 *pipe = PORT_TO_PIPE(tmp);
1314         } else {
1315                 u32 trans_sel;
1316                 u32 trans_dp;
1317                 int i;
1318
1319                 switch (intel_dp->output_reg) {
1320                 case PCH_DP_B:
1321                         trans_sel = TRANS_DP_PORT_SEL_B;
1322                         break;
1323                 case PCH_DP_C:
1324                         trans_sel = TRANS_DP_PORT_SEL_C;
1325                         break;
1326                 case PCH_DP_D:
1327                         trans_sel = TRANS_DP_PORT_SEL_D;
1328                         break;
1329                 default:
1330                         return true;
1331                 }
1332
1333                 for_each_pipe(i) {
1334                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1335                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1336                                 *pipe = i;
1337                                 return true;
1338                         }
1339                 }
1340
1341                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342                               intel_dp->output_reg);
1343         }
1344
1345         return true;
1346 }
1347
1348 static void intel_disable_dp(struct intel_encoder *encoder)
1349 {
1350         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1351
1352         /* Make sure the panel is off before trying to change the mode. But also
1353          * ensure that we have vdd while we switch off the panel. */
1354         ironlake_edp_panel_vdd_on(intel_dp);
1355         ironlake_edp_backlight_off(intel_dp);
1356         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1357         ironlake_edp_panel_off(intel_dp);
1358
1359         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1360         if (!is_cpu_edp(intel_dp))
1361                 intel_dp_link_down(intel_dp);
1362 }
1363
1364 static void intel_post_disable_dp(struct intel_encoder *encoder)
1365 {
1366         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1367         struct drm_device *dev = encoder->base.dev;
1368
1369         if (is_cpu_edp(intel_dp)) {
1370                 intel_dp_link_down(intel_dp);
1371                 if (!IS_VALLEYVIEW(dev))
1372                         ironlake_edp_pll_off(intel_dp);
1373         }
1374 }
1375
1376 static void intel_enable_dp(struct intel_encoder *encoder)
1377 {
1378         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379         struct drm_device *dev = encoder->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1382
1383         if (WARN_ON(dp_reg & DP_PORT_EN))
1384                 return;
1385
1386         ironlake_edp_panel_vdd_on(intel_dp);
1387         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1388         intel_dp_start_link_train(intel_dp);
1389         ironlake_edp_panel_on(intel_dp);
1390         ironlake_edp_panel_vdd_off(intel_dp, true);
1391         intel_dp_complete_link_train(intel_dp);
1392         ironlake_edp_backlight_on(intel_dp);
1393 }
1394
1395 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1396 {
1397         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1398         struct drm_device *dev = encoder->base.dev;
1399
1400         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1401                 ironlake_edp_pll_on(intel_dp);
1402 }
1403
1404 /*
1405  * Native read with retry for link status and receiver capability reads for
1406  * cases where the sink may still be asleep.
1407  */
1408 static bool
1409 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1410                                uint8_t *recv, int recv_bytes)
1411 {
1412         int ret, i;
1413
1414         /*
1415          * Sinks are *supposed* to come up within 1ms from an off state,
1416          * but we're also supposed to retry 3 times per the spec.
1417          */
1418         for (i = 0; i < 3; i++) {
1419                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1420                                                recv_bytes);
1421                 if (ret == recv_bytes)
1422                         return true;
1423                 msleep(1);
1424         }
1425
1426         return false;
1427 }
1428
1429 /*
1430  * Fetch AUX CH registers 0x202 - 0x207 which contain
1431  * link status information
1432  */
1433 static bool
1434 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1435 {
1436         return intel_dp_aux_native_read_retry(intel_dp,
1437                                               DP_LANE0_1_STATUS,
1438                                               link_status,
1439                                               DP_LINK_STATUS_SIZE);
1440 }
1441
1442 #if 0
1443 static char     *voltage_names[] = {
1444         "0.4V", "0.6V", "0.8V", "1.2V"
1445 };
1446 static char     *pre_emph_names[] = {
1447         "0dB", "3.5dB", "6dB", "9.5dB"
1448 };
1449 static char     *link_train_names[] = {
1450         "pattern 1", "pattern 2", "idle", "off"
1451 };
1452 #endif
1453
1454 /*
1455  * These are source-specific values; current Intel hardware supports
1456  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1457  */
1458
1459 static uint8_t
1460 intel_dp_voltage_max(struct intel_dp *intel_dp)
1461 {
1462         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1463
1464         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1465                 return DP_TRAIN_VOLTAGE_SWING_800;
1466         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1467                 return DP_TRAIN_VOLTAGE_SWING_1200;
1468         else
1469                 return DP_TRAIN_VOLTAGE_SWING_800;
1470 }
1471
1472 static uint8_t
1473 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1474 {
1475         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1476
1477         if (HAS_DDI(dev)) {
1478                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1479                 case DP_TRAIN_VOLTAGE_SWING_400:
1480                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1481                 case DP_TRAIN_VOLTAGE_SWING_600:
1482                         return DP_TRAIN_PRE_EMPHASIS_6;
1483                 case DP_TRAIN_VOLTAGE_SWING_800:
1484                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1485                 case DP_TRAIN_VOLTAGE_SWING_1200:
1486                 default:
1487                         return DP_TRAIN_PRE_EMPHASIS_0;
1488                 }
1489         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1490                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491                 case DP_TRAIN_VOLTAGE_SWING_400:
1492                         return DP_TRAIN_PRE_EMPHASIS_6;
1493                 case DP_TRAIN_VOLTAGE_SWING_600:
1494                 case DP_TRAIN_VOLTAGE_SWING_800:
1495                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1496                 default:
1497                         return DP_TRAIN_PRE_EMPHASIS_0;
1498                 }
1499         } else {
1500                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1501                 case DP_TRAIN_VOLTAGE_SWING_400:
1502                         return DP_TRAIN_PRE_EMPHASIS_6;
1503                 case DP_TRAIN_VOLTAGE_SWING_600:
1504                         return DP_TRAIN_PRE_EMPHASIS_6;
1505                 case DP_TRAIN_VOLTAGE_SWING_800:
1506                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1507                 case DP_TRAIN_VOLTAGE_SWING_1200:
1508                 default:
1509                         return DP_TRAIN_PRE_EMPHASIS_0;
1510                 }
1511         }
1512 }
1513
1514 static void
1515 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1516 {
1517         uint8_t v = 0;
1518         uint8_t p = 0;
1519         int lane;
1520         uint8_t voltage_max;
1521         uint8_t preemph_max;
1522
1523         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1524                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1525                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1526
1527                 if (this_v > v)
1528                         v = this_v;
1529                 if (this_p > p)
1530                         p = this_p;
1531         }
1532
1533         voltage_max = intel_dp_voltage_max(intel_dp);
1534         if (v >= voltage_max)
1535                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1536
1537         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1538         if (p >= preemph_max)
1539                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1540
1541         for (lane = 0; lane < 4; lane++)
1542                 intel_dp->train_set[lane] = v | p;
1543 }
1544
1545 static uint32_t
1546 intel_gen4_signal_levels(uint8_t train_set)
1547 {
1548         uint32_t        signal_levels = 0;
1549
1550         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1551         case DP_TRAIN_VOLTAGE_SWING_400:
1552         default:
1553                 signal_levels |= DP_VOLTAGE_0_4;
1554                 break;
1555         case DP_TRAIN_VOLTAGE_SWING_600:
1556                 signal_levels |= DP_VOLTAGE_0_6;
1557                 break;
1558         case DP_TRAIN_VOLTAGE_SWING_800:
1559                 signal_levels |= DP_VOLTAGE_0_8;
1560                 break;
1561         case DP_TRAIN_VOLTAGE_SWING_1200:
1562                 signal_levels |= DP_VOLTAGE_1_2;
1563                 break;
1564         }
1565         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1566         case DP_TRAIN_PRE_EMPHASIS_0:
1567         default:
1568                 signal_levels |= DP_PRE_EMPHASIS_0;
1569                 break;
1570         case DP_TRAIN_PRE_EMPHASIS_3_5:
1571                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1572                 break;
1573         case DP_TRAIN_PRE_EMPHASIS_6:
1574                 signal_levels |= DP_PRE_EMPHASIS_6;
1575                 break;
1576         case DP_TRAIN_PRE_EMPHASIS_9_5:
1577                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1578                 break;
1579         }
1580         return signal_levels;
1581 }
1582
1583 /* Gen6's DP voltage swing and pre-emphasis control */
1584 static uint32_t
1585 intel_gen6_edp_signal_levels(uint8_t train_set)
1586 {
1587         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1588                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1589         switch (signal_levels) {
1590         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1591         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1592                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1593         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1595         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1596         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1597                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1598         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1599         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1600                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1601         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1602         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1603                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1604         default:
1605                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606                               "0x%x\n", signal_levels);
1607                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1608         }
1609 }
1610
1611 /* Gen7's DP voltage swing and pre-emphasis control */
1612 static uint32_t
1613 intel_gen7_edp_signal_levels(uint8_t train_set)
1614 {
1615         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1616                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1617         switch (signal_levels) {
1618         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1619                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1620         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1621                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1622         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1623                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1624
1625         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1626                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1627         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1628                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1629
1630         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1631                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1632         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1633                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1634
1635         default:
1636                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1637                               "0x%x\n", signal_levels);
1638                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1639         }
1640 }
1641
1642 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1643 static uint32_t
1644 intel_hsw_signal_levels(uint8_t train_set)
1645 {
1646         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1647                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1648         switch (signal_levels) {
1649         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1650                 return DDI_BUF_EMP_400MV_0DB_HSW;
1651         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1653         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1654                 return DDI_BUF_EMP_400MV_6DB_HSW;
1655         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1656                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1657
1658         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1659                 return DDI_BUF_EMP_600MV_0DB_HSW;
1660         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1662         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1663                 return DDI_BUF_EMP_600MV_6DB_HSW;
1664
1665         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1666                 return DDI_BUF_EMP_800MV_0DB_HSW;
1667         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1668                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1669         default:
1670                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1671                               "0x%x\n", signal_levels);
1672                 return DDI_BUF_EMP_400MV_0DB_HSW;
1673         }
1674 }
1675
1676 /* Properly updates "DP" with the correct signal levels. */
1677 static void
1678 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1679 {
1680         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1681         struct drm_device *dev = intel_dig_port->base.base.dev;
1682         uint32_t signal_levels, mask;
1683         uint8_t train_set = intel_dp->train_set[0];
1684
1685         if (HAS_DDI(dev)) {
1686                 signal_levels = intel_hsw_signal_levels(train_set);
1687                 mask = DDI_BUF_EMP_MASK;
1688         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1689                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1690                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1691         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1692                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1693                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1694         } else {
1695                 signal_levels = intel_gen4_signal_levels(train_set);
1696                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1697         }
1698
1699         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1700
1701         *DP = (*DP & ~mask) | signal_levels;
1702 }
1703
1704 static bool
1705 intel_dp_set_link_train(struct intel_dp *intel_dp,
1706                         uint32_t dp_reg_value,
1707                         uint8_t dp_train_pat)
1708 {
1709         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1710         struct drm_device *dev = intel_dig_port->base.base.dev;
1711         struct drm_i915_private *dev_priv = dev->dev_private;
1712         enum port port = intel_dig_port->port;
1713         int ret;
1714         uint32_t temp;
1715
1716         if (HAS_DDI(dev)) {
1717                 temp = I915_READ(DP_TP_CTL(port));
1718
1719                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1720                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1721                 else
1722                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1723
1724                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1725                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1726                 case DP_TRAINING_PATTERN_DISABLE:
1727
1728                         if (port != PORT_A) {
1729                                 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1730                                 I915_WRITE(DP_TP_CTL(port), temp);
1731
1732                                 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1733                                               DP_TP_STATUS_IDLE_DONE), 1))
1734                                         DRM_ERROR("Timed out waiting for DP idle patterns\n");
1735
1736                                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1737                         }
1738
1739                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1740
1741                         break;
1742                 case DP_TRAINING_PATTERN_1:
1743                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1744                         break;
1745                 case DP_TRAINING_PATTERN_2:
1746                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1747                         break;
1748                 case DP_TRAINING_PATTERN_3:
1749                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1750                         break;
1751                 }
1752                 I915_WRITE(DP_TP_CTL(port), temp);
1753
1754         } else if (HAS_PCH_CPT(dev) &&
1755                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1756                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1757
1758                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1759                 case DP_TRAINING_PATTERN_DISABLE:
1760                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1761                         break;
1762                 case DP_TRAINING_PATTERN_1:
1763                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1764                         break;
1765                 case DP_TRAINING_PATTERN_2:
1766                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1767                         break;
1768                 case DP_TRAINING_PATTERN_3:
1769                         DRM_ERROR("DP training pattern 3 not supported\n");
1770                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1771                         break;
1772                 }
1773
1774         } else {
1775                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1776
1777                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1778                 case DP_TRAINING_PATTERN_DISABLE:
1779                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1780                         break;
1781                 case DP_TRAINING_PATTERN_1:
1782                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1783                         break;
1784                 case DP_TRAINING_PATTERN_2:
1785                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1786                         break;
1787                 case DP_TRAINING_PATTERN_3:
1788                         DRM_ERROR("DP training pattern 3 not supported\n");
1789                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1790                         break;
1791                 }
1792         }
1793
1794         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1795         POSTING_READ(intel_dp->output_reg);
1796
1797         intel_dp_aux_native_write_1(intel_dp,
1798                                     DP_TRAINING_PATTERN_SET,
1799                                     dp_train_pat);
1800
1801         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1802             DP_TRAINING_PATTERN_DISABLE) {
1803                 ret = intel_dp_aux_native_write(intel_dp,
1804                                                 DP_TRAINING_LANE0_SET,
1805                                                 intel_dp->train_set,
1806                                                 intel_dp->lane_count);
1807                 if (ret != intel_dp->lane_count)
1808                         return false;
1809         }
1810
1811         return true;
1812 }
1813
1814 /* Enable corresponding port and start training pattern 1 */
1815 void
1816 intel_dp_start_link_train(struct intel_dp *intel_dp)
1817 {
1818         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1819         struct drm_device *dev = encoder->dev;
1820         int i;
1821         uint8_t voltage;
1822         bool clock_recovery = false;
1823         int voltage_tries, loop_tries;
1824         uint32_t DP = intel_dp->DP;
1825
1826         if (HAS_DDI(dev))
1827                 intel_ddi_prepare_link_retrain(encoder);
1828
1829         /* Write the link configuration data */
1830         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1831                                   intel_dp->link_configuration,
1832                                   DP_LINK_CONFIGURATION_SIZE);
1833
1834         DP |= DP_PORT_EN;
1835
1836         memset(intel_dp->train_set, 0, 4);
1837         voltage = 0xff;
1838         voltage_tries = 0;
1839         loop_tries = 0;
1840         clock_recovery = false;
1841         for (;;) {
1842                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1843                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1844
1845                 intel_dp_set_signal_levels(intel_dp, &DP);
1846
1847                 /* Set training pattern 1 */
1848                 if (!intel_dp_set_link_train(intel_dp, DP,
1849                                              DP_TRAINING_PATTERN_1 |
1850                                              DP_LINK_SCRAMBLING_DISABLE))
1851                         break;
1852
1853                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1854                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1855                         DRM_ERROR("failed to get link status\n");
1856                         break;
1857                 }
1858
1859                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1860                         DRM_DEBUG_KMS("clock recovery OK\n");
1861                         clock_recovery = true;
1862                         break;
1863                 }
1864
1865                 /* Check to see if we've tried the max voltage */
1866                 for (i = 0; i < intel_dp->lane_count; i++)
1867                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1868                                 break;
1869                 if (i == intel_dp->lane_count) {
1870                         ++loop_tries;
1871                         if (loop_tries == 5) {
1872                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1873                                 break;
1874                         }
1875                         memset(intel_dp->train_set, 0, 4);
1876                         voltage_tries = 0;
1877                         continue;
1878                 }
1879
1880                 /* Check to see if we've tried the same voltage 5 times */
1881                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1882                         ++voltage_tries;
1883                         if (voltage_tries == 5) {
1884                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1885                                 break;
1886                         }
1887                 } else
1888                         voltage_tries = 0;
1889                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1890
1891                 /* Compute new intel_dp->train_set as requested by target */
1892                 intel_get_adjust_train(intel_dp, link_status);
1893         }
1894
1895         intel_dp->DP = DP;
1896 }
1897
1898 void
1899 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1900 {
1901         bool channel_eq = false;
1902         int tries, cr_tries;
1903         uint32_t DP = intel_dp->DP;
1904
1905         /* channel equalization */
1906         tries = 0;
1907         cr_tries = 0;
1908         channel_eq = false;
1909         for (;;) {
1910                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1911
1912                 if (cr_tries > 5) {
1913                         DRM_ERROR("failed to train DP, aborting\n");
1914                         intel_dp_link_down(intel_dp);
1915                         break;
1916                 }
1917
1918                 intel_dp_set_signal_levels(intel_dp, &DP);
1919
1920                 /* channel eq pattern */
1921                 if (!intel_dp_set_link_train(intel_dp, DP,
1922                                              DP_TRAINING_PATTERN_2 |
1923                                              DP_LINK_SCRAMBLING_DISABLE))
1924                         break;
1925
1926                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1927                 if (!intel_dp_get_link_status(intel_dp, link_status))
1928                         break;
1929
1930                 /* Make sure clock is still ok */
1931                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1932                         intel_dp_start_link_train(intel_dp);
1933                         cr_tries++;
1934                         continue;
1935                 }
1936
1937                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1938                         channel_eq = true;
1939                         break;
1940                 }
1941
1942                 /* Try 5 times, then try clock recovery if that fails */
1943                 if (tries > 5) {
1944                         intel_dp_link_down(intel_dp);
1945                         intel_dp_start_link_train(intel_dp);
1946                         tries = 0;
1947                         cr_tries++;
1948                         continue;
1949                 }
1950
1951                 /* Compute new intel_dp->train_set as requested by target */
1952                 intel_get_adjust_train(intel_dp, link_status);
1953                 ++tries;
1954         }
1955
1956         if (channel_eq)
1957                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
1958
1959         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1960 }
1961
1962 static void
1963 intel_dp_link_down(struct intel_dp *intel_dp)
1964 {
1965         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1966         struct drm_device *dev = intel_dig_port->base.base.dev;
1967         struct drm_i915_private *dev_priv = dev->dev_private;
1968         struct intel_crtc *intel_crtc =
1969                 to_intel_crtc(intel_dig_port->base.base.crtc);
1970         uint32_t DP = intel_dp->DP;
1971
1972         /*
1973          * DDI code has a strict mode set sequence and we should try to respect
1974          * it, otherwise we might hang the machine in many different ways. So we
1975          * really should be disabling the port only on a complete crtc_disable
1976          * sequence. This function is just called under two conditions on DDI
1977          * code:
1978          * - Link train failed while doing crtc_enable, and on this case we
1979          *   really should respect the mode set sequence and wait for a
1980          *   crtc_disable.
1981          * - Someone turned the monitor off and intel_dp_check_link_status
1982          *   called us. We don't need to disable the whole port on this case, so
1983          *   when someone turns the monitor on again,
1984          *   intel_ddi_prepare_link_retrain will take care of redoing the link
1985          *   train.
1986          */
1987         if (HAS_DDI(dev))
1988                 return;
1989
1990         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1991                 return;
1992
1993         DRM_DEBUG_KMS("\n");
1994
1995         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1996                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1997                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1998         } else {
1999                 DP &= ~DP_LINK_TRAIN_MASK;
2000                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2001         }
2002         POSTING_READ(intel_dp->output_reg);
2003
2004         /* We don't really know why we're doing this */
2005         intel_wait_for_vblank(dev, intel_crtc->pipe);
2006
2007         if (HAS_PCH_IBX(dev) &&
2008             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2009                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2010
2011                 /* Hardware workaround: leaving our transcoder select
2012                  * set to transcoder B while it's off will prevent the
2013                  * corresponding HDMI output on transcoder A.
2014                  *
2015                  * Combine this with another hardware workaround:
2016                  * transcoder select bit can only be cleared while the
2017                  * port is enabled.
2018                  */
2019                 DP &= ~DP_PIPEB_SELECT;
2020                 I915_WRITE(intel_dp->output_reg, DP);
2021
2022                 /* Changes to enable or select take place the vblank
2023                  * after being written.
2024                  */
2025                 if (WARN_ON(crtc == NULL)) {
2026                         /* We should never try to disable a port without a crtc
2027                          * attached. For paranoia keep the code around for a
2028                          * bit. */
2029                         POSTING_READ(intel_dp->output_reg);
2030                         msleep(50);
2031                 } else
2032                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2033         }
2034
2035         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2036         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2037         POSTING_READ(intel_dp->output_reg);
2038         msleep(intel_dp->panel_power_down_delay);
2039 }
2040
2041 static bool
2042 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2043 {
2044         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2045
2046         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2047                                            sizeof(intel_dp->dpcd)) == 0)
2048                 return false; /* aux transfer failed */
2049
2050         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2051                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2052         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2053
2054         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2055                 return false; /* DPCD not present */
2056
2057         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2058               DP_DWN_STRM_PORT_PRESENT))
2059                 return true; /* native DP sink */
2060
2061         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2062                 return true; /* no per-port downstream info */
2063
2064         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2065                                            intel_dp->downstream_ports,
2066                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2067                 return false; /* downstream port status fetch failed */
2068
2069         return true;
2070 }
2071
2072 static void
2073 intel_dp_probe_oui(struct intel_dp *intel_dp)
2074 {
2075         u8 buf[3];
2076
2077         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2078                 return;
2079
2080         ironlake_edp_panel_vdd_on(intel_dp);
2081
2082         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2083                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2084                               buf[0], buf[1], buf[2]);
2085
2086         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2087                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2088                               buf[0], buf[1], buf[2]);
2089
2090         ironlake_edp_panel_vdd_off(intel_dp, false);
2091 }
2092
2093 static bool
2094 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2095 {
2096         int ret;
2097
2098         ret = intel_dp_aux_native_read_retry(intel_dp,
2099                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2100                                              sink_irq_vector, 1);
2101         if (!ret)
2102                 return false;
2103
2104         return true;
2105 }
2106
2107 static void
2108 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2109 {
2110         /* NAK by default */
2111         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2112 }
2113
2114 /*
2115  * According to DP spec
2116  * 5.1.2:
2117  *  1. Read DPCD
2118  *  2. Configure link according to Receiver Capabilities
2119  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2120  *  4. Check link status on receipt of hot-plug interrupt
2121  */
2122
2123 void
2124 intel_dp_check_link_status(struct intel_dp *intel_dp)
2125 {
2126         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2127         u8 sink_irq_vector;
2128         u8 link_status[DP_LINK_STATUS_SIZE];
2129
2130         if (!intel_encoder->connectors_active)
2131                 return;
2132
2133         if (WARN_ON(!intel_encoder->base.crtc))
2134                 return;
2135
2136         /* Try to read receiver status if the link appears to be up */
2137         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2138                 intel_dp_link_down(intel_dp);
2139                 return;
2140         }
2141
2142         /* Now read the DPCD to see if it's actually running */
2143         if (!intel_dp_get_dpcd(intel_dp)) {
2144                 intel_dp_link_down(intel_dp);
2145                 return;
2146         }
2147
2148         /* Try to read the source of the interrupt */
2149         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2150             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2151                 /* Clear interrupt source */
2152                 intel_dp_aux_native_write_1(intel_dp,
2153                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2154                                             sink_irq_vector);
2155
2156                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2157                         intel_dp_handle_test_request(intel_dp);
2158                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2159                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2160         }
2161
2162         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2163                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2164                               drm_get_encoder_name(&intel_encoder->base));
2165                 intel_dp_start_link_train(intel_dp);
2166                 intel_dp_complete_link_train(intel_dp);
2167         }
2168 }
2169
2170 /* XXX this is probably wrong for multiple downstream ports */
2171 static enum drm_connector_status
2172 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2173 {
2174         uint8_t *dpcd = intel_dp->dpcd;
2175         bool hpd;
2176         uint8_t type;
2177
2178         if (!intel_dp_get_dpcd(intel_dp))
2179                 return connector_status_disconnected;
2180
2181         /* if there's no downstream port, we're done */
2182         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2183                 return connector_status_connected;
2184
2185         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2186         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2187         if (hpd) {
2188                 uint8_t reg;
2189                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2190                                                     &reg, 1))
2191                         return connector_status_unknown;
2192                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2193                                               : connector_status_disconnected;
2194         }
2195
2196         /* If no HPD, poke DDC gently */
2197         if (drm_probe_ddc(&intel_dp->adapter))
2198                 return connector_status_connected;
2199
2200         /* Well we tried, say unknown for unreliable port types */
2201         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2202         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2203                 return connector_status_unknown;
2204
2205         /* Anything else is out of spec, warn and ignore */
2206         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2207         return connector_status_disconnected;
2208 }
2209
2210 static enum drm_connector_status
2211 ironlake_dp_detect(struct intel_dp *intel_dp)
2212 {
2213         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2214         struct drm_i915_private *dev_priv = dev->dev_private;
2215         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2216         enum drm_connector_status status;
2217
2218         /* Can't disconnect eDP, but you can close the lid... */
2219         if (is_edp(intel_dp)) {
2220                 status = intel_panel_detect(dev);
2221                 if (status == connector_status_unknown)
2222                         status = connector_status_connected;
2223                 return status;
2224         }
2225
2226         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2227                 return connector_status_disconnected;
2228
2229         return intel_dp_detect_dpcd(intel_dp);
2230 }
2231
2232 static enum drm_connector_status
2233 g4x_dp_detect(struct intel_dp *intel_dp)
2234 {
2235         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2236         struct drm_i915_private *dev_priv = dev->dev_private;
2237         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2238         uint32_t bit;
2239
2240         /* Can't disconnect eDP, but you can close the lid... */
2241         if (is_edp(intel_dp)) {
2242                 enum drm_connector_status status;
2243
2244                 status = intel_panel_detect(dev);
2245                 if (status == connector_status_unknown)
2246                         status = connector_status_connected;
2247                 return status;
2248         }
2249
2250         switch (intel_dig_port->port) {
2251         case PORT_B:
2252                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2253                 break;
2254         case PORT_C:
2255                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2256                 break;
2257         case PORT_D:
2258                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2259                 break;
2260         default:
2261                 return connector_status_unknown;
2262         }
2263
2264         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2265                 return connector_status_disconnected;
2266
2267         return intel_dp_detect_dpcd(intel_dp);
2268 }
2269
2270 static struct edid *
2271 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2272 {
2273         struct intel_connector *intel_connector = to_intel_connector(connector);
2274
2275         /* use cached edid if we have one */
2276         if (intel_connector->edid) {
2277                 struct edid *edid;
2278                 int size;
2279
2280                 /* invalid edid */
2281                 if (IS_ERR(intel_connector->edid))
2282                         return NULL;
2283
2284                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2285                 edid = kmalloc(size, GFP_KERNEL);
2286                 if (!edid)
2287                         return NULL;
2288
2289                 memcpy(edid, intel_connector->edid, size);
2290                 return edid;
2291         }
2292
2293         return drm_get_edid(connector, adapter);
2294 }
2295
2296 static int
2297 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2298 {
2299         struct intel_connector *intel_connector = to_intel_connector(connector);
2300
2301         /* use cached edid if we have one */
2302         if (intel_connector->edid) {
2303                 /* invalid edid */
2304                 if (IS_ERR(intel_connector->edid))
2305                         return 0;
2306
2307                 return intel_connector_update_modes(connector,
2308                                                     intel_connector->edid);
2309         }
2310
2311         return intel_ddc_get_modes(connector, adapter);
2312 }
2313
2314 static enum drm_connector_status
2315 intel_dp_detect(struct drm_connector *connector, bool force)
2316 {
2317         struct intel_dp *intel_dp = intel_attached_dp(connector);
2318         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2319         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2320         struct drm_device *dev = connector->dev;
2321         enum drm_connector_status status;
2322         struct edid *edid = NULL;
2323
2324         intel_dp->has_audio = false;
2325
2326         if (HAS_PCH_SPLIT(dev))
2327                 status = ironlake_dp_detect(intel_dp);
2328         else
2329                 status = g4x_dp_detect(intel_dp);
2330
2331         if (status != connector_status_connected)
2332                 return status;
2333
2334         intel_dp_probe_oui(intel_dp);
2335
2336         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2337                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2338         } else {
2339                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2340                 if (edid) {
2341                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2342                         kfree(edid);
2343                 }
2344         }
2345
2346         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2347                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2348         return connector_status_connected;
2349 }
2350
2351 static int intel_dp_get_modes(struct drm_connector *connector)
2352 {
2353         struct intel_dp *intel_dp = intel_attached_dp(connector);
2354         struct intel_connector *intel_connector = to_intel_connector(connector);
2355         struct drm_device *dev = connector->dev;
2356         int ret;
2357
2358         /* We should parse the EDID data and find out if it has an audio sink
2359          */
2360
2361         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2362         if (ret)
2363                 return ret;
2364
2365         /* if eDP has no EDID, fall back to fixed mode */
2366         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2367                 struct drm_display_mode *mode;
2368                 mode = drm_mode_duplicate(dev,
2369                                           intel_connector->panel.fixed_mode);
2370                 if (mode) {
2371                         drm_mode_probed_add(connector, mode);
2372                         return 1;
2373                 }
2374         }
2375         return 0;
2376 }
2377
2378 static bool
2379 intel_dp_detect_audio(struct drm_connector *connector)
2380 {
2381         struct intel_dp *intel_dp = intel_attached_dp(connector);
2382         struct edid *edid;
2383         bool has_audio = false;
2384
2385         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2386         if (edid) {
2387                 has_audio = drm_detect_monitor_audio(edid);
2388                 kfree(edid);
2389         }
2390
2391         return has_audio;
2392 }
2393
2394 static int
2395 intel_dp_set_property(struct drm_connector *connector,
2396                       struct drm_property *property,
2397                       uint64_t val)
2398 {
2399         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2400         struct intel_connector *intel_connector = to_intel_connector(connector);
2401         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2402         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2403         int ret;
2404
2405         ret = drm_object_property_set_value(&connector->base, property, val);
2406         if (ret)
2407                 return ret;
2408
2409         if (property == dev_priv->force_audio_property) {
2410                 int i = val;
2411                 bool has_audio;
2412
2413                 if (i == intel_dp->force_audio)
2414                         return 0;
2415
2416                 intel_dp->force_audio = i;
2417
2418                 if (i == HDMI_AUDIO_AUTO)
2419                         has_audio = intel_dp_detect_audio(connector);
2420                 else
2421                         has_audio = (i == HDMI_AUDIO_ON);
2422
2423                 if (has_audio == intel_dp->has_audio)
2424                         return 0;
2425
2426                 intel_dp->has_audio = has_audio;
2427                 goto done;
2428         }
2429
2430         if (property == dev_priv->broadcast_rgb_property) {
2431                 bool old_auto = intel_dp->color_range_auto;
2432                 uint32_t old_range = intel_dp->color_range;
2433
2434                 switch (val) {
2435                 case INTEL_BROADCAST_RGB_AUTO:
2436                         intel_dp->color_range_auto = true;
2437                         break;
2438                 case INTEL_BROADCAST_RGB_FULL:
2439                         intel_dp->color_range_auto = false;
2440                         intel_dp->color_range = 0;
2441                         break;
2442                 case INTEL_BROADCAST_RGB_LIMITED:
2443                         intel_dp->color_range_auto = false;
2444                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2445                         break;
2446                 default:
2447                         return -EINVAL;
2448                 }
2449
2450                 if (old_auto == intel_dp->color_range_auto &&
2451                     old_range == intel_dp->color_range)
2452                         return 0;
2453
2454                 goto done;
2455         }
2456
2457         if (is_edp(intel_dp) &&
2458             property == connector->dev->mode_config.scaling_mode_property) {
2459                 if (val == DRM_MODE_SCALE_NONE) {
2460                         DRM_DEBUG_KMS("no scaling not supported\n");
2461                         return -EINVAL;
2462                 }
2463
2464                 if (intel_connector->panel.fitting_mode == val) {
2465                         /* the eDP scaling property is not changed */
2466                         return 0;
2467                 }
2468                 intel_connector->panel.fitting_mode = val;
2469
2470                 goto done;
2471         }
2472
2473         return -EINVAL;
2474
2475 done:
2476         if (intel_encoder->base.crtc)
2477                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2478
2479         return 0;
2480 }
2481
2482 static void
2483 intel_dp_destroy(struct drm_connector *connector)
2484 {
2485         struct intel_dp *intel_dp = intel_attached_dp(connector);
2486         struct intel_connector *intel_connector = to_intel_connector(connector);
2487
2488         if (!IS_ERR_OR_NULL(intel_connector->edid))
2489                 kfree(intel_connector->edid);
2490
2491         if (is_edp(intel_dp))
2492                 intel_panel_fini(&intel_connector->panel);
2493
2494         drm_sysfs_connector_remove(connector);
2495         drm_connector_cleanup(connector);
2496         kfree(connector);
2497 }
2498
2499 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2500 {
2501         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2502         struct intel_dp *intel_dp = &intel_dig_port->dp;
2503         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2504
2505         i2c_del_adapter(&intel_dp->adapter);
2506         drm_encoder_cleanup(encoder);
2507         if (is_edp(intel_dp)) {
2508                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2509                 mutex_lock(&dev->mode_config.mutex);
2510                 ironlake_panel_vdd_off_sync(intel_dp);
2511                 mutex_unlock(&dev->mode_config.mutex);
2512         }
2513         kfree(intel_dig_port);
2514 }
2515
2516 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2517         .mode_set = intel_dp_mode_set,
2518 };
2519
2520 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2521         .dpms = intel_connector_dpms,
2522         .detect = intel_dp_detect,
2523         .fill_modes = drm_helper_probe_single_connector_modes,
2524         .set_property = intel_dp_set_property,
2525         .destroy = intel_dp_destroy,
2526 };
2527
2528 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2529         .get_modes = intel_dp_get_modes,
2530         .mode_valid = intel_dp_mode_valid,
2531         .best_encoder = intel_best_encoder,
2532 };
2533
2534 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2535         .destroy = intel_dp_encoder_destroy,
2536 };
2537
2538 static void
2539 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2540 {
2541         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2542
2543         intel_dp_check_link_status(intel_dp);
2544 }
2545
2546 /* Return which DP Port should be selected for Transcoder DP control */
2547 int
2548 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2549 {
2550         struct drm_device *dev = crtc->dev;
2551         struct intel_encoder *intel_encoder;
2552         struct intel_dp *intel_dp;
2553
2554         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2555                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2556
2557                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2558                     intel_encoder->type == INTEL_OUTPUT_EDP)
2559                         return intel_dp->output_reg;
2560         }
2561
2562         return -1;
2563 }
2564
2565 /* check the VBT to see whether the eDP is on DP-D port */
2566 bool intel_dpd_is_edp(struct drm_device *dev)
2567 {
2568         struct drm_i915_private *dev_priv = dev->dev_private;
2569         struct child_device_config *p_child;
2570         int i;
2571
2572         if (!dev_priv->child_dev_num)
2573                 return false;
2574
2575         for (i = 0; i < dev_priv->child_dev_num; i++) {
2576                 p_child = dev_priv->child_dev + i;
2577
2578                 if (p_child->dvo_port == PORT_IDPD &&
2579                     p_child->device_type == DEVICE_TYPE_eDP)
2580                         return true;
2581         }
2582         return false;
2583 }
2584
2585 static void
2586 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2587 {
2588         struct intel_connector *intel_connector = to_intel_connector(connector);
2589
2590         intel_attach_force_audio_property(connector);
2591         intel_attach_broadcast_rgb_property(connector);
2592         intel_dp->color_range_auto = true;
2593
2594         if (is_edp(intel_dp)) {
2595                 drm_mode_create_scaling_mode_property(connector->dev);
2596                 drm_object_attach_property(
2597                         &connector->base,
2598                         connector->dev->mode_config.scaling_mode_property,
2599                         DRM_MODE_SCALE_ASPECT);
2600                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2601         }
2602 }
2603
2604 static void
2605 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2606                                     struct intel_dp *intel_dp,
2607                                     struct edp_power_seq *out)
2608 {
2609         struct drm_i915_private *dev_priv = dev->dev_private;
2610         struct edp_power_seq cur, vbt, spec, final;
2611         u32 pp_on, pp_off, pp_div, pp;
2612         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2613
2614         if (HAS_PCH_SPLIT(dev)) {
2615                 pp_control_reg = PCH_PP_CONTROL;
2616                 pp_on_reg = PCH_PP_ON_DELAYS;
2617                 pp_off_reg = PCH_PP_OFF_DELAYS;
2618                 pp_div_reg = PCH_PP_DIVISOR;
2619         } else {
2620                 pp_control_reg = PIPEA_PP_CONTROL;
2621                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2622                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2623                 pp_div_reg = PIPEA_PP_DIVISOR;
2624         }
2625
2626         /* Workaround: Need to write PP_CONTROL with the unlock key as
2627          * the very first thing. */
2628         pp = ironlake_get_pp_control(intel_dp);
2629         I915_WRITE(pp_control_reg, pp);
2630
2631         pp_on = I915_READ(pp_on_reg);
2632         pp_off = I915_READ(pp_off_reg);
2633         pp_div = I915_READ(pp_div_reg);
2634
2635         /* Pull timing values out of registers */
2636         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2637                 PANEL_POWER_UP_DELAY_SHIFT;
2638
2639         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2640                 PANEL_LIGHT_ON_DELAY_SHIFT;
2641
2642         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2643                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2644
2645         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2646                 PANEL_POWER_DOWN_DELAY_SHIFT;
2647
2648         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2649                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2650
2651         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2652                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2653
2654         vbt = dev_priv->edp.pps;
2655
2656         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2657          * our hw here, which are all in 100usec. */
2658         spec.t1_t3 = 210 * 10;
2659         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2660         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2661         spec.t10 = 500 * 10;
2662         /* This one is special and actually in units of 100ms, but zero
2663          * based in the hw (so we need to add 100 ms). But the sw vbt
2664          * table multiplies it with 1000 to make it in units of 100usec,
2665          * too. */
2666         spec.t11_t12 = (510 + 100) * 10;
2667
2668         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2669                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2670
2671         /* Use the max of the register settings and vbt. If both are
2672          * unset, fall back to the spec limits. */
2673 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2674                                        spec.field : \
2675                                        max(cur.field, vbt.field))
2676         assign_final(t1_t3);
2677         assign_final(t8);
2678         assign_final(t9);
2679         assign_final(t10);
2680         assign_final(t11_t12);
2681 #undef assign_final
2682
2683 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2684         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2685         intel_dp->backlight_on_delay = get_delay(t8);
2686         intel_dp->backlight_off_delay = get_delay(t9);
2687         intel_dp->panel_power_down_delay = get_delay(t10);
2688         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2689 #undef get_delay
2690
2691         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2692                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2693                       intel_dp->panel_power_cycle_delay);
2694
2695         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2696                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2697
2698         if (out)
2699                 *out = final;
2700 }
2701
2702 static void
2703 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2704                                               struct intel_dp *intel_dp,
2705                                               struct edp_power_seq *seq)
2706 {
2707         struct drm_i915_private *dev_priv = dev->dev_private;
2708         u32 pp_on, pp_off, pp_div, port_sel = 0;
2709         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2710         int pp_on_reg, pp_off_reg, pp_div_reg;
2711
2712         if (HAS_PCH_SPLIT(dev)) {
2713                 pp_on_reg = PCH_PP_ON_DELAYS;
2714                 pp_off_reg = PCH_PP_OFF_DELAYS;
2715                 pp_div_reg = PCH_PP_DIVISOR;
2716         } else {
2717                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2718                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2719                 pp_div_reg = PIPEA_PP_DIVISOR;
2720         }
2721
2722         if (IS_VALLEYVIEW(dev))
2723                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2724
2725         /* And finally store the new values in the power sequencer. */
2726         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2727                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2728         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2729                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2730         /* Compute the divisor for the pp clock, simply match the Bspec
2731          * formula. */
2732         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2733         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2734                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2735
2736         /* Haswell doesn't have any port selection bits for the panel
2737          * power sequencer any more. */
2738         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2739                 if (is_cpu_edp(intel_dp))
2740                         port_sel = PANEL_POWER_PORT_DP_A;
2741                 else
2742                         port_sel = PANEL_POWER_PORT_DP_D;
2743         }
2744
2745         pp_on |= port_sel;
2746
2747         I915_WRITE(pp_on_reg, pp_on);
2748         I915_WRITE(pp_off_reg, pp_off);
2749         I915_WRITE(pp_div_reg, pp_div);
2750
2751         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2752                       I915_READ(pp_on_reg),
2753                       I915_READ(pp_off_reg),
2754                       I915_READ(pp_div_reg));
2755 }
2756
2757 void
2758 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2759                         struct intel_connector *intel_connector)
2760 {
2761         struct drm_connector *connector = &intel_connector->base;
2762         struct intel_dp *intel_dp = &intel_dig_port->dp;
2763         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2764         struct drm_device *dev = intel_encoder->base.dev;
2765         struct drm_i915_private *dev_priv = dev->dev_private;
2766         struct drm_display_mode *fixed_mode = NULL;
2767         struct edp_power_seq power_seq = { 0 };
2768         enum port port = intel_dig_port->port;
2769         const char *name = NULL;
2770         int type;
2771
2772         /* Preserve the current hw state. */
2773         intel_dp->DP = I915_READ(intel_dp->output_reg);
2774         intel_dp->attached_connector = intel_connector;
2775
2776         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2777                 if (intel_dpd_is_edp(dev))
2778                         intel_dp->is_pch_edp = true;
2779
2780         /*
2781          * FIXME : We need to initialize built-in panels before external panels.
2782          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2783          */
2784         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2785                 type = DRM_MODE_CONNECTOR_eDP;
2786                 intel_encoder->type = INTEL_OUTPUT_EDP;
2787         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2788                 type = DRM_MODE_CONNECTOR_eDP;
2789                 intel_encoder->type = INTEL_OUTPUT_EDP;
2790         } else {
2791                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2792                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2793                  * rewrite it.
2794                  */
2795                 type = DRM_MODE_CONNECTOR_DisplayPort;
2796         }
2797
2798         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2799         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2800
2801         connector->interlace_allowed = true;
2802         connector->doublescan_allowed = 0;
2803
2804         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2805                           ironlake_panel_vdd_work);
2806
2807         intel_connector_attach_encoder(intel_connector, intel_encoder);
2808         drm_sysfs_connector_add(connector);
2809
2810         if (HAS_DDI(dev))
2811                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2812         else
2813                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2814
2815         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2816         if (HAS_DDI(dev)) {
2817                 switch (intel_dig_port->port) {
2818                 case PORT_A:
2819                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2820                         break;
2821                 case PORT_B:
2822                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2823                         break;
2824                 case PORT_C:
2825                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2826                         break;
2827                 case PORT_D:
2828                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2829                         break;
2830                 default:
2831                         BUG();
2832                 }
2833         }
2834
2835         /* Set up the DDC bus. */
2836         switch (port) {
2837         case PORT_A:
2838                 intel_encoder->hpd_pin = HPD_PORT_A;
2839                 name = "DPDDC-A";
2840                 break;
2841         case PORT_B:
2842                 intel_encoder->hpd_pin = HPD_PORT_B;
2843                 name = "DPDDC-B";
2844                 break;
2845         case PORT_C:
2846                 intel_encoder->hpd_pin = HPD_PORT_C;
2847                 name = "DPDDC-C";
2848                 break;
2849         case PORT_D:
2850                 intel_encoder->hpd_pin = HPD_PORT_D;
2851                 name = "DPDDC-D";
2852                 break;
2853         default:
2854                 BUG();
2855         }
2856
2857         if (is_edp(intel_dp))
2858                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2859
2860         intel_dp_i2c_init(intel_dp, intel_connector, name);
2861
2862         /* Cache DPCD and EDID for edp. */
2863         if (is_edp(intel_dp)) {
2864                 bool ret;
2865                 struct drm_display_mode *scan;
2866                 struct edid *edid;
2867
2868                 ironlake_edp_panel_vdd_on(intel_dp);
2869                 ret = intel_dp_get_dpcd(intel_dp);
2870                 ironlake_edp_panel_vdd_off(intel_dp, false);
2871
2872                 if (ret) {
2873                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2874                                 dev_priv->no_aux_handshake =
2875                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2876                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2877                 } else {
2878                         /* if this fails, presume the device is a ghost */
2879                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2880                         intel_dp_encoder_destroy(&intel_encoder->base);
2881                         intel_dp_destroy(connector);
2882                         return;
2883                 }
2884
2885                 /* We now know it's not a ghost, init power sequence regs. */
2886                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2887                                                               &power_seq);
2888
2889                 ironlake_edp_panel_vdd_on(intel_dp);
2890                 edid = drm_get_edid(connector, &intel_dp->adapter);
2891                 if (edid) {
2892                         if (drm_add_edid_modes(connector, edid)) {
2893                                 drm_mode_connector_update_edid_property(connector, edid);
2894                                 drm_edid_to_eld(connector, edid);
2895                         } else {
2896                                 kfree(edid);
2897                                 edid = ERR_PTR(-EINVAL);
2898                         }
2899                 } else {
2900                         edid = ERR_PTR(-ENOENT);
2901                 }
2902                 intel_connector->edid = edid;
2903
2904                 /* prefer fixed mode from EDID if available */
2905                 list_for_each_entry(scan, &connector->probed_modes, head) {
2906                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2907                                 fixed_mode = drm_mode_duplicate(dev, scan);
2908                                 break;
2909                         }
2910                 }
2911
2912                 /* fallback to VBT if available for eDP */
2913                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2914                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2915                         if (fixed_mode)
2916                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2917                 }
2918
2919                 ironlake_edp_panel_vdd_off(intel_dp, false);
2920         }
2921
2922         if (is_edp(intel_dp)) {
2923                 intel_panel_init(&intel_connector->panel, fixed_mode);
2924                 intel_panel_setup_backlight(connector);
2925         }
2926
2927         intel_dp_add_properties(intel_dp, connector);
2928
2929         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2930          * 0xd.  Failure to do so will result in spurious interrupts being
2931          * generated on the port when a cable is not attached.
2932          */
2933         if (IS_G4X(dev) && !IS_GM45(dev)) {
2934                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2935                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2936         }
2937 }
2938
2939 void
2940 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2941 {
2942         struct intel_digital_port *intel_dig_port;
2943         struct intel_encoder *intel_encoder;
2944         struct drm_encoder *encoder;
2945         struct intel_connector *intel_connector;
2946
2947         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2948         if (!intel_dig_port)
2949                 return;
2950
2951         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2952         if (!intel_connector) {
2953                 kfree(intel_dig_port);
2954                 return;
2955         }
2956
2957         intel_encoder = &intel_dig_port->base;
2958         encoder = &intel_encoder->base;
2959
2960         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2961                          DRM_MODE_ENCODER_TMDS);
2962         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2963
2964         intel_encoder->compute_config = intel_dp_compute_config;
2965         intel_encoder->enable = intel_enable_dp;
2966         intel_encoder->pre_enable = intel_pre_enable_dp;
2967         intel_encoder->disable = intel_disable_dp;
2968         intel_encoder->post_disable = intel_post_disable_dp;
2969         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2970
2971         intel_dig_port->port = port;
2972         intel_dig_port->dp.output_reg = output_reg;
2973
2974         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2975         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2976         intel_encoder->cloneable = false;
2977         intel_encoder->hot_plug = intel_dp_hot_plug;
2978
2979         intel_dp_init_connector(intel_dig_port, intel_connector);
2980 }