drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll g4x_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 111 {
 112         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 113
 114         return intel_dig_port->base.base.dev;
 115 }
 116
 117 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 118 {
 119         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 120 }
 121
 122 static void intel_dp_link_down(struct intel_encoder *encoder,
 123                                const struct intel_crtc_state *old_crtc_state);
 124 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 125 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 126 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 127                                            const struct intel_crtc_state *crtc_state);
 128 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 129                                       enum pipe pipe);
 130 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 131
 132 /* update sink rates from dpcd */
 133 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 134 {
 135         static const int dp_rates[] = {
 136                 162000, 270000, 540000, 810000
 137         };
 138         int i, max_rate;
 139
 140         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 141
 142         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 143                 if (dp_rates[i] > max_rate)
 144                         break;
 145                 intel_dp->sink_rates[i] = dp_rates[i];
 146         }
 147
 148         intel_dp->num_sink_rates = i;
 149 }
 150
 151 /* Get length of rates array potentially limited by max_rate. */
 152 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 153 {
 154         int i;
 155
 156         /* Limit results by potentially reduced max rate */
 157         for (i = 0; i < len; i++) {
 158                 if (rates[len - i - 1] <= max_rate)
 159                         return len - i;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /* Get length of common rates array potentially limited by max_rate. */
 166 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 167                                           int max_rate)
 168 {
 169         return intel_dp_rate_limit_len(intel_dp->common_rates,
 170                                        intel_dp->num_common_rates, max_rate);
 171 }
 172
 173 /* Theoretical max between source and sink */
 174 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 175 {
 176         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 177 }
 178
 179 /* Theoretical max between source and sink */
 180 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 181 {
 182         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 183         int source_max = intel_dig_port->max_lanes;
 184         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 185
 186         return min(source_max, sink_max);
 187 }
 188
 189 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 190 {
 191         return intel_dp->max_link_lane_count;
 192 }
 193
 194 int
 195 intel_dp_link_required(int pixel_clock, int bpp)
 196 {
 197         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 198         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 199 }
 200
 201 int
 202 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 203 {
 204         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 205          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 206          * is transmitted every LS_Clk per lane, there is no need to account for
 207          * the channel encoding that is done in the PHY layer here.
 208          */
 209
 210         return max_link_clock * max_lanes;
 211 }
 212
 213 static int
 214 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 215 {
 216         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 217         struct intel_encoder *encoder = &intel_dig_port->base;
 218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 219         int max_dotclk = dev_priv->max_dotclk_freq;
 220         int ds_max_dotclk;
 221
 222         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 223
 224         if (type != DP_DS_PORT_TYPE_VGA)
 225                 return max_dotclk;
 226
 227         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 228                                                     intel_dp->downstream_ports);
 229
 230         if (ds_max_dotclk != 0)
 231                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 232
 233         return max_dotclk;
 234 }
 235
 236 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 237 {
 238         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 239         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 240         enum port port = dig_port->base.port;
 241
 242         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 243
 244         /* Low voltage SKUs are limited to max of 5.4G */
 245         if (voltage == VOLTAGE_INFO_0_85V)
 246                 return 540000;
 247
 248         /* For this SKU 8.1G is supported in all ports */
 249         if (IS_CNL_WITH_PORT_F(dev_priv))
 250                 return 810000;
 251
 252         /* For other SKUs, max rate on ports A and D is 5.4G */
 253         if (port == PORT_A || port == PORT_D)
 254                 return 540000;
 255
 256         return 810000;
 257 }
 258
 259 static int icl_max_source_rate(struct intel_dp *intel_dp)
 260 {
 261         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 262         enum port port = dig_port->base.port;
 263
 264         if (port == PORT_B)
 265                 return 540000;
 266
 267         return 810000;
 268 }
 269
 270 static void
 271 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 272 {
 273         /* The values must be in increasing order */
 274         static const int cnl_rates[] = {
 275                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 276         };
 277         static const int bxt_rates[] = {
 278                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 279         };
 280         static const int skl_rates[] = {
 281                 162000, 216000, 270000, 324000, 432000, 540000
 282         };
 283         static const int hsw_rates[] = {
 284                 162000, 270000, 540000
 285         };
 286         static const int g4x_rates[] = {
 287                 162000, 270000
 288         };
 289         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 290         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 291         const struct ddi_vbt_port_info *info =
 292                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 293         const int *source_rates;
 294         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 295
 296         /* This should only be done once */
 297         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 298
 299         if (INTEL_GEN(dev_priv) >= 10) {
 300                 source_rates = cnl_rates;
 301                 size = ARRAY_SIZE(cnl_rates);
 302                 if (INTEL_GEN(dev_priv) == 10)
 303                         max_rate = cnl_max_source_rate(intel_dp);
 304                 else
 305                         max_rate = icl_max_source_rate(intel_dp);
 306         } else if (IS_GEN9_LP(dev_priv)) {
 307                 source_rates = bxt_rates;
 308                 size = ARRAY_SIZE(bxt_rates);
 309         } else if (IS_GEN9_BC(dev_priv)) {
 310                 source_rates = skl_rates;
 311                 size = ARRAY_SIZE(skl_rates);
 312         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 313                    IS_BROADWELL(dev_priv)) {
 314                 source_rates = hsw_rates;
 315                 size = ARRAY_SIZE(hsw_rates);
 316         } else {
 317                 source_rates = g4x_rates;
 318                 size = ARRAY_SIZE(g4x_rates);
 319         }
 320
 321         if (max_rate && vbt_max_rate)
 322                 max_rate = min(max_rate, vbt_max_rate);
 323         else if (vbt_max_rate)
 324                 max_rate = vbt_max_rate;
 325
 326         if (max_rate)
 327                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 328
 329         intel_dp->source_rates = source_rates;
 330         intel_dp->num_source_rates = size;
 331 }
 332
 333 static int intersect_rates(const int *source_rates, int source_len,
 334                            const int *sink_rates, int sink_len,
 335                            int *common_rates)
 336 {
 337         int i = 0, j = 0, k = 0;
 338
 339         while (i < source_len && j < sink_len) {
 340                 if (source_rates[i] == sink_rates[j]) {
 341                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 342                                 return k;
 343                         common_rates[k] = source_rates[i];
 344                         ++k;
 345                         ++i;
 346                         ++j;
 347                 } else if (source_rates[i] < sink_rates[j]) {
 348                         ++i;
 349                 } else {
 350                         ++j;
 351                 }
 352         }
 353         return k;
 354 }
 355
 356 /* return index of rate in rates array, or -1 if not found */
 357 static int intel_dp_rate_index(const int *rates, int len, int rate)
 358 {
 359         int i;
 360
 361         for (i = 0; i < len; i++)
 362                 if (rate == rates[i])
 363                         return i;
 364
 365         return -1;
 366 }
 367
 368 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 369 {
 370         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 371
 372         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 373                                                      intel_dp->num_source_rates,
 374                                                      intel_dp->sink_rates,
 375                                                      intel_dp->num_sink_rates,
 376                                                      intel_dp->common_rates);
 377
 378         /* Paranoia, there should always be something in common. */
 379         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 380                 intel_dp->common_rates[0] = 162000;
 381                 intel_dp->num_common_rates = 1;
 382         }
 383 }
 384
 385 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 386                                        uint8_t lane_count)
 387 {
 388         /*
 389          * FIXME: we need to synchronize the current link parameters with
 390          * hardware readout. Currently fast link training doesn't work on
 391          * boot-up.
 392          */
 393         if (link_rate == 0 ||
 394             link_rate > intel_dp->max_link_rate)
 395                 return false;
 396
 397         if (lane_count == 0 ||
 398             lane_count > intel_dp_max_lane_count(intel_dp))
 399                 return false;
 400
 401         return true;
 402 }
 403
 404 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 405                                             int link_rate, uint8_t lane_count)
 406 {
 407         int index;
 408
 409         index = intel_dp_rate_index(intel_dp->common_rates,
 410                                     intel_dp->num_common_rates,
 411                                     link_rate);
 412         if (index > 0) {
 413                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 414                 intel_dp->max_link_lane_count = lane_count;
 415         } else if (lane_count > 1) {
 416                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 417                 intel_dp->max_link_lane_count = lane_count >> 1;
 418         } else {
 419                 DRM_ERROR("Link Training Unsuccessful\n");
 420                 return -1;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static enum drm_mode_status
 427 intel_dp_mode_valid(struct drm_connector *connector,
 428                     struct drm_display_mode *mode)
 429 {
 430         struct intel_dp *intel_dp = intel_attached_dp(connector);
 431         struct intel_connector *intel_connector = to_intel_connector(connector);
 432         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 433         int target_clock = mode->clock;
 434         int max_rate, mode_rate, max_lanes, max_link_clock;
 435         int max_dotclk;
 436
 437         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 438                 return MODE_NO_DBLESCAN;
 439
 440         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 441
 442         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 443                 if (mode->hdisplay > fixed_mode->hdisplay)
 444                         return MODE_PANEL;
 445
 446                 if (mode->vdisplay > fixed_mode->vdisplay)
 447                         return MODE_PANEL;
 448
 449                 target_clock = fixed_mode->clock;
 450         }
 451
 452         max_link_clock = intel_dp_max_link_rate(intel_dp);
 453         max_lanes = intel_dp_max_lane_count(intel_dp);
 454
 455         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 456         mode_rate = intel_dp_link_required(target_clock, 18);
 457
 458         if (mode_rate > max_rate || target_clock > max_dotclk)
 459                 return MODE_CLOCK_HIGH;
 460
 461         if (mode->clock < 10000)
 462                 return MODE_CLOCK_LOW;
 463
 464         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 465                 return MODE_H_ILLEGAL;
 466
 467         return MODE_OK;
 468 }
 469
 470 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 471 {
 472         int     i;
 473         uint32_t v = 0;
 474
 475         if (src_bytes > 4)
 476                 src_bytes = 4;
 477         for (i = 0; i < src_bytes; i++)
 478                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 479         return v;
 480 }
 481
 482 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 483 {
 484         int i;
 485         if (dst_bytes > 4)
 486                 dst_bytes = 4;
 487         for (i = 0; i < dst_bytes; i++)
 488                 dst[i] = src >> ((3-i) * 8);
 489 }
 490
 491 static void
 492 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 493 static void
 494 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 495                                               bool force_disable_vdd);
 496 static void
 497 intel_dp_pps_init(struct intel_dp *intel_dp);
 498
 499 static void pps_lock(struct intel_dp *intel_dp)
 500 {
 501         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 502
 503         /*
 504          * See intel_power_sequencer_reset() why we need
 505          * a power domain reference here.
 506          */
 507         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 508
 509         mutex_lock(&dev_priv->pps_mutex);
 510 }
 511
 512 static void pps_unlock(struct intel_dp *intel_dp)
 513 {
 514         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 515
 516         mutex_unlock(&dev_priv->pps_mutex);
 517
 518         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 519 }
 520
 521 static void
 522 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 525         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 526         enum pipe pipe = intel_dp->pps_pipe;
 527         bool pll_enabled, release_cl_override = false;
 528         enum dpio_phy phy = DPIO_PHY(pipe);
 529         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 530         uint32_t DP;
 531
 532         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 533                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 534                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 535                 return;
 536
 537         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 538                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 539
 540         /* Preserve the BIOS-computed detected bit. This is
 541          * supposed to be read-only.
 542          */
 543         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 544         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 545         DP |= DP_PORT_WIDTH(1);
 546         DP |= DP_LINK_TRAIN_PAT_1;
 547
 548         if (IS_CHERRYVIEW(dev_priv))
 549                 DP |= DP_PIPE_SEL_CHV(pipe);
 550         else
 551                 DP |= DP_PIPE_SEL(pipe);
 552
 553         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 554
 555         /*
 556          * The DPLL for the pipe must be enabled for this to work.
 557          * So enable temporarily it if it's not already enabled.
 558          */
 559         if (!pll_enabled) {
 560                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 561                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 562
 563                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 564                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 565                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 566                                   pipe_name(pipe));
 567                         return;
 568                 }
 569         }
 570
 571         /*
 572          * Similar magic as in intel_dp_enable_port().
 573          * We _must_ do this port enable + disable trick
 574          * to make this power sequencer lock onto the port.
 575          * Otherwise even VDD force bit won't work.
 576          */
 577         I915_WRITE(intel_dp->output_reg, DP);
 578         POSTING_READ(intel_dp->output_reg);
 579
 580         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 581         POSTING_READ(intel_dp->output_reg);
 582
 583         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 584         POSTING_READ(intel_dp->output_reg);
 585
 586         if (!pll_enabled) {
 587                 vlv_force_pll_off(dev_priv, pipe);
 588
 589                 if (release_cl_override)
 590                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 591         }
 592 }
 593
 594 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 595 {
 596         struct intel_encoder *encoder;
 597         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 598
 599         /*
 600          * We don't have power sequencer currently.
 601          * Pick one that's not used by other ports.
 602          */
 603         for_each_intel_dp(&dev_priv->drm, encoder) {
 604                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 605
 606                 if (encoder->type == INTEL_OUTPUT_EDP) {
 607                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 608                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 609
 610                         if (intel_dp->pps_pipe != INVALID_PIPE)
 611                                 pipes &= ~(1 << intel_dp->pps_pipe);
 612                 } else {
 613                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 614
 615                         if (intel_dp->active_pipe != INVALID_PIPE)
 616                                 pipes &= ~(1 << intel_dp->active_pipe);
 617                 }
 618         }
 619
 620         if (pipes == 0)
 621                 return INVALID_PIPE;
 622
 623         return ffs(pipes) - 1;
 624 }
 625
 626 static enum pipe
 627 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 628 {
 629         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 630         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 631         enum pipe pipe;
 632
 633         lockdep_assert_held(&dev_priv->pps_mutex);
 634
 635         /* We should never land here with regular DP ports */
 636         WARN_ON(!intel_dp_is_edp(intel_dp));
 637
 638         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 639                 intel_dp->active_pipe != intel_dp->pps_pipe);
 640
 641         if (intel_dp->pps_pipe != INVALID_PIPE)
 642                 return intel_dp->pps_pipe;
 643
 644         pipe = vlv_find_free_pps(dev_priv);
 645
 646         /*
 647          * Didn't find one. This should not happen since there
 648          * are two power sequencers and up to two eDP ports.
 649          */
 650         if (WARN_ON(pipe == INVALID_PIPE))
 651                 pipe = PIPE_A;
 652
 653         vlv_steal_power_sequencer(dev_priv, pipe);
 654         intel_dp->pps_pipe = pipe;
 655
 656         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 657                       pipe_name(intel_dp->pps_pipe),
 658                       port_name(intel_dig_port->base.port));
 659
 660         /* init power sequencer on this pipe and port */
 661         intel_dp_init_panel_power_sequencer(intel_dp);
 662         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 663
 664         /*
 665          * Even vdd force doesn't work until we've made
 666          * the power sequencer lock in on the port.
 667          */
 668         vlv_power_sequencer_kick(intel_dp);
 669
 670         return intel_dp->pps_pipe;
 671 }
 672
 673 static int
 674 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 675 {
 676         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 677         int backlight_controller = dev_priv->vbt.backlight.controller;
 678
 679         lockdep_assert_held(&dev_priv->pps_mutex);
 680
 681         /* We should never land here with regular DP ports */
 682         WARN_ON(!intel_dp_is_edp(intel_dp));
 683
 684         if (!intel_dp->pps_reset)
 685                 return backlight_controller;
 686
 687         intel_dp->pps_reset = false;
 688
 689         /*
 690          * Only the HW needs to be reprogrammed, the SW state is fixed and
 691          * has been setup during connector init.
 692          */
 693         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 694
 695         return backlight_controller;
 696 }
 697
 698 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 699                                enum pipe pipe);
 700
 701 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 702                                enum pipe pipe)
 703 {
 704         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 705 }
 706
 707 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 708                                 enum pipe pipe)
 709 {
 710         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 711 }
 712
 713 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 714                          enum pipe pipe)
 715 {
 716         return true;
 717 }
 718
 719 static enum pipe
 720 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 721                      enum port port,
 722                      vlv_pipe_check pipe_check)
 723 {
 724         enum pipe pipe;
 725
 726         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 727                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 728                         PANEL_PORT_SELECT_MASK;
 729
 730                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 731                         continue;
 732
 733                 if (!pipe_check(dev_priv, pipe))
 734                         continue;
 735
 736                 return pipe;
 737         }
 738
 739         return INVALID_PIPE;
 740 }
 741
 742 static void
 743 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 744 {
 745         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 746         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 747         enum port port = intel_dig_port->base.port;
 748
 749         lockdep_assert_held(&dev_priv->pps_mutex);
 750
 751         /* try to find a pipe with this port selected */
 752         /* first pick one where the panel is on */
 753         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 754                                                   vlv_pipe_has_pp_on);
 755         /* didn't find one? pick one where vdd is on */
 756         if (intel_dp->pps_pipe == INVALID_PIPE)
 757                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 758                                                           vlv_pipe_has_vdd_on);
 759         /* didn't find one? pick one with just the correct port */
 760         if (intel_dp->pps_pipe == INVALID_PIPE)
 761                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 762                                                           vlv_pipe_any);
 763
 764         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 765         if (intel_dp->pps_pipe == INVALID_PIPE) {
 766                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 767                               port_name(port));
 768                 return;
 769         }
 770
 771         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 772                       port_name(port), pipe_name(intel_dp->pps_pipe));
 773
 774         intel_dp_init_panel_power_sequencer(intel_dp);
 775         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 776 }
 777
 778 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 779 {
 780         struct intel_encoder *encoder;
 781
 782         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 783                     !IS_GEN9_LP(dev_priv)))
 784                 return;
 785
 786         /*
 787          * We can't grab pps_mutex here due to deadlock with power_domain
 788          * mutex when power_domain functions are called while holding pps_mutex.
 789          * That also means that in order to use pps_pipe the code needs to
 790          * hold both a power domain reference and pps_mutex, and the power domain
 791          * reference get/put must be done while _not_ holding pps_mutex.
 792          * pps_{lock,unlock}() do these steps in the correct order, so one
 793          * should use them always.
 794          */
 795
 796         for_each_intel_dp(&dev_priv->drm, encoder) {
 797                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 798
 799                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 800
 801                 if (encoder->type != INTEL_OUTPUT_EDP)
 802                         continue;
 803
 804                 if (IS_GEN9_LP(dev_priv))
 805                         intel_dp->pps_reset = true;
 806                 else
 807                         intel_dp->pps_pipe = INVALID_PIPE;
 808         }
 809 }
 810
 811 struct pps_registers {
 812         i915_reg_t pp_ctrl;
 813         i915_reg_t pp_stat;
 814         i915_reg_t pp_on;
 815         i915_reg_t pp_off;
 816         i915_reg_t pp_div;
 817 };
 818
 819 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 820                                     struct pps_registers *regs)
 821 {
 822         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 823         int pps_idx = 0;
 824
 825         memset(regs, 0, sizeof(*regs));
 826
 827         if (IS_GEN9_LP(dev_priv))
 828                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 829         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 830                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 831
 832         regs->pp_ctrl = PP_CONTROL(pps_idx);
 833         regs->pp_stat = PP_STATUS(pps_idx);
 834         regs->pp_on = PP_ON_DELAYS(pps_idx);
 835         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 836         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 837             !HAS_PCH_ICP(dev_priv))
 838                 regs->pp_div = PP_DIVISOR(pps_idx);
 839 }
 840
 841 static i915_reg_t
 842 _pp_ctrl_reg(struct intel_dp *intel_dp)
 843 {
 844         struct pps_registers regs;
 845
 846         intel_pps_get_registers(intel_dp, &regs);
 847
 848         return regs.pp_ctrl;
 849 }
 850
 851 static i915_reg_t
 852 _pp_stat_reg(struct intel_dp *intel_dp)
 853 {
 854         struct pps_registers regs;
 855
 856         intel_pps_get_registers(intel_dp, &regs);
 857
 858         return regs.pp_stat;
 859 }
 860
 861 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 862    This function only applicable when panel PM state is not to be tracked */
 863 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 864                               void *unused)
 865 {
 866         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 867                                                  edp_notifier);
 868         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 869
 870         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 871                 return 0;
 872
 873         pps_lock(intel_dp);
 874
 875         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 876                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 877                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 878                 u32 pp_div;
 879
 880                 pp_ctrl_reg = PP_CONTROL(pipe);
 881                 pp_div_reg  = PP_DIVISOR(pipe);
 882                 pp_div = I915_READ(pp_div_reg);
 883                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 884
 885                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 886                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 887                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 888                 msleep(intel_dp->panel_power_cycle_delay);
 889         }
 890
 891         pps_unlock(intel_dp);
 892
 893         return 0;
 894 }
 895
 896 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 897 {
 898         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 899
 900         lockdep_assert_held(&dev_priv->pps_mutex);
 901
 902         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 903             intel_dp->pps_pipe == INVALID_PIPE)
 904                 return false;
 905
 906         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 907 }
 908
 909 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 910 {
 911         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 912
 913         lockdep_assert_held(&dev_priv->pps_mutex);
 914
 915         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 916             intel_dp->pps_pipe == INVALID_PIPE)
 917                 return false;
 918
 919         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 920 }
 921
 922 static void
 923 intel_dp_check_edp(struct intel_dp *intel_dp)
 924 {
 925         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 926
 927         if (!intel_dp_is_edp(intel_dp))
 928                 return;
 929
 930         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 931                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 932                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 933                               I915_READ(_pp_stat_reg(intel_dp)),
 934                               I915_READ(_pp_ctrl_reg(intel_dp)));
 935         }
 936 }
 937
 938 static uint32_t
 939 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
 940 {
 941         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 942         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
 943         uint32_t status;
 944         bool done;
 945
 946 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 947         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 948                                   msecs_to_jiffies_timeout(10));
 949         if (!done)
 950                 DRM_ERROR("dp aux hw did not signal timeout!\n");
 951 #undef C
 952
 953         return status;
 954 }
 955
 956 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 959
 960         if (index)
 961                 return 0;
 962
 963         /*
 964          * The clock divider is based off the hrawclk, and would like to run at
 965          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 966          */
 967         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 968 }
 969
 970 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 971 {
 972         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 973
 974         if (index)
 975                 return 0;
 976
 977         /*
 978          * The clock divider is based off the cdclk or PCH rawclk, and would
 979          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 980          * divide by 2000 and use that
 981          */
 982         if (intel_dp->aux_ch == AUX_CH_A)
 983                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 984         else
 985                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 986 }
 987
 988 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 989 {
 990         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 991
 992         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
 993                 /* Workaround for non-ULT HSW */
 994                 switch (index) {
 995                 case 0: return 63;
 996                 case 1: return 72;
 997                 default: return 0;
 998                 }
 999         }
1000
1001         return ilk_get_aux_clock_divider(intel_dp, index);
1002 }
1003
1004 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1005 {
1006         /*
1007          * SKL doesn't need us to program the AUX clock divider (Hardware will
1008          * derive the clock from CDCLK automatically). We still implement the
1009          * get_aux_clock_divider vfunc to plug-in into the existing code.
1010          */
1011         return index ? 0 : 1;
1012 }
1013
1014 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1015                                      int send_bytes,
1016                                      uint32_t aux_clock_divider)
1017 {
1018         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1019         struct drm_i915_private *dev_priv =
1020                         to_i915(intel_dig_port->base.base.dev);
1021         uint32_t precharge, timeout;
1022
1023         if (IS_GEN6(dev_priv))
1024                 precharge = 3;
1025         else
1026                 precharge = 5;
1027
1028         if (IS_BROADWELL(dev_priv))
1029                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1030         else
1031                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1032
1033         return DP_AUX_CH_CTL_SEND_BUSY |
1034                DP_AUX_CH_CTL_DONE |
1035                DP_AUX_CH_CTL_INTERRUPT |
1036                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1037                timeout |
1038                DP_AUX_CH_CTL_RECEIVE_ERROR |
1039                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1040                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1041                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1042 }
1043
1044 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1045                                       int send_bytes,
1046                                       uint32_t unused)
1047 {
1048         return DP_AUX_CH_CTL_SEND_BUSY |
1049                DP_AUX_CH_CTL_DONE |
1050                DP_AUX_CH_CTL_INTERRUPT |
1051                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1052                DP_AUX_CH_CTL_TIME_OUT_MAX |
1053                DP_AUX_CH_CTL_RECEIVE_ERROR |
1054                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1055                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1056                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1057 }
1058
1059 static int
1060 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1061                   const uint8_t *send, int send_bytes,
1062                   uint8_t *recv, int recv_size,
1063                   u32 aux_send_ctl_flags)
1064 {
1065         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1066         struct drm_i915_private *dev_priv =
1067                         to_i915(intel_dig_port->base.base.dev);
1068         i915_reg_t ch_ctl, ch_data[5];
1069         uint32_t aux_clock_divider;
1070         int i, ret, recv_bytes;
1071         uint32_t status;
1072         int try, clock = 0;
1073         bool vdd;
1074
1075         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1076         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1077                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1078
1079         pps_lock(intel_dp);
1080
1081         /*
1082          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1083          * In such cases we want to leave VDD enabled and it's up to upper layers
1084          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1085          * ourselves.
1086          */
1087         vdd = edp_panel_vdd_on(intel_dp);
1088
1089         /* dp aux is extremely sensitive to irq latency, hence request the
1090          * lowest possible wakeup latency and so prevent the cpu from going into
1091          * deep sleep states.
1092          */
1093         pm_qos_update_request(&dev_priv->pm_qos, 0);
1094
1095         intel_dp_check_edp(intel_dp);
1096
1097         /* Try to wait for any previous AUX channel activity */
1098         for (try = 0; try < 3; try++) {
1099                 status = I915_READ_NOTRACE(ch_ctl);
1100                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1101                         break;
1102                 msleep(1);
1103         }
1104
1105         if (try == 3) {
1106                 static u32 last_status = -1;
1107                 const u32 status = I915_READ(ch_ctl);
1108
1109                 if (status != last_status) {
1110                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1111                              status);
1112                         last_status = status;
1113                 }
1114
1115                 ret = -EBUSY;
1116                 goto out;
1117         }
1118
1119         /* Only 5 data registers! */
1120         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1121                 ret = -E2BIG;
1122                 goto out;
1123         }
1124
1125         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1126                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1127                                                           send_bytes,
1128                                                           aux_clock_divider);
1129
1130                 send_ctl |= aux_send_ctl_flags;
1131
1132                 /* Must try at least 3 times according to DP spec */
1133                 for (try = 0; try < 5; try++) {
1134                         /* Load the send data into the aux channel data registers */
1135                         for (i = 0; i < send_bytes; i += 4)
1136                                 I915_WRITE(ch_data[i >> 2],
1137                                            intel_dp_pack_aux(send + i,
1138                                                              send_bytes - i));
1139
1140                         /* Send the command and wait for it to complete */
1141                         I915_WRITE(ch_ctl, send_ctl);
1142
1143                         status = intel_dp_aux_wait_done(intel_dp);
1144
1145                         /* Clear done status and any errors */
1146                         I915_WRITE(ch_ctl,
1147                                    status |
1148                                    DP_AUX_CH_CTL_DONE |
1149                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1150                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1151
1152                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1153                          *   400us delay required for errors and timeouts
1154                          *   Timeout errors from the HW already meet this
1155                          *   requirement so skip to next iteration
1156                          */
1157                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1158                                 continue;
1159
1160                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1161                                 usleep_range(400, 500);
1162                                 continue;
1163                         }
1164                         if (status & DP_AUX_CH_CTL_DONE)
1165                                 goto done;
1166                 }
1167         }
1168
1169         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1170                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1171                 ret = -EBUSY;
1172                 goto out;
1173         }
1174
1175 done:
1176         /* Check for timeout or receive error.
1177          * Timeouts occur when the sink is not connected
1178          */
1179         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1180                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1181                 ret = -EIO;
1182                 goto out;
1183         }
1184
1185         /* Timeouts occur when the device isn't connected, so they're
1186          * "normal" -- don't fill the kernel log with these */
1187         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1188                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1189                 ret = -ETIMEDOUT;
1190                 goto out;
1191         }
1192
1193         /* Unload any bytes sent back from the other side */
1194         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1195                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1196
1197         /*
1198          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1199          * We have no idea of what happened so we return -EBUSY so
1200          * drm layer takes care for the necessary retries.
1201          */
1202         if (recv_bytes == 0 || recv_bytes > 20) {
1203                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1204                               recv_bytes);
1205                 ret = -EBUSY;
1206                 goto out;
1207         }
1208
1209         if (recv_bytes > recv_size)
1210                 recv_bytes = recv_size;
1211
1212         for (i = 0; i < recv_bytes; i += 4)
1213                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1214                                     recv + i, recv_bytes - i);
1215
1216         ret = recv_bytes;
1217 out:
1218         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1219
1220         if (vdd)
1221                 edp_panel_vdd_off(intel_dp, false);
1222
1223         pps_unlock(intel_dp);
1224
1225         return ret;
1226 }
1227
1228 #define BARE_ADDRESS_SIZE       3
1229 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1230
1231 static void
1232 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1233                     const struct drm_dp_aux_msg *msg)
1234 {
1235         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1236         txbuf[1] = (msg->address >> 8) & 0xff;
1237         txbuf[2] = msg->address & 0xff;
1238         txbuf[3] = msg->size - 1;
1239 }
1240
1241 static ssize_t
1242 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1243 {
1244         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1245         uint8_t txbuf[20], rxbuf[20];
1246         size_t txsize, rxsize;
1247         int ret;
1248
1249         intel_dp_aux_header(txbuf, msg);
1250
1251         switch (msg->request & ~DP_AUX_I2C_MOT) {
1252         case DP_AUX_NATIVE_WRITE:
1253         case DP_AUX_I2C_WRITE:
1254         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1255                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1256                 rxsize = 2; /* 0 or 1 data bytes */
1257
1258                 if (WARN_ON(txsize > 20))
1259                         return -E2BIG;
1260
1261                 WARN_ON(!msg->buffer != !msg->size);
1262
1263                 if (msg->buffer)
1264                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1265
1266                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1267                                         rxbuf, rxsize, 0);
1268                 if (ret > 0) {
1269                         msg->reply = rxbuf[0] >> 4;
1270
1271                         if (ret > 1) {
1272                                 /* Number of bytes written in a short write. */
1273                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1274                         } else {
1275                                 /* Return payload size. */
1276                                 ret = msg->size;
1277                         }
1278                 }
1279                 break;
1280
1281         case DP_AUX_NATIVE_READ:
1282         case DP_AUX_I2C_READ:
1283                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1284                 rxsize = msg->size + 1;
1285
1286                 if (WARN_ON(rxsize > 20))
1287                         return -E2BIG;
1288
1289                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1290                                         rxbuf, rxsize, 0);
1291                 if (ret > 0) {
1292                         msg->reply = rxbuf[0] >> 4;
1293                         /*
1294                          * Assume happy day, and copy the data. The caller is
1295                          * expected to check msg->reply before touching it.
1296                          *
1297                          * Return payload size.
1298                          */
1299                         ret--;
1300                         memcpy(msg->buffer, rxbuf + 1, ret);
1301                 }
1302                 break;
1303
1304         default:
1305                 ret = -EINVAL;
1306                 break;
1307         }
1308
1309         return ret;
1310 }
1311
1312 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1313 {
1314         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1315         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1316         enum port port = encoder->port;
1317         const struct ddi_vbt_port_info *info =
1318                 &dev_priv->vbt.ddi_port_info[port];
1319         enum aux_ch aux_ch;
1320
1321         if (!info->alternate_aux_channel) {
1322                 aux_ch = (enum aux_ch) port;
1323
1324                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1325                               aux_ch_name(aux_ch), port_name(port));
1326                 return aux_ch;
1327         }
1328
1329         switch (info->alternate_aux_channel) {
1330         case DP_AUX_A:
1331                 aux_ch = AUX_CH_A;
1332                 break;
1333         case DP_AUX_B:
1334                 aux_ch = AUX_CH_B;
1335                 break;
1336         case DP_AUX_C:
1337                 aux_ch = AUX_CH_C;
1338                 break;
1339         case DP_AUX_D:
1340                 aux_ch = AUX_CH_D;
1341                 break;
1342         case DP_AUX_E:
1343                 aux_ch = AUX_CH_E;
1344                 break;
1345         case DP_AUX_F:
1346                 aux_ch = AUX_CH_F;
1347                 break;
1348         default:
1349                 MISSING_CASE(info->alternate_aux_channel);
1350                 aux_ch = AUX_CH_A;
1351                 break;
1352         }
1353
1354         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1355                       aux_ch_name(aux_ch), port_name(port));
1356
1357         return aux_ch;
1358 }
1359
1360 static enum intel_display_power_domain
1361 intel_aux_power_domain(struct intel_dp *intel_dp)
1362 {
1363         switch (intel_dp->aux_ch) {
1364         case AUX_CH_A:
1365                 return POWER_DOMAIN_AUX_A;
1366         case AUX_CH_B:
1367                 return POWER_DOMAIN_AUX_B;
1368         case AUX_CH_C:
1369                 return POWER_DOMAIN_AUX_C;
1370         case AUX_CH_D:
1371                 return POWER_DOMAIN_AUX_D;
1372         case AUX_CH_E:
1373                 return POWER_DOMAIN_AUX_E;
1374         case AUX_CH_F:
1375                 return POWER_DOMAIN_AUX_F;
1376         default:
1377                 MISSING_CASE(intel_dp->aux_ch);
1378                 return POWER_DOMAIN_AUX_A;
1379         }
1380 }
1381
1382 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1383 {
1384         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1385         enum aux_ch aux_ch = intel_dp->aux_ch;
1386
1387         switch (aux_ch) {
1388         case AUX_CH_B:
1389         case AUX_CH_C:
1390         case AUX_CH_D:
1391                 return DP_AUX_CH_CTL(aux_ch);
1392         default:
1393                 MISSING_CASE(aux_ch);
1394                 return DP_AUX_CH_CTL(AUX_CH_B);
1395         }
1396 }
1397
1398 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1399 {
1400         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1401         enum aux_ch aux_ch = intel_dp->aux_ch;
1402
1403         switch (aux_ch) {
1404         case AUX_CH_B:
1405         case AUX_CH_C:
1406         case AUX_CH_D:
1407                 return DP_AUX_CH_DATA(aux_ch, index);
1408         default:
1409                 MISSING_CASE(aux_ch);
1410                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1411         }
1412 }
1413
1414 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1415 {
1416         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1417         enum aux_ch aux_ch = intel_dp->aux_ch;
1418
1419         switch (aux_ch) {
1420         case AUX_CH_A:
1421                 return DP_AUX_CH_CTL(aux_ch);
1422         case AUX_CH_B:
1423         case AUX_CH_C:
1424         case AUX_CH_D:
1425                 return PCH_DP_AUX_CH_CTL(aux_ch);
1426         default:
1427                 MISSING_CASE(aux_ch);
1428                 return DP_AUX_CH_CTL(AUX_CH_A);
1429         }
1430 }
1431
1432 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1433 {
1434         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1435         enum aux_ch aux_ch = intel_dp->aux_ch;
1436
1437         switch (aux_ch) {
1438         case AUX_CH_A:
1439                 return DP_AUX_CH_DATA(aux_ch, index);
1440         case AUX_CH_B:
1441         case AUX_CH_C:
1442         case AUX_CH_D:
1443                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1444         default:
1445                 MISSING_CASE(aux_ch);
1446                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1447         }
1448 }
1449
1450 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1451 {
1452         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1453         enum aux_ch aux_ch = intel_dp->aux_ch;
1454
1455         switch (aux_ch) {
1456         case AUX_CH_A:
1457         case AUX_CH_B:
1458         case AUX_CH_C:
1459         case AUX_CH_D:
1460         case AUX_CH_E:
1461         case AUX_CH_F:
1462                 return DP_AUX_CH_CTL(aux_ch);
1463         default:
1464                 MISSING_CASE(aux_ch);
1465                 return DP_AUX_CH_CTL(AUX_CH_A);
1466         }
1467 }
1468
1469 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1470 {
1471         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1472         enum aux_ch aux_ch = intel_dp->aux_ch;
1473
1474         switch (aux_ch) {
1475         case AUX_CH_A:
1476         case AUX_CH_B:
1477         case AUX_CH_C:
1478         case AUX_CH_D:
1479         case AUX_CH_E:
1480         case AUX_CH_F:
1481                 return DP_AUX_CH_DATA(aux_ch, index);
1482         default:
1483                 MISSING_CASE(aux_ch);
1484                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1485         }
1486 }
1487
1488 static void
1489 intel_dp_aux_fini(struct intel_dp *intel_dp)
1490 {
1491         kfree(intel_dp->aux.name);
1492 }
1493
1494 static void
1495 intel_dp_aux_init(struct intel_dp *intel_dp)
1496 {
1497         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1498         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1499
1500         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1501         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1502
1503         if (INTEL_GEN(dev_priv) >= 9) {
1504                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1505                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1506         } else if (HAS_PCH_SPLIT(dev_priv)) {
1507                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1508                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1509         } else {
1510                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1511                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1512         }
1513
1514         if (INTEL_GEN(dev_priv) >= 9)
1515                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1516         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1517                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1518         else if (HAS_PCH_SPLIT(dev_priv))
1519                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1520         else
1521                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1522
1523         if (INTEL_GEN(dev_priv) >= 9)
1524                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1525         else
1526                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1527
1528         drm_dp_aux_init(&intel_dp->aux);
1529
1530         /* Failure to allocate our preferred name is not critical */
1531         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1532                                        port_name(encoder->port));
1533         intel_dp->aux.transfer = intel_dp_aux_transfer;
1534 }
1535
1536 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1537 {
1538         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1539
1540         return max_rate >= 540000;
1541 }
1542
1543 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1544 {
1545         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1546
1547         return max_rate >= 810000;
1548 }
1549
1550 static void
1551 intel_dp_set_clock(struct intel_encoder *encoder,
1552                    struct intel_crtc_state *pipe_config)
1553 {
1554         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1555         const struct dp_link_dpll *divisor = NULL;
1556         int i, count = 0;
1557
1558         if (IS_G4X(dev_priv)) {
1559                 divisor = g4x_dpll;
1560                 count = ARRAY_SIZE(g4x_dpll);
1561         } else if (HAS_PCH_SPLIT(dev_priv)) {
1562                 divisor = pch_dpll;
1563                 count = ARRAY_SIZE(pch_dpll);
1564         } else if (IS_CHERRYVIEW(dev_priv)) {
1565                 divisor = chv_dpll;
1566                 count = ARRAY_SIZE(chv_dpll);
1567         } else if (IS_VALLEYVIEW(dev_priv)) {
1568                 divisor = vlv_dpll;
1569                 count = ARRAY_SIZE(vlv_dpll);
1570         }
1571
1572         if (divisor && count) {
1573                 for (i = 0; i < count; i++) {
1574                         if (pipe_config->port_clock == divisor[i].clock) {
1575                                 pipe_config->dpll = divisor[i].dpll;
1576                                 pipe_config->clock_set = true;
1577                                 break;
1578                         }
1579                 }
1580         }
1581 }
1582
1583 static void snprintf_int_array(char *str, size_t len,
1584                                const int *array, int nelem)
1585 {
1586         int i;
1587
1588         str[0] = '\0';
1589
1590         for (i = 0; i < nelem; i++) {
1591                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1592                 if (r >= len)
1593                         return;
1594                 str += r;
1595                 len -= r;
1596         }
1597 }
1598
1599 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1600 {
1601         char str[128]; /* FIXME: too big for stack? */
1602
1603         if ((drm_debug & DRM_UT_KMS) == 0)
1604                 return;
1605
1606         snprintf_int_array(str, sizeof(str),
1607                            intel_dp->source_rates, intel_dp->num_source_rates);
1608         DRM_DEBUG_KMS("source rates: %s\n", str);
1609
1610         snprintf_int_array(str, sizeof(str),
1611                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1612         DRM_DEBUG_KMS("sink rates: %s\n", str);
1613
1614         snprintf_int_array(str, sizeof(str),
1615                            intel_dp->common_rates, intel_dp->num_common_rates);
1616         DRM_DEBUG_KMS("common rates: %s\n", str);
1617 }
1618
1619 int
1620 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1621 {
1622         int len;
1623
1624         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1625         if (WARN_ON(len <= 0))
1626                 return 162000;
1627
1628         return intel_dp->common_rates[len - 1];
1629 }
1630
1631 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1632 {
1633         int i = intel_dp_rate_index(intel_dp->sink_rates,
1634                                     intel_dp->num_sink_rates, rate);
1635
1636         if (WARN_ON(i < 0))
1637                 i = 0;
1638
1639         return i;
1640 }
1641
1642 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1643                            uint8_t *link_bw, uint8_t *rate_select)
1644 {
1645         /* eDP 1.4 rate select method. */
1646         if (intel_dp->use_rate_select) {
1647                 *link_bw = 0;
1648                 *rate_select =
1649                         intel_dp_rate_select(intel_dp, port_clock);
1650         } else {
1651                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1652                 *rate_select = 0;
1653         }
1654 }
1655
1656 struct link_config_limits {
1657         int min_clock, max_clock;
1658         int min_lane_count, max_lane_count;
1659         int min_bpp, max_bpp;
1660 };
1661
1662 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1663                                 struct intel_crtc_state *pipe_config)
1664 {
1665         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1666         struct intel_connector *intel_connector = intel_dp->attached_connector;
1667         int bpp, bpc;
1668
1669         bpp = pipe_config->pipe_bpp;
1670         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1671
1672         if (bpc > 0)
1673                 bpp = min(bpp, 3*bpc);
1674
1675         if (intel_dp_is_edp(intel_dp)) {
1676                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1677                 if (intel_connector->base.display_info.bpc == 0 &&
1678                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1679                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1680                                       dev_priv->vbt.edp.bpp);
1681                         bpp = dev_priv->vbt.edp.bpp;
1682                 }
1683         }
1684
1685         return bpp;
1686 }
1687
1688 /* Adjust link config limits based on compliance test requests. */
1689 static void
1690 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1691                                   struct intel_crtc_state *pipe_config,
1692                                   struct link_config_limits *limits)
1693 {
1694         /* For DP Compliance we override the computed bpp for the pipe */
1695         if (intel_dp->compliance.test_data.bpc != 0) {
1696                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1697
1698                 limits->min_bpp = limits->max_bpp = bpp;
1699                 pipe_config->dither_force_disable = bpp == 6 * 3;
1700
1701                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1702         }
1703
1704         /* Use values requested by Compliance Test Request */
1705         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1706                 int index;
1707
1708                 /* Validate the compliance test data since max values
1709                  * might have changed due to link train fallback.
1710                  */
1711                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1712                                                intel_dp->compliance.test_lane_count)) {
1713                         index = intel_dp_rate_index(intel_dp->common_rates,
1714                                                     intel_dp->num_common_rates,
1715                                                     intel_dp->compliance.test_link_rate);
1716                         if (index >= 0)
1717                                 limits->min_clock = limits->max_clock = index;
1718                         limits->min_lane_count = limits->max_lane_count =
1719                                 intel_dp->compliance.test_lane_count;
1720                 }
1721         }
1722 }
1723
1724 /* Optimize link config in order: max bpp, min clock, min lanes */
1725 static bool
1726 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1727                                   struct intel_crtc_state *pipe_config,
1728                                   const struct link_config_limits *limits)
1729 {
1730         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1731         int bpp, clock, lane_count;
1732         int mode_rate, link_clock, link_avail;
1733
1734         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1735                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1736                                                    bpp);
1737
1738                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1739                         for (lane_count = limits->min_lane_count;
1740                              lane_count <= limits->max_lane_count;
1741                              lane_count <<= 1) {
1742                                 link_clock = intel_dp->common_rates[clock];
1743                                 link_avail = intel_dp_max_data_rate(link_clock,
1744                                                                     lane_count);
1745
1746                                 if (mode_rate <= link_avail) {
1747                                         pipe_config->lane_count = lane_count;
1748                                         pipe_config->pipe_bpp = bpp;
1749                                         pipe_config->port_clock = link_clock;
1750
1751                                         return true;
1752                                 }
1753                         }
1754                 }
1755         }
1756
1757         return false;
1758 }
1759
1760 static bool
1761 intel_dp_compute_link_config(struct intel_encoder *encoder,
1762                              struct intel_crtc_state *pipe_config)
1763 {
1764         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1765         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1766         struct link_config_limits limits;
1767         int common_len;
1768
1769         common_len = intel_dp_common_len_rate_limit(intel_dp,
1770                                                     intel_dp->max_link_rate);
1771
1772         /* No common link rates between source and sink */
1773         WARN_ON(common_len <= 0);
1774
1775         limits.min_clock = 0;
1776         limits.max_clock = common_len - 1;
1777
1778         limits.min_lane_count = 1;
1779         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1780
1781         limits.min_bpp = 6 * 3;
1782         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1783
1784         if (intel_dp_is_edp(intel_dp)) {
1785                 /*
1786                  * Use the maximum clock and number of lanes the eDP panel
1787                  * advertizes being capable of. The panels are generally
1788                  * designed to support only a single clock and lane
1789                  * configuration, and typically these values correspond to the
1790                  * native resolution of the panel.
1791                  */
1792                 limits.min_lane_count = limits.max_lane_count;
1793                 limits.min_clock = limits.max_clock;
1794         }
1795
1796         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1797
1798         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1799                       "max rate %d max bpp %d pixel clock %iKHz\n",
1800                       limits.max_lane_count,
1801                       intel_dp->common_rates[limits.max_clock],
1802                       limits.max_bpp, adjusted_mode->crtc_clock);
1803
1804         /*
1805          * Optimize for slow and wide. This is the place to add alternative
1806          * optimization policy.
1807          */
1808         if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
1809                 return false;
1810
1811         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1812                       pipe_config->lane_count, pipe_config->port_clock,
1813                       pipe_config->pipe_bpp);
1814
1815         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1816                       intel_dp_link_required(adjusted_mode->crtc_clock,
1817                                              pipe_config->pipe_bpp),
1818                       intel_dp_max_data_rate(pipe_config->port_clock,
1819                                              pipe_config->lane_count));
1820
1821         return true;
1822 }
1823
1824 bool
1825 intel_dp_compute_config(struct intel_encoder *encoder,
1826                         struct intel_crtc_state *pipe_config,
1827                         struct drm_connector_state *conn_state)
1828 {
1829         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1830         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1831         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1832         enum port port = encoder->port;
1833         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1834         struct intel_connector *intel_connector = intel_dp->attached_connector;
1835         struct intel_digital_connector_state *intel_conn_state =
1836                 to_intel_digital_connector_state(conn_state);
1837         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1838                                            DP_DPCD_QUIRK_LIMITED_M_N);
1839
1840         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1841                 pipe_config->has_pch_encoder = true;
1842
1843         pipe_config->has_drrs = false;
1844         if (IS_G4X(dev_priv) || port == PORT_A)
1845                 pipe_config->has_audio = false;
1846         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1847                 pipe_config->has_audio = intel_dp->has_audio;
1848         else
1849                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1850
1851         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1852                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1853                                        adjusted_mode);
1854
1855                 if (INTEL_GEN(dev_priv) >= 9) {
1856                         int ret;
1857
1858                         ret = skl_update_scaler_crtc(pipe_config);
1859                         if (ret)
1860                                 return ret;
1861                 }
1862
1863                 if (HAS_GMCH_DISPLAY(dev_priv))
1864                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1865                                                  conn_state->scaling_mode);
1866                 else
1867                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1868                                                 conn_state->scaling_mode);
1869         }
1870
1871         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1872                 return false;
1873
1874         if (HAS_GMCH_DISPLAY(dev_priv) &&
1875             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1876                 return false;
1877
1878         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1879                 return false;
1880
1881         if (!intel_dp_compute_link_config(encoder, pipe_config))
1882                 return false;
1883
1884         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1885                 /*
1886                  * See:
1887                  * CEA-861-E - 5.1 Default Encoding Parameters
1888                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1889                  */
1890                 pipe_config->limited_color_range =
1891                         pipe_config->pipe_bpp != 18 &&
1892                         drm_default_rgb_quant_range(adjusted_mode) ==
1893                         HDMI_QUANTIZATION_RANGE_LIMITED;
1894         } else {
1895                 pipe_config->limited_color_range =
1896                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1897         }
1898
1899         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
1900                                adjusted_mode->crtc_clock,
1901                                pipe_config->port_clock,
1902                                &pipe_config->dp_m_n,
1903                                reduce_m_n);
1904
1905         if (intel_connector->panel.downclock_mode != NULL &&
1906                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1907                         pipe_config->has_drrs = true;
1908                         intel_link_compute_m_n(pipe_config->pipe_bpp,
1909                                                pipe_config->lane_count,
1910                                                intel_connector->panel.downclock_mode->clock,
1911                                                pipe_config->port_clock,
1912                                                &pipe_config->dp_m2_n2,
1913                                                reduce_m_n);
1914         }
1915
1916         if (!HAS_DDI(dev_priv))
1917                 intel_dp_set_clock(encoder, pipe_config);
1918
1919         intel_psr_compute_config(intel_dp, pipe_config);
1920
1921         return true;
1922 }
1923
1924 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1925                               int link_rate, uint8_t lane_count,
1926                               bool link_mst)
1927 {
1928         intel_dp->link_trained = false;
1929         intel_dp->link_rate = link_rate;
1930         intel_dp->lane_count = lane_count;
1931         intel_dp->link_mst = link_mst;
1932 }
1933
1934 static void intel_dp_prepare(struct intel_encoder *encoder,
1935                              const struct intel_crtc_state *pipe_config)
1936 {
1937         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1938         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1939         enum port port = encoder->port;
1940         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1941         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1942
1943         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1944                                  pipe_config->lane_count,
1945                                  intel_crtc_has_type(pipe_config,
1946                                                      INTEL_OUTPUT_DP_MST));
1947
1948         /*
1949          * There are four kinds of DP registers:
1950          *
1951          *      IBX PCH
1952          *      SNB CPU
1953          *      IVB CPU
1954          *      CPT PCH
1955          *
1956          * IBX PCH and CPU are the same for almost everything,
1957          * except that the CPU DP PLL is configured in this
1958          * register
1959          *
1960          * CPT PCH is quite different, having many bits moved
1961          * to the TRANS_DP_CTL register instead. That
1962          * configuration happens (oddly) in ironlake_pch_enable
1963          */
1964
1965         /* Preserve the BIOS-computed detected bit. This is
1966          * supposed to be read-only.
1967          */
1968         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1969
1970         /* Handle DP bits in common between all three register formats */
1971         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1972         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1973
1974         /* Split out the IBX/CPU vs CPT settings */
1975
1976         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
1977                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1978                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1979                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1980                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1981                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1982
1983                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1984                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1985
1986                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
1987         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1988                 u32 trans_dp;
1989
1990                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1991
1992                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1993                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1994                         trans_dp |= TRANS_DP_ENH_FRAMING;
1995                 else
1996                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1997                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1998         } else {
1999                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2000                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2001
2002                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2003                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2004                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2005                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2006                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2007
2008                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2009                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2010
2011                 if (IS_CHERRYVIEW(dev_priv))
2012                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2013                 else
2014                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2015         }
2016 }
2017
2018 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2019 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2020
2021 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2022 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2023
2024 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2025 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2026
2027 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2028
2029 static void wait_panel_status(struct intel_dp *intel_dp,
2030                                        u32 mask,
2031                                        u32 value)
2032 {
2033         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2034         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2035
2036         lockdep_assert_held(&dev_priv->pps_mutex);
2037
2038         intel_pps_verify_state(intel_dp);
2039
2040         pp_stat_reg = _pp_stat_reg(intel_dp);
2041         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2042
2043         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2044                         mask, value,
2045                         I915_READ(pp_stat_reg),
2046                         I915_READ(pp_ctrl_reg));
2047
2048         if (intel_wait_for_register(dev_priv,
2049                                     pp_stat_reg, mask, value,
2050                                     5000))
2051                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2052                                 I915_READ(pp_stat_reg),
2053                                 I915_READ(pp_ctrl_reg));
2054
2055         DRM_DEBUG_KMS("Wait complete\n");
2056 }
2057
2058 static void wait_panel_on(struct intel_dp *intel_dp)
2059 {
2060         DRM_DEBUG_KMS("Wait for panel power on\n");
2061         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2062 }
2063
2064 static void wait_panel_off(struct intel_dp *intel_dp)
2065 {
2066         DRM_DEBUG_KMS("Wait for panel power off time\n");
2067         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2068 }
2069
2070 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2071 {
2072         ktime_t panel_power_on_time;
2073         s64 panel_power_off_duration;
2074
2075         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2076
2077         /* take the difference of currrent time and panel power off time
2078          * and then make panel wait for t11_t12 if needed. */
2079         panel_power_on_time = ktime_get_boottime();
2080         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2081
2082         /* When we disable the VDD override bit last we have to do the manual
2083          * wait. */
2084         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2085                 wait_remaining_ms_from_jiffies(jiffies,
2086                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2087
2088         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2089 }
2090
2091 static void wait_backlight_on(struct intel_dp *intel_dp)
2092 {
2093         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2094                                        intel_dp->backlight_on_delay);
2095 }
2096
2097 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2098 {
2099         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2100                                        intel_dp->backlight_off_delay);
2101 }
2102
2103 /* Read the current pp_control value, unlocking the register if it
2104  * is locked
2105  */
2106
2107 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2108 {
2109         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2110         u32 control;
2111
2112         lockdep_assert_held(&dev_priv->pps_mutex);
2113
2114         control = I915_READ(_pp_ctrl_reg(intel_dp));
2115         if (WARN_ON(!HAS_DDI(dev_priv) &&
2116                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2117                 control &= ~PANEL_UNLOCK_MASK;
2118                 control |= PANEL_UNLOCK_REGS;
2119         }
2120         return control;
2121 }
2122
2123 /*
2124  * Must be paired with edp_panel_vdd_off().
2125  * Must hold pps_mutex around the whole on/off sequence.
2126  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2127  */
2128 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2129 {
2130         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2131         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2132         u32 pp;
2133         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2134         bool need_to_disable = !intel_dp->want_panel_vdd;
2135
2136         lockdep_assert_held(&dev_priv->pps_mutex);
2137
2138         if (!intel_dp_is_edp(intel_dp))
2139                 return false;
2140
2141         cancel_delayed_work(&intel_dp->panel_vdd_work);
2142         intel_dp->want_panel_vdd = true;
2143
2144         if (edp_have_panel_vdd(intel_dp))
2145                 return need_to_disable;
2146
2147         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2148
2149         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2150                       port_name(intel_dig_port->base.port));
2151
2152         if (!edp_have_panel_power(intel_dp))
2153                 wait_panel_power_cycle(intel_dp);
2154
2155         pp = ironlake_get_pp_control(intel_dp);
2156         pp |= EDP_FORCE_VDD;
2157
2158         pp_stat_reg = _pp_stat_reg(intel_dp);
2159         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2160
2161         I915_WRITE(pp_ctrl_reg, pp);
2162         POSTING_READ(pp_ctrl_reg);
2163         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2164                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2165         /*
2166          * If the panel wasn't on, delay before accessing aux channel
2167          */
2168         if (!edp_have_panel_power(intel_dp)) {
2169                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2170                               port_name(intel_dig_port->base.port));
2171                 msleep(intel_dp->panel_power_up_delay);
2172         }
2173
2174         return need_to_disable;
2175 }
2176
2177 /*
2178  * Must be paired with intel_edp_panel_vdd_off() or
2179  * intel_edp_panel_off().
2180  * Nested calls to these functions are not allowed since
2181  * we drop the lock. Caller must use some higher level
2182  * locking to prevent nested calls from other threads.
2183  */
2184 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2185 {
2186         bool vdd;
2187
2188         if (!intel_dp_is_edp(intel_dp))
2189                 return;
2190
2191         pps_lock(intel_dp);
2192         vdd = edp_panel_vdd_on(intel_dp);
2193         pps_unlock(intel_dp);
2194
2195         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2196              port_name(dp_to_dig_port(intel_dp)->base.port));
2197 }
2198
2199 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2200 {
2201         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2202         struct intel_digital_port *intel_dig_port =
2203                 dp_to_dig_port(intel_dp);
2204         u32 pp;
2205         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2206
2207         lockdep_assert_held(&dev_priv->pps_mutex);
2208
2209         WARN_ON(intel_dp->want_panel_vdd);
2210
2211         if (!edp_have_panel_vdd(intel_dp))
2212                 return;
2213
2214         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2215                       port_name(intel_dig_port->base.port));
2216
2217         pp = ironlake_get_pp_control(intel_dp);
2218         pp &= ~EDP_FORCE_VDD;
2219
2220         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2221         pp_stat_reg = _pp_stat_reg(intel_dp);
2222
2223         I915_WRITE(pp_ctrl_reg, pp);
2224         POSTING_READ(pp_ctrl_reg);
2225
2226         /* Make sure sequencer is idle before allowing subsequent activity */
2227         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2228         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2229
2230         if ((pp & PANEL_POWER_ON) == 0)
2231                 intel_dp->panel_power_off_time = ktime_get_boottime();
2232
2233         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2234 }
2235
2236 static void edp_panel_vdd_work(struct work_struct *__work)
2237 {
2238         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2239                                                  struct intel_dp, panel_vdd_work);
2240
2241         pps_lock(intel_dp);
2242         if (!intel_dp->want_panel_vdd)
2243                 edp_panel_vdd_off_sync(intel_dp);
2244         pps_unlock(intel_dp);
2245 }
2246
2247 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2248 {
2249         unsigned long delay;
2250
2251         /*
2252          * Queue the timer to fire a long time from now (relative to the power
2253          * down delay) to keep the panel power up across a sequence of
2254          * operations.
2255          */
2256         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2257         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2258 }
2259
2260 /*
2261  * Must be paired with edp_panel_vdd_on().
2262  * Must hold pps_mutex around the whole on/off sequence.
2263  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2264  */
2265 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2266 {
2267         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2268
2269         lockdep_assert_held(&dev_priv->pps_mutex);
2270
2271         if (!intel_dp_is_edp(intel_dp))
2272                 return;
2273
2274         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2275              port_name(dp_to_dig_port(intel_dp)->base.port));
2276
2277         intel_dp->want_panel_vdd = false;
2278
2279         if (sync)
2280                 edp_panel_vdd_off_sync(intel_dp);
2281         else
2282                 edp_panel_vdd_schedule_off(intel_dp);
2283 }
2284
2285 static void edp_panel_on(struct intel_dp *intel_dp)
2286 {
2287         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2288         u32 pp;
2289         i915_reg_t pp_ctrl_reg;
2290
2291         lockdep_assert_held(&dev_priv->pps_mutex);
2292
2293         if (!intel_dp_is_edp(intel_dp))
2294                 return;
2295
2296         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2297                       port_name(dp_to_dig_port(intel_dp)->base.port));
2298
2299         if (WARN(edp_have_panel_power(intel_dp),
2300                  "eDP port %c panel power already on\n",
2301                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2302                 return;
2303
2304         wait_panel_power_cycle(intel_dp);
2305
2306         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2307         pp = ironlake_get_pp_control(intel_dp);
2308         if (IS_GEN5(dev_priv)) {
2309                 /* ILK workaround: disable reset around power sequence */
2310                 pp &= ~PANEL_POWER_RESET;
2311                 I915_WRITE(pp_ctrl_reg, pp);
2312                 POSTING_READ(pp_ctrl_reg);
2313         }
2314
2315         pp |= PANEL_POWER_ON;
2316         if (!IS_GEN5(dev_priv))
2317                 pp |= PANEL_POWER_RESET;
2318
2319         I915_WRITE(pp_ctrl_reg, pp);
2320         POSTING_READ(pp_ctrl_reg);
2321
2322         wait_panel_on(intel_dp);
2323         intel_dp->last_power_on = jiffies;
2324
2325         if (IS_GEN5(dev_priv)) {
2326                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2327                 I915_WRITE(pp_ctrl_reg, pp);
2328                 POSTING_READ(pp_ctrl_reg);
2329         }
2330 }
2331
2332 void intel_edp_panel_on(struct intel_dp *intel_dp)
2333 {
2334         if (!intel_dp_is_edp(intel_dp))
2335                 return;
2336
2337         pps_lock(intel_dp);
2338         edp_panel_on(intel_dp);
2339         pps_unlock(intel_dp);
2340 }
2341
2342
2343 static void edp_panel_off(struct intel_dp *intel_dp)
2344 {
2345         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2346         u32 pp;
2347         i915_reg_t pp_ctrl_reg;
2348
2349         lockdep_assert_held(&dev_priv->pps_mutex);
2350
2351         if (!intel_dp_is_edp(intel_dp))
2352                 return;
2353
2354         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2355                       port_name(dp_to_dig_port(intel_dp)->base.port));
2356
2357         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2358              port_name(dp_to_dig_port(intel_dp)->base.port));
2359
2360         pp = ironlake_get_pp_control(intel_dp);
2361         /* We need to switch off panel power _and_ force vdd, for otherwise some
2362          * panels get very unhappy and cease to work. */
2363         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2364                 EDP_BLC_ENABLE);
2365
2366         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2367
2368         intel_dp->want_panel_vdd = false;
2369
2370         I915_WRITE(pp_ctrl_reg, pp);
2371         POSTING_READ(pp_ctrl_reg);
2372
2373         wait_panel_off(intel_dp);
2374         intel_dp->panel_power_off_time = ktime_get_boottime();
2375
2376         /* We got a reference when we enabled the VDD. */
2377         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2378 }
2379
2380 void intel_edp_panel_off(struct intel_dp *intel_dp)
2381 {
2382         if (!intel_dp_is_edp(intel_dp))
2383                 return;
2384
2385         pps_lock(intel_dp);
2386         edp_panel_off(intel_dp);
2387         pps_unlock(intel_dp);
2388 }
2389
2390 /* Enable backlight in the panel power control. */
2391 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2392 {
2393         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2394         u32 pp;
2395         i915_reg_t pp_ctrl_reg;
2396
2397         /*
2398          * If we enable the backlight right away following a panel power
2399          * on, we may see slight flicker as the panel syncs with the eDP
2400          * link.  So delay a bit to make sure the image is solid before
2401          * allowing it to appear.
2402          */
2403         wait_backlight_on(intel_dp);
2404
2405         pps_lock(intel_dp);
2406
2407         pp = ironlake_get_pp_control(intel_dp);
2408         pp |= EDP_BLC_ENABLE;
2409
2410         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2411
2412         I915_WRITE(pp_ctrl_reg, pp);
2413         POSTING_READ(pp_ctrl_reg);
2414
2415         pps_unlock(intel_dp);
2416 }
2417
2418 /* Enable backlight PWM and backlight PP control. */
2419 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2420                             const struct drm_connector_state *conn_state)
2421 {
2422         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2423
2424         if (!intel_dp_is_edp(intel_dp))
2425                 return;
2426
2427         DRM_DEBUG_KMS("\n");
2428
2429         intel_panel_enable_backlight(crtc_state, conn_state);
2430         _intel_edp_backlight_on(intel_dp);
2431 }
2432
2433 /* Disable backlight in the panel power control. */
2434 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2435 {
2436         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2437         u32 pp;
2438         i915_reg_t pp_ctrl_reg;
2439
2440         if (!intel_dp_is_edp(intel_dp))
2441                 return;
2442
2443         pps_lock(intel_dp);
2444
2445         pp = ironlake_get_pp_control(intel_dp);
2446         pp &= ~EDP_BLC_ENABLE;
2447
2448         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2449
2450         I915_WRITE(pp_ctrl_reg, pp);
2451         POSTING_READ(pp_ctrl_reg);
2452
2453         pps_unlock(intel_dp);
2454
2455         intel_dp->last_backlight_off = jiffies;
2456         edp_wait_backlight_off(intel_dp);
2457 }
2458
2459 /* Disable backlight PP control and backlight PWM. */
2460 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2461 {
2462         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2463
2464         if (!intel_dp_is_edp(intel_dp))
2465                 return;
2466
2467         DRM_DEBUG_KMS("\n");
2468
2469         _intel_edp_backlight_off(intel_dp);
2470         intel_panel_disable_backlight(old_conn_state);
2471 }
2472
2473 /*
2474  * Hook for controlling the panel power control backlight through the bl_power
2475  * sysfs attribute. Take care to handle multiple calls.
2476  */
2477 static void intel_edp_backlight_power(struct intel_connector *connector,
2478                                       bool enable)
2479 {
2480         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2481         bool is_enabled;
2482
2483         pps_lock(intel_dp);
2484         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2485         pps_unlock(intel_dp);
2486
2487         if (is_enabled == enable)
2488                 return;
2489
2490         DRM_DEBUG_KMS("panel power control backlight %s\n",
2491                       enable ? "enable" : "disable");
2492
2493         if (enable)
2494                 _intel_edp_backlight_on(intel_dp);
2495         else
2496                 _intel_edp_backlight_off(intel_dp);
2497 }
2498
2499 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2500 {
2501         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2502         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2503         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2504
2505         I915_STATE_WARN(cur_state != state,
2506                         "DP port %c state assertion failure (expected %s, current %s)\n",
2507                         port_name(dig_port->base.port),
2508                         onoff(state), onoff(cur_state));
2509 }
2510 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2511
2512 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2513 {
2514         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2515
2516         I915_STATE_WARN(cur_state != state,
2517                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2518                         onoff(state), onoff(cur_state));
2519 }
2520 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2521 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2522
2523 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2524                                 const struct intel_crtc_state *pipe_config)
2525 {
2526         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2527         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2528
2529         assert_pipe_disabled(dev_priv, crtc->pipe);
2530         assert_dp_port_disabled(intel_dp);
2531         assert_edp_pll_disabled(dev_priv);
2532
2533         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2534                       pipe_config->port_clock);
2535
2536         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2537
2538         if (pipe_config->port_clock == 162000)
2539                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2540         else
2541                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2542
2543         I915_WRITE(DP_A, intel_dp->DP);
2544         POSTING_READ(DP_A);
2545         udelay(500);
2546
2547         /*
2548          * [DevILK] Work around required when enabling DP PLL
2549          * while a pipe is enabled going to FDI:
2550          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2551          * 2. Program DP PLL enable
2552          */
2553         if (IS_GEN5(dev_priv))
2554                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2555
2556         intel_dp->DP |= DP_PLL_ENABLE;
2557
2558         I915_WRITE(DP_A, intel_dp->DP);
2559         POSTING_READ(DP_A);
2560         udelay(200);
2561 }
2562
2563 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2564                                  const struct intel_crtc_state *old_crtc_state)
2565 {
2566         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2567         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2568
2569         assert_pipe_disabled(dev_priv, crtc->pipe);
2570         assert_dp_port_disabled(intel_dp);
2571         assert_edp_pll_enabled(dev_priv);
2572
2573         DRM_DEBUG_KMS("disabling eDP PLL\n");
2574
2575         intel_dp->DP &= ~DP_PLL_ENABLE;
2576
2577         I915_WRITE(DP_A, intel_dp->DP);
2578         POSTING_READ(DP_A);
2579         udelay(200);
2580 }
2581
2582 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2583 {
2584         /*
2585          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2586          * be capable of signalling downstream hpd with a long pulse.
2587          * Whether or not that means D3 is safe to use is not clear,
2588          * but let's assume so until proven otherwise.
2589          *
2590          * FIXME should really check all downstream ports...
2591          */
2592         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2593                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2594                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2595 }
2596
2597 /* If the sink supports it, try to set the power state appropriately */
2598 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2599 {
2600         int ret, i;
2601
2602         /* Should have a valid DPCD by this point */
2603         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2604                 return;
2605
2606         if (mode != DRM_MODE_DPMS_ON) {
2607                 if (downstream_hpd_needs_d0(intel_dp))
2608                         return;
2609
2610                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2611                                          DP_SET_POWER_D3);
2612         } else {
2613                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2614
2615                 /*
2616                  * When turning on, we need to retry for 1ms to give the sink
2617                  * time to wake up.
2618                  */
2619                 for (i = 0; i < 3; i++) {
2620                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2621                                                  DP_SET_POWER_D0);
2622                         if (ret == 1)
2623                                 break;
2624                         msleep(1);
2625                 }
2626
2627                 if (ret == 1 && lspcon->active)
2628                         lspcon_wait_pcon_mode(lspcon);
2629         }
2630
2631         if (ret != 1)
2632                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2633                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2634 }
2635
2636 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2637                                  enum port port, enum pipe *pipe)
2638 {
2639         enum pipe p;
2640
2641         for_each_pipe(dev_priv, p) {
2642                 u32 val = I915_READ(TRANS_DP_CTL(p));
2643
2644                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2645                         *pipe = p;
2646                         return true;
2647                 }
2648         }
2649
2650         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2651
2652         /* must initialize pipe to something for the asserts */
2653         *pipe = PIPE_A;
2654
2655         return false;
2656 }
2657
2658 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2659                            i915_reg_t dp_reg, enum port port,
2660                            enum pipe *pipe)
2661 {
2662         bool ret;
2663         u32 val;
2664
2665         val = I915_READ(dp_reg);
2666
2667         ret = val & DP_PORT_EN;
2668
2669         /* asserts want to know the pipe even if the port is disabled */
2670         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2671                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2672         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2673                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2674         else if (IS_CHERRYVIEW(dev_priv))
2675                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2676         else
2677                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2678
2679         return ret;
2680 }
2681
2682 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2683                                   enum pipe *pipe)
2684 {
2685         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2686         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2687         bool ret;
2688
2689         if (!intel_display_power_get_if_enabled(dev_priv,
2690                                                 encoder->power_domain))
2691                 return false;
2692
2693         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2694                                     encoder->port, pipe);
2695
2696         intel_display_power_put(dev_priv, encoder->power_domain);
2697
2698         return ret;
2699 }
2700
2701 static void intel_dp_get_config(struct intel_encoder *encoder,
2702                                 struct intel_crtc_state *pipe_config)
2703 {
2704         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2705         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2706         u32 tmp, flags = 0;
2707         enum port port = encoder->port;
2708         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2709
2710         if (encoder->type == INTEL_OUTPUT_EDP)
2711                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2712         else
2713                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2714
2715         tmp = I915_READ(intel_dp->output_reg);
2716
2717         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2718
2719         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2720                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2721
2722                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2723                         flags |= DRM_MODE_FLAG_PHSYNC;
2724                 else
2725                         flags |= DRM_MODE_FLAG_NHSYNC;
2726
2727                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2728                         flags |= DRM_MODE_FLAG_PVSYNC;
2729                 else
2730                         flags |= DRM_MODE_FLAG_NVSYNC;
2731         } else {
2732                 if (tmp & DP_SYNC_HS_HIGH)
2733                         flags |= DRM_MODE_FLAG_PHSYNC;
2734                 else
2735                         flags |= DRM_MODE_FLAG_NHSYNC;
2736
2737                 if (tmp & DP_SYNC_VS_HIGH)
2738                         flags |= DRM_MODE_FLAG_PVSYNC;
2739                 else
2740                         flags |= DRM_MODE_FLAG_NVSYNC;
2741         }
2742
2743         pipe_config->base.adjusted_mode.flags |= flags;
2744
2745         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2746                 pipe_config->limited_color_range = true;
2747
2748         pipe_config->lane_count =
2749                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2750
2751         intel_dp_get_m_n(crtc, pipe_config);
2752
2753         if (port == PORT_A) {
2754                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2755                         pipe_config->port_clock = 162000;
2756                 else
2757                         pipe_config->port_clock = 270000;
2758         }
2759
2760         pipe_config->base.adjusted_mode.crtc_clock =
2761                 intel_dotclock_calculate(pipe_config->port_clock,
2762                                          &pipe_config->dp_m_n);
2763
2764         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2765             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2766                 /*
2767                  * This is a big fat ugly hack.
2768                  *
2769                  * Some machines in UEFI boot mode provide us a VBT that has 18
2770                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2771                  * unknown we fail to light up. Yet the same BIOS boots up with
2772                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2773                  * max, not what it tells us to use.
2774                  *
2775                  * Note: This will still be broken if the eDP panel is not lit
2776                  * up by the BIOS, and thus we can't get the mode at module
2777                  * load.
2778                  */
2779                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2780                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2781                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2782         }
2783 }
2784
2785 static void intel_disable_dp(struct intel_encoder *encoder,
2786                              const struct intel_crtc_state *old_crtc_state,
2787                              const struct drm_connector_state *old_conn_state)
2788 {
2789         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2790
2791         intel_dp->link_trained = false;
2792
2793         if (old_crtc_state->has_audio)
2794                 intel_audio_codec_disable(encoder,
2795                                           old_crtc_state, old_conn_state);
2796
2797         /* Make sure the panel is off before trying to change the mode. But also
2798          * ensure that we have vdd while we switch off the panel. */
2799         intel_edp_panel_vdd_on(intel_dp);
2800         intel_edp_backlight_off(old_conn_state);
2801         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2802         intel_edp_panel_off(intel_dp);
2803 }
2804
2805 static void g4x_disable_dp(struct intel_encoder *encoder,
2806                            const struct intel_crtc_state *old_crtc_state,
2807                            const struct drm_connector_state *old_conn_state)
2808 {
2809         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2810 }
2811
2812 static void vlv_disable_dp(struct intel_encoder *encoder,
2813                            const struct intel_crtc_state *old_crtc_state,
2814                            const struct drm_connector_state *old_conn_state)
2815 {
2816         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2817 }
2818
2819 static void g4x_post_disable_dp(struct intel_encoder *encoder,
2820                                 const struct intel_crtc_state *old_crtc_state,
2821                                 const struct drm_connector_state *old_conn_state)
2822 {
2823         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2824         enum port port = encoder->port;
2825
2826         /*
2827          * Bspec does not list a specific disable sequence for g4x DP.
2828          * Follow the ilk+ sequence (disable pipe before the port) for
2829          * g4x DP as it does not suffer from underruns like the normal
2830          * g4x modeset sequence (disable pipe after the port).
2831          */
2832         intel_dp_link_down(encoder, old_crtc_state);
2833
2834         /* Only ilk+ has port A */
2835         if (port == PORT_A)
2836                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2837 }
2838
2839 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2840                                 const struct intel_crtc_state *old_crtc_state,
2841                                 const struct drm_connector_state *old_conn_state)
2842 {
2843         intel_dp_link_down(encoder, old_crtc_state);
2844 }
2845
2846 static void chv_post_disable_dp(struct intel_encoder *encoder,
2847                                 const struct intel_crtc_state *old_crtc_state,
2848                                 const struct drm_connector_state *old_conn_state)
2849 {
2850         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2851
2852         intel_dp_link_down(encoder, old_crtc_state);
2853
2854         mutex_lock(&dev_priv->sb_lock);
2855
2856         /* Assert data lane reset */
2857         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2858
2859         mutex_unlock(&dev_priv->sb_lock);
2860 }
2861
2862 static void
2863 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2864                          uint32_t *DP,
2865                          uint8_t dp_train_pat)
2866 {
2867         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2868         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2869         enum port port = intel_dig_port->base.port;
2870         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
2871
2872         if (dp_train_pat & train_pat_mask)
2873                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2874                               dp_train_pat & train_pat_mask);
2875
2876         if (HAS_DDI(dev_priv)) {
2877                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2878
2879                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2880                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2881                 else
2882                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2883
2884                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2885                 switch (dp_train_pat & train_pat_mask) {
2886                 case DP_TRAINING_PATTERN_DISABLE:
2887                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2888
2889                         break;
2890                 case DP_TRAINING_PATTERN_1:
2891                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2892                         break;
2893                 case DP_TRAINING_PATTERN_2:
2894                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2895                         break;
2896                 case DP_TRAINING_PATTERN_3:
2897                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2898                         break;
2899                 case DP_TRAINING_PATTERN_4:
2900                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
2901                         break;
2902                 }
2903                 I915_WRITE(DP_TP_CTL(port), temp);
2904
2905         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
2906                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2907                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2908
2909                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2910                 case DP_TRAINING_PATTERN_DISABLE:
2911                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2912                         break;
2913                 case DP_TRAINING_PATTERN_1:
2914                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2915                         break;
2916                 case DP_TRAINING_PATTERN_2:
2917                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2918                         break;
2919                 case DP_TRAINING_PATTERN_3:
2920                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2921                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2922                         break;
2923                 }
2924
2925         } else {
2926                 *DP &= ~DP_LINK_TRAIN_MASK;
2927
2928                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2929                 case DP_TRAINING_PATTERN_DISABLE:
2930                         *DP |= DP_LINK_TRAIN_OFF;
2931                         break;
2932                 case DP_TRAINING_PATTERN_1:
2933                         *DP |= DP_LINK_TRAIN_PAT_1;
2934                         break;
2935                 case DP_TRAINING_PATTERN_2:
2936                         *DP |= DP_LINK_TRAIN_PAT_2;
2937                         break;
2938                 case DP_TRAINING_PATTERN_3:
2939                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2940                         *DP |= DP_LINK_TRAIN_PAT_2;
2941                         break;
2942                 }
2943         }
2944 }
2945
2946 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2947                                  const struct intel_crtc_state *old_crtc_state)
2948 {
2949         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2950
2951         /* enable with pattern 1 (as per spec) */
2952
2953         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2954
2955         /*
2956          * Magic for VLV/CHV. We _must_ first set up the register
2957          * without actually enabling the port, and then do another
2958          * write to enable the port. Otherwise link training will
2959          * fail when the power sequencer is freshly used for this port.
2960          */
2961         intel_dp->DP |= DP_PORT_EN;
2962         if (old_crtc_state->has_audio)
2963                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2964
2965         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2966         POSTING_READ(intel_dp->output_reg);
2967 }
2968
2969 static void intel_enable_dp(struct intel_encoder *encoder,
2970                             const struct intel_crtc_state *pipe_config,
2971                             const struct drm_connector_state *conn_state)
2972 {
2973         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2974         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2975         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2976         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2977         enum pipe pipe = crtc->pipe;
2978
2979         if (WARN_ON(dp_reg & DP_PORT_EN))
2980                 return;
2981
2982         pps_lock(intel_dp);
2983
2984         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2985                 vlv_init_panel_power_sequencer(encoder, pipe_config);
2986
2987         intel_dp_enable_port(intel_dp, pipe_config);
2988
2989         edp_panel_vdd_on(intel_dp);
2990         edp_panel_on(intel_dp);
2991         edp_panel_vdd_off(intel_dp, true);
2992
2993         pps_unlock(intel_dp);
2994
2995         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2996                 unsigned int lane_mask = 0x0;
2997
2998                 if (IS_CHERRYVIEW(dev_priv))
2999                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3000
3001                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3002                                     lane_mask);
3003         }
3004
3005         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3006         intel_dp_start_link_train(intel_dp);
3007         intel_dp_stop_link_train(intel_dp);
3008
3009         if (pipe_config->has_audio) {
3010                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3011                                  pipe_name(pipe));
3012                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3013         }
3014 }
3015
3016 static void g4x_enable_dp(struct intel_encoder *encoder,
3017                           const struct intel_crtc_state *pipe_config,
3018                           const struct drm_connector_state *conn_state)
3019 {
3020         intel_enable_dp(encoder, pipe_config, conn_state);
3021         intel_edp_backlight_on(pipe_config, conn_state);
3022 }
3023
3024 static void vlv_enable_dp(struct intel_encoder *encoder,
3025                           const struct intel_crtc_state *pipe_config,
3026                           const struct drm_connector_state *conn_state)
3027 {
3028         intel_edp_backlight_on(pipe_config, conn_state);
3029 }
3030
3031 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3032                               const struct intel_crtc_state *pipe_config,
3033                               const struct drm_connector_state *conn_state)
3034 {
3035         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3036         enum port port = encoder->port;
3037
3038         intel_dp_prepare(encoder, pipe_config);
3039
3040         /* Only ilk+ has port A */
3041         if (port == PORT_A)
3042                 ironlake_edp_pll_on(intel_dp, pipe_config);
3043 }
3044
3045 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3046 {
3047         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3048         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3049         enum pipe pipe = intel_dp->pps_pipe;
3050         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3051
3052         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3053
3054         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3055                 return;
3056
3057         edp_panel_vdd_off_sync(intel_dp);
3058
3059         /*
3060          * VLV seems to get confused when multiple power sequencers
3061          * have the same port selected (even if only one has power/vdd
3062          * enabled). The failure manifests as vlv_wait_port_ready() failing
3063          * CHV on the other hand doesn't seem to mind having the same port
3064          * selected in multiple power sequencers, but let's clear the
3065          * port select always when logically disconnecting a power sequencer
3066          * from a port.
3067          */
3068         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3069                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3070         I915_WRITE(pp_on_reg, 0);
3071         POSTING_READ(pp_on_reg);
3072
3073         intel_dp->pps_pipe = INVALID_PIPE;
3074 }
3075
3076 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3077                                       enum pipe pipe)
3078 {
3079         struct intel_encoder *encoder;
3080
3081         lockdep_assert_held(&dev_priv->pps_mutex);
3082
3083         for_each_intel_dp(&dev_priv->drm, encoder) {
3084                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3085                 enum port port = encoder->port;
3086
3087                 WARN(intel_dp->active_pipe == pipe,
3088                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3089                      pipe_name(pipe), port_name(port));
3090
3091                 if (intel_dp->pps_pipe != pipe)
3092                         continue;
3093
3094                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3095                               pipe_name(pipe), port_name(port));
3096
3097                 /* make sure vdd is off before we steal it */
3098                 vlv_detach_power_sequencer(intel_dp);
3099         }
3100 }
3101
3102 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3103                                            const struct intel_crtc_state *crtc_state)
3104 {
3105         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3106         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3107         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3108
3109         lockdep_assert_held(&dev_priv->pps_mutex);
3110
3111         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3112
3113         if (intel_dp->pps_pipe != INVALID_PIPE &&
3114             intel_dp->pps_pipe != crtc->pipe) {
3115                 /*
3116                  * If another power sequencer was being used on this
3117                  * port previously make sure to turn off vdd there while
3118                  * we still have control of it.
3119                  */
3120                 vlv_detach_power_sequencer(intel_dp);
3121         }
3122
3123         /*
3124          * We may be stealing the power
3125          * sequencer from another port.
3126          */
3127         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3128
3129         intel_dp->active_pipe = crtc->pipe;
3130
3131         if (!intel_dp_is_edp(intel_dp))
3132                 return;
3133
3134         /* now it's all ours */
3135         intel_dp->pps_pipe = crtc->pipe;
3136
3137         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3138                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3139
3140         /* init power sequencer on this pipe and port */
3141         intel_dp_init_panel_power_sequencer(intel_dp);
3142         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3143 }
3144
3145 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3146                               const struct intel_crtc_state *pipe_config,
3147                               const struct drm_connector_state *conn_state)
3148 {
3149         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3150
3151         intel_enable_dp(encoder, pipe_config, conn_state);
3152 }
3153
3154 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3155                                   const struct intel_crtc_state *pipe_config,
3156                                   const struct drm_connector_state *conn_state)
3157 {
3158         intel_dp_prepare(encoder, pipe_config);
3159
3160         vlv_phy_pre_pll_enable(encoder, pipe_config);
3161 }
3162
3163 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3164                               const struct intel_crtc_state *pipe_config,
3165                               const struct drm_connector_state *conn_state)
3166 {
3167         chv_phy_pre_encoder_enable(encoder, pipe_config);
3168
3169         intel_enable_dp(encoder, pipe_config, conn_state);
3170
3171         /* Second common lane will stay alive on its own now */
3172         chv_phy_release_cl2_override(encoder);
3173 }
3174
3175 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3176                                   const struct intel_crtc_state *pipe_config,
3177                                   const struct drm_connector_state *conn_state)
3178 {
3179         intel_dp_prepare(encoder, pipe_config);
3180
3181         chv_phy_pre_pll_enable(encoder, pipe_config);
3182 }
3183
3184 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3185                                     const struct intel_crtc_state *old_crtc_state,
3186                                     const struct drm_connector_state *old_conn_state)
3187 {
3188         chv_phy_post_pll_disable(encoder, old_crtc_state);
3189 }
3190
3191 /*
3192  * Fetch AUX CH registers 0x202 - 0x207 which contain
3193  * link status information
3194  */
3195 bool
3196 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3197 {
3198         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3199                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3200 }
3201
3202 /* These are source-specific values. */
3203 uint8_t
3204 intel_dp_voltage_max(struct intel_dp *intel_dp)
3205 {
3206         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3207         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3208         enum port port = encoder->port;
3209
3210         if (HAS_DDI(dev_priv))
3211                 return intel_ddi_dp_voltage_max(encoder);
3212         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3213                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3214         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3215                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3216         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3217                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3218         else
3219                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3220 }
3221
3222 uint8_t
3223 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3224 {
3225         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3226         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3227         enum port port = encoder->port;
3228
3229         if (HAS_DDI(dev_priv)) {
3230                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3231         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3232                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3233                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3234                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3235                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3236                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3237                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3238                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3239                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3240                 default:
3241                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3242                 }
3243         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3244                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3245                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3246                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3247                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3248                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3249                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3250                 default:
3251                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3252                 }
3253         } else {
3254                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3255                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3256                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3257                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3258                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3259                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3260                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3261                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3262                 default:
3263                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3264                 }
3265         }
3266 }
3267
3268 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3269 {
3270         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3271         unsigned long demph_reg_value, preemph_reg_value,
3272                 uniqtranscale_reg_value;
3273         uint8_t train_set = intel_dp->train_set[0];
3274
3275         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3276         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3277                 preemph_reg_value = 0x0004000;
3278                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3279                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3280                         demph_reg_value = 0x2B405555;
3281                         uniqtranscale_reg_value = 0x552AB83A;
3282                         break;
3283                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3284                         demph_reg_value = 0x2B404040;
3285                         uniqtranscale_reg_value = 0x5548B83A;
3286                         break;
3287                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3288                         demph_reg_value = 0x2B245555;
3289                         uniqtranscale_reg_value = 0x5560B83A;
3290                         break;
3291                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3292                         demph_reg_value = 0x2B405555;
3293                         uniqtranscale_reg_value = 0x5598DA3A;
3294                         break;
3295                 default:
3296                         return 0;
3297                 }
3298                 break;
3299         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3300                 preemph_reg_value = 0x0002000;
3301                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3302                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3303                         demph_reg_value = 0x2B404040;
3304                         uniqtranscale_reg_value = 0x5552B83A;
3305                         break;
3306                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3307                         demph_reg_value = 0x2B404848;
3308                         uniqtranscale_reg_value = 0x5580B83A;
3309                         break;
3310                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3311                         demph_reg_value = 0x2B404040;
3312                         uniqtranscale_reg_value = 0x55ADDA3A;
3313                         break;
3314                 default:
3315                         return 0;
3316                 }
3317                 break;
3318         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3319                 preemph_reg_value = 0x0000000;
3320                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3321                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3322                         demph_reg_value = 0x2B305555;
3323                         uniqtranscale_reg_value = 0x5570B83A;
3324                         break;
3325                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3326                         demph_reg_value = 0x2B2B4040;
3327                         uniqtranscale_reg_value = 0x55ADDA3A;
3328                         break;
3329                 default:
3330                         return 0;
3331                 }
3332                 break;
3333         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3334                 preemph_reg_value = 0x0006000;
3335                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3336                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3337                         demph_reg_value = 0x1B405555;
3338                         uniqtranscale_reg_value = 0x55ADDA3A;
3339                         break;
3340                 default:
3341                         return 0;
3342                 }
3343                 break;
3344         default:
3345                 return 0;
3346         }
3347
3348         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3349                                  uniqtranscale_reg_value, 0);
3350
3351         return 0;
3352 }
3353
3354 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3355 {
3356         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3357         u32 deemph_reg_value, margin_reg_value;
3358         bool uniq_trans_scale = false;
3359         uint8_t train_set = intel_dp->train_set[0];
3360
3361         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3362         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3363                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3364                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3365                         deemph_reg_value = 128;
3366                         margin_reg_value = 52;
3367                         break;
3368                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3369                         deemph_reg_value = 128;
3370                         margin_reg_value = 77;
3371                         break;
3372                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3373                         deemph_reg_value = 128;
3374                         margin_reg_value = 102;
3375                         break;
3376                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3377                         deemph_reg_value = 128;
3378                         margin_reg_value = 154;
3379                         uniq_trans_scale = true;
3380                         break;
3381                 default:
3382                         return 0;
3383                 }
3384                 break;
3385         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3386                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3387                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3388                         deemph_reg_value = 85;
3389                         margin_reg_value = 78;
3390                         break;
3391                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3392                         deemph_reg_value = 85;
3393                         margin_reg_value = 116;
3394                         break;
3395                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3396                         deemph_reg_value = 85;
3397                         margin_reg_value = 154;
3398                         break;
3399                 default:
3400                         return 0;
3401                 }
3402                 break;
3403         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3404                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3405                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3406                         deemph_reg_value = 64;
3407                         margin_reg_value = 104;
3408                         break;
3409                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3410                         deemph_reg_value = 64;
3411                         margin_reg_value = 154;
3412                         break;
3413                 default:
3414                         return 0;
3415                 }
3416                 break;
3417         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3418                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3419                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3420                         deemph_reg_value = 43;
3421                         margin_reg_value = 154;
3422                         break;
3423                 default:
3424                         return 0;
3425                 }
3426                 break;
3427         default:
3428                 return 0;
3429         }
3430
3431         chv_set_phy_signal_level(encoder, deemph_reg_value,
3432                                  margin_reg_value, uniq_trans_scale);
3433
3434         return 0;
3435 }
3436
3437 static uint32_t
3438 g4x_signal_levels(uint8_t train_set)
3439 {
3440         uint32_t        signal_levels = 0;
3441
3442         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3443         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3444         default:
3445                 signal_levels |= DP_VOLTAGE_0_4;
3446                 break;
3447         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3448                 signal_levels |= DP_VOLTAGE_0_6;
3449                 break;
3450         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3451                 signal_levels |= DP_VOLTAGE_0_8;
3452                 break;
3453         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3454                 signal_levels |= DP_VOLTAGE_1_2;
3455                 break;
3456         }
3457         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3458         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3459         default:
3460                 signal_levels |= DP_PRE_EMPHASIS_0;
3461                 break;
3462         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3463                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3464                 break;
3465         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3466                 signal_levels |= DP_PRE_EMPHASIS_6;
3467                 break;
3468         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3469                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3470                 break;
3471         }
3472         return signal_levels;
3473 }
3474
3475 /* SNB CPU eDP voltage swing and pre-emphasis control */
3476 static uint32_t
3477 snb_cpu_edp_signal_levels(uint8_t train_set)
3478 {
3479         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3480                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3481         switch (signal_levels) {
3482         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3483         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3484                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3485         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3486                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3487         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3488         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3489                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3490         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3491         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3492                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3493         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3494         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3495                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3496         default:
3497                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3498                               "0x%x\n", signal_levels);
3499                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3500         }
3501 }
3502
3503 /* IVB CPU eDP voltage swing and pre-emphasis control */
3504 static uint32_t
3505 ivb_cpu_edp_signal_levels(uint8_t train_set)
3506 {
3507         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3508                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3509         switch (signal_levels) {
3510         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3511                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3512         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3513                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3514         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3515                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3516
3517         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3518                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3519         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3520                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3521
3522         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3523                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3524         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3525                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3526
3527         default:
3528                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3529                               "0x%x\n", signal_levels);
3530                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3531         }
3532 }
3533
3534 void
3535 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3536 {
3537         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3538         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3539         enum port port = intel_dig_port->base.port;
3540         uint32_t signal_levels, mask = 0;
3541         uint8_t train_set = intel_dp->train_set[0];
3542
3543         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3544                 signal_levels = bxt_signal_levels(intel_dp);
3545         } else if (HAS_DDI(dev_priv)) {
3546                 signal_levels = ddi_signal_levels(intel_dp);
3547                 mask = DDI_BUF_EMP_MASK;
3548         } else if (IS_CHERRYVIEW(dev_priv)) {
3549                 signal_levels = chv_signal_levels(intel_dp);
3550         } else if (IS_VALLEYVIEW(dev_priv)) {
3551                 signal_levels = vlv_signal_levels(intel_dp);
3552         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3553                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3554                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3555         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3556                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3557                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3558         } else {
3559                 signal_levels = g4x_signal_levels(train_set);
3560                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3561         }
3562
3563         if (mask)
3564                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3565
3566         DRM_DEBUG_KMS("Using vswing level %d\n",
3567                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3568         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3569                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3570                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3571
3572         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3573
3574         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3575         POSTING_READ(intel_dp->output_reg);
3576 }
3577
3578 void
3579 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3580                                        uint8_t dp_train_pat)
3581 {
3582         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3583         struct drm_i915_private *dev_priv =
3584                 to_i915(intel_dig_port->base.base.dev);
3585
3586         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3587
3588         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3589         POSTING_READ(intel_dp->output_reg);
3590 }
3591
3592 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3593 {
3594         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3595         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3596         enum port port = intel_dig_port->base.port;
3597         uint32_t val;
3598
3599         if (!HAS_DDI(dev_priv))
3600                 return;
3601
3602         val = I915_READ(DP_TP_CTL(port));
3603         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3604         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3605         I915_WRITE(DP_TP_CTL(port), val);
3606
3607         /*
3608          * On PORT_A we can have only eDP in SST mode. There the only reason
3609          * we need to set idle transmission mode is to work around a HW issue
3610          * where we enable the pipe while not in idle link-training mode.
3611          * In this case there is requirement to wait for a minimum number of
3612          * idle patterns to be sent.
3613          */
3614         if (port == PORT_A)
3615                 return;
3616
3617         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3618                                     DP_TP_STATUS_IDLE_DONE,
3619                                     DP_TP_STATUS_IDLE_DONE,
3620                                     1))
3621                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3622 }
3623
3624 static void
3625 intel_dp_link_down(struct intel_encoder *encoder,
3626                    const struct intel_crtc_state *old_crtc_state)
3627 {
3628         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3629         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3630         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3631         enum port port = encoder->port;
3632         uint32_t DP = intel_dp->DP;
3633
3634         if (WARN_ON(HAS_DDI(dev_priv)))
3635                 return;
3636
3637         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3638                 return;
3639
3640         DRM_DEBUG_KMS("\n");
3641
3642         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3643             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3644                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3645                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3646         } else {
3647                 DP &= ~DP_LINK_TRAIN_MASK;
3648                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3649         }
3650         I915_WRITE(intel_dp->output_reg, DP);
3651         POSTING_READ(intel_dp->output_reg);
3652
3653         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3654         I915_WRITE(intel_dp->output_reg, DP);
3655         POSTING_READ(intel_dp->output_reg);
3656
3657         /*
3658          * HW workaround for IBX, we need to move the port
3659          * to transcoder A after disabling it to allow the
3660          * matching HDMI port to be enabled on transcoder A.
3661          */
3662         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3663                 /*
3664                  * We get CPU/PCH FIFO underruns on the other pipe when
3665                  * doing the workaround. Sweep them under the rug.
3666                  */
3667                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3668                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3669
3670                 /* always enable with pattern 1 (as per spec) */
3671                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3672                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3673                         DP_LINK_TRAIN_PAT_1;
3674                 I915_WRITE(intel_dp->output_reg, DP);
3675                 POSTING_READ(intel_dp->output_reg);
3676
3677                 DP &= ~DP_PORT_EN;
3678                 I915_WRITE(intel_dp->output_reg, DP);
3679                 POSTING_READ(intel_dp->output_reg);
3680
3681                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3682                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3683                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3684         }
3685
3686         msleep(intel_dp->panel_power_down_delay);
3687
3688         intel_dp->DP = DP;
3689
3690         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3691                 pps_lock(intel_dp);
3692                 intel_dp->active_pipe = INVALID_PIPE;
3693                 pps_unlock(intel_dp);
3694         }
3695 }
3696
3697 bool
3698 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3699 {
3700         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3701                              sizeof(intel_dp->dpcd)) < 0)
3702                 return false; /* aux transfer failed */
3703
3704         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3705
3706         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3707 }
3708
3709 static bool
3710 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3711 {
3712         struct drm_i915_private *dev_priv =
3713                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3714
3715         /* this function is meant to be called only once */
3716         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3717
3718         if (!intel_dp_read_dpcd(intel_dp))
3719                 return false;
3720
3721         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3722                          drm_dp_is_branch(intel_dp->dpcd));
3723
3724         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3725                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3726                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3727
3728         /*
3729          * Read the eDP display control registers.
3730          *
3731          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3732          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3733          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3734          * method). The display control registers should read zero if they're
3735          * not supported anyway.
3736          */
3737         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3738                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3739                              sizeof(intel_dp->edp_dpcd))
3740                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3741                               intel_dp->edp_dpcd);
3742
3743         /*
3744          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3745          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3746          */
3747         intel_psr_init_dpcd(intel_dp);
3748
3749         /* Read the eDP 1.4+ supported link rates. */
3750         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3751                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3752                 int i;
3753
3754                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3755                                 sink_rates, sizeof(sink_rates));
3756
3757                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3758                         int val = le16_to_cpu(sink_rates[i]);
3759
3760                         if (val == 0)
3761                                 break;
3762
3763                         /* Value read multiplied by 200kHz gives the per-lane
3764                          * link rate in kHz. The source rates are, however,
3765                          * stored in terms of LS_Clk kHz. The full conversion
3766                          * back to symbols is
3767                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3768                          */
3769                         intel_dp->sink_rates[i] = (val * 200) / 10;
3770                 }
3771                 intel_dp->num_sink_rates = i;
3772         }
3773
3774         /*
3775          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3776          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3777          */
3778         if (intel_dp->num_sink_rates)
3779                 intel_dp->use_rate_select = true;
3780         else
3781                 intel_dp_set_sink_rates(intel_dp);
3782
3783         intel_dp_set_common_rates(intel_dp);
3784
3785         return true;
3786 }
3787
3788
3789 static bool
3790 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3791 {
3792         u8 sink_count;
3793
3794         if (!intel_dp_read_dpcd(intel_dp))
3795                 return false;
3796
3797         /* Don't clobber cached eDP rates. */
3798         if (!intel_dp_is_edp(intel_dp)) {
3799                 intel_dp_set_sink_rates(intel_dp);
3800                 intel_dp_set_common_rates(intel_dp);
3801         }
3802
3803         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3804                 return false;
3805
3806         /*
3807          * Sink count can change between short pulse hpd hence
3808          * a member variable in intel_dp will track any changes
3809          * between short pulse interrupts.
3810          */
3811         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3812
3813         /*
3814          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3815          * a dongle is present but no display. Unless we require to know
3816          * if a dongle is present or not, we don't need to update
3817          * downstream port information. So, an early return here saves
3818          * time from performing other operations which are not required.
3819          */
3820         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3821                 return false;
3822
3823         if (!drm_dp_is_branch(intel_dp->dpcd))
3824                 return true; /* native DP sink */
3825
3826         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3827                 return true; /* no per-port downstream info */
3828
3829         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3830                              intel_dp->downstream_ports,
3831                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3832                 return false; /* downstream port status fetch failed */
3833
3834         return true;
3835 }
3836
3837 static bool
3838 intel_dp_can_mst(struct intel_dp *intel_dp)
3839 {
3840         u8 mstm_cap;
3841
3842         if (!i915_modparams.enable_dp_mst)
3843                 return false;
3844
3845         if (!intel_dp->can_mst)
3846                 return false;
3847
3848         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3849                 return false;
3850
3851         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3852                 return false;
3853
3854         return mstm_cap & DP_MST_CAP;
3855 }
3856
3857 static void
3858 intel_dp_configure_mst(struct intel_dp *intel_dp)
3859 {
3860         if (!i915_modparams.enable_dp_mst)
3861                 return;
3862
3863         if (!intel_dp->can_mst)
3864                 return;
3865
3866         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3867
3868         if (intel_dp->is_mst)
3869                 DRM_DEBUG_KMS("Sink is MST capable\n");
3870         else
3871                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3872
3873         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3874                                         intel_dp->is_mst);
3875 }
3876
3877 static bool
3878 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3879 {
3880         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3881                                  sink_irq_vector) == 1;
3882 }
3883
3884 static bool
3885 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3886 {
3887         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
3888                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
3889                 DP_DPRX_ESI_LEN;
3890 }
3891
3892 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3893 {
3894         int status = 0;
3895         int test_link_rate;
3896         uint8_t test_lane_count, test_link_bw;
3897         /* (DP CTS 1.2)
3898          * 4.3.1.11
3899          */
3900         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3901         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3902                                    &test_lane_count);
3903
3904         if (status <= 0) {
3905                 DRM_DEBUG_KMS("Lane count read failed\n");
3906                 return DP_TEST_NAK;
3907         }
3908         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3909
3910         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3911                                    &test_link_bw);
3912         if (status <= 0) {
3913                 DRM_DEBUG_KMS("Link Rate read failed\n");
3914                 return DP_TEST_NAK;
3915         }
3916         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3917
3918         /* Validate the requested link rate and lane count */
3919         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3920                                         test_lane_count))
3921                 return DP_TEST_NAK;
3922
3923         intel_dp->compliance.test_lane_count = test_lane_count;
3924         intel_dp->compliance.test_link_rate = test_link_rate;
3925
3926         return DP_TEST_ACK;
3927 }
3928
3929 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3930 {
3931         uint8_t test_pattern;
3932         uint8_t test_misc;
3933         __be16 h_width, v_height;
3934         int status = 0;
3935
3936         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3937         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3938                                    &test_pattern);
3939         if (status <= 0) {
3940                 DRM_DEBUG_KMS("Test pattern read failed\n");
3941                 return DP_TEST_NAK;
3942         }
3943         if (test_pattern != DP_COLOR_RAMP)
3944                 return DP_TEST_NAK;
3945
3946         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3947                                   &h_width, 2);
3948         if (status <= 0) {
3949                 DRM_DEBUG_KMS("H Width read failed\n");
3950                 return DP_TEST_NAK;
3951         }
3952
3953         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3954                                   &v_height, 2);
3955         if (status <= 0) {
3956                 DRM_DEBUG_KMS("V Height read failed\n");
3957                 return DP_TEST_NAK;
3958         }
3959
3960         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3961                                    &test_misc);
3962         if (status <= 0) {
3963                 DRM_DEBUG_KMS("TEST MISC read failed\n");
3964                 return DP_TEST_NAK;
3965         }
3966         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3967                 return DP_TEST_NAK;
3968         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3969                 return DP_TEST_NAK;
3970         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3971         case DP_TEST_BIT_DEPTH_6:
3972                 intel_dp->compliance.test_data.bpc = 6;
3973                 break;
3974         case DP_TEST_BIT_DEPTH_8:
3975                 intel_dp->compliance.test_data.bpc = 8;
3976                 break;
3977         default:
3978                 return DP_TEST_NAK;
3979         }
3980
3981         intel_dp->compliance.test_data.video_pattern = test_pattern;
3982         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3983         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3984         /* Set test active flag here so userspace doesn't interrupt things */
3985         intel_dp->compliance.test_active = 1;
3986
3987         return DP_TEST_ACK;
3988 }
3989
3990 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3991 {
3992         uint8_t test_result = DP_TEST_ACK;
3993         struct intel_connector *intel_connector = intel_dp->attached_connector;
3994         struct drm_connector *connector = &intel_connector->base;
3995
3996         if (intel_connector->detect_edid == NULL ||
3997             connector->edid_corrupt ||
3998             intel_dp->aux.i2c_defer_count > 6) {
3999                 /* Check EDID read for NACKs, DEFERs and corruption
4000                  * (DP CTS 1.2 Core r1.1)
4001                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4002                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4003                  *    4.2.2.6 : EDID corruption detected
4004                  * Use failsafe mode for all cases
4005                  */
4006                 if (intel_dp->aux.i2c_nack_count > 0 ||
4007                         intel_dp->aux.i2c_defer_count > 0)
4008                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4009                                       intel_dp->aux.i2c_nack_count,
4010                                       intel_dp->aux.i2c_defer_count);
4011                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4012         } else {
4013                 struct edid *block = intel_connector->detect_edid;
4014
4015                 /* We have to write the checksum
4016                  * of the last block read
4017                  */
4018                 block += intel_connector->detect_edid->extensions;
4019
4020                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4021                                        block->checksum) <= 0)
4022                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4023
4024                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4025                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4026         }
4027
4028         /* Set test active flag here so userspace doesn't interrupt things */
4029         intel_dp->compliance.test_active = 1;
4030
4031         return test_result;
4032 }
4033
4034 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4035 {
4036         uint8_t test_result = DP_TEST_NAK;
4037         return test_result;
4038 }
4039
4040 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4041 {
4042         uint8_t response = DP_TEST_NAK;
4043         uint8_t request = 0;
4044         int status;
4045
4046         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4047         if (status <= 0) {
4048                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4049                 goto update_status;
4050         }
4051
4052         switch (request) {
4053         case DP_TEST_LINK_TRAINING:
4054                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4055                 response = intel_dp_autotest_link_training(intel_dp);
4056                 break;
4057         case DP_TEST_LINK_VIDEO_PATTERN:
4058                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4059                 response = intel_dp_autotest_video_pattern(intel_dp);
4060                 break;
4061         case DP_TEST_LINK_EDID_READ:
4062                 DRM_DEBUG_KMS("EDID test requested\n");
4063                 response = intel_dp_autotest_edid(intel_dp);
4064                 break;
4065         case DP_TEST_LINK_PHY_TEST_PATTERN:
4066                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4067                 response = intel_dp_autotest_phy_pattern(intel_dp);
4068                 break;
4069         default:
4070                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4071                 break;
4072         }
4073
4074         if (response & DP_TEST_ACK)
4075                 intel_dp->compliance.test_type = request;
4076
4077 update_status:
4078         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4079         if (status <= 0)
4080                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4081 }
4082
4083 static int
4084 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4085 {
4086         bool bret;
4087
4088         if (intel_dp->is_mst) {
4089                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4090                 int ret = 0;
4091                 int retry;
4092                 bool handled;
4093                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4094 go_again:
4095                 if (bret == true) {
4096
4097                         /* check link status - esi[10] = 0x200c */
4098                         if (intel_dp->active_mst_links &&
4099                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4100                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4101                                 intel_dp_start_link_train(intel_dp);
4102                                 intel_dp_stop_link_train(intel_dp);
4103                         }
4104
4105                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4106                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4107
4108                         if (handled) {
4109                                 for (retry = 0; retry < 3; retry++) {
4110                                         int wret;
4111                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4112                                                                  DP_SINK_COUNT_ESI+1,
4113                                                                  &esi[1], 3);
4114                                         if (wret == 3) {
4115                                                 break;
4116                                         }
4117                                 }
4118
4119                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4120                                 if (bret == true) {
4121                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4122                                         goto go_again;
4123                                 }
4124                         } else
4125                                 ret = 0;
4126
4127                         return ret;
4128                 } else {
4129                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4130                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4131                         intel_dp->is_mst = false;
4132                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4133                         /* send a hotplug event */
4134                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4135                 }
4136         }
4137         return -EINVAL;
4138 }
4139
4140 static bool
4141 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4142 {
4143         u8 link_status[DP_LINK_STATUS_SIZE];
4144
4145         if (!intel_dp->link_trained)
4146                 return false;
4147
4148         if (!intel_dp_get_link_status(intel_dp, link_status))
4149                 return false;
4150
4151         /*
4152          * Validate the cached values of intel_dp->link_rate and
4153          * intel_dp->lane_count before attempting to retrain.
4154          */
4155         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4156                                         intel_dp->lane_count))
4157                 return false;
4158
4159         /* Retrain if Channel EQ or CR not ok */
4160         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4161 }
4162
4163 /*
4164  * If display is now connected check links status,
4165  * there has been known issues of link loss triggering
4166  * long pulse.
4167  *
4168  * Some sinks (eg. ASUS PB287Q) seem to perform some
4169  * weird HPD ping pong during modesets. So we can apparently
4170  * end up with HPD going low during a modeset, and then
4171  * going back up soon after. And once that happens we must
4172  * retrain the link to get a picture. That's in case no
4173  * userspace component reacted to intermittent HPD dip.
4174  */
4175 int intel_dp_retrain_link(struct intel_encoder *encoder,
4176                           struct drm_modeset_acquire_ctx *ctx)
4177 {
4178         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4179         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4180         struct intel_connector *connector = intel_dp->attached_connector;
4181         struct drm_connector_state *conn_state;
4182         struct intel_crtc_state *crtc_state;
4183         struct intel_crtc *crtc;
4184         int ret;
4185
4186         /* FIXME handle the MST connectors as well */
4187
4188         if (!connector || connector->base.status != connector_status_connected)
4189                 return 0;
4190
4191         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4192                                ctx);
4193         if (ret)
4194                 return ret;
4195
4196         conn_state = connector->base.state;
4197
4198         crtc = to_intel_crtc(conn_state->crtc);
4199         if (!crtc)
4200                 return 0;
4201
4202         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4203         if (ret)
4204                 return ret;
4205
4206         crtc_state = to_intel_crtc_state(crtc->base.state);
4207
4208         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4209
4210         if (!crtc_state->base.active)
4211                 return 0;
4212
4213         if (conn_state->commit &&
4214             !try_wait_for_completion(&conn_state->commit->hw_done))
4215                 return 0;
4216
4217         if (!intel_dp_needs_link_retrain(intel_dp))
4218                 return 0;
4219
4220         /* Suppress underruns caused by re-training */
4221         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4222         if (crtc->config->has_pch_encoder)
4223                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4224                                                       intel_crtc_pch_transcoder(crtc), false);
4225
4226         intel_dp_start_link_train(intel_dp);
4227         intel_dp_stop_link_train(intel_dp);
4228
4229         /* Keep underrun reporting disabled until things are stable */
4230         intel_wait_for_vblank(dev_priv, crtc->pipe);
4231
4232         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4233         if (crtc->config->has_pch_encoder)
4234                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4235                                                       intel_crtc_pch_transcoder(crtc), true);
4236
4237         return 0;
4238 }
4239
4240 /*
4241  * If display is now connected check links status,
4242  * there has been known issues of link loss triggering
4243  * long pulse.
4244  *
4245  * Some sinks (eg. ASUS PB287Q) seem to perform some
4246  * weird HPD ping pong during modesets. So we can apparently
4247  * end up with HPD going low during a modeset, and then
4248  * going back up soon after. And once that happens we must
4249  * retrain the link to get a picture. That's in case no
4250  * userspace component reacted to intermittent HPD dip.
4251  */
4252 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4253                              struct intel_connector *connector)
4254 {
4255         struct drm_modeset_acquire_ctx ctx;
4256         bool changed;
4257         int ret;
4258
4259         changed = intel_encoder_hotplug(encoder, connector);
4260
4261         drm_modeset_acquire_init(&ctx, 0);
4262
4263         for (;;) {
4264                 ret = intel_dp_retrain_link(encoder, &ctx);
4265
4266                 if (ret == -EDEADLK) {
4267                         drm_modeset_backoff(&ctx);
4268                         continue;
4269                 }
4270
4271                 break;
4272         }
4273
4274         drm_modeset_drop_locks(&ctx);
4275         drm_modeset_acquire_fini(&ctx);
4276         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4277
4278         return changed;
4279 }
4280
4281 /*
4282  * According to DP spec
4283  * 5.1.2:
4284  *  1. Read DPCD
4285  *  2. Configure link according to Receiver Capabilities
4286  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4287  *  4. Check link status on receipt of hot-plug interrupt
4288  *
4289  * intel_dp_short_pulse -  handles short pulse interrupts
4290  * when full detection is not required.
4291  * Returns %true if short pulse is handled and full detection
4292  * is NOT required and %false otherwise.
4293  */
4294 static bool
4295 intel_dp_short_pulse(struct intel_dp *intel_dp)
4296 {
4297         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4298         u8 sink_irq_vector = 0;
4299         u8 old_sink_count = intel_dp->sink_count;
4300         bool ret;
4301
4302         /*
4303          * Clearing compliance test variables to allow capturing
4304          * of values for next automated test request.
4305          */
4306         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4307
4308         /*
4309          * Now read the DPCD to see if it's actually running
4310          * If the current value of sink count doesn't match with
4311          * the value that was stored earlier or dpcd read failed
4312          * we need to do full detection
4313          */
4314         ret = intel_dp_get_dpcd(intel_dp);
4315
4316         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4317                 /* No need to proceed if we are going to do full detect */
4318                 return false;
4319         }
4320
4321         /* Try to read the source of the interrupt */
4322         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4323             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4324             sink_irq_vector != 0) {
4325                 /* Clear interrupt source */
4326                 drm_dp_dpcd_writeb(&intel_dp->aux,
4327                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4328                                    sink_irq_vector);
4329
4330                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4331                         intel_dp_handle_test_request(intel_dp);
4332                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4333                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4334         }
4335
4336         /* Handle CEC interrupts, if any */
4337         drm_dp_cec_irq(&intel_dp->aux);
4338
4339         /* defer to the hotplug work for link retraining if needed */
4340         if (intel_dp_needs_link_retrain(intel_dp))
4341                 return false;
4342
4343         intel_psr_short_pulse(intel_dp);
4344
4345         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4346                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4347                 /* Send a Hotplug Uevent to userspace to start modeset */
4348                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4349         }
4350
4351         return true;
4352 }
4353
4354 /* XXX this is probably wrong for multiple downstream ports */
4355 static enum drm_connector_status
4356 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4357 {
4358         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4359         uint8_t *dpcd = intel_dp->dpcd;
4360         uint8_t type;
4361
4362         if (lspcon->active)
4363                 lspcon_resume(lspcon);
4364
4365         if (!intel_dp_get_dpcd(intel_dp))
4366                 return connector_status_disconnected;
4367
4368         if (intel_dp_is_edp(intel_dp))
4369                 return connector_status_connected;
4370
4371         /* if there's no downstream port, we're done */
4372         if (!drm_dp_is_branch(dpcd))
4373                 return connector_status_connected;
4374
4375         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4376         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4377             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4378
4379                 return intel_dp->sink_count ?
4380                 connector_status_connected : connector_status_disconnected;
4381         }
4382
4383         if (intel_dp_can_mst(intel_dp))
4384                 return connector_status_connected;
4385
4386         /* If no HPD, poke DDC gently */
4387         if (drm_probe_ddc(&intel_dp->aux.ddc))
4388                 return connector_status_connected;
4389
4390         /* Well we tried, say unknown for unreliable port types */
4391         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4392                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4393                 if (type == DP_DS_PORT_TYPE_VGA ||
4394                     type == DP_DS_PORT_TYPE_NON_EDID)
4395                         return connector_status_unknown;
4396         } else {
4397                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4398                         DP_DWN_STRM_PORT_TYPE_MASK;
4399                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4400                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4401                         return connector_status_unknown;
4402         }
4403
4404         /* Anything else is out of spec, warn and ignore */
4405         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4406         return connector_status_disconnected;
4407 }
4408
4409 static enum drm_connector_status
4410 edp_detect(struct intel_dp *intel_dp)
4411 {
4412         return connector_status_connected;
4413 }
4414
4415 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4416 {
4417         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4418         u32 bit;
4419
4420         switch (encoder->hpd_pin) {
4421         case HPD_PORT_B:
4422                 bit = SDE_PORTB_HOTPLUG;
4423                 break;
4424         case HPD_PORT_C:
4425                 bit = SDE_PORTC_HOTPLUG;
4426                 break;
4427         case HPD_PORT_D:
4428                 bit = SDE_PORTD_HOTPLUG;
4429                 break;
4430         default:
4431                 MISSING_CASE(encoder->hpd_pin);
4432                 return false;
4433         }
4434
4435         return I915_READ(SDEISR) & bit;
4436 }
4437
4438 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4439 {
4440         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4441         u32 bit;
4442
4443         switch (encoder->hpd_pin) {
4444         case HPD_PORT_B:
4445                 bit = SDE_PORTB_HOTPLUG_CPT;
4446                 break;
4447         case HPD_PORT_C:
4448                 bit = SDE_PORTC_HOTPLUG_CPT;
4449                 break;
4450         case HPD_PORT_D:
4451                 bit = SDE_PORTD_HOTPLUG_CPT;
4452                 break;
4453         default:
4454                 MISSING_CASE(encoder->hpd_pin);
4455                 return false;
4456         }
4457
4458         return I915_READ(SDEISR) & bit;
4459 }
4460
4461 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4462 {
4463         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4464         u32 bit;
4465
4466         switch (encoder->hpd_pin) {
4467         case HPD_PORT_A:
4468                 bit = SDE_PORTA_HOTPLUG_SPT;
4469                 break;
4470         case HPD_PORT_E:
4471                 bit = SDE_PORTE_HOTPLUG_SPT;
4472                 break;
4473         default:
4474                 return cpt_digital_port_connected(encoder);
4475         }
4476
4477         return I915_READ(SDEISR) & bit;
4478 }
4479
4480 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4481 {
4482         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4483         u32 bit;
4484
4485         switch (encoder->hpd_pin) {
4486         case HPD_PORT_B:
4487                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4488                 break;
4489         case HPD_PORT_C:
4490                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4491                 break;
4492         case HPD_PORT_D:
4493                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4494                 break;
4495         default:
4496                 MISSING_CASE(encoder->hpd_pin);
4497                 return false;
4498         }
4499
4500         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4501 }
4502
4503 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4504 {
4505         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4506         u32 bit;
4507
4508         switch (encoder->hpd_pin) {
4509         case HPD_PORT_B:
4510                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4511                 break;
4512         case HPD_PORT_C:
4513                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4514                 break;
4515         case HPD_PORT_D:
4516                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4517                 break;
4518         default:
4519                 MISSING_CASE(encoder->hpd_pin);
4520                 return false;
4521         }
4522
4523         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4524 }
4525
4526 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4527 {
4528         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4529
4530         if (encoder->hpd_pin == HPD_PORT_A)
4531                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4532         else
4533                 return ibx_digital_port_connected(encoder);
4534 }
4535
4536 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4537 {
4538         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4539
4540         if (encoder->hpd_pin == HPD_PORT_A)
4541                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4542         else
4543                 return cpt_digital_port_connected(encoder);
4544 }
4545
4546 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4547 {
4548         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4549
4550         if (encoder->hpd_pin == HPD_PORT_A)
4551                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4552         else
4553                 return cpt_digital_port_connected(encoder);
4554 }
4555
4556 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4557 {
4558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4559
4560         if (encoder->hpd_pin == HPD_PORT_A)
4561                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4562         else
4563                 return cpt_digital_port_connected(encoder);
4564 }
4565
4566 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4567 {
4568         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4569         u32 bit;
4570
4571         switch (encoder->hpd_pin) {
4572         case HPD_PORT_A:
4573                 bit = BXT_DE_PORT_HP_DDIA;
4574                 break;
4575         case HPD_PORT_B:
4576                 bit = BXT_DE_PORT_HP_DDIB;
4577                 break;
4578         case HPD_PORT_C:
4579                 bit = BXT_DE_PORT_HP_DDIC;
4580                 break;
4581         default:
4582                 MISSING_CASE(encoder->hpd_pin);
4583                 return false;
4584         }
4585
4586         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4587 }
4588
4589 /*
4590  * intel_digital_port_connected - is the specified port connected?
4591  * @encoder: intel_encoder
4592  *
4593  * Return %true if port is connected, %false otherwise.
4594  */
4595 bool intel_digital_port_connected(struct intel_encoder *encoder)
4596 {
4597         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4598
4599         if (HAS_GMCH_DISPLAY(dev_priv)) {
4600                 if (IS_GM45(dev_priv))
4601                         return gm45_digital_port_connected(encoder);
4602                 else
4603                         return g4x_digital_port_connected(encoder);
4604         }
4605
4606         if (IS_GEN5(dev_priv))
4607                 return ilk_digital_port_connected(encoder);
4608         else if (IS_GEN6(dev_priv))
4609                 return snb_digital_port_connected(encoder);
4610         else if (IS_GEN7(dev_priv))
4611                 return ivb_digital_port_connected(encoder);
4612         else if (IS_GEN8(dev_priv))
4613                 return bdw_digital_port_connected(encoder);
4614         else if (IS_GEN9_LP(dev_priv))
4615                 return bxt_digital_port_connected(encoder);
4616         else
4617                 return spt_digital_port_connected(encoder);
4618 }
4619
4620 static struct edid *
4621 intel_dp_get_edid(struct intel_dp *intel_dp)
4622 {
4623         struct intel_connector *intel_connector = intel_dp->attached_connector;
4624
4625         /* use cached edid if we have one */
4626         if (intel_connector->edid) {
4627                 /* invalid edid */
4628                 if (IS_ERR(intel_connector->edid))
4629                         return NULL;
4630
4631                 return drm_edid_duplicate(intel_connector->edid);
4632         } else
4633                 return drm_get_edid(&intel_connector->base,
4634                                     &intel_dp->aux.ddc);
4635 }
4636
4637 static void
4638 intel_dp_set_edid(struct intel_dp *intel_dp)
4639 {
4640         struct intel_connector *intel_connector = intel_dp->attached_connector;
4641         struct edid *edid;
4642
4643         intel_dp_unset_edid(intel_dp);
4644         edid = intel_dp_get_edid(intel_dp);
4645         intel_connector->detect_edid = edid;
4646
4647         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4648         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4649 }
4650
4651 static void
4652 intel_dp_unset_edid(struct intel_dp *intel_dp)
4653 {
4654         struct intel_connector *intel_connector = intel_dp->attached_connector;
4655
4656         drm_dp_cec_unset_edid(&intel_dp->aux);
4657         kfree(intel_connector->detect_edid);
4658         intel_connector->detect_edid = NULL;
4659
4660         intel_dp->has_audio = false;
4661 }
4662
4663 static int
4664 intel_dp_long_pulse(struct intel_connector *connector)
4665 {
4666         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4667         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4668         enum drm_connector_status status;
4669         u8 sink_irq_vector = 0;
4670
4671         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4672
4673         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4674
4675         /* Can't disconnect eDP */
4676         if (intel_dp_is_edp(intel_dp))
4677                 status = edp_detect(intel_dp);
4678         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4679                 status = intel_dp_detect_dpcd(intel_dp);
4680         else
4681                 status = connector_status_disconnected;
4682
4683         if (status == connector_status_disconnected) {
4684                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4685
4686                 if (intel_dp->is_mst) {
4687                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4688                                       intel_dp->is_mst,
4689                                       intel_dp->mst_mgr.mst_state);
4690                         intel_dp->is_mst = false;
4691                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4692                                                         intel_dp->is_mst);
4693                 }
4694
4695                 goto out;
4696         }
4697
4698         if (intel_dp->reset_link_params) {
4699                 /* Initial max link lane count */
4700                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4701
4702                 /* Initial max link rate */
4703                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4704
4705                 intel_dp->reset_link_params = false;
4706         }
4707
4708         intel_dp_print_rates(intel_dp);
4709
4710         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4711                          drm_dp_is_branch(intel_dp->dpcd));
4712
4713         intel_dp_configure_mst(intel_dp);
4714
4715         if (intel_dp->is_mst) {
4716                 /*
4717                  * If we are in MST mode then this connector
4718                  * won't appear connected or have anything
4719                  * with EDID on it
4720                  */
4721                 status = connector_status_disconnected;
4722                 goto out;
4723         }
4724
4725         /*
4726          * Clearing NACK and defer counts to get their exact values
4727          * while reading EDID which are required by Compliance tests
4728          * 4.2.2.4 and 4.2.2.5
4729          */
4730         intel_dp->aux.i2c_nack_count = 0;
4731         intel_dp->aux.i2c_defer_count = 0;
4732
4733         intel_dp_set_edid(intel_dp);
4734         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4735                 status = connector_status_connected;
4736         intel_dp->detect_done = true;
4737
4738         /* Try to read the source of the interrupt */
4739         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4740             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4741             sink_irq_vector != 0) {
4742                 /* Clear interrupt source */
4743                 drm_dp_dpcd_writeb(&intel_dp->aux,
4744                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4745                                    sink_irq_vector);
4746
4747                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4748                         intel_dp_handle_test_request(intel_dp);
4749                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4750                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4751         }
4752
4753 out:
4754         if (status != connector_status_connected && !intel_dp->is_mst)
4755                 intel_dp_unset_edid(intel_dp);
4756
4757         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4758         return status;
4759 }
4760
4761 static int
4762 intel_dp_detect(struct drm_connector *connector,
4763                 struct drm_modeset_acquire_ctx *ctx,
4764                 bool force)
4765 {
4766         struct intel_dp *intel_dp = intel_attached_dp(connector);
4767         int status = connector->status;
4768
4769         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4770                       connector->base.id, connector->name);
4771
4772         /* If full detect is not performed yet, do a full detect */
4773         if (!intel_dp->detect_done) {
4774                 struct drm_crtc *crtc;
4775                 int ret;
4776
4777                 crtc = connector->state->crtc;
4778                 if (crtc) {
4779                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4780                         if (ret)
4781                                 return ret;
4782                 }
4783
4784                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4785         }
4786
4787         intel_dp->detect_done = false;
4788
4789         return status;
4790 }
4791
4792 static void
4793 intel_dp_force(struct drm_connector *connector)
4794 {
4795         struct intel_dp *intel_dp = intel_attached_dp(connector);
4796         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4797         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4798
4799         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4800                       connector->base.id, connector->name);
4801         intel_dp_unset_edid(intel_dp);
4802
4803         if (connector->status != connector_status_connected)
4804                 return;
4805
4806         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4807
4808         intel_dp_set_edid(intel_dp);
4809
4810         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4811 }
4812
4813 static int intel_dp_get_modes(struct drm_connector *connector)
4814 {
4815         struct intel_connector *intel_connector = to_intel_connector(connector);
4816         struct edid *edid;
4817
4818         edid = intel_connector->detect_edid;
4819         if (edid) {
4820                 int ret = intel_connector_update_modes(connector, edid);
4821                 if (ret)
4822                         return ret;
4823         }
4824
4825         /* if eDP has no EDID, fall back to fixed mode */
4826         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4827             intel_connector->panel.fixed_mode) {
4828                 struct drm_display_mode *mode;
4829
4830                 mode = drm_mode_duplicate(connector->dev,
4831                                           intel_connector->panel.fixed_mode);
4832                 if (mode) {
4833                         drm_mode_probed_add(connector, mode);
4834                         return 1;
4835                 }
4836         }
4837
4838         return 0;
4839 }
4840
4841 static int
4842 intel_dp_connector_register(struct drm_connector *connector)
4843 {
4844         struct intel_dp *intel_dp = intel_attached_dp(connector);
4845         struct drm_device *dev = connector->dev;
4846         int ret;
4847
4848         ret = intel_connector_register(connector);
4849         if (ret)
4850                 return ret;
4851
4852         i915_debugfs_connector_add(connector);
4853
4854         DRM_DEBUG_KMS("registering %s bus for %s\n",
4855                       intel_dp->aux.name, connector->kdev->kobj.name);
4856
4857         intel_dp->aux.dev = connector->kdev;
4858         ret = drm_dp_aux_register(&intel_dp->aux);
4859         if (!ret)
4860                 drm_dp_cec_register_connector(&intel_dp->aux,
4861                                               connector->name, dev->dev);
4862         return ret;
4863 }
4864
4865 static void
4866 intel_dp_connector_unregister(struct drm_connector *connector)
4867 {
4868         struct intel_dp *intel_dp = intel_attached_dp(connector);
4869
4870         drm_dp_cec_unregister_connector(&intel_dp->aux);
4871         drm_dp_aux_unregister(&intel_dp->aux);
4872         intel_connector_unregister(connector);
4873 }
4874
4875 static void
4876 intel_dp_connector_destroy(struct drm_connector *connector)
4877 {
4878         struct intel_connector *intel_connector = to_intel_connector(connector);
4879
4880         kfree(intel_connector->detect_edid);
4881
4882         if (!IS_ERR_OR_NULL(intel_connector->edid))
4883                 kfree(intel_connector->edid);
4884
4885         /*
4886          * Can't call intel_dp_is_edp() since the encoder may have been
4887          * destroyed already.
4888          */
4889         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4890                 intel_panel_fini(&intel_connector->panel);
4891
4892         drm_connector_cleanup(connector);
4893         kfree(connector);
4894 }
4895
4896 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4897 {
4898         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4899         struct intel_dp *intel_dp = &intel_dig_port->dp;
4900
4901         intel_dp_mst_encoder_cleanup(intel_dig_port);
4902         if (intel_dp_is_edp(intel_dp)) {
4903                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4904                 /*
4905                  * vdd might still be enabled do to the delayed vdd off.
4906                  * Make sure vdd is actually turned off here.
4907                  */
4908                 pps_lock(intel_dp);
4909                 edp_panel_vdd_off_sync(intel_dp);
4910                 pps_unlock(intel_dp);
4911
4912                 if (intel_dp->edp_notifier.notifier_call) {
4913                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4914                         intel_dp->edp_notifier.notifier_call = NULL;
4915                 }
4916         }
4917
4918         intel_dp_aux_fini(intel_dp);
4919
4920         drm_encoder_cleanup(encoder);
4921         kfree(intel_dig_port);
4922 }
4923
4924 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4925 {
4926         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4927
4928         if (!intel_dp_is_edp(intel_dp))
4929                 return;
4930
4931         /*
4932          * vdd might still be enabled do to the delayed vdd off.
4933          * Make sure vdd is actually turned off here.
4934          */
4935         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4936         pps_lock(intel_dp);
4937         edp_panel_vdd_off_sync(intel_dp);
4938         pps_unlock(intel_dp);
4939 }
4940
4941 static
4942 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
4943                                 u8 *an)
4944 {
4945         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
4946         static const struct drm_dp_aux_msg msg = {
4947                 .request = DP_AUX_NATIVE_WRITE,
4948                 .address = DP_AUX_HDCP_AKSV,
4949                 .size = DRM_HDCP_KSV_LEN,
4950         };
4951         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
4952         ssize_t dpcd_ret;
4953         int ret;
4954
4955         /* Output An first, that's easy */
4956         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
4957                                      an, DRM_HDCP_AN_LEN);
4958         if (dpcd_ret != DRM_HDCP_AN_LEN) {
4959                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
4960                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
4961         }
4962
4963         /*
4964          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
4965          * order to get it on the wire, we need to create the AUX header as if
4966          * we were writing the data, and then tickle the hardware to output the
4967          * data once the header is sent out.
4968          */
4969         intel_dp_aux_header(txbuf, &msg);
4970
4971         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
4972                                 rxbuf, sizeof(rxbuf),
4973                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
4974         if (ret < 0) {
4975                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
4976                 return ret;
4977         } else if (ret == 0) {
4978                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
4979                 return -EIO;
4980         }
4981
4982         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
4983         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
4984 }
4985
4986 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
4987                                    u8 *bksv)
4988 {
4989         ssize_t ret;
4990         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
4991                                DRM_HDCP_KSV_LEN);
4992         if (ret != DRM_HDCP_KSV_LEN) {
4993                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
4994                 return ret >= 0 ? -EIO : ret;
4995         }
4996         return 0;
4997 }
4998
4999 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5000                                       u8 *bstatus)
5001 {
5002         ssize_t ret;
5003         /*
5004          * For some reason the HDMI and DP HDCP specs call this register
5005          * definition by different names. In the HDMI spec, it's called BSTATUS,
5006          * but in DP it's called BINFO.
5007          */
5008         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5009                                bstatus, DRM_HDCP_BSTATUS_LEN);
5010         if (ret != DRM_HDCP_BSTATUS_LEN) {
5011                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5012                 return ret >= 0 ? -EIO : ret;
5013         }
5014         return 0;
5015 }
5016
5017 static
5018 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5019                              u8 *bcaps)
5020 {
5021         ssize_t ret;
5022
5023         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5024                                bcaps, 1);
5025         if (ret != 1) {
5026                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5027                 return ret >= 0 ? -EIO : ret;
5028         }
5029
5030         return 0;
5031 }
5032
5033 static
5034 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5035                                    bool *repeater_present)
5036 {
5037         ssize_t ret;
5038         u8 bcaps;
5039
5040         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5041         if (ret)
5042                 return ret;
5043
5044         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5045         return 0;
5046 }
5047
5048 static
5049 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5050                                 u8 *ri_prime)
5051 {
5052         ssize_t ret;
5053         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5054                                ri_prime, DRM_HDCP_RI_LEN);
5055         if (ret != DRM_HDCP_RI_LEN) {
5056                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5057                 return ret >= 0 ? -EIO : ret;
5058         }
5059         return 0;
5060 }
5061
5062 static
5063 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5064                                  bool *ksv_ready)
5065 {
5066         ssize_t ret;
5067         u8 bstatus;
5068         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5069                                &bstatus, 1);
5070         if (ret != 1) {
5071                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5072                 return ret >= 0 ? -EIO : ret;
5073         }
5074         *ksv_ready = bstatus & DP_BSTATUS_READY;
5075         return 0;
5076 }
5077
5078 static
5079 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5080                                 int num_downstream, u8 *ksv_fifo)
5081 {
5082         ssize_t ret;
5083         int i;
5084
5085         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5086         for (i = 0; i < num_downstream; i += 3) {
5087                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5088                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5089                                        DP_AUX_HDCP_KSV_FIFO,
5090                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5091                                        len);
5092                 if (ret != len) {
5093                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5094                                   ret);
5095                         return ret >= 0 ? -EIO : ret;
5096                 }
5097         }
5098         return 0;
5099 }
5100
5101 static
5102 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5103                                     int i, u32 *part)
5104 {
5105         ssize_t ret;
5106
5107         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5108                 return -EINVAL;
5109
5110         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5111                                DP_AUX_HDCP_V_PRIME(i), part,
5112                                DRM_HDCP_V_PRIME_PART_LEN);
5113         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5114                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5115                 return ret >= 0 ? -EIO : ret;
5116         }
5117         return 0;
5118 }
5119
5120 static
5121 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5122                                     bool enable)
5123 {
5124         /* Not used for single stream DisplayPort setups */
5125         return 0;
5126 }
5127
5128 static
5129 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5130 {
5131         ssize_t ret;
5132         u8 bstatus;
5133
5134         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5135                                &bstatus, 1);
5136         if (ret != 1) {
5137                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5138                 return false;
5139         }
5140
5141         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5142 }
5143
5144 static
5145 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5146                           bool *hdcp_capable)
5147 {
5148         ssize_t ret;
5149         u8 bcaps;
5150
5151         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5152         if (ret)
5153                 return ret;
5154
5155         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5156         return 0;
5157 }
5158
5159 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5160         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5161         .read_bksv = intel_dp_hdcp_read_bksv,
5162         .read_bstatus = intel_dp_hdcp_read_bstatus,
5163         .repeater_present = intel_dp_hdcp_repeater_present,
5164         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5165         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5166         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5167         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5168         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5169         .check_link = intel_dp_hdcp_check_link,
5170         .hdcp_capable = intel_dp_hdcp_capable,
5171 };
5172
5173 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5174 {
5175         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5176
5177         lockdep_assert_held(&dev_priv->pps_mutex);
5178
5179         if (!edp_have_panel_vdd(intel_dp))
5180                 return;
5181
5182         /*
5183          * The VDD bit needs a power domain reference, so if the bit is
5184          * already enabled when we boot or resume, grab this reference and
5185          * schedule a vdd off, so we don't hold on to the reference
5186          * indefinitely.
5187          */
5188         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5189         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5190
5191         edp_panel_vdd_schedule_off(intel_dp);
5192 }
5193
5194 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5195 {
5196         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5197         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5198         enum pipe pipe;
5199
5200         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5201                                   encoder->port, &pipe))
5202                 return pipe;
5203
5204         return INVALID_PIPE;
5205 }
5206
5207 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5208 {
5209         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5210         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5211         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5212
5213         if (!HAS_DDI(dev_priv))
5214                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5215
5216         if (lspcon->active)
5217                 lspcon_resume(lspcon);
5218
5219         intel_dp->reset_link_params = true;
5220
5221         pps_lock(intel_dp);
5222
5223         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5224                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5225
5226         if (intel_dp_is_edp(intel_dp)) {
5227                 /* Reinit the power sequencer, in case BIOS did something with it. */
5228                 intel_dp_pps_init(intel_dp);
5229                 intel_edp_panel_vdd_sanitize(intel_dp);
5230         }
5231
5232         pps_unlock(intel_dp);
5233 }
5234
5235 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5236         .force = intel_dp_force,
5237         .fill_modes = drm_helper_probe_single_connector_modes,
5238         .atomic_get_property = intel_digital_connector_atomic_get_property,
5239         .atomic_set_property = intel_digital_connector_atomic_set_property,
5240         .late_register = intel_dp_connector_register,
5241         .early_unregister = intel_dp_connector_unregister,
5242         .destroy = intel_dp_connector_destroy,
5243         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5244         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5245 };
5246
5247 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5248         .detect_ctx = intel_dp_detect,
5249         .get_modes = intel_dp_get_modes,
5250         .mode_valid = intel_dp_mode_valid,
5251         .atomic_check = intel_digital_connector_atomic_check,
5252 };
5253
5254 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5255         .reset = intel_dp_encoder_reset,
5256         .destroy = intel_dp_encoder_destroy,
5257 };
5258
5259 enum irqreturn
5260 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5261 {
5262         struct intel_dp *intel_dp = &intel_dig_port->dp;
5263         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5264         enum irqreturn ret = IRQ_NONE;
5265
5266         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5267                 /*
5268                  * vdd off can generate a long pulse on eDP which
5269                  * would require vdd on to handle it, and thus we
5270                  * would end up in an endless cycle of
5271                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5272                  */
5273                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5274                               port_name(intel_dig_port->base.port));
5275                 return IRQ_HANDLED;
5276         }
5277
5278         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5279                       port_name(intel_dig_port->base.port),
5280                       long_hpd ? "long" : "short");
5281
5282         if (long_hpd) {
5283                 intel_dp->reset_link_params = true;
5284                 intel_dp->detect_done = false;
5285                 return IRQ_NONE;
5286         }
5287
5288         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5289
5290         if (intel_dp->is_mst) {
5291                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5292                         /*
5293                          * If we were in MST mode, and device is not
5294                          * there, get out of MST mode
5295                          */
5296                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5297                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5298                         intel_dp->is_mst = false;
5299                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5300                                                         intel_dp->is_mst);
5301                         intel_dp->detect_done = false;
5302                         goto put_power;
5303                 }
5304         }
5305
5306         if (!intel_dp->is_mst) {
5307                 bool handled;
5308
5309                 handled = intel_dp_short_pulse(intel_dp);
5310
5311                 /* Short pulse can signify loss of hdcp authentication */
5312                 intel_hdcp_check_link(intel_dp->attached_connector);
5313
5314                 if (!handled) {
5315                         intel_dp->detect_done = false;
5316                         goto put_power;
5317                 }
5318         }
5319
5320         ret = IRQ_HANDLED;
5321
5322 put_power:
5323         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5324
5325         return ret;
5326 }
5327
5328 /* check the VBT to see whether the eDP is on another port */
5329 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5330 {
5331         /*
5332          * eDP not supported on g4x. so bail out early just
5333          * for a bit extra safety in case the VBT is bonkers.
5334          */
5335         if (INTEL_GEN(dev_priv) < 5)
5336                 return false;
5337
5338         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5339                 return true;
5340
5341         return intel_bios_is_port_edp(dev_priv, port);
5342 }
5343
5344 static void
5345 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5346 {
5347         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5348         enum port port = dp_to_dig_port(intel_dp)->base.port;
5349
5350         if (!IS_G4X(dev_priv) && port != PORT_A)
5351                 intel_attach_force_audio_property(connector);
5352
5353         intel_attach_broadcast_rgb_property(connector);
5354
5355         if (intel_dp_is_edp(intel_dp)) {
5356                 u32 allowed_scalers;
5357
5358                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5359                 if (!HAS_GMCH_DISPLAY(dev_priv))
5360                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5361
5362                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5363
5364                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5365
5366         }
5367 }
5368
5369 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5370 {
5371         intel_dp->panel_power_off_time = ktime_get_boottime();
5372         intel_dp->last_power_on = jiffies;
5373         intel_dp->last_backlight_off = jiffies;
5374 }
5375
5376 static void
5377 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5378 {
5379         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5380         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5381         struct pps_registers regs;
5382
5383         intel_pps_get_registers(intel_dp, &regs);
5384
5385         /* Workaround: Need to write PP_CONTROL with the unlock key as
5386          * the very first thing. */
5387         pp_ctl = ironlake_get_pp_control(intel_dp);
5388
5389         pp_on = I915_READ(regs.pp_on);
5390         pp_off = I915_READ(regs.pp_off);
5391         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5392             !HAS_PCH_ICP(dev_priv)) {
5393                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5394                 pp_div = I915_READ(regs.pp_div);
5395         }
5396
5397         /* Pull timing values out of registers */
5398         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5399                      PANEL_POWER_UP_DELAY_SHIFT;
5400
5401         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5402                   PANEL_LIGHT_ON_DELAY_SHIFT;
5403
5404         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5405                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5406
5407         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5408                    PANEL_POWER_DOWN_DELAY_SHIFT;
5409
5410         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5411             HAS_PCH_ICP(dev_priv)) {
5412                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5413                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5414         } else {
5415                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5416                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5417         }
5418 }
5419
5420 static void
5421 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5422 {
5423         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5424                       state_name,
5425                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5426 }
5427
5428 static void
5429 intel_pps_verify_state(struct intel_dp *intel_dp)
5430 {
5431         struct edp_power_seq hw;
5432         struct edp_power_seq *sw = &intel_dp->pps_delays;
5433
5434         intel_pps_readout_hw_state(intel_dp, &hw);
5435
5436         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5437             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5438                 DRM_ERROR("PPS state mismatch\n");
5439                 intel_pps_dump_state("sw", sw);
5440                 intel_pps_dump_state("hw", &hw);
5441         }
5442 }
5443
5444 static void
5445 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5446 {
5447         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5448         struct edp_power_seq cur, vbt, spec,
5449                 *final = &intel_dp->pps_delays;
5450
5451         lockdep_assert_held(&dev_priv->pps_mutex);
5452
5453         /* already initialized? */
5454         if (final->t11_t12 != 0)
5455                 return;
5456
5457         intel_pps_readout_hw_state(intel_dp, &cur);
5458
5459         intel_pps_dump_state("cur", &cur);
5460
5461         vbt = dev_priv->vbt.edp.pps;
5462         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5463          * of 500ms appears to be too short. Ocassionally the panel
5464          * just fails to power back on. Increasing the delay to 800ms
5465          * seems sufficient to avoid this problem.
5466          */
5467         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5468                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5469                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5470                               vbt.t11_t12);
5471         }
5472         /* T11_T12 delay is special and actually in units of 100ms, but zero
5473          * based in the hw (so we need to add 100 ms). But the sw vbt
5474          * table multiplies it with 1000 to make it in units of 100usec,
5475          * too. */
5476         vbt.t11_t12 += 100 * 10;
5477
5478         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5479          * our hw here, which are all in 100usec. */
5480         spec.t1_t3 = 210 * 10;
5481         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5482         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5483         spec.t10 = 500 * 10;
5484         /* This one is special and actually in units of 100ms, but zero
5485          * based in the hw (so we need to add 100 ms). But the sw vbt
5486          * table multiplies it with 1000 to make it in units of 100usec,
5487          * too. */
5488         spec.t11_t12 = (510 + 100) * 10;
5489
5490         intel_pps_dump_state("vbt", &vbt);
5491
5492         /* Use the max of the register settings and vbt. If both are
5493          * unset, fall back to the spec limits. */
5494 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5495                                        spec.field : \
5496                                        max(cur.field, vbt.field))
5497         assign_final(t1_t3);
5498         assign_final(t8);
5499         assign_final(t9);
5500         assign_final(t10);
5501         assign_final(t11_t12);
5502 #undef assign_final
5503
5504 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5505         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5506         intel_dp->backlight_on_delay = get_delay(t8);
5507         intel_dp->backlight_off_delay = get_delay(t9);
5508         intel_dp->panel_power_down_delay = get_delay(t10);
5509         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5510 #undef get_delay
5511
5512         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5513                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5514                       intel_dp->panel_power_cycle_delay);
5515
5516         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5517                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5518
5519         /*
5520          * We override the HW backlight delays to 1 because we do manual waits
5521          * on them. For T8, even BSpec recommends doing it. For T9, if we
5522          * don't do this, we'll end up waiting for the backlight off delay
5523          * twice: once when we do the manual sleep, and once when we disable
5524          * the panel and wait for the PP_STATUS bit to become zero.
5525          */
5526         final->t8 = 1;
5527         final->t9 = 1;
5528
5529         /*
5530          * HW has only a 100msec granularity for t11_t12 so round it up
5531          * accordingly.
5532          */
5533         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5534 }
5535
5536 static void
5537 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5538                                               bool force_disable_vdd)
5539 {
5540         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5541         u32 pp_on, pp_off, pp_div, port_sel = 0;
5542         int div = dev_priv->rawclk_freq / 1000;
5543         struct pps_registers regs;
5544         enum port port = dp_to_dig_port(intel_dp)->base.port;
5545         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5546
5547         lockdep_assert_held(&dev_priv->pps_mutex);
5548
5549         intel_pps_get_registers(intel_dp, &regs);
5550
5551         /*
5552          * On some VLV machines the BIOS can leave the VDD
5553          * enabled even on power sequencers which aren't
5554          * hooked up to any port. This would mess up the
5555          * power domain tracking the first time we pick
5556          * one of these power sequencers for use since
5557          * edp_panel_vdd_on() would notice that the VDD was
5558          * already on and therefore wouldn't grab the power
5559          * domain reference. Disable VDD first to avoid this.
5560          * This also avoids spuriously turning the VDD on as
5561          * soon as the new power sequencer gets initialized.
5562          */
5563         if (force_disable_vdd) {
5564                 u32 pp = ironlake_get_pp_control(intel_dp);
5565
5566                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5567
5568                 if (pp & EDP_FORCE_VDD)
5569                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5570
5571                 pp &= ~EDP_FORCE_VDD;
5572
5573                 I915_WRITE(regs.pp_ctrl, pp);
5574         }
5575
5576         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5577                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5578         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5579                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5580         /* Compute the divisor for the pp clock, simply match the Bspec
5581          * formula. */
5582         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5583             HAS_PCH_ICP(dev_priv)) {
5584                 pp_div = I915_READ(regs.pp_ctrl);
5585                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5586                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5587                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5588         } else {
5589                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5590                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5591                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5592         }
5593
5594         /* Haswell doesn't have any port selection bits for the panel
5595          * power sequencer any more. */
5596         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5597                 port_sel = PANEL_PORT_SELECT_VLV(port);
5598         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5599                 switch (port) {
5600                 case PORT_A:
5601                         port_sel = PANEL_PORT_SELECT_DPA;
5602                         break;
5603                 case PORT_C:
5604                         port_sel = PANEL_PORT_SELECT_DPC;
5605                         break;
5606                 case PORT_D:
5607                         port_sel = PANEL_PORT_SELECT_DPD;
5608                         break;
5609                 default:
5610                         MISSING_CASE(port);
5611                         break;
5612                 }
5613         }
5614
5615         pp_on |= port_sel;
5616
5617         I915_WRITE(regs.pp_on, pp_on);
5618         I915_WRITE(regs.pp_off, pp_off);
5619         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5620             HAS_PCH_ICP(dev_priv))
5621                 I915_WRITE(regs.pp_ctrl, pp_div);
5622         else
5623                 I915_WRITE(regs.pp_div, pp_div);
5624
5625         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5626                       I915_READ(regs.pp_on),
5627                       I915_READ(regs.pp_off),
5628                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5629                        HAS_PCH_ICP(dev_priv)) ?
5630                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5631                       I915_READ(regs.pp_div));
5632 }
5633
5634 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5635 {
5636         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5637
5638         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5639                 vlv_initial_power_sequencer_setup(intel_dp);
5640         } else {
5641                 intel_dp_init_panel_power_sequencer(intel_dp);
5642                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5643         }
5644 }
5645
5646 /**
5647  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5648  * @dev_priv: i915 device
5649  * @crtc_state: a pointer to the active intel_crtc_state
5650  * @refresh_rate: RR to be programmed
5651  *
5652  * This function gets called when refresh rate (RR) has to be changed from
5653  * one frequency to another. Switches can be between high and low RR
5654  * supported by the panel or to any other RR based on media playback (in
5655  * this case, RR value needs to be passed from user space).
5656  *
5657  * The caller of this function needs to take a lock on dev_priv->drrs.
5658  */
5659 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5660                                     const struct intel_crtc_state *crtc_state,
5661                                     int refresh_rate)
5662 {
5663         struct intel_encoder *encoder;
5664         struct intel_digital_port *dig_port = NULL;
5665         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5667         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5668
5669         if (refresh_rate <= 0) {
5670                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5671                 return;
5672         }
5673
5674         if (intel_dp == NULL) {
5675                 DRM_DEBUG_KMS("DRRS not supported.\n");
5676                 return;
5677         }
5678
5679         dig_port = dp_to_dig_port(intel_dp);
5680         encoder = &dig_port->base;
5681
5682         if (!intel_crtc) {
5683                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5684                 return;
5685         }
5686
5687         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5688                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5689                 return;
5690         }
5691
5692         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5693                         refresh_rate)
5694                 index = DRRS_LOW_RR;
5695
5696         if (index == dev_priv->drrs.refresh_rate_type) {
5697                 DRM_DEBUG_KMS(
5698                         "DRRS requested for previously set RR...ignoring\n");
5699                 return;
5700         }
5701
5702         if (!crtc_state->base.active) {
5703                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5704                 return;
5705         }
5706
5707         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5708                 switch (index) {
5709                 case DRRS_HIGH_RR:
5710                         intel_dp_set_m_n(intel_crtc, M1_N1);
5711                         break;
5712                 case DRRS_LOW_RR:
5713                         intel_dp_set_m_n(intel_crtc, M2_N2);
5714                         break;
5715                 case DRRS_MAX_RR:
5716                 default:
5717                         DRM_ERROR("Unsupported refreshrate type\n");
5718                 }
5719         } else if (INTEL_GEN(dev_priv) > 6) {
5720                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5721                 u32 val;
5722
5723                 val = I915_READ(reg);
5724                 if (index > DRRS_HIGH_RR) {
5725                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5726                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5727                         else
5728                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5729                 } else {
5730                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5731                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5732                         else
5733                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5734                 }
5735                 I915_WRITE(reg, val);
5736         }
5737
5738         dev_priv->drrs.refresh_rate_type = index;
5739
5740         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5741 }
5742
5743 /**
5744  * intel_edp_drrs_enable - init drrs struct if supported
5745  * @intel_dp: DP struct
5746  * @crtc_state: A pointer to the active crtc state.
5747  *
5748  * Initializes frontbuffer_bits and drrs.dp
5749  */
5750 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5751                            const struct intel_crtc_state *crtc_state)
5752 {
5753         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5754
5755         if (!crtc_state->has_drrs) {
5756                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5757                 return;
5758         }
5759
5760         if (dev_priv->psr.enabled) {
5761                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5762                 return;
5763         }
5764
5765         mutex_lock(&dev_priv->drrs.mutex);
5766         if (WARN_ON(dev_priv->drrs.dp)) {
5767                 DRM_ERROR("DRRS already enabled\n");
5768                 goto unlock;
5769         }
5770
5771         dev_priv->drrs.busy_frontbuffer_bits = 0;
5772
5773         dev_priv->drrs.dp = intel_dp;
5774
5775 unlock:
5776         mutex_unlock(&dev_priv->drrs.mutex);
5777 }
5778
5779 /**
5780  * intel_edp_drrs_disable - Disable DRRS
5781  * @intel_dp: DP struct
5782  * @old_crtc_state: Pointer to old crtc_state.
5783  *
5784  */
5785 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5786                             const struct intel_crtc_state *old_crtc_state)
5787 {
5788         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5789
5790         if (!old_crtc_state->has_drrs)
5791                 return;
5792
5793         mutex_lock(&dev_priv->drrs.mutex);
5794         if (!dev_priv->drrs.dp) {
5795                 mutex_unlock(&dev_priv->drrs.mutex);
5796                 return;
5797         }
5798
5799         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5800                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5801                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5802
5803         dev_priv->drrs.dp = NULL;
5804         mutex_unlock(&dev_priv->drrs.mutex);
5805
5806         cancel_delayed_work_sync(&dev_priv->drrs.work);
5807 }
5808
5809 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5810 {
5811         struct drm_i915_private *dev_priv =
5812                 container_of(work, typeof(*dev_priv), drrs.work.work);
5813         struct intel_dp *intel_dp;
5814
5815         mutex_lock(&dev_priv->drrs.mutex);
5816
5817         intel_dp = dev_priv->drrs.dp;
5818
5819         if (!intel_dp)
5820                 goto unlock;
5821
5822         /*
5823          * The delayed work can race with an invalidate hence we need to
5824          * recheck.
5825          */
5826
5827         if (dev_priv->drrs.busy_frontbuffer_bits)
5828                 goto unlock;
5829
5830         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5831                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5832
5833                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5834                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5835         }
5836
5837 unlock:
5838         mutex_unlock(&dev_priv->drrs.mutex);
5839 }
5840
5841 /**
5842  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5843  * @dev_priv: i915 device
5844  * @frontbuffer_bits: frontbuffer plane tracking bits
5845  *
5846  * This function gets called everytime rendering on the given planes start.
5847  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5848  *
5849  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5850  */
5851 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5852                                unsigned int frontbuffer_bits)
5853 {
5854         struct drm_crtc *crtc;
5855         enum pipe pipe;
5856
5857         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5858                 return;
5859
5860         cancel_delayed_work(&dev_priv->drrs.work);
5861
5862         mutex_lock(&dev_priv->drrs.mutex);
5863         if (!dev_priv->drrs.dp) {
5864                 mutex_unlock(&dev_priv->drrs.mutex);
5865                 return;
5866         }
5867
5868         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5869         pipe = to_intel_crtc(crtc)->pipe;
5870
5871         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5872         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5873
5874         /* invalidate means busy screen hence upclock */
5875         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5876                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5877                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5878
5879         mutex_unlock(&dev_priv->drrs.mutex);
5880 }
5881
5882 /**
5883  * intel_edp_drrs_flush - Restart Idleness DRRS
5884  * @dev_priv: i915 device
5885  * @frontbuffer_bits: frontbuffer plane tracking bits
5886  *
5887  * This function gets called every time rendering on the given planes has
5888  * completed or flip on a crtc is completed. So DRRS should be upclocked
5889  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5890  * if no other planes are dirty.
5891  *
5892  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5893  */
5894 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5895                           unsigned int frontbuffer_bits)
5896 {
5897         struct drm_crtc *crtc;
5898         enum pipe pipe;
5899
5900         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5901                 return;
5902
5903         cancel_delayed_work(&dev_priv->drrs.work);
5904
5905         mutex_lock(&dev_priv->drrs.mutex);
5906         if (!dev_priv->drrs.dp) {
5907                 mutex_unlock(&dev_priv->drrs.mutex);
5908                 return;
5909         }
5910
5911         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5912         pipe = to_intel_crtc(crtc)->pipe;
5913
5914         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5915         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5916
5917         /* flush means busy screen hence upclock */
5918         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5919                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5920                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5921
5922         /*
5923          * flush also means no more activity hence schedule downclock, if all
5924          * other fbs are quiescent too
5925          */
5926         if (!dev_priv->drrs.busy_frontbuffer_bits)
5927                 schedule_delayed_work(&dev_priv->drrs.work,
5928                                 msecs_to_jiffies(1000));
5929         mutex_unlock(&dev_priv->drrs.mutex);
5930 }
5931
5932 /**
5933  * DOC: Display Refresh Rate Switching (DRRS)
5934  *
5935  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5936  * which enables swtching between low and high refresh rates,
5937  * dynamically, based on the usage scenario. This feature is applicable
5938  * for internal panels.
5939  *
5940  * Indication that the panel supports DRRS is given by the panel EDID, which
5941  * would list multiple refresh rates for one resolution.
5942  *
5943  * DRRS is of 2 types - static and seamless.
5944  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5945  * (may appear as a blink on screen) and is used in dock-undock scenario.
5946  * Seamless DRRS involves changing RR without any visual effect to the user
5947  * and can be used during normal system usage. This is done by programming
5948  * certain registers.
5949  *
5950  * Support for static/seamless DRRS may be indicated in the VBT based on
5951  * inputs from the panel spec.
5952  *
5953  * DRRS saves power by switching to low RR based on usage scenarios.
5954  *
5955  * The implementation is based on frontbuffer tracking implementation.  When
5956  * there is a disturbance on the screen triggered by user activity or a periodic
5957  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5958  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5959  * made.
5960  *
5961  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5962  * and intel_edp_drrs_flush() are called.
5963  *
5964  * DRRS can be further extended to support other internal panels and also
5965  * the scenario of video playback wherein RR is set based on the rate
5966  * requested by userspace.
5967  */
5968
5969 /**
5970  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5971  * @connector: eDP connector
5972  * @fixed_mode: preferred mode of panel
5973  *
5974  * This function is  called only once at driver load to initialize basic
5975  * DRRS stuff.
5976  *
5977  * Returns:
5978  * Downclock mode if panel supports it, else return NULL.
5979  * DRRS support is determined by the presence of downclock mode (apart
5980  * from VBT setting).
5981  */
5982 static struct drm_display_mode *
5983 intel_dp_drrs_init(struct intel_connector *connector,
5984                    struct drm_display_mode *fixed_mode)
5985 {
5986         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5987         struct drm_display_mode *downclock_mode = NULL;
5988
5989         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5990         mutex_init(&dev_priv->drrs.mutex);
5991
5992         if (INTEL_GEN(dev_priv) <= 6) {
5993                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5994                 return NULL;
5995         }
5996
5997         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5998                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5999                 return NULL;
6000         }
6001
6002         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6003                                                     &connector->base);
6004
6005         if (!downclock_mode) {
6006                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6007                 return NULL;
6008         }
6009
6010         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6011
6012         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6013         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6014         return downclock_mode;
6015 }
6016
6017 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6018                                      struct intel_connector *intel_connector)
6019 {
6020         struct drm_device *dev = intel_dp_to_dev(intel_dp);
6021         struct drm_i915_private *dev_priv = to_i915(dev);
6022         struct drm_connector *connector = &intel_connector->base;
6023         struct drm_display_mode *fixed_mode = NULL;
6024         struct drm_display_mode *downclock_mode = NULL;
6025         bool has_dpcd;
6026         struct drm_display_mode *scan;
6027         struct edid *edid;
6028         enum pipe pipe = INVALID_PIPE;
6029
6030         if (!intel_dp_is_edp(intel_dp))
6031                 return true;
6032
6033         /*
6034          * On IBX/CPT we may get here with LVDS already registered. Since the
6035          * driver uses the only internal power sequencer available for both
6036          * eDP and LVDS bail out early in this case to prevent interfering
6037          * with an already powered-on LVDS power sequencer.
6038          */
6039         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6040                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6041                 DRM_INFO("LVDS was detected, not registering eDP\n");
6042
6043                 return false;
6044         }
6045
6046         pps_lock(intel_dp);
6047
6048         intel_dp_init_panel_power_timestamps(intel_dp);
6049         intel_dp_pps_init(intel_dp);
6050         intel_edp_panel_vdd_sanitize(intel_dp);
6051
6052         pps_unlock(intel_dp);
6053
6054         /* Cache DPCD and EDID for edp. */
6055         has_dpcd = intel_edp_init_dpcd(intel_dp);
6056
6057         if (!has_dpcd) {
6058                 /* if this fails, presume the device is a ghost */
6059                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6060                 goto out_vdd_off;
6061         }
6062
6063         mutex_lock(&dev->mode_config.mutex);
6064         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6065         if (edid) {
6066                 if (drm_add_edid_modes(connector, edid)) {
6067                         drm_connector_update_edid_property(connector,
6068                                                                 edid);
6069                 } else {
6070                         kfree(edid);
6071                         edid = ERR_PTR(-EINVAL);
6072                 }
6073         } else {
6074                 edid = ERR_PTR(-ENOENT);
6075         }
6076         intel_connector->edid = edid;
6077
6078         /* prefer fixed mode from EDID if available */
6079         list_for_each_entry(scan, &connector->probed_modes, head) {
6080                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6081                         fixed_mode = drm_mode_duplicate(dev, scan);
6082                         downclock_mode = intel_dp_drrs_init(
6083                                                 intel_connector, fixed_mode);
6084                         break;
6085                 }
6086         }
6087
6088         /* fallback to VBT if available for eDP */
6089         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6090                 fixed_mode = drm_mode_duplicate(dev,
6091                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6092                 if (fixed_mode) {
6093                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6094                         connector->display_info.width_mm = fixed_mode->width_mm;
6095                         connector->display_info.height_mm = fixed_mode->height_mm;
6096                 }
6097         }
6098         mutex_unlock(&dev->mode_config.mutex);
6099
6100         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6101                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6102                 register_reboot_notifier(&intel_dp->edp_notifier);
6103
6104                 /*
6105                  * Figure out the current pipe for the initial backlight setup.
6106                  * If the current pipe isn't valid, try the PPS pipe, and if that
6107                  * fails just assume pipe A.
6108                  */
6109                 pipe = vlv_active_pipe(intel_dp);
6110
6111                 if (pipe != PIPE_A && pipe != PIPE_B)
6112                         pipe = intel_dp->pps_pipe;
6113
6114                 if (pipe != PIPE_A && pipe != PIPE_B)
6115                         pipe = PIPE_A;
6116
6117                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6118                               pipe_name(pipe));
6119         }
6120
6121         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6122         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6123         intel_panel_setup_backlight(connector, pipe);
6124
6125         return true;
6126
6127 out_vdd_off:
6128         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6129         /*
6130          * vdd might still be enabled do to the delayed vdd off.
6131          * Make sure vdd is actually turned off here.
6132          */
6133         pps_lock(intel_dp);
6134         edp_panel_vdd_off_sync(intel_dp);
6135         pps_unlock(intel_dp);
6136
6137         return false;
6138 }
6139
6140 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6141 {
6142         struct intel_connector *intel_connector;
6143         struct drm_connector *connector;
6144
6145         intel_connector = container_of(work, typeof(*intel_connector),
6146                                        modeset_retry_work);
6147         connector = &intel_connector->base;
6148         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6149                       connector->name);
6150
6151         /* Grab the locks before changing connector property*/
6152         mutex_lock(&connector->dev->mode_config.mutex);
6153         /* Set connector link status to BAD and send a Uevent to notify
6154          * userspace to do a modeset.
6155          */
6156         drm_connector_set_link_status_property(connector,
6157                                                DRM_MODE_LINK_STATUS_BAD);
6158         mutex_unlock(&connector->dev->mode_config.mutex);
6159         /* Send Hotplug uevent so userspace can reprobe */
6160         drm_kms_helper_hotplug_event(connector->dev);
6161 }
6162
6163 bool
6164 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6165                         struct intel_connector *intel_connector)
6166 {
6167         struct drm_connector *connector = &intel_connector->base;
6168         struct intel_dp *intel_dp = &intel_dig_port->dp;
6169         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6170         struct drm_device *dev = intel_encoder->base.dev;
6171         struct drm_i915_private *dev_priv = to_i915(dev);
6172         enum port port = intel_encoder->port;
6173         int type;
6174
6175         /* Initialize the work for modeset in case of link train failure */
6176         INIT_WORK(&intel_connector->modeset_retry_work,
6177                   intel_dp_modeset_retry_work_fn);
6178
6179         if (WARN(intel_dig_port->max_lanes < 1,
6180                  "Not enough lanes (%d) for DP on port %c\n",
6181                  intel_dig_port->max_lanes, port_name(port)))
6182                 return false;
6183
6184         intel_dp_set_source_rates(intel_dp);
6185
6186         intel_dp->reset_link_params = true;
6187         intel_dp->pps_pipe = INVALID_PIPE;
6188         intel_dp->active_pipe = INVALID_PIPE;
6189
6190         /* intel_dp vfuncs */
6191         if (HAS_DDI(dev_priv))
6192                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6193
6194         /* Preserve the current hw state. */
6195         intel_dp->DP = I915_READ(intel_dp->output_reg);
6196         intel_dp->attached_connector = intel_connector;
6197
6198         if (intel_dp_is_port_edp(dev_priv, port))
6199                 type = DRM_MODE_CONNECTOR_eDP;
6200         else
6201                 type = DRM_MODE_CONNECTOR_DisplayPort;
6202
6203         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6204                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6205
6206         /*
6207          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6208          * for DP the encoder type can be set by the caller to
6209          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6210          */
6211         if (type == DRM_MODE_CONNECTOR_eDP)
6212                 intel_encoder->type = INTEL_OUTPUT_EDP;
6213
6214         /* eDP only on port B and/or C on vlv/chv */
6215         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6216                     intel_dp_is_edp(intel_dp) &&
6217                     port != PORT_B && port != PORT_C))
6218                 return false;
6219
6220         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6221                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6222                         port_name(port));
6223
6224         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6225         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6226
6227         if (!HAS_GMCH_DISPLAY(dev_priv))
6228                 connector->interlace_allowed = true;
6229         connector->doublescan_allowed = 0;
6230
6231         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6232
6233         intel_dp_aux_init(intel_dp);
6234
6235         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6236                           edp_panel_vdd_work);
6237
6238         intel_connector_attach_encoder(intel_connector, intel_encoder);
6239
6240         if (HAS_DDI(dev_priv))
6241                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6242         else
6243                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6244
6245         /* init MST on ports that can support it */
6246         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6247             (port == PORT_B || port == PORT_C ||
6248              port == PORT_D || port == PORT_F))
6249                 intel_dp_mst_encoder_init(intel_dig_port,
6250                                           intel_connector->base.base.id);
6251
6252         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6253                 intel_dp_aux_fini(intel_dp);
6254                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6255                 goto fail;
6256         }
6257
6258         intel_dp_add_properties(intel_dp, connector);
6259
6260         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6261                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6262                 if (ret)
6263                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6264         }
6265
6266         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6267          * 0xd.  Failure to do so will result in spurious interrupts being
6268          * generated on the port when a cable is not attached.
6269          */
6270         if (IS_G45(dev_priv)) {
6271                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6272                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6273         }
6274
6275         return true;
6276
6277 fail:
6278         drm_connector_cleanup(connector);
6279
6280         return false;
6281 }
6282
6283 bool intel_dp_init(struct drm_i915_private *dev_priv,
6284                    i915_reg_t output_reg,
6285                    enum port port)
6286 {
6287         struct intel_digital_port *intel_dig_port;
6288         struct intel_encoder *intel_encoder;
6289         struct drm_encoder *encoder;
6290         struct intel_connector *intel_connector;
6291
6292         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6293         if (!intel_dig_port)
6294                 return false;
6295
6296         intel_connector = intel_connector_alloc();
6297         if (!intel_connector)
6298                 goto err_connector_alloc;
6299
6300         intel_encoder = &intel_dig_port->base;
6301         encoder = &intel_encoder->base;
6302
6303         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6304                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6305                              "DP %c", port_name(port)))
6306                 goto err_encoder_init;
6307
6308         intel_encoder->hotplug = intel_dp_hotplug;
6309         intel_encoder->compute_config = intel_dp_compute_config;
6310         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6311         intel_encoder->get_config = intel_dp_get_config;
6312         intel_encoder->suspend = intel_dp_encoder_suspend;
6313         if (IS_CHERRYVIEW(dev_priv)) {
6314                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6315                 intel_encoder->pre_enable = chv_pre_enable_dp;
6316                 intel_encoder->enable = vlv_enable_dp;
6317                 intel_encoder->disable = vlv_disable_dp;
6318                 intel_encoder->post_disable = chv_post_disable_dp;
6319                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6320         } else if (IS_VALLEYVIEW(dev_priv)) {
6321                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6322                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6323                 intel_encoder->enable = vlv_enable_dp;
6324                 intel_encoder->disable = vlv_disable_dp;
6325                 intel_encoder->post_disable = vlv_post_disable_dp;
6326         } else {
6327                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6328                 intel_encoder->enable = g4x_enable_dp;
6329                 intel_encoder->disable = g4x_disable_dp;
6330                 intel_encoder->post_disable = g4x_post_disable_dp;
6331         }
6332
6333         intel_dig_port->dp.output_reg = output_reg;
6334         intel_dig_port->max_lanes = 4;
6335
6336         intel_encoder->type = INTEL_OUTPUT_DP;
6337         intel_encoder->power_domain = intel_port_to_power_domain(port);
6338         if (IS_CHERRYVIEW(dev_priv)) {
6339                 if (port == PORT_D)
6340                         intel_encoder->crtc_mask = 1 << 2;
6341                 else
6342                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6343         } else {
6344                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6345         }
6346         intel_encoder->cloneable = 0;
6347         intel_encoder->port = port;
6348
6349         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6350
6351         if (port != PORT_A)
6352                 intel_infoframe_init(intel_dig_port);
6353
6354         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6355                 goto err_init_connector;
6356
6357         return true;
6358
6359 err_init_connector:
6360         drm_encoder_cleanup(encoder);
6361 err_encoder_init:
6362         kfree(intel_connector);
6363 err_connector_alloc:
6364         kfree(intel_dig_port);
6365         return false;
6366 }
6367
6368 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6369 {
6370         struct intel_encoder *encoder;
6371
6372         for_each_intel_encoder(&dev_priv->drm, encoder) {
6373                 struct intel_dp *intel_dp;
6374
6375                 if (encoder->type != INTEL_OUTPUT_DDI)
6376                         continue;
6377
6378                 intel_dp = enc_to_intel_dp(&encoder->base);
6379
6380                 if (!intel_dp->can_mst)
6381                         continue;
6382
6383                 if (intel_dp->is_mst)
6384                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6385         }
6386 }
6387
6388 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6389 {
6390         struct intel_encoder *encoder;
6391
6392         for_each_intel_encoder(&dev_priv->drm, encoder) {
6393                 struct intel_dp *intel_dp;
6394                 int ret;
6395
6396                 if (encoder->type != INTEL_OUTPUT_DDI)
6397                         continue;
6398
6399                 intel_dp = enc_to_intel_dp(&encoder->base);
6400
6401                 if (!intel_dp->can_mst)
6402                         continue;
6403
6404                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
6405                 if (ret)
6406                         intel_dp_check_mst_status(intel_dp);
6407         }
6408 }