2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_RECEIVER_CAP_SIZE 0xf
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
50 static bool is_edp(struct intel_dp *intel_dp)
52 return intel_dp->base.type == INTEL_OUTPUT_EDP;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp *intel_dp)
65 return intel_dp->is_pch_edp;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp *intel_dp)
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
79 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
81 return container_of(intel_attached_encoder(connector),
82 struct intel_dp, base);
86 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
87 * @encoder: DRM encoder
89 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
92 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
94 struct intel_dp *intel_dp;
99 intel_dp = enc_to_intel_dp(encoder);
101 return is_pch_edp(intel_dp);
104 static void intel_dp_link_down(struct intel_dp *intel_dp);
107 intel_edp_link_config(struct intel_encoder *intel_encoder,
108 int *lane_num, int *link_bw)
110 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
112 *lane_num = intel_dp->lane_count;
113 if (intel_dp->link_bw == DP_LINK_BW_1_62)
115 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
120 intel_edp_target_clock(struct intel_encoder *intel_encoder,
121 struct drm_display_mode *mode)
123 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
125 if (intel_dp->panel_fixed_mode)
126 return intel_dp->panel_fixed_mode->clock;
132 intel_dp_max_lane_count(struct intel_dp *intel_dp)
134 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
135 switch (max_lane_count) {
136 case 1: case 2: case 4:
141 return max_lane_count;
145 intel_dp_max_link_bw(struct intel_dp *intel_dp)
147 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
149 switch (max_link_bw) {
150 case DP_LINK_BW_1_62:
154 max_link_bw = DP_LINK_BW_1_62;
161 intel_dp_link_clock(uint8_t link_bw)
163 if (link_bw == DP_LINK_BW_2_7)
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
175 * 270000 * 1 * 8 / 10 == 216000
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
187 intel_dp_link_required(int pixel_clock, int bpp)
189 return (pixel_clock * bpp + 9) / 10;
193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
195 return (max_link_clock * max_lanes * 8) / 10;
199 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
200 struct drm_display_mode *mode,
203 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
204 int max_lanes = intel_dp_max_lane_count(intel_dp);
205 int max_rate, mode_rate;
207 mode_rate = intel_dp_link_required(mode->clock, 24);
208 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
210 if (mode_rate > max_rate) {
211 mode_rate = intel_dp_link_required(mode->clock, 18);
212 if (mode_rate > max_rate)
217 |= INTEL_MODE_DP_FORCE_6BPC;
226 intel_dp_mode_valid(struct drm_connector *connector,
227 struct drm_display_mode *mode)
229 struct intel_dp *intel_dp = intel_attached_dp(connector);
231 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
232 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
235 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
239 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
240 return MODE_CLOCK_HIGH;
242 if (mode->clock < 10000)
243 return MODE_CLOCK_LOW;
245 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
246 return MODE_H_ILLEGAL;
252 pack_aux(uint8_t *src, int src_bytes)
259 for (i = 0; i < src_bytes; i++)
260 v |= ((uint32_t) src[i]) << ((3-i) * 8);
265 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
270 for (i = 0; i < dst_bytes; i++)
271 dst[i] = src >> ((3-i) * 8);
274 /* hrawclock is 1/4 the FSB frequency */
276 intel_hrawclk(struct drm_device *dev)
278 struct drm_i915_private *dev_priv = dev->dev_private;
281 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
282 if (IS_VALLEYVIEW(dev))
285 clkcfg = I915_READ(CLKCFG);
286 switch (clkcfg & CLKCFG_FSB_MASK) {
295 case CLKCFG_FSB_1067:
297 case CLKCFG_FSB_1333:
299 /* these two are just a guess; one of them might be right */
300 case CLKCFG_FSB_1600:
301 case CLKCFG_FSB_1600_ALT:
308 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
310 struct drm_device *dev = intel_dp->base.base.dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
313 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
316 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
318 struct drm_device *dev = intel_dp->base.base.dev;
319 struct drm_i915_private *dev_priv = dev->dev_private;
321 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325 intel_dp_check_edp(struct intel_dp *intel_dp)
327 struct drm_device *dev = intel_dp->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
330 if (!is_edp(intel_dp))
332 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
333 WARN(1, "eDP powered off while attempting aux channel communication.\n");
334 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
335 I915_READ(PCH_PP_STATUS),
336 I915_READ(PCH_PP_CONTROL));
341 intel_dp_aux_ch(struct intel_dp *intel_dp,
342 uint8_t *send, int send_bytes,
343 uint8_t *recv, int recv_size)
345 uint32_t output_reg = intel_dp->output_reg;
346 struct drm_device *dev = intel_dp->base.base.dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 uint32_t ch_ctl = output_reg + 0x10;
349 uint32_t ch_data = ch_ctl + 4;
353 uint32_t aux_clock_divider;
356 if (IS_HASWELL(dev)) {
357 switch (intel_dp->port) {
359 ch_ctl = DPA_AUX_CH_CTL;
360 ch_data = DPA_AUX_CH_DATA1;
363 ch_ctl = PCH_DPB_AUX_CH_CTL;
364 ch_data = PCH_DPB_AUX_CH_DATA1;
367 ch_ctl = PCH_DPC_AUX_CH_CTL;
368 ch_data = PCH_DPC_AUX_CH_DATA1;
371 ch_ctl = PCH_DPD_AUX_CH_CTL;
372 ch_data = PCH_DPD_AUX_CH_DATA1;
379 intel_dp_check_edp(intel_dp);
380 /* The clock divider is based off the hrawclk,
381 * and would like to run at 2MHz. So, take the
382 * hrawclk value and divide by 2 and use that
384 * Note that PCH attached eDP panels should use a 125MHz input
387 if (is_cpu_edp(intel_dp)) {
388 if (IS_VALLEYVIEW(dev))
389 aux_clock_divider = 100;
390 else if (IS_GEN6(dev) || IS_GEN7(dev))
391 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
393 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
394 } else if (HAS_PCH_SPLIT(dev))
395 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
397 aux_clock_divider = intel_hrawclk(dev) / 2;
404 /* Try to wait for any previous AUX channel activity */
405 for (try = 0; try < 3; try++) {
406 status = I915_READ(ch_ctl);
407 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
413 WARN(1, "dp_aux_ch not started status 0x%08x\n",
418 /* Must try at least 3 times according to DP spec */
419 for (try = 0; try < 5; try++) {
420 /* Load the send data into the aux channel data registers */
421 for (i = 0; i < send_bytes; i += 4)
422 I915_WRITE(ch_data + i,
423 pack_aux(send + i, send_bytes - i));
425 /* Send the command and wait for it to complete */
427 DP_AUX_CH_CTL_SEND_BUSY |
428 DP_AUX_CH_CTL_TIME_OUT_400us |
429 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
430 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
431 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
433 DP_AUX_CH_CTL_TIME_OUT_ERROR |
434 DP_AUX_CH_CTL_RECEIVE_ERROR);
436 status = I915_READ(ch_ctl);
437 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
442 /* Clear done status and any errors */
446 DP_AUX_CH_CTL_TIME_OUT_ERROR |
447 DP_AUX_CH_CTL_RECEIVE_ERROR);
449 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
450 DP_AUX_CH_CTL_RECEIVE_ERROR))
452 if (status & DP_AUX_CH_CTL_DONE)
456 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
457 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
461 /* Check for timeout or receive error.
462 * Timeouts occur when the sink is not connected
464 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
465 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
469 /* Timeouts occur when the device isn't connected, so they're
470 * "normal" -- don't fill the kernel log with these */
471 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
472 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
476 /* Unload any bytes sent back from the other side */
477 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
478 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
479 if (recv_bytes > recv_size)
480 recv_bytes = recv_size;
482 for (i = 0; i < recv_bytes; i += 4)
483 unpack_aux(I915_READ(ch_data + i),
484 recv + i, recv_bytes - i);
489 /* Write data to the aux channel in native mode */
491 intel_dp_aux_native_write(struct intel_dp *intel_dp,
492 uint16_t address, uint8_t *send, int send_bytes)
499 intel_dp_check_edp(intel_dp);
502 msg[0] = AUX_NATIVE_WRITE << 4;
503 msg[1] = address >> 8;
504 msg[2] = address & 0xff;
505 msg[3] = send_bytes - 1;
506 memcpy(&msg[4], send, send_bytes);
507 msg_bytes = send_bytes + 4;
509 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
512 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
514 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
522 /* Write a single byte to the aux channel in native mode */
524 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
525 uint16_t address, uint8_t byte)
527 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
530 /* read bytes from a native aux channel */
532 intel_dp_aux_native_read(struct intel_dp *intel_dp,
533 uint16_t address, uint8_t *recv, int recv_bytes)
542 intel_dp_check_edp(intel_dp);
543 msg[0] = AUX_NATIVE_READ << 4;
544 msg[1] = address >> 8;
545 msg[2] = address & 0xff;
546 msg[3] = recv_bytes - 1;
549 reply_bytes = recv_bytes + 1;
552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
559 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
560 memcpy(recv, reply + 1, ret - 1);
563 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
571 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
572 uint8_t write_byte, uint8_t *read_byte)
574 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
575 struct intel_dp *intel_dp = container_of(adapter,
578 uint16_t address = algo_data->address;
586 intel_dp_check_edp(intel_dp);
587 /* Set up the command byte */
588 if (mode & MODE_I2C_READ)
589 msg[0] = AUX_I2C_READ << 4;
591 msg[0] = AUX_I2C_WRITE << 4;
593 if (!(mode & MODE_I2C_STOP))
594 msg[0] |= AUX_I2C_MOT << 4;
596 msg[1] = address >> 8;
617 for (retry = 0; retry < 5; retry++) {
618 ret = intel_dp_aux_ch(intel_dp,
622 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
626 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
627 case AUX_NATIVE_REPLY_ACK:
628 /* I2C-over-AUX Reply field is only valid
629 * when paired with AUX ACK.
632 case AUX_NATIVE_REPLY_NACK:
633 DRM_DEBUG_KMS("aux_ch native nack\n");
635 case AUX_NATIVE_REPLY_DEFER:
639 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
644 switch (reply[0] & AUX_I2C_REPLY_MASK) {
645 case AUX_I2C_REPLY_ACK:
646 if (mode == MODE_I2C_READ) {
647 *read_byte = reply[1];
649 return reply_bytes - 1;
650 case AUX_I2C_REPLY_NACK:
651 DRM_DEBUG_KMS("aux_i2c nack\n");
653 case AUX_I2C_REPLY_DEFER:
654 DRM_DEBUG_KMS("aux_i2c defer\n");
658 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
663 DRM_ERROR("too many retries, giving up\n");
667 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
668 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
671 intel_dp_i2c_init(struct intel_dp *intel_dp,
672 struct intel_connector *intel_connector, const char *name)
676 DRM_DEBUG_KMS("i2c_init %s\n", name);
677 intel_dp->algo.running = false;
678 intel_dp->algo.address = 0;
679 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
681 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
682 intel_dp->adapter.owner = THIS_MODULE;
683 intel_dp->adapter.class = I2C_CLASS_DDC;
684 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
685 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
686 intel_dp->adapter.algo_data = &intel_dp->algo;
687 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
689 ironlake_edp_panel_vdd_on(intel_dp);
690 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
691 ironlake_edp_panel_vdd_off(intel_dp, false);
696 intel_dp_mode_fixup(struct drm_encoder *encoder,
697 const struct drm_display_mode *mode,
698 struct drm_display_mode *adjusted_mode)
700 struct drm_device *dev = encoder->dev;
701 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
702 int lane_count, clock;
703 int max_lane_count = intel_dp_max_lane_count(intel_dp);
704 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
706 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
708 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
709 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
710 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
711 mode, adjusted_mode);
714 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
717 DRM_DEBUG_KMS("DP link computation with max lane count %i "
718 "max bw %02x pixel clock %iKHz\n",
719 max_lane_count, bws[max_clock], adjusted_mode->clock);
721 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
724 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
725 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
727 for (clock = 0; clock <= max_clock; clock++) {
728 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
729 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
731 if (mode_rate <= link_avail) {
732 intel_dp->link_bw = bws[clock];
733 intel_dp->lane_count = lane_count;
734 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
735 DRM_DEBUG_KMS("DP link bw %02x lane "
736 "count %d clock %d bpp %d\n",
737 intel_dp->link_bw, intel_dp->lane_count,
738 adjusted_mode->clock, bpp);
739 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
740 mode_rate, link_avail);
749 struct intel_dp_m_n {
758 intel_reduce_ratio(uint32_t *num, uint32_t *den)
760 while (*num > 0xffffff || *den > 0xffffff) {
767 intel_dp_compute_m_n(int bpp,
771 struct intel_dp_m_n *m_n)
774 m_n->gmch_m = (pixel_clock * bpp) >> 3;
775 m_n->gmch_n = link_clock * nlanes;
776 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
777 m_n->link_m = pixel_clock;
778 m_n->link_n = link_clock;
779 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
783 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
784 struct drm_display_mode *adjusted_mode)
786 struct drm_device *dev = crtc->dev;
787 struct intel_encoder *encoder;
788 struct drm_i915_private *dev_priv = dev->dev_private;
789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
791 struct intel_dp_m_n m_n;
792 int pipe = intel_crtc->pipe;
795 * Find the lane count in the intel_encoder private
797 for_each_encoder_on_crtc(dev, crtc, encoder) {
798 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
800 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
801 intel_dp->base.type == INTEL_OUTPUT_EDP)
803 lane_count = intel_dp->lane_count;
809 * Compute the GMCH and Link ratios. The '3' here is
810 * the number of bytes_per_pixel post-LUT, which we always
811 * set up for 8-bits of R/G/B, or 3 bytes total.
813 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
814 mode->clock, adjusted_mode->clock, &m_n);
816 if (IS_HASWELL(dev)) {
817 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
818 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
819 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
820 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
821 } else if (HAS_PCH_SPLIT(dev)) {
822 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
823 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
824 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
825 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
826 } else if (IS_VALLEYVIEW(dev)) {
827 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
828 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
829 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
830 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
832 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
833 TU_SIZE(m_n.tu) | m_n.gmch_m);
834 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
835 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
836 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
840 void intel_dp_init_link_config(struct intel_dp *intel_dp)
842 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
843 intel_dp->link_configuration[0] = intel_dp->link_bw;
844 intel_dp->link_configuration[1] = intel_dp->lane_count;
845 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
847 * Check for DPCD version > 1.1 and enhanced framing support
849 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
850 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
851 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
856 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
857 struct drm_display_mode *adjusted_mode)
859 struct drm_device *dev = encoder->dev;
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
862 struct drm_crtc *crtc = intel_dp->base.base.crtc;
863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
866 * There are four kinds of DP registers:
873 * IBX PCH and CPU are the same for almost everything,
874 * except that the CPU DP PLL is configured in this
877 * CPT PCH is quite different, having many bits moved
878 * to the TRANS_DP_CTL register instead. That
879 * configuration happens (oddly) in ironlake_pch_enable
882 /* Preserve the BIOS-computed detected bit. This is
883 * supposed to be read-only.
885 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
887 /* Handle DP bits in common between all three register formats */
888 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
890 switch (intel_dp->lane_count) {
892 intel_dp->DP |= DP_PORT_WIDTH_1;
895 intel_dp->DP |= DP_PORT_WIDTH_2;
898 intel_dp->DP |= DP_PORT_WIDTH_4;
901 if (intel_dp->has_audio) {
902 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
903 pipe_name(intel_crtc->pipe));
904 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
905 intel_write_eld(encoder, adjusted_mode);
908 intel_dp_init_link_config(intel_dp);
910 /* Split out the IBX/CPU vs CPT settings */
912 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
913 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
914 intel_dp->DP |= DP_SYNC_HS_HIGH;
915 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
916 intel_dp->DP |= DP_SYNC_VS_HIGH;
917 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
919 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
920 intel_dp->DP |= DP_ENHANCED_FRAMING;
922 intel_dp->DP |= intel_crtc->pipe << 29;
924 /* don't miss out required setting for eDP */
925 if (adjusted_mode->clock < 200000)
926 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
928 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
929 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
930 intel_dp->DP |= intel_dp->color_range;
932 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
933 intel_dp->DP |= DP_SYNC_HS_HIGH;
934 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
935 intel_dp->DP |= DP_SYNC_VS_HIGH;
936 intel_dp->DP |= DP_LINK_TRAIN_OFF;
938 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
939 intel_dp->DP |= DP_ENHANCED_FRAMING;
941 if (intel_crtc->pipe == 1)
942 intel_dp->DP |= DP_PIPEB_SELECT;
944 if (is_cpu_edp(intel_dp)) {
945 /* don't miss out required setting for eDP */
946 if (adjusted_mode->clock < 200000)
947 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
949 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
952 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
956 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
957 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
959 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
960 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
962 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
963 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
965 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
969 struct drm_device *dev = intel_dp->base.base.dev;
970 struct drm_i915_private *dev_priv = dev->dev_private;
972 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
974 I915_READ(PCH_PP_STATUS),
975 I915_READ(PCH_PP_CONTROL));
977 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
978 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
979 I915_READ(PCH_PP_STATUS),
980 I915_READ(PCH_PP_CONTROL));
984 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
986 DRM_DEBUG_KMS("Wait for panel power on\n");
987 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
990 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
992 DRM_DEBUG_KMS("Wait for panel power off time\n");
993 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
996 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
998 DRM_DEBUG_KMS("Wait for panel power cycle\n");
999 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1003 /* Read the current pp_control value, unlocking the register if it
1007 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1009 u32 control = I915_READ(PCH_PP_CONTROL);
1011 control &= ~PANEL_UNLOCK_MASK;
1012 control |= PANEL_UNLOCK_REGS;
1016 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1018 struct drm_device *dev = intel_dp->base.base.dev;
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1022 if (!is_edp(intel_dp))
1024 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1026 WARN(intel_dp->want_panel_vdd,
1027 "eDP VDD already requested on\n");
1029 intel_dp->want_panel_vdd = true;
1031 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1032 DRM_DEBUG_KMS("eDP VDD already on\n");
1036 if (!ironlake_edp_have_panel_power(intel_dp))
1037 ironlake_wait_panel_power_cycle(intel_dp);
1039 pp = ironlake_get_pp_control(dev_priv);
1040 pp |= EDP_FORCE_VDD;
1041 I915_WRITE(PCH_PP_CONTROL, pp);
1042 POSTING_READ(PCH_PP_CONTROL);
1043 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1044 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1047 * If the panel wasn't on, delay before accessing aux channel
1049 if (!ironlake_edp_have_panel_power(intel_dp)) {
1050 DRM_DEBUG_KMS("eDP was not running\n");
1051 msleep(intel_dp->panel_power_up_delay);
1055 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1057 struct drm_device *dev = intel_dp->base.base.dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1061 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1062 pp = ironlake_get_pp_control(dev_priv);
1063 pp &= ~EDP_FORCE_VDD;
1064 I915_WRITE(PCH_PP_CONTROL, pp);
1065 POSTING_READ(PCH_PP_CONTROL);
1067 /* Make sure sequencer is idle before allowing subsequent activity */
1068 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1069 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1071 msleep(intel_dp->panel_power_down_delay);
1075 static void ironlake_panel_vdd_work(struct work_struct *__work)
1077 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1078 struct intel_dp, panel_vdd_work);
1079 struct drm_device *dev = intel_dp->base.base.dev;
1081 mutex_lock(&dev->mode_config.mutex);
1082 ironlake_panel_vdd_off_sync(intel_dp);
1083 mutex_unlock(&dev->mode_config.mutex);
1086 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1088 if (!is_edp(intel_dp))
1091 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1092 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1094 intel_dp->want_panel_vdd = false;
1097 ironlake_panel_vdd_off_sync(intel_dp);
1100 * Queue the timer to fire a long
1101 * time from now (relative to the power down delay)
1102 * to keep the panel power up across a sequence of operations
1104 schedule_delayed_work(&intel_dp->panel_vdd_work,
1105 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1109 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1111 struct drm_device *dev = intel_dp->base.base.dev;
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1115 if (!is_edp(intel_dp))
1118 DRM_DEBUG_KMS("Turn eDP power on\n");
1120 if (ironlake_edp_have_panel_power(intel_dp)) {
1121 DRM_DEBUG_KMS("eDP power already on\n");
1125 ironlake_wait_panel_power_cycle(intel_dp);
1127 pp = ironlake_get_pp_control(dev_priv);
1129 /* ILK workaround: disable reset around power sequence */
1130 pp &= ~PANEL_POWER_RESET;
1131 I915_WRITE(PCH_PP_CONTROL, pp);
1132 POSTING_READ(PCH_PP_CONTROL);
1135 pp |= POWER_TARGET_ON;
1137 pp |= PANEL_POWER_RESET;
1139 I915_WRITE(PCH_PP_CONTROL, pp);
1140 POSTING_READ(PCH_PP_CONTROL);
1142 ironlake_wait_panel_on(intel_dp);
1145 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1146 I915_WRITE(PCH_PP_CONTROL, pp);
1147 POSTING_READ(PCH_PP_CONTROL);
1151 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1153 struct drm_device *dev = intel_dp->base.base.dev;
1154 struct drm_i915_private *dev_priv = dev->dev_private;
1157 if (!is_edp(intel_dp))
1160 DRM_DEBUG_KMS("Turn eDP power off\n");
1162 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1164 pp = ironlake_get_pp_control(dev_priv);
1165 /* We need to switch off panel power _and_ force vdd, for otherwise some
1166 * panels get very unhappy and cease to work. */
1167 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1168 I915_WRITE(PCH_PP_CONTROL, pp);
1169 POSTING_READ(PCH_PP_CONTROL);
1171 intel_dp->want_panel_vdd = false;
1173 ironlake_wait_panel_off(intel_dp);
1176 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1178 struct drm_device *dev = intel_dp->base.base.dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1182 if (!is_edp(intel_dp))
1185 DRM_DEBUG_KMS("\n");
1187 * If we enable the backlight right away following a panel power
1188 * on, we may see slight flicker as the panel syncs with the eDP
1189 * link. So delay a bit to make sure the image is solid before
1190 * allowing it to appear.
1192 msleep(intel_dp->backlight_on_delay);
1193 pp = ironlake_get_pp_control(dev_priv);
1194 pp |= EDP_BLC_ENABLE;
1195 I915_WRITE(PCH_PP_CONTROL, pp);
1196 POSTING_READ(PCH_PP_CONTROL);
1199 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1201 struct drm_device *dev = intel_dp->base.base.dev;
1202 struct drm_i915_private *dev_priv = dev->dev_private;
1205 if (!is_edp(intel_dp))
1208 DRM_DEBUG_KMS("\n");
1209 pp = ironlake_get_pp_control(dev_priv);
1210 pp &= ~EDP_BLC_ENABLE;
1211 I915_WRITE(PCH_PP_CONTROL, pp);
1212 POSTING_READ(PCH_PP_CONTROL);
1213 msleep(intel_dp->backlight_off_delay);
1216 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1218 struct drm_device *dev = intel_dp->base.base.dev;
1219 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1223 assert_pipe_disabled(dev_priv,
1224 to_intel_crtc(crtc)->pipe);
1226 DRM_DEBUG_KMS("\n");
1227 dpa_ctl = I915_READ(DP_A);
1228 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1229 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1231 /* We don't adjust intel_dp->DP while tearing down the link, to
1232 * facilitate link retraining (e.g. after hotplug). Hence clear all
1233 * enable bits here to ensure that we don't enable too much. */
1234 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1235 intel_dp->DP |= DP_PLL_ENABLE;
1236 I915_WRITE(DP_A, intel_dp->DP);
1241 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1243 struct drm_device *dev = intel_dp->base.base.dev;
1244 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1248 assert_pipe_disabled(dev_priv,
1249 to_intel_crtc(crtc)->pipe);
1251 dpa_ctl = I915_READ(DP_A);
1252 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1253 "dp pll off, should be on\n");
1254 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1256 /* We can't rely on the value tracked for the DP register in
1257 * intel_dp->DP because link_down must not change that (otherwise link
1258 * re-training will fail. */
1259 dpa_ctl &= ~DP_PLL_ENABLE;
1260 I915_WRITE(DP_A, dpa_ctl);
1265 /* If the sink supports it, try to set the power state appropriately */
1266 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1270 /* Should have a valid DPCD by this point */
1271 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1274 if (mode != DRM_MODE_DPMS_ON) {
1275 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1278 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1281 * When turning on, we need to retry for 1ms to give the sink
1284 for (i = 0; i < 3; i++) {
1285 ret = intel_dp_aux_native_write_1(intel_dp,
1295 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1298 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1299 struct drm_device *dev = encoder->base.dev;
1300 struct drm_i915_private *dev_priv = dev->dev_private;
1301 u32 tmp = I915_READ(intel_dp->output_reg);
1303 if (!(tmp & DP_PORT_EN))
1306 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1307 *pipe = PORT_TO_PIPE_CPT(tmp);
1308 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1309 *pipe = PORT_TO_PIPE(tmp);
1315 switch (intel_dp->output_reg) {
1317 trans_sel = TRANS_DP_PORT_SEL_B;
1320 trans_sel = TRANS_DP_PORT_SEL_C;
1323 trans_sel = TRANS_DP_PORT_SEL_D;
1330 trans_dp = I915_READ(TRANS_DP_CTL(i));
1331 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1338 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1343 static void intel_disable_dp(struct intel_encoder *encoder)
1345 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1347 /* Make sure the panel is off before trying to change the mode. But also
1348 * ensure that we have vdd while we switch off the panel. */
1349 ironlake_edp_panel_vdd_on(intel_dp);
1350 ironlake_edp_backlight_off(intel_dp);
1351 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1352 ironlake_edp_panel_off(intel_dp);
1354 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1355 if (!is_cpu_edp(intel_dp))
1356 intel_dp_link_down(intel_dp);
1359 static void intel_post_disable_dp(struct intel_encoder *encoder)
1361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1363 if (is_cpu_edp(intel_dp)) {
1364 intel_dp_link_down(intel_dp);
1365 ironlake_edp_pll_off(intel_dp);
1369 static void intel_enable_dp(struct intel_encoder *encoder)
1371 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1372 struct drm_device *dev = encoder->base.dev;
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1376 if (WARN_ON(dp_reg & DP_PORT_EN))
1379 ironlake_edp_panel_vdd_on(intel_dp);
1380 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1381 intel_dp_start_link_train(intel_dp);
1382 ironlake_edp_panel_on(intel_dp);
1383 ironlake_edp_panel_vdd_off(intel_dp, true);
1384 intel_dp_complete_link_train(intel_dp);
1385 ironlake_edp_backlight_on(intel_dp);
1388 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1390 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1392 if (is_cpu_edp(intel_dp))
1393 ironlake_edp_pll_on(intel_dp);
1397 * Native read with retry for link status and receiver capability reads for
1398 * cases where the sink may still be asleep.
1401 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1402 uint8_t *recv, int recv_bytes)
1407 * Sinks are *supposed* to come up within 1ms from an off state,
1408 * but we're also supposed to retry 3 times per the spec.
1410 for (i = 0; i < 3; i++) {
1411 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1413 if (ret == recv_bytes)
1422 * Fetch AUX CH registers 0x202 - 0x207 which contain
1423 * link status information
1426 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1428 return intel_dp_aux_native_read_retry(intel_dp,
1431 DP_LINK_STATUS_SIZE);
1435 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1438 return link_status[r - DP_LANE0_1_STATUS];
1442 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1445 int s = ((lane & 1) ?
1446 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1447 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1448 uint8_t l = adjust_request[lane>>1];
1450 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1454 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1457 int s = ((lane & 1) ?
1458 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1459 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1460 uint8_t l = adjust_request[lane>>1];
1462 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1467 static char *voltage_names[] = {
1468 "0.4V", "0.6V", "0.8V", "1.2V"
1470 static char *pre_emph_names[] = {
1471 "0dB", "3.5dB", "6dB", "9.5dB"
1473 static char *link_train_names[] = {
1474 "pattern 1", "pattern 2", "idle", "off"
1479 * These are source-specific values; current Intel hardware supports
1480 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1484 intel_dp_voltage_max(struct intel_dp *intel_dp)
1486 struct drm_device *dev = intel_dp->base.base.dev;
1488 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1489 return DP_TRAIN_VOLTAGE_SWING_800;
1490 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1491 return DP_TRAIN_VOLTAGE_SWING_1200;
1493 return DP_TRAIN_VOLTAGE_SWING_800;
1497 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1499 struct drm_device *dev = intel_dp->base.base.dev;
1501 if (IS_HASWELL(dev)) {
1502 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1503 case DP_TRAIN_VOLTAGE_SWING_400:
1504 return DP_TRAIN_PRE_EMPHASIS_9_5;
1505 case DP_TRAIN_VOLTAGE_SWING_600:
1506 return DP_TRAIN_PRE_EMPHASIS_6;
1507 case DP_TRAIN_VOLTAGE_SWING_800:
1508 return DP_TRAIN_PRE_EMPHASIS_3_5;
1509 case DP_TRAIN_VOLTAGE_SWING_1200:
1511 return DP_TRAIN_PRE_EMPHASIS_0;
1513 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1514 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1515 case DP_TRAIN_VOLTAGE_SWING_400:
1516 return DP_TRAIN_PRE_EMPHASIS_6;
1517 case DP_TRAIN_VOLTAGE_SWING_600:
1518 case DP_TRAIN_VOLTAGE_SWING_800:
1519 return DP_TRAIN_PRE_EMPHASIS_3_5;
1521 return DP_TRAIN_PRE_EMPHASIS_0;
1524 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1525 case DP_TRAIN_VOLTAGE_SWING_400:
1526 return DP_TRAIN_PRE_EMPHASIS_6;
1527 case DP_TRAIN_VOLTAGE_SWING_600:
1528 return DP_TRAIN_PRE_EMPHASIS_6;
1529 case DP_TRAIN_VOLTAGE_SWING_800:
1530 return DP_TRAIN_PRE_EMPHASIS_3_5;
1531 case DP_TRAIN_VOLTAGE_SWING_1200:
1533 return DP_TRAIN_PRE_EMPHASIS_0;
1539 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1544 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1545 uint8_t voltage_max;
1546 uint8_t preemph_max;
1548 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1549 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1550 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1558 voltage_max = intel_dp_voltage_max(intel_dp);
1559 if (v >= voltage_max)
1560 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1562 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1563 if (p >= preemph_max)
1564 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1566 for (lane = 0; lane < 4; lane++)
1567 intel_dp->train_set[lane] = v | p;
1571 intel_dp_signal_levels(uint8_t train_set)
1573 uint32_t signal_levels = 0;
1575 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576 case DP_TRAIN_VOLTAGE_SWING_400:
1578 signal_levels |= DP_VOLTAGE_0_4;
1580 case DP_TRAIN_VOLTAGE_SWING_600:
1581 signal_levels |= DP_VOLTAGE_0_6;
1583 case DP_TRAIN_VOLTAGE_SWING_800:
1584 signal_levels |= DP_VOLTAGE_0_8;
1586 case DP_TRAIN_VOLTAGE_SWING_1200:
1587 signal_levels |= DP_VOLTAGE_1_2;
1590 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1591 case DP_TRAIN_PRE_EMPHASIS_0:
1593 signal_levels |= DP_PRE_EMPHASIS_0;
1595 case DP_TRAIN_PRE_EMPHASIS_3_5:
1596 signal_levels |= DP_PRE_EMPHASIS_3_5;
1598 case DP_TRAIN_PRE_EMPHASIS_6:
1599 signal_levels |= DP_PRE_EMPHASIS_6;
1601 case DP_TRAIN_PRE_EMPHASIS_9_5:
1602 signal_levels |= DP_PRE_EMPHASIS_9_5;
1605 return signal_levels;
1608 /* Gen6's DP voltage swing and pre-emphasis control */
1610 intel_gen6_edp_signal_levels(uint8_t train_set)
1612 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1613 DP_TRAIN_PRE_EMPHASIS_MASK);
1614 switch (signal_levels) {
1615 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1616 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1617 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1618 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1619 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1620 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1621 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1622 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1623 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1624 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1625 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1626 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1627 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1628 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1630 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1631 "0x%x\n", signal_levels);
1632 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1636 /* Gen7's DP voltage swing and pre-emphasis control */
1638 intel_gen7_edp_signal_levels(uint8_t train_set)
1640 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1641 DP_TRAIN_PRE_EMPHASIS_MASK);
1642 switch (signal_levels) {
1643 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1644 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1645 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1646 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1647 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1648 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1650 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1651 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1652 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1653 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1655 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1656 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1657 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1658 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1661 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1662 "0x%x\n", signal_levels);
1663 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1667 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1669 intel_dp_signal_levels_hsw(uint8_t train_set)
1671 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1672 DP_TRAIN_PRE_EMPHASIS_MASK);
1673 switch (signal_levels) {
1674 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1675 return DDI_BUF_EMP_400MV_0DB_HSW;
1676 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1678 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1679 return DDI_BUF_EMP_400MV_6DB_HSW;
1680 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1681 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1683 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1684 return DDI_BUF_EMP_600MV_0DB_HSW;
1685 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1686 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1687 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1688 return DDI_BUF_EMP_600MV_6DB_HSW;
1690 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1691 return DDI_BUF_EMP_800MV_0DB_HSW;
1692 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1693 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1695 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1696 "0x%x\n", signal_levels);
1697 return DDI_BUF_EMP_400MV_0DB_HSW;
1702 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1705 int s = (lane & 1) * 4;
1706 uint8_t l = link_status[lane>>1];
1708 return (l >> s) & 0xf;
1711 /* Check for clock recovery is done on all channels */
1713 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1716 uint8_t lane_status;
1718 for (lane = 0; lane < lane_count; lane++) {
1719 lane_status = intel_get_lane_status(link_status, lane);
1720 if ((lane_status & DP_LANE_CR_DONE) == 0)
1726 /* Check to see if channel eq is done on all channels */
1727 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1728 DP_LANE_CHANNEL_EQ_DONE|\
1729 DP_LANE_SYMBOL_LOCKED)
1731 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1734 uint8_t lane_status;
1737 lane_align = intel_dp_link_status(link_status,
1738 DP_LANE_ALIGN_STATUS_UPDATED);
1739 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1741 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1742 lane_status = intel_get_lane_status(link_status, lane);
1743 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1750 intel_dp_set_link_train(struct intel_dp *intel_dp,
1751 uint32_t dp_reg_value,
1752 uint8_t dp_train_pat)
1754 struct drm_device *dev = intel_dp->base.base.dev;
1755 struct drm_i915_private *dev_priv = dev->dev_private;
1759 if (IS_HASWELL(dev)) {
1760 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1762 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1763 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1765 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1767 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1768 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1769 case DP_TRAINING_PATTERN_DISABLE:
1770 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1771 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1773 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1774 DP_TP_STATUS_IDLE_DONE), 1))
1775 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1777 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1778 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1781 case DP_TRAINING_PATTERN_1:
1782 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1784 case DP_TRAINING_PATTERN_2:
1785 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1787 case DP_TRAINING_PATTERN_3:
1788 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1791 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1793 } else if (HAS_PCH_CPT(dev) &&
1794 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1795 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1797 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1798 case DP_TRAINING_PATTERN_DISABLE:
1799 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1801 case DP_TRAINING_PATTERN_1:
1802 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1804 case DP_TRAINING_PATTERN_2:
1805 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1807 case DP_TRAINING_PATTERN_3:
1808 DRM_ERROR("DP training pattern 3 not supported\n");
1809 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1814 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1816 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1817 case DP_TRAINING_PATTERN_DISABLE:
1818 dp_reg_value |= DP_LINK_TRAIN_OFF;
1820 case DP_TRAINING_PATTERN_1:
1821 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1823 case DP_TRAINING_PATTERN_2:
1824 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1826 case DP_TRAINING_PATTERN_3:
1827 DRM_ERROR("DP training pattern 3 not supported\n");
1828 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1833 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1834 POSTING_READ(intel_dp->output_reg);
1836 intel_dp_aux_native_write_1(intel_dp,
1837 DP_TRAINING_PATTERN_SET,
1840 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1841 DP_TRAINING_PATTERN_DISABLE) {
1842 ret = intel_dp_aux_native_write(intel_dp,
1843 DP_TRAINING_LANE0_SET,
1844 intel_dp->train_set,
1845 intel_dp->lane_count);
1846 if (ret != intel_dp->lane_count)
1853 /* Enable corresponding port and start training pattern 1 */
1855 intel_dp_start_link_train(struct intel_dp *intel_dp)
1857 struct drm_encoder *encoder = &intel_dp->base.base;
1858 struct drm_device *dev = encoder->dev;
1861 bool clock_recovery = false;
1862 int voltage_tries, loop_tries;
1863 uint32_t DP = intel_dp->DP;
1865 if (IS_HASWELL(dev))
1866 intel_ddi_prepare_link_retrain(encoder);
1868 /* Write the link configuration data */
1869 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1870 intel_dp->link_configuration,
1871 DP_LINK_CONFIGURATION_SIZE);
1875 memset(intel_dp->train_set, 0, 4);
1879 clock_recovery = false;
1881 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1882 uint8_t link_status[DP_LINK_STATUS_SIZE];
1883 uint32_t signal_levels;
1885 if (IS_HASWELL(dev)) {
1886 signal_levels = intel_dp_signal_levels_hsw(
1887 intel_dp->train_set[0]);
1888 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1889 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1890 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1891 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1892 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1893 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1894 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1896 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1897 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1899 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1902 if (!intel_dp_set_link_train(intel_dp, DP,
1903 DP_TRAINING_PATTERN_1 |
1904 DP_LINK_SCRAMBLING_DISABLE))
1906 /* Set training pattern 1 */
1909 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1910 DRM_ERROR("failed to get link status\n");
1914 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1915 DRM_DEBUG_KMS("clock recovery OK\n");
1916 clock_recovery = true;
1920 /* Check to see if we've tried the max voltage */
1921 for (i = 0; i < intel_dp->lane_count; i++)
1922 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1924 if (i == intel_dp->lane_count && voltage_tries == 5) {
1925 if (++loop_tries == 5) {
1926 DRM_DEBUG_KMS("too many full retries, give up\n");
1929 memset(intel_dp->train_set, 0, 4);
1934 /* Check to see if we've tried the same voltage 5 times */
1935 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1936 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1941 /* Compute new intel_dp->train_set as requested by target */
1942 intel_get_adjust_train(intel_dp, link_status);
1949 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1951 struct drm_device *dev = intel_dp->base.base.dev;
1952 bool channel_eq = false;
1953 int tries, cr_tries;
1954 uint32_t DP = intel_dp->DP;
1956 /* channel equalization */
1961 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1962 uint32_t signal_levels;
1963 uint8_t link_status[DP_LINK_STATUS_SIZE];
1966 DRM_ERROR("failed to train DP, aborting\n");
1967 intel_dp_link_down(intel_dp);
1971 if (IS_HASWELL(dev)) {
1972 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1973 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1974 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1975 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1976 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1977 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1978 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1979 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1981 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1982 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1985 /* channel eq pattern */
1986 if (!intel_dp_set_link_train(intel_dp, DP,
1987 DP_TRAINING_PATTERN_2 |
1988 DP_LINK_SCRAMBLING_DISABLE))
1992 if (!intel_dp_get_link_status(intel_dp, link_status))
1995 /* Make sure clock is still ok */
1996 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1997 intel_dp_start_link_train(intel_dp);
2002 if (intel_channel_eq_ok(intel_dp, link_status)) {
2007 /* Try 5 times, then try clock recovery if that fails */
2009 intel_dp_link_down(intel_dp);
2010 intel_dp_start_link_train(intel_dp);
2016 /* Compute new intel_dp->train_set as requested by target */
2017 intel_get_adjust_train(intel_dp, link_status);
2022 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2024 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2028 intel_dp_link_down(struct intel_dp *intel_dp)
2030 struct drm_device *dev = intel_dp->base.base.dev;
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 uint32_t DP = intel_dp->DP;
2035 * DDI code has a strict mode set sequence and we should try to respect
2036 * it, otherwise we might hang the machine in many different ways. So we
2037 * really should be disabling the port only on a complete crtc_disable
2038 * sequence. This function is just called under two conditions on DDI
2040 * - Link train failed while doing crtc_enable, and on this case we
2041 * really should respect the mode set sequence and wait for a
2043 * - Someone turned the monitor off and intel_dp_check_link_status
2044 * called us. We don't need to disable the whole port on this case, so
2045 * when someone turns the monitor on again,
2046 * intel_ddi_prepare_link_retrain will take care of redoing the link
2049 if (IS_HASWELL(dev))
2052 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2055 DRM_DEBUG_KMS("\n");
2057 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2058 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2059 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2061 DP &= ~DP_LINK_TRAIN_MASK;
2062 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2064 POSTING_READ(intel_dp->output_reg);
2068 if (HAS_PCH_IBX(dev) &&
2069 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2070 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2072 /* Hardware workaround: leaving our transcoder select
2073 * set to transcoder B while it's off will prevent the
2074 * corresponding HDMI output on transcoder A.
2076 * Combine this with another hardware workaround:
2077 * transcoder select bit can only be cleared while the
2080 DP &= ~DP_PIPEB_SELECT;
2081 I915_WRITE(intel_dp->output_reg, DP);
2083 /* Changes to enable or select take place the vblank
2084 * after being written.
2087 /* We can arrive here never having been attached
2088 * to a CRTC, for instance, due to inheriting
2089 * random state from the BIOS.
2091 * If the pipe is not running, play safe and
2092 * wait for the clocks to stabilise before
2095 POSTING_READ(intel_dp->output_reg);
2098 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2101 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2102 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2103 POSTING_READ(intel_dp->output_reg);
2104 msleep(intel_dp->panel_power_down_delay);
2108 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2110 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2111 sizeof(intel_dp->dpcd)) == 0)
2112 return false; /* aux transfer failed */
2114 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2115 return false; /* DPCD not present */
2117 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2118 DP_DWN_STRM_PORT_PRESENT))
2119 return true; /* native DP sink */
2121 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2122 return true; /* no per-port downstream info */
2124 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2125 intel_dp->downstream_ports,
2126 DP_MAX_DOWNSTREAM_PORTS) == 0)
2127 return false; /* downstream port status fetch failed */
2133 intel_dp_probe_oui(struct intel_dp *intel_dp)
2137 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2140 ironlake_edp_panel_vdd_on(intel_dp);
2142 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2143 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2144 buf[0], buf[1], buf[2]);
2146 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2147 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2148 buf[0], buf[1], buf[2]);
2150 ironlake_edp_panel_vdd_off(intel_dp, false);
2154 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2158 ret = intel_dp_aux_native_read_retry(intel_dp,
2159 DP_DEVICE_SERVICE_IRQ_VECTOR,
2160 sink_irq_vector, 1);
2168 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2170 /* NAK by default */
2171 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2175 * According to DP spec
2178 * 2. Configure link according to Receiver Capabilities
2179 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2180 * 4. Check link status on receipt of hot-plug interrupt
2184 intel_dp_check_link_status(struct intel_dp *intel_dp)
2187 u8 link_status[DP_LINK_STATUS_SIZE];
2189 if (!intel_dp->base.connectors_active)
2192 if (WARN_ON(!intel_dp->base.base.crtc))
2195 /* Try to read receiver status if the link appears to be up */
2196 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2197 intel_dp_link_down(intel_dp);
2201 /* Now read the DPCD to see if it's actually running */
2202 if (!intel_dp_get_dpcd(intel_dp)) {
2203 intel_dp_link_down(intel_dp);
2207 /* Try to read the source of the interrupt */
2208 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2209 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2210 /* Clear interrupt source */
2211 intel_dp_aux_native_write_1(intel_dp,
2212 DP_DEVICE_SERVICE_IRQ_VECTOR,
2215 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2216 intel_dp_handle_test_request(intel_dp);
2217 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2218 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2221 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2222 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2223 drm_get_encoder_name(&intel_dp->base.base));
2224 intel_dp_start_link_train(intel_dp);
2225 intel_dp_complete_link_train(intel_dp);
2229 /* XXX this is probably wrong for multiple downstream ports */
2230 static enum drm_connector_status
2231 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2233 uint8_t *dpcd = intel_dp->dpcd;
2237 if (!intel_dp_get_dpcd(intel_dp))
2238 return connector_status_disconnected;
2240 /* if there's no downstream port, we're done */
2241 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2242 return connector_status_connected;
2244 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2245 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2248 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2250 return connector_status_unknown;
2251 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2252 : connector_status_disconnected;
2255 /* If no HPD, poke DDC gently */
2256 if (drm_probe_ddc(&intel_dp->adapter))
2257 return connector_status_connected;
2259 /* Well we tried, say unknown for unreliable port types */
2260 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2261 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2262 return connector_status_unknown;
2264 /* Anything else is out of spec, warn and ignore */
2265 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2266 return connector_status_disconnected;
2269 static enum drm_connector_status
2270 ironlake_dp_detect(struct intel_dp *intel_dp)
2272 enum drm_connector_status status;
2274 /* Can't disconnect eDP, but you can close the lid... */
2275 if (is_edp(intel_dp)) {
2276 status = intel_panel_detect(intel_dp->base.base.dev);
2277 if (status == connector_status_unknown)
2278 status = connector_status_connected;
2282 return intel_dp_detect_dpcd(intel_dp);
2285 static enum drm_connector_status
2286 g4x_dp_detect(struct intel_dp *intel_dp)
2288 struct drm_device *dev = intel_dp->base.base.dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2292 switch (intel_dp->output_reg) {
2294 bit = DPB_HOTPLUG_LIVE_STATUS;
2297 bit = DPC_HOTPLUG_LIVE_STATUS;
2300 bit = DPD_HOTPLUG_LIVE_STATUS;
2303 return connector_status_unknown;
2306 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2307 return connector_status_disconnected;
2309 return intel_dp_detect_dpcd(intel_dp);
2312 static struct edid *
2313 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2315 struct intel_dp *intel_dp = intel_attached_dp(connector);
2319 if (is_edp(intel_dp)) {
2320 if (!intel_dp->edid)
2323 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2324 edid = kmalloc(size, GFP_KERNEL);
2328 memcpy(edid, intel_dp->edid, size);
2332 edid = drm_get_edid(connector, adapter);
2337 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2339 struct intel_dp *intel_dp = intel_attached_dp(connector);
2342 if (is_edp(intel_dp)) {
2343 drm_mode_connector_update_edid_property(connector,
2345 ret = drm_add_edid_modes(connector, intel_dp->edid);
2346 drm_edid_to_eld(connector,
2348 return intel_dp->edid_mode_count;
2351 ret = intel_ddc_get_modes(connector, adapter);
2357 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2359 * \return true if DP port is connected.
2360 * \return false if DP port is disconnected.
2362 static enum drm_connector_status
2363 intel_dp_detect(struct drm_connector *connector, bool force)
2365 struct intel_dp *intel_dp = intel_attached_dp(connector);
2366 struct drm_device *dev = intel_dp->base.base.dev;
2367 enum drm_connector_status status;
2368 struct edid *edid = NULL;
2370 intel_dp->has_audio = false;
2372 if (HAS_PCH_SPLIT(dev))
2373 status = ironlake_dp_detect(intel_dp);
2375 status = g4x_dp_detect(intel_dp);
2377 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2378 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2379 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2380 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2382 if (status != connector_status_connected)
2385 intel_dp_probe_oui(intel_dp);
2387 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2388 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2390 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2392 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2397 return connector_status_connected;
2400 static int intel_dp_get_modes(struct drm_connector *connector)
2402 struct intel_dp *intel_dp = intel_attached_dp(connector);
2403 struct drm_device *dev = intel_dp->base.base.dev;
2406 /* We should parse the EDID data and find out if it has an audio sink
2409 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2413 /* if eDP has no EDID, fall back to fixed mode */
2414 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
2415 struct drm_display_mode *mode;
2416 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2418 drm_mode_probed_add(connector, mode);
2426 intel_dp_detect_audio(struct drm_connector *connector)
2428 struct intel_dp *intel_dp = intel_attached_dp(connector);
2430 bool has_audio = false;
2432 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2434 has_audio = drm_detect_monitor_audio(edid);
2442 intel_dp_set_property(struct drm_connector *connector,
2443 struct drm_property *property,
2446 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2447 struct intel_dp *intel_dp = intel_attached_dp(connector);
2450 ret = drm_connector_property_set_value(connector, property, val);
2454 if (property == dev_priv->force_audio_property) {
2458 if (i == intel_dp->force_audio)
2461 intel_dp->force_audio = i;
2463 if (i == HDMI_AUDIO_AUTO)
2464 has_audio = intel_dp_detect_audio(connector);
2466 has_audio = (i == HDMI_AUDIO_ON);
2468 if (has_audio == intel_dp->has_audio)
2471 intel_dp->has_audio = has_audio;
2475 if (property == dev_priv->broadcast_rgb_property) {
2476 if (val == !!intel_dp->color_range)
2479 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2486 if (intel_dp->base.base.crtc) {
2487 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2488 intel_set_mode(crtc, &crtc->mode,
2489 crtc->x, crtc->y, crtc->fb);
2496 intel_dp_destroy(struct drm_connector *connector)
2498 struct drm_device *dev = connector->dev;
2499 struct intel_dp *intel_dp = intel_attached_dp(connector);
2501 if (is_edp(intel_dp))
2502 intel_panel_destroy_backlight(dev);
2504 drm_sysfs_connector_remove(connector);
2505 drm_connector_cleanup(connector);
2509 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2511 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2513 i2c_del_adapter(&intel_dp->adapter);
2514 drm_encoder_cleanup(encoder);
2515 if (is_edp(intel_dp)) {
2516 kfree(intel_dp->edid);
2517 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2518 ironlake_panel_vdd_off_sync(intel_dp);
2523 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2524 .mode_fixup = intel_dp_mode_fixup,
2525 .mode_set = intel_dp_mode_set,
2526 .disable = intel_encoder_noop,
2529 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2530 .mode_fixup = intel_dp_mode_fixup,
2531 .mode_set = intel_ddi_mode_set,
2532 .disable = intel_encoder_noop,
2535 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2536 .dpms = intel_connector_dpms,
2537 .detect = intel_dp_detect,
2538 .fill_modes = drm_helper_probe_single_connector_modes,
2539 .set_property = intel_dp_set_property,
2540 .destroy = intel_dp_destroy,
2543 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2544 .get_modes = intel_dp_get_modes,
2545 .mode_valid = intel_dp_mode_valid,
2546 .best_encoder = intel_best_encoder,
2549 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2550 .destroy = intel_dp_encoder_destroy,
2554 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2556 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2558 intel_dp_check_link_status(intel_dp);
2561 /* Return which DP Port should be selected for Transcoder DP control */
2563 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2565 struct drm_device *dev = crtc->dev;
2566 struct intel_encoder *encoder;
2568 for_each_encoder_on_crtc(dev, crtc, encoder) {
2569 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2571 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2572 intel_dp->base.type == INTEL_OUTPUT_EDP)
2573 return intel_dp->output_reg;
2579 /* check the VBT to see whether the eDP is on DP-D port */
2580 bool intel_dpd_is_edp(struct drm_device *dev)
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct child_device_config *p_child;
2586 if (!dev_priv->child_dev_num)
2589 for (i = 0; i < dev_priv->child_dev_num; i++) {
2590 p_child = dev_priv->child_dev + i;
2592 if (p_child->dvo_port == PORT_IDPD &&
2593 p_child->device_type == DEVICE_TYPE_eDP)
2600 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2602 intel_attach_force_audio_property(connector);
2603 intel_attach_broadcast_rgb_property(connector);
2607 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2610 struct drm_connector *connector;
2611 struct intel_dp *intel_dp;
2612 struct intel_encoder *intel_encoder;
2613 struct intel_connector *intel_connector;
2614 struct drm_display_mode *fixed_mode = NULL;
2615 const char *name = NULL;
2618 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2622 intel_dp->output_reg = output_reg;
2623 intel_dp->port = port;
2624 /* Preserve the current hw state. */
2625 intel_dp->DP = I915_READ(intel_dp->output_reg);
2627 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2628 if (!intel_connector) {
2632 intel_encoder = &intel_dp->base;
2634 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2635 if (intel_dpd_is_edp(dev))
2636 intel_dp->is_pch_edp = true;
2639 * FIXME : We need to initialize built-in panels before external panels.
2640 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2642 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2643 type = DRM_MODE_CONNECTOR_eDP;
2644 intel_encoder->type = INTEL_OUTPUT_EDP;
2645 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2646 type = DRM_MODE_CONNECTOR_eDP;
2647 intel_encoder->type = INTEL_OUTPUT_EDP;
2649 type = DRM_MODE_CONNECTOR_DisplayPort;
2650 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2653 connector = &intel_connector->base;
2654 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2655 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2657 connector->polled = DRM_CONNECTOR_POLL_HPD;
2659 intel_encoder->cloneable = false;
2661 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2662 ironlake_panel_vdd_work);
2664 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2666 connector->interlace_allowed = true;
2667 connector->doublescan_allowed = 0;
2669 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2670 DRM_MODE_ENCODER_TMDS);
2672 if (IS_HASWELL(dev))
2673 drm_encoder_helper_add(&intel_encoder->base,
2674 &intel_dp_helper_funcs_hsw);
2676 drm_encoder_helper_add(&intel_encoder->base,
2677 &intel_dp_helper_funcs);
2679 intel_connector_attach_encoder(intel_connector, intel_encoder);
2680 drm_sysfs_connector_add(connector);
2682 if (IS_HASWELL(dev)) {
2683 intel_encoder->enable = intel_enable_ddi;
2684 intel_encoder->pre_enable = intel_ddi_pre_enable;
2685 intel_encoder->disable = intel_disable_ddi;
2686 intel_encoder->post_disable = intel_ddi_post_disable;
2687 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2689 intel_encoder->enable = intel_enable_dp;
2690 intel_encoder->pre_enable = intel_pre_enable_dp;
2691 intel_encoder->disable = intel_disable_dp;
2692 intel_encoder->post_disable = intel_post_disable_dp;
2693 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2695 intel_connector->get_hw_state = intel_connector_get_hw_state;
2697 /* Set up the DDC bus. */
2703 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2707 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2711 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2715 WARN(1, "Invalid port %c\n", port_name(port));
2719 /* Cache some DPCD data in the eDP case */
2720 if (is_edp(intel_dp)) {
2721 struct edp_power_seq cur, vbt;
2722 u32 pp_on, pp_off, pp_div;
2724 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2725 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2726 pp_div = I915_READ(PCH_PP_DIVISOR);
2728 if (!pp_on || !pp_off || !pp_div) {
2729 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2730 intel_dp_encoder_destroy(&intel_dp->base.base);
2731 intel_dp_destroy(&intel_connector->base);
2735 /* Pull timing values out of registers */
2736 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2737 PANEL_POWER_UP_DELAY_SHIFT;
2739 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2740 PANEL_LIGHT_ON_DELAY_SHIFT;
2742 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2743 PANEL_LIGHT_OFF_DELAY_SHIFT;
2745 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2746 PANEL_POWER_DOWN_DELAY_SHIFT;
2748 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2749 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2751 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2752 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2754 vbt = dev_priv->edp.pps;
2756 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2757 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2759 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2761 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2762 intel_dp->backlight_on_delay = get_delay(t8);
2763 intel_dp->backlight_off_delay = get_delay(t9);
2764 intel_dp->panel_power_down_delay = get_delay(t10);
2765 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2767 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2768 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2769 intel_dp->panel_power_cycle_delay);
2771 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2772 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2775 intel_dp_i2c_init(intel_dp, intel_connector, name);
2777 if (is_edp(intel_dp)) {
2779 struct drm_display_mode *scan;
2782 ironlake_edp_panel_vdd_on(intel_dp);
2783 ret = intel_dp_get_dpcd(intel_dp);
2784 ironlake_edp_panel_vdd_off(intel_dp, false);
2787 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2788 dev_priv->no_aux_handshake =
2789 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2790 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2792 /* if this fails, presume the device is a ghost */
2793 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2794 intel_dp_encoder_destroy(&intel_dp->base.base);
2795 intel_dp_destroy(&intel_connector->base);
2799 ironlake_edp_panel_vdd_on(intel_dp);
2800 edid = drm_get_edid(connector, &intel_dp->adapter);
2802 drm_mode_connector_update_edid_property(connector,
2804 intel_dp->edid_mode_count =
2805 drm_add_edid_modes(connector, edid);
2806 drm_edid_to_eld(connector, edid);
2807 intel_dp->edid = edid;
2810 /* prefer fixed mode from EDID if available */
2811 list_for_each_entry(scan, &connector->probed_modes, head) {
2812 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2813 fixed_mode = drm_mode_duplicate(dev, scan);
2818 /* fallback to VBT if available for eDP */
2819 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2820 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2822 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2824 intel_dp->panel_fixed_mode = fixed_mode;
2826 ironlake_edp_panel_vdd_off(intel_dp, false);
2829 intel_encoder->hot_plug = intel_dp_hot_plug;
2831 if (is_edp(intel_dp))
2832 intel_panel_setup_backlight(connector);
2834 intel_dp_add_properties(intel_dp, connector);
2836 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2837 * 0xd. Failure to do so will result in spurious interrupts being
2838 * generated on the port when a cable is not attached.
2840 if (IS_G4X(dev) && !IS_GM45(dev)) {
2841 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2842 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);