2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll[] = {
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
62 static const struct dp_link_dpll pch_dpll[] = {
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
69 static const struct dp_link_dpll vlv_dpll[] = {
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp *intel_dp)
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
118 return intel_dig_port->base.base.dev;
121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
126 static void intel_dp_link_down(struct intel_dp *intel_dp);
127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130 static void vlv_steal_power_sequencer(struct drm_device *dev,
132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
135 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw = DP_LINK_BW_1_62;
153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 u8 source_max, sink_max;
158 source_max = intel_dig_port->max_lanes;
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
161 return min(source_max, sink_max);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock, int bpp)
184 return (pixel_clock * bpp + 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
190 return (max_link_clock * max_lanes * 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
197 struct intel_dp *intel_dp = intel_attached_dp(connector);
198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
208 if (mode->vdisplay > fixed_mode->vdisplay)
211 target_clock = fixed_mode->clock;
214 max_link_clock = intel_dp_max_link_rate(intel_dp);
215 max_lanes = intel_dp_max_lane_count(intel_dp);
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
220 if (mode_rate > max_rate || target_clock > max_dotclk)
221 return MODE_CLOCK_HIGH;
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
254 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
255 struct intel_dp *intel_dp);
257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
258 struct intel_dp *intel_dp);
260 static void pps_lock(struct intel_dp *intel_dp)
262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
263 struct intel_encoder *encoder = &intel_dig_port->base;
264 struct drm_device *dev = encoder->base.dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 enum intel_display_power_domain power_domain;
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
272 power_domain = intel_display_port_aux_power_domain(encoder);
273 intel_display_power_get(dev_priv, power_domain);
275 mutex_lock(&dev_priv->pps_mutex);
278 static void pps_unlock(struct intel_dp *intel_dp)
280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
281 struct intel_encoder *encoder = &intel_dig_port->base;
282 struct drm_device *dev = encoder->base.dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
284 enum intel_display_power_domain power_domain;
286 mutex_unlock(&dev_priv->pps_mutex);
288 power_domain = intel_display_port_aux_power_domain(encoder);
289 intel_display_power_put(dev_priv, power_domain);
293 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum pipe pipe = intel_dp->pps_pipe;
299 bool pll_enabled, release_cl_override = false;
300 enum dpio_phy phy = DPIO_PHY(pipe);
301 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe), port_name(intel_dig_port->port)))
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe), port_name(intel_dig_port->port));
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
317 DP |= DP_PORT_WIDTH(1);
318 DP |= DP_LINK_TRAIN_PAT_1;
320 if (IS_CHERRYVIEW(dev))
321 DP |= DP_PIPE_SELECT_CHV(pipe);
322 else if (pipe == PIPE_B)
323 DP |= DP_PIPEB_SELECT;
325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
332 release_cl_override = IS_CHERRYVIEW(dev) &&
333 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
349 I915_WRITE(intel_dp->output_reg, DP);
350 POSTING_READ(intel_dp->output_reg);
352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
353 POSTING_READ(intel_dp->output_reg);
355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
356 POSTING_READ(intel_dp->output_reg);
359 vlv_force_pll_off(dev, pipe);
361 if (release_cl_override)
362 chv_phy_powergate_ch(dev_priv, phy, ch, false);
367 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
370 struct drm_device *dev = intel_dig_port->base.base.dev;
371 struct drm_i915_private *dev_priv = dev->dev_private;
372 struct intel_encoder *encoder;
373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
376 lockdep_assert_held(&dev_priv->pps_mutex);
378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp));
381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
388 for_each_intel_encoder(dev, encoder) {
389 struct intel_dp *tmp;
391 if (encoder->type != INTEL_OUTPUT_EDP)
394 tmp = enc_to_intel_dp(&encoder->base);
396 if (tmp->pps_pipe != INVALID_PIPE)
397 pipes &= ~(1 << tmp->pps_pipe);
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
404 if (WARN_ON(pipes == 0))
407 pipe = ffs(pipes) - 1;
409 vlv_steal_power_sequencer(dev, pipe);
410 intel_dp->pps_pipe = pipe;
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp->pps_pipe),
414 port_name(intel_dig_port->port));
416 /* init power sequencer on this pipe and port */
417 intel_dp_init_panel_power_sequencer(dev, intel_dp);
418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
424 vlv_power_sequencer_kick(intel_dp);
426 return intel_dp->pps_pipe;
430 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
433 struct drm_device *dev = intel_dig_port->base.base.dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
436 lockdep_assert_held(&dev_priv->pps_mutex);
438 /* We should never land here with regular DP ports */
439 WARN_ON(!is_edp(intel_dp));
442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
443 * mapping needs to be retrieved from VBT, for now just hard-code to
444 * use instance #0 always.
446 if (!intel_dp->pps_reset)
449 intel_dp->pps_reset = false;
452 * Only the HW needs to be reprogrammed, the SW state is fixed and
453 * has been setup during connector init.
455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
460 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
463 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
466 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
475 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
482 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
484 vlv_pipe_check pipe_check)
488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
489 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
490 PANEL_PORT_SELECT_MASK;
492 if (port_sel != PANEL_PORT_SELECT_VLV(port))
495 if (!pipe_check(dev_priv, pipe))
505 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
508 struct drm_device *dev = intel_dig_port->base.base.dev;
509 struct drm_i915_private *dev_priv = dev->dev_private;
510 enum port port = intel_dig_port->port;
512 lockdep_assert_held(&dev_priv->pps_mutex);
514 /* try to find a pipe with this port selected */
515 /* first pick one where the panel is on */
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
518 /* didn't find one? pick one where vdd is on */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_has_vdd_on);
522 /* didn't find one? pick one with just the correct port */
523 if (intel_dp->pps_pipe == INVALID_PIPE)
524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
528 if (intel_dp->pps_pipe == INVALID_PIPE) {
529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
535 port_name(port), pipe_name(intel_dp->pps_pipe));
537 intel_dp_init_panel_power_sequencer(dev, intel_dp);
538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
541 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
543 struct drm_device *dev = dev_priv->dev;
544 struct intel_encoder *encoder;
546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
551 * We can't grab pps_mutex here due to deadlock with power_domain
552 * mutex when power_domain functions are called while holding pps_mutex.
553 * That also means that in order to use pps_pipe the code needs to
554 * hold both a power domain reference and pps_mutex, and the power domain
555 * reference get/put must be done while _not_ holding pps_mutex.
556 * pps_{lock,unlock}() do these steps in the correct order, so one
557 * should use them always.
560 for_each_intel_encoder(dev, encoder) {
561 struct intel_dp *intel_dp;
563 if (encoder->type != INTEL_OUTPUT_EDP)
566 intel_dp = enc_to_intel_dp(&encoder->base);
568 intel_dp->pps_reset = true;
570 intel_dp->pps_pipe = INVALID_PIPE;
574 struct pps_registers {
582 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
583 struct intel_dp *intel_dp,
584 struct pps_registers *regs)
586 memset(regs, 0, sizeof(*regs));
588 if (IS_BROXTON(dev_priv)) {
589 int idx = bxt_power_sequencer_idx(intel_dp);
591 regs->pp_ctrl = BXT_PP_CONTROL(idx);
592 regs->pp_stat = BXT_PP_STATUS(idx);
593 regs->pp_on = BXT_PP_ON_DELAYS(idx);
594 regs->pp_off = BXT_PP_OFF_DELAYS(idx);
595 } else if (HAS_PCH_SPLIT(dev_priv)) {
596 regs->pp_ctrl = PCH_PP_CONTROL;
597 regs->pp_stat = PCH_PP_STATUS;
598 regs->pp_on = PCH_PP_ON_DELAYS;
599 regs->pp_off = PCH_PP_OFF_DELAYS;
600 regs->pp_div = PCH_PP_DIVISOR;
602 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
604 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe);
605 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe);
606 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe);
607 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe);
608 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe);
613 _pp_ctrl_reg(struct intel_dp *intel_dp)
615 struct pps_registers regs;
617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
624 _pp_stat_reg(struct intel_dp *intel_dp)
626 struct pps_registers regs;
628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
635 This function only applicable when panel PM state is not to be tracked */
636 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
639 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
641 struct drm_device *dev = intel_dp_to_dev(intel_dp);
642 struct drm_i915_private *dev_priv = dev->dev_private;
644 if (!is_edp(intel_dp) || code != SYS_RESTART)
649 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
650 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
651 i915_reg_t pp_ctrl_reg, pp_div_reg;
654 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
655 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
656 pp_div = I915_READ(pp_div_reg);
657 pp_div &= PP_REFERENCE_DIVIDER_MASK;
659 /* 0x1F write to PP_DIV_REG sets max cycle delay */
660 I915_WRITE(pp_div_reg, pp_div | 0x1F);
661 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
662 msleep(intel_dp->panel_power_cycle_delay);
665 pps_unlock(intel_dp);
670 static bool edp_have_panel_power(struct intel_dp *intel_dp)
672 struct drm_device *dev = intel_dp_to_dev(intel_dp);
673 struct drm_i915_private *dev_priv = dev->dev_private;
675 lockdep_assert_held(&dev_priv->pps_mutex);
677 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
678 intel_dp->pps_pipe == INVALID_PIPE)
681 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
684 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
686 struct drm_device *dev = intel_dp_to_dev(intel_dp);
687 struct drm_i915_private *dev_priv = dev->dev_private;
689 lockdep_assert_held(&dev_priv->pps_mutex);
691 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
692 intel_dp->pps_pipe == INVALID_PIPE)
695 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
699 intel_dp_check_edp(struct intel_dp *intel_dp)
701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
702 struct drm_i915_private *dev_priv = dev->dev_private;
704 if (!is_edp(intel_dp))
707 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
708 WARN(1, "eDP powered off while attempting aux channel communication.\n");
709 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
710 I915_READ(_pp_stat_reg(intel_dp)),
711 I915_READ(_pp_ctrl_reg(intel_dp)));
716 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
719 struct drm_device *dev = intel_dig_port->base.base.dev;
720 struct drm_i915_private *dev_priv = dev->dev_private;
721 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
725 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
727 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
728 msecs_to_jiffies_timeout(10));
730 done = wait_for_atomic(C, 10) == 0;
732 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
739 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
742 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
748 * The clock divider is based off the hrawclk, and would like to run at
749 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
751 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
754 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
757 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
763 * The clock divider is based off the cdclk or PCH rawclk, and would
764 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
765 * divide by 2000 and use that
767 if (intel_dig_port->port == PORT_A)
768 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
770 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
773 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
775 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
776 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
778 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
779 /* Workaround for non-ULT HSW */
787 return ilk_get_aux_clock_divider(intel_dp, index);
790 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
793 * SKL doesn't need us to program the AUX clock divider (Hardware will
794 * derive the clock from CDCLK automatically). We still implement the
795 * get_aux_clock_divider vfunc to plug-in into the existing code.
797 return index ? 0 : 1;
800 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
803 uint32_t aux_clock_divider)
805 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
806 struct drm_device *dev = intel_dig_port->base.base.dev;
807 uint32_t precharge, timeout;
814 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
815 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
817 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
819 return DP_AUX_CH_CTL_SEND_BUSY |
821 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
822 DP_AUX_CH_CTL_TIME_OUT_ERROR |
824 DP_AUX_CH_CTL_RECEIVE_ERROR |
825 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
826 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
827 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
830 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
835 return DP_AUX_CH_CTL_SEND_BUSY |
837 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
838 DP_AUX_CH_CTL_TIME_OUT_ERROR |
839 DP_AUX_CH_CTL_TIME_OUT_1600us |
840 DP_AUX_CH_CTL_RECEIVE_ERROR |
841 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
842 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
843 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
847 intel_dp_aux_ch(struct intel_dp *intel_dp,
848 const uint8_t *send, int send_bytes,
849 uint8_t *recv, int recv_size)
851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
852 struct drm_device *dev = intel_dig_port->base.base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
855 uint32_t aux_clock_divider;
856 int i, ret, recv_bytes;
859 bool has_aux_irq = HAS_AUX_IRQ(dev);
865 * We will be called with VDD already enabled for dpcd/edid/oui reads.
866 * In such cases we want to leave VDD enabled and it's up to upper layers
867 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
870 vdd = edp_panel_vdd_on(intel_dp);
872 /* dp aux is extremely sensitive to irq latency, hence request the
873 * lowest possible wakeup latency and so prevent the cpu from going into
876 pm_qos_update_request(&dev_priv->pm_qos, 0);
878 intel_dp_check_edp(intel_dp);
880 /* Try to wait for any previous AUX channel activity */
881 for (try = 0; try < 3; try++) {
882 status = I915_READ_NOTRACE(ch_ctl);
883 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
889 static u32 last_status = -1;
890 const u32 status = I915_READ(ch_ctl);
892 if (status != last_status) {
893 WARN(1, "dp_aux_ch not started status 0x%08x\n",
895 last_status = status;
902 /* Only 5 data registers! */
903 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
908 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
909 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
914 /* Must try at least 3 times according to DP spec */
915 for (try = 0; try < 5; try++) {
916 /* Load the send data into the aux channel data registers */
917 for (i = 0; i < send_bytes; i += 4)
918 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
919 intel_dp_pack_aux(send + i,
922 /* Send the command and wait for it to complete */
923 I915_WRITE(ch_ctl, send_ctl);
925 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
927 /* Clear done status and any errors */
931 DP_AUX_CH_CTL_TIME_OUT_ERROR |
932 DP_AUX_CH_CTL_RECEIVE_ERROR);
934 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
937 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
938 * 400us delay required for errors and timeouts
939 * Timeout errors from the HW already meet this
940 * requirement so skip to next iteration
942 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
943 usleep_range(400, 500);
946 if (status & DP_AUX_CH_CTL_DONE)
951 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
952 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
958 /* Check for timeout or receive error.
959 * Timeouts occur when the sink is not connected
961 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
962 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
967 /* Timeouts occur when the device isn't connected, so they're
968 * "normal" -- don't fill the kernel log with these */
969 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
970 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
975 /* Unload any bytes sent back from the other side */
976 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
977 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
980 * By BSpec: "Message sizes of 0 or >20 are not allowed."
981 * We have no idea of what happened so we return -EBUSY so
982 * drm layer takes care for the necessary retries.
984 if (recv_bytes == 0 || recv_bytes > 20) {
985 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
988 * FIXME: This patch was created on top of a series that
989 * organize the retries at drm level. There EBUSY should
990 * also take care for 1ms wait before retrying.
991 * That aux retries re-org is still needed and after that is
992 * merged we remove this sleep from here.
994 usleep_range(1000, 1500);
999 if (recv_bytes > recv_size)
1000 recv_bytes = recv_size;
1002 for (i = 0; i < recv_bytes; i += 4)
1003 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1004 recv + i, recv_bytes - i);
1008 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1011 edp_panel_vdd_off(intel_dp, false);
1013 pps_unlock(intel_dp);
1018 #define BARE_ADDRESS_SIZE 3
1019 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1021 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1023 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1024 uint8_t txbuf[20], rxbuf[20];
1025 size_t txsize, rxsize;
1028 txbuf[0] = (msg->request << 4) |
1029 ((msg->address >> 16) & 0xf);
1030 txbuf[1] = (msg->address >> 8) & 0xff;
1031 txbuf[2] = msg->address & 0xff;
1032 txbuf[3] = msg->size - 1;
1034 switch (msg->request & ~DP_AUX_I2C_MOT) {
1035 case DP_AUX_NATIVE_WRITE:
1036 case DP_AUX_I2C_WRITE:
1037 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1038 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1039 rxsize = 2; /* 0 or 1 data bytes */
1041 if (WARN_ON(txsize > 20))
1045 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1049 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1051 msg->reply = rxbuf[0] >> 4;
1054 /* Number of bytes written in a short write. */
1055 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1057 /* Return payload size. */
1063 case DP_AUX_NATIVE_READ:
1064 case DP_AUX_I2C_READ:
1065 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1066 rxsize = msg->size + 1;
1068 if (WARN_ON(rxsize > 20))
1071 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1073 msg->reply = rxbuf[0] >> 4;
1075 * Assume happy day, and copy the data. The caller is
1076 * expected to check msg->reply before touching it.
1078 * Return payload size.
1081 memcpy(msg->buffer, rxbuf + 1, ret);
1093 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1100 return DP_AUX_CH_CTL(port);
1103 return DP_AUX_CH_CTL(PORT_B);
1107 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1108 enum port port, int index)
1114 return DP_AUX_CH_DATA(port, index);
1117 return DP_AUX_CH_DATA(PORT_B, index);
1121 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1126 return DP_AUX_CH_CTL(port);
1130 return PCH_DP_AUX_CH_CTL(port);
1133 return DP_AUX_CH_CTL(PORT_A);
1137 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1138 enum port port, int index)
1142 return DP_AUX_CH_DATA(port, index);
1146 return PCH_DP_AUX_CH_DATA(port, index);
1149 return DP_AUX_CH_DATA(PORT_A, index);
1154 * On SKL we don't have Aux for port E so we rely
1155 * on VBT to set a proper alternate aux channel.
1157 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1159 const struct ddi_vbt_port_info *info =
1160 &dev_priv->vbt.ddi_port_info[PORT_E];
1162 switch (info->alternate_aux_channel) {
1172 MISSING_CASE(info->alternate_aux_channel);
1177 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1181 port = skl_porte_aux_port(dev_priv);
1188 return DP_AUX_CH_CTL(port);
1191 return DP_AUX_CH_CTL(PORT_A);
1195 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1196 enum port port, int index)
1199 port = skl_porte_aux_port(dev_priv);
1206 return DP_AUX_CH_DATA(port, index);
1209 return DP_AUX_CH_DATA(PORT_A, index);
1213 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1216 if (INTEL_INFO(dev_priv)->gen >= 9)
1217 return skl_aux_ctl_reg(dev_priv, port);
1218 else if (HAS_PCH_SPLIT(dev_priv))
1219 return ilk_aux_ctl_reg(dev_priv, port);
1221 return g4x_aux_ctl_reg(dev_priv, port);
1224 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1225 enum port port, int index)
1227 if (INTEL_INFO(dev_priv)->gen >= 9)
1228 return skl_aux_data_reg(dev_priv, port, index);
1229 else if (HAS_PCH_SPLIT(dev_priv))
1230 return ilk_aux_data_reg(dev_priv, port, index);
1232 return g4x_aux_data_reg(dev_priv, port, index);
1235 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1237 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1238 enum port port = dp_to_dig_port(intel_dp)->port;
1241 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1242 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1243 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1247 intel_dp_aux_fini(struct intel_dp *intel_dp)
1249 drm_dp_aux_unregister(&intel_dp->aux);
1250 kfree(intel_dp->aux.name);
1254 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1256 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1257 enum port port = intel_dig_port->port;
1260 intel_aux_reg_init(intel_dp);
1262 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1263 if (!intel_dp->aux.name)
1266 intel_dp->aux.dev = connector->base.kdev;
1267 intel_dp->aux.transfer = intel_dp_aux_transfer;
1269 DRM_DEBUG_KMS("registering %s bus for %s\n",
1271 connector->base.kdev->kobj.name);
1273 ret = drm_dp_aux_register(&intel_dp->aux);
1275 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1276 intel_dp->aux.name, ret);
1277 kfree(intel_dp->aux.name);
1285 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1287 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1289 intel_dp_aux_fini(intel_dp);
1290 intel_connector_unregister(intel_connector);
1294 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1296 if (intel_dp->num_sink_rates) {
1297 *sink_rates = intel_dp->sink_rates;
1298 return intel_dp->num_sink_rates;
1301 *sink_rates = default_rates;
1303 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1306 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1308 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_device *dev = dig_port->base.base.dev;
1311 /* WaDisableHBR2:skl */
1312 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1315 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1316 (INTEL_INFO(dev)->gen >= 9))
1323 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1325 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1326 struct drm_device *dev = dig_port->base.base.dev;
1329 if (IS_BROXTON(dev)) {
1330 *source_rates = bxt_rates;
1331 size = ARRAY_SIZE(bxt_rates);
1332 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1333 *source_rates = skl_rates;
1334 size = ARRAY_SIZE(skl_rates);
1336 *source_rates = default_rates;
1337 size = ARRAY_SIZE(default_rates);
1340 /* This depends on the fact that 5.4 is last value in the array */
1341 if (!intel_dp_source_supports_hbr2(intel_dp))
1348 intel_dp_set_clock(struct intel_encoder *encoder,
1349 struct intel_crtc_state *pipe_config)
1351 struct drm_device *dev = encoder->base.dev;
1352 const struct dp_link_dpll *divisor = NULL;
1356 divisor = gen4_dpll;
1357 count = ARRAY_SIZE(gen4_dpll);
1358 } else if (HAS_PCH_SPLIT(dev)) {
1360 count = ARRAY_SIZE(pch_dpll);
1361 } else if (IS_CHERRYVIEW(dev)) {
1363 count = ARRAY_SIZE(chv_dpll);
1364 } else if (IS_VALLEYVIEW(dev)) {
1366 count = ARRAY_SIZE(vlv_dpll);
1369 if (divisor && count) {
1370 for (i = 0; i < count; i++) {
1371 if (pipe_config->port_clock == divisor[i].clock) {
1372 pipe_config->dpll = divisor[i].dpll;
1373 pipe_config->clock_set = true;
1380 static int intersect_rates(const int *source_rates, int source_len,
1381 const int *sink_rates, int sink_len,
1384 int i = 0, j = 0, k = 0;
1386 while (i < source_len && j < sink_len) {
1387 if (source_rates[i] == sink_rates[j]) {
1388 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1390 common_rates[k] = source_rates[i];
1394 } else if (source_rates[i] < sink_rates[j]) {
1403 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1406 const int *source_rates, *sink_rates;
1407 int source_len, sink_len;
1409 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1410 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1412 return intersect_rates(source_rates, source_len,
1413 sink_rates, sink_len,
1417 static void snprintf_int_array(char *str, size_t len,
1418 const int *array, int nelem)
1424 for (i = 0; i < nelem; i++) {
1425 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1433 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1435 const int *source_rates, *sink_rates;
1436 int source_len, sink_len, common_len;
1437 int common_rates[DP_MAX_SUPPORTED_RATES];
1438 char str[128]; /* FIXME: too big for stack? */
1440 if ((drm_debug & DRM_UT_KMS) == 0)
1443 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1444 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1445 DRM_DEBUG_KMS("source rates: %s\n", str);
1447 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1448 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1449 DRM_DEBUG_KMS("sink rates: %s\n", str);
1451 common_len = intel_dp_common_rates(intel_dp, common_rates);
1452 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1453 DRM_DEBUG_KMS("common rates: %s\n", str);
1456 static int rate_to_index(int find, const int *rates)
1460 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1461 if (find == rates[i])
1468 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1470 int rates[DP_MAX_SUPPORTED_RATES] = {};
1473 len = intel_dp_common_rates(intel_dp, rates);
1474 if (WARN_ON(len <= 0))
1477 return rates[rate_to_index(0, rates) - 1];
1480 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1482 return rate_to_index(rate, intel_dp->sink_rates);
1485 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1486 uint8_t *link_bw, uint8_t *rate_select)
1488 if (intel_dp->num_sink_rates) {
1491 intel_dp_rate_select(intel_dp, port_clock);
1493 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1499 intel_dp_compute_config(struct intel_encoder *encoder,
1500 struct intel_crtc_state *pipe_config)
1502 struct drm_device *dev = encoder->base.dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1505 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1506 enum port port = dp_to_dig_port(intel_dp)->port;
1507 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1508 struct intel_connector *intel_connector = intel_dp->attached_connector;
1509 int lane_count, clock;
1510 int min_lane_count = 1;
1511 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1512 /* Conveniently, the link BW constants become indices with a shift...*/
1516 int link_avail, link_clock;
1517 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1519 uint8_t link_bw, rate_select;
1521 common_len = intel_dp_common_rates(intel_dp, common_rates);
1523 /* No common link rates between source and sink */
1524 WARN_ON(common_len <= 0);
1526 max_clock = common_len - 1;
1528 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1529 pipe_config->has_pch_encoder = true;
1531 pipe_config->has_dp_encoder = true;
1532 pipe_config->has_drrs = false;
1533 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1535 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1536 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1539 if (INTEL_INFO(dev)->gen >= 9) {
1541 ret = skl_update_scaler_crtc(pipe_config);
1546 if (HAS_GMCH_DISPLAY(dev))
1547 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1548 intel_connector->panel.fitting_mode);
1550 intel_pch_panel_fitting(intel_crtc, pipe_config,
1551 intel_connector->panel.fitting_mode);
1554 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1557 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1558 "max bw %d pixel clock %iKHz\n",
1559 max_lane_count, common_rates[max_clock],
1560 adjusted_mode->crtc_clock);
1562 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1563 * bpc in between. */
1564 bpp = pipe_config->pipe_bpp;
1565 if (is_edp(intel_dp)) {
1567 /* Get bpp from vbt only for panels that dont have bpp in edid */
1568 if (intel_connector->base.display_info.bpc == 0 &&
1569 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1570 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1571 dev_priv->vbt.edp.bpp);
1572 bpp = dev_priv->vbt.edp.bpp;
1576 * Use the maximum clock and number of lanes the eDP panel
1577 * advertizes being capable of. The panels are generally
1578 * designed to support only a single clock and lane
1579 * configuration, and typically these values correspond to the
1580 * native resolution of the panel.
1582 min_lane_count = max_lane_count;
1583 min_clock = max_clock;
1586 for (; bpp >= 6*3; bpp -= 2*3) {
1587 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1590 for (clock = min_clock; clock <= max_clock; clock++) {
1591 for (lane_count = min_lane_count;
1592 lane_count <= max_lane_count;
1595 link_clock = common_rates[clock];
1596 link_avail = intel_dp_max_data_rate(link_clock,
1599 if (mode_rate <= link_avail) {
1609 if (intel_dp->color_range_auto) {
1612 * CEA-861-E - 5.1 Default Encoding Parameters
1613 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1615 pipe_config->limited_color_range =
1616 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1618 pipe_config->limited_color_range =
1619 intel_dp->limited_color_range;
1622 pipe_config->lane_count = lane_count;
1624 pipe_config->pipe_bpp = bpp;
1625 pipe_config->port_clock = common_rates[clock];
1627 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1628 &link_bw, &rate_select);
1630 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1631 link_bw, rate_select, pipe_config->lane_count,
1632 pipe_config->port_clock, bpp);
1633 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1634 mode_rate, link_avail);
1636 intel_link_compute_m_n(bpp, lane_count,
1637 adjusted_mode->crtc_clock,
1638 pipe_config->port_clock,
1639 &pipe_config->dp_m_n);
1641 if (intel_connector->panel.downclock_mode != NULL &&
1642 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1643 pipe_config->has_drrs = true;
1644 intel_link_compute_m_n(bpp, lane_count,
1645 intel_connector->panel.downclock_mode->clock,
1646 pipe_config->port_clock,
1647 &pipe_config->dp_m2_n2);
1651 * DPLL0 VCO may need to be adjusted to get the correct
1652 * clock for eDP. This will affect cdclk as well.
1654 if (is_edp(intel_dp) &&
1655 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1658 switch (pipe_config->port_clock / 2) {
1668 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1672 intel_dp_set_clock(encoder, pipe_config);
1677 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1678 const struct intel_crtc_state *pipe_config)
1680 intel_dp->link_rate = pipe_config->port_clock;
1681 intel_dp->lane_count = pipe_config->lane_count;
1684 static void intel_dp_prepare(struct intel_encoder *encoder)
1686 struct drm_device *dev = encoder->base.dev;
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1689 enum port port = dp_to_dig_port(intel_dp)->port;
1690 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1691 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1693 intel_dp_set_link_params(intel_dp, crtc->config);
1696 * There are four kinds of DP registers:
1703 * IBX PCH and CPU are the same for almost everything,
1704 * except that the CPU DP PLL is configured in this
1707 * CPT PCH is quite different, having many bits moved
1708 * to the TRANS_DP_CTL register instead. That
1709 * configuration happens (oddly) in ironlake_pch_enable
1712 /* Preserve the BIOS-computed detected bit. This is
1713 * supposed to be read-only.
1715 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1717 /* Handle DP bits in common between all three register formats */
1718 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1719 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1721 /* Split out the IBX/CPU vs CPT settings */
1723 if (IS_GEN7(dev) && port == PORT_A) {
1724 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1725 intel_dp->DP |= DP_SYNC_HS_HIGH;
1726 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1727 intel_dp->DP |= DP_SYNC_VS_HIGH;
1728 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1730 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1731 intel_dp->DP |= DP_ENHANCED_FRAMING;
1733 intel_dp->DP |= crtc->pipe << 29;
1734 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1737 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1739 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1740 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1741 trans_dp |= TRANS_DP_ENH_FRAMING;
1743 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1744 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1746 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1747 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1748 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1750 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1751 intel_dp->DP |= DP_SYNC_HS_HIGH;
1752 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1753 intel_dp->DP |= DP_SYNC_VS_HIGH;
1754 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1756 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1757 intel_dp->DP |= DP_ENHANCED_FRAMING;
1759 if (IS_CHERRYVIEW(dev))
1760 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1761 else if (crtc->pipe == PIPE_B)
1762 intel_dp->DP |= DP_PIPEB_SELECT;
1766 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1767 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1769 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1770 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1772 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1773 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1775 static void wait_panel_status(struct intel_dp *intel_dp,
1779 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1780 struct drm_i915_private *dev_priv = dev->dev_private;
1781 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1783 lockdep_assert_held(&dev_priv->pps_mutex);
1785 pp_stat_reg = _pp_stat_reg(intel_dp);
1786 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1788 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1790 I915_READ(pp_stat_reg),
1791 I915_READ(pp_ctrl_reg));
1793 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1794 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
1795 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1796 I915_READ(pp_stat_reg),
1797 I915_READ(pp_ctrl_reg));
1799 DRM_DEBUG_KMS("Wait complete\n");
1802 static void wait_panel_on(struct intel_dp *intel_dp)
1804 DRM_DEBUG_KMS("Wait for panel power on\n");
1805 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1808 static void wait_panel_off(struct intel_dp *intel_dp)
1810 DRM_DEBUG_KMS("Wait for panel power off time\n");
1811 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1814 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1816 ktime_t panel_power_on_time;
1817 s64 panel_power_off_duration;
1819 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1821 /* take the difference of currrent time and panel power off time
1822 * and then make panel wait for t11_t12 if needed. */
1823 panel_power_on_time = ktime_get_boottime();
1824 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1826 /* When we disable the VDD override bit last we have to do the manual
1828 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1829 wait_remaining_ms_from_jiffies(jiffies,
1830 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1832 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1835 static void wait_backlight_on(struct intel_dp *intel_dp)
1837 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1838 intel_dp->backlight_on_delay);
1841 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1843 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1844 intel_dp->backlight_off_delay);
1847 /* Read the current pp_control value, unlocking the register if it
1851 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1857 lockdep_assert_held(&dev_priv->pps_mutex);
1859 control = I915_READ(_pp_ctrl_reg(intel_dp));
1860 if (!IS_BROXTON(dev)) {
1861 control &= ~PANEL_UNLOCK_MASK;
1862 control |= PANEL_UNLOCK_REGS;
1868 * Must be paired with edp_panel_vdd_off().
1869 * Must hold pps_mutex around the whole on/off sequence.
1870 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1872 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1874 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1875 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1876 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1877 struct drm_i915_private *dev_priv = dev->dev_private;
1878 enum intel_display_power_domain power_domain;
1880 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1881 bool need_to_disable = !intel_dp->want_panel_vdd;
1883 lockdep_assert_held(&dev_priv->pps_mutex);
1885 if (!is_edp(intel_dp))
1888 cancel_delayed_work(&intel_dp->panel_vdd_work);
1889 intel_dp->want_panel_vdd = true;
1891 if (edp_have_panel_vdd(intel_dp))
1892 return need_to_disable;
1894 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1895 intel_display_power_get(dev_priv, power_domain);
1897 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1898 port_name(intel_dig_port->port));
1900 if (!edp_have_panel_power(intel_dp))
1901 wait_panel_power_cycle(intel_dp);
1903 pp = ironlake_get_pp_control(intel_dp);
1904 pp |= EDP_FORCE_VDD;
1906 pp_stat_reg = _pp_stat_reg(intel_dp);
1907 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1909 I915_WRITE(pp_ctrl_reg, pp);
1910 POSTING_READ(pp_ctrl_reg);
1911 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1912 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1914 * If the panel wasn't on, delay before accessing aux channel
1916 if (!edp_have_panel_power(intel_dp)) {
1917 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1918 port_name(intel_dig_port->port));
1919 msleep(intel_dp->panel_power_up_delay);
1922 return need_to_disable;
1926 * Must be paired with intel_edp_panel_vdd_off() or
1927 * intel_edp_panel_off().
1928 * Nested calls to these functions are not allowed since
1929 * we drop the lock. Caller must use some higher level
1930 * locking to prevent nested calls from other threads.
1932 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1936 if (!is_edp(intel_dp))
1940 vdd = edp_panel_vdd_on(intel_dp);
1941 pps_unlock(intel_dp);
1943 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1944 port_name(dp_to_dig_port(intel_dp)->port));
1947 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1949 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1951 struct intel_digital_port *intel_dig_port =
1952 dp_to_dig_port(intel_dp);
1953 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1954 enum intel_display_power_domain power_domain;
1956 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1958 lockdep_assert_held(&dev_priv->pps_mutex);
1960 WARN_ON(intel_dp->want_panel_vdd);
1962 if (!edp_have_panel_vdd(intel_dp))
1965 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1966 port_name(intel_dig_port->port));
1968 pp = ironlake_get_pp_control(intel_dp);
1969 pp &= ~EDP_FORCE_VDD;
1971 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1972 pp_stat_reg = _pp_stat_reg(intel_dp);
1974 I915_WRITE(pp_ctrl_reg, pp);
1975 POSTING_READ(pp_ctrl_reg);
1977 /* Make sure sequencer is idle before allowing subsequent activity */
1978 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1979 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1981 if ((pp & POWER_TARGET_ON) == 0)
1982 intel_dp->panel_power_off_time = ktime_get_boottime();
1984 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1985 intel_display_power_put(dev_priv, power_domain);
1988 static void edp_panel_vdd_work(struct work_struct *__work)
1990 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1991 struct intel_dp, panel_vdd_work);
1994 if (!intel_dp->want_panel_vdd)
1995 edp_panel_vdd_off_sync(intel_dp);
1996 pps_unlock(intel_dp);
1999 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2001 unsigned long delay;
2004 * Queue the timer to fire a long time from now (relative to the power
2005 * down delay) to keep the panel power up across a sequence of
2008 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2009 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2013 * Must be paired with edp_panel_vdd_on().
2014 * Must hold pps_mutex around the whole on/off sequence.
2015 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2017 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2019 struct drm_i915_private *dev_priv =
2020 intel_dp_to_dev(intel_dp)->dev_private;
2022 lockdep_assert_held(&dev_priv->pps_mutex);
2024 if (!is_edp(intel_dp))
2027 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2028 port_name(dp_to_dig_port(intel_dp)->port));
2030 intel_dp->want_panel_vdd = false;
2033 edp_panel_vdd_off_sync(intel_dp);
2035 edp_panel_vdd_schedule_off(intel_dp);
2038 static void edp_panel_on(struct intel_dp *intel_dp)
2040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2041 struct drm_i915_private *dev_priv = dev->dev_private;
2043 i915_reg_t pp_ctrl_reg;
2045 lockdep_assert_held(&dev_priv->pps_mutex);
2047 if (!is_edp(intel_dp))
2050 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2051 port_name(dp_to_dig_port(intel_dp)->port));
2053 if (WARN(edp_have_panel_power(intel_dp),
2054 "eDP port %c panel power already on\n",
2055 port_name(dp_to_dig_port(intel_dp)->port)))
2058 wait_panel_power_cycle(intel_dp);
2060 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2061 pp = ironlake_get_pp_control(intel_dp);
2063 /* ILK workaround: disable reset around power sequence */
2064 pp &= ~PANEL_POWER_RESET;
2065 I915_WRITE(pp_ctrl_reg, pp);
2066 POSTING_READ(pp_ctrl_reg);
2069 pp |= POWER_TARGET_ON;
2071 pp |= PANEL_POWER_RESET;
2073 I915_WRITE(pp_ctrl_reg, pp);
2074 POSTING_READ(pp_ctrl_reg);
2076 wait_panel_on(intel_dp);
2077 intel_dp->last_power_on = jiffies;
2080 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2081 I915_WRITE(pp_ctrl_reg, pp);
2082 POSTING_READ(pp_ctrl_reg);
2086 void intel_edp_panel_on(struct intel_dp *intel_dp)
2088 if (!is_edp(intel_dp))
2092 edp_panel_on(intel_dp);
2093 pps_unlock(intel_dp);
2097 static void edp_panel_off(struct intel_dp *intel_dp)
2099 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2100 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2102 struct drm_i915_private *dev_priv = dev->dev_private;
2103 enum intel_display_power_domain power_domain;
2105 i915_reg_t pp_ctrl_reg;
2107 lockdep_assert_held(&dev_priv->pps_mutex);
2109 if (!is_edp(intel_dp))
2112 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2113 port_name(dp_to_dig_port(intel_dp)->port));
2115 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2116 port_name(dp_to_dig_port(intel_dp)->port));
2118 pp = ironlake_get_pp_control(intel_dp);
2119 /* We need to switch off panel power _and_ force vdd, for otherwise some
2120 * panels get very unhappy and cease to work. */
2121 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2126 intel_dp->want_panel_vdd = false;
2128 I915_WRITE(pp_ctrl_reg, pp);
2129 POSTING_READ(pp_ctrl_reg);
2131 intel_dp->panel_power_off_time = ktime_get_boottime();
2132 wait_panel_off(intel_dp);
2134 /* We got a reference when we enabled the VDD. */
2135 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2136 intel_display_power_put(dev_priv, power_domain);
2139 void intel_edp_panel_off(struct intel_dp *intel_dp)
2141 if (!is_edp(intel_dp))
2145 edp_panel_off(intel_dp);
2146 pps_unlock(intel_dp);
2149 /* Enable backlight in the panel power control. */
2150 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2152 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2153 struct drm_device *dev = intel_dig_port->base.base.dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2156 i915_reg_t pp_ctrl_reg;
2159 * If we enable the backlight right away following a panel power
2160 * on, we may see slight flicker as the panel syncs with the eDP
2161 * link. So delay a bit to make sure the image is solid before
2162 * allowing it to appear.
2164 wait_backlight_on(intel_dp);
2168 pp = ironlake_get_pp_control(intel_dp);
2169 pp |= EDP_BLC_ENABLE;
2171 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2173 I915_WRITE(pp_ctrl_reg, pp);
2174 POSTING_READ(pp_ctrl_reg);
2176 pps_unlock(intel_dp);
2179 /* Enable backlight PWM and backlight PP control. */
2180 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2182 if (!is_edp(intel_dp))
2185 DRM_DEBUG_KMS("\n");
2187 intel_panel_enable_backlight(intel_dp->attached_connector);
2188 _intel_edp_backlight_on(intel_dp);
2191 /* Disable backlight in the panel power control. */
2192 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2194 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2197 i915_reg_t pp_ctrl_reg;
2199 if (!is_edp(intel_dp))
2204 pp = ironlake_get_pp_control(intel_dp);
2205 pp &= ~EDP_BLC_ENABLE;
2207 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2209 I915_WRITE(pp_ctrl_reg, pp);
2210 POSTING_READ(pp_ctrl_reg);
2212 pps_unlock(intel_dp);
2214 intel_dp->last_backlight_off = jiffies;
2215 edp_wait_backlight_off(intel_dp);
2218 /* Disable backlight PP control and backlight PWM. */
2219 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2221 if (!is_edp(intel_dp))
2224 DRM_DEBUG_KMS("\n");
2226 _intel_edp_backlight_off(intel_dp);
2227 intel_panel_disable_backlight(intel_dp->attached_connector);
2231 * Hook for controlling the panel power control backlight through the bl_power
2232 * sysfs attribute. Take care to handle multiple calls.
2234 static void intel_edp_backlight_power(struct intel_connector *connector,
2237 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2241 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2242 pps_unlock(intel_dp);
2244 if (is_enabled == enable)
2247 DRM_DEBUG_KMS("panel power control backlight %s\n",
2248 enable ? "enable" : "disable");
2251 _intel_edp_backlight_on(intel_dp);
2253 _intel_edp_backlight_off(intel_dp);
2256 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2258 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2259 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2260 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2262 I915_STATE_WARN(cur_state != state,
2263 "DP port %c state assertion failure (expected %s, current %s)\n",
2264 port_name(dig_port->port),
2265 onoff(state), onoff(cur_state));
2267 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2269 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2271 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2273 I915_STATE_WARN(cur_state != state,
2274 "eDP PLL state assertion failure (expected %s, current %s)\n",
2275 onoff(state), onoff(cur_state));
2277 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2278 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2280 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2283 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2284 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2286 assert_pipe_disabled(dev_priv, crtc->pipe);
2287 assert_dp_port_disabled(intel_dp);
2288 assert_edp_pll_disabled(dev_priv);
2290 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2291 crtc->config->port_clock);
2293 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2295 if (crtc->config->port_clock == 162000)
2296 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2298 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2300 I915_WRITE(DP_A, intel_dp->DP);
2305 * [DevILK] Work around required when enabling DP PLL
2306 * while a pipe is enabled going to FDI:
2307 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2308 * 2. Program DP PLL enable
2310 if (IS_GEN5(dev_priv))
2311 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2313 intel_dp->DP |= DP_PLL_ENABLE;
2315 I915_WRITE(DP_A, intel_dp->DP);
2320 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2323 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2324 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2326 assert_pipe_disabled(dev_priv, crtc->pipe);
2327 assert_dp_port_disabled(intel_dp);
2328 assert_edp_pll_enabled(dev_priv);
2330 DRM_DEBUG_KMS("disabling eDP PLL\n");
2332 intel_dp->DP &= ~DP_PLL_ENABLE;
2334 I915_WRITE(DP_A, intel_dp->DP);
2339 /* If the sink supports it, try to set the power state appropriately */
2340 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2344 /* Should have a valid DPCD by this point */
2345 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2348 if (mode != DRM_MODE_DPMS_ON) {
2349 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2353 * When turning on, we need to retry for 1ms to give the sink
2356 for (i = 0; i < 3; i++) {
2357 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2366 DRM_DEBUG_KMS("failed to %s sink power state\n",
2367 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2370 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2373 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2374 enum port port = dp_to_dig_port(intel_dp)->port;
2375 struct drm_device *dev = encoder->base.dev;
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 enum intel_display_power_domain power_domain;
2381 power_domain = intel_display_port_power_domain(encoder);
2382 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2387 tmp = I915_READ(intel_dp->output_reg);
2389 if (!(tmp & DP_PORT_EN))
2392 if (IS_GEN7(dev) && port == PORT_A) {
2393 *pipe = PORT_TO_PIPE_CPT(tmp);
2394 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2397 for_each_pipe(dev_priv, p) {
2398 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2399 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2407 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2408 i915_mmio_reg_offset(intel_dp->output_reg));
2409 } else if (IS_CHERRYVIEW(dev)) {
2410 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2412 *pipe = PORT_TO_PIPE(tmp);
2418 intel_display_power_put(dev_priv, power_domain);
2423 static void intel_dp_get_config(struct intel_encoder *encoder,
2424 struct intel_crtc_state *pipe_config)
2426 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2428 struct drm_device *dev = encoder->base.dev;
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 enum port port = dp_to_dig_port(intel_dp)->port;
2431 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2433 tmp = I915_READ(intel_dp->output_reg);
2435 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2437 if (HAS_PCH_CPT(dev) && port != PORT_A) {
2438 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2440 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2441 flags |= DRM_MODE_FLAG_PHSYNC;
2443 flags |= DRM_MODE_FLAG_NHSYNC;
2445 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2446 flags |= DRM_MODE_FLAG_PVSYNC;
2448 flags |= DRM_MODE_FLAG_NVSYNC;
2450 if (tmp & DP_SYNC_HS_HIGH)
2451 flags |= DRM_MODE_FLAG_PHSYNC;
2453 flags |= DRM_MODE_FLAG_NHSYNC;
2455 if (tmp & DP_SYNC_VS_HIGH)
2456 flags |= DRM_MODE_FLAG_PVSYNC;
2458 flags |= DRM_MODE_FLAG_NVSYNC;
2461 pipe_config->base.adjusted_mode.flags |= flags;
2463 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2464 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2465 pipe_config->limited_color_range = true;
2467 pipe_config->has_dp_encoder = true;
2469 pipe_config->lane_count =
2470 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2472 intel_dp_get_m_n(crtc, pipe_config);
2474 if (port == PORT_A) {
2475 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2476 pipe_config->port_clock = 162000;
2478 pipe_config->port_clock = 270000;
2481 pipe_config->base.adjusted_mode.crtc_clock =
2482 intel_dotclock_calculate(pipe_config->port_clock,
2483 &pipe_config->dp_m_n);
2485 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2486 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2488 * This is a big fat ugly hack.
2490 * Some machines in UEFI boot mode provide us a VBT that has 18
2491 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2492 * unknown we fail to light up. Yet the same BIOS boots up with
2493 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2494 * max, not what it tells us to use.
2496 * Note: This will still be broken if the eDP panel is not lit
2497 * up by the BIOS, and thus we can't get the mode at module
2500 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2501 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2502 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2506 static void intel_disable_dp(struct intel_encoder *encoder)
2508 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2509 struct drm_device *dev = encoder->base.dev;
2510 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2512 if (crtc->config->has_audio)
2513 intel_audio_codec_disable(encoder);
2515 if (HAS_PSR(dev) && !HAS_DDI(dev))
2516 intel_psr_disable(intel_dp);
2518 /* Make sure the panel is off before trying to change the mode. But also
2519 * ensure that we have vdd while we switch off the panel. */
2520 intel_edp_panel_vdd_on(intel_dp);
2521 intel_edp_backlight_off(intel_dp);
2522 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2523 intel_edp_panel_off(intel_dp);
2525 /* disable the port before the pipe on g4x */
2526 if (INTEL_INFO(dev)->gen < 5)
2527 intel_dp_link_down(intel_dp);
2530 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2532 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2533 enum port port = dp_to_dig_port(intel_dp)->port;
2535 intel_dp_link_down(intel_dp);
2537 /* Only ilk+ has port A */
2539 ironlake_edp_pll_off(intel_dp);
2542 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2544 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2546 intel_dp_link_down(intel_dp);
2549 static void chv_post_disable_dp(struct intel_encoder *encoder)
2551 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2552 struct drm_device *dev = encoder->base.dev;
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2555 intel_dp_link_down(intel_dp);
2557 mutex_lock(&dev_priv->sb_lock);
2559 /* Assert data lane reset */
2560 chv_data_lane_soft_reset(encoder, true);
2562 mutex_unlock(&dev_priv->sb_lock);
2566 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2568 uint8_t dp_train_pat)
2570 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2571 struct drm_device *dev = intel_dig_port->base.base.dev;
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573 enum port port = intel_dig_port->port;
2576 uint32_t temp = I915_READ(DP_TP_CTL(port));
2578 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2579 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2581 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2583 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2584 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2585 case DP_TRAINING_PATTERN_DISABLE:
2586 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2589 case DP_TRAINING_PATTERN_1:
2590 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2592 case DP_TRAINING_PATTERN_2:
2593 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2595 case DP_TRAINING_PATTERN_3:
2596 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2599 I915_WRITE(DP_TP_CTL(port), temp);
2601 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2602 (HAS_PCH_CPT(dev) && port != PORT_A)) {
2603 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2605 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2606 case DP_TRAINING_PATTERN_DISABLE:
2607 *DP |= DP_LINK_TRAIN_OFF_CPT;
2609 case DP_TRAINING_PATTERN_1:
2610 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2612 case DP_TRAINING_PATTERN_2:
2613 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2615 case DP_TRAINING_PATTERN_3:
2616 DRM_ERROR("DP training pattern 3 not supported\n");
2617 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2622 if (IS_CHERRYVIEW(dev))
2623 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2625 *DP &= ~DP_LINK_TRAIN_MASK;
2627 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2628 case DP_TRAINING_PATTERN_DISABLE:
2629 *DP |= DP_LINK_TRAIN_OFF;
2631 case DP_TRAINING_PATTERN_1:
2632 *DP |= DP_LINK_TRAIN_PAT_1;
2634 case DP_TRAINING_PATTERN_2:
2635 *DP |= DP_LINK_TRAIN_PAT_2;
2637 case DP_TRAINING_PATTERN_3:
2638 if (IS_CHERRYVIEW(dev)) {
2639 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2641 DRM_ERROR("DP training pattern 3 not supported\n");
2642 *DP |= DP_LINK_TRAIN_PAT_2;
2649 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2651 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 struct intel_crtc *crtc =
2654 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2656 /* enable with pattern 1 (as per spec) */
2657 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2658 DP_TRAINING_PATTERN_1);
2660 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2661 POSTING_READ(intel_dp->output_reg);
2664 * Magic for VLV/CHV. We _must_ first set up the register
2665 * without actually enabling the port, and then do another
2666 * write to enable the port. Otherwise link training will
2667 * fail when the power sequencer is freshly used for this port.
2669 intel_dp->DP |= DP_PORT_EN;
2670 if (crtc->config->has_audio)
2671 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2673 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2674 POSTING_READ(intel_dp->output_reg);
2677 static void intel_enable_dp(struct intel_encoder *encoder)
2679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2680 struct drm_device *dev = encoder->base.dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2683 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2684 enum pipe pipe = crtc->pipe;
2686 if (WARN_ON(dp_reg & DP_PORT_EN))
2691 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2692 vlv_init_panel_power_sequencer(intel_dp);
2694 intel_dp_enable_port(intel_dp);
2696 edp_panel_vdd_on(intel_dp);
2697 edp_panel_on(intel_dp);
2698 edp_panel_vdd_off(intel_dp, true);
2700 pps_unlock(intel_dp);
2702 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2703 unsigned int lane_mask = 0x0;
2705 if (IS_CHERRYVIEW(dev))
2706 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2708 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2712 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2713 intel_dp_start_link_train(intel_dp);
2714 intel_dp_stop_link_train(intel_dp);
2716 if (crtc->config->has_audio) {
2717 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2719 intel_audio_codec_enable(encoder);
2723 static void g4x_enable_dp(struct intel_encoder *encoder)
2725 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2727 intel_enable_dp(encoder);
2728 intel_edp_backlight_on(intel_dp);
2731 static void vlv_enable_dp(struct intel_encoder *encoder)
2733 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2735 intel_edp_backlight_on(intel_dp);
2736 intel_psr_enable(intel_dp);
2739 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2741 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2742 enum port port = dp_to_dig_port(intel_dp)->port;
2744 intel_dp_prepare(encoder);
2746 /* Only ilk+ has port A */
2748 ironlake_edp_pll_on(intel_dp);
2751 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2754 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2755 enum pipe pipe = intel_dp->pps_pipe;
2756 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2758 edp_panel_vdd_off_sync(intel_dp);
2761 * VLV seems to get confused when multiple power seqeuencers
2762 * have the same port selected (even if only one has power/vdd
2763 * enabled). The failure manifests as vlv_wait_port_ready() failing
2764 * CHV on the other hand doesn't seem to mind having the same port
2765 * selected in multiple power seqeuencers, but let's clear the
2766 * port select always when logically disconnecting a power sequencer
2769 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2770 pipe_name(pipe), port_name(intel_dig_port->port));
2771 I915_WRITE(pp_on_reg, 0);
2772 POSTING_READ(pp_on_reg);
2774 intel_dp->pps_pipe = INVALID_PIPE;
2777 static void vlv_steal_power_sequencer(struct drm_device *dev,
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_encoder *encoder;
2783 lockdep_assert_held(&dev_priv->pps_mutex);
2785 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2788 for_each_intel_encoder(dev, encoder) {
2789 struct intel_dp *intel_dp;
2792 if (encoder->type != INTEL_OUTPUT_EDP)
2795 intel_dp = enc_to_intel_dp(&encoder->base);
2796 port = dp_to_dig_port(intel_dp)->port;
2798 if (intel_dp->pps_pipe != pipe)
2801 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2802 pipe_name(pipe), port_name(port));
2804 WARN(encoder->base.crtc,
2805 "stealing pipe %c power sequencer from active eDP port %c\n",
2806 pipe_name(pipe), port_name(port));
2808 /* make sure vdd is off before we steal it */
2809 vlv_detach_power_sequencer(intel_dp);
2813 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2815 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2816 struct intel_encoder *encoder = &intel_dig_port->base;
2817 struct drm_device *dev = encoder->base.dev;
2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2821 lockdep_assert_held(&dev_priv->pps_mutex);
2823 if (!is_edp(intel_dp))
2826 if (intel_dp->pps_pipe == crtc->pipe)
2830 * If another power sequencer was being used on this
2831 * port previously make sure to turn off vdd there while
2832 * we still have control of it.
2834 if (intel_dp->pps_pipe != INVALID_PIPE)
2835 vlv_detach_power_sequencer(intel_dp);
2838 * We may be stealing the power
2839 * sequencer from another port.
2841 vlv_steal_power_sequencer(dev, crtc->pipe);
2843 /* now it's all ours */
2844 intel_dp->pps_pipe = crtc->pipe;
2846 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2847 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2849 /* init power sequencer on this pipe and port */
2850 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2851 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2854 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2856 vlv_phy_pre_encoder_enable(encoder);
2858 intel_enable_dp(encoder);
2861 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2863 intel_dp_prepare(encoder);
2865 vlv_phy_pre_pll_enable(encoder);
2868 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2870 chv_phy_pre_encoder_enable(encoder);
2872 intel_enable_dp(encoder);
2874 /* Second common lane will stay alive on its own now */
2875 chv_phy_release_cl2_override(encoder);
2878 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2880 intel_dp_prepare(encoder);
2882 chv_phy_pre_pll_enable(encoder);
2885 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2887 chv_phy_post_pll_disable(encoder);
2891 * Fetch AUX CH registers 0x202 - 0x207 which contain
2892 * link status information
2895 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2897 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2898 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2901 /* These are source-specific values. */
2903 intel_dp_voltage_max(struct intel_dp *intel_dp)
2905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 enum port port = dp_to_dig_port(intel_dp)->port;
2909 if (IS_BROXTON(dev))
2910 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2911 else if (INTEL_INFO(dev)->gen >= 9) {
2912 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2913 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2914 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2915 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2916 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2917 else if (IS_GEN7(dev) && port == PORT_A)
2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2919 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2920 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2922 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2926 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2929 enum port port = dp_to_dig_port(intel_dp)->port;
2931 if (INTEL_INFO(dev)->gen >= 9) {
2932 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2942 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2944 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2945 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2954 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2956 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2957 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2968 } else if (IS_GEN7(dev) && port == PORT_A) {
2969 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2974 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2976 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2979 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2993 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
2995 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2996 unsigned long demph_reg_value, preemph_reg_value,
2997 uniqtranscale_reg_value;
2998 uint8_t train_set = intel_dp->train_set[0];
3000 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3001 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3002 preemph_reg_value = 0x0004000;
3003 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3005 demph_reg_value = 0x2B405555;
3006 uniqtranscale_reg_value = 0x552AB83A;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3009 demph_reg_value = 0x2B404040;
3010 uniqtranscale_reg_value = 0x5548B83A;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3013 demph_reg_value = 0x2B245555;
3014 uniqtranscale_reg_value = 0x5560B83A;
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3017 demph_reg_value = 0x2B405555;
3018 uniqtranscale_reg_value = 0x5598DA3A;
3024 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3025 preemph_reg_value = 0x0002000;
3026 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3028 demph_reg_value = 0x2B404040;
3029 uniqtranscale_reg_value = 0x5552B83A;
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3032 demph_reg_value = 0x2B404848;
3033 uniqtranscale_reg_value = 0x5580B83A;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3036 demph_reg_value = 0x2B404040;
3037 uniqtranscale_reg_value = 0x55ADDA3A;
3043 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3044 preemph_reg_value = 0x0000000;
3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3047 demph_reg_value = 0x2B305555;
3048 uniqtranscale_reg_value = 0x5570B83A;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3051 demph_reg_value = 0x2B2B4040;
3052 uniqtranscale_reg_value = 0x55ADDA3A;
3058 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3059 preemph_reg_value = 0x0006000;
3060 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3062 demph_reg_value = 0x1B405555;
3063 uniqtranscale_reg_value = 0x55ADDA3A;
3073 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3074 uniqtranscale_reg_value, 0);
3079 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3081 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3082 u32 deemph_reg_value, margin_reg_value;
3083 bool uniq_trans_scale = false;
3084 uint8_t train_set = intel_dp->train_set[0];
3086 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3087 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3088 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3090 deemph_reg_value = 128;
3091 margin_reg_value = 52;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3094 deemph_reg_value = 128;
3095 margin_reg_value = 77;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3098 deemph_reg_value = 128;
3099 margin_reg_value = 102;
3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3102 deemph_reg_value = 128;
3103 margin_reg_value = 154;
3104 uniq_trans_scale = true;
3110 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3113 deemph_reg_value = 85;
3114 margin_reg_value = 78;
3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3117 deemph_reg_value = 85;
3118 margin_reg_value = 116;
3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3121 deemph_reg_value = 85;
3122 margin_reg_value = 154;
3128 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3129 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3131 deemph_reg_value = 64;
3132 margin_reg_value = 104;
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3135 deemph_reg_value = 64;
3136 margin_reg_value = 154;
3142 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3145 deemph_reg_value = 43;
3146 margin_reg_value = 154;
3156 chv_set_phy_signal_level(encoder, deemph_reg_value,
3157 margin_reg_value, uniq_trans_scale);
3163 gen4_signal_levels(uint8_t train_set)
3165 uint32_t signal_levels = 0;
3167 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3170 signal_levels |= DP_VOLTAGE_0_4;
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3173 signal_levels |= DP_VOLTAGE_0_6;
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3176 signal_levels |= DP_VOLTAGE_0_8;
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3179 signal_levels |= DP_VOLTAGE_1_2;
3182 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3183 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3185 signal_levels |= DP_PRE_EMPHASIS_0;
3187 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3188 signal_levels |= DP_PRE_EMPHASIS_3_5;
3190 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3191 signal_levels |= DP_PRE_EMPHASIS_6;
3193 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3194 signal_levels |= DP_PRE_EMPHASIS_9_5;
3197 return signal_levels;
3200 /* Gen6's DP voltage swing and pre-emphasis control */
3202 gen6_edp_signal_levels(uint8_t train_set)
3204 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3205 DP_TRAIN_PRE_EMPHASIS_MASK);
3206 switch (signal_levels) {
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3209 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3211 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3214 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3217 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3220 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3222 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3223 "0x%x\n", signal_levels);
3224 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3228 /* Gen7's DP voltage swing and pre-emphasis control */
3230 gen7_edp_signal_levels(uint8_t train_set)
3232 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3233 DP_TRAIN_PRE_EMPHASIS_MASK);
3234 switch (signal_levels) {
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3236 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3238 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3240 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3243 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3245 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3248 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3250 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3253 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3254 "0x%x\n", signal_levels);
3255 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3260 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3263 enum port port = intel_dig_port->port;
3264 struct drm_device *dev = intel_dig_port->base.base.dev;
3265 struct drm_i915_private *dev_priv = to_i915(dev);
3266 uint32_t signal_levels, mask = 0;
3267 uint8_t train_set = intel_dp->train_set[0];
3270 signal_levels = ddi_signal_levels(intel_dp);
3272 if (IS_BROXTON(dev))
3275 mask = DDI_BUF_EMP_MASK;
3276 } else if (IS_CHERRYVIEW(dev)) {
3277 signal_levels = chv_signal_levels(intel_dp);
3278 } else if (IS_VALLEYVIEW(dev)) {
3279 signal_levels = vlv_signal_levels(intel_dp);
3280 } else if (IS_GEN7(dev) && port == PORT_A) {
3281 signal_levels = gen7_edp_signal_levels(train_set);
3282 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3283 } else if (IS_GEN6(dev) && port == PORT_A) {
3284 signal_levels = gen6_edp_signal_levels(train_set);
3285 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3287 signal_levels = gen4_signal_levels(train_set);
3288 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3292 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3294 DRM_DEBUG_KMS("Using vswing level %d\n",
3295 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3296 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3297 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3298 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3300 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3302 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3303 POSTING_READ(intel_dp->output_reg);
3307 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3308 uint8_t dp_train_pat)
3310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3311 struct drm_i915_private *dev_priv =
3312 to_i915(intel_dig_port->base.base.dev);
3314 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3316 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3317 POSTING_READ(intel_dp->output_reg);
3320 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3323 struct drm_device *dev = intel_dig_port->base.base.dev;
3324 struct drm_i915_private *dev_priv = dev->dev_private;
3325 enum port port = intel_dig_port->port;
3331 val = I915_READ(DP_TP_CTL(port));
3332 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3333 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3334 I915_WRITE(DP_TP_CTL(port), val);
3337 * On PORT_A we can have only eDP in SST mode. There the only reason
3338 * we need to set idle transmission mode is to work around a HW issue
3339 * where we enable the pipe while not in idle link-training mode.
3340 * In this case there is requirement to wait for a minimum number of
3341 * idle patterns to be sent.
3346 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3348 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3352 intel_dp_link_down(struct intel_dp *intel_dp)
3354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3355 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3356 enum port port = intel_dig_port->port;
3357 struct drm_device *dev = intel_dig_port->base.base.dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 uint32_t DP = intel_dp->DP;
3361 if (WARN_ON(HAS_DDI(dev)))
3364 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3367 DRM_DEBUG_KMS("\n");
3369 if ((IS_GEN7(dev) && port == PORT_A) ||
3370 (HAS_PCH_CPT(dev) && port != PORT_A)) {
3371 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3372 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3374 if (IS_CHERRYVIEW(dev))
3375 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3377 DP &= ~DP_LINK_TRAIN_MASK;
3378 DP |= DP_LINK_TRAIN_PAT_IDLE;
3380 I915_WRITE(intel_dp->output_reg, DP);
3381 POSTING_READ(intel_dp->output_reg);
3383 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3384 I915_WRITE(intel_dp->output_reg, DP);
3385 POSTING_READ(intel_dp->output_reg);
3388 * HW workaround for IBX, we need to move the port
3389 * to transcoder A after disabling it to allow the
3390 * matching HDMI port to be enabled on transcoder A.
3392 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3394 * We get CPU/PCH FIFO underruns on the other pipe when
3395 * doing the workaround. Sweep them under the rug.
3397 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3398 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3400 /* always enable with pattern 1 (as per spec) */
3401 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3402 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3403 I915_WRITE(intel_dp->output_reg, DP);
3404 POSTING_READ(intel_dp->output_reg);
3407 I915_WRITE(intel_dp->output_reg, DP);
3408 POSTING_READ(intel_dp->output_reg);
3410 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3411 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3412 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3415 msleep(intel_dp->panel_power_down_delay);
3421 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3423 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3424 struct drm_device *dev = dig_port->base.base.dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3427 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3428 sizeof(intel_dp->dpcd)) < 0)
3429 return false; /* aux transfer failed */
3431 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3433 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3434 return false; /* DPCD not present */
3436 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3437 &intel_dp->sink_count, 1) < 0)
3441 * Sink count can change between short pulse hpd hence
3442 * a member variable in intel_dp will track any changes
3443 * between short pulse interrupts.
3445 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3448 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3449 * a dongle is present but no display. Unless we require to know
3450 * if a dongle is present or not, we don't need to update
3451 * downstream port information. So, an early return here saves
3452 * time from performing other operations which are not required.
3454 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3457 /* Check if the panel supports PSR */
3458 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3459 if (is_edp(intel_dp)) {
3460 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3462 sizeof(intel_dp->psr_dpcd));
3463 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3464 dev_priv->psr.sink_support = true;
3465 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3468 if (INTEL_INFO(dev)->gen >= 9 &&
3469 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3470 uint8_t frame_sync_cap;
3472 dev_priv->psr.sink_support = true;
3473 drm_dp_dpcd_read(&intel_dp->aux,
3474 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3475 &frame_sync_cap, 1);
3476 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3477 /* PSR2 needs frame sync as well */
3478 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3479 DRM_DEBUG_KMS("PSR2 %s on sink",
3480 dev_priv->psr.psr2_support ? "supported" : "not supported");
3483 /* Read the eDP Display control capabilities registers */
3484 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3485 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3486 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3487 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3488 sizeof(intel_dp->edp_dpcd)))
3489 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3490 intel_dp->edp_dpcd);
3493 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3494 yesno(intel_dp_source_supports_hbr2(intel_dp)),
3495 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3497 /* Intermediate frequency support */
3498 if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
3499 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3502 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3503 sink_rates, sizeof(sink_rates));
3505 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3506 int val = le16_to_cpu(sink_rates[i]);
3511 /* Value read is in kHz while drm clock is saved in deca-kHz */
3512 intel_dp->sink_rates[i] = (val * 200) / 10;
3514 intel_dp->num_sink_rates = i;
3517 intel_dp_print_rates(intel_dp);
3519 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3520 DP_DWN_STRM_PORT_PRESENT))
3521 return true; /* native DP sink */
3523 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3524 return true; /* no per-port downstream info */
3526 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3527 intel_dp->downstream_ports,
3528 DP_MAX_DOWNSTREAM_PORTS) < 0)
3529 return false; /* downstream port status fetch failed */
3535 intel_dp_probe_oui(struct intel_dp *intel_dp)
3539 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3542 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3543 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3544 buf[0], buf[1], buf[2]);
3546 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3547 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3548 buf[0], buf[1], buf[2]);
3552 intel_dp_probe_mst(struct intel_dp *intel_dp)
3556 if (!i915.enable_dp_mst)
3559 if (!intel_dp->can_mst)
3562 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3565 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3566 if (buf[0] & DP_MST_CAP) {
3567 DRM_DEBUG_KMS("Sink is MST capable\n");
3568 intel_dp->is_mst = true;
3570 DRM_DEBUG_KMS("Sink is not MST capable\n");
3571 intel_dp->is_mst = false;
3575 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3576 return intel_dp->is_mst;
3579 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3581 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3582 struct drm_device *dev = dig_port->base.base.dev;
3583 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3589 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3590 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3595 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3596 buf & ~DP_TEST_SINK_START) < 0) {
3597 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3603 intel_wait_for_vblank(dev, intel_crtc->pipe);
3605 if (drm_dp_dpcd_readb(&intel_dp->aux,
3606 DP_TEST_SINK_MISC, &buf) < 0) {
3610 count = buf & DP_TEST_COUNT_MASK;
3611 } while (--attempts && count);
3613 if (attempts == 0) {
3614 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3619 hsw_enable_ips(intel_crtc);
3623 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3625 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3626 struct drm_device *dev = dig_port->base.base.dev;
3627 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3631 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3634 if (!(buf & DP_TEST_CRC_SUPPORTED))
3637 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3640 if (buf & DP_TEST_SINK_START) {
3641 ret = intel_dp_sink_crc_stop(intel_dp);
3646 hsw_disable_ips(intel_crtc);
3648 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3649 buf | DP_TEST_SINK_START) < 0) {
3650 hsw_enable_ips(intel_crtc);
3654 intel_wait_for_vblank(dev, intel_crtc->pipe);
3658 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3660 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3661 struct drm_device *dev = dig_port->base.base.dev;
3662 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3667 ret = intel_dp_sink_crc_start(intel_dp);
3672 intel_wait_for_vblank(dev, intel_crtc->pipe);
3674 if (drm_dp_dpcd_readb(&intel_dp->aux,
3675 DP_TEST_SINK_MISC, &buf) < 0) {
3679 count = buf & DP_TEST_COUNT_MASK;
3681 } while (--attempts && count == 0);
3683 if (attempts == 0) {
3684 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3689 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3695 intel_dp_sink_crc_stop(intel_dp);
3700 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3702 return drm_dp_dpcd_read(&intel_dp->aux,
3703 DP_DEVICE_SERVICE_IRQ_VECTOR,
3704 sink_irq_vector, 1) == 1;
3708 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3712 ret = drm_dp_dpcd_read(&intel_dp->aux,
3714 sink_irq_vector, 14);
3721 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3723 uint8_t test_result = DP_TEST_ACK;
3727 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3729 uint8_t test_result = DP_TEST_NAK;
3733 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3735 uint8_t test_result = DP_TEST_NAK;
3736 struct intel_connector *intel_connector = intel_dp->attached_connector;
3737 struct drm_connector *connector = &intel_connector->base;
3739 if (intel_connector->detect_edid == NULL ||
3740 connector->edid_corrupt ||
3741 intel_dp->aux.i2c_defer_count > 6) {
3742 /* Check EDID read for NACKs, DEFERs and corruption
3743 * (DP CTS 1.2 Core r1.1)
3744 * 4.2.2.4 : Failed EDID read, I2C_NAK
3745 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3746 * 4.2.2.6 : EDID corruption detected
3747 * Use failsafe mode for all cases
3749 if (intel_dp->aux.i2c_nack_count > 0 ||
3750 intel_dp->aux.i2c_defer_count > 0)
3751 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3752 intel_dp->aux.i2c_nack_count,
3753 intel_dp->aux.i2c_defer_count);
3754 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3756 struct edid *block = intel_connector->detect_edid;
3758 /* We have to write the checksum
3759 * of the last block read
3761 block += intel_connector->detect_edid->extensions;
3763 if (!drm_dp_dpcd_write(&intel_dp->aux,
3764 DP_TEST_EDID_CHECKSUM,
3767 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3769 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3770 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3773 /* Set test active flag here so userspace doesn't interrupt things */
3774 intel_dp->compliance_test_active = 1;
3779 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3781 uint8_t test_result = DP_TEST_NAK;
3785 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3787 uint8_t response = DP_TEST_NAK;
3791 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3793 DRM_DEBUG_KMS("Could not read test request from sink\n");
3798 case DP_TEST_LINK_TRAINING:
3799 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3800 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3801 response = intel_dp_autotest_link_training(intel_dp);
3803 case DP_TEST_LINK_VIDEO_PATTERN:
3804 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3805 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3806 response = intel_dp_autotest_video_pattern(intel_dp);
3808 case DP_TEST_LINK_EDID_READ:
3809 DRM_DEBUG_KMS("EDID test requested\n");
3810 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3811 response = intel_dp_autotest_edid(intel_dp);
3813 case DP_TEST_LINK_PHY_TEST_PATTERN:
3814 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3815 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3816 response = intel_dp_autotest_phy_pattern(intel_dp);
3819 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3824 status = drm_dp_dpcd_write(&intel_dp->aux,
3828 DRM_DEBUG_KMS("Could not write test response to sink\n");
3832 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3836 if (intel_dp->is_mst) {
3841 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3845 /* check link status - esi[10] = 0x200c */
3846 if (intel_dp->active_mst_links &&
3847 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3848 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3849 intel_dp_start_link_train(intel_dp);
3850 intel_dp_stop_link_train(intel_dp);
3853 DRM_DEBUG_KMS("got esi %3ph\n", esi);
3854 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3857 for (retry = 0; retry < 3; retry++) {
3859 wret = drm_dp_dpcd_write(&intel_dp->aux,
3860 DP_SINK_COUNT_ESI+1,
3867 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3869 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3878 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3879 intel_dp->is_mst = false;
3880 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3881 /* send a hotplug event */
3882 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3889 intel_dp_check_link_status(struct intel_dp *intel_dp)
3891 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3893 u8 link_status[DP_LINK_STATUS_SIZE];
3895 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3897 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3898 DRM_ERROR("Failed to get link status\n");
3902 if (!intel_encoder->base.crtc)
3905 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3908 /* if link training is requested we should perform it always */
3909 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3910 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3911 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3912 intel_encoder->base.name);
3913 intel_dp_start_link_train(intel_dp);
3914 intel_dp_stop_link_train(intel_dp);
3919 * According to DP spec
3922 * 2. Configure link according to Receiver Capabilities
3923 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3924 * 4. Check link status on receipt of hot-plug interrupt
3926 * intel_dp_short_pulse - handles short pulse interrupts
3927 * when full detection is not required.
3928 * Returns %true if short pulse is handled and full detection
3929 * is NOT required and %false otherwise.
3932 intel_dp_short_pulse(struct intel_dp *intel_dp)
3934 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3936 u8 old_sink_count = intel_dp->sink_count;
3940 * Clearing compliance test variables to allow capturing
3941 * of values for next automated test request.
3943 intel_dp->compliance_test_active = 0;
3944 intel_dp->compliance_test_type = 0;
3945 intel_dp->compliance_test_data = 0;
3948 * Now read the DPCD to see if it's actually running
3949 * If the current value of sink count doesn't match with
3950 * the value that was stored earlier or dpcd read failed
3951 * we need to do full detection
3953 ret = intel_dp_get_dpcd(intel_dp);
3955 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3956 /* No need to proceed if we are going to do full detect */
3960 /* Try to read the source of the interrupt */
3961 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3962 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3963 /* Clear interrupt source */
3964 drm_dp_dpcd_writeb(&intel_dp->aux,
3965 DP_DEVICE_SERVICE_IRQ_VECTOR,
3968 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3969 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3970 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3971 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3974 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3975 intel_dp_check_link_status(intel_dp);
3976 drm_modeset_unlock(&dev->mode_config.connection_mutex);
3981 /* XXX this is probably wrong for multiple downstream ports */
3982 static enum drm_connector_status
3983 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3985 uint8_t *dpcd = intel_dp->dpcd;
3988 if (!intel_dp_get_dpcd(intel_dp))
3989 return connector_status_disconnected;
3991 if (is_edp(intel_dp))
3992 return connector_status_connected;
3994 /* if there's no downstream port, we're done */
3995 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3996 return connector_status_connected;
3998 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3999 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4000 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4002 return intel_dp->sink_count ?
4003 connector_status_connected : connector_status_disconnected;
4006 /* If no HPD, poke DDC gently */
4007 if (drm_probe_ddc(&intel_dp->aux.ddc))
4008 return connector_status_connected;
4010 /* Well we tried, say unknown for unreliable port types */
4011 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4012 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4013 if (type == DP_DS_PORT_TYPE_VGA ||
4014 type == DP_DS_PORT_TYPE_NON_EDID)
4015 return connector_status_unknown;
4017 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4018 DP_DWN_STRM_PORT_TYPE_MASK;
4019 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4020 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4021 return connector_status_unknown;
4024 /* Anything else is out of spec, warn and ignore */
4025 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4026 return connector_status_disconnected;
4029 static enum drm_connector_status
4030 edp_detect(struct intel_dp *intel_dp)
4032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4033 enum drm_connector_status status;
4035 status = intel_panel_detect(dev);
4036 if (status == connector_status_unknown)
4037 status = connector_status_connected;
4042 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4043 struct intel_digital_port *port)
4047 switch (port->port) {
4051 bit = SDE_PORTB_HOTPLUG;
4054 bit = SDE_PORTC_HOTPLUG;
4057 bit = SDE_PORTD_HOTPLUG;
4060 MISSING_CASE(port->port);
4064 return I915_READ(SDEISR) & bit;
4067 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4068 struct intel_digital_port *port)
4072 switch (port->port) {
4076 bit = SDE_PORTB_HOTPLUG_CPT;
4079 bit = SDE_PORTC_HOTPLUG_CPT;
4082 bit = SDE_PORTD_HOTPLUG_CPT;
4085 bit = SDE_PORTE_HOTPLUG_SPT;
4088 MISSING_CASE(port->port);
4092 return I915_READ(SDEISR) & bit;
4095 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4096 struct intel_digital_port *port)
4100 switch (port->port) {
4102 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4105 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4108 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4111 MISSING_CASE(port->port);
4115 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4118 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4119 struct intel_digital_port *port)
4123 switch (port->port) {
4125 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4128 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4131 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4134 MISSING_CASE(port->port);
4138 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4141 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4142 struct intel_digital_port *intel_dig_port)
4144 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4148 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4151 bit = BXT_DE_PORT_HP_DDIA;
4154 bit = BXT_DE_PORT_HP_DDIB;
4157 bit = BXT_DE_PORT_HP_DDIC;
4164 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4168 * intel_digital_port_connected - is the specified port connected?
4169 * @dev_priv: i915 private structure
4170 * @port: the port to test
4172 * Return %true if @port is connected, %false otherwise.
4174 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4175 struct intel_digital_port *port)
4177 if (HAS_PCH_IBX(dev_priv))
4178 return ibx_digital_port_connected(dev_priv, port);
4179 else if (HAS_PCH_SPLIT(dev_priv))
4180 return cpt_digital_port_connected(dev_priv, port);
4181 else if (IS_BROXTON(dev_priv))
4182 return bxt_digital_port_connected(dev_priv, port);
4183 else if (IS_GM45(dev_priv))
4184 return gm45_digital_port_connected(dev_priv, port);
4186 return g4x_digital_port_connected(dev_priv, port);
4189 static struct edid *
4190 intel_dp_get_edid(struct intel_dp *intel_dp)
4192 struct intel_connector *intel_connector = intel_dp->attached_connector;
4194 /* use cached edid if we have one */
4195 if (intel_connector->edid) {
4197 if (IS_ERR(intel_connector->edid))
4200 return drm_edid_duplicate(intel_connector->edid);
4202 return drm_get_edid(&intel_connector->base,
4203 &intel_dp->aux.ddc);
4207 intel_dp_set_edid(struct intel_dp *intel_dp)
4209 struct intel_connector *intel_connector = intel_dp->attached_connector;
4212 intel_dp_unset_edid(intel_dp);
4213 edid = intel_dp_get_edid(intel_dp);
4214 intel_connector->detect_edid = edid;
4216 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4217 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4219 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4223 intel_dp_unset_edid(struct intel_dp *intel_dp)
4225 struct intel_connector *intel_connector = intel_dp->attached_connector;
4227 kfree(intel_connector->detect_edid);
4228 intel_connector->detect_edid = NULL;
4230 intel_dp->has_audio = false;
4234 intel_dp_long_pulse(struct intel_connector *intel_connector)
4236 struct drm_connector *connector = &intel_connector->base;
4237 struct intel_dp *intel_dp = intel_attached_dp(connector);
4238 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4240 struct drm_device *dev = connector->dev;
4241 enum drm_connector_status status;
4242 enum intel_display_power_domain power_domain;
4246 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4247 intel_display_power_get(to_i915(dev), power_domain);
4249 /* Can't disconnect eDP, but you can close the lid... */
4250 if (is_edp(intel_dp))
4251 status = edp_detect(intel_dp);
4252 else if (intel_digital_port_connected(to_i915(dev),
4253 dp_to_dig_port(intel_dp)))
4254 status = intel_dp_detect_dpcd(intel_dp);
4256 status = connector_status_disconnected;
4258 if (status != connector_status_connected) {
4259 intel_dp->compliance_test_active = 0;
4260 intel_dp->compliance_test_type = 0;
4261 intel_dp->compliance_test_data = 0;
4263 if (intel_dp->is_mst) {
4264 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4266 intel_dp->mst_mgr.mst_state);
4267 intel_dp->is_mst = false;
4268 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4275 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4276 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4278 intel_dp_probe_oui(intel_dp);
4280 ret = intel_dp_probe_mst(intel_dp);
4283 * If we are in MST mode then this connector
4284 * won't appear connected or have anything
4287 status = connector_status_disconnected;
4289 } else if (connector->status == connector_status_connected) {
4291 * If display was connected already and is still connected
4292 * check links status, there has been known issues of
4293 * link loss triggerring long pulse!!!!
4295 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4296 intel_dp_check_link_status(intel_dp);
4297 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4302 * Clearing NACK and defer counts to get their exact values
4303 * while reading EDID which are required by Compliance tests
4304 * 4.2.2.4 and 4.2.2.5
4306 intel_dp->aux.i2c_nack_count = 0;
4307 intel_dp->aux.i2c_defer_count = 0;
4309 intel_dp_set_edid(intel_dp);
4311 status = connector_status_connected;
4312 intel_dp->detect_done = true;
4314 /* Try to read the source of the interrupt */
4315 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4316 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4317 /* Clear interrupt source */
4318 drm_dp_dpcd_writeb(&intel_dp->aux,
4319 DP_DEVICE_SERVICE_IRQ_VECTOR,
4322 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4323 intel_dp_handle_test_request(intel_dp);
4324 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4325 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4329 if ((status != connector_status_connected) &&
4330 (intel_dp->is_mst == false))
4331 intel_dp_unset_edid(intel_dp);
4333 intel_display_power_put(to_i915(dev), power_domain);
4337 static enum drm_connector_status
4338 intel_dp_detect(struct drm_connector *connector, bool force)
4340 struct intel_dp *intel_dp = intel_attached_dp(connector);
4341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4342 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4343 struct intel_connector *intel_connector = to_intel_connector(connector);
4345 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4346 connector->base.id, connector->name);
4348 if (intel_dp->is_mst) {
4349 /* MST devices are disconnected from a monitor POV */
4350 intel_dp_unset_edid(intel_dp);
4351 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4352 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4353 return connector_status_disconnected;
4356 /* If full detect is not performed yet, do a full detect */
4357 if (!intel_dp->detect_done)
4358 intel_dp_long_pulse(intel_dp->attached_connector);
4360 intel_dp->detect_done = false;
4362 if (intel_connector->detect_edid)
4363 return connector_status_connected;
4365 return connector_status_disconnected;
4369 intel_dp_force(struct drm_connector *connector)
4371 struct intel_dp *intel_dp = intel_attached_dp(connector);
4372 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4373 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4374 enum intel_display_power_domain power_domain;
4376 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4377 connector->base.id, connector->name);
4378 intel_dp_unset_edid(intel_dp);
4380 if (connector->status != connector_status_connected)
4383 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4384 intel_display_power_get(dev_priv, power_domain);
4386 intel_dp_set_edid(intel_dp);
4388 intel_display_power_put(dev_priv, power_domain);
4390 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4391 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4394 static int intel_dp_get_modes(struct drm_connector *connector)
4396 struct intel_connector *intel_connector = to_intel_connector(connector);
4399 edid = intel_connector->detect_edid;
4401 int ret = intel_connector_update_modes(connector, edid);
4406 /* if eDP has no EDID, fall back to fixed mode */
4407 if (is_edp(intel_attached_dp(connector)) &&
4408 intel_connector->panel.fixed_mode) {
4409 struct drm_display_mode *mode;
4411 mode = drm_mode_duplicate(connector->dev,
4412 intel_connector->panel.fixed_mode);
4414 drm_mode_probed_add(connector, mode);
4423 intel_dp_detect_audio(struct drm_connector *connector)
4425 bool has_audio = false;
4428 edid = to_intel_connector(connector)->detect_edid;
4430 has_audio = drm_detect_monitor_audio(edid);
4436 intel_dp_set_property(struct drm_connector *connector,
4437 struct drm_property *property,
4440 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4441 struct intel_connector *intel_connector = to_intel_connector(connector);
4442 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4443 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4446 ret = drm_object_property_set_value(&connector->base, property, val);
4450 if (property == dev_priv->force_audio_property) {
4454 if (i == intel_dp->force_audio)
4457 intel_dp->force_audio = i;
4459 if (i == HDMI_AUDIO_AUTO)
4460 has_audio = intel_dp_detect_audio(connector);
4462 has_audio = (i == HDMI_AUDIO_ON);
4464 if (has_audio == intel_dp->has_audio)
4467 intel_dp->has_audio = has_audio;
4471 if (property == dev_priv->broadcast_rgb_property) {
4472 bool old_auto = intel_dp->color_range_auto;
4473 bool old_range = intel_dp->limited_color_range;
4476 case INTEL_BROADCAST_RGB_AUTO:
4477 intel_dp->color_range_auto = true;
4479 case INTEL_BROADCAST_RGB_FULL:
4480 intel_dp->color_range_auto = false;
4481 intel_dp->limited_color_range = false;
4483 case INTEL_BROADCAST_RGB_LIMITED:
4484 intel_dp->color_range_auto = false;
4485 intel_dp->limited_color_range = true;
4491 if (old_auto == intel_dp->color_range_auto &&
4492 old_range == intel_dp->limited_color_range)
4498 if (is_edp(intel_dp) &&
4499 property == connector->dev->mode_config.scaling_mode_property) {
4500 if (val == DRM_MODE_SCALE_NONE) {
4501 DRM_DEBUG_KMS("no scaling not supported\n");
4504 if (HAS_GMCH_DISPLAY(dev_priv) &&
4505 val == DRM_MODE_SCALE_CENTER) {
4506 DRM_DEBUG_KMS("centering not supported\n");
4510 if (intel_connector->panel.fitting_mode == val) {
4511 /* the eDP scaling property is not changed */
4514 intel_connector->panel.fitting_mode = val;
4522 if (intel_encoder->base.crtc)
4523 intel_crtc_restore_mode(intel_encoder->base.crtc);
4529 intel_dp_connector_destroy(struct drm_connector *connector)
4531 struct intel_connector *intel_connector = to_intel_connector(connector);
4533 kfree(intel_connector->detect_edid);
4535 if (!IS_ERR_OR_NULL(intel_connector->edid))
4536 kfree(intel_connector->edid);
4538 /* Can't call is_edp() since the encoder may have been destroyed
4540 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4541 intel_panel_fini(&intel_connector->panel);
4543 drm_connector_cleanup(connector);
4547 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4549 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4550 struct intel_dp *intel_dp = &intel_dig_port->dp;
4552 intel_dp_mst_encoder_cleanup(intel_dig_port);
4553 if (is_edp(intel_dp)) {
4554 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4556 * vdd might still be enabled do to the delayed vdd off.
4557 * Make sure vdd is actually turned off here.
4560 edp_panel_vdd_off_sync(intel_dp);
4561 pps_unlock(intel_dp);
4563 if (intel_dp->edp_notifier.notifier_call) {
4564 unregister_reboot_notifier(&intel_dp->edp_notifier);
4565 intel_dp->edp_notifier.notifier_call = NULL;
4568 drm_encoder_cleanup(encoder);
4569 kfree(intel_dig_port);
4572 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4574 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4576 if (!is_edp(intel_dp))
4580 * vdd might still be enabled do to the delayed vdd off.
4581 * Make sure vdd is actually turned off here.
4583 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4585 edp_panel_vdd_off_sync(intel_dp);
4586 pps_unlock(intel_dp);
4589 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4591 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4592 struct drm_device *dev = intel_dig_port->base.base.dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 enum intel_display_power_domain power_domain;
4596 lockdep_assert_held(&dev_priv->pps_mutex);
4598 if (!edp_have_panel_vdd(intel_dp))
4602 * The VDD bit needs a power domain reference, so if the bit is
4603 * already enabled when we boot or resume, grab this reference and
4604 * schedule a vdd off, so we don't hold on to the reference
4607 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4608 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4609 intel_display_power_get(dev_priv, power_domain);
4611 edp_panel_vdd_schedule_off(intel_dp);
4614 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4616 struct intel_dp *intel_dp;
4618 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4621 intel_dp = enc_to_intel_dp(encoder);
4626 * Read out the current power sequencer assignment,
4627 * in case the BIOS did something with it.
4629 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4630 vlv_initial_power_sequencer_setup(intel_dp);
4632 intel_edp_panel_vdd_sanitize(intel_dp);
4634 pps_unlock(intel_dp);
4637 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4638 .dpms = drm_atomic_helper_connector_dpms,
4639 .detect = intel_dp_detect,
4640 .force = intel_dp_force,
4641 .fill_modes = drm_helper_probe_single_connector_modes,
4642 .set_property = intel_dp_set_property,
4643 .atomic_get_property = intel_connector_atomic_get_property,
4644 .destroy = intel_dp_connector_destroy,
4645 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4646 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4649 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4650 .get_modes = intel_dp_get_modes,
4651 .mode_valid = intel_dp_mode_valid,
4654 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4655 .reset = intel_dp_encoder_reset,
4656 .destroy = intel_dp_encoder_destroy,
4660 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4662 struct intel_dp *intel_dp = &intel_dig_port->dp;
4663 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4664 struct drm_device *dev = intel_dig_port->base.base.dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 enum intel_display_power_domain power_domain;
4667 enum irqreturn ret = IRQ_NONE;
4669 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4670 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4671 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4673 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4675 * vdd off can generate a long pulse on eDP which
4676 * would require vdd on to handle it, and thus we
4677 * would end up in an endless cycle of
4678 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4680 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4681 port_name(intel_dig_port->port));
4685 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4686 port_name(intel_dig_port->port),
4687 long_hpd ? "long" : "short");
4689 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4690 intel_display_power_get(dev_priv, power_domain);
4693 intel_dp_long_pulse(intel_dp->attached_connector);
4694 if (intel_dp->is_mst)
4699 if (intel_dp->is_mst) {
4700 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4702 * If we were in MST mode, and device is not
4703 * there, get out of MST mode
4705 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4706 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4707 intel_dp->is_mst = false;
4708 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4714 if (!intel_dp->is_mst) {
4715 if (!intel_dp_short_pulse(intel_dp)) {
4716 intel_dp_long_pulse(intel_dp->attached_connector);
4725 intel_display_power_put(dev_priv, power_domain);
4730 /* check the VBT to see whether the eDP is on another port */
4731 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4736 * eDP not supported on g4x. so bail out early just
4737 * for a bit extra safety in case the VBT is bonkers.
4739 if (INTEL_INFO(dev)->gen < 5)
4745 return intel_bios_is_port_edp(dev_priv, port);
4749 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4751 struct intel_connector *intel_connector = to_intel_connector(connector);
4753 intel_attach_force_audio_property(connector);
4754 intel_attach_broadcast_rgb_property(connector);
4755 intel_dp->color_range_auto = true;
4757 if (is_edp(intel_dp)) {
4758 drm_mode_create_scaling_mode_property(connector->dev);
4759 drm_object_attach_property(
4761 connector->dev->mode_config.scaling_mode_property,
4762 DRM_MODE_SCALE_ASPECT);
4763 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4767 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4769 intel_dp->panel_power_off_time = ktime_get_boottime();
4770 intel_dp->last_power_on = jiffies;
4771 intel_dp->last_backlight_off = jiffies;
4775 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4776 struct intel_dp *intel_dp)
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779 struct edp_power_seq cur, vbt, spec,
4780 *final = &intel_dp->pps_delays;
4781 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4782 struct pps_registers regs;
4784 lockdep_assert_held(&dev_priv->pps_mutex);
4786 /* already initialized? */
4787 if (final->t11_t12 != 0)
4790 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4792 /* Workaround: Need to write PP_CONTROL with the unlock key as
4793 * the very first thing. */
4794 pp_ctl = ironlake_get_pp_control(intel_dp);
4796 pp_on = I915_READ(regs.pp_on);
4797 pp_off = I915_READ(regs.pp_off);
4798 if (!IS_BROXTON(dev)) {
4799 I915_WRITE(regs.pp_ctrl, pp_ctl);
4800 pp_div = I915_READ(regs.pp_div);
4803 /* Pull timing values out of registers */
4804 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4805 PANEL_POWER_UP_DELAY_SHIFT;
4807 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4808 PANEL_LIGHT_ON_DELAY_SHIFT;
4810 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4811 PANEL_LIGHT_OFF_DELAY_SHIFT;
4813 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4814 PANEL_POWER_DOWN_DELAY_SHIFT;
4816 if (IS_BROXTON(dev)) {
4817 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4818 BXT_POWER_CYCLE_DELAY_SHIFT;
4820 cur.t11_t12 = (tmp - 1) * 1000;
4824 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4825 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4828 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4829 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4831 vbt = dev_priv->vbt.edp.pps;
4833 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4834 * our hw here, which are all in 100usec. */
4835 spec.t1_t3 = 210 * 10;
4836 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4837 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4838 spec.t10 = 500 * 10;
4839 /* This one is special and actually in units of 100ms, but zero
4840 * based in the hw (so we need to add 100 ms). But the sw vbt
4841 * table multiplies it with 1000 to make it in units of 100usec,
4843 spec.t11_t12 = (510 + 100) * 10;
4845 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4846 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4848 /* Use the max of the register settings and vbt. If both are
4849 * unset, fall back to the spec limits. */
4850 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4852 max(cur.field, vbt.field))
4853 assign_final(t1_t3);
4857 assign_final(t11_t12);
4860 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4861 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4862 intel_dp->backlight_on_delay = get_delay(t8);
4863 intel_dp->backlight_off_delay = get_delay(t9);
4864 intel_dp->panel_power_down_delay = get_delay(t10);
4865 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4868 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4869 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4870 intel_dp->panel_power_cycle_delay);
4872 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4873 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4877 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4878 struct intel_dp *intel_dp)
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 u32 pp_on, pp_off, pp_div, port_sel = 0;
4882 int div = dev_priv->rawclk_freq / 1000;
4883 struct pps_registers regs;
4884 enum port port = dp_to_dig_port(intel_dp)->port;
4885 const struct edp_power_seq *seq = &intel_dp->pps_delays;
4887 lockdep_assert_held(&dev_priv->pps_mutex);
4889 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4892 * And finally store the new values in the power sequencer. The
4893 * backlight delays are set to 1 because we do manual waits on them. For
4894 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4895 * we'll end up waiting for the backlight off delay twice: once when we
4896 * do the manual sleep, and once when we disable the panel and wait for
4897 * the PP_STATUS bit to become zero.
4899 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4900 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4901 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4902 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4903 /* Compute the divisor for the pp clock, simply match the Bspec
4905 if (IS_BROXTON(dev)) {
4906 pp_div = I915_READ(regs.pp_ctrl);
4907 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4908 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4909 << BXT_POWER_CYCLE_DELAY_SHIFT);
4911 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4912 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4913 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4916 /* Haswell doesn't have any port selection bits for the panel
4917 * power sequencer any more. */
4918 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4919 port_sel = PANEL_PORT_SELECT_VLV(port);
4920 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4922 port_sel = PANEL_PORT_SELECT_DPA;
4924 port_sel = PANEL_PORT_SELECT_DPD;
4929 I915_WRITE(regs.pp_on, pp_on);
4930 I915_WRITE(regs.pp_off, pp_off);
4931 if (IS_BROXTON(dev))
4932 I915_WRITE(regs.pp_ctrl, pp_div);
4934 I915_WRITE(regs.pp_div, pp_div);
4936 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4937 I915_READ(regs.pp_on),
4938 I915_READ(regs.pp_off),
4940 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
4941 I915_READ(regs.pp_div));
4945 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4947 * @refresh_rate: RR to be programmed
4949 * This function gets called when refresh rate (RR) has to be changed from
4950 * one frequency to another. Switches can be between high and low RR
4951 * supported by the panel or to any other RR based on media playback (in
4952 * this case, RR value needs to be passed from user space).
4954 * The caller of this function needs to take a lock on dev_priv->drrs.
4956 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4958 struct drm_i915_private *dev_priv = dev->dev_private;
4959 struct intel_encoder *encoder;
4960 struct intel_digital_port *dig_port = NULL;
4961 struct intel_dp *intel_dp = dev_priv->drrs.dp;
4962 struct intel_crtc_state *config = NULL;
4963 struct intel_crtc *intel_crtc = NULL;
4964 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4966 if (refresh_rate <= 0) {
4967 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4971 if (intel_dp == NULL) {
4972 DRM_DEBUG_KMS("DRRS not supported.\n");
4977 * FIXME: This needs proper synchronization with psr state for some
4978 * platforms that cannot have PSR and DRRS enabled at the same time.
4981 dig_port = dp_to_dig_port(intel_dp);
4982 encoder = &dig_port->base;
4983 intel_crtc = to_intel_crtc(encoder->base.crtc);
4986 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4990 config = intel_crtc->config;
4992 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4993 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4997 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4999 index = DRRS_LOW_RR;
5001 if (index == dev_priv->drrs.refresh_rate_type) {
5003 "DRRS requested for previously set RR...ignoring\n");
5007 if (!intel_crtc->active) {
5008 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5012 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5015 intel_dp_set_m_n(intel_crtc, M1_N1);
5018 intel_dp_set_m_n(intel_crtc, M2_N2);
5022 DRM_ERROR("Unsupported refreshrate type\n");
5024 } else if (INTEL_INFO(dev)->gen > 6) {
5025 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5028 val = I915_READ(reg);
5029 if (index > DRRS_HIGH_RR) {
5030 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5031 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5033 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5035 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5036 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5038 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5040 I915_WRITE(reg, val);
5043 dev_priv->drrs.refresh_rate_type = index;
5045 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5049 * intel_edp_drrs_enable - init drrs struct if supported
5050 * @intel_dp: DP struct
5052 * Initializes frontbuffer_bits and drrs.dp
5054 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5059 struct drm_crtc *crtc = dig_port->base.base.crtc;
5060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062 if (!intel_crtc->config->has_drrs) {
5063 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5067 mutex_lock(&dev_priv->drrs.mutex);
5068 if (WARN_ON(dev_priv->drrs.dp)) {
5069 DRM_ERROR("DRRS already enabled\n");
5073 dev_priv->drrs.busy_frontbuffer_bits = 0;
5075 dev_priv->drrs.dp = intel_dp;
5078 mutex_unlock(&dev_priv->drrs.mutex);
5082 * intel_edp_drrs_disable - Disable DRRS
5083 * @intel_dp: DP struct
5086 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5088 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5089 struct drm_i915_private *dev_priv = dev->dev_private;
5090 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5091 struct drm_crtc *crtc = dig_port->base.base.crtc;
5092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5094 if (!intel_crtc->config->has_drrs)
5097 mutex_lock(&dev_priv->drrs.mutex);
5098 if (!dev_priv->drrs.dp) {
5099 mutex_unlock(&dev_priv->drrs.mutex);
5103 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5104 intel_dp_set_drrs_state(dev_priv->dev,
5105 intel_dp->attached_connector->panel.
5106 fixed_mode->vrefresh);
5108 dev_priv->drrs.dp = NULL;
5109 mutex_unlock(&dev_priv->drrs.mutex);
5111 cancel_delayed_work_sync(&dev_priv->drrs.work);
5114 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5116 struct drm_i915_private *dev_priv =
5117 container_of(work, typeof(*dev_priv), drrs.work.work);
5118 struct intel_dp *intel_dp;
5120 mutex_lock(&dev_priv->drrs.mutex);
5122 intel_dp = dev_priv->drrs.dp;
5128 * The delayed work can race with an invalidate hence we need to
5132 if (dev_priv->drrs.busy_frontbuffer_bits)
5135 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5136 intel_dp_set_drrs_state(dev_priv->dev,
5137 intel_dp->attached_connector->panel.
5138 downclock_mode->vrefresh);
5141 mutex_unlock(&dev_priv->drrs.mutex);
5145 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5147 * @frontbuffer_bits: frontbuffer plane tracking bits
5149 * This function gets called everytime rendering on the given planes start.
5150 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5152 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5154 void intel_edp_drrs_invalidate(struct drm_device *dev,
5155 unsigned frontbuffer_bits)
5157 struct drm_i915_private *dev_priv = dev->dev_private;
5158 struct drm_crtc *crtc;
5161 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5164 cancel_delayed_work(&dev_priv->drrs.work);
5166 mutex_lock(&dev_priv->drrs.mutex);
5167 if (!dev_priv->drrs.dp) {
5168 mutex_unlock(&dev_priv->drrs.mutex);
5172 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5173 pipe = to_intel_crtc(crtc)->pipe;
5175 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5176 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5178 /* invalidate means busy screen hence upclock */
5179 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5180 intel_dp_set_drrs_state(dev_priv->dev,
5181 dev_priv->drrs.dp->attached_connector->panel.
5182 fixed_mode->vrefresh);
5184 mutex_unlock(&dev_priv->drrs.mutex);
5188 * intel_edp_drrs_flush - Restart Idleness DRRS
5190 * @frontbuffer_bits: frontbuffer plane tracking bits
5192 * This function gets called every time rendering on the given planes has
5193 * completed or flip on a crtc is completed. So DRRS should be upclocked
5194 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5195 * if no other planes are dirty.
5197 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5199 void intel_edp_drrs_flush(struct drm_device *dev,
5200 unsigned frontbuffer_bits)
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct drm_crtc *crtc;
5206 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5209 cancel_delayed_work(&dev_priv->drrs.work);
5211 mutex_lock(&dev_priv->drrs.mutex);
5212 if (!dev_priv->drrs.dp) {
5213 mutex_unlock(&dev_priv->drrs.mutex);
5217 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5218 pipe = to_intel_crtc(crtc)->pipe;
5220 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5221 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5223 /* flush means busy screen hence upclock */
5224 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5225 intel_dp_set_drrs_state(dev_priv->dev,
5226 dev_priv->drrs.dp->attached_connector->panel.
5227 fixed_mode->vrefresh);
5230 * flush also means no more activity hence schedule downclock, if all
5231 * other fbs are quiescent too
5233 if (!dev_priv->drrs.busy_frontbuffer_bits)
5234 schedule_delayed_work(&dev_priv->drrs.work,
5235 msecs_to_jiffies(1000));
5236 mutex_unlock(&dev_priv->drrs.mutex);
5240 * DOC: Display Refresh Rate Switching (DRRS)
5242 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5243 * which enables swtching between low and high refresh rates,
5244 * dynamically, based on the usage scenario. This feature is applicable
5245 * for internal panels.
5247 * Indication that the panel supports DRRS is given by the panel EDID, which
5248 * would list multiple refresh rates for one resolution.
5250 * DRRS is of 2 types - static and seamless.
5251 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5252 * (may appear as a blink on screen) and is used in dock-undock scenario.
5253 * Seamless DRRS involves changing RR without any visual effect to the user
5254 * and can be used during normal system usage. This is done by programming
5255 * certain registers.
5257 * Support for static/seamless DRRS may be indicated in the VBT based on
5258 * inputs from the panel spec.
5260 * DRRS saves power by switching to low RR based on usage scenarios.
5262 * The implementation is based on frontbuffer tracking implementation. When
5263 * there is a disturbance on the screen triggered by user activity or a periodic
5264 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5265 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5268 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5269 * and intel_edp_drrs_flush() are called.
5271 * DRRS can be further extended to support other internal panels and also
5272 * the scenario of video playback wherein RR is set based on the rate
5273 * requested by userspace.
5277 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5278 * @intel_connector: eDP connector
5279 * @fixed_mode: preferred mode of panel
5281 * This function is called only once at driver load to initialize basic
5285 * Downclock mode if panel supports it, else return NULL.
5286 * DRRS support is determined by the presence of downclock mode (apart
5287 * from VBT setting).
5289 static struct drm_display_mode *
5290 intel_dp_drrs_init(struct intel_connector *intel_connector,
5291 struct drm_display_mode *fixed_mode)
5293 struct drm_connector *connector = &intel_connector->base;
5294 struct drm_device *dev = connector->dev;
5295 struct drm_i915_private *dev_priv = dev->dev_private;
5296 struct drm_display_mode *downclock_mode = NULL;
5298 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5299 mutex_init(&dev_priv->drrs.mutex);
5301 if (INTEL_INFO(dev)->gen <= 6) {
5302 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5306 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5307 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5311 downclock_mode = intel_find_panel_downclock
5312 (dev, fixed_mode, connector);
5314 if (!downclock_mode) {
5315 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5319 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5321 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5322 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5323 return downclock_mode;
5326 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5327 struct intel_connector *intel_connector)
5329 struct drm_connector *connector = &intel_connector->base;
5330 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5331 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5332 struct drm_device *dev = intel_encoder->base.dev;
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 struct drm_display_mode *fixed_mode = NULL;
5335 struct drm_display_mode *downclock_mode = NULL;
5337 struct drm_display_mode *scan;
5339 enum pipe pipe = INVALID_PIPE;
5341 if (!is_edp(intel_dp))
5345 * On IBX/CPT we may get here with LVDS already registered. Since the
5346 * driver uses the only internal power sequencer available for both
5347 * eDP and LVDS bail out early in this case to prevent interfering
5348 * with an already powered-on LVDS power sequencer.
5350 if (intel_get_lvds_encoder(dev)) {
5351 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5352 DRM_INFO("LVDS was detected, not registering eDP\n");
5359 intel_dp_init_panel_power_timestamps(intel_dp);
5361 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5362 vlv_initial_power_sequencer_setup(intel_dp);
5364 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5365 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5368 intel_edp_panel_vdd_sanitize(intel_dp);
5370 pps_unlock(intel_dp);
5372 /* Cache DPCD and EDID for edp. */
5373 has_dpcd = intel_dp_get_dpcd(intel_dp);
5376 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5377 dev_priv->no_aux_handshake =
5378 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5379 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5381 /* if this fails, presume the device is a ghost */
5382 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5386 mutex_lock(&dev->mode_config.mutex);
5387 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5389 if (drm_add_edid_modes(connector, edid)) {
5390 drm_mode_connector_update_edid_property(connector,
5392 drm_edid_to_eld(connector, edid);
5395 edid = ERR_PTR(-EINVAL);
5398 edid = ERR_PTR(-ENOENT);
5400 intel_connector->edid = edid;
5402 /* prefer fixed mode from EDID if available */
5403 list_for_each_entry(scan, &connector->probed_modes, head) {
5404 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5405 fixed_mode = drm_mode_duplicate(dev, scan);
5406 downclock_mode = intel_dp_drrs_init(
5407 intel_connector, fixed_mode);
5412 /* fallback to VBT if available for eDP */
5413 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5414 fixed_mode = drm_mode_duplicate(dev,
5415 dev_priv->vbt.lfp_lvds_vbt_mode);
5417 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5418 connector->display_info.width_mm = fixed_mode->width_mm;
5419 connector->display_info.height_mm = fixed_mode->height_mm;
5422 mutex_unlock(&dev->mode_config.mutex);
5424 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5425 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5426 register_reboot_notifier(&intel_dp->edp_notifier);
5429 * Figure out the current pipe for the initial backlight setup.
5430 * If the current pipe isn't valid, try the PPS pipe, and if that
5431 * fails just assume pipe A.
5433 if (IS_CHERRYVIEW(dev))
5434 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5436 pipe = PORT_TO_PIPE(intel_dp->DP);
5438 if (pipe != PIPE_A && pipe != PIPE_B)
5439 pipe = intel_dp->pps_pipe;
5441 if (pipe != PIPE_A && pipe != PIPE_B)
5444 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5448 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5449 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5450 intel_panel_setup_backlight(connector, pipe);
5455 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5457 * vdd might still be enabled do to the delayed vdd off.
5458 * Make sure vdd is actually turned off here.
5461 edp_panel_vdd_off_sync(intel_dp);
5462 pps_unlock(intel_dp);
5468 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5469 struct intel_connector *intel_connector)
5471 struct drm_connector *connector = &intel_connector->base;
5472 struct intel_dp *intel_dp = &intel_dig_port->dp;
5473 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5474 struct drm_device *dev = intel_encoder->base.dev;
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 enum port port = intel_dig_port->port;
5479 if (WARN(intel_dig_port->max_lanes < 1,
5480 "Not enough lanes (%d) for DP on port %c\n",
5481 intel_dig_port->max_lanes, port_name(port)))
5484 intel_dp->pps_pipe = INVALID_PIPE;
5486 /* intel_dp vfuncs */
5487 if (INTEL_INFO(dev)->gen >= 9)
5488 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5489 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5490 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5491 else if (HAS_PCH_SPLIT(dev))
5492 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5494 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5496 if (INTEL_INFO(dev)->gen >= 9)
5497 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5499 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5502 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5504 /* Preserve the current hw state. */
5505 intel_dp->DP = I915_READ(intel_dp->output_reg);
5506 intel_dp->attached_connector = intel_connector;
5508 if (intel_dp_is_edp(dev, port))
5509 type = DRM_MODE_CONNECTOR_eDP;
5511 type = DRM_MODE_CONNECTOR_DisplayPort;
5514 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5515 * for DP the encoder type can be set by the caller to
5516 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5518 if (type == DRM_MODE_CONNECTOR_eDP)
5519 intel_encoder->type = INTEL_OUTPUT_EDP;
5521 /* eDP only on port B and/or C on vlv/chv */
5522 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5523 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5526 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5527 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5530 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5531 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5533 connector->interlace_allowed = true;
5534 connector->doublescan_allowed = 0;
5536 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5537 edp_panel_vdd_work);
5539 intel_connector_attach_encoder(intel_connector, intel_encoder);
5540 drm_connector_register(connector);
5543 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5545 intel_connector->get_hw_state = intel_connector_get_hw_state;
5546 intel_connector->unregister = intel_dp_connector_unregister;
5548 /* Set up the hotplug pin. */
5551 intel_encoder->hpd_pin = HPD_PORT_A;
5554 intel_encoder->hpd_pin = HPD_PORT_B;
5555 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5556 intel_encoder->hpd_pin = HPD_PORT_A;
5559 intel_encoder->hpd_pin = HPD_PORT_C;
5562 intel_encoder->hpd_pin = HPD_PORT_D;
5565 intel_encoder->hpd_pin = HPD_PORT_E;
5571 ret = intel_dp_aux_init(intel_dp, intel_connector);
5575 /* init MST on ports that can support it */
5576 if (HAS_DP_MST(dev) &&
5577 (port == PORT_B || port == PORT_C || port == PORT_D))
5578 intel_dp_mst_encoder_init(intel_dig_port,
5579 intel_connector->base.base.id);
5581 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5582 intel_dp_aux_fini(intel_dp);
5583 intel_dp_mst_encoder_cleanup(intel_dig_port);
5587 intel_dp_add_properties(intel_dp, connector);
5589 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5590 * 0xd. Failure to do so will result in spurious interrupts being
5591 * generated on the port when a cable is not attached.
5593 if (IS_G4X(dev) && !IS_GM45(dev)) {
5594 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5595 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5598 i915_debugfs_connector_add(connector);
5603 drm_connector_unregister(connector);
5604 drm_connector_cleanup(connector);
5609 bool intel_dp_init(struct drm_device *dev,
5610 i915_reg_t output_reg,
5613 struct drm_i915_private *dev_priv = dev->dev_private;
5614 struct intel_digital_port *intel_dig_port;
5615 struct intel_encoder *intel_encoder;
5616 struct drm_encoder *encoder;
5617 struct intel_connector *intel_connector;
5619 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5620 if (!intel_dig_port)
5623 intel_connector = intel_connector_alloc();
5624 if (!intel_connector)
5625 goto err_connector_alloc;
5627 intel_encoder = &intel_dig_port->base;
5628 encoder = &intel_encoder->base;
5630 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5631 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5632 goto err_encoder_init;
5634 intel_encoder->compute_config = intel_dp_compute_config;
5635 intel_encoder->disable = intel_disable_dp;
5636 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5637 intel_encoder->get_config = intel_dp_get_config;
5638 intel_encoder->suspend = intel_dp_encoder_suspend;
5639 if (IS_CHERRYVIEW(dev)) {
5640 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5641 intel_encoder->pre_enable = chv_pre_enable_dp;
5642 intel_encoder->enable = vlv_enable_dp;
5643 intel_encoder->post_disable = chv_post_disable_dp;
5644 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5645 } else if (IS_VALLEYVIEW(dev)) {
5646 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5647 intel_encoder->pre_enable = vlv_pre_enable_dp;
5648 intel_encoder->enable = vlv_enable_dp;
5649 intel_encoder->post_disable = vlv_post_disable_dp;
5651 intel_encoder->pre_enable = g4x_pre_enable_dp;
5652 intel_encoder->enable = g4x_enable_dp;
5653 if (INTEL_INFO(dev)->gen >= 5)
5654 intel_encoder->post_disable = ilk_post_disable_dp;
5657 intel_dig_port->port = port;
5658 intel_dig_port->dp.output_reg = output_reg;
5659 intel_dig_port->max_lanes = 4;
5661 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5662 if (IS_CHERRYVIEW(dev)) {
5664 intel_encoder->crtc_mask = 1 << 2;
5666 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5668 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5670 intel_encoder->cloneable = 0;
5672 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5673 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5675 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5676 goto err_init_connector;
5681 drm_encoder_cleanup(encoder);
5683 kfree(intel_connector);
5684 err_connector_alloc:
5685 kfree(intel_dig_port);
5689 void intel_dp_mst_suspend(struct drm_device *dev)
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5695 for (i = 0; i < I915_MAX_PORTS; i++) {
5696 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5697 if (!intel_dig_port)
5700 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5701 if (!intel_dig_port->dp.can_mst)
5703 if (intel_dig_port->dp.is_mst)
5704 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5709 void intel_dp_mst_resume(struct drm_device *dev)
5711 struct drm_i915_private *dev_priv = dev->dev_private;
5714 for (i = 0; i < I915_MAX_PORTS; i++) {
5715 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5716 if (!intel_dig_port)
5718 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5721 if (!intel_dig_port->dp.can_mst)
5724 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5726 intel_dp_check_mst_status(&intel_dig_port->dp);