2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp *intel_dp)
65 return intel_dp->is_pch_edp;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp *intel_dp)
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
83 return intel_dig_port->base.base.dev;
86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
100 struct intel_dp *intel_dp;
105 intel_dp = enc_to_intel_dp(encoder);
107 return is_pch_edp(intel_dp);
110 static void intel_dp_link_down(struct intel_dp *intel_dp);
113 intel_dp_max_link_bw(struct intel_dp *intel_dp)
115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
122 max_link_bw = DP_LINK_BW_1_62;
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
134 * 270000 * 1 * 8 / 10 == 216000
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
146 intel_dp_link_required(int pixel_clock, int bpp)
148 return (pixel_clock * bpp + 9) / 10;
152 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
154 return (max_link_clock * max_lanes * 8) / 10;
158 intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
161 struct intel_dp *intel_dp = intel_attached_dp(connector);
162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
171 if (mode->vdisplay > fixed_mode->vdisplay)
174 target_clock = fixed_mode->clock;
177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
183 if (mode_rate > max_rate)
184 return MODE_CLOCK_HIGH;
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
196 pack_aux(uint8_t *src, int src_bytes)
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
209 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
218 /* hrawclock is 1/4 the FSB frequency */
220 intel_hrawclk(struct drm_device *dev)
222 struct drm_i915_private *dev_priv = dev->dev_private;
225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
239 case CLKCFG_FSB_1067:
241 case CLKCFG_FSB_1333:
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
252 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
255 struct drm_i915_private *dev_priv = dev->dev_private;
258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
262 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
265 struct drm_i915_private *dev_priv = dev->dev_private;
268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
273 intel_dp_check_edp(struct intel_dp *intel_dp)
275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
276 struct drm_i915_private *dev_priv = dev->dev_private;
277 u32 pp_stat_reg, pp_ctrl_reg;
279 if (!is_edp(intel_dp))
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
294 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
308 done = wait_for_atomic(C, 10) == 0;
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
318 intel_dp_aux_ch(struct intel_dp *intel_dp,
319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
326 uint32_t ch_data = ch_ctl + 4;
327 int i, ret, recv_bytes;
329 uint32_t aux_clock_divider;
331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
339 intel_dp_check_edp(intel_dp);
340 /* The clock divider is based off the hrawclk,
341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
344 * Note that PCH attached eDP panels should use a 125MHz input
347 if (is_cpu_edp(intel_dp)) {
349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
356 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider = 74;
359 } else if (HAS_PCH_SPLIT(dev)) {
360 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
362 aux_clock_divider = intel_hrawclk(dev) / 2;
370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
372 status = I915_READ_NOTRACE(ch_ctl);
373 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
388 for (i = 0; i < send_bytes; i += 4)
389 I915_WRITE(ch_data + i,
390 pack_aux(send + i, send_bytes - i));
392 /* Send the command and wait for it to complete */
394 DP_AUX_CH_CTL_SEND_BUSY |
395 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
396 DP_AUX_CH_CTL_TIME_OUT_400us |
397 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
398 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
399 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR |
402 DP_AUX_CH_CTL_RECEIVE_ERROR);
404 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
406 /* Clear done status and any errors */
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
413 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR))
416 if (status & DP_AUX_CH_CTL_DONE)
420 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
429 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
437 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
443 /* Unload any bytes sent back from the other side */
444 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
446 if (recv_bytes > recv_size)
447 recv_bytes = recv_size;
449 for (i = 0; i < recv_bytes; i += 4)
450 unpack_aux(I915_READ(ch_data + i),
451 recv + i, recv_bytes - i);
455 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
460 /* Write data to the aux channel in native mode */
462 intel_dp_aux_native_write(struct intel_dp *intel_dp,
463 uint16_t address, uint8_t *send, int send_bytes)
470 intel_dp_check_edp(intel_dp);
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
475 msg[2] = address & 0xff;
476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 /* Write a single byte to the aux channel in native mode */
495 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
496 uint16_t address, uint8_t byte)
498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
501 /* read bytes from a native aux channel */
503 intel_dp_aux_native_read(struct intel_dp *intel_dp,
504 uint16_t address, uint8_t *recv, int recv_bytes)
513 intel_dp_check_edp(intel_dp);
514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
520 reply_bytes = recv_bytes + 1;
523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
542 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
546 struct intel_dp *intel_dp = container_of(adapter,
549 uint16_t address = algo_data->address;
557 intel_dp_check_edp(intel_dp);
558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
562 msg[0] = AUX_I2C_WRITE << 4;
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
567 msg[1] = address >> 8;
588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
606 case AUX_NATIVE_REPLY_DEFER:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
622 DRM_DEBUG_KMS("aux_i2c nack\n");
624 case AUX_I2C_REPLY_DEFER:
625 DRM_DEBUG_KMS("aux_i2c defer\n");
629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
634 DRM_ERROR("too many retries, giving up\n");
639 intel_dp_i2c_init(struct intel_dp *intel_dp,
640 struct intel_connector *intel_connector, const char *name)
644 DRM_DEBUG_KMS("i2c_init %s\n", name);
645 intel_dp->algo.running = false;
646 intel_dp->algo.address = 0;
647 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
649 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
650 intel_dp->adapter.owner = THIS_MODULE;
651 intel_dp->adapter.class = I2C_CLASS_DDC;
652 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
653 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
654 intel_dp->adapter.algo_data = &intel_dp->algo;
655 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
657 ironlake_edp_panel_vdd_on(intel_dp);
658 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
659 ironlake_edp_panel_vdd_off(intel_dp, false);
664 intel_dp_set_clock(struct intel_encoder *encoder,
665 struct intel_crtc_config *pipe_config, int link_bw)
667 struct drm_device *dev = encoder->base.dev;
670 if (link_bw == DP_LINK_BW_1_62) {
671 pipe_config->dpll.p1 = 2;
672 pipe_config->dpll.p2 = 10;
673 pipe_config->dpll.n = 2;
674 pipe_config->dpll.m1 = 23;
675 pipe_config->dpll.m2 = 8;
677 pipe_config->dpll.p1 = 1;
678 pipe_config->dpll.p2 = 10;
679 pipe_config->dpll.n = 1;
680 pipe_config->dpll.m1 = 14;
681 pipe_config->dpll.m2 = 2;
683 pipe_config->clock_set = true;
684 } else if (IS_HASWELL(dev)) {
685 /* Haswell has special-purpose DP DDI clocks. */
686 } else if (HAS_PCH_SPLIT(dev)) {
687 if (link_bw == DP_LINK_BW_1_62) {
688 pipe_config->dpll.n = 1;
689 pipe_config->dpll.p1 = 2;
690 pipe_config->dpll.p2 = 10;
691 pipe_config->dpll.m1 = 12;
692 pipe_config->dpll.m2 = 9;
694 pipe_config->dpll.n = 2;
695 pipe_config->dpll.p1 = 1;
696 pipe_config->dpll.p2 = 10;
697 pipe_config->dpll.m1 = 14;
698 pipe_config->dpll.m2 = 8;
700 pipe_config->clock_set = true;
701 } else if (IS_VALLEYVIEW(dev)) {
702 /* FIXME: Need to figure out optimized DP clocks for vlv. */
707 intel_dp_compute_config(struct intel_encoder *encoder,
708 struct intel_crtc_config *pipe_config)
710 struct drm_device *dev = encoder->base.dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
713 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
714 struct intel_crtc *intel_crtc = encoder->new_crtc;
715 struct intel_connector *intel_connector = intel_dp->attached_connector;
716 int lane_count, clock;
717 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
718 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
720 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
721 int target_clock, link_avail, link_clock;
723 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
724 pipe_config->has_pch_encoder = true;
726 pipe_config->has_dp_encoder = true;
728 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
729 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
731 if (!HAS_PCH_SPLIT(dev))
732 intel_gmch_panel_fitting(intel_crtc, pipe_config,
733 intel_connector->panel.fitting_mode);
735 intel_pch_panel_fitting(intel_crtc, pipe_config,
736 intel_connector->panel.fitting_mode);
738 /* We need to take the panel's fixed mode into account. */
739 target_clock = adjusted_mode->clock;
741 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
744 DRM_DEBUG_KMS("DP link computation with max lane count %i "
745 "max bw %02x pixel clock %iKHz\n",
746 max_lane_count, bws[max_clock], adjusted_mode->clock);
748 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
750 bpp = pipe_config->pipe_bpp;
753 * eDP panels are really fickle, try to enfore the bpp the firmware
754 * recomments. This means we'll up-dither 16bpp framebuffers on
757 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
758 DRM_DEBUG_KMS("forcing bpp for eDP panel to BIOS-provided %i\n",
760 bpp = dev_priv->edp.bpp;
763 for (; bpp >= 6*3; bpp -= 2*3) {
764 mode_rate = intel_dp_link_required(target_clock, bpp);
766 for (clock = 0; clock <= max_clock; clock++) {
767 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
768 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
769 link_avail = intel_dp_max_data_rate(link_clock,
772 if (mode_rate <= link_avail) {
782 if (intel_dp->color_range_auto) {
785 * CEA-861-E - 5.1 Default Encoding Parameters
786 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
788 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
789 intel_dp->color_range = DP_COLOR_RANGE_16_235;
791 intel_dp->color_range = 0;
794 if (intel_dp->color_range)
795 pipe_config->limited_color_range = true;
797 intel_dp->link_bw = bws[clock];
798 intel_dp->lane_count = lane_count;
799 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
800 pipe_config->pixel_target_clock = target_clock;
802 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
803 intel_dp->link_bw, intel_dp->lane_count,
804 adjusted_mode->clock, bpp);
805 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
806 mode_rate, link_avail);
808 intel_link_compute_m_n(bpp, lane_count,
809 target_clock, adjusted_mode->clock,
810 &pipe_config->dp_m_n);
812 pipe_config->pipe_bpp = bpp;
814 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
819 void intel_dp_init_link_config(struct intel_dp *intel_dp)
821 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
822 intel_dp->link_configuration[0] = intel_dp->link_bw;
823 intel_dp->link_configuration[1] = intel_dp->lane_count;
824 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
826 * Check for DPCD version > 1.1 and enhanced framing support
828 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
829 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
830 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
834 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
836 struct drm_device *dev = crtc->dev;
837 struct drm_i915_private *dev_priv = dev->dev_private;
840 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
841 dpa_ctl = I915_READ(DP_A);
842 dpa_ctl &= ~DP_PLL_FREQ_MASK;
844 if (clock < 200000) {
845 /* For a long time we've carried around a ILK-DevA w/a for the
846 * 160MHz clock. If we're really unlucky, it's still required.
848 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
849 dpa_ctl |= DP_PLL_FREQ_160MHZ;
851 dpa_ctl |= DP_PLL_FREQ_270MHZ;
854 I915_WRITE(DP_A, dpa_ctl);
861 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
862 struct drm_display_mode *adjusted_mode)
864 struct drm_device *dev = encoder->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
867 struct drm_crtc *crtc = encoder->crtc;
868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
871 * There are four kinds of DP registers:
878 * IBX PCH and CPU are the same for almost everything,
879 * except that the CPU DP PLL is configured in this
882 * CPT PCH is quite different, having many bits moved
883 * to the TRANS_DP_CTL register instead. That
884 * configuration happens (oddly) in ironlake_pch_enable
887 /* Preserve the BIOS-computed detected bit. This is
888 * supposed to be read-only.
890 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
892 /* Handle DP bits in common between all three register formats */
893 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
894 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
896 if (intel_dp->has_audio) {
897 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
898 pipe_name(intel_crtc->pipe));
899 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
900 intel_write_eld(encoder, adjusted_mode);
903 intel_dp_init_link_config(intel_dp);
905 /* Split out the IBX/CPU vs CPT settings */
907 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
908 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
909 intel_dp->DP |= DP_SYNC_HS_HIGH;
910 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
911 intel_dp->DP |= DP_SYNC_VS_HIGH;
912 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
914 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
915 intel_dp->DP |= DP_ENHANCED_FRAMING;
917 intel_dp->DP |= intel_crtc->pipe << 29;
919 /* don't miss out required setting for eDP */
920 if (adjusted_mode->clock < 200000)
921 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
923 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
924 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
925 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
926 intel_dp->DP |= intel_dp->color_range;
928 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
929 intel_dp->DP |= DP_SYNC_HS_HIGH;
930 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
931 intel_dp->DP |= DP_SYNC_VS_HIGH;
932 intel_dp->DP |= DP_LINK_TRAIN_OFF;
934 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
935 intel_dp->DP |= DP_ENHANCED_FRAMING;
937 if (intel_crtc->pipe == 1)
938 intel_dp->DP |= DP_PIPEB_SELECT;
940 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
941 /* don't miss out required setting for eDP */
942 if (adjusted_mode->clock < 200000)
943 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
945 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
948 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
951 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
952 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
955 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
956 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
958 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
959 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
961 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
962 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
964 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
968 struct drm_device *dev = intel_dp_to_dev(intel_dp);
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 u32 pp_stat_reg, pp_ctrl_reg;
972 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
973 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
975 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
977 I915_READ(pp_stat_reg),
978 I915_READ(pp_ctrl_reg));
980 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
981 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
982 I915_READ(pp_stat_reg),
983 I915_READ(pp_ctrl_reg));
987 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
989 DRM_DEBUG_KMS("Wait for panel power on\n");
990 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
993 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
995 DRM_DEBUG_KMS("Wait for panel power off time\n");
996 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
999 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1001 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1002 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1006 /* Read the current pp_control value, unlocking the register if it
1010 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1012 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1017 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1018 control = I915_READ(pp_ctrl_reg);
1020 control &= ~PANEL_UNLOCK_MASK;
1021 control |= PANEL_UNLOCK_REGS;
1025 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1027 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1028 struct drm_i915_private *dev_priv = dev->dev_private;
1030 u32 pp_stat_reg, pp_ctrl_reg;
1032 if (!is_edp(intel_dp))
1034 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1036 WARN(intel_dp->want_panel_vdd,
1037 "eDP VDD already requested on\n");
1039 intel_dp->want_panel_vdd = true;
1041 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1042 DRM_DEBUG_KMS("eDP VDD already on\n");
1046 if (!ironlake_edp_have_panel_power(intel_dp))
1047 ironlake_wait_panel_power_cycle(intel_dp);
1049 pp = ironlake_get_pp_control(intel_dp);
1050 pp |= EDP_FORCE_VDD;
1052 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1053 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1055 I915_WRITE(pp_ctrl_reg, pp);
1056 POSTING_READ(pp_ctrl_reg);
1057 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1058 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1060 * If the panel wasn't on, delay before accessing aux channel
1062 if (!ironlake_edp_have_panel_power(intel_dp)) {
1063 DRM_DEBUG_KMS("eDP was not running\n");
1064 msleep(intel_dp->panel_power_up_delay);
1068 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1073 u32 pp_stat_reg, pp_ctrl_reg;
1075 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1077 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1078 pp = ironlake_get_pp_control(intel_dp);
1079 pp &= ~EDP_FORCE_VDD;
1081 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1082 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1084 I915_WRITE(pp_ctrl_reg, pp);
1085 POSTING_READ(pp_ctrl_reg);
1087 /* Make sure sequencer is idle before allowing subsequent activity */
1088 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1089 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1090 msleep(intel_dp->panel_power_down_delay);
1094 static void ironlake_panel_vdd_work(struct work_struct *__work)
1096 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1097 struct intel_dp, panel_vdd_work);
1098 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1100 mutex_lock(&dev->mode_config.mutex);
1101 ironlake_panel_vdd_off_sync(intel_dp);
1102 mutex_unlock(&dev->mode_config.mutex);
1105 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1107 if (!is_edp(intel_dp))
1110 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1111 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1113 intel_dp->want_panel_vdd = false;
1116 ironlake_panel_vdd_off_sync(intel_dp);
1119 * Queue the timer to fire a long
1120 * time from now (relative to the power down delay)
1121 * to keep the panel power up across a sequence of operations
1123 schedule_delayed_work(&intel_dp->panel_vdd_work,
1124 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1128 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1130 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1135 if (!is_edp(intel_dp))
1138 DRM_DEBUG_KMS("Turn eDP power on\n");
1140 if (ironlake_edp_have_panel_power(intel_dp)) {
1141 DRM_DEBUG_KMS("eDP power already on\n");
1145 ironlake_wait_panel_power_cycle(intel_dp);
1147 pp = ironlake_get_pp_control(intel_dp);
1149 /* ILK workaround: disable reset around power sequence */
1150 pp &= ~PANEL_POWER_RESET;
1151 I915_WRITE(PCH_PP_CONTROL, pp);
1152 POSTING_READ(PCH_PP_CONTROL);
1155 pp |= POWER_TARGET_ON;
1157 pp |= PANEL_POWER_RESET;
1159 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1161 I915_WRITE(pp_ctrl_reg, pp);
1162 POSTING_READ(pp_ctrl_reg);
1164 ironlake_wait_panel_on(intel_dp);
1167 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1168 I915_WRITE(PCH_PP_CONTROL, pp);
1169 POSTING_READ(PCH_PP_CONTROL);
1173 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1175 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1180 if (!is_edp(intel_dp))
1183 DRM_DEBUG_KMS("Turn eDP power off\n");
1185 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1187 pp = ironlake_get_pp_control(intel_dp);
1188 /* We need to switch off panel power _and_ force vdd, for otherwise some
1189 * panels get very unhappy and cease to work. */
1190 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1192 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1194 I915_WRITE(pp_ctrl_reg, pp);
1195 POSTING_READ(pp_ctrl_reg);
1197 intel_dp->want_panel_vdd = false;
1199 ironlake_wait_panel_off(intel_dp);
1202 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1204 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205 struct drm_device *dev = intel_dig_port->base.base.dev;
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1211 if (!is_edp(intel_dp))
1214 DRM_DEBUG_KMS("\n");
1216 * If we enable the backlight right away following a panel power
1217 * on, we may see slight flicker as the panel syncs with the eDP
1218 * link. So delay a bit to make sure the image is solid before
1219 * allowing it to appear.
1221 msleep(intel_dp->backlight_on_delay);
1222 pp = ironlake_get_pp_control(intel_dp);
1223 pp |= EDP_BLC_ENABLE;
1225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1227 I915_WRITE(pp_ctrl_reg, pp);
1228 POSTING_READ(pp_ctrl_reg);
1230 intel_panel_enable_backlight(dev, pipe);
1233 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1235 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1240 if (!is_edp(intel_dp))
1243 intel_panel_disable_backlight(dev);
1245 DRM_DEBUG_KMS("\n");
1246 pp = ironlake_get_pp_control(intel_dp);
1247 pp &= ~EDP_BLC_ENABLE;
1249 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1251 I915_WRITE(pp_ctrl_reg, pp);
1252 POSTING_READ(pp_ctrl_reg);
1253 msleep(intel_dp->backlight_off_delay);
1256 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1259 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1260 struct drm_device *dev = crtc->dev;
1261 struct drm_i915_private *dev_priv = dev->dev_private;
1264 assert_pipe_disabled(dev_priv,
1265 to_intel_crtc(crtc)->pipe);
1267 DRM_DEBUG_KMS("\n");
1268 dpa_ctl = I915_READ(DP_A);
1269 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1270 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1272 /* We don't adjust intel_dp->DP while tearing down the link, to
1273 * facilitate link retraining (e.g. after hotplug). Hence clear all
1274 * enable bits here to ensure that we don't enable too much. */
1275 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1276 intel_dp->DP |= DP_PLL_ENABLE;
1277 I915_WRITE(DP_A, intel_dp->DP);
1282 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1284 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1285 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1286 struct drm_device *dev = crtc->dev;
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1290 assert_pipe_disabled(dev_priv,
1291 to_intel_crtc(crtc)->pipe);
1293 dpa_ctl = I915_READ(DP_A);
1294 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1295 "dp pll off, should be on\n");
1296 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1298 /* We can't rely on the value tracked for the DP register in
1299 * intel_dp->DP because link_down must not change that (otherwise link
1300 * re-training will fail. */
1301 dpa_ctl &= ~DP_PLL_ENABLE;
1302 I915_WRITE(DP_A, dpa_ctl);
1307 /* If the sink supports it, try to set the power state appropriately */
1308 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1312 /* Should have a valid DPCD by this point */
1313 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1316 if (mode != DRM_MODE_DPMS_ON) {
1317 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1320 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1323 * When turning on, we need to retry for 1ms to give the sink
1326 for (i = 0; i < 3; i++) {
1327 ret = intel_dp_aux_native_write_1(intel_dp,
1337 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1340 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1341 struct drm_device *dev = encoder->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 u32 tmp = I915_READ(intel_dp->output_reg);
1345 if (!(tmp & DP_PORT_EN))
1348 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1349 *pipe = PORT_TO_PIPE_CPT(tmp);
1350 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1351 *pipe = PORT_TO_PIPE(tmp);
1357 switch (intel_dp->output_reg) {
1359 trans_sel = TRANS_DP_PORT_SEL_B;
1362 trans_sel = TRANS_DP_PORT_SEL_C;
1365 trans_sel = TRANS_DP_PORT_SEL_D;
1372 trans_dp = I915_READ(TRANS_DP_CTL(i));
1373 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1379 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1380 intel_dp->output_reg);
1386 static void intel_disable_dp(struct intel_encoder *encoder)
1388 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1390 /* Make sure the panel is off before trying to change the mode. But also
1391 * ensure that we have vdd while we switch off the panel. */
1392 ironlake_edp_panel_vdd_on(intel_dp);
1393 ironlake_edp_backlight_off(intel_dp);
1394 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1395 ironlake_edp_panel_off(intel_dp);
1397 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1398 if (!is_cpu_edp(intel_dp))
1399 intel_dp_link_down(intel_dp);
1402 static void intel_post_disable_dp(struct intel_encoder *encoder)
1404 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1405 struct drm_device *dev = encoder->base.dev;
1407 if (is_cpu_edp(intel_dp)) {
1408 intel_dp_link_down(intel_dp);
1409 if (!IS_VALLEYVIEW(dev))
1410 ironlake_edp_pll_off(intel_dp);
1414 static void intel_enable_dp(struct intel_encoder *encoder)
1416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1417 struct drm_device *dev = encoder->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1421 if (WARN_ON(dp_reg & DP_PORT_EN))
1424 ironlake_edp_panel_vdd_on(intel_dp);
1425 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1426 intel_dp_start_link_train(intel_dp);
1427 ironlake_edp_panel_on(intel_dp);
1428 ironlake_edp_panel_vdd_off(intel_dp, true);
1429 intel_dp_complete_link_train(intel_dp);
1430 ironlake_edp_backlight_on(intel_dp);
1432 if (IS_VALLEYVIEW(dev)) {
1433 struct intel_digital_port *dport =
1434 enc_to_dig_port(&encoder->base);
1435 int channel = vlv_dport_to_channel(dport);
1437 vlv_wait_port_ready(dev_priv, channel);
1441 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1443 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1447 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1448 ironlake_edp_pll_on(intel_dp);
1450 if (IS_VALLEYVIEW(dev)) {
1451 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1452 struct intel_crtc *intel_crtc =
1453 to_intel_crtc(encoder->base.crtc);
1454 int port = vlv_dport_to_channel(dport);
1455 int pipe = intel_crtc->pipe;
1458 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1460 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1467 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1469 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1471 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1476 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1478 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1479 struct drm_device *dev = encoder->base.dev;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 int port = vlv_dport_to_channel(dport);
1483 if (!IS_VALLEYVIEW(dev))
1486 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1488 /* Program Tx lane resets to default */
1489 intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1490 DPIO_PCS_TX_LANE2_RESET |
1491 DPIO_PCS_TX_LANE1_RESET);
1492 intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1493 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1494 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1495 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1496 DPIO_PCS_CLK_SOFT_RESET);
1498 /* Fix up inter-pair skew failure */
1499 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1500 intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1501 intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1505 * Native read with retry for link status and receiver capability reads for
1506 * cases where the sink may still be asleep.
1509 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1510 uint8_t *recv, int recv_bytes)
1515 * Sinks are *supposed* to come up within 1ms from an off state,
1516 * but we're also supposed to retry 3 times per the spec.
1518 for (i = 0; i < 3; i++) {
1519 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1521 if (ret == recv_bytes)
1530 * Fetch AUX CH registers 0x202 - 0x207 which contain
1531 * link status information
1534 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1536 return intel_dp_aux_native_read_retry(intel_dp,
1539 DP_LINK_STATUS_SIZE);
1543 static char *voltage_names[] = {
1544 "0.4V", "0.6V", "0.8V", "1.2V"
1546 static char *pre_emph_names[] = {
1547 "0dB", "3.5dB", "6dB", "9.5dB"
1549 static char *link_train_names[] = {
1550 "pattern 1", "pattern 2", "idle", "off"
1555 * These are source-specific values; current Intel hardware supports
1556 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1560 intel_dp_voltage_max(struct intel_dp *intel_dp)
1562 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1564 if (IS_VALLEYVIEW(dev))
1565 return DP_TRAIN_VOLTAGE_SWING_1200;
1566 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1567 return DP_TRAIN_VOLTAGE_SWING_800;
1568 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1569 return DP_TRAIN_VOLTAGE_SWING_1200;
1571 return DP_TRAIN_VOLTAGE_SWING_800;
1575 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1577 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1580 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1581 case DP_TRAIN_VOLTAGE_SWING_400:
1582 return DP_TRAIN_PRE_EMPHASIS_9_5;
1583 case DP_TRAIN_VOLTAGE_SWING_600:
1584 return DP_TRAIN_PRE_EMPHASIS_6;
1585 case DP_TRAIN_VOLTAGE_SWING_800:
1586 return DP_TRAIN_PRE_EMPHASIS_3_5;
1587 case DP_TRAIN_VOLTAGE_SWING_1200:
1589 return DP_TRAIN_PRE_EMPHASIS_0;
1591 } else if (IS_VALLEYVIEW(dev)) {
1592 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1593 case DP_TRAIN_VOLTAGE_SWING_400:
1594 return DP_TRAIN_PRE_EMPHASIS_9_5;
1595 case DP_TRAIN_VOLTAGE_SWING_600:
1596 return DP_TRAIN_PRE_EMPHASIS_6;
1597 case DP_TRAIN_VOLTAGE_SWING_800:
1598 return DP_TRAIN_PRE_EMPHASIS_3_5;
1599 case DP_TRAIN_VOLTAGE_SWING_1200:
1601 return DP_TRAIN_PRE_EMPHASIS_0;
1603 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1604 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1605 case DP_TRAIN_VOLTAGE_SWING_400:
1606 return DP_TRAIN_PRE_EMPHASIS_6;
1607 case DP_TRAIN_VOLTAGE_SWING_600:
1608 case DP_TRAIN_VOLTAGE_SWING_800:
1609 return DP_TRAIN_PRE_EMPHASIS_3_5;
1611 return DP_TRAIN_PRE_EMPHASIS_0;
1614 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1615 case DP_TRAIN_VOLTAGE_SWING_400:
1616 return DP_TRAIN_PRE_EMPHASIS_6;
1617 case DP_TRAIN_VOLTAGE_SWING_600:
1618 return DP_TRAIN_PRE_EMPHASIS_6;
1619 case DP_TRAIN_VOLTAGE_SWING_800:
1620 return DP_TRAIN_PRE_EMPHASIS_3_5;
1621 case DP_TRAIN_VOLTAGE_SWING_1200:
1623 return DP_TRAIN_PRE_EMPHASIS_0;
1628 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1633 unsigned long demph_reg_value, preemph_reg_value,
1634 uniqtranscale_reg_value;
1635 uint8_t train_set = intel_dp->train_set[0];
1636 int port = vlv_dport_to_channel(dport);
1638 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1640 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1641 case DP_TRAIN_PRE_EMPHASIS_0:
1642 preemph_reg_value = 0x0004000;
1643 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1644 case DP_TRAIN_VOLTAGE_SWING_400:
1645 demph_reg_value = 0x2B405555;
1646 uniqtranscale_reg_value = 0x552AB83A;
1648 case DP_TRAIN_VOLTAGE_SWING_600:
1649 demph_reg_value = 0x2B404040;
1650 uniqtranscale_reg_value = 0x5548B83A;
1652 case DP_TRAIN_VOLTAGE_SWING_800:
1653 demph_reg_value = 0x2B245555;
1654 uniqtranscale_reg_value = 0x5560B83A;
1656 case DP_TRAIN_VOLTAGE_SWING_1200:
1657 demph_reg_value = 0x2B405555;
1658 uniqtranscale_reg_value = 0x5598DA3A;
1664 case DP_TRAIN_PRE_EMPHASIS_3_5:
1665 preemph_reg_value = 0x0002000;
1666 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1667 case DP_TRAIN_VOLTAGE_SWING_400:
1668 demph_reg_value = 0x2B404040;
1669 uniqtranscale_reg_value = 0x5552B83A;
1671 case DP_TRAIN_VOLTAGE_SWING_600:
1672 demph_reg_value = 0x2B404848;
1673 uniqtranscale_reg_value = 0x5580B83A;
1675 case DP_TRAIN_VOLTAGE_SWING_800:
1676 demph_reg_value = 0x2B404040;
1677 uniqtranscale_reg_value = 0x55ADDA3A;
1683 case DP_TRAIN_PRE_EMPHASIS_6:
1684 preemph_reg_value = 0x0000000;
1685 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1686 case DP_TRAIN_VOLTAGE_SWING_400:
1687 demph_reg_value = 0x2B305555;
1688 uniqtranscale_reg_value = 0x5570B83A;
1690 case DP_TRAIN_VOLTAGE_SWING_600:
1691 demph_reg_value = 0x2B2B4040;
1692 uniqtranscale_reg_value = 0x55ADDA3A;
1698 case DP_TRAIN_PRE_EMPHASIS_9_5:
1699 preemph_reg_value = 0x0006000;
1700 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1701 case DP_TRAIN_VOLTAGE_SWING_400:
1702 demph_reg_value = 0x1B405555;
1703 uniqtranscale_reg_value = 0x55ADDA3A;
1713 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1714 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1715 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1716 uniqtranscale_reg_value);
1717 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1718 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1719 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1720 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1726 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1731 uint8_t voltage_max;
1732 uint8_t preemph_max;
1734 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1735 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1736 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1744 voltage_max = intel_dp_voltage_max(intel_dp);
1745 if (v >= voltage_max)
1746 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1748 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1749 if (p >= preemph_max)
1750 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1752 for (lane = 0; lane < 4; lane++)
1753 intel_dp->train_set[lane] = v | p;
1757 intel_gen4_signal_levels(uint8_t train_set)
1759 uint32_t signal_levels = 0;
1761 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1762 case DP_TRAIN_VOLTAGE_SWING_400:
1764 signal_levels |= DP_VOLTAGE_0_4;
1766 case DP_TRAIN_VOLTAGE_SWING_600:
1767 signal_levels |= DP_VOLTAGE_0_6;
1769 case DP_TRAIN_VOLTAGE_SWING_800:
1770 signal_levels |= DP_VOLTAGE_0_8;
1772 case DP_TRAIN_VOLTAGE_SWING_1200:
1773 signal_levels |= DP_VOLTAGE_1_2;
1776 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1777 case DP_TRAIN_PRE_EMPHASIS_0:
1779 signal_levels |= DP_PRE_EMPHASIS_0;
1781 case DP_TRAIN_PRE_EMPHASIS_3_5:
1782 signal_levels |= DP_PRE_EMPHASIS_3_5;
1784 case DP_TRAIN_PRE_EMPHASIS_6:
1785 signal_levels |= DP_PRE_EMPHASIS_6;
1787 case DP_TRAIN_PRE_EMPHASIS_9_5:
1788 signal_levels |= DP_PRE_EMPHASIS_9_5;
1791 return signal_levels;
1794 /* Gen6's DP voltage swing and pre-emphasis control */
1796 intel_gen6_edp_signal_levels(uint8_t train_set)
1798 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1799 DP_TRAIN_PRE_EMPHASIS_MASK);
1800 switch (signal_levels) {
1801 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1802 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1803 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1804 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1805 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1806 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1807 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1808 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1809 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1810 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1811 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1812 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1813 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1814 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1816 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1817 "0x%x\n", signal_levels);
1818 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1822 /* Gen7's DP voltage swing and pre-emphasis control */
1824 intel_gen7_edp_signal_levels(uint8_t train_set)
1826 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1827 DP_TRAIN_PRE_EMPHASIS_MASK);
1828 switch (signal_levels) {
1829 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1830 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1831 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1832 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1833 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1834 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1836 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1837 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1838 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1839 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1841 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1842 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1843 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1844 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1847 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1848 "0x%x\n", signal_levels);
1849 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1853 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1855 intel_hsw_signal_levels(uint8_t train_set)
1857 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1858 DP_TRAIN_PRE_EMPHASIS_MASK);
1859 switch (signal_levels) {
1860 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1861 return DDI_BUF_EMP_400MV_0DB_HSW;
1862 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1863 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1864 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1865 return DDI_BUF_EMP_400MV_6DB_HSW;
1866 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1867 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1869 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1870 return DDI_BUF_EMP_600MV_0DB_HSW;
1871 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1872 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1873 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1874 return DDI_BUF_EMP_600MV_6DB_HSW;
1876 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1877 return DDI_BUF_EMP_800MV_0DB_HSW;
1878 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1879 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1881 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1882 "0x%x\n", signal_levels);
1883 return DDI_BUF_EMP_400MV_0DB_HSW;
1887 /* Properly updates "DP" with the correct signal levels. */
1889 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1891 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1892 struct drm_device *dev = intel_dig_port->base.base.dev;
1893 uint32_t signal_levels, mask;
1894 uint8_t train_set = intel_dp->train_set[0];
1897 signal_levels = intel_hsw_signal_levels(train_set);
1898 mask = DDI_BUF_EMP_MASK;
1899 } else if (IS_VALLEYVIEW(dev)) {
1900 signal_levels = intel_vlv_signal_levels(intel_dp);
1902 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1903 signal_levels = intel_gen7_edp_signal_levels(train_set);
1904 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1905 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1906 signal_levels = intel_gen6_edp_signal_levels(train_set);
1907 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1909 signal_levels = intel_gen4_signal_levels(train_set);
1910 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1913 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1915 *DP = (*DP & ~mask) | signal_levels;
1919 intel_dp_set_link_train(struct intel_dp *intel_dp,
1920 uint32_t dp_reg_value,
1921 uint8_t dp_train_pat)
1923 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1924 struct drm_device *dev = intel_dig_port->base.base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 enum port port = intel_dig_port->port;
1931 temp = I915_READ(DP_TP_CTL(port));
1933 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1934 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1936 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1938 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1939 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1940 case DP_TRAINING_PATTERN_DISABLE:
1942 if (port != PORT_A) {
1943 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1944 I915_WRITE(DP_TP_CTL(port), temp);
1946 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1947 DP_TP_STATUS_IDLE_DONE), 1))
1948 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1950 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1953 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1956 case DP_TRAINING_PATTERN_1:
1957 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1959 case DP_TRAINING_PATTERN_2:
1960 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1962 case DP_TRAINING_PATTERN_3:
1963 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1966 I915_WRITE(DP_TP_CTL(port), temp);
1968 } else if (HAS_PCH_CPT(dev) &&
1969 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1970 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1972 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1973 case DP_TRAINING_PATTERN_DISABLE:
1974 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1976 case DP_TRAINING_PATTERN_1:
1977 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1979 case DP_TRAINING_PATTERN_2:
1980 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1982 case DP_TRAINING_PATTERN_3:
1983 DRM_ERROR("DP training pattern 3 not supported\n");
1984 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1989 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1991 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1992 case DP_TRAINING_PATTERN_DISABLE:
1993 dp_reg_value |= DP_LINK_TRAIN_OFF;
1995 case DP_TRAINING_PATTERN_1:
1996 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1998 case DP_TRAINING_PATTERN_2:
1999 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2001 case DP_TRAINING_PATTERN_3:
2002 DRM_ERROR("DP training pattern 3 not supported\n");
2003 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2008 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2009 POSTING_READ(intel_dp->output_reg);
2011 intel_dp_aux_native_write_1(intel_dp,
2012 DP_TRAINING_PATTERN_SET,
2015 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2016 DP_TRAINING_PATTERN_DISABLE) {
2017 ret = intel_dp_aux_native_write(intel_dp,
2018 DP_TRAINING_LANE0_SET,
2019 intel_dp->train_set,
2020 intel_dp->lane_count);
2021 if (ret != intel_dp->lane_count)
2028 /* Enable corresponding port and start training pattern 1 */
2030 intel_dp_start_link_train(struct intel_dp *intel_dp)
2032 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2033 struct drm_device *dev = encoder->dev;
2036 bool clock_recovery = false;
2037 int voltage_tries, loop_tries;
2038 uint32_t DP = intel_dp->DP;
2041 intel_ddi_prepare_link_retrain(encoder);
2043 /* Write the link configuration data */
2044 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2045 intel_dp->link_configuration,
2046 DP_LINK_CONFIGURATION_SIZE);
2050 memset(intel_dp->train_set, 0, 4);
2054 clock_recovery = false;
2056 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2057 uint8_t link_status[DP_LINK_STATUS_SIZE];
2059 intel_dp_set_signal_levels(intel_dp, &DP);
2061 /* Set training pattern 1 */
2062 if (!intel_dp_set_link_train(intel_dp, DP,
2063 DP_TRAINING_PATTERN_1 |
2064 DP_LINK_SCRAMBLING_DISABLE))
2067 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2068 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2069 DRM_ERROR("failed to get link status\n");
2073 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2074 DRM_DEBUG_KMS("clock recovery OK\n");
2075 clock_recovery = true;
2079 /* Check to see if we've tried the max voltage */
2080 for (i = 0; i < intel_dp->lane_count; i++)
2081 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2083 if (i == intel_dp->lane_count) {
2085 if (loop_tries == 5) {
2086 DRM_DEBUG_KMS("too many full retries, give up\n");
2089 memset(intel_dp->train_set, 0, 4);
2094 /* Check to see if we've tried the same voltage 5 times */
2095 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2097 if (voltage_tries == 5) {
2098 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2103 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2105 /* Compute new intel_dp->train_set as requested by target */
2106 intel_get_adjust_train(intel_dp, link_status);
2113 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2115 bool channel_eq = false;
2116 int tries, cr_tries;
2117 uint32_t DP = intel_dp->DP;
2119 /* channel equalization */
2124 uint8_t link_status[DP_LINK_STATUS_SIZE];
2127 DRM_ERROR("failed to train DP, aborting\n");
2128 intel_dp_link_down(intel_dp);
2132 intel_dp_set_signal_levels(intel_dp, &DP);
2134 /* channel eq pattern */
2135 if (!intel_dp_set_link_train(intel_dp, DP,
2136 DP_TRAINING_PATTERN_2 |
2137 DP_LINK_SCRAMBLING_DISABLE))
2140 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2141 if (!intel_dp_get_link_status(intel_dp, link_status))
2144 /* Make sure clock is still ok */
2145 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2146 intel_dp_start_link_train(intel_dp);
2151 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2156 /* Try 5 times, then try clock recovery if that fails */
2158 intel_dp_link_down(intel_dp);
2159 intel_dp_start_link_train(intel_dp);
2165 /* Compute new intel_dp->train_set as requested by target */
2166 intel_get_adjust_train(intel_dp, link_status);
2171 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2173 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2177 intel_dp_link_down(struct intel_dp *intel_dp)
2179 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2180 struct drm_device *dev = intel_dig_port->base.base.dev;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 struct intel_crtc *intel_crtc =
2183 to_intel_crtc(intel_dig_port->base.base.crtc);
2184 uint32_t DP = intel_dp->DP;
2187 * DDI code has a strict mode set sequence and we should try to respect
2188 * it, otherwise we might hang the machine in many different ways. So we
2189 * really should be disabling the port only on a complete crtc_disable
2190 * sequence. This function is just called under two conditions on DDI
2192 * - Link train failed while doing crtc_enable, and on this case we
2193 * really should respect the mode set sequence and wait for a
2195 * - Someone turned the monitor off and intel_dp_check_link_status
2196 * called us. We don't need to disable the whole port on this case, so
2197 * when someone turns the monitor on again,
2198 * intel_ddi_prepare_link_retrain will take care of redoing the link
2204 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2207 DRM_DEBUG_KMS("\n");
2209 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2210 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2211 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2213 DP &= ~DP_LINK_TRAIN_MASK;
2214 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2216 POSTING_READ(intel_dp->output_reg);
2218 /* We don't really know why we're doing this */
2219 intel_wait_for_vblank(dev, intel_crtc->pipe);
2221 if (HAS_PCH_IBX(dev) &&
2222 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2223 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2225 /* Hardware workaround: leaving our transcoder select
2226 * set to transcoder B while it's off will prevent the
2227 * corresponding HDMI output on transcoder A.
2229 * Combine this with another hardware workaround:
2230 * transcoder select bit can only be cleared while the
2233 DP &= ~DP_PIPEB_SELECT;
2234 I915_WRITE(intel_dp->output_reg, DP);
2236 /* Changes to enable or select take place the vblank
2237 * after being written.
2239 if (WARN_ON(crtc == NULL)) {
2240 /* We should never try to disable a port without a crtc
2241 * attached. For paranoia keep the code around for a
2243 POSTING_READ(intel_dp->output_reg);
2246 intel_wait_for_vblank(dev, intel_crtc->pipe);
2249 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2250 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2251 POSTING_READ(intel_dp->output_reg);
2252 msleep(intel_dp->panel_power_down_delay);
2256 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2258 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2260 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2261 sizeof(intel_dp->dpcd)) == 0)
2262 return false; /* aux transfer failed */
2264 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2265 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2266 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2268 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2269 return false; /* DPCD not present */
2271 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2272 DP_DWN_STRM_PORT_PRESENT))
2273 return true; /* native DP sink */
2275 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2276 return true; /* no per-port downstream info */
2278 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2279 intel_dp->downstream_ports,
2280 DP_MAX_DOWNSTREAM_PORTS) == 0)
2281 return false; /* downstream port status fetch failed */
2287 intel_dp_probe_oui(struct intel_dp *intel_dp)
2291 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2294 ironlake_edp_panel_vdd_on(intel_dp);
2296 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2297 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2298 buf[0], buf[1], buf[2]);
2300 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2301 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2302 buf[0], buf[1], buf[2]);
2304 ironlake_edp_panel_vdd_off(intel_dp, false);
2308 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2312 ret = intel_dp_aux_native_read_retry(intel_dp,
2313 DP_DEVICE_SERVICE_IRQ_VECTOR,
2314 sink_irq_vector, 1);
2322 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2324 /* NAK by default */
2325 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2329 * According to DP spec
2332 * 2. Configure link according to Receiver Capabilities
2333 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2334 * 4. Check link status on receipt of hot-plug interrupt
2338 intel_dp_check_link_status(struct intel_dp *intel_dp)
2340 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2342 u8 link_status[DP_LINK_STATUS_SIZE];
2344 if (!intel_encoder->connectors_active)
2347 if (WARN_ON(!intel_encoder->base.crtc))
2350 /* Try to read receiver status if the link appears to be up */
2351 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2352 intel_dp_link_down(intel_dp);
2356 /* Now read the DPCD to see if it's actually running */
2357 if (!intel_dp_get_dpcd(intel_dp)) {
2358 intel_dp_link_down(intel_dp);
2362 /* Try to read the source of the interrupt */
2363 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2364 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2365 /* Clear interrupt source */
2366 intel_dp_aux_native_write_1(intel_dp,
2367 DP_DEVICE_SERVICE_IRQ_VECTOR,
2370 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2371 intel_dp_handle_test_request(intel_dp);
2372 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2373 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2376 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2377 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2378 drm_get_encoder_name(&intel_encoder->base));
2379 intel_dp_start_link_train(intel_dp);
2380 intel_dp_complete_link_train(intel_dp);
2384 /* XXX this is probably wrong for multiple downstream ports */
2385 static enum drm_connector_status
2386 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2388 uint8_t *dpcd = intel_dp->dpcd;
2392 if (!intel_dp_get_dpcd(intel_dp))
2393 return connector_status_disconnected;
2395 /* if there's no downstream port, we're done */
2396 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2397 return connector_status_connected;
2399 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2400 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2403 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2405 return connector_status_unknown;
2406 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2407 : connector_status_disconnected;
2410 /* If no HPD, poke DDC gently */
2411 if (drm_probe_ddc(&intel_dp->adapter))
2412 return connector_status_connected;
2414 /* Well we tried, say unknown for unreliable port types */
2415 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2416 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2417 return connector_status_unknown;
2419 /* Anything else is out of spec, warn and ignore */
2420 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2421 return connector_status_disconnected;
2424 static enum drm_connector_status
2425 ironlake_dp_detect(struct intel_dp *intel_dp)
2427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2430 enum drm_connector_status status;
2432 /* Can't disconnect eDP, but you can close the lid... */
2433 if (is_edp(intel_dp)) {
2434 status = intel_panel_detect(dev);
2435 if (status == connector_status_unknown)
2436 status = connector_status_connected;
2440 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2441 return connector_status_disconnected;
2443 return intel_dp_detect_dpcd(intel_dp);
2446 static enum drm_connector_status
2447 g4x_dp_detect(struct intel_dp *intel_dp)
2449 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2454 /* Can't disconnect eDP, but you can close the lid... */
2455 if (is_edp(intel_dp)) {
2456 enum drm_connector_status status;
2458 status = intel_panel_detect(dev);
2459 if (status == connector_status_unknown)
2460 status = connector_status_connected;
2464 switch (intel_dig_port->port) {
2466 bit = PORTB_HOTPLUG_LIVE_STATUS;
2469 bit = PORTC_HOTPLUG_LIVE_STATUS;
2472 bit = PORTD_HOTPLUG_LIVE_STATUS;
2475 return connector_status_unknown;
2478 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2479 return connector_status_disconnected;
2481 return intel_dp_detect_dpcd(intel_dp);
2484 static struct edid *
2485 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2487 struct intel_connector *intel_connector = to_intel_connector(connector);
2489 /* use cached edid if we have one */
2490 if (intel_connector->edid) {
2495 if (IS_ERR(intel_connector->edid))
2498 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2499 edid = kmalloc(size, GFP_KERNEL);
2503 memcpy(edid, intel_connector->edid, size);
2507 return drm_get_edid(connector, adapter);
2511 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2513 struct intel_connector *intel_connector = to_intel_connector(connector);
2515 /* use cached edid if we have one */
2516 if (intel_connector->edid) {
2518 if (IS_ERR(intel_connector->edid))
2521 return intel_connector_update_modes(connector,
2522 intel_connector->edid);
2525 return intel_ddc_get_modes(connector, adapter);
2528 static enum drm_connector_status
2529 intel_dp_detect(struct drm_connector *connector, bool force)
2531 struct intel_dp *intel_dp = intel_attached_dp(connector);
2532 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2533 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2534 struct drm_device *dev = connector->dev;
2535 enum drm_connector_status status;
2536 struct edid *edid = NULL;
2538 intel_dp->has_audio = false;
2540 if (HAS_PCH_SPLIT(dev))
2541 status = ironlake_dp_detect(intel_dp);
2543 status = g4x_dp_detect(intel_dp);
2545 if (status != connector_status_connected)
2548 intel_dp_probe_oui(intel_dp);
2550 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2551 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2553 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2555 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2560 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2561 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2562 return connector_status_connected;
2565 static int intel_dp_get_modes(struct drm_connector *connector)
2567 struct intel_dp *intel_dp = intel_attached_dp(connector);
2568 struct intel_connector *intel_connector = to_intel_connector(connector);
2569 struct drm_device *dev = connector->dev;
2572 /* We should parse the EDID data and find out if it has an audio sink
2575 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2579 /* if eDP has no EDID, fall back to fixed mode */
2580 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2581 struct drm_display_mode *mode;
2582 mode = drm_mode_duplicate(dev,
2583 intel_connector->panel.fixed_mode);
2585 drm_mode_probed_add(connector, mode);
2593 intel_dp_detect_audio(struct drm_connector *connector)
2595 struct intel_dp *intel_dp = intel_attached_dp(connector);
2597 bool has_audio = false;
2599 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2601 has_audio = drm_detect_monitor_audio(edid);
2609 intel_dp_set_property(struct drm_connector *connector,
2610 struct drm_property *property,
2613 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2614 struct intel_connector *intel_connector = to_intel_connector(connector);
2615 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2616 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2619 ret = drm_object_property_set_value(&connector->base, property, val);
2623 if (property == dev_priv->force_audio_property) {
2627 if (i == intel_dp->force_audio)
2630 intel_dp->force_audio = i;
2632 if (i == HDMI_AUDIO_AUTO)
2633 has_audio = intel_dp_detect_audio(connector);
2635 has_audio = (i == HDMI_AUDIO_ON);
2637 if (has_audio == intel_dp->has_audio)
2640 intel_dp->has_audio = has_audio;
2644 if (property == dev_priv->broadcast_rgb_property) {
2646 case INTEL_BROADCAST_RGB_AUTO:
2647 intel_dp->color_range_auto = true;
2649 case INTEL_BROADCAST_RGB_FULL:
2650 intel_dp->color_range_auto = false;
2651 intel_dp->color_range = 0;
2653 case INTEL_BROADCAST_RGB_LIMITED:
2654 intel_dp->color_range_auto = false;
2655 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2663 if (is_edp(intel_dp) &&
2664 property == connector->dev->mode_config.scaling_mode_property) {
2665 if (val == DRM_MODE_SCALE_NONE) {
2666 DRM_DEBUG_KMS("no scaling not supported\n");
2670 if (intel_connector->panel.fitting_mode == val) {
2671 /* the eDP scaling property is not changed */
2674 intel_connector->panel.fitting_mode = val;
2682 if (intel_encoder->base.crtc)
2683 intel_crtc_restore_mode(intel_encoder->base.crtc);
2689 intel_dp_destroy(struct drm_connector *connector)
2691 struct intel_dp *intel_dp = intel_attached_dp(connector);
2692 struct intel_connector *intel_connector = to_intel_connector(connector);
2694 if (!IS_ERR_OR_NULL(intel_connector->edid))
2695 kfree(intel_connector->edid);
2697 if (is_edp(intel_dp))
2698 intel_panel_fini(&intel_connector->panel);
2700 drm_sysfs_connector_remove(connector);
2701 drm_connector_cleanup(connector);
2705 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2707 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2708 struct intel_dp *intel_dp = &intel_dig_port->dp;
2710 i2c_del_adapter(&intel_dp->adapter);
2711 drm_encoder_cleanup(encoder);
2712 if (is_edp(intel_dp)) {
2713 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2714 ironlake_panel_vdd_off_sync(intel_dp);
2716 kfree(intel_dig_port);
2719 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2720 .mode_set = intel_dp_mode_set,
2723 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2724 .dpms = intel_connector_dpms,
2725 .detect = intel_dp_detect,
2726 .fill_modes = drm_helper_probe_single_connector_modes,
2727 .set_property = intel_dp_set_property,
2728 .destroy = intel_dp_destroy,
2731 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2732 .get_modes = intel_dp_get_modes,
2733 .mode_valid = intel_dp_mode_valid,
2734 .best_encoder = intel_best_encoder,
2737 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2738 .destroy = intel_dp_encoder_destroy,
2742 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2744 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2746 intel_dp_check_link_status(intel_dp);
2749 /* Return which DP Port should be selected for Transcoder DP control */
2751 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2753 struct drm_device *dev = crtc->dev;
2754 struct intel_encoder *intel_encoder;
2755 struct intel_dp *intel_dp;
2757 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2758 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2760 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2761 intel_encoder->type == INTEL_OUTPUT_EDP)
2762 return intel_dp->output_reg;
2768 /* check the VBT to see whether the eDP is on DP-D port */
2769 bool intel_dpd_is_edp(struct drm_device *dev)
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct child_device_config *p_child;
2775 if (!dev_priv->child_dev_num)
2778 for (i = 0; i < dev_priv->child_dev_num; i++) {
2779 p_child = dev_priv->child_dev + i;
2781 if (p_child->dvo_port == PORT_IDPD &&
2782 p_child->device_type == DEVICE_TYPE_eDP)
2789 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2791 struct intel_connector *intel_connector = to_intel_connector(connector);
2793 intel_attach_force_audio_property(connector);
2794 intel_attach_broadcast_rgb_property(connector);
2795 intel_dp->color_range_auto = true;
2797 if (is_edp(intel_dp)) {
2798 drm_mode_create_scaling_mode_property(connector->dev);
2799 drm_object_attach_property(
2801 connector->dev->mode_config.scaling_mode_property,
2802 DRM_MODE_SCALE_ASPECT);
2803 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2808 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2809 struct intel_dp *intel_dp,
2810 struct edp_power_seq *out)
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 struct edp_power_seq cur, vbt, spec, final;
2814 u32 pp_on, pp_off, pp_div, pp;
2815 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2817 if (HAS_PCH_SPLIT(dev)) {
2818 pp_control_reg = PCH_PP_CONTROL;
2819 pp_on_reg = PCH_PP_ON_DELAYS;
2820 pp_off_reg = PCH_PP_OFF_DELAYS;
2821 pp_div_reg = PCH_PP_DIVISOR;
2823 pp_control_reg = PIPEA_PP_CONTROL;
2824 pp_on_reg = PIPEA_PP_ON_DELAYS;
2825 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2826 pp_div_reg = PIPEA_PP_DIVISOR;
2829 /* Workaround: Need to write PP_CONTROL with the unlock key as
2830 * the very first thing. */
2831 pp = ironlake_get_pp_control(intel_dp);
2832 I915_WRITE(pp_control_reg, pp);
2834 pp_on = I915_READ(pp_on_reg);
2835 pp_off = I915_READ(pp_off_reg);
2836 pp_div = I915_READ(pp_div_reg);
2838 /* Pull timing values out of registers */
2839 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2840 PANEL_POWER_UP_DELAY_SHIFT;
2842 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2843 PANEL_LIGHT_ON_DELAY_SHIFT;
2845 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2846 PANEL_LIGHT_OFF_DELAY_SHIFT;
2848 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2849 PANEL_POWER_DOWN_DELAY_SHIFT;
2851 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2852 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2854 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2855 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2857 vbt = dev_priv->edp.pps;
2859 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2860 * our hw here, which are all in 100usec. */
2861 spec.t1_t3 = 210 * 10;
2862 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2863 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2864 spec.t10 = 500 * 10;
2865 /* This one is special and actually in units of 100ms, but zero
2866 * based in the hw (so we need to add 100 ms). But the sw vbt
2867 * table multiplies it with 1000 to make it in units of 100usec,
2869 spec.t11_t12 = (510 + 100) * 10;
2871 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2872 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2874 /* Use the max of the register settings and vbt. If both are
2875 * unset, fall back to the spec limits. */
2876 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2878 max(cur.field, vbt.field))
2879 assign_final(t1_t3);
2883 assign_final(t11_t12);
2886 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2887 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2888 intel_dp->backlight_on_delay = get_delay(t8);
2889 intel_dp->backlight_off_delay = get_delay(t9);
2890 intel_dp->panel_power_down_delay = get_delay(t10);
2891 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2894 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2895 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2896 intel_dp->panel_power_cycle_delay);
2898 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2899 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2906 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2907 struct intel_dp *intel_dp,
2908 struct edp_power_seq *seq)
2910 struct drm_i915_private *dev_priv = dev->dev_private;
2911 u32 pp_on, pp_off, pp_div, port_sel = 0;
2912 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2913 int pp_on_reg, pp_off_reg, pp_div_reg;
2915 if (HAS_PCH_SPLIT(dev)) {
2916 pp_on_reg = PCH_PP_ON_DELAYS;
2917 pp_off_reg = PCH_PP_OFF_DELAYS;
2918 pp_div_reg = PCH_PP_DIVISOR;
2920 pp_on_reg = PIPEA_PP_ON_DELAYS;
2921 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2922 pp_div_reg = PIPEA_PP_DIVISOR;
2925 if (IS_VALLEYVIEW(dev))
2926 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2928 /* And finally store the new values in the power sequencer. */
2929 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2930 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2931 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2932 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2933 /* Compute the divisor for the pp clock, simply match the Bspec
2935 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2936 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2937 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2939 /* Haswell doesn't have any port selection bits for the panel
2940 * power sequencer any more. */
2941 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2942 if (is_cpu_edp(intel_dp))
2943 port_sel = PANEL_POWER_PORT_DP_A;
2945 port_sel = PANEL_POWER_PORT_DP_D;
2950 I915_WRITE(pp_on_reg, pp_on);
2951 I915_WRITE(pp_off_reg, pp_off);
2952 I915_WRITE(pp_div_reg, pp_div);
2954 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2955 I915_READ(pp_on_reg),
2956 I915_READ(pp_off_reg),
2957 I915_READ(pp_div_reg));
2961 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2962 struct intel_connector *intel_connector)
2964 struct drm_connector *connector = &intel_connector->base;
2965 struct intel_dp *intel_dp = &intel_dig_port->dp;
2966 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2967 struct drm_device *dev = intel_encoder->base.dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct drm_display_mode *fixed_mode = NULL;
2970 struct edp_power_seq power_seq = { 0 };
2971 enum port port = intel_dig_port->port;
2972 const char *name = NULL;
2975 /* Preserve the current hw state. */
2976 intel_dp->DP = I915_READ(intel_dp->output_reg);
2977 intel_dp->attached_connector = intel_connector;
2979 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2980 if (intel_dpd_is_edp(dev))
2981 intel_dp->is_pch_edp = true;
2984 * FIXME : We need to initialize built-in panels before external panels.
2985 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2987 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2988 type = DRM_MODE_CONNECTOR_eDP;
2989 intel_encoder->type = INTEL_OUTPUT_EDP;
2990 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2991 type = DRM_MODE_CONNECTOR_eDP;
2992 intel_encoder->type = INTEL_OUTPUT_EDP;
2994 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2995 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2998 type = DRM_MODE_CONNECTOR_DisplayPort;
3001 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3002 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3004 connector->interlace_allowed = true;
3005 connector->doublescan_allowed = 0;
3007 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3008 ironlake_panel_vdd_work);
3010 intel_connector_attach_encoder(intel_connector, intel_encoder);
3011 drm_sysfs_connector_add(connector);
3014 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3016 intel_connector->get_hw_state = intel_connector_get_hw_state;
3018 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3020 switch (intel_dig_port->port) {
3022 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3025 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3028 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3031 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3038 /* Set up the DDC bus. */
3041 intel_encoder->hpd_pin = HPD_PORT_A;
3045 intel_encoder->hpd_pin = HPD_PORT_B;
3049 intel_encoder->hpd_pin = HPD_PORT_C;
3053 intel_encoder->hpd_pin = HPD_PORT_D;
3060 if (is_edp(intel_dp))
3061 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3063 intel_dp_i2c_init(intel_dp, intel_connector, name);
3065 /* Cache DPCD and EDID for edp. */
3066 if (is_edp(intel_dp)) {
3068 struct drm_display_mode *scan;
3071 ironlake_edp_panel_vdd_on(intel_dp);
3072 ret = intel_dp_get_dpcd(intel_dp);
3073 ironlake_edp_panel_vdd_off(intel_dp, false);
3076 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3077 dev_priv->no_aux_handshake =
3078 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3079 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3081 /* if this fails, presume the device is a ghost */
3082 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3083 intel_dp_encoder_destroy(&intel_encoder->base);
3084 intel_dp_destroy(connector);
3088 /* We now know it's not a ghost, init power sequence regs. */
3089 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3092 ironlake_edp_panel_vdd_on(intel_dp);
3093 edid = drm_get_edid(connector, &intel_dp->adapter);
3095 if (drm_add_edid_modes(connector, edid)) {
3096 drm_mode_connector_update_edid_property(connector, edid);
3097 drm_edid_to_eld(connector, edid);
3100 edid = ERR_PTR(-EINVAL);
3103 edid = ERR_PTR(-ENOENT);
3105 intel_connector->edid = edid;
3107 /* prefer fixed mode from EDID if available */
3108 list_for_each_entry(scan, &connector->probed_modes, head) {
3109 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3110 fixed_mode = drm_mode_duplicate(dev, scan);
3115 /* fallback to VBT if available for eDP */
3116 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3117 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3119 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3122 ironlake_edp_panel_vdd_off(intel_dp, false);
3125 if (is_edp(intel_dp)) {
3126 intel_panel_init(&intel_connector->panel, fixed_mode);
3127 intel_panel_setup_backlight(connector);
3130 intel_dp_add_properties(intel_dp, connector);
3132 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3133 * 0xd. Failure to do so will result in spurious interrupts being
3134 * generated on the port when a cable is not attached.
3136 if (IS_G4X(dev) && !IS_GM45(dev)) {
3137 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3138 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3143 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3145 struct intel_digital_port *intel_dig_port;
3146 struct intel_encoder *intel_encoder;
3147 struct drm_encoder *encoder;
3148 struct intel_connector *intel_connector;
3150 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3151 if (!intel_dig_port)
3154 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3155 if (!intel_connector) {
3156 kfree(intel_dig_port);
3160 intel_encoder = &intel_dig_port->base;
3161 encoder = &intel_encoder->base;
3163 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3164 DRM_MODE_ENCODER_TMDS);
3165 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3167 intel_encoder->compute_config = intel_dp_compute_config;
3168 intel_encoder->enable = intel_enable_dp;
3169 intel_encoder->pre_enable = intel_pre_enable_dp;
3170 intel_encoder->disable = intel_disable_dp;
3171 intel_encoder->post_disable = intel_post_disable_dp;
3172 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3173 if (IS_VALLEYVIEW(dev))
3174 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3176 intel_dig_port->port = port;
3177 intel_dig_port->dp.output_reg = output_reg;
3179 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3180 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3181 intel_encoder->cloneable = false;
3182 intel_encoder->hot_plug = intel_dp_hot_plug;
3184 intel_dp_init_connector(intel_dig_port, intel_connector);