drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 159         switch (max_lane_count) {
 160         case 1: case 2: case 4:
 161                 break;
 162         default:
 163                 max_lane_count = 4;
 164         }
 165         return max_lane_count;
 166 }
 167
 168 static int
 169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 170 {
 171         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 172
 173         switch (max_link_bw) {
 174         case DP_LINK_BW_1_62:
 175         case DP_LINK_BW_2_7:
 176                 break;
 177         default:
 178                 max_link_bw = DP_LINK_BW_1_62;
 179                 break;
 180         }
 181         return max_link_bw;
 182 }
 183
 184 static int
 185 intel_dp_link_clock(uint8_t link_bw)
 186 {
 187         if (link_bw == DP_LINK_BW_2_7)
 188                 return 270000;
 189         else
 190                 return 162000;
 191 }
 192
 193 /*
 194  * The units on the numbers in the next two are... bizarre.  Examples will
 195  * make it clearer; this one parallels an example in the eDP spec.
 196  *
 197  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 198  *
 199  *     270000 * 1 * 8 / 10 == 216000
 200  *
 201  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 202  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 203  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 204  * 119000.  At 18bpp that's 2142000 kilobits per second.
 205  *
 206  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 207  * get the result in decakilobits instead of kilobits.
 208  */
 209
 210 static int
 211 intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)
 212 {
 213         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 215         int bpp = 24;
 216
 217         if (check_bpp)
 218                 bpp = check_bpp;
 219         else if (intel_crtc)
 220                 bpp = intel_crtc->bpp;
 221
 222         return (pixel_clock * bpp + 9) / 10;
 223 }
 224
 225 static int
 226 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 227 {
 228         return (max_link_clock * max_lanes * 8) / 10;
 229 }
 230
 231 static int
 232 intel_dp_mode_valid(struct drm_connector *connector,
 233                     struct drm_display_mode *mode)
 234 {
 235         struct intel_dp *intel_dp = intel_attached_dp(connector);
 236         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 237         int max_lanes = intel_dp_max_lane_count(intel_dp);
 238         int max_rate, mode_rate;
 239
 240         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 241                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 242                         return MODE_PANEL;
 243
 244                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 245                         return MODE_PANEL;
 246         }
 247
 248         mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);
 249         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 250
 251         if (mode_rate > max_rate) {
 252                         mode_rate = intel_dp_link_required(intel_dp,
 253                                                            mode->clock, 18);
 254                         if (mode_rate > max_rate)
 255                                 return MODE_CLOCK_HIGH;
 256                         else
 257                                 mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
 258         }
 259
 260         if (mode->clock < 10000)
 261                 return MODE_CLOCK_LOW;
 262
 263         return MODE_OK;
 264 }
 265
 266 static uint32_t
 267 pack_aux(uint8_t *src, int src_bytes)
 268 {
 269         int     i;
 270         uint32_t v = 0;
 271
 272         if (src_bytes > 4)
 273                 src_bytes = 4;
 274         for (i = 0; i < src_bytes; i++)
 275                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 276         return v;
 277 }
 278
 279 static void
 280 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 281 {
 282         int i;
 283         if (dst_bytes > 4)
 284                 dst_bytes = 4;
 285         for (i = 0; i < dst_bytes; i++)
 286                 dst[i] = src >> ((3-i) * 8);
 287 }
 288
 289 /* hrawclock is 1/4 the FSB frequency */
 290 static int
 291 intel_hrawclk(struct drm_device *dev)
 292 {
 293         struct drm_i915_private *dev_priv = dev->dev_private;
 294         uint32_t clkcfg;
 295
 296         clkcfg = I915_READ(CLKCFG);
 297         switch (clkcfg & CLKCFG_FSB_MASK) {
 298         case CLKCFG_FSB_400:
 299                 return 100;
 300         case CLKCFG_FSB_533:
 301                 return 133;
 302         case CLKCFG_FSB_667:
 303                 return 166;
 304         case CLKCFG_FSB_800:
 305                 return 200;
 306         case CLKCFG_FSB_1067:
 307                 return 266;
 308         case CLKCFG_FSB_1333:
 309                 return 333;
 310         /* these two are just a guess; one of them might be right */
 311         case CLKCFG_FSB_1600:
 312         case CLKCFG_FSB_1600_ALT:
 313                 return 400;
 314         default:
 315                 return 133;
 316         }
 317 }
 318
 319 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 320 {
 321         struct drm_device *dev = intel_dp->base.base.dev;
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 325 }
 326
 327 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 328 {
 329         struct drm_device *dev = intel_dp->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331
 332         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 333 }
 334
 335 static void
 336 intel_dp_check_edp(struct intel_dp *intel_dp)
 337 {
 338         struct drm_device *dev = intel_dp->base.base.dev;
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         if (!is_edp(intel_dp))
 342                 return;
 343         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 344                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 345                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 346                               I915_READ(PCH_PP_STATUS),
 347                               I915_READ(PCH_PP_CONTROL));
 348         }
 349 }
 350
 351 static int
 352 intel_dp_aux_ch(struct intel_dp *intel_dp,
 353                 uint8_t *send, int send_bytes,
 354                 uint8_t *recv, int recv_size)
 355 {
 356         uint32_t output_reg = intel_dp->output_reg;
 357         struct drm_device *dev = intel_dp->base.base.dev;
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         uint32_t ch_ctl = output_reg + 0x10;
 360         uint32_t ch_data = ch_ctl + 4;
 361         int i;
 362         int recv_bytes;
 363         uint32_t status;
 364         uint32_t aux_clock_divider;
 365         int try, precharge = 5;
 366
 367         intel_dp_check_edp(intel_dp);
 368         /* The clock divider is based off the hrawclk,
 369          * and would like to run at 2MHz. So, take the
 370          * hrawclk value and divide by 2 and use that
 371          *
 372          * Note that PCH attached eDP panels should use a 125MHz input
 373          * clock divider.
 374          */
 375         if (is_cpu_edp(intel_dp)) {
 376                 if (IS_GEN6(dev) || IS_GEN7(dev))
 377                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 378                 else
 379                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 380         } else if (HAS_PCH_SPLIT(dev))
 381                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 382         else
 383                 aux_clock_divider = intel_hrawclk(dev) / 2;
 384
 385         /* Try to wait for any previous AUX channel activity */
 386         for (try = 0; try < 3; try++) {
 387                 status = I915_READ(ch_ctl);
 388                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 389                         break;
 390                 msleep(1);
 391         }
 392
 393         if (try == 3) {
 394                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 395                      I915_READ(ch_ctl));
 396                 return -EBUSY;
 397         }
 398
 399         /* Must try at least 3 times according to DP spec */
 400         for (try = 0; try < 5; try++) {
 401                 /* Load the send data into the aux channel data registers */
 402                 for (i = 0; i < send_bytes; i += 4)
 403                         I915_WRITE(ch_data + i,
 404                                    pack_aux(send + i, send_bytes - i));
 405
 406                 /* Send the command and wait for it to complete */
 407                 I915_WRITE(ch_ctl,
 408                            DP_AUX_CH_CTL_SEND_BUSY |
 409                            DP_AUX_CH_CTL_TIME_OUT_400us |
 410                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 411                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 412                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 413                            DP_AUX_CH_CTL_DONE |
 414                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 415                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 416                 for (;;) {
 417                         status = I915_READ(ch_ctl);
 418                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 419                                 break;
 420                         udelay(100);
 421                 }
 422
 423                 /* Clear done status and any errors */
 424                 I915_WRITE(ch_ctl,
 425                            status |
 426                            DP_AUX_CH_CTL_DONE |
 427                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 428                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 429
 430                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 431                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 432                         continue;
 433                 if (status & DP_AUX_CH_CTL_DONE)
 434                         break;
 435         }
 436
 437         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 438                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 439                 return -EBUSY;
 440         }
 441
 442         /* Check for timeout or receive error.
 443          * Timeouts occur when the sink is not connected
 444          */
 445         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 446                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 447                 return -EIO;
 448         }
 449
 450         /* Timeouts occur when the device isn't connected, so they're
 451          * "normal" -- don't fill the kernel log with these */
 452         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 453                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 454                 return -ETIMEDOUT;
 455         }
 456
 457         /* Unload any bytes sent back from the other side */
 458         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 459                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 460         if (recv_bytes > recv_size)
 461                 recv_bytes = recv_size;
 462
 463         for (i = 0; i < recv_bytes; i += 4)
 464                 unpack_aux(I915_READ(ch_data + i),
 465                            recv + i, recv_bytes - i);
 466
 467         return recv_bytes;
 468 }
 469
 470 /* Write data to the aux channel in native mode */
 471 static int
 472 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 473                           uint16_t address, uint8_t *send, int send_bytes)
 474 {
 475         int ret;
 476         uint8_t msg[20];
 477         int msg_bytes;
 478         uint8_t ack;
 479
 480         intel_dp_check_edp(intel_dp);
 481         if (send_bytes > 16)
 482                 return -1;
 483         msg[0] = AUX_NATIVE_WRITE << 4;
 484         msg[1] = address >> 8;
 485         msg[2] = address & 0xff;
 486         msg[3] = send_bytes - 1;
 487         memcpy(&msg[4], send, send_bytes);
 488         msg_bytes = send_bytes + 4;
 489         for (;;) {
 490                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 491                 if (ret < 0)
 492                         return ret;
 493                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 494                         break;
 495                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 496                         udelay(100);
 497                 else
 498                         return -EIO;
 499         }
 500         return send_bytes;
 501 }
 502
 503 /* Write a single byte to the aux channel in native mode */
 504 static int
 505 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 506                             uint16_t address, uint8_t byte)
 507 {
 508         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 509 }
 510
 511 /* read bytes from a native aux channel */
 512 static int
 513 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 514                          uint16_t address, uint8_t *recv, int recv_bytes)
 515 {
 516         uint8_t msg[4];
 517         int msg_bytes;
 518         uint8_t reply[20];
 519         int reply_bytes;
 520         uint8_t ack;
 521         int ret;
 522
 523         intel_dp_check_edp(intel_dp);
 524         msg[0] = AUX_NATIVE_READ << 4;
 525         msg[1] = address >> 8;
 526         msg[2] = address & 0xff;
 527         msg[3] = recv_bytes - 1;
 528
 529         msg_bytes = 4;
 530         reply_bytes = recv_bytes + 1;
 531
 532         for (;;) {
 533                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 534                                       reply, reply_bytes);
 535                 if (ret == 0)
 536                         return -EPROTO;
 537                 if (ret < 0)
 538                         return ret;
 539                 ack = reply[0];
 540                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 541                         memcpy(recv, reply + 1, ret - 1);
 542                         return ret - 1;
 543                 }
 544                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 545                         udelay(100);
 546                 else
 547                         return -EIO;
 548         }
 549 }
 550
 551 static int
 552 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 553                     uint8_t write_byte, uint8_t *read_byte)
 554 {
 555         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 556         struct intel_dp *intel_dp = container_of(adapter,
 557                                                 struct intel_dp,
 558                                                 adapter);
 559         uint16_t address = algo_data->address;
 560         uint8_t msg[5];
 561         uint8_t reply[2];
 562         unsigned retry;
 563         int msg_bytes;
 564         int reply_bytes;
 565         int ret;
 566
 567         intel_dp_check_edp(intel_dp);
 568         /* Set up the command byte */
 569         if (mode & MODE_I2C_READ)
 570                 msg[0] = AUX_I2C_READ << 4;
 571         else
 572                 msg[0] = AUX_I2C_WRITE << 4;
 573
 574         if (!(mode & MODE_I2C_STOP))
 575                 msg[0] |= AUX_I2C_MOT << 4;
 576
 577         msg[1] = address >> 8;
 578         msg[2] = address;
 579
 580         switch (mode) {
 581         case MODE_I2C_WRITE:
 582                 msg[3] = 0;
 583                 msg[4] = write_byte;
 584                 msg_bytes = 5;
 585                 reply_bytes = 1;
 586                 break;
 587         case MODE_I2C_READ:
 588                 msg[3] = 0;
 589                 msg_bytes = 4;
 590                 reply_bytes = 2;
 591                 break;
 592         default:
 593                 msg_bytes = 3;
 594                 reply_bytes = 1;
 595                 break;
 596         }
 597
 598         for (retry = 0; retry < 5; retry++) {
 599                 ret = intel_dp_aux_ch(intel_dp,
 600                                       msg, msg_bytes,
 601                                       reply, reply_bytes);
 602                 if (ret < 0) {
 603                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 604                         return ret;
 605                 }
 606
 607                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 608                 case AUX_NATIVE_REPLY_ACK:
 609                         /* I2C-over-AUX Reply field is only valid
 610                          * when paired with AUX ACK.
 611                          */
 612                         break;
 613                 case AUX_NATIVE_REPLY_NACK:
 614                         DRM_DEBUG_KMS("aux_ch native nack\n");
 615                         return -EREMOTEIO;
 616                 case AUX_NATIVE_REPLY_DEFER:
 617                         udelay(100);
 618                         continue;
 619                 default:
 620                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 621                                   reply[0]);
 622                         return -EREMOTEIO;
 623                 }
 624
 625                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 626                 case AUX_I2C_REPLY_ACK:
 627                         if (mode == MODE_I2C_READ) {
 628                                 *read_byte = reply[1];
 629                         }
 630                         return reply_bytes - 1;
 631                 case AUX_I2C_REPLY_NACK:
 632                         DRM_DEBUG_KMS("aux_i2c nack\n");
 633                         return -EREMOTEIO;
 634                 case AUX_I2C_REPLY_DEFER:
 635                         DRM_DEBUG_KMS("aux_i2c defer\n");
 636                         udelay(100);
 637                         break;
 638                 default:
 639                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 640                         return -EREMOTEIO;
 641                 }
 642         }
 643
 644         DRM_ERROR("too many retries, giving up\n");
 645         return -EREMOTEIO;
 646 }
 647
 648 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 649 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 650
 651 static int
 652 intel_dp_i2c_init(struct intel_dp *intel_dp,
 653                   struct intel_connector *intel_connector, const char *name)
 654 {
 655         int     ret;
 656
 657         DRM_DEBUG_KMS("i2c_init %s\n", name);
 658         intel_dp->algo.running = false;
 659         intel_dp->algo.address = 0;
 660         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 661
 662         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 663         intel_dp->adapter.owner = THIS_MODULE;
 664         intel_dp->adapter.class = I2C_CLASS_DDC;
 665         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 666         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 667         intel_dp->adapter.algo_data = &intel_dp->algo;
 668         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 669
 670         ironlake_edp_panel_vdd_on(intel_dp);
 671         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 672         ironlake_edp_panel_vdd_off(intel_dp, false);
 673         return ret;
 674 }
 675
 676 static bool
 677 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 678                     struct drm_display_mode *adjusted_mode)
 679 {
 680         struct drm_device *dev = encoder->dev;
 681         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 682         int lane_count, clock;
 683         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 684         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 685         int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;
 686         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 687
 688         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 689                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 690                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 691                                         mode, adjusted_mode);
 692                 /*
 693                  * the mode->clock is used to calculate the Data&Link M/N
 694                  * of the pipe. For the eDP the fixed clock should be used.
 695                  */
 696                 mode->clock = intel_dp->panel_fixed_mode->clock;
 697         }
 698
 699         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 700                 for (clock = 0; clock <= max_clock; clock++) {
 701                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 702
 703                         if (intel_dp_link_required(intel_dp, mode->clock, bpp)
 704                                         <= link_avail) {
 705                                 intel_dp->link_bw = bws[clock];
 706                                 intel_dp->lane_count = lane_count;
 707                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 708                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 709                                                 "count %d clock %d\n",
 710                                        intel_dp->link_bw, intel_dp->lane_count,
 711                                        adjusted_mode->clock);
 712                                 return true;
 713                         }
 714                 }
 715         }
 716
 717         return false;
 718 }
 719
 720 struct intel_dp_m_n {
 721         uint32_t        tu;
 722         uint32_t        gmch_m;
 723         uint32_t        gmch_n;
 724         uint32_t        link_m;
 725         uint32_t        link_n;
 726 };
 727
 728 static void
 729 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 730 {
 731         while (*num > 0xffffff || *den > 0xffffff) {
 732                 *num >>= 1;
 733                 *den >>= 1;
 734         }
 735 }
 736
 737 static void
 738 intel_dp_compute_m_n(int bpp,
 739                      int nlanes,
 740                      int pixel_clock,
 741                      int link_clock,
 742                      struct intel_dp_m_n *m_n)
 743 {
 744         m_n->tu = 64;
 745         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 746         m_n->gmch_n = link_clock * nlanes;
 747         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 748         m_n->link_m = pixel_clock;
 749         m_n->link_n = link_clock;
 750         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 751 }
 752
 753 void
 754 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 755                  struct drm_display_mode *adjusted_mode)
 756 {
 757         struct drm_device *dev = crtc->dev;
 758         struct drm_mode_config *mode_config = &dev->mode_config;
 759         struct drm_encoder *encoder;
 760         struct drm_i915_private *dev_priv = dev->dev_private;
 761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 762         int lane_count = 4;
 763         struct intel_dp_m_n m_n;
 764         int pipe = intel_crtc->pipe;
 765
 766         /*
 767          * Find the lane count in the intel_encoder private
 768          */
 769         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 770                 struct intel_dp *intel_dp;
 771
 772                 if (encoder->crtc != crtc)
 773                         continue;
 774
 775                 intel_dp = enc_to_intel_dp(encoder);
 776                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 777                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 778                 {
 779                         lane_count = intel_dp->lane_count;
 780                         break;
 781                 }
 782         }
 783
 784         /*
 785          * Compute the GMCH and Link ratios. The '3' here is
 786          * the number of bytes_per_pixel post-LUT, which we always
 787          * set up for 8-bits of R/G/B, or 3 bytes total.
 788          */
 789         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 790                              mode->clock, adjusted_mode->clock, &m_n);
 791
 792         if (HAS_PCH_SPLIT(dev)) {
 793                 I915_WRITE(TRANSDATA_M1(pipe),
 794                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 795                            m_n.gmch_m);
 796                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 797                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 798                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 799         } else {
 800                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 801                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 802                            m_n.gmch_m);
 803                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 804                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 805                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 806         }
 807 }
 808
 809 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 810 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 811
 812 static void
 813 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 814                   struct drm_display_mode *adjusted_mode)
 815 {
 816         struct drm_device *dev = encoder->dev;
 817         struct drm_i915_private *dev_priv = dev->dev_private;
 818         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 819         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /* Turn on the eDP PLL if needed */
 823         if (is_edp(intel_dp)) {
 824                 if (!is_pch_edp(intel_dp))
 825                         ironlake_edp_pll_on(encoder);
 826                 else
 827                         ironlake_edp_pll_off(encoder);
 828         }
 829
 830         /*
 831          * There are four kinds of DP registers:
 832          *
 833          *      IBX PCH
 834          *      SNB CPU
 835          *      IVB CPU
 836          *      CPT PCH
 837          *
 838          * IBX PCH and CPU are the same for almost everything,
 839          * except that the CPU DP PLL is configured in this
 840          * register
 841          *
 842          * CPT PCH is quite different, having many bits moved
 843          * to the TRANS_DP_CTL register instead. That
 844          * configuration happens (oddly) in ironlake_pch_enable
 845          */
 846
 847         /* Preserve the BIOS-computed detected bit. This is
 848          * supposed to be read-only.
 849          */
 850         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 851         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 852
 853         /* Handle DP bits in common between all three register formats */
 854
 855         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 856
 857         switch (intel_dp->lane_count) {
 858         case 1:
 859                 intel_dp->DP |= DP_PORT_WIDTH_1;
 860                 break;
 861         case 2:
 862                 intel_dp->DP |= DP_PORT_WIDTH_2;
 863                 break;
 864         case 4:
 865                 intel_dp->DP |= DP_PORT_WIDTH_4;
 866                 break;
 867         }
 868         if (intel_dp->has_audio) {
 869                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 870                                  pipe_name(intel_crtc->pipe));
 871                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 872                 intel_write_eld(encoder, adjusted_mode);
 873         }
 874         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 875         intel_dp->link_configuration[0] = intel_dp->link_bw;
 876         intel_dp->link_configuration[1] = intel_dp->lane_count;
 877         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 878         /*
 879          * Check for DPCD version > 1.1 and enhanced framing support
 880          */
 881         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 882             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 883                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 884         }
 885
 886         /* Split out the IBX/CPU vs CPT settings */
 887
 888         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 889                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 890                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 891                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 892                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 893                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 894
 895                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 896                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 897
 898                 intel_dp->DP |= intel_crtc->pipe << 29;
 899
 900                 /* don't miss out required setting for eDP */
 901                 intel_dp->DP |= DP_PLL_ENABLE;
 902                 if (adjusted_mode->clock < 200000)
 903                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 904                 else
 905                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 906         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 907                 intel_dp->DP |= intel_dp->color_range;
 908
 909                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 910                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 911                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 912                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 913                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 914
 915                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 916                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 917
 918                 if (intel_crtc->pipe == 1)
 919                         intel_dp->DP |= DP_PIPEB_SELECT;
 920
 921                 if (is_cpu_edp(intel_dp)) {
 922                         /* don't miss out required setting for eDP */
 923                         intel_dp->DP |= DP_PLL_ENABLE;
 924                         if (adjusted_mode->clock < 200000)
 925                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 926                         else
 927                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 928                 }
 929         } else {
 930                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 931         }
 932 }
 933
 934 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 935 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 936
 937 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 938 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 939
 940 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 941 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 942
 943 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 944                                        u32 mask,
 945                                        u32 value)
 946 {
 947         struct drm_device *dev = intel_dp->base.base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949
 950         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 951                       mask, value,
 952                       I915_READ(PCH_PP_STATUS),
 953                       I915_READ(PCH_PP_CONTROL));
 954
 955         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 956                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 957                           I915_READ(PCH_PP_STATUS),
 958                           I915_READ(PCH_PP_CONTROL));
 959         }
 960 }
 961
 962 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 963 {
 964         DRM_DEBUG_KMS("Wait for panel power on\n");
 965         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 966 }
 967
 968 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 969 {
 970         DRM_DEBUG_KMS("Wait for panel power off time\n");
 971         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 972 }
 973
 974 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 975 {
 976         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 977         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 978 }
 979
 980
 981 /* Read the current pp_control value, unlocking the register if it
 982  * is locked
 983  */
 984
 985 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 986 {
 987         u32     control = I915_READ(PCH_PP_CONTROL);
 988
 989         control &= ~PANEL_UNLOCK_MASK;
 990         control |= PANEL_UNLOCK_REGS;
 991         return control;
 992 }
 993
 994 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 995 {
 996         struct drm_device *dev = intel_dp->base.base.dev;
 997         struct drm_i915_private *dev_priv = dev->dev_private;
 998         u32 pp;
 999
1000         if (!is_edp(intel_dp))
1001                 return;
1002         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1003
1004         WARN(intel_dp->want_panel_vdd,
1005              "eDP VDD already requested on\n");
1006
1007         intel_dp->want_panel_vdd = true;
1008
1009         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1010                 DRM_DEBUG_KMS("eDP VDD already on\n");
1011                 return;
1012         }
1013
1014         if (!ironlake_edp_have_panel_power(intel_dp))
1015                 ironlake_wait_panel_power_cycle(intel_dp);
1016
1017         pp = ironlake_get_pp_control(dev_priv);
1018         pp |= EDP_FORCE_VDD;
1019         I915_WRITE(PCH_PP_CONTROL, pp);
1020         POSTING_READ(PCH_PP_CONTROL);
1021         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1022                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1023
1024         /*
1025          * If the panel wasn't on, delay before accessing aux channel
1026          */
1027         if (!ironlake_edp_have_panel_power(intel_dp)) {
1028                 DRM_DEBUG_KMS("eDP was not running\n");
1029                 msleep(intel_dp->panel_power_up_delay);
1030         }
1031 }
1032
1033 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1034 {
1035         struct drm_device *dev = intel_dp->base.base.dev;
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         u32 pp;
1038
1039         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1040                 pp = ironlake_get_pp_control(dev_priv);
1041                 pp &= ~EDP_FORCE_VDD;
1042                 I915_WRITE(PCH_PP_CONTROL, pp);
1043                 POSTING_READ(PCH_PP_CONTROL);
1044
1045                 /* Make sure sequencer is idle before allowing subsequent activity */
1046                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1047                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1048
1049                 msleep(intel_dp->panel_power_down_delay);
1050         }
1051 }
1052
1053 static void ironlake_panel_vdd_work(struct work_struct *__work)
1054 {
1055         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1056                                                  struct intel_dp, panel_vdd_work);
1057         struct drm_device *dev = intel_dp->base.base.dev;
1058
1059         mutex_lock(&dev->mode_config.mutex);
1060         ironlake_panel_vdd_off_sync(intel_dp);
1061         mutex_unlock(&dev->mode_config.mutex);
1062 }
1063
1064 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1065 {
1066         if (!is_edp(intel_dp))
1067                 return;
1068
1069         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1070         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1071
1072         intel_dp->want_panel_vdd = false;
1073
1074         if (sync) {
1075                 ironlake_panel_vdd_off_sync(intel_dp);
1076         } else {
1077                 /*
1078                  * Queue the timer to fire a long
1079                  * time from now (relative to the power down delay)
1080                  * to keep the panel power up across a sequence of operations
1081                  */
1082                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1083                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1084         }
1085 }
1086
1087 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1088 {
1089         struct drm_device *dev = intel_dp->base.base.dev;
1090         struct drm_i915_private *dev_priv = dev->dev_private;
1091         u32 pp;
1092
1093         if (!is_edp(intel_dp))
1094                 return;
1095
1096         DRM_DEBUG_KMS("Turn eDP power on\n");
1097
1098         if (ironlake_edp_have_panel_power(intel_dp)) {
1099                 DRM_DEBUG_KMS("eDP power already on\n");
1100                 return;
1101         }
1102
1103         ironlake_wait_panel_power_cycle(intel_dp);
1104
1105         pp = ironlake_get_pp_control(dev_priv);
1106         if (IS_GEN5(dev)) {
1107                 /* ILK workaround: disable reset around power sequence */
1108                 pp &= ~PANEL_POWER_RESET;
1109                 I915_WRITE(PCH_PP_CONTROL, pp);
1110                 POSTING_READ(PCH_PP_CONTROL);
1111         }
1112
1113         pp |= POWER_TARGET_ON;
1114         if (!IS_GEN5(dev))
1115                 pp |= PANEL_POWER_RESET;
1116
1117         I915_WRITE(PCH_PP_CONTROL, pp);
1118         POSTING_READ(PCH_PP_CONTROL);
1119
1120         ironlake_wait_panel_on(intel_dp);
1121
1122         if (IS_GEN5(dev)) {
1123                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1124                 I915_WRITE(PCH_PP_CONTROL, pp);
1125                 POSTING_READ(PCH_PP_CONTROL);
1126         }
1127 }
1128
1129 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1130 {
1131         struct drm_device *dev = intel_dp->base.base.dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         u32 pp;
1134
1135         if (!is_edp(intel_dp))
1136                 return;
1137
1138         DRM_DEBUG_KMS("Turn eDP power off\n");
1139
1140         WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1141
1142         pp = ironlake_get_pp_control(dev_priv);
1143         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1144         I915_WRITE(PCH_PP_CONTROL, pp);
1145         POSTING_READ(PCH_PP_CONTROL);
1146
1147         ironlake_wait_panel_off(intel_dp);
1148 }
1149
1150 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1151 {
1152         struct drm_device *dev = intel_dp->base.base.dev;
1153         struct drm_i915_private *dev_priv = dev->dev_private;
1154         u32 pp;
1155
1156         if (!is_edp(intel_dp))
1157                 return;
1158
1159         DRM_DEBUG_KMS("\n");
1160         /*
1161          * If we enable the backlight right away following a panel power
1162          * on, we may see slight flicker as the panel syncs with the eDP
1163          * link.  So delay a bit to make sure the image is solid before
1164          * allowing it to appear.
1165          */
1166         msleep(intel_dp->backlight_on_delay);
1167         pp = ironlake_get_pp_control(dev_priv);
1168         pp |= EDP_BLC_ENABLE;
1169         I915_WRITE(PCH_PP_CONTROL, pp);
1170         POSTING_READ(PCH_PP_CONTROL);
1171 }
1172
1173 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1174 {
1175         struct drm_device *dev = intel_dp->base.base.dev;
1176         struct drm_i915_private *dev_priv = dev->dev_private;
1177         u32 pp;
1178
1179         if (!is_edp(intel_dp))
1180                 return;
1181
1182         DRM_DEBUG_KMS("\n");
1183         pp = ironlake_get_pp_control(dev_priv);
1184         pp &= ~EDP_BLC_ENABLE;
1185         I915_WRITE(PCH_PP_CONTROL, pp);
1186         POSTING_READ(PCH_PP_CONTROL);
1187         msleep(intel_dp->backlight_off_delay);
1188 }
1189
1190 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1191 {
1192         struct drm_device *dev = encoder->dev;
1193         struct drm_i915_private *dev_priv = dev->dev_private;
1194         u32 dpa_ctl;
1195
1196         DRM_DEBUG_KMS("\n");
1197         dpa_ctl = I915_READ(DP_A);
1198         dpa_ctl |= DP_PLL_ENABLE;
1199         I915_WRITE(DP_A, dpa_ctl);
1200         POSTING_READ(DP_A);
1201         udelay(200);
1202 }
1203
1204 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1205 {
1206         struct drm_device *dev = encoder->dev;
1207         struct drm_i915_private *dev_priv = dev->dev_private;
1208         u32 dpa_ctl;
1209
1210         dpa_ctl = I915_READ(DP_A);
1211         dpa_ctl &= ~DP_PLL_ENABLE;
1212         I915_WRITE(DP_A, dpa_ctl);
1213         POSTING_READ(DP_A);
1214         udelay(200);
1215 }
1216
1217 /* If the sink supports it, try to set the power state appropriately */
1218 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1219 {
1220         int ret, i;
1221
1222         /* Should have a valid DPCD by this point */
1223         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1224                 return;
1225
1226         if (mode != DRM_MODE_DPMS_ON) {
1227                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1228                                                   DP_SET_POWER_D3);
1229                 if (ret != 1)
1230                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1231         } else {
1232                 /*
1233                  * When turning on, we need to retry for 1ms to give the sink
1234                  * time to wake up.
1235                  */
1236                 for (i = 0; i < 3; i++) {
1237                         ret = intel_dp_aux_native_write_1(intel_dp,
1238                                                           DP_SET_POWER,
1239                                                           DP_SET_POWER_D0);
1240                         if (ret == 1)
1241                                 break;
1242                         msleep(1);
1243                 }
1244         }
1245 }
1246
1247 static void intel_dp_prepare(struct drm_encoder *encoder)
1248 {
1249         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1250
1251         ironlake_edp_backlight_off(intel_dp);
1252         ironlake_edp_panel_off(intel_dp);
1253
1254         /* Wake up the sink first */
1255         ironlake_edp_panel_vdd_on(intel_dp);
1256         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1257         intel_dp_link_down(intel_dp);
1258         ironlake_edp_panel_vdd_off(intel_dp, false);
1259
1260         /* Make sure the panel is off before trying to
1261          * change the mode
1262          */
1263 }
1264
1265 static void intel_dp_commit(struct drm_encoder *encoder)
1266 {
1267         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1268         struct drm_device *dev = encoder->dev;
1269         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1270
1271         ironlake_edp_panel_vdd_on(intel_dp);
1272         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1273         intel_dp_start_link_train(intel_dp);
1274         ironlake_edp_panel_on(intel_dp);
1275         ironlake_edp_panel_vdd_off(intel_dp, true);
1276         intel_dp_complete_link_train(intel_dp);
1277         ironlake_edp_backlight_on(intel_dp);
1278
1279         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1280
1281         if (HAS_PCH_CPT(dev))
1282                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1283 }
1284
1285 static void
1286 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1287 {
1288         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1289         struct drm_device *dev = encoder->dev;
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1292
1293         if (mode != DRM_MODE_DPMS_ON) {
1294                 ironlake_edp_backlight_off(intel_dp);
1295                 ironlake_edp_panel_off(intel_dp);
1296
1297                 ironlake_edp_panel_vdd_on(intel_dp);
1298                 intel_dp_sink_dpms(intel_dp, mode);
1299                 intel_dp_link_down(intel_dp);
1300                 ironlake_edp_panel_vdd_off(intel_dp, false);
1301
1302                 if (is_cpu_edp(intel_dp))
1303                         ironlake_edp_pll_off(encoder);
1304         } else {
1305                 if (is_cpu_edp(intel_dp))
1306                         ironlake_edp_pll_on(encoder);
1307
1308                 ironlake_edp_panel_vdd_on(intel_dp);
1309                 intel_dp_sink_dpms(intel_dp, mode);
1310                 if (!(dp_reg & DP_PORT_EN)) {
1311                         intel_dp_start_link_train(intel_dp);
1312                         ironlake_edp_panel_on(intel_dp);
1313                         ironlake_edp_panel_vdd_off(intel_dp, true);
1314                         intel_dp_complete_link_train(intel_dp);
1315                 } else
1316                         ironlake_edp_panel_vdd_off(intel_dp, false);
1317                 ironlake_edp_backlight_on(intel_dp);
1318         }
1319         intel_dp->dpms_mode = mode;
1320 }
1321
1322 /*
1323  * Native read with retry for link status and receiver capability reads for
1324  * cases where the sink may still be asleep.
1325  */
1326 static bool
1327 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1328                                uint8_t *recv, int recv_bytes)
1329 {
1330         int ret, i;
1331
1332         /*
1333          * Sinks are *supposed* to come up within 1ms from an off state,
1334          * but we're also supposed to retry 3 times per the spec.
1335          */
1336         for (i = 0; i < 3; i++) {
1337                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1338                                                recv_bytes);
1339                 if (ret == recv_bytes)
1340                         return true;
1341                 msleep(1);
1342         }
1343
1344         return false;
1345 }
1346
1347 /*
1348  * Fetch AUX CH registers 0x202 - 0x207 which contain
1349  * link status information
1350  */
1351 static bool
1352 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1353 {
1354         return intel_dp_aux_native_read_retry(intel_dp,
1355                                               DP_LANE0_1_STATUS,
1356                                               link_status,
1357                                               DP_LINK_STATUS_SIZE);
1358 }
1359
1360 static uint8_t
1361 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1362                      int r)
1363 {
1364         return link_status[r - DP_LANE0_1_STATUS];
1365 }
1366
1367 static uint8_t
1368 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1369                                  int lane)
1370 {
1371         int         s = ((lane & 1) ?
1372                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1373                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1374         uint8_t l = adjust_request[lane>>1];
1375
1376         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1377 }
1378
1379 static uint8_t
1380 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1381                                       int lane)
1382 {
1383         int         s = ((lane & 1) ?
1384                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1385                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1386         uint8_t l = adjust_request[lane>>1];
1387
1388         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1389 }
1390
1391
1392 #if 0
1393 static char     *voltage_names[] = {
1394         "0.4V", "0.6V", "0.8V", "1.2V"
1395 };
1396 static char     *pre_emph_names[] = {
1397         "0dB", "3.5dB", "6dB", "9.5dB"
1398 };
1399 static char     *link_train_names[] = {
1400         "pattern 1", "pattern 2", "idle", "off"
1401 };
1402 #endif
1403
1404 /*
1405  * These are source-specific values; current Intel hardware supports
1406  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1407  */
1408
1409 static uint8_t
1410 intel_dp_voltage_max(struct intel_dp *intel_dp)
1411 {
1412         struct drm_device *dev = intel_dp->base.base.dev;
1413
1414         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1415                 return DP_TRAIN_VOLTAGE_SWING_800;
1416         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1417                 return DP_TRAIN_VOLTAGE_SWING_1200;
1418         else
1419                 return DP_TRAIN_VOLTAGE_SWING_800;
1420 }
1421
1422 static uint8_t
1423 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1424 {
1425         struct drm_device *dev = intel_dp->base.base.dev;
1426
1427         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1428                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1429                 case DP_TRAIN_VOLTAGE_SWING_400:
1430                         return DP_TRAIN_PRE_EMPHASIS_6;
1431                 case DP_TRAIN_VOLTAGE_SWING_600:
1432                 case DP_TRAIN_VOLTAGE_SWING_800:
1433                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1434                 default:
1435                         return DP_TRAIN_PRE_EMPHASIS_0;
1436                 }
1437         } else {
1438                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1439                 case DP_TRAIN_VOLTAGE_SWING_400:
1440                         return DP_TRAIN_PRE_EMPHASIS_6;
1441                 case DP_TRAIN_VOLTAGE_SWING_600:
1442                         return DP_TRAIN_PRE_EMPHASIS_6;
1443                 case DP_TRAIN_VOLTAGE_SWING_800:
1444                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1445                 case DP_TRAIN_VOLTAGE_SWING_1200:
1446                 default:
1447                         return DP_TRAIN_PRE_EMPHASIS_0;
1448                 }
1449         }
1450 }
1451
1452 static void
1453 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1454 {
1455         uint8_t v = 0;
1456         uint8_t p = 0;
1457         int lane;
1458         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1459         uint8_t voltage_max;
1460         uint8_t preemph_max;
1461
1462         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1463                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1464                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1465
1466                 if (this_v > v)
1467                         v = this_v;
1468                 if (this_p > p)
1469                         p = this_p;
1470         }
1471
1472         voltage_max = intel_dp_voltage_max(intel_dp);
1473         if (v >= voltage_max)
1474                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1475
1476         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1477         if (p >= preemph_max)
1478                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1479
1480         for (lane = 0; lane < 4; lane++)
1481                 intel_dp->train_set[lane] = v | p;
1482 }
1483
1484 static uint32_t
1485 intel_dp_signal_levels(uint8_t train_set)
1486 {
1487         uint32_t        signal_levels = 0;
1488
1489         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1490         case DP_TRAIN_VOLTAGE_SWING_400:
1491         default:
1492                 signal_levels |= DP_VOLTAGE_0_4;
1493                 break;
1494         case DP_TRAIN_VOLTAGE_SWING_600:
1495                 signal_levels |= DP_VOLTAGE_0_6;
1496                 break;
1497         case DP_TRAIN_VOLTAGE_SWING_800:
1498                 signal_levels |= DP_VOLTAGE_0_8;
1499                 break;
1500         case DP_TRAIN_VOLTAGE_SWING_1200:
1501                 signal_levels |= DP_VOLTAGE_1_2;
1502                 break;
1503         }
1504         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1505         case DP_TRAIN_PRE_EMPHASIS_0:
1506         default:
1507                 signal_levels |= DP_PRE_EMPHASIS_0;
1508                 break;
1509         case DP_TRAIN_PRE_EMPHASIS_3_5:
1510                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1511                 break;
1512         case DP_TRAIN_PRE_EMPHASIS_6:
1513                 signal_levels |= DP_PRE_EMPHASIS_6;
1514                 break;
1515         case DP_TRAIN_PRE_EMPHASIS_9_5:
1516                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1517                 break;
1518         }
1519         return signal_levels;
1520 }
1521
1522 /* Gen6's DP voltage swing and pre-emphasis control */
1523 static uint32_t
1524 intel_gen6_edp_signal_levels(uint8_t train_set)
1525 {
1526         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1527                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1528         switch (signal_levels) {
1529         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1530         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1531                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1532         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1533                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1534         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1535         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1536                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1537         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1538         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1539                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1540         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1541         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1542                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1543         default:
1544                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1545                               "0x%x\n", signal_levels);
1546                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1547         }
1548 }
1549
1550 /* Gen7's DP voltage swing and pre-emphasis control */
1551 static uint32_t
1552 intel_gen7_edp_signal_levels(uint8_t train_set)
1553 {
1554         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1555                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1556         switch (signal_levels) {
1557         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1558                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1559         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1560                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1561         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1562                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1563
1564         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1565                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1566         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1567                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1568
1569         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1570                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1571         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1572                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1573
1574         default:
1575                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1576                               "0x%x\n", signal_levels);
1577                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1578         }
1579 }
1580
1581 static uint8_t
1582 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1583                       int lane)
1584 {
1585         int s = (lane & 1) * 4;
1586         uint8_t l = link_status[lane>>1];
1587
1588         return (l >> s) & 0xf;
1589 }
1590
1591 /* Check for clock recovery is done on all channels */
1592 static bool
1593 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1594 {
1595         int lane;
1596         uint8_t lane_status;
1597
1598         for (lane = 0; lane < lane_count; lane++) {
1599                 lane_status = intel_get_lane_status(link_status, lane);
1600                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1601                         return false;
1602         }
1603         return true;
1604 }
1605
1606 /* Check to see if channel eq is done on all channels */
1607 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1608                          DP_LANE_CHANNEL_EQ_DONE|\
1609                          DP_LANE_SYMBOL_LOCKED)
1610 static bool
1611 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1612 {
1613         uint8_t lane_align;
1614         uint8_t lane_status;
1615         int lane;
1616
1617         lane_align = intel_dp_link_status(link_status,
1618                                           DP_LANE_ALIGN_STATUS_UPDATED);
1619         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1620                 return false;
1621         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1622                 lane_status = intel_get_lane_status(link_status, lane);
1623                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1624                         return false;
1625         }
1626         return true;
1627 }
1628
1629 static bool
1630 intel_dp_set_link_train(struct intel_dp *intel_dp,
1631                         uint32_t dp_reg_value,
1632                         uint8_t dp_train_pat)
1633 {
1634         struct drm_device *dev = intel_dp->base.base.dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636         int ret;
1637
1638         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1639         POSTING_READ(intel_dp->output_reg);
1640
1641         intel_dp_aux_native_write_1(intel_dp,
1642                                     DP_TRAINING_PATTERN_SET,
1643                                     dp_train_pat);
1644
1645         ret = intel_dp_aux_native_write(intel_dp,
1646                                         DP_TRAINING_LANE0_SET,
1647                                         intel_dp->train_set,
1648                                         intel_dp->lane_count);
1649         if (ret != intel_dp->lane_count)
1650                 return false;
1651
1652         return true;
1653 }
1654
1655 /* Enable corresponding port and start training pattern 1 */
1656 static void
1657 intel_dp_start_link_train(struct intel_dp *intel_dp)
1658 {
1659         struct drm_device *dev = intel_dp->base.base.dev;
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1662         int i;
1663         uint8_t voltage;
1664         bool clock_recovery = false;
1665         int voltage_tries, loop_tries;
1666         u32 reg;
1667         uint32_t DP = intel_dp->DP;
1668
1669         /*
1670          * On CPT we have to enable the port in training pattern 1, which
1671          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1672          * the port and wait for it to become active.
1673          */
1674         if (!HAS_PCH_CPT(dev)) {
1675                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1676                 POSTING_READ(intel_dp->output_reg);
1677                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1678         }
1679
1680         /* Write the link configuration data */
1681         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1682                                   intel_dp->link_configuration,
1683                                   DP_LINK_CONFIGURATION_SIZE);
1684
1685         DP |= DP_PORT_EN;
1686
1687         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1688                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1689         else
1690                 DP &= ~DP_LINK_TRAIN_MASK;
1691         memset(intel_dp->train_set, 0, 4);
1692         voltage = 0xff;
1693         voltage_tries = 0;
1694         loop_tries = 0;
1695         clock_recovery = false;
1696         for (;;) {
1697                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1698                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1699                 uint32_t    signal_levels;
1700
1701
1702                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1703                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1704                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1705                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1706                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1707                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1708                 } else {
1709                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1710                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1711                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1712                 }
1713
1714                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1715                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1716                 else
1717                         reg = DP | DP_LINK_TRAIN_PAT_1;
1718
1719                 if (!intel_dp_set_link_train(intel_dp, reg,
1720                                              DP_TRAINING_PATTERN_1 |
1721                                              DP_LINK_SCRAMBLING_DISABLE))
1722                         break;
1723                 /* Set training pattern 1 */
1724
1725                 udelay(100);
1726                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1727                         DRM_ERROR("failed to get link status\n");
1728                         break;
1729                 }
1730
1731                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1732                         DRM_DEBUG_KMS("clock recovery OK\n");
1733                         clock_recovery = true;
1734                         break;
1735                 }
1736
1737                 /* Check to see if we've tried the max voltage */
1738                 for (i = 0; i < intel_dp->lane_count; i++)
1739                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1740                                 break;
1741                 if (i == intel_dp->lane_count) {
1742                         ++loop_tries;
1743                         if (loop_tries == 5) {
1744                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1745                                 break;
1746                         }
1747                         memset(intel_dp->train_set, 0, 4);
1748                         voltage_tries = 0;
1749                         continue;
1750                 }
1751
1752                 /* Check to see if we've tried the same voltage 5 times */
1753                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1754                         ++voltage_tries;
1755                         if (voltage_tries == 5) {
1756                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1757                                 break;
1758                         }
1759                 } else
1760                         voltage_tries = 0;
1761                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1762
1763                 /* Compute new intel_dp->train_set as requested by target */
1764                 intel_get_adjust_train(intel_dp, link_status);
1765         }
1766
1767         intel_dp->DP = DP;
1768 }
1769
1770 static void
1771 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1772 {
1773         struct drm_device *dev = intel_dp->base.base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         bool channel_eq = false;
1776         int tries, cr_tries;
1777         u32 reg;
1778         uint32_t DP = intel_dp->DP;
1779
1780         /* channel equalization */
1781         tries = 0;
1782         cr_tries = 0;
1783         channel_eq = false;
1784         for (;;) {
1785                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1786                 uint32_t    signal_levels;
1787                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1788
1789                 if (cr_tries > 5) {
1790                         DRM_ERROR("failed to train DP, aborting\n");
1791                         intel_dp_link_down(intel_dp);
1792                         break;
1793                 }
1794
1795                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1796                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1797                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1798                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1799                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1800                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1801                 } else {
1802                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1803                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1804                 }
1805
1806                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1807                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1808                 else
1809                         reg = DP | DP_LINK_TRAIN_PAT_2;
1810
1811                 /* channel eq pattern */
1812                 if (!intel_dp_set_link_train(intel_dp, reg,
1813                                              DP_TRAINING_PATTERN_2 |
1814                                              DP_LINK_SCRAMBLING_DISABLE))
1815                         break;
1816
1817                 udelay(400);
1818                 if (!intel_dp_get_link_status(intel_dp, link_status))
1819                         break;
1820
1821                 /* Make sure clock is still ok */
1822                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1823                         intel_dp_start_link_train(intel_dp);
1824                         cr_tries++;
1825                         continue;
1826                 }
1827
1828                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1829                         channel_eq = true;
1830                         break;
1831                 }
1832
1833                 /* Try 5 times, then try clock recovery if that fails */
1834                 if (tries > 5) {
1835                         intel_dp_link_down(intel_dp);
1836                         intel_dp_start_link_train(intel_dp);
1837                         tries = 0;
1838                         cr_tries++;
1839                         continue;
1840                 }
1841
1842                 /* Compute new intel_dp->train_set as requested by target */
1843                 intel_get_adjust_train(intel_dp, link_status);
1844                 ++tries;
1845         }
1846
1847         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1848                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1849         else
1850                 reg = DP | DP_LINK_TRAIN_OFF;
1851
1852         I915_WRITE(intel_dp->output_reg, reg);
1853         POSTING_READ(intel_dp->output_reg);
1854         intel_dp_aux_native_write_1(intel_dp,
1855                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1856 }
1857
1858 static void
1859 intel_dp_link_down(struct intel_dp *intel_dp)
1860 {
1861         struct drm_device *dev = intel_dp->base.base.dev;
1862         struct drm_i915_private *dev_priv = dev->dev_private;
1863         uint32_t DP = intel_dp->DP;
1864
1865         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1866                 return;
1867
1868         DRM_DEBUG_KMS("\n");
1869
1870         if (is_edp(intel_dp)) {
1871                 DP &= ~DP_PLL_ENABLE;
1872                 I915_WRITE(intel_dp->output_reg, DP);
1873                 POSTING_READ(intel_dp->output_reg);
1874                 udelay(100);
1875         }
1876
1877         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1878                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1879                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1880         } else {
1881                 DP &= ~DP_LINK_TRAIN_MASK;
1882                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1883         }
1884         POSTING_READ(intel_dp->output_reg);
1885
1886         msleep(17);
1887
1888         if (is_edp(intel_dp)) {
1889                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1890                         DP |= DP_LINK_TRAIN_OFF_CPT;
1891                 else
1892                         DP |= DP_LINK_TRAIN_OFF;
1893         }
1894
1895         if (!HAS_PCH_CPT(dev) &&
1896             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1897                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1898
1899                 /* Hardware workaround: leaving our transcoder select
1900                  * set to transcoder B while it's off will prevent the
1901                  * corresponding HDMI output on transcoder A.
1902                  *
1903                  * Combine this with another hardware workaround:
1904                  * transcoder select bit can only be cleared while the
1905                  * port is enabled.
1906                  */
1907                 DP &= ~DP_PIPEB_SELECT;
1908                 I915_WRITE(intel_dp->output_reg, DP);
1909
1910                 /* Changes to enable or select take place the vblank
1911                  * after being written.
1912                  */
1913                 if (crtc == NULL) {
1914                         /* We can arrive here never having been attached
1915                          * to a CRTC, for instance, due to inheriting
1916                          * random state from the BIOS.
1917                          *
1918                          * If the pipe is not running, play safe and
1919                          * wait for the clocks to stabilise before
1920                          * continuing.
1921                          */
1922                         POSTING_READ(intel_dp->output_reg);
1923                         msleep(50);
1924                 } else
1925                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1926         }
1927
1928         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1929         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1930         POSTING_READ(intel_dp->output_reg);
1931         msleep(intel_dp->panel_power_down_delay);
1932 }
1933
1934 static bool
1935 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1936 {
1937         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1938                                            sizeof(intel_dp->dpcd)) &&
1939             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1940                 return true;
1941         }
1942
1943         return false;
1944 }
1945
1946 static bool
1947 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1948 {
1949         int ret;
1950
1951         ret = intel_dp_aux_native_read_retry(intel_dp,
1952                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1953                                              sink_irq_vector, 1);
1954         if (!ret)
1955                 return false;
1956
1957         return true;
1958 }
1959
1960 static void
1961 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1962 {
1963         /* NAK by default */
1964         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1965 }
1966
1967 /*
1968  * According to DP spec
1969  * 5.1.2:
1970  *  1. Read DPCD
1971  *  2. Configure link according to Receiver Capabilities
1972  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1973  *  4. Check link status on receipt of hot-plug interrupt
1974  */
1975
1976 static void
1977 intel_dp_check_link_status(struct intel_dp *intel_dp)
1978 {
1979         u8 sink_irq_vector;
1980         u8 link_status[DP_LINK_STATUS_SIZE];
1981
1982         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1983                 return;
1984
1985         if (!intel_dp->base.base.crtc)
1986                 return;
1987
1988         /* Try to read receiver status if the link appears to be up */
1989         if (!intel_dp_get_link_status(intel_dp, link_status)) {
1990                 intel_dp_link_down(intel_dp);
1991                 return;
1992         }
1993
1994         /* Now read the DPCD to see if it's actually running */
1995         if (!intel_dp_get_dpcd(intel_dp)) {
1996                 intel_dp_link_down(intel_dp);
1997                 return;
1998         }
1999
2000         /* Try to read the source of the interrupt */
2001         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2002             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2003                 /* Clear interrupt source */
2004                 intel_dp_aux_native_write_1(intel_dp,
2005                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2006                                             sink_irq_vector);
2007
2008                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2009                         intel_dp_handle_test_request(intel_dp);
2010                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2011                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2012         }
2013
2014         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2015                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2016                               drm_get_encoder_name(&intel_dp->base.base));
2017                 intel_dp_start_link_train(intel_dp);
2018                 intel_dp_complete_link_train(intel_dp);
2019         }
2020 }
2021
2022 static enum drm_connector_status
2023 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2024 {
2025         if (intel_dp_get_dpcd(intel_dp))
2026                 return connector_status_connected;
2027         return connector_status_disconnected;
2028 }
2029
2030 static enum drm_connector_status
2031 ironlake_dp_detect(struct intel_dp *intel_dp)
2032 {
2033         enum drm_connector_status status;
2034
2035         /* Can't disconnect eDP, but you can close the lid... */
2036         if (is_edp(intel_dp)) {
2037                 status = intel_panel_detect(intel_dp->base.base.dev);
2038                 if (status == connector_status_unknown)
2039                         status = connector_status_connected;
2040                 return status;
2041         }
2042
2043         return intel_dp_detect_dpcd(intel_dp);
2044 }
2045
2046 static enum drm_connector_status
2047 g4x_dp_detect(struct intel_dp *intel_dp)
2048 {
2049         struct drm_device *dev = intel_dp->base.base.dev;
2050         struct drm_i915_private *dev_priv = dev->dev_private;
2051         uint32_t temp, bit;
2052
2053         switch (intel_dp->output_reg) {
2054         case DP_B:
2055                 bit = DPB_HOTPLUG_INT_STATUS;
2056                 break;
2057         case DP_C:
2058                 bit = DPC_HOTPLUG_INT_STATUS;
2059                 break;
2060         case DP_D:
2061                 bit = DPD_HOTPLUG_INT_STATUS;
2062                 break;
2063         default:
2064                 return connector_status_unknown;
2065         }
2066
2067         temp = I915_READ(PORT_HOTPLUG_STAT);
2068
2069         if ((temp & bit) == 0)
2070                 return connector_status_disconnected;
2071
2072         return intel_dp_detect_dpcd(intel_dp);
2073 }
2074
2075 static struct edid *
2076 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2077 {
2078         struct intel_dp *intel_dp = intel_attached_dp(connector);
2079         struct edid     *edid;
2080
2081         ironlake_edp_panel_vdd_on(intel_dp);
2082         edid = drm_get_edid(connector, adapter);
2083         ironlake_edp_panel_vdd_off(intel_dp, false);
2084         return edid;
2085 }
2086
2087 static int
2088 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2089 {
2090         struct intel_dp *intel_dp = intel_attached_dp(connector);
2091         int     ret;
2092
2093         ironlake_edp_panel_vdd_on(intel_dp);
2094         ret = intel_ddc_get_modes(connector, adapter);
2095         ironlake_edp_panel_vdd_off(intel_dp, false);
2096         return ret;
2097 }
2098
2099
2100 /**
2101  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2102  *
2103  * \return true if DP port is connected.
2104  * \return false if DP port is disconnected.
2105  */
2106 static enum drm_connector_status
2107 intel_dp_detect(struct drm_connector *connector, bool force)
2108 {
2109         struct intel_dp *intel_dp = intel_attached_dp(connector);
2110         struct drm_device *dev = intel_dp->base.base.dev;
2111         enum drm_connector_status status;
2112         struct edid *edid = NULL;
2113
2114         intel_dp->has_audio = false;
2115
2116         if (HAS_PCH_SPLIT(dev))
2117                 status = ironlake_dp_detect(intel_dp);
2118         else
2119                 status = g4x_dp_detect(intel_dp);
2120
2121         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2122                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2123                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2124                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2125
2126         if (status != connector_status_connected)
2127                 return status;
2128
2129         if (intel_dp->force_audio) {
2130                 intel_dp->has_audio = intel_dp->force_audio > 0;
2131         } else {
2132                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2133                 if (edid) {
2134                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2135                         connector->display_info.raw_edid = NULL;
2136                         kfree(edid);
2137                 }
2138         }
2139
2140         return connector_status_connected;
2141 }
2142
2143 static int intel_dp_get_modes(struct drm_connector *connector)
2144 {
2145         struct intel_dp *intel_dp = intel_attached_dp(connector);
2146         struct drm_device *dev = intel_dp->base.base.dev;
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         int ret;
2149
2150         /* We should parse the EDID data and find out if it has an audio sink
2151          */
2152
2153         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2154         if (ret) {
2155                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2156                         struct drm_display_mode *newmode;
2157                         list_for_each_entry(newmode, &connector->probed_modes,
2158                                             head) {
2159                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2160                                         intel_dp->panel_fixed_mode =
2161                                                 drm_mode_duplicate(dev, newmode);
2162                                         break;
2163                                 }
2164                         }
2165                 }
2166                 return ret;
2167         }
2168
2169         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2170         if (is_edp(intel_dp)) {
2171                 /* initialize panel mode from VBT if available for eDP */
2172                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2173                         intel_dp->panel_fixed_mode =
2174                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2175                         if (intel_dp->panel_fixed_mode) {
2176                                 intel_dp->panel_fixed_mode->type |=
2177                                         DRM_MODE_TYPE_PREFERRED;
2178                         }
2179                 }
2180                 if (intel_dp->panel_fixed_mode) {
2181                         struct drm_display_mode *mode;
2182                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2183                         drm_mode_probed_add(connector, mode);
2184                         return 1;
2185                 }
2186         }
2187         return 0;
2188 }
2189
2190 static bool
2191 intel_dp_detect_audio(struct drm_connector *connector)
2192 {
2193         struct intel_dp *intel_dp = intel_attached_dp(connector);
2194         struct edid *edid;
2195         bool has_audio = false;
2196
2197         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2198         if (edid) {
2199                 has_audio = drm_detect_monitor_audio(edid);
2200
2201                 connector->display_info.raw_edid = NULL;
2202                 kfree(edid);
2203         }
2204
2205         return has_audio;
2206 }
2207
2208 static int
2209 intel_dp_set_property(struct drm_connector *connector,
2210                       struct drm_property *property,
2211                       uint64_t val)
2212 {
2213         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2214         struct intel_dp *intel_dp = intel_attached_dp(connector);
2215         int ret;
2216
2217         ret = drm_connector_property_set_value(connector, property, val);
2218         if (ret)
2219                 return ret;
2220
2221         if (property == dev_priv->force_audio_property) {
2222                 int i = val;
2223                 bool has_audio;
2224
2225                 if (i == intel_dp->force_audio)
2226                         return 0;
2227
2228                 intel_dp->force_audio = i;
2229
2230                 if (i == 0)
2231                         has_audio = intel_dp_detect_audio(connector);
2232                 else
2233                         has_audio = i > 0;
2234
2235                 if (has_audio == intel_dp->has_audio)
2236                         return 0;
2237
2238                 intel_dp->has_audio = has_audio;
2239                 goto done;
2240         }
2241
2242         if (property == dev_priv->broadcast_rgb_property) {
2243                 if (val == !!intel_dp->color_range)
2244                         return 0;
2245
2246                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2247                 goto done;
2248         }
2249
2250         return -EINVAL;
2251
2252 done:
2253         if (intel_dp->base.base.crtc) {
2254                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2255                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2256                                          crtc->x, crtc->y,
2257                                          crtc->fb);
2258         }
2259
2260         return 0;
2261 }
2262
2263 static void
2264 intel_dp_destroy(struct drm_connector *connector)
2265 {
2266         struct drm_device *dev = connector->dev;
2267
2268         if (intel_dpd_is_edp(dev))
2269                 intel_panel_destroy_backlight(dev);
2270
2271         drm_sysfs_connector_remove(connector);
2272         drm_connector_cleanup(connector);
2273         kfree(connector);
2274 }
2275
2276 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2277 {
2278         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2279
2280         i2c_del_adapter(&intel_dp->adapter);
2281         drm_encoder_cleanup(encoder);
2282         if (is_edp(intel_dp)) {
2283                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2284                 ironlake_panel_vdd_off_sync(intel_dp);
2285         }
2286         kfree(intel_dp);
2287 }
2288
2289 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2290         .dpms = intel_dp_dpms,
2291         .mode_fixup = intel_dp_mode_fixup,
2292         .prepare = intel_dp_prepare,
2293         .mode_set = intel_dp_mode_set,
2294         .commit = intel_dp_commit,
2295 };
2296
2297 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2298         .dpms = drm_helper_connector_dpms,
2299         .detect = intel_dp_detect,
2300         .fill_modes = drm_helper_probe_single_connector_modes,
2301         .set_property = intel_dp_set_property,
2302         .destroy = intel_dp_destroy,
2303 };
2304
2305 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2306         .get_modes = intel_dp_get_modes,
2307         .mode_valid = intel_dp_mode_valid,
2308         .best_encoder = intel_best_encoder,
2309 };
2310
2311 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2312         .destroy = intel_dp_encoder_destroy,
2313 };
2314
2315 static void
2316 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2317 {
2318         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2319
2320         intel_dp_check_link_status(intel_dp);
2321 }
2322
2323 /* Return which DP Port should be selected for Transcoder DP control */
2324 int
2325 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2326 {
2327         struct drm_device *dev = crtc->dev;
2328         struct drm_mode_config *mode_config = &dev->mode_config;
2329         struct drm_encoder *encoder;
2330
2331         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2332                 struct intel_dp *intel_dp;
2333
2334                 if (encoder->crtc != crtc)
2335                         continue;
2336
2337                 intel_dp = enc_to_intel_dp(encoder);
2338                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2339                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2340                         return intel_dp->output_reg;
2341         }
2342
2343         return -1;
2344 }
2345
2346 /* check the VBT to see whether the eDP is on DP-D port */
2347 bool intel_dpd_is_edp(struct drm_device *dev)
2348 {
2349         struct drm_i915_private *dev_priv = dev->dev_private;
2350         struct child_device_config *p_child;
2351         int i;
2352
2353         if (!dev_priv->child_dev_num)
2354                 return false;
2355
2356         for (i = 0; i < dev_priv->child_dev_num; i++) {
2357                 p_child = dev_priv->child_dev + i;
2358
2359                 if (p_child->dvo_port == PORT_IDPD &&
2360                     p_child->device_type == DEVICE_TYPE_eDP)
2361                         return true;
2362         }
2363         return false;
2364 }
2365
2366 static void
2367 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2368 {
2369         intel_attach_force_audio_property(connector);
2370         intel_attach_broadcast_rgb_property(connector);
2371 }
2372
2373 void
2374 intel_dp_init(struct drm_device *dev, int output_reg)
2375 {
2376         struct drm_i915_private *dev_priv = dev->dev_private;
2377         struct drm_connector *connector;
2378         struct intel_dp *intel_dp;
2379         struct intel_encoder *intel_encoder;
2380         struct intel_connector *intel_connector;
2381         const char *name = NULL;
2382         int type;
2383
2384         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2385         if (!intel_dp)
2386                 return;
2387
2388         intel_dp->output_reg = output_reg;
2389         intel_dp->dpms_mode = -1;
2390
2391         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2392         if (!intel_connector) {
2393                 kfree(intel_dp);
2394                 return;
2395         }
2396         intel_encoder = &intel_dp->base;
2397
2398         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2399                 if (intel_dpd_is_edp(dev))
2400                         intel_dp->is_pch_edp = true;
2401
2402         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2403                 type = DRM_MODE_CONNECTOR_eDP;
2404                 intel_encoder->type = INTEL_OUTPUT_EDP;
2405         } else {
2406                 type = DRM_MODE_CONNECTOR_DisplayPort;
2407                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2408         }
2409
2410         connector = &intel_connector->base;
2411         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2412         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2413
2414         connector->polled = DRM_CONNECTOR_POLL_HPD;
2415
2416         if (output_reg == DP_B || output_reg == PCH_DP_B)
2417                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2418         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2419                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2420         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2421                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2422
2423         if (is_edp(intel_dp)) {
2424                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2425                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2426                                   ironlake_panel_vdd_work);
2427         }
2428
2429         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2430         connector->interlace_allowed = true;
2431         connector->doublescan_allowed = 0;
2432
2433         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2434                          DRM_MODE_ENCODER_TMDS);
2435         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2436
2437         intel_connector_attach_encoder(intel_connector, intel_encoder);
2438         drm_sysfs_connector_add(connector);
2439
2440         /* Set up the DDC bus. */
2441         switch (output_reg) {
2442                 case DP_A:
2443                         name = "DPDDC-A";
2444                         break;
2445                 case DP_B:
2446                 case PCH_DP_B:
2447                         dev_priv->hotplug_supported_mask |=
2448                                 HDMIB_HOTPLUG_INT_STATUS;
2449                         name = "DPDDC-B";
2450                         break;
2451                 case DP_C:
2452                 case PCH_DP_C:
2453                         dev_priv->hotplug_supported_mask |=
2454                                 HDMIC_HOTPLUG_INT_STATUS;
2455                         name = "DPDDC-C";
2456                         break;
2457                 case DP_D:
2458                 case PCH_DP_D:
2459                         dev_priv->hotplug_supported_mask |=
2460                                 HDMID_HOTPLUG_INT_STATUS;
2461                         name = "DPDDC-D";
2462                         break;
2463         }
2464
2465         /* Cache some DPCD data in the eDP case */
2466         if (is_edp(intel_dp)) {
2467                 bool ret;
2468                 struct edp_power_seq    cur, vbt;
2469                 u32 pp_on, pp_off, pp_div;
2470
2471                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2472                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2473                 pp_div = I915_READ(PCH_PP_DIVISOR);
2474
2475                 /* Pull timing values out of registers */
2476                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2477                         PANEL_POWER_UP_DELAY_SHIFT;
2478
2479                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2480                         PANEL_LIGHT_ON_DELAY_SHIFT;
2481
2482                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2483                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2484
2485                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2486                         PANEL_POWER_DOWN_DELAY_SHIFT;
2487
2488                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2489                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2490
2491                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2492                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2493
2494                 vbt = dev_priv->edp.pps;
2495
2496                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2497                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2498
2499 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2500
2501                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2502                 intel_dp->backlight_on_delay = get_delay(t8);
2503                 intel_dp->backlight_off_delay = get_delay(t9);
2504                 intel_dp->panel_power_down_delay = get_delay(t10);
2505                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2506
2507                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2508                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2509                               intel_dp->panel_power_cycle_delay);
2510
2511                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2512                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2513
2514                 ironlake_edp_panel_vdd_on(intel_dp);
2515                 ret = intel_dp_get_dpcd(intel_dp);
2516                 ironlake_edp_panel_vdd_off(intel_dp, false);
2517
2518                 if (ret) {
2519                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2520                                 dev_priv->no_aux_handshake =
2521                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2522                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2523                 } else {
2524                         /* if this fails, presume the device is a ghost */
2525                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2526                         intel_dp_encoder_destroy(&intel_dp->base.base);
2527                         intel_dp_destroy(&intel_connector->base);
2528                         return;
2529                 }
2530         }
2531
2532         intel_dp_i2c_init(intel_dp, intel_connector, name);
2533
2534         intel_encoder->hot_plug = intel_dp_hot_plug;
2535
2536         if (is_edp(intel_dp)) {
2537                 dev_priv->int_edp_connector = connector;
2538                 intel_panel_setup_backlight(dev);
2539         }
2540
2541         intel_dp_add_properties(intel_dp, connector);
2542
2543         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2544          * 0xd.  Failure to do so will result in spurious interrupts being
2545          * generated on the port when a cable is not attached.
2546          */
2547         if (IS_G4X(dev) && !IS_GM45(dev)) {
2548                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2549                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2550         }
2551 }