drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_RECEIVER_CAP_SIZE    0xf
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 /**
  44  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  45  * @intel_dp: DP struct
  46  *
  47  * If a CPU or PCH DP output is attached to an eDP panel, this function
  48  * will return true, and false otherwise.
  49  */
  50 static bool is_edp(struct intel_dp *intel_dp)
  51 {
  52         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  80 {
  81         return container_of(intel_attached_encoder(connector),
  82                             struct intel_dp, base);
  83 }
  84
  85 /**
  86  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  87  * @encoder: DRM encoder
  88  *
  89  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  90  * by intel_display.c.
  91  */
  92 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  93 {
  94         struct intel_dp *intel_dp;
  95
  96         if (!encoder)
  97                 return false;
  98
  99         intel_dp = enc_to_intel_dp(encoder);
 100
 101         return is_pch_edp(intel_dp);
 102 }
 103
 104 static void intel_dp_link_down(struct intel_dp *intel_dp);
 105
 106 void
 107 intel_edp_link_config(struct intel_encoder *intel_encoder,
 108                        int *lane_num, int *link_bw)
 109 {
 110         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 111
 112         *lane_num = intel_dp->lane_count;
 113         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 114                 *link_bw = 162000;
 115         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 116                 *link_bw = 270000;
 117 }
 118
 119 int
 120 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 121                        struct drm_display_mode *mode)
 122 {
 123         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 124
 125         if (intel_dp->panel_fixed_mode)
 126                 return intel_dp->panel_fixed_mode->clock;
 127         else
 128                 return mode->clock;
 129 }
 130
 131 static int
 132 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 133 {
 134         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 135         switch (max_lane_count) {
 136         case 1: case 2: case 4:
 137                 break;
 138         default:
 139                 max_lane_count = 4;
 140         }
 141         return max_lane_count;
 142 }
 143
 144 static int
 145 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 146 {
 147         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 148
 149         switch (max_link_bw) {
 150         case DP_LINK_BW_1_62:
 151         case DP_LINK_BW_2_7:
 152                 break;
 153         default:
 154                 max_link_bw = DP_LINK_BW_1_62;
 155                 break;
 156         }
 157         return max_link_bw;
 158 }
 159
 160 static int
 161 intel_dp_link_clock(uint8_t link_bw)
 162 {
 163         if (link_bw == DP_LINK_BW_2_7)
 164                 return 270000;
 165         else
 166                 return 162000;
 167 }
 168
 169 /*
 170  * The units on the numbers in the next two are... bizarre.  Examples will
 171  * make it clearer; this one parallels an example in the eDP spec.
 172  *
 173  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 174  *
 175  *     270000 * 1 * 8 / 10 == 216000
 176  *
 177  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 178  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 179  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 180  * 119000.  At 18bpp that's 2142000 kilobits per second.
 181  *
 182  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 183  * get the result in decakilobits instead of kilobits.
 184  */
 185
 186 static int
 187 intel_dp_link_required(int pixel_clock, int bpp)
 188 {
 189         return (pixel_clock * bpp + 9) / 10;
 190 }
 191
 192 static int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         return (max_link_clock * max_lanes * 8) / 10;
 196 }
 197
 198 static bool
 199 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 200                           struct drm_display_mode *mode,
 201                           bool adjust_mode)
 202 {
 203         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 204         int max_lanes = intel_dp_max_lane_count(intel_dp);
 205         int max_rate, mode_rate;
 206
 207         mode_rate = intel_dp_link_required(mode->clock, 24);
 208         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 209
 210         if (mode_rate > max_rate) {
 211                 mode_rate = intel_dp_link_required(mode->clock, 18);
 212                 if (mode_rate > max_rate)
 213                         return false;
 214
 215                 if (adjust_mode)
 216                         mode->private_flags
 217                                 |= INTEL_MODE_DP_FORCE_6BPC;
 218
 219                 return true;
 220         }
 221
 222         return true;
 223 }
 224
 225 static int
 226 intel_dp_mode_valid(struct drm_connector *connector,
 227                     struct drm_display_mode *mode)
 228 {
 229         struct intel_dp *intel_dp = intel_attached_dp(connector);
 230
 231         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 232                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 233                         return MODE_PANEL;
 234
 235                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 236                         return MODE_PANEL;
 237         }
 238
 239         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 240                 return MODE_CLOCK_HIGH;
 241
 242         if (mode->clock < 10000)
 243                 return MODE_CLOCK_LOW;
 244
 245         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 246                 return MODE_H_ILLEGAL;
 247
 248         return MODE_OK;
 249 }
 250
 251 static uint32_t
 252 pack_aux(uint8_t *src, int src_bytes)
 253 {
 254         int     i;
 255         uint32_t v = 0;
 256
 257         if (src_bytes > 4)
 258                 src_bytes = 4;
 259         for (i = 0; i < src_bytes; i++)
 260                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 261         return v;
 262 }
 263
 264 static void
 265 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 266 {
 267         int i;
 268         if (dst_bytes > 4)
 269                 dst_bytes = 4;
 270         for (i = 0; i < dst_bytes; i++)
 271                 dst[i] = src >> ((3-i) * 8);
 272 }
 273
 274 /* hrawclock is 1/4 the FSB frequency */
 275 static int
 276 intel_hrawclk(struct drm_device *dev)
 277 {
 278         struct drm_i915_private *dev_priv = dev->dev_private;
 279         uint32_t clkcfg;
 280
 281         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 282         if (IS_VALLEYVIEW(dev))
 283                 return 200;
 284
 285         clkcfg = I915_READ(CLKCFG);
 286         switch (clkcfg & CLKCFG_FSB_MASK) {
 287         case CLKCFG_FSB_400:
 288                 return 100;
 289         case CLKCFG_FSB_533:
 290                 return 133;
 291         case CLKCFG_FSB_667:
 292                 return 166;
 293         case CLKCFG_FSB_800:
 294                 return 200;
 295         case CLKCFG_FSB_1067:
 296                 return 266;
 297         case CLKCFG_FSB_1333:
 298                 return 333;
 299         /* these two are just a guess; one of them might be right */
 300         case CLKCFG_FSB_1600:
 301         case CLKCFG_FSB_1600_ALT:
 302                 return 400;
 303         default:
 304                 return 133;
 305         }
 306 }
 307
 308 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 309 {
 310         struct drm_device *dev = intel_dp->base.base.dev;
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312
 313         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 314 }
 315
 316 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 317 {
 318         struct drm_device *dev = intel_dp->base.base.dev;
 319         struct drm_i915_private *dev_priv = dev->dev_private;
 320
 321         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 322 }
 323
 324 static void
 325 intel_dp_check_edp(struct intel_dp *intel_dp)
 326 {
 327         struct drm_device *dev = intel_dp->base.base.dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329
 330         if (!is_edp(intel_dp))
 331                 return;
 332         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 333                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 334                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 335                               I915_READ(PCH_PP_STATUS),
 336                               I915_READ(PCH_PP_CONTROL));
 337         }
 338 }
 339
 340 static int
 341 intel_dp_aux_ch(struct intel_dp *intel_dp,
 342                 uint8_t *send, int send_bytes,
 343                 uint8_t *recv, int recv_size)
 344 {
 345         uint32_t output_reg = intel_dp->output_reg;
 346         struct drm_device *dev = intel_dp->base.base.dev;
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348         uint32_t ch_ctl = output_reg + 0x10;
 349         uint32_t ch_data = ch_ctl + 4;
 350         int i;
 351         int recv_bytes;
 352         uint32_t status;
 353         uint32_t aux_clock_divider;
 354         int try, precharge;
 355
 356         if (IS_HASWELL(dev)) {
 357                 switch (intel_dp->port) {
 358                 case PORT_A:
 359                         ch_ctl = DPA_AUX_CH_CTL;
 360                         ch_data = DPA_AUX_CH_DATA1;
 361                         break;
 362                 case PORT_B:
 363                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 364                         ch_data = PCH_DPB_AUX_CH_DATA1;
 365                         break;
 366                 case PORT_C:
 367                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 368                         ch_data = PCH_DPC_AUX_CH_DATA1;
 369                         break;
 370                 case PORT_D:
 371                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 372                         ch_data = PCH_DPD_AUX_CH_DATA1;
 373                         break;
 374                 default:
 375                         BUG();
 376                 }
 377         }
 378
 379         intel_dp_check_edp(intel_dp);
 380         /* The clock divider is based off the hrawclk,
 381          * and would like to run at 2MHz. So, take the
 382          * hrawclk value and divide by 2 and use that
 383          *
 384          * Note that PCH attached eDP panels should use a 125MHz input
 385          * clock divider.
 386          */
 387         if (is_cpu_edp(intel_dp)) {
 388                 if (IS_VALLEYVIEW(dev))
 389                         aux_clock_divider = 100;
 390                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 391                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 392                 else
 393                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 394         } else if (HAS_PCH_SPLIT(dev))
 395                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 396         else
 397                 aux_clock_divider = intel_hrawclk(dev) / 2;
 398
 399         if (IS_GEN6(dev))
 400                 precharge = 3;
 401         else
 402                 precharge = 5;
 403
 404         /* Try to wait for any previous AUX channel activity */
 405         for (try = 0; try < 3; try++) {
 406                 status = I915_READ(ch_ctl);
 407                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 408                         break;
 409                 msleep(1);
 410         }
 411
 412         if (try == 3) {
 413                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 414                      I915_READ(ch_ctl));
 415                 return -EBUSY;
 416         }
 417
 418         /* Must try at least 3 times according to DP spec */
 419         for (try = 0; try < 5; try++) {
 420                 /* Load the send data into the aux channel data registers */
 421                 for (i = 0; i < send_bytes; i += 4)
 422                         I915_WRITE(ch_data + i,
 423                                    pack_aux(send + i, send_bytes - i));
 424
 425                 /* Send the command and wait for it to complete */
 426                 I915_WRITE(ch_ctl,
 427                            DP_AUX_CH_CTL_SEND_BUSY |
 428                            DP_AUX_CH_CTL_TIME_OUT_400us |
 429                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 430                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 431                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 432                            DP_AUX_CH_CTL_DONE |
 433                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 434                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 435                 for (;;) {
 436                         status = I915_READ(ch_ctl);
 437                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 438                                 break;
 439                         udelay(100);
 440                 }
 441
 442                 /* Clear done status and any errors */
 443                 I915_WRITE(ch_ctl,
 444                            status |
 445                            DP_AUX_CH_CTL_DONE |
 446                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 447                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 448
 449                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 450                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 451                         continue;
 452                 if (status & DP_AUX_CH_CTL_DONE)
 453                         break;
 454         }
 455
 456         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 457                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 458                 return -EBUSY;
 459         }
 460
 461         /* Check for timeout or receive error.
 462          * Timeouts occur when the sink is not connected
 463          */
 464         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 465                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 466                 return -EIO;
 467         }
 468
 469         /* Timeouts occur when the device isn't connected, so they're
 470          * "normal" -- don't fill the kernel log with these */
 471         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 472                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 473                 return -ETIMEDOUT;
 474         }
 475
 476         /* Unload any bytes sent back from the other side */
 477         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 478                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 479         if (recv_bytes > recv_size)
 480                 recv_bytes = recv_size;
 481
 482         for (i = 0; i < recv_bytes; i += 4)
 483                 unpack_aux(I915_READ(ch_data + i),
 484                            recv + i, recv_bytes - i);
 485
 486         return recv_bytes;
 487 }
 488
 489 /* Write data to the aux channel in native mode */
 490 static int
 491 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 492                           uint16_t address, uint8_t *send, int send_bytes)
 493 {
 494         int ret;
 495         uint8_t msg[20];
 496         int msg_bytes;
 497         uint8_t ack;
 498
 499         intel_dp_check_edp(intel_dp);
 500         if (send_bytes > 16)
 501                 return -1;
 502         msg[0] = AUX_NATIVE_WRITE << 4;
 503         msg[1] = address >> 8;
 504         msg[2] = address & 0xff;
 505         msg[3] = send_bytes - 1;
 506         memcpy(&msg[4], send, send_bytes);
 507         msg_bytes = send_bytes + 4;
 508         for (;;) {
 509                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 510                 if (ret < 0)
 511                         return ret;
 512                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 513                         break;
 514                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 515                         udelay(100);
 516                 else
 517                         return -EIO;
 518         }
 519         return send_bytes;
 520 }
 521
 522 /* Write a single byte to the aux channel in native mode */
 523 static int
 524 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 525                             uint16_t address, uint8_t byte)
 526 {
 527         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 528 }
 529
 530 /* read bytes from a native aux channel */
 531 static int
 532 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 533                          uint16_t address, uint8_t *recv, int recv_bytes)
 534 {
 535         uint8_t msg[4];
 536         int msg_bytes;
 537         uint8_t reply[20];
 538         int reply_bytes;
 539         uint8_t ack;
 540         int ret;
 541
 542         intel_dp_check_edp(intel_dp);
 543         msg[0] = AUX_NATIVE_READ << 4;
 544         msg[1] = address >> 8;
 545         msg[2] = address & 0xff;
 546         msg[3] = recv_bytes - 1;
 547
 548         msg_bytes = 4;
 549         reply_bytes = recv_bytes + 1;
 550
 551         for (;;) {
 552                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 553                                       reply, reply_bytes);
 554                 if (ret == 0)
 555                         return -EPROTO;
 556                 if (ret < 0)
 557                         return ret;
 558                 ack = reply[0];
 559                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 560                         memcpy(recv, reply + 1, ret - 1);
 561                         return ret - 1;
 562                 }
 563                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 564                         udelay(100);
 565                 else
 566                         return -EIO;
 567         }
 568 }
 569
 570 static int
 571 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 572                     uint8_t write_byte, uint8_t *read_byte)
 573 {
 574         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 575         struct intel_dp *intel_dp = container_of(adapter,
 576                                                 struct intel_dp,
 577                                                 adapter);
 578         uint16_t address = algo_data->address;
 579         uint8_t msg[5];
 580         uint8_t reply[2];
 581         unsigned retry;
 582         int msg_bytes;
 583         int reply_bytes;
 584         int ret;
 585
 586         intel_dp_check_edp(intel_dp);
 587         /* Set up the command byte */
 588         if (mode & MODE_I2C_READ)
 589                 msg[0] = AUX_I2C_READ << 4;
 590         else
 591                 msg[0] = AUX_I2C_WRITE << 4;
 592
 593         if (!(mode & MODE_I2C_STOP))
 594                 msg[0] |= AUX_I2C_MOT << 4;
 595
 596         msg[1] = address >> 8;
 597         msg[2] = address;
 598
 599         switch (mode) {
 600         case MODE_I2C_WRITE:
 601                 msg[3] = 0;
 602                 msg[4] = write_byte;
 603                 msg_bytes = 5;
 604                 reply_bytes = 1;
 605                 break;
 606         case MODE_I2C_READ:
 607                 msg[3] = 0;
 608                 msg_bytes = 4;
 609                 reply_bytes = 2;
 610                 break;
 611         default:
 612                 msg_bytes = 3;
 613                 reply_bytes = 1;
 614                 break;
 615         }
 616
 617         for (retry = 0; retry < 5; retry++) {
 618                 ret = intel_dp_aux_ch(intel_dp,
 619                                       msg, msg_bytes,
 620                                       reply, reply_bytes);
 621                 if (ret < 0) {
 622                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 623                         return ret;
 624                 }
 625
 626                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 627                 case AUX_NATIVE_REPLY_ACK:
 628                         /* I2C-over-AUX Reply field is only valid
 629                          * when paired with AUX ACK.
 630                          */
 631                         break;
 632                 case AUX_NATIVE_REPLY_NACK:
 633                         DRM_DEBUG_KMS("aux_ch native nack\n");
 634                         return -EREMOTEIO;
 635                 case AUX_NATIVE_REPLY_DEFER:
 636                         udelay(100);
 637                         continue;
 638                 default:
 639                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 640                                   reply[0]);
 641                         return -EREMOTEIO;
 642                 }
 643
 644                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 645                 case AUX_I2C_REPLY_ACK:
 646                         if (mode == MODE_I2C_READ) {
 647                                 *read_byte = reply[1];
 648                         }
 649                         return reply_bytes - 1;
 650                 case AUX_I2C_REPLY_NACK:
 651                         DRM_DEBUG_KMS("aux_i2c nack\n");
 652                         return -EREMOTEIO;
 653                 case AUX_I2C_REPLY_DEFER:
 654                         DRM_DEBUG_KMS("aux_i2c defer\n");
 655                         udelay(100);
 656                         break;
 657                 default:
 658                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 659                         return -EREMOTEIO;
 660                 }
 661         }
 662
 663         DRM_ERROR("too many retries, giving up\n");
 664         return -EREMOTEIO;
 665 }
 666
 667 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 668 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 669
 670 static int
 671 intel_dp_i2c_init(struct intel_dp *intel_dp,
 672                   struct intel_connector *intel_connector, const char *name)
 673 {
 674         int     ret;
 675
 676         DRM_DEBUG_KMS("i2c_init %s\n", name);
 677         intel_dp->algo.running = false;
 678         intel_dp->algo.address = 0;
 679         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 680
 681         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 682         intel_dp->adapter.owner = THIS_MODULE;
 683         intel_dp->adapter.class = I2C_CLASS_DDC;
 684         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 685         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 686         intel_dp->adapter.algo_data = &intel_dp->algo;
 687         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 688
 689         ironlake_edp_panel_vdd_on(intel_dp);
 690         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 691         ironlake_edp_panel_vdd_off(intel_dp, false);
 692         return ret;
 693 }
 694
 695 static bool
 696 intel_dp_mode_fixup(struct drm_encoder *encoder,
 697                     const struct drm_display_mode *mode,
 698                     struct drm_display_mode *adjusted_mode)
 699 {
 700         struct drm_device *dev = encoder->dev;
 701         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 702         int lane_count, clock;
 703         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 704         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 705         int bpp, mode_rate;
 706         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 707
 708         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 709                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 710                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 711                                         mode, adjusted_mode);
 712         }
 713
 714         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 715                 return false;
 716
 717         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 718                       "max bw %02x pixel clock %iKHz\n",
 719                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 720
 721         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 722                 return false;
 723
 724         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 725         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 726
 727         for (clock = 0; clock <= max_clock; clock++) {
 728                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 729                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 730
 731                         if (mode_rate <= link_avail) {
 732                                 intel_dp->link_bw = bws[clock];
 733                                 intel_dp->lane_count = lane_count;
 734                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 735                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 736                                                 "count %d clock %d bpp %d\n",
 737                                        intel_dp->link_bw, intel_dp->lane_count,
 738                                        adjusted_mode->clock, bpp);
 739                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 740                                               mode_rate, link_avail);
 741                                 return true;
 742                         }
 743                 }
 744         }
 745
 746         return false;
 747 }
 748
 749 struct intel_dp_m_n {
 750         uint32_t        tu;
 751         uint32_t        gmch_m;
 752         uint32_t        gmch_n;
 753         uint32_t        link_m;
 754         uint32_t        link_n;
 755 };
 756
 757 static void
 758 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 759 {
 760         while (*num > 0xffffff || *den > 0xffffff) {
 761                 *num >>= 1;
 762                 *den >>= 1;
 763         }
 764 }
 765
 766 static void
 767 intel_dp_compute_m_n(int bpp,
 768                      int nlanes,
 769                      int pixel_clock,
 770                      int link_clock,
 771                      struct intel_dp_m_n *m_n)
 772 {
 773         m_n->tu = 64;
 774         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 775         m_n->gmch_n = link_clock * nlanes;
 776         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 777         m_n->link_m = pixel_clock;
 778         m_n->link_n = link_clock;
 779         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 780 }
 781
 782 void
 783 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 784                  struct drm_display_mode *adjusted_mode)
 785 {
 786         struct drm_device *dev = crtc->dev;
 787         struct intel_encoder *encoder;
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 790         int lane_count = 4;
 791         struct intel_dp_m_n m_n;
 792         int pipe = intel_crtc->pipe;
 793
 794         /*
 795          * Find the lane count in the intel_encoder private
 796          */
 797         for_each_encoder_on_crtc(dev, crtc, encoder) {
 798                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 799
 800                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 801                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 802                 {
 803                         lane_count = intel_dp->lane_count;
 804                         break;
 805                 }
 806         }
 807
 808         /*
 809          * Compute the GMCH and Link ratios. The '3' here is
 810          * the number of bytes_per_pixel post-LUT, which we always
 811          * set up for 8-bits of R/G/B, or 3 bytes total.
 812          */
 813         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 814                              mode->clock, adjusted_mode->clock, &m_n);
 815
 816         if (IS_HASWELL(dev)) {
 817                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 818                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 819                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 820                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 821         } else if (HAS_PCH_SPLIT(dev)) {
 822                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 823                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 824                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 825                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 826         } else if (IS_VALLEYVIEW(dev)) {
 827                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 828                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 829                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 830                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 831         } else {
 832                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 833                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 834                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 835                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 836                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 837         }
 838 }
 839
 840 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 841 {
 842         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 843         intel_dp->link_configuration[0] = intel_dp->link_bw;
 844         intel_dp->link_configuration[1] = intel_dp->lane_count;
 845         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 846         /*
 847          * Check for DPCD version > 1.1 and enhanced framing support
 848          */
 849         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 850             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 851                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 852         }
 853 }
 854
 855 static void
 856 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 857                   struct drm_display_mode *adjusted_mode)
 858 {
 859         struct drm_device *dev = encoder->dev;
 860         struct drm_i915_private *dev_priv = dev->dev_private;
 861         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 862         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 864
 865         /*
 866          * There are four kinds of DP registers:
 867          *
 868          *      IBX PCH
 869          *      SNB CPU
 870          *      IVB CPU
 871          *      CPT PCH
 872          *
 873          * IBX PCH and CPU are the same for almost everything,
 874          * except that the CPU DP PLL is configured in this
 875          * register
 876          *
 877          * CPT PCH is quite different, having many bits moved
 878          * to the TRANS_DP_CTL register instead. That
 879          * configuration happens (oddly) in ironlake_pch_enable
 880          */
 881
 882         /* Preserve the BIOS-computed detected bit. This is
 883          * supposed to be read-only.
 884          */
 885         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 886
 887         /* Handle DP bits in common between all three register formats */
 888         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 889
 890         switch (intel_dp->lane_count) {
 891         case 1:
 892                 intel_dp->DP |= DP_PORT_WIDTH_1;
 893                 break;
 894         case 2:
 895                 intel_dp->DP |= DP_PORT_WIDTH_2;
 896                 break;
 897         case 4:
 898                 intel_dp->DP |= DP_PORT_WIDTH_4;
 899                 break;
 900         }
 901         if (intel_dp->has_audio) {
 902                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 903                                  pipe_name(intel_crtc->pipe));
 904                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 905                 intel_write_eld(encoder, adjusted_mode);
 906         }
 907
 908         intel_dp_init_link_config(intel_dp);
 909
 910         /* Split out the IBX/CPU vs CPT settings */
 911
 912         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 913                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 914                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 915                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 916                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 917                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 918
 919                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 920                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 921
 922                 intel_dp->DP |= intel_crtc->pipe << 29;
 923
 924                 /* don't miss out required setting for eDP */
 925                 if (adjusted_mode->clock < 200000)
 926                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 927                 else
 928                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 929         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 930                 intel_dp->DP |= intel_dp->color_range;
 931
 932                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 933                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 934                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 935                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 936                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 937
 938                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 939                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 940
 941                 if (intel_crtc->pipe == 1)
 942                         intel_dp->DP |= DP_PIPEB_SELECT;
 943
 944                 if (is_cpu_edp(intel_dp)) {
 945                         /* don't miss out required setting for eDP */
 946                         if (adjusted_mode->clock < 200000)
 947                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 948                         else
 949                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 950                 }
 951         } else {
 952                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 953         }
 954 }
 955
 956 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 957 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 958
 959 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 960 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 961
 962 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 963 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 964
 965 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 966                                        u32 mask,
 967                                        u32 value)
 968 {
 969         struct drm_device *dev = intel_dp->base.base.dev;
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971
 972         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 973                       mask, value,
 974                       I915_READ(PCH_PP_STATUS),
 975                       I915_READ(PCH_PP_CONTROL));
 976
 977         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 978                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 979                           I915_READ(PCH_PP_STATUS),
 980                           I915_READ(PCH_PP_CONTROL));
 981         }
 982 }
 983
 984 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 985 {
 986         DRM_DEBUG_KMS("Wait for panel power on\n");
 987         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 988 }
 989
 990 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 991 {
 992         DRM_DEBUG_KMS("Wait for panel power off time\n");
 993         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 994 }
 995
 996 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 997 {
 998         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 999         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1000 }
1001
1002
1003 /* Read the current pp_control value, unlocking the register if it
1004  * is locked
1005  */
1006
1007 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1008 {
1009         u32     control = I915_READ(PCH_PP_CONTROL);
1010
1011         control &= ~PANEL_UNLOCK_MASK;
1012         control |= PANEL_UNLOCK_REGS;
1013         return control;
1014 }
1015
1016 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1017 {
1018         struct drm_device *dev = intel_dp->base.base.dev;
1019         struct drm_i915_private *dev_priv = dev->dev_private;
1020         u32 pp;
1021
1022         if (!is_edp(intel_dp))
1023                 return;
1024         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1025
1026         WARN(intel_dp->want_panel_vdd,
1027              "eDP VDD already requested on\n");
1028
1029         intel_dp->want_panel_vdd = true;
1030
1031         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1032                 DRM_DEBUG_KMS("eDP VDD already on\n");
1033                 return;
1034         }
1035
1036         if (!ironlake_edp_have_panel_power(intel_dp))
1037                 ironlake_wait_panel_power_cycle(intel_dp);
1038
1039         pp = ironlake_get_pp_control(dev_priv);
1040         pp |= EDP_FORCE_VDD;
1041         I915_WRITE(PCH_PP_CONTROL, pp);
1042         POSTING_READ(PCH_PP_CONTROL);
1043         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1044                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1045
1046         /*
1047          * If the panel wasn't on, delay before accessing aux channel
1048          */
1049         if (!ironlake_edp_have_panel_power(intel_dp)) {
1050                 DRM_DEBUG_KMS("eDP was not running\n");
1051                 msleep(intel_dp->panel_power_up_delay);
1052         }
1053 }
1054
1055 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1056 {
1057         struct drm_device *dev = intel_dp->base.base.dev;
1058         struct drm_i915_private *dev_priv = dev->dev_private;
1059         u32 pp;
1060
1061         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1062                 pp = ironlake_get_pp_control(dev_priv);
1063                 pp &= ~EDP_FORCE_VDD;
1064                 I915_WRITE(PCH_PP_CONTROL, pp);
1065                 POSTING_READ(PCH_PP_CONTROL);
1066
1067                 /* Make sure sequencer is idle before allowing subsequent activity */
1068                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1069                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1070
1071                 msleep(intel_dp->panel_power_down_delay);
1072         }
1073 }
1074
1075 static void ironlake_panel_vdd_work(struct work_struct *__work)
1076 {
1077         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1078                                                  struct intel_dp, panel_vdd_work);
1079         struct drm_device *dev = intel_dp->base.base.dev;
1080
1081         mutex_lock(&dev->mode_config.mutex);
1082         ironlake_panel_vdd_off_sync(intel_dp);
1083         mutex_unlock(&dev->mode_config.mutex);
1084 }
1085
1086 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1087 {
1088         if (!is_edp(intel_dp))
1089                 return;
1090
1091         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1092         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1093
1094         intel_dp->want_panel_vdd = false;
1095
1096         if (sync) {
1097                 ironlake_panel_vdd_off_sync(intel_dp);
1098         } else {
1099                 /*
1100                  * Queue the timer to fire a long
1101                  * time from now (relative to the power down delay)
1102                  * to keep the panel power up across a sequence of operations
1103                  */
1104                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1105                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1106         }
1107 }
1108
1109 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1110 {
1111         struct drm_device *dev = intel_dp->base.base.dev;
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113         u32 pp;
1114
1115         if (!is_edp(intel_dp))
1116                 return;
1117
1118         DRM_DEBUG_KMS("Turn eDP power on\n");
1119
1120         if (ironlake_edp_have_panel_power(intel_dp)) {
1121                 DRM_DEBUG_KMS("eDP power already on\n");
1122                 return;
1123         }
1124
1125         ironlake_wait_panel_power_cycle(intel_dp);
1126
1127         pp = ironlake_get_pp_control(dev_priv);
1128         if (IS_GEN5(dev)) {
1129                 /* ILK workaround: disable reset around power sequence */
1130                 pp &= ~PANEL_POWER_RESET;
1131                 I915_WRITE(PCH_PP_CONTROL, pp);
1132                 POSTING_READ(PCH_PP_CONTROL);
1133         }
1134
1135         pp |= POWER_TARGET_ON;
1136         if (!IS_GEN5(dev))
1137                 pp |= PANEL_POWER_RESET;
1138
1139         I915_WRITE(PCH_PP_CONTROL, pp);
1140         POSTING_READ(PCH_PP_CONTROL);
1141
1142         ironlake_wait_panel_on(intel_dp);
1143
1144         if (IS_GEN5(dev)) {
1145                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1146                 I915_WRITE(PCH_PP_CONTROL, pp);
1147                 POSTING_READ(PCH_PP_CONTROL);
1148         }
1149 }
1150
1151 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1152 {
1153         struct drm_device *dev = intel_dp->base.base.dev;
1154         struct drm_i915_private *dev_priv = dev->dev_private;
1155         u32 pp;
1156
1157         if (!is_edp(intel_dp))
1158                 return;
1159
1160         DRM_DEBUG_KMS("Turn eDP power off\n");
1161
1162         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1163
1164         pp = ironlake_get_pp_control(dev_priv);
1165         /* We need to switch off panel power _and_ force vdd, for otherwise some
1166          * panels get very unhappy and cease to work. */
1167         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1168         I915_WRITE(PCH_PP_CONTROL, pp);
1169         POSTING_READ(PCH_PP_CONTROL);
1170
1171         intel_dp->want_panel_vdd = false;
1172
1173         ironlake_wait_panel_off(intel_dp);
1174 }
1175
1176 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1177 {
1178         struct drm_device *dev = intel_dp->base.base.dev;
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         u32 pp;
1181
1182         if (!is_edp(intel_dp))
1183                 return;
1184
1185         DRM_DEBUG_KMS("\n");
1186         /*
1187          * If we enable the backlight right away following a panel power
1188          * on, we may see slight flicker as the panel syncs with the eDP
1189          * link.  So delay a bit to make sure the image is solid before
1190          * allowing it to appear.
1191          */
1192         msleep(intel_dp->backlight_on_delay);
1193         pp = ironlake_get_pp_control(dev_priv);
1194         pp |= EDP_BLC_ENABLE;
1195         I915_WRITE(PCH_PP_CONTROL, pp);
1196         POSTING_READ(PCH_PP_CONTROL);
1197 }
1198
1199 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1200 {
1201         struct drm_device *dev = intel_dp->base.base.dev;
1202         struct drm_i915_private *dev_priv = dev->dev_private;
1203         u32 pp;
1204
1205         if (!is_edp(intel_dp))
1206                 return;
1207
1208         DRM_DEBUG_KMS("\n");
1209         pp = ironlake_get_pp_control(dev_priv);
1210         pp &= ~EDP_BLC_ENABLE;
1211         I915_WRITE(PCH_PP_CONTROL, pp);
1212         POSTING_READ(PCH_PP_CONTROL);
1213         msleep(intel_dp->backlight_off_delay);
1214 }
1215
1216 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1217 {
1218         struct drm_device *dev = intel_dp->base.base.dev;
1219         struct drm_crtc *crtc = intel_dp->base.base.crtc;
1220         struct drm_i915_private *dev_priv = dev->dev_private;
1221         u32 dpa_ctl;
1222
1223         assert_pipe_disabled(dev_priv,
1224                              to_intel_crtc(crtc)->pipe);
1225
1226         DRM_DEBUG_KMS("\n");
1227         dpa_ctl = I915_READ(DP_A);
1228         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1229         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1230
1231         /* We don't adjust intel_dp->DP while tearing down the link, to
1232          * facilitate link retraining (e.g. after hotplug). Hence clear all
1233          * enable bits here to ensure that we don't enable too much. */
1234         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1235         intel_dp->DP |= DP_PLL_ENABLE;
1236         I915_WRITE(DP_A, intel_dp->DP);
1237         POSTING_READ(DP_A);
1238         udelay(200);
1239 }
1240
1241 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1242 {
1243         struct drm_device *dev = intel_dp->base.base.dev;
1244         struct drm_crtc *crtc = intel_dp->base.base.crtc;
1245         struct drm_i915_private *dev_priv = dev->dev_private;
1246         u32 dpa_ctl;
1247
1248         assert_pipe_disabled(dev_priv,
1249                              to_intel_crtc(crtc)->pipe);
1250
1251         dpa_ctl = I915_READ(DP_A);
1252         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1253              "dp pll off, should be on\n");
1254         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1255
1256         /* We can't rely on the value tracked for the DP register in
1257          * intel_dp->DP because link_down must not change that (otherwise link
1258          * re-training will fail. */
1259         dpa_ctl &= ~DP_PLL_ENABLE;
1260         I915_WRITE(DP_A, dpa_ctl);
1261         POSTING_READ(DP_A);
1262         udelay(200);
1263 }
1264
1265 /* If the sink supports it, try to set the power state appropriately */
1266 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1267 {
1268         int ret, i;
1269
1270         /* Should have a valid DPCD by this point */
1271         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1272                 return;
1273
1274         if (mode != DRM_MODE_DPMS_ON) {
1275                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1276                                                   DP_SET_POWER_D3);
1277                 if (ret != 1)
1278                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1279         } else {
1280                 /*
1281                  * When turning on, we need to retry for 1ms to give the sink
1282                  * time to wake up.
1283                  */
1284                 for (i = 0; i < 3; i++) {
1285                         ret = intel_dp_aux_native_write_1(intel_dp,
1286                                                           DP_SET_POWER,
1287                                                           DP_SET_POWER_D0);
1288                         if (ret == 1)
1289                                 break;
1290                         msleep(1);
1291                 }
1292         }
1293 }
1294
1295 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1296                                   enum pipe *pipe)
1297 {
1298         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1299         struct drm_device *dev = encoder->base.dev;
1300         struct drm_i915_private *dev_priv = dev->dev_private;
1301         u32 tmp = I915_READ(intel_dp->output_reg);
1302
1303         if (!(tmp & DP_PORT_EN))
1304                 return false;
1305
1306         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1307                 *pipe = PORT_TO_PIPE_CPT(tmp);
1308         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1309                 *pipe = PORT_TO_PIPE(tmp);
1310         } else {
1311                 u32 trans_sel;
1312                 u32 trans_dp;
1313                 int i;
1314
1315                 switch (intel_dp->output_reg) {
1316                 case PCH_DP_B:
1317                         trans_sel = TRANS_DP_PORT_SEL_B;
1318                         break;
1319                 case PCH_DP_C:
1320                         trans_sel = TRANS_DP_PORT_SEL_C;
1321                         break;
1322                 case PCH_DP_D:
1323                         trans_sel = TRANS_DP_PORT_SEL_D;
1324                         break;
1325                 default:
1326                         return true;
1327                 }
1328
1329                 for_each_pipe(i) {
1330                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1331                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1332                                 *pipe = i;
1333                                 return true;
1334                         }
1335                 }
1336         }
1337
1338         DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1339
1340         return true;
1341 }
1342
1343 static void intel_disable_dp(struct intel_encoder *encoder)
1344 {
1345         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1346
1347         /* Make sure the panel is off before trying to change the mode. But also
1348          * ensure that we have vdd while we switch off the panel. */
1349         ironlake_edp_panel_vdd_on(intel_dp);
1350         ironlake_edp_backlight_off(intel_dp);
1351         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1352         ironlake_edp_panel_off(intel_dp);
1353
1354         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1355         if (!is_cpu_edp(intel_dp))
1356                 intel_dp_link_down(intel_dp);
1357 }
1358
1359 static void intel_post_disable_dp(struct intel_encoder *encoder)
1360 {
1361         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1362
1363         if (is_cpu_edp(intel_dp)) {
1364                 intel_dp_link_down(intel_dp);
1365                 ironlake_edp_pll_off(intel_dp);
1366         }
1367 }
1368
1369 static void intel_enable_dp(struct intel_encoder *encoder)
1370 {
1371         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1372         struct drm_device *dev = encoder->base.dev;
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1375
1376         if (WARN_ON(dp_reg & DP_PORT_EN))
1377                 return;
1378
1379         ironlake_edp_panel_vdd_on(intel_dp);
1380         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1381         intel_dp_start_link_train(intel_dp);
1382         ironlake_edp_panel_on(intel_dp);
1383         ironlake_edp_panel_vdd_off(intel_dp, true);
1384         intel_dp_complete_link_train(intel_dp);
1385         ironlake_edp_backlight_on(intel_dp);
1386 }
1387
1388 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1389 {
1390         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1391
1392         if (is_cpu_edp(intel_dp))
1393                 ironlake_edp_pll_on(intel_dp);
1394 }
1395
1396 /*
1397  * Native read with retry for link status and receiver capability reads for
1398  * cases where the sink may still be asleep.
1399  */
1400 static bool
1401 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1402                                uint8_t *recv, int recv_bytes)
1403 {
1404         int ret, i;
1405
1406         /*
1407          * Sinks are *supposed* to come up within 1ms from an off state,
1408          * but we're also supposed to retry 3 times per the spec.
1409          */
1410         for (i = 0; i < 3; i++) {
1411                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1412                                                recv_bytes);
1413                 if (ret == recv_bytes)
1414                         return true;
1415                 msleep(1);
1416         }
1417
1418         return false;
1419 }
1420
1421 /*
1422  * Fetch AUX CH registers 0x202 - 0x207 which contain
1423  * link status information
1424  */
1425 static bool
1426 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1427 {
1428         return intel_dp_aux_native_read_retry(intel_dp,
1429                                               DP_LANE0_1_STATUS,
1430                                               link_status,
1431                                               DP_LINK_STATUS_SIZE);
1432 }
1433
1434 static uint8_t
1435 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1436                      int r)
1437 {
1438         return link_status[r - DP_LANE0_1_STATUS];
1439 }
1440
1441 static uint8_t
1442 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1443                                  int lane)
1444 {
1445         int         s = ((lane & 1) ?
1446                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1447                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1448         uint8_t l = adjust_request[lane>>1];
1449
1450         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1451 }
1452
1453 static uint8_t
1454 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1455                                       int lane)
1456 {
1457         int         s = ((lane & 1) ?
1458                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1459                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1460         uint8_t l = adjust_request[lane>>1];
1461
1462         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1463 }
1464
1465
1466 #if 0
1467 static char     *voltage_names[] = {
1468         "0.4V", "0.6V", "0.8V", "1.2V"
1469 };
1470 static char     *pre_emph_names[] = {
1471         "0dB", "3.5dB", "6dB", "9.5dB"
1472 };
1473 static char     *link_train_names[] = {
1474         "pattern 1", "pattern 2", "idle", "off"
1475 };
1476 #endif
1477
1478 /*
1479  * These are source-specific values; current Intel hardware supports
1480  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1481  */
1482
1483 static uint8_t
1484 intel_dp_voltage_max(struct intel_dp *intel_dp)
1485 {
1486         struct drm_device *dev = intel_dp->base.base.dev;
1487
1488         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1489                 return DP_TRAIN_VOLTAGE_SWING_800;
1490         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1491                 return DP_TRAIN_VOLTAGE_SWING_1200;
1492         else
1493                 return DP_TRAIN_VOLTAGE_SWING_800;
1494 }
1495
1496 static uint8_t
1497 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1498 {
1499         struct drm_device *dev = intel_dp->base.base.dev;
1500
1501         if (IS_HASWELL(dev)) {
1502                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1503                 case DP_TRAIN_VOLTAGE_SWING_400:
1504                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1505                 case DP_TRAIN_VOLTAGE_SWING_600:
1506                         return DP_TRAIN_PRE_EMPHASIS_6;
1507                 case DP_TRAIN_VOLTAGE_SWING_800:
1508                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1509                 case DP_TRAIN_VOLTAGE_SWING_1200:
1510                 default:
1511                         return DP_TRAIN_PRE_EMPHASIS_0;
1512                 }
1513         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1514                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1515                 case DP_TRAIN_VOLTAGE_SWING_400:
1516                         return DP_TRAIN_PRE_EMPHASIS_6;
1517                 case DP_TRAIN_VOLTAGE_SWING_600:
1518                 case DP_TRAIN_VOLTAGE_SWING_800:
1519                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1520                 default:
1521                         return DP_TRAIN_PRE_EMPHASIS_0;
1522                 }
1523         } else {
1524                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1525                 case DP_TRAIN_VOLTAGE_SWING_400:
1526                         return DP_TRAIN_PRE_EMPHASIS_6;
1527                 case DP_TRAIN_VOLTAGE_SWING_600:
1528                         return DP_TRAIN_PRE_EMPHASIS_6;
1529                 case DP_TRAIN_VOLTAGE_SWING_800:
1530                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1531                 case DP_TRAIN_VOLTAGE_SWING_1200:
1532                 default:
1533                         return DP_TRAIN_PRE_EMPHASIS_0;
1534                 }
1535         }
1536 }
1537
1538 static void
1539 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1540 {
1541         uint8_t v = 0;
1542         uint8_t p = 0;
1543         int lane;
1544         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1545         uint8_t voltage_max;
1546         uint8_t preemph_max;
1547
1548         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1549                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1550                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1551
1552                 if (this_v > v)
1553                         v = this_v;
1554                 if (this_p > p)
1555                         p = this_p;
1556         }
1557
1558         voltage_max = intel_dp_voltage_max(intel_dp);
1559         if (v >= voltage_max)
1560                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1561
1562         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1563         if (p >= preemph_max)
1564                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1565
1566         for (lane = 0; lane < 4; lane++)
1567                 intel_dp->train_set[lane] = v | p;
1568 }
1569
1570 static uint32_t
1571 intel_dp_signal_levels(uint8_t train_set)
1572 {
1573         uint32_t        signal_levels = 0;
1574
1575         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576         case DP_TRAIN_VOLTAGE_SWING_400:
1577         default:
1578                 signal_levels |= DP_VOLTAGE_0_4;
1579                 break;
1580         case DP_TRAIN_VOLTAGE_SWING_600:
1581                 signal_levels |= DP_VOLTAGE_0_6;
1582                 break;
1583         case DP_TRAIN_VOLTAGE_SWING_800:
1584                 signal_levels |= DP_VOLTAGE_0_8;
1585                 break;
1586         case DP_TRAIN_VOLTAGE_SWING_1200:
1587                 signal_levels |= DP_VOLTAGE_1_2;
1588                 break;
1589         }
1590         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1591         case DP_TRAIN_PRE_EMPHASIS_0:
1592         default:
1593                 signal_levels |= DP_PRE_EMPHASIS_0;
1594                 break;
1595         case DP_TRAIN_PRE_EMPHASIS_3_5:
1596                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1597                 break;
1598         case DP_TRAIN_PRE_EMPHASIS_6:
1599                 signal_levels |= DP_PRE_EMPHASIS_6;
1600                 break;
1601         case DP_TRAIN_PRE_EMPHASIS_9_5:
1602                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1603                 break;
1604         }
1605         return signal_levels;
1606 }
1607
1608 /* Gen6's DP voltage swing and pre-emphasis control */
1609 static uint32_t
1610 intel_gen6_edp_signal_levels(uint8_t train_set)
1611 {
1612         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1613                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1614         switch (signal_levels) {
1615         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1616         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1617                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1618         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1619                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1620         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1621         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1622                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1623         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1624         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1625                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1626         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1627         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1628                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1629         default:
1630                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1631                               "0x%x\n", signal_levels);
1632                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1633         }
1634 }
1635
1636 /* Gen7's DP voltage swing and pre-emphasis control */
1637 static uint32_t
1638 intel_gen7_edp_signal_levels(uint8_t train_set)
1639 {
1640         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1641                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1642         switch (signal_levels) {
1643         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1644                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1645         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1646                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1647         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1648                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1649
1650         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1651                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1652         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1653                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1654
1655         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1656                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1657         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1658                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1659
1660         default:
1661                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1662                               "0x%x\n", signal_levels);
1663                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1664         }
1665 }
1666
1667 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1668 static uint32_t
1669 intel_dp_signal_levels_hsw(uint8_t train_set)
1670 {
1671         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1672                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1673         switch (signal_levels) {
1674         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1675                 return DDI_BUF_EMP_400MV_0DB_HSW;
1676         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1678         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1679                 return DDI_BUF_EMP_400MV_6DB_HSW;
1680         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1681                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1682
1683         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1684                 return DDI_BUF_EMP_600MV_0DB_HSW;
1685         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1686                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1687         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1688                 return DDI_BUF_EMP_600MV_6DB_HSW;
1689
1690         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1691                 return DDI_BUF_EMP_800MV_0DB_HSW;
1692         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1693                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1694         default:
1695                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1696                               "0x%x\n", signal_levels);
1697                 return DDI_BUF_EMP_400MV_0DB_HSW;
1698         }
1699 }
1700
1701 static uint8_t
1702 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1703                       int lane)
1704 {
1705         int s = (lane & 1) * 4;
1706         uint8_t l = link_status[lane>>1];
1707
1708         return (l >> s) & 0xf;
1709 }
1710
1711 /* Check for clock recovery is done on all channels */
1712 static bool
1713 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1714 {
1715         int lane;
1716         uint8_t lane_status;
1717
1718         for (lane = 0; lane < lane_count; lane++) {
1719                 lane_status = intel_get_lane_status(link_status, lane);
1720                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1721                         return false;
1722         }
1723         return true;
1724 }
1725
1726 /* Check to see if channel eq is done on all channels */
1727 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1728                          DP_LANE_CHANNEL_EQ_DONE|\
1729                          DP_LANE_SYMBOL_LOCKED)
1730 static bool
1731 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1732 {
1733         uint8_t lane_align;
1734         uint8_t lane_status;
1735         int lane;
1736
1737         lane_align = intel_dp_link_status(link_status,
1738                                           DP_LANE_ALIGN_STATUS_UPDATED);
1739         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1740                 return false;
1741         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1742                 lane_status = intel_get_lane_status(link_status, lane);
1743                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1744                         return false;
1745         }
1746         return true;
1747 }
1748
1749 static bool
1750 intel_dp_set_link_train(struct intel_dp *intel_dp,
1751                         uint32_t dp_reg_value,
1752                         uint8_t dp_train_pat)
1753 {
1754         struct drm_device *dev = intel_dp->base.base.dev;
1755         struct drm_i915_private *dev_priv = dev->dev_private;
1756         int ret;
1757         uint32_t temp;
1758
1759         if (IS_HASWELL(dev)) {
1760                 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1761
1762                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1763                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1764                 else
1765                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1766
1767                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1768                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1769                 case DP_TRAINING_PATTERN_DISABLE:
1770                         temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1771                         I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1772
1773                         if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1774                                       DP_TP_STATUS_IDLE_DONE), 1))
1775                                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1776
1777                         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1778                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1779
1780                         break;
1781                 case DP_TRAINING_PATTERN_1:
1782                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1783                         break;
1784                 case DP_TRAINING_PATTERN_2:
1785                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1786                         break;
1787                 case DP_TRAINING_PATTERN_3:
1788                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1789                         break;
1790                 }
1791                 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1792
1793         } else if (HAS_PCH_CPT(dev) &&
1794                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1795                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1796
1797                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1798                 case DP_TRAINING_PATTERN_DISABLE:
1799                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1800                         break;
1801                 case DP_TRAINING_PATTERN_1:
1802                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1803                         break;
1804                 case DP_TRAINING_PATTERN_2:
1805                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1806                         break;
1807                 case DP_TRAINING_PATTERN_3:
1808                         DRM_ERROR("DP training pattern 3 not supported\n");
1809                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1810                         break;
1811                 }
1812
1813         } else {
1814                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1815
1816                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1817                 case DP_TRAINING_PATTERN_DISABLE:
1818                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1819                         break;
1820                 case DP_TRAINING_PATTERN_1:
1821                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1822                         break;
1823                 case DP_TRAINING_PATTERN_2:
1824                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1825                         break;
1826                 case DP_TRAINING_PATTERN_3:
1827                         DRM_ERROR("DP training pattern 3 not supported\n");
1828                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1829                         break;
1830                 }
1831         }
1832
1833         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1834         POSTING_READ(intel_dp->output_reg);
1835
1836         intel_dp_aux_native_write_1(intel_dp,
1837                                     DP_TRAINING_PATTERN_SET,
1838                                     dp_train_pat);
1839
1840         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1841             DP_TRAINING_PATTERN_DISABLE) {
1842                 ret = intel_dp_aux_native_write(intel_dp,
1843                                                 DP_TRAINING_LANE0_SET,
1844                                                 intel_dp->train_set,
1845                                                 intel_dp->lane_count);
1846                 if (ret != intel_dp->lane_count)
1847                         return false;
1848         }
1849
1850         return true;
1851 }
1852
1853 /* Enable corresponding port and start training pattern 1 */
1854 void
1855 intel_dp_start_link_train(struct intel_dp *intel_dp)
1856 {
1857         struct drm_encoder *encoder = &intel_dp->base.base;
1858         struct drm_device *dev = encoder->dev;
1859         int i;
1860         uint8_t voltage;
1861         bool clock_recovery = false;
1862         int voltage_tries, loop_tries;
1863         uint32_t DP = intel_dp->DP;
1864
1865         if (IS_HASWELL(dev))
1866                 intel_ddi_prepare_link_retrain(encoder);
1867
1868         /* Write the link configuration data */
1869         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1870                                   intel_dp->link_configuration,
1871                                   DP_LINK_CONFIGURATION_SIZE);
1872
1873         DP |= DP_PORT_EN;
1874
1875         memset(intel_dp->train_set, 0, 4);
1876         voltage = 0xff;
1877         voltage_tries = 0;
1878         loop_tries = 0;
1879         clock_recovery = false;
1880         for (;;) {
1881                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1882                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1883                 uint32_t    signal_levels;
1884
1885                 if (IS_HASWELL(dev)) {
1886                         signal_levels = intel_dp_signal_levels_hsw(
1887                                                         intel_dp->train_set[0]);
1888                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1889                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1890                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1891                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1892                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1893                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1894                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1895                 } else {
1896                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1897                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1898                 }
1899                 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1900                               signal_levels);
1901
1902                 if (!intel_dp_set_link_train(intel_dp, DP,
1903                                              DP_TRAINING_PATTERN_1 |
1904                                              DP_LINK_SCRAMBLING_DISABLE))
1905                         break;
1906                 /* Set training pattern 1 */
1907
1908                 udelay(100);
1909                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1910                         DRM_ERROR("failed to get link status\n");
1911                         break;
1912                 }
1913
1914                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1915                         DRM_DEBUG_KMS("clock recovery OK\n");
1916                         clock_recovery = true;
1917                         break;
1918                 }
1919
1920                 /* Check to see if we've tried the max voltage */
1921                 for (i = 0; i < intel_dp->lane_count; i++)
1922                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1923                                 break;
1924                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1925                         if (++loop_tries == 5) {
1926                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1927                                 break;
1928                         }
1929                         memset(intel_dp->train_set, 0, 4);
1930                         voltage_tries = 0;
1931                         continue;
1932                 }
1933
1934                 /* Check to see if we've tried the same voltage 5 times */
1935                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1936                         voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1937                         voltage_tries = 0;
1938                 } else
1939                         ++voltage_tries;
1940
1941                 /* Compute new intel_dp->train_set as requested by target */
1942                 intel_get_adjust_train(intel_dp, link_status);
1943         }
1944
1945         intel_dp->DP = DP;
1946 }
1947
1948 void
1949 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1950 {
1951         struct drm_device *dev = intel_dp->base.base.dev;
1952         bool channel_eq = false;
1953         int tries, cr_tries;
1954         uint32_t DP = intel_dp->DP;
1955
1956         /* channel equalization */
1957         tries = 0;
1958         cr_tries = 0;
1959         channel_eq = false;
1960         for (;;) {
1961                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1962                 uint32_t    signal_levels;
1963                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1964
1965                 if (cr_tries > 5) {
1966                         DRM_ERROR("failed to train DP, aborting\n");
1967                         intel_dp_link_down(intel_dp);
1968                         break;
1969                 }
1970
1971                 if (IS_HASWELL(dev)) {
1972                         signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1973                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1974                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1975                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1976                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1977                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1978                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1979                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1980                 } else {
1981                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1982                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1983                 }
1984
1985                 /* channel eq pattern */
1986                 if (!intel_dp_set_link_train(intel_dp, DP,
1987                                              DP_TRAINING_PATTERN_2 |
1988                                              DP_LINK_SCRAMBLING_DISABLE))
1989                         break;
1990
1991                 udelay(400);
1992                 if (!intel_dp_get_link_status(intel_dp, link_status))
1993                         break;
1994
1995                 /* Make sure clock is still ok */
1996                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1997                         intel_dp_start_link_train(intel_dp);
1998                         cr_tries++;
1999                         continue;
2000                 }
2001
2002                 if (intel_channel_eq_ok(intel_dp, link_status)) {
2003                         channel_eq = true;
2004                         break;
2005                 }
2006
2007                 /* Try 5 times, then try clock recovery if that fails */
2008                 if (tries > 5) {
2009                         intel_dp_link_down(intel_dp);
2010                         intel_dp_start_link_train(intel_dp);
2011                         tries = 0;
2012                         cr_tries++;
2013                         continue;
2014                 }
2015
2016                 /* Compute new intel_dp->train_set as requested by target */
2017                 intel_get_adjust_train(intel_dp, link_status);
2018                 ++tries;
2019         }
2020
2021         if (channel_eq)
2022                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2023
2024         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2025 }
2026
2027 static void
2028 intel_dp_link_down(struct intel_dp *intel_dp)
2029 {
2030         struct drm_device *dev = intel_dp->base.base.dev;
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032         uint32_t DP = intel_dp->DP;
2033
2034         /*
2035          * DDI code has a strict mode set sequence and we should try to respect
2036          * it, otherwise we might hang the machine in many different ways. So we
2037          * really should be disabling the port only on a complete crtc_disable
2038          * sequence. This function is just called under two conditions on DDI
2039          * code:
2040          * - Link train failed while doing crtc_enable, and on this case we
2041          *   really should respect the mode set sequence and wait for a
2042          *   crtc_disable.
2043          * - Someone turned the monitor off and intel_dp_check_link_status
2044          *   called us. We don't need to disable the whole port on this case, so
2045          *   when someone turns the monitor on again,
2046          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2047          *   train.
2048          */
2049         if (IS_HASWELL(dev))
2050                 return;
2051
2052         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2053                 return;
2054
2055         DRM_DEBUG_KMS("\n");
2056
2057         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2058                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2059                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2060         } else {
2061                 DP &= ~DP_LINK_TRAIN_MASK;
2062                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2063         }
2064         POSTING_READ(intel_dp->output_reg);
2065
2066         msleep(17);
2067
2068         if (HAS_PCH_IBX(dev) &&
2069             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2070                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2071
2072                 /* Hardware workaround: leaving our transcoder select
2073                  * set to transcoder B while it's off will prevent the
2074                  * corresponding HDMI output on transcoder A.
2075                  *
2076                  * Combine this with another hardware workaround:
2077                  * transcoder select bit can only be cleared while the
2078                  * port is enabled.
2079                  */
2080                 DP &= ~DP_PIPEB_SELECT;
2081                 I915_WRITE(intel_dp->output_reg, DP);
2082
2083                 /* Changes to enable or select take place the vblank
2084                  * after being written.
2085                  */
2086                 if (crtc == NULL) {
2087                         /* We can arrive here never having been attached
2088                          * to a CRTC, for instance, due to inheriting
2089                          * random state from the BIOS.
2090                          *
2091                          * If the pipe is not running, play safe and
2092                          * wait for the clocks to stabilise before
2093                          * continuing.
2094                          */
2095                         POSTING_READ(intel_dp->output_reg);
2096                         msleep(50);
2097                 } else
2098                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2099         }
2100
2101         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2102         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2103         POSTING_READ(intel_dp->output_reg);
2104         msleep(intel_dp->panel_power_down_delay);
2105 }
2106
2107 static bool
2108 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2109 {
2110         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2111                                            sizeof(intel_dp->dpcd)) == 0)
2112                 return false; /* aux transfer failed */
2113
2114         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2115                 return false; /* DPCD not present */
2116
2117         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2118               DP_DWN_STRM_PORT_PRESENT))
2119                 return true; /* native DP sink */
2120
2121         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2122                 return true; /* no per-port downstream info */
2123
2124         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2125                                            intel_dp->downstream_ports,
2126                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2127                 return false; /* downstream port status fetch failed */
2128
2129         return true;
2130 }
2131
2132 static void
2133 intel_dp_probe_oui(struct intel_dp *intel_dp)
2134 {
2135         u8 buf[3];
2136
2137         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2138                 return;
2139
2140         ironlake_edp_panel_vdd_on(intel_dp);
2141
2142         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2143                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2144                               buf[0], buf[1], buf[2]);
2145
2146         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2147                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2148                               buf[0], buf[1], buf[2]);
2149
2150         ironlake_edp_panel_vdd_off(intel_dp, false);
2151 }
2152
2153 static bool
2154 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2155 {
2156         int ret;
2157
2158         ret = intel_dp_aux_native_read_retry(intel_dp,
2159                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2160                                              sink_irq_vector, 1);
2161         if (!ret)
2162                 return false;
2163
2164         return true;
2165 }
2166
2167 static void
2168 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2169 {
2170         /* NAK by default */
2171         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2172 }
2173
2174 /*
2175  * According to DP spec
2176  * 5.1.2:
2177  *  1. Read DPCD
2178  *  2. Configure link according to Receiver Capabilities
2179  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2180  *  4. Check link status on receipt of hot-plug interrupt
2181  */
2182
2183 static void
2184 intel_dp_check_link_status(struct intel_dp *intel_dp)
2185 {
2186         u8 sink_irq_vector;
2187         u8 link_status[DP_LINK_STATUS_SIZE];
2188
2189         if (!intel_dp->base.connectors_active)
2190                 return;
2191
2192         if (WARN_ON(!intel_dp->base.base.crtc))
2193                 return;
2194
2195         /* Try to read receiver status if the link appears to be up */
2196         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2197                 intel_dp_link_down(intel_dp);
2198                 return;
2199         }
2200
2201         /* Now read the DPCD to see if it's actually running */
2202         if (!intel_dp_get_dpcd(intel_dp)) {
2203                 intel_dp_link_down(intel_dp);
2204                 return;
2205         }
2206
2207         /* Try to read the source of the interrupt */
2208         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2209             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2210                 /* Clear interrupt source */
2211                 intel_dp_aux_native_write_1(intel_dp,
2212                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2213                                             sink_irq_vector);
2214
2215                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2216                         intel_dp_handle_test_request(intel_dp);
2217                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2218                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2219         }
2220
2221         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2222                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2223                               drm_get_encoder_name(&intel_dp->base.base));
2224                 intel_dp_start_link_train(intel_dp);
2225                 intel_dp_complete_link_train(intel_dp);
2226         }
2227 }
2228
2229 /* XXX this is probably wrong for multiple downstream ports */
2230 static enum drm_connector_status
2231 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2232 {
2233         uint8_t *dpcd = intel_dp->dpcd;
2234         bool hpd;
2235         uint8_t type;
2236
2237         if (!intel_dp_get_dpcd(intel_dp))
2238                 return connector_status_disconnected;
2239
2240         /* if there's no downstream port, we're done */
2241         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2242                 return connector_status_connected;
2243
2244         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2245         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2246         if (hpd) {
2247                 uint8_t reg;
2248                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2249                                                     &reg, 1))
2250                         return connector_status_unknown;
2251                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2252                                               : connector_status_disconnected;
2253         }
2254
2255         /* If no HPD, poke DDC gently */
2256         if (drm_probe_ddc(&intel_dp->adapter))
2257                 return connector_status_connected;
2258
2259         /* Well we tried, say unknown for unreliable port types */
2260         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2261         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2262                 return connector_status_unknown;
2263
2264         /* Anything else is out of spec, warn and ignore */
2265         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2266         return connector_status_disconnected;
2267 }
2268
2269 static enum drm_connector_status
2270 ironlake_dp_detect(struct intel_dp *intel_dp)
2271 {
2272         enum drm_connector_status status;
2273
2274         /* Can't disconnect eDP, but you can close the lid... */
2275         if (is_edp(intel_dp)) {
2276                 status = intel_panel_detect(intel_dp->base.base.dev);
2277                 if (status == connector_status_unknown)
2278                         status = connector_status_connected;
2279                 return status;
2280         }
2281
2282         return intel_dp_detect_dpcd(intel_dp);
2283 }
2284
2285 static enum drm_connector_status
2286 g4x_dp_detect(struct intel_dp *intel_dp)
2287 {
2288         struct drm_device *dev = intel_dp->base.base.dev;
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         uint32_t bit;
2291
2292         switch (intel_dp->output_reg) {
2293         case DP_B:
2294                 bit = DPB_HOTPLUG_LIVE_STATUS;
2295                 break;
2296         case DP_C:
2297                 bit = DPC_HOTPLUG_LIVE_STATUS;
2298                 break;
2299         case DP_D:
2300                 bit = DPD_HOTPLUG_LIVE_STATUS;
2301                 break;
2302         default:
2303                 return connector_status_unknown;
2304         }
2305
2306         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2307                 return connector_status_disconnected;
2308
2309         return intel_dp_detect_dpcd(intel_dp);
2310 }
2311
2312 static struct edid *
2313 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2314 {
2315         struct intel_dp *intel_dp = intel_attached_dp(connector);
2316         struct edid     *edid;
2317         int size;
2318
2319         if (is_edp(intel_dp)) {
2320                 if (!intel_dp->edid)
2321                         return NULL;
2322
2323                 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2324                 edid = kmalloc(size, GFP_KERNEL);
2325                 if (!edid)
2326                         return NULL;
2327
2328                 memcpy(edid, intel_dp->edid, size);
2329                 return edid;
2330         }
2331
2332         edid = drm_get_edid(connector, adapter);
2333         return edid;
2334 }
2335
2336 static int
2337 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2338 {
2339         struct intel_dp *intel_dp = intel_attached_dp(connector);
2340         int     ret;
2341
2342         if (is_edp(intel_dp)) {
2343                 drm_mode_connector_update_edid_property(connector,
2344                                                         intel_dp->edid);
2345                 ret = drm_add_edid_modes(connector, intel_dp->edid);
2346                 drm_edid_to_eld(connector,
2347                                 intel_dp->edid);
2348                 return intel_dp->edid_mode_count;
2349         }
2350
2351         ret = intel_ddc_get_modes(connector, adapter);
2352         return ret;
2353 }
2354
2355
2356 /**
2357  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2358  *
2359  * \return true if DP port is connected.
2360  * \return false if DP port is disconnected.
2361  */
2362 static enum drm_connector_status
2363 intel_dp_detect(struct drm_connector *connector, bool force)
2364 {
2365         struct intel_dp *intel_dp = intel_attached_dp(connector);
2366         struct drm_device *dev = intel_dp->base.base.dev;
2367         enum drm_connector_status status;
2368         struct edid *edid = NULL;
2369
2370         intel_dp->has_audio = false;
2371
2372         if (HAS_PCH_SPLIT(dev))
2373                 status = ironlake_dp_detect(intel_dp);
2374         else
2375                 status = g4x_dp_detect(intel_dp);
2376
2377         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2378                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2379                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2380                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2381
2382         if (status != connector_status_connected)
2383                 return status;
2384
2385         intel_dp_probe_oui(intel_dp);
2386
2387         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2388                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2389         } else {
2390                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2391                 if (edid) {
2392                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2393                         kfree(edid);
2394                 }
2395         }
2396
2397         return connector_status_connected;
2398 }
2399
2400 static int intel_dp_get_modes(struct drm_connector *connector)
2401 {
2402         struct intel_dp *intel_dp = intel_attached_dp(connector);
2403         struct drm_device *dev = intel_dp->base.base.dev;
2404         int ret;
2405
2406         /* We should parse the EDID data and find out if it has an audio sink
2407          */
2408
2409         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2410         if (ret)
2411                 return ret;
2412
2413         /* if eDP has no EDID, fall back to fixed mode */
2414         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
2415                 struct drm_display_mode *mode;
2416                 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2417                 if (mode) {
2418                         drm_mode_probed_add(connector, mode);
2419                         return 1;
2420                 }
2421         }
2422         return 0;
2423 }
2424
2425 static bool
2426 intel_dp_detect_audio(struct drm_connector *connector)
2427 {
2428         struct intel_dp *intel_dp = intel_attached_dp(connector);
2429         struct edid *edid;
2430         bool has_audio = false;
2431
2432         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2433         if (edid) {
2434                 has_audio = drm_detect_monitor_audio(edid);
2435                 kfree(edid);
2436         }
2437
2438         return has_audio;
2439 }
2440
2441 static int
2442 intel_dp_set_property(struct drm_connector *connector,
2443                       struct drm_property *property,
2444                       uint64_t val)
2445 {
2446         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2447         struct intel_dp *intel_dp = intel_attached_dp(connector);
2448         int ret;
2449
2450         ret = drm_connector_property_set_value(connector, property, val);
2451         if (ret)
2452                 return ret;
2453
2454         if (property == dev_priv->force_audio_property) {
2455                 int i = val;
2456                 bool has_audio;
2457
2458                 if (i == intel_dp->force_audio)
2459                         return 0;
2460
2461                 intel_dp->force_audio = i;
2462
2463                 if (i == HDMI_AUDIO_AUTO)
2464                         has_audio = intel_dp_detect_audio(connector);
2465                 else
2466                         has_audio = (i == HDMI_AUDIO_ON);
2467
2468                 if (has_audio == intel_dp->has_audio)
2469                         return 0;
2470
2471                 intel_dp->has_audio = has_audio;
2472                 goto done;
2473         }
2474
2475         if (property == dev_priv->broadcast_rgb_property) {
2476                 if (val == !!intel_dp->color_range)
2477                         return 0;
2478
2479                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2480                 goto done;
2481         }
2482
2483         return -EINVAL;
2484
2485 done:
2486         if (intel_dp->base.base.crtc) {
2487                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2488                 intel_set_mode(crtc, &crtc->mode,
2489                                crtc->x, crtc->y, crtc->fb);
2490         }
2491
2492         return 0;
2493 }
2494
2495 static void
2496 intel_dp_destroy(struct drm_connector *connector)
2497 {
2498         struct drm_device *dev = connector->dev;
2499         struct intel_dp *intel_dp = intel_attached_dp(connector);
2500         struct intel_connector *intel_connector = to_intel_connector(connector);
2501
2502         if (is_edp(intel_dp)) {
2503                 intel_panel_destroy_backlight(dev);
2504                 intel_panel_fini(&intel_connector->panel);
2505         }
2506
2507         drm_sysfs_connector_remove(connector);
2508         drm_connector_cleanup(connector);
2509         kfree(connector);
2510 }
2511
2512 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2513 {
2514         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2515
2516         i2c_del_adapter(&intel_dp->adapter);
2517         drm_encoder_cleanup(encoder);
2518         if (is_edp(intel_dp)) {
2519                 kfree(intel_dp->edid);
2520                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2521                 ironlake_panel_vdd_off_sync(intel_dp);
2522         }
2523         kfree(intel_dp);
2524 }
2525
2526 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2527         .mode_fixup = intel_dp_mode_fixup,
2528         .mode_set = intel_dp_mode_set,
2529         .disable = intel_encoder_noop,
2530 };
2531
2532 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2533         .mode_fixup = intel_dp_mode_fixup,
2534         .mode_set = intel_ddi_mode_set,
2535         .disable = intel_encoder_noop,
2536 };
2537
2538 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2539         .dpms = intel_connector_dpms,
2540         .detect = intel_dp_detect,
2541         .fill_modes = drm_helper_probe_single_connector_modes,
2542         .set_property = intel_dp_set_property,
2543         .destroy = intel_dp_destroy,
2544 };
2545
2546 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2547         .get_modes = intel_dp_get_modes,
2548         .mode_valid = intel_dp_mode_valid,
2549         .best_encoder = intel_best_encoder,
2550 };
2551
2552 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2553         .destroy = intel_dp_encoder_destroy,
2554 };
2555
2556 static void
2557 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2558 {
2559         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2560
2561         intel_dp_check_link_status(intel_dp);
2562 }
2563
2564 /* Return which DP Port should be selected for Transcoder DP control */
2565 int
2566 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2567 {
2568         struct drm_device *dev = crtc->dev;
2569         struct intel_encoder *encoder;
2570
2571         for_each_encoder_on_crtc(dev, crtc, encoder) {
2572                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2573
2574                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2575                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2576                         return intel_dp->output_reg;
2577         }
2578
2579         return -1;
2580 }
2581
2582 /* check the VBT to see whether the eDP is on DP-D port */
2583 bool intel_dpd_is_edp(struct drm_device *dev)
2584 {
2585         struct drm_i915_private *dev_priv = dev->dev_private;
2586         struct child_device_config *p_child;
2587         int i;
2588
2589         if (!dev_priv->child_dev_num)
2590                 return false;
2591
2592         for (i = 0; i < dev_priv->child_dev_num; i++) {
2593                 p_child = dev_priv->child_dev + i;
2594
2595                 if (p_child->dvo_port == PORT_IDPD &&
2596                     p_child->device_type == DEVICE_TYPE_eDP)
2597                         return true;
2598         }
2599         return false;
2600 }
2601
2602 static void
2603 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2604 {
2605         intel_attach_force_audio_property(connector);
2606         intel_attach_broadcast_rgb_property(connector);
2607 }
2608
2609 void
2610 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2611 {
2612         struct drm_i915_private *dev_priv = dev->dev_private;
2613         struct drm_connector *connector;
2614         struct intel_dp *intel_dp;
2615         struct intel_encoder *intel_encoder;
2616         struct intel_connector *intel_connector;
2617         struct drm_display_mode *fixed_mode = NULL;
2618         const char *name = NULL;
2619         int type;
2620
2621         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2622         if (!intel_dp)
2623                 return;
2624
2625         intel_dp->output_reg = output_reg;
2626         intel_dp->port = port;
2627         /* Preserve the current hw state. */
2628         intel_dp->DP = I915_READ(intel_dp->output_reg);
2629
2630         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2631         if (!intel_connector) {
2632                 kfree(intel_dp);
2633                 return;
2634         }
2635         intel_encoder = &intel_dp->base;
2636
2637         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2638                 if (intel_dpd_is_edp(dev))
2639                         intel_dp->is_pch_edp = true;
2640
2641         /*
2642          * FIXME : We need to initialize built-in panels before external panels.
2643          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2644          */
2645         if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2646                 type = DRM_MODE_CONNECTOR_eDP;
2647                 intel_encoder->type = INTEL_OUTPUT_EDP;
2648         } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2649                 type = DRM_MODE_CONNECTOR_eDP;
2650                 intel_encoder->type = INTEL_OUTPUT_EDP;
2651         } else {
2652                 type = DRM_MODE_CONNECTOR_DisplayPort;
2653                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2654         }
2655
2656         connector = &intel_connector->base;
2657         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2658         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2659
2660         connector->polled = DRM_CONNECTOR_POLL_HPD;
2661
2662         intel_encoder->cloneable = false;
2663
2664         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2665                           ironlake_panel_vdd_work);
2666
2667         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2668
2669         connector->interlace_allowed = true;
2670         connector->doublescan_allowed = 0;
2671
2672         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2673                          DRM_MODE_ENCODER_TMDS);
2674
2675         if (IS_HASWELL(dev))
2676                 drm_encoder_helper_add(&intel_encoder->base,
2677                                        &intel_dp_helper_funcs_hsw);
2678         else
2679                 drm_encoder_helper_add(&intel_encoder->base,
2680                                        &intel_dp_helper_funcs);
2681
2682         intel_connector_attach_encoder(intel_connector, intel_encoder);
2683         drm_sysfs_connector_add(connector);
2684
2685         if (IS_HASWELL(dev)) {
2686                 intel_encoder->enable = intel_enable_ddi;
2687                 intel_encoder->pre_enable = intel_ddi_pre_enable;
2688                 intel_encoder->disable = intel_disable_ddi;
2689                 intel_encoder->post_disable = intel_ddi_post_disable;
2690                 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2691         } else {
2692                 intel_encoder->enable = intel_enable_dp;
2693                 intel_encoder->pre_enable = intel_pre_enable_dp;
2694                 intel_encoder->disable = intel_disable_dp;
2695                 intel_encoder->post_disable = intel_post_disable_dp;
2696                 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2697         }
2698         intel_connector->get_hw_state = intel_connector_get_hw_state;
2699
2700         /* Set up the DDC bus. */
2701         switch (port) {
2702         case PORT_A:
2703                 name = "DPDDC-A";
2704                 break;
2705         case PORT_B:
2706                 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2707                 name = "DPDDC-B";
2708                 break;
2709         case PORT_C:
2710                 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2711                 name = "DPDDC-C";
2712                 break;
2713         case PORT_D:
2714                 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2715                 name = "DPDDC-D";
2716                 break;
2717         default:
2718                 WARN(1, "Invalid port %c\n", port_name(port));
2719                 break;
2720         }
2721
2722         /* Cache some DPCD data in the eDP case */
2723         if (is_edp(intel_dp)) {
2724                 struct edp_power_seq    cur, vbt;
2725                 u32 pp_on, pp_off, pp_div;
2726
2727                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2728                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2729                 pp_div = I915_READ(PCH_PP_DIVISOR);
2730
2731                 if (!pp_on || !pp_off || !pp_div) {
2732                         DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2733                         intel_dp_encoder_destroy(&intel_dp->base.base);
2734                         intel_dp_destroy(&intel_connector->base);
2735                         return;
2736                 }
2737
2738                 /* Pull timing values out of registers */
2739                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2740                         PANEL_POWER_UP_DELAY_SHIFT;
2741
2742                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2743                         PANEL_LIGHT_ON_DELAY_SHIFT;
2744
2745                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2746                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2747
2748                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2749                         PANEL_POWER_DOWN_DELAY_SHIFT;
2750
2751                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2752                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2753
2754                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2755                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2756
2757                 vbt = dev_priv->edp.pps;
2758
2759                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2760                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2761
2762 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2763
2764                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2765                 intel_dp->backlight_on_delay = get_delay(t8);
2766                 intel_dp->backlight_off_delay = get_delay(t9);
2767                 intel_dp->panel_power_down_delay = get_delay(t10);
2768                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2769
2770                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2771                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2772                               intel_dp->panel_power_cycle_delay);
2773
2774                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2775                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2776         }
2777
2778         intel_dp_i2c_init(intel_dp, intel_connector, name);
2779
2780         if (is_edp(intel_dp)) {
2781                 bool ret;
2782                 struct drm_display_mode *scan;
2783                 struct edid *edid;
2784
2785                 ironlake_edp_panel_vdd_on(intel_dp);
2786                 ret = intel_dp_get_dpcd(intel_dp);
2787                 ironlake_edp_panel_vdd_off(intel_dp, false);
2788
2789                 if (ret) {
2790                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2791                                 dev_priv->no_aux_handshake =
2792                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2793                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2794                 } else {
2795                         /* if this fails, presume the device is a ghost */
2796                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2797                         intel_dp_encoder_destroy(&intel_dp->base.base);
2798                         intel_dp_destroy(&intel_connector->base);
2799                         return;
2800                 }
2801
2802                 ironlake_edp_panel_vdd_on(intel_dp);
2803                 edid = drm_get_edid(connector, &intel_dp->adapter);
2804                 if (edid) {
2805                         drm_mode_connector_update_edid_property(connector,
2806                                                                 edid);
2807                         intel_dp->edid_mode_count =
2808                                 drm_add_edid_modes(connector, edid);
2809                         drm_edid_to_eld(connector, edid);
2810                         intel_dp->edid = edid;
2811                 }
2812
2813                 /* prefer fixed mode from EDID if available */
2814                 list_for_each_entry(scan, &connector->probed_modes, head) {
2815                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2816                                 fixed_mode = drm_mode_duplicate(dev, scan);
2817                                 break;
2818                         }
2819                 }
2820
2821                 /* fallback to VBT if available for eDP */
2822                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2823                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2824                         if (fixed_mode)
2825                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2826                 }
2827                 intel_dp->panel_fixed_mode = fixed_mode;
2828
2829                 ironlake_edp_panel_vdd_off(intel_dp, false);
2830         }
2831
2832         intel_encoder->hot_plug = intel_dp_hot_plug;
2833
2834         if (is_edp(intel_dp)) {
2835                 intel_panel_init(&intel_connector->panel);
2836                 intel_panel_setup_backlight(connector);
2837         }
2838
2839         intel_dp_add_properties(intel_dp, connector);
2840
2841         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2842          * 0xd.  Failure to do so will result in spurious interrupts being
2843          * generated on the port when a cable is not attached.
2844          */
2845         if (IS_G4X(dev) && !IS_GM45(dev)) {
2846                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2847                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2848         }
2849 }