drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 static int
 113 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 114 {
 115         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 116
 117         switch (max_link_bw) {
 118         case DP_LINK_BW_1_62:
 119         case DP_LINK_BW_2_7:
 120                 break;
 121         default:
 122                 max_link_bw = DP_LINK_BW_1_62;
 123                 break;
 124         }
 125         return max_link_bw;
 126 }
 127
 128 /*
 129  * The units on the numbers in the next two are... bizarre.  Examples will
 130  * make it clearer; this one parallels an example in the eDP spec.
 131  *
 132  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 133  *
 134  *     270000 * 1 * 8 / 10 == 216000
 135  *
 136  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 137  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 138  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 139  * 119000.  At 18bpp that's 2142000 kilobits per second.
 140  *
 141  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 142  * get the result in decakilobits instead of kilobits.
 143  */
 144
 145 static int
 146 intel_dp_link_required(int pixel_clock, int bpp)
 147 {
 148         return (pixel_clock * bpp + 9) / 10;
 149 }
 150
 151 static int
 152 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 153 {
 154         return (max_link_clock * max_lanes * 8) / 10;
 155 }
 156
 157 static int
 158 intel_dp_mode_valid(struct drm_connector *connector,
 159                     struct drm_display_mode *mode)
 160 {
 161         struct intel_dp *intel_dp = intel_attached_dp(connector);
 162         struct intel_connector *intel_connector = to_intel_connector(connector);
 163         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 164         int target_clock = mode->clock;
 165         int max_rate, mode_rate, max_lanes, max_link_clock;
 166
 167         if (is_edp(intel_dp) && fixed_mode) {
 168                 if (mode->hdisplay > fixed_mode->hdisplay)
 169                         return MODE_PANEL;
 170
 171                 if (mode->vdisplay > fixed_mode->vdisplay)
 172                         return MODE_PANEL;
 173
 174                 target_clock = fixed_mode->clock;
 175         }
 176
 177         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 178         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 179
 180         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 181         mode_rate = intel_dp_link_required(target_clock, 18);
 182
 183         if (mode_rate > max_rate)
 184                 return MODE_CLOCK_HIGH;
 185
 186         if (mode->clock < 10000)
 187                 return MODE_CLOCK_LOW;
 188
 189         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 190                 return MODE_H_ILLEGAL;
 191
 192         return MODE_OK;
 193 }
 194
 195 static uint32_t
 196 pack_aux(uint8_t *src, int src_bytes)
 197 {
 198         int     i;
 199         uint32_t v = 0;
 200
 201         if (src_bytes > 4)
 202                 src_bytes = 4;
 203         for (i = 0; i < src_bytes; i++)
 204                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 205         return v;
 206 }
 207
 208 static void
 209 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 210 {
 211         int i;
 212         if (dst_bytes > 4)
 213                 dst_bytes = 4;
 214         for (i = 0; i < dst_bytes; i++)
 215                 dst[i] = src >> ((3-i) * 8);
 216 }
 217
 218 /* hrawclock is 1/4 the FSB frequency */
 219 static int
 220 intel_hrawclk(struct drm_device *dev)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         uint32_t clkcfg;
 224
 225         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 226         if (IS_VALLEYVIEW(dev))
 227                 return 200;
 228
 229         clkcfg = I915_READ(CLKCFG);
 230         switch (clkcfg & CLKCFG_FSB_MASK) {
 231         case CLKCFG_FSB_400:
 232                 return 100;
 233         case CLKCFG_FSB_533:
 234                 return 133;
 235         case CLKCFG_FSB_667:
 236                 return 166;
 237         case CLKCFG_FSB_800:
 238                 return 200;
 239         case CLKCFG_FSB_1067:
 240                 return 266;
 241         case CLKCFG_FSB_1333:
 242                 return 333;
 243         /* these two are just a guess; one of them might be right */
 244         case CLKCFG_FSB_1600:
 245         case CLKCFG_FSB_1600_ALT:
 246                 return 400;
 247         default:
 248                 return 133;
 249         }
 250 }
 251
 252 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 253 {
 254         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         u32 pp_stat_reg;
 257
 258         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 259         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 260 }
 261
 262 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 263 {
 264         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 265         struct drm_i915_private *dev_priv = dev->dev_private;
 266         u32 pp_ctrl_reg;
 267
 268         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 269         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 270 }
 271
 272 static void
 273 intel_dp_check_edp(struct intel_dp *intel_dp)
 274 {
 275         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         u32 pp_stat_reg, pp_ctrl_reg;
 278
 279         if (!is_edp(intel_dp))
 280                 return;
 281
 282         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 283         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 284
 285         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 286                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 287                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 288                                 I915_READ(pp_stat_reg),
 289                                 I915_READ(pp_ctrl_reg));
 290         }
 291 }
 292
 293 static uint32_t
 294 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_device *dev = intel_dig_port->base.base.dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 300         uint32_t status;
 301         bool done;
 302
 303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 304         if (has_aux_irq)
 305                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 306                                           msecs_to_jiffies(10));
 307         else
 308                 done = wait_for_atomic(C, 10) == 0;
 309         if (!done)
 310                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 311                           has_aux_irq);
 312 #undef C
 313
 314         return status;
 315 }
 316
 317 static int
 318 intel_dp_aux_ch(struct intel_dp *intel_dp,
 319                 uint8_t *send, int send_bytes,
 320                 uint8_t *recv, int recv_size)
 321 {
 322         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 323         struct drm_device *dev = intel_dig_port->base.base.dev;
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 326         uint32_t ch_data = ch_ctl + 4;
 327         int i, ret, recv_bytes;
 328         uint32_t status;
 329         uint32_t aux_clock_divider;
 330         int try, precharge;
 331         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 332
 333         /* dp aux is extremely sensitive to irq latency, hence request the
 334          * lowest possible wakeup latency and so prevent the cpu from going into
 335          * deep sleep states.
 336          */
 337         pm_qos_update_request(&dev_priv->pm_qos, 0);
 338
 339         intel_dp_check_edp(intel_dp);
 340         /* The clock divider is based off the hrawclk,
 341          * and would like to run at 2MHz. So, take the
 342          * hrawclk value and divide by 2 and use that
 343          *
 344          * Note that PCH attached eDP panels should use a 125MHz input
 345          * clock divider.
 346          */
 347         if (is_cpu_edp(intel_dp)) {
 348                 if (HAS_DDI(dev))
 349                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 350                 else if (IS_VALLEYVIEW(dev))
 351                         aux_clock_divider = 100;
 352                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 353                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 354                 else
 355                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 356         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 357                 /* Workaround for non-ULT HSW */
 358                 aux_clock_divider = 74;
 359         } else if (HAS_PCH_SPLIT(dev)) {
 360                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 361         } else {
 362                 aux_clock_divider = intel_hrawclk(dev) / 2;
 363         }
 364
 365         if (IS_GEN6(dev))
 366                 precharge = 3;
 367         else
 368                 precharge = 5;
 369
 370         /* Try to wait for any previous AUX channel activity */
 371         for (try = 0; try < 3; try++) {
 372                 status = I915_READ_NOTRACE(ch_ctl);
 373                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 374                         break;
 375                 msleep(1);
 376         }
 377
 378         if (try == 3) {
 379                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 380                      I915_READ(ch_ctl));
 381                 ret = -EBUSY;
 382                 goto out;
 383         }
 384
 385         /* Must try at least 3 times according to DP spec */
 386         for (try = 0; try < 5; try++) {
 387                 /* Load the send data into the aux channel data registers */
 388                 for (i = 0; i < send_bytes; i += 4)
 389                         I915_WRITE(ch_data + i,
 390                                    pack_aux(send + i, send_bytes - i));
 391
 392                 /* Send the command and wait for it to complete */
 393                 I915_WRITE(ch_ctl,
 394                            DP_AUX_CH_CTL_SEND_BUSY |
 395                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 396                            DP_AUX_CH_CTL_TIME_OUT_400us |
 397                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 398                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 399                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 400                            DP_AUX_CH_CTL_DONE |
 401                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 402                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 403
 404                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 405
 406                 /* Clear done status and any errors */
 407                 I915_WRITE(ch_ctl,
 408                            status |
 409                            DP_AUX_CH_CTL_DONE |
 410                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 411                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 412
 413                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 414                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 415                         continue;
 416                 if (status & DP_AUX_CH_CTL_DONE)
 417                         break;
 418         }
 419
 420         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 421                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 422                 ret = -EBUSY;
 423                 goto out;
 424         }
 425
 426         /* Check for timeout or receive error.
 427          * Timeouts occur when the sink is not connected
 428          */
 429         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 430                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 431                 ret = -EIO;
 432                 goto out;
 433         }
 434
 435         /* Timeouts occur when the device isn't connected, so they're
 436          * "normal" -- don't fill the kernel log with these */
 437         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 438                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 439                 ret = -ETIMEDOUT;
 440                 goto out;
 441         }
 442
 443         /* Unload any bytes sent back from the other side */
 444         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 445                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 446         if (recv_bytes > recv_size)
 447                 recv_bytes = recv_size;
 448
 449         for (i = 0; i < recv_bytes; i += 4)
 450                 unpack_aux(I915_READ(ch_data + i),
 451                            recv + i, recv_bytes - i);
 452
 453         ret = recv_bytes;
 454 out:
 455         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 456
 457         return ret;
 458 }
 459
 460 /* Write data to the aux channel in native mode */
 461 static int
 462 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 463                           uint16_t address, uint8_t *send, int send_bytes)
 464 {
 465         int ret;
 466         uint8_t msg[20];
 467         int msg_bytes;
 468         uint8_t ack;
 469
 470         intel_dp_check_edp(intel_dp);
 471         if (send_bytes > 16)
 472                 return -1;
 473         msg[0] = AUX_NATIVE_WRITE << 4;
 474         msg[1] = address >> 8;
 475         msg[2] = address & 0xff;
 476         msg[3] = send_bytes - 1;
 477         memcpy(&msg[4], send, send_bytes);
 478         msg_bytes = send_bytes + 4;
 479         for (;;) {
 480                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 481                 if (ret < 0)
 482                         return ret;
 483                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 484                         break;
 485                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 486                         udelay(100);
 487                 else
 488                         return -EIO;
 489         }
 490         return send_bytes;
 491 }
 492
 493 /* Write a single byte to the aux channel in native mode */
 494 static int
 495 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 496                             uint16_t address, uint8_t byte)
 497 {
 498         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 499 }
 500
 501 /* read bytes from a native aux channel */
 502 static int
 503 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 504                          uint16_t address, uint8_t *recv, int recv_bytes)
 505 {
 506         uint8_t msg[4];
 507         int msg_bytes;
 508         uint8_t reply[20];
 509         int reply_bytes;
 510         uint8_t ack;
 511         int ret;
 512
 513         intel_dp_check_edp(intel_dp);
 514         msg[0] = AUX_NATIVE_READ << 4;
 515         msg[1] = address >> 8;
 516         msg[2] = address & 0xff;
 517         msg[3] = recv_bytes - 1;
 518
 519         msg_bytes = 4;
 520         reply_bytes = recv_bytes + 1;
 521
 522         for (;;) {
 523                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 524                                       reply, reply_bytes);
 525                 if (ret == 0)
 526                         return -EPROTO;
 527                 if (ret < 0)
 528                         return ret;
 529                 ack = reply[0];
 530                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 531                         memcpy(recv, reply + 1, ret - 1);
 532                         return ret - 1;
 533                 }
 534                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 535                         udelay(100);
 536                 else
 537                         return -EIO;
 538         }
 539 }
 540
 541 static int
 542 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 543                     uint8_t write_byte, uint8_t *read_byte)
 544 {
 545         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 546         struct intel_dp *intel_dp = container_of(adapter,
 547                                                 struct intel_dp,
 548                                                 adapter);
 549         uint16_t address = algo_data->address;
 550         uint8_t msg[5];
 551         uint8_t reply[2];
 552         unsigned retry;
 553         int msg_bytes;
 554         int reply_bytes;
 555         int ret;
 556
 557         intel_dp_check_edp(intel_dp);
 558         /* Set up the command byte */
 559         if (mode & MODE_I2C_READ)
 560                 msg[0] = AUX_I2C_READ << 4;
 561         else
 562                 msg[0] = AUX_I2C_WRITE << 4;
 563
 564         if (!(mode & MODE_I2C_STOP))
 565                 msg[0] |= AUX_I2C_MOT << 4;
 566
 567         msg[1] = address >> 8;
 568         msg[2] = address;
 569
 570         switch (mode) {
 571         case MODE_I2C_WRITE:
 572                 msg[3] = 0;
 573                 msg[4] = write_byte;
 574                 msg_bytes = 5;
 575                 reply_bytes = 1;
 576                 break;
 577         case MODE_I2C_READ:
 578                 msg[3] = 0;
 579                 msg_bytes = 4;
 580                 reply_bytes = 2;
 581                 break;
 582         default:
 583                 msg_bytes = 3;
 584                 reply_bytes = 1;
 585                 break;
 586         }
 587
 588         for (retry = 0; retry < 5; retry++) {
 589                 ret = intel_dp_aux_ch(intel_dp,
 590                                       msg, msg_bytes,
 591                                       reply, reply_bytes);
 592                 if (ret < 0) {
 593                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 594                         return ret;
 595                 }
 596
 597                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 598                 case AUX_NATIVE_REPLY_ACK:
 599                         /* I2C-over-AUX Reply field is only valid
 600                          * when paired with AUX ACK.
 601                          */
 602                         break;
 603                 case AUX_NATIVE_REPLY_NACK:
 604                         DRM_DEBUG_KMS("aux_ch native nack\n");
 605                         return -EREMOTEIO;
 606                 case AUX_NATIVE_REPLY_DEFER:
 607                         udelay(100);
 608                         continue;
 609                 default:
 610                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 611                                   reply[0]);
 612                         return -EREMOTEIO;
 613                 }
 614
 615                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 616                 case AUX_I2C_REPLY_ACK:
 617                         if (mode == MODE_I2C_READ) {
 618                                 *read_byte = reply[1];
 619                         }
 620                         return reply_bytes - 1;
 621                 case AUX_I2C_REPLY_NACK:
 622                         DRM_DEBUG_KMS("aux_i2c nack\n");
 623                         return -EREMOTEIO;
 624                 case AUX_I2C_REPLY_DEFER:
 625                         DRM_DEBUG_KMS("aux_i2c defer\n");
 626                         udelay(100);
 627                         break;
 628                 default:
 629                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 630                         return -EREMOTEIO;
 631                 }
 632         }
 633
 634         DRM_ERROR("too many retries, giving up\n");
 635         return -EREMOTEIO;
 636 }
 637
 638 static int
 639 intel_dp_i2c_init(struct intel_dp *intel_dp,
 640                   struct intel_connector *intel_connector, const char *name)
 641 {
 642         int     ret;
 643
 644         DRM_DEBUG_KMS("i2c_init %s\n", name);
 645         intel_dp->algo.running = false;
 646         intel_dp->algo.address = 0;
 647         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 648
 649         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 650         intel_dp->adapter.owner = THIS_MODULE;
 651         intel_dp->adapter.class = I2C_CLASS_DDC;
 652         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 653         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 654         intel_dp->adapter.algo_data = &intel_dp->algo;
 655         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 656
 657         ironlake_edp_panel_vdd_on(intel_dp);
 658         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 659         ironlake_edp_panel_vdd_off(intel_dp, false);
 660         return ret;
 661 }
 662
 663 static void
 664 intel_dp_set_clock(struct intel_encoder *encoder,
 665                    struct intel_crtc_config *pipe_config, int link_bw)
 666 {
 667         struct drm_device *dev = encoder->base.dev;
 668
 669         if (IS_G4X(dev)) {
 670                 if (link_bw == DP_LINK_BW_1_62) {
 671                         pipe_config->dpll.p1 = 2;
 672                         pipe_config->dpll.p2 = 10;
 673                         pipe_config->dpll.n = 2;
 674                         pipe_config->dpll.m1 = 23;
 675                         pipe_config->dpll.m2 = 8;
 676                 } else {
 677                         pipe_config->dpll.p1 = 1;
 678                         pipe_config->dpll.p2 = 10;
 679                         pipe_config->dpll.n = 1;
 680                         pipe_config->dpll.m1 = 14;
 681                         pipe_config->dpll.m2 = 2;
 682                 }
 683                 pipe_config->clock_set = true;
 684         } else if (IS_HASWELL(dev)) {
 685                 /* Haswell has special-purpose DP DDI clocks. */
 686         } else if (HAS_PCH_SPLIT(dev)) {
 687                 if (link_bw == DP_LINK_BW_1_62) {
 688                         pipe_config->dpll.n = 1;
 689                         pipe_config->dpll.p1 = 2;
 690                         pipe_config->dpll.p2 = 10;
 691                         pipe_config->dpll.m1 = 12;
 692                         pipe_config->dpll.m2 = 9;
 693                 } else {
 694                         pipe_config->dpll.n = 2;
 695                         pipe_config->dpll.p1 = 1;
 696                         pipe_config->dpll.p2 = 10;
 697                         pipe_config->dpll.m1 = 14;
 698                         pipe_config->dpll.m2 = 8;
 699                 }
 700                 pipe_config->clock_set = true;
 701         } else if (IS_VALLEYVIEW(dev)) {
 702                 /* FIXME: Need to figure out optimized DP clocks for vlv. */
 703         }
 704 }
 705
 706 bool
 707 intel_dp_compute_config(struct intel_encoder *encoder,
 708                         struct intel_crtc_config *pipe_config)
 709 {
 710         struct drm_device *dev = encoder->base.dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 713         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 714         struct intel_crtc *intel_crtc = encoder->new_crtc;
 715         struct intel_connector *intel_connector = intel_dp->attached_connector;
 716         int lane_count, clock;
 717         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 718         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 719         int bpp, mode_rate;
 720         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 721         int target_clock, link_avail, link_clock;
 722
 723         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
 724                 pipe_config->has_pch_encoder = true;
 725
 726         pipe_config->has_dp_encoder = true;
 727
 728         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 729                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 730                                        adjusted_mode);
 731                 if (!HAS_PCH_SPLIT(dev))
 732                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 733                                                  intel_connector->panel.fitting_mode);
 734                 else
 735                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 736                                                 intel_connector->panel.fitting_mode);
 737         }
 738         /* We need to take the panel's fixed mode into account. */
 739         target_clock = adjusted_mode->clock;
 740
 741         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 742                 return false;
 743
 744         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 745                       "max bw %02x pixel clock %iKHz\n",
 746                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 747
 748         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 749          * bpc in between. */
 750         bpp = pipe_config->pipe_bpp;
 751
 752         /*
 753          * eDP panels are really fickle, try to enfore the bpp the firmware
 754          * recomments. This means we'll up-dither 16bpp framebuffers on
 755          * high-depth panels.
 756          */
 757         if (is_edp(intel_dp) && dev_priv->edp.bpp) {
 758                 DRM_DEBUG_KMS("forcing bpp for eDP panel to BIOS-provided %i\n",
 759                               dev_priv->edp.bpp);
 760                 bpp = dev_priv->edp.bpp;
 761         }
 762
 763         for (; bpp >= 6*3; bpp -= 2*3) {
 764                 mode_rate = intel_dp_link_required(target_clock, bpp);
 765
 766                 for (clock = 0; clock <= max_clock; clock++) {
 767                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 768                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 769                                 link_avail = intel_dp_max_data_rate(link_clock,
 770                                                                     lane_count);
 771
 772                                 if (mode_rate <= link_avail) {
 773                                         goto found;
 774                                 }
 775                         }
 776                 }
 777         }
 778
 779         return false;
 780
 781 found:
 782         if (intel_dp->color_range_auto) {
 783                 /*
 784                  * See:
 785                  * CEA-861-E - 5.1 Default Encoding Parameters
 786                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 787                  */
 788                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 789                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 790                 else
 791                         intel_dp->color_range = 0;
 792         }
 793
 794         if (intel_dp->color_range)
 795                 pipe_config->limited_color_range = true;
 796
 797         intel_dp->link_bw = bws[clock];
 798         intel_dp->lane_count = lane_count;
 799         adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 800         pipe_config->pixel_target_clock = target_clock;
 801
 802         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 803                       intel_dp->link_bw, intel_dp->lane_count,
 804                       adjusted_mode->clock, bpp);
 805         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 806                       mode_rate, link_avail);
 807
 808         intel_link_compute_m_n(bpp, lane_count,
 809                                target_clock, adjusted_mode->clock,
 810                                &pipe_config->dp_m_n);
 811
 812         pipe_config->pipe_bpp = bpp;
 813
 814         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 815
 816         return true;
 817 }
 818
 819 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 820 {
 821         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 822         intel_dp->link_configuration[0] = intel_dp->link_bw;
 823         intel_dp->link_configuration[1] = intel_dp->lane_count;
 824         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 825         /*
 826          * Check for DPCD version > 1.1 and enhanced framing support
 827          */
 828         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 829             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 830                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 831         }
 832 }
 833
 834 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 835 {
 836         struct drm_device *dev = crtc->dev;
 837         struct drm_i915_private *dev_priv = dev->dev_private;
 838         u32 dpa_ctl;
 839
 840         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 841         dpa_ctl = I915_READ(DP_A);
 842         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 843
 844         if (clock < 200000) {
 845                 /* For a long time we've carried around a ILK-DevA w/a for the
 846                  * 160MHz clock. If we're really unlucky, it's still required.
 847                  */
 848                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 849                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 850         } else {
 851                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 852         }
 853
 854         I915_WRITE(DP_A, dpa_ctl);
 855
 856         POSTING_READ(DP_A);
 857         udelay(500);
 858 }
 859
 860 static void
 861 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 862                   struct drm_display_mode *adjusted_mode)
 863 {
 864         struct drm_device *dev = encoder->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 867         struct drm_crtc *crtc = encoder->crtc;
 868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 869
 870         /*
 871          * There are four kinds of DP registers:
 872          *
 873          *      IBX PCH
 874          *      SNB CPU
 875          *      IVB CPU
 876          *      CPT PCH
 877          *
 878          * IBX PCH and CPU are the same for almost everything,
 879          * except that the CPU DP PLL is configured in this
 880          * register
 881          *
 882          * CPT PCH is quite different, having many bits moved
 883          * to the TRANS_DP_CTL register instead. That
 884          * configuration happens (oddly) in ironlake_pch_enable
 885          */
 886
 887         /* Preserve the BIOS-computed detected bit. This is
 888          * supposed to be read-only.
 889          */
 890         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 891
 892         /* Handle DP bits in common between all three register formats */
 893         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 894         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 895
 896         if (intel_dp->has_audio) {
 897                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 898                                  pipe_name(intel_crtc->pipe));
 899                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 900                 intel_write_eld(encoder, adjusted_mode);
 901         }
 902
 903         intel_dp_init_link_config(intel_dp);
 904
 905         /* Split out the IBX/CPU vs CPT settings */
 906
 907         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 908                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 909                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 910                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 911                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 912                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 913
 914                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 915                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 916
 917                 intel_dp->DP |= intel_crtc->pipe << 29;
 918
 919                 /* don't miss out required setting for eDP */
 920                 if (adjusted_mode->clock < 200000)
 921                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 922                 else
 923                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 924         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 925                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 926                         intel_dp->DP |= intel_dp->color_range;
 927
 928                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 929                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 930                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 931                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 932                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 933
 934                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 935                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 936
 937                 if (intel_crtc->pipe == 1)
 938                         intel_dp->DP |= DP_PIPEB_SELECT;
 939
 940                 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 941                         /* don't miss out required setting for eDP */
 942                         if (adjusted_mode->clock < 200000)
 943                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 944                         else
 945                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 946                 }
 947         } else {
 948                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 949         }
 950
 951         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 952                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 953 }
 954
 955 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 956 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 957
 958 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 959 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 960
 961 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 962 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 963
 964 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 965                                        u32 mask,
 966                                        u32 value)
 967 {
 968         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         u32 pp_stat_reg, pp_ctrl_reg;
 971
 972         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 973         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 974
 975         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 976                         mask, value,
 977                         I915_READ(pp_stat_reg),
 978                         I915_READ(pp_ctrl_reg));
 979
 980         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 981                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 982                                 I915_READ(pp_stat_reg),
 983                                 I915_READ(pp_ctrl_reg));
 984         }
 985 }
 986
 987 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 988 {
 989         DRM_DEBUG_KMS("Wait for panel power on\n");
 990         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 991 }
 992
 993 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 994 {
 995         DRM_DEBUG_KMS("Wait for panel power off time\n");
 996         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 997 }
 998
 999 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1000 {
1001         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1002         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1003 }
1004
1005
1006 /* Read the current pp_control value, unlocking the register if it
1007  * is locked
1008  */
1009
1010 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1011 {
1012         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1013         struct drm_i915_private *dev_priv = dev->dev_private;
1014         u32 control;
1015         u32 pp_ctrl_reg;
1016
1017         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1018         control = I915_READ(pp_ctrl_reg);
1019
1020         control &= ~PANEL_UNLOCK_MASK;
1021         control |= PANEL_UNLOCK_REGS;
1022         return control;
1023 }
1024
1025 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1026 {
1027         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029         u32 pp;
1030         u32 pp_stat_reg, pp_ctrl_reg;
1031
1032         if (!is_edp(intel_dp))
1033                 return;
1034         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1035
1036         WARN(intel_dp->want_panel_vdd,
1037              "eDP VDD already requested on\n");
1038
1039         intel_dp->want_panel_vdd = true;
1040
1041         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1042                 DRM_DEBUG_KMS("eDP VDD already on\n");
1043                 return;
1044         }
1045
1046         if (!ironlake_edp_have_panel_power(intel_dp))
1047                 ironlake_wait_panel_power_cycle(intel_dp);
1048
1049         pp = ironlake_get_pp_control(intel_dp);
1050         pp |= EDP_FORCE_VDD;
1051
1052         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1053         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1054
1055         I915_WRITE(pp_ctrl_reg, pp);
1056         POSTING_READ(pp_ctrl_reg);
1057         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1058                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1059         /*
1060          * If the panel wasn't on, delay before accessing aux channel
1061          */
1062         if (!ironlake_edp_have_panel_power(intel_dp)) {
1063                 DRM_DEBUG_KMS("eDP was not running\n");
1064                 msleep(intel_dp->panel_power_up_delay);
1065         }
1066 }
1067
1068 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1069 {
1070         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 pp;
1073         u32 pp_stat_reg, pp_ctrl_reg;
1074
1075         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1076
1077         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1078                 pp = ironlake_get_pp_control(intel_dp);
1079                 pp &= ~EDP_FORCE_VDD;
1080
1081                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1082                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1083
1084                 I915_WRITE(pp_ctrl_reg, pp);
1085                 POSTING_READ(pp_ctrl_reg);
1086
1087                 /* Make sure sequencer is idle before allowing subsequent activity */
1088                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1089                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1090                 msleep(intel_dp->panel_power_down_delay);
1091         }
1092 }
1093
1094 static void ironlake_panel_vdd_work(struct work_struct *__work)
1095 {
1096         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1097                                                  struct intel_dp, panel_vdd_work);
1098         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1099
1100         mutex_lock(&dev->mode_config.mutex);
1101         ironlake_panel_vdd_off_sync(intel_dp);
1102         mutex_unlock(&dev->mode_config.mutex);
1103 }
1104
1105 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1106 {
1107         if (!is_edp(intel_dp))
1108                 return;
1109
1110         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1111         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1112
1113         intel_dp->want_panel_vdd = false;
1114
1115         if (sync) {
1116                 ironlake_panel_vdd_off_sync(intel_dp);
1117         } else {
1118                 /*
1119                  * Queue the timer to fire a long
1120                  * time from now (relative to the power down delay)
1121                  * to keep the panel power up across a sequence of operations
1122                  */
1123                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1124                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1125         }
1126 }
1127
1128 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1129 {
1130         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132         u32 pp;
1133         u32 pp_ctrl_reg;
1134
1135         if (!is_edp(intel_dp))
1136                 return;
1137
1138         DRM_DEBUG_KMS("Turn eDP power on\n");
1139
1140         if (ironlake_edp_have_panel_power(intel_dp)) {
1141                 DRM_DEBUG_KMS("eDP power already on\n");
1142                 return;
1143         }
1144
1145         ironlake_wait_panel_power_cycle(intel_dp);
1146
1147         pp = ironlake_get_pp_control(intel_dp);
1148         if (IS_GEN5(dev)) {
1149                 /* ILK workaround: disable reset around power sequence */
1150                 pp &= ~PANEL_POWER_RESET;
1151                 I915_WRITE(PCH_PP_CONTROL, pp);
1152                 POSTING_READ(PCH_PP_CONTROL);
1153         }
1154
1155         pp |= POWER_TARGET_ON;
1156         if (!IS_GEN5(dev))
1157                 pp |= PANEL_POWER_RESET;
1158
1159         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1160
1161         I915_WRITE(pp_ctrl_reg, pp);
1162         POSTING_READ(pp_ctrl_reg);
1163
1164         ironlake_wait_panel_on(intel_dp);
1165
1166         if (IS_GEN5(dev)) {
1167                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1168                 I915_WRITE(PCH_PP_CONTROL, pp);
1169                 POSTING_READ(PCH_PP_CONTROL);
1170         }
1171 }
1172
1173 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1174 {
1175         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1176         struct drm_i915_private *dev_priv = dev->dev_private;
1177         u32 pp;
1178         u32 pp_ctrl_reg;
1179
1180         if (!is_edp(intel_dp))
1181                 return;
1182
1183         DRM_DEBUG_KMS("Turn eDP power off\n");
1184
1185         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1186
1187         pp = ironlake_get_pp_control(intel_dp);
1188         /* We need to switch off panel power _and_ force vdd, for otherwise some
1189          * panels get very unhappy and cease to work. */
1190         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1191
1192         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1193
1194         I915_WRITE(pp_ctrl_reg, pp);
1195         POSTING_READ(pp_ctrl_reg);
1196
1197         intel_dp->want_panel_vdd = false;
1198
1199         ironlake_wait_panel_off(intel_dp);
1200 }
1201
1202 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1203 {
1204         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205         struct drm_device *dev = intel_dig_port->base.base.dev;
1206         struct drm_i915_private *dev_priv = dev->dev_private;
1207         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1208         u32 pp;
1209         u32 pp_ctrl_reg;
1210
1211         if (!is_edp(intel_dp))
1212                 return;
1213
1214         DRM_DEBUG_KMS("\n");
1215         /*
1216          * If we enable the backlight right away following a panel power
1217          * on, we may see slight flicker as the panel syncs with the eDP
1218          * link.  So delay a bit to make sure the image is solid before
1219          * allowing it to appear.
1220          */
1221         msleep(intel_dp->backlight_on_delay);
1222         pp = ironlake_get_pp_control(intel_dp);
1223         pp |= EDP_BLC_ENABLE;
1224
1225         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1226
1227         I915_WRITE(pp_ctrl_reg, pp);
1228         POSTING_READ(pp_ctrl_reg);
1229
1230         intel_panel_enable_backlight(dev, pipe);
1231 }
1232
1233 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1234 {
1235         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1236         struct drm_i915_private *dev_priv = dev->dev_private;
1237         u32 pp;
1238         u32 pp_ctrl_reg;
1239
1240         if (!is_edp(intel_dp))
1241                 return;
1242
1243         intel_panel_disable_backlight(dev);
1244
1245         DRM_DEBUG_KMS("\n");
1246         pp = ironlake_get_pp_control(intel_dp);
1247         pp &= ~EDP_BLC_ENABLE;
1248
1249         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1250
1251         I915_WRITE(pp_ctrl_reg, pp);
1252         POSTING_READ(pp_ctrl_reg);
1253         msleep(intel_dp->backlight_off_delay);
1254 }
1255
1256 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1257 {
1258         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1259         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1260         struct drm_device *dev = crtc->dev;
1261         struct drm_i915_private *dev_priv = dev->dev_private;
1262         u32 dpa_ctl;
1263
1264         assert_pipe_disabled(dev_priv,
1265                              to_intel_crtc(crtc)->pipe);
1266
1267         DRM_DEBUG_KMS("\n");
1268         dpa_ctl = I915_READ(DP_A);
1269         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1270         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1271
1272         /* We don't adjust intel_dp->DP while tearing down the link, to
1273          * facilitate link retraining (e.g. after hotplug). Hence clear all
1274          * enable bits here to ensure that we don't enable too much. */
1275         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1276         intel_dp->DP |= DP_PLL_ENABLE;
1277         I915_WRITE(DP_A, intel_dp->DP);
1278         POSTING_READ(DP_A);
1279         udelay(200);
1280 }
1281
1282 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1283 {
1284         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1285         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1286         struct drm_device *dev = crtc->dev;
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288         u32 dpa_ctl;
1289
1290         assert_pipe_disabled(dev_priv,
1291                              to_intel_crtc(crtc)->pipe);
1292
1293         dpa_ctl = I915_READ(DP_A);
1294         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1295              "dp pll off, should be on\n");
1296         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1297
1298         /* We can't rely on the value tracked for the DP register in
1299          * intel_dp->DP because link_down must not change that (otherwise link
1300          * re-training will fail. */
1301         dpa_ctl &= ~DP_PLL_ENABLE;
1302         I915_WRITE(DP_A, dpa_ctl);
1303         POSTING_READ(DP_A);
1304         udelay(200);
1305 }
1306
1307 /* If the sink supports it, try to set the power state appropriately */
1308 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1309 {
1310         int ret, i;
1311
1312         /* Should have a valid DPCD by this point */
1313         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1314                 return;
1315
1316         if (mode != DRM_MODE_DPMS_ON) {
1317                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1318                                                   DP_SET_POWER_D3);
1319                 if (ret != 1)
1320                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1321         } else {
1322                 /*
1323                  * When turning on, we need to retry for 1ms to give the sink
1324                  * time to wake up.
1325                  */
1326                 for (i = 0; i < 3; i++) {
1327                         ret = intel_dp_aux_native_write_1(intel_dp,
1328                                                           DP_SET_POWER,
1329                                                           DP_SET_POWER_D0);
1330                         if (ret == 1)
1331                                 break;
1332                         msleep(1);
1333                 }
1334         }
1335 }
1336
1337 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1338                                   enum pipe *pipe)
1339 {
1340         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1341         struct drm_device *dev = encoder->base.dev;
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343         u32 tmp = I915_READ(intel_dp->output_reg);
1344
1345         if (!(tmp & DP_PORT_EN))
1346                 return false;
1347
1348         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1349                 *pipe = PORT_TO_PIPE_CPT(tmp);
1350         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1351                 *pipe = PORT_TO_PIPE(tmp);
1352         } else {
1353                 u32 trans_sel;
1354                 u32 trans_dp;
1355                 int i;
1356
1357                 switch (intel_dp->output_reg) {
1358                 case PCH_DP_B:
1359                         trans_sel = TRANS_DP_PORT_SEL_B;
1360                         break;
1361                 case PCH_DP_C:
1362                         trans_sel = TRANS_DP_PORT_SEL_C;
1363                         break;
1364                 case PCH_DP_D:
1365                         trans_sel = TRANS_DP_PORT_SEL_D;
1366                         break;
1367                 default:
1368                         return true;
1369                 }
1370
1371                 for_each_pipe(i) {
1372                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1373                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1374                                 *pipe = i;
1375                                 return true;
1376                         }
1377                 }
1378
1379                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1380                               intel_dp->output_reg);
1381         }
1382
1383         return true;
1384 }
1385
1386 static void intel_disable_dp(struct intel_encoder *encoder)
1387 {
1388         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1389
1390         /* Make sure the panel is off before trying to change the mode. But also
1391          * ensure that we have vdd while we switch off the panel. */
1392         ironlake_edp_panel_vdd_on(intel_dp);
1393         ironlake_edp_backlight_off(intel_dp);
1394         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1395         ironlake_edp_panel_off(intel_dp);
1396
1397         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1398         if (!is_cpu_edp(intel_dp))
1399                 intel_dp_link_down(intel_dp);
1400 }
1401
1402 static void intel_post_disable_dp(struct intel_encoder *encoder)
1403 {
1404         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1405         struct drm_device *dev = encoder->base.dev;
1406
1407         if (is_cpu_edp(intel_dp)) {
1408                 intel_dp_link_down(intel_dp);
1409                 if (!IS_VALLEYVIEW(dev))
1410                         ironlake_edp_pll_off(intel_dp);
1411         }
1412 }
1413
1414 static void intel_enable_dp(struct intel_encoder *encoder)
1415 {
1416         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1417         struct drm_device *dev = encoder->base.dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1420
1421         if (WARN_ON(dp_reg & DP_PORT_EN))
1422                 return;
1423
1424         ironlake_edp_panel_vdd_on(intel_dp);
1425         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1426         intel_dp_start_link_train(intel_dp);
1427         ironlake_edp_panel_on(intel_dp);
1428         ironlake_edp_panel_vdd_off(intel_dp, true);
1429         intel_dp_complete_link_train(intel_dp);
1430         ironlake_edp_backlight_on(intel_dp);
1431
1432         if (IS_VALLEYVIEW(dev)) {
1433                 struct intel_digital_port *dport =
1434                         enc_to_dig_port(&encoder->base);
1435                 int channel = vlv_dport_to_channel(dport);
1436
1437                 vlv_wait_port_ready(dev_priv, channel);
1438         }
1439 }
1440
1441 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1442 {
1443         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1444         struct drm_device *dev = encoder->base.dev;
1445         struct drm_i915_private *dev_priv = dev->dev_private;
1446
1447         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1448                 ironlake_edp_pll_on(intel_dp);
1449
1450         if (IS_VALLEYVIEW(dev)) {
1451                 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1452                 struct intel_crtc *intel_crtc =
1453                         to_intel_crtc(encoder->base.crtc);
1454                 int port = vlv_dport_to_channel(dport);
1455                 int pipe = intel_crtc->pipe;
1456                 u32 val;
1457
1458                 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1459
1460                 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1461                 val = 0;
1462                 if (pipe)
1463                         val |= (1<<21);
1464                 else
1465                         val &= ~(1<<21);
1466                 val |= 0x001000c4;
1467                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1468
1469                 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1470                                  0x00760018);
1471                 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1472                                  0x00400888);
1473         }
1474 }
1475
1476 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1477 {
1478         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1479         struct drm_device *dev = encoder->base.dev;
1480         struct drm_i915_private *dev_priv = dev->dev_private;
1481         int port = vlv_dport_to_channel(dport);
1482
1483         if (!IS_VALLEYVIEW(dev))
1484                 return;
1485
1486         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1487
1488         /* Program Tx lane resets to default */
1489         intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1490                          DPIO_PCS_TX_LANE2_RESET |
1491                          DPIO_PCS_TX_LANE1_RESET);
1492         intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1493                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1494                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1495                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1496                                  DPIO_PCS_CLK_SOFT_RESET);
1497
1498         /* Fix up inter-pair skew failure */
1499         intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1500         intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1501         intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1502 }
1503
1504 /*
1505  * Native read with retry for link status and receiver capability reads for
1506  * cases where the sink may still be asleep.
1507  */
1508 static bool
1509 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1510                                uint8_t *recv, int recv_bytes)
1511 {
1512         int ret, i;
1513
1514         /*
1515          * Sinks are *supposed* to come up within 1ms from an off state,
1516          * but we're also supposed to retry 3 times per the spec.
1517          */
1518         for (i = 0; i < 3; i++) {
1519                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1520                                                recv_bytes);
1521                 if (ret == recv_bytes)
1522                         return true;
1523                 msleep(1);
1524         }
1525
1526         return false;
1527 }
1528
1529 /*
1530  * Fetch AUX CH registers 0x202 - 0x207 which contain
1531  * link status information
1532  */
1533 static bool
1534 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1535 {
1536         return intel_dp_aux_native_read_retry(intel_dp,
1537                                               DP_LANE0_1_STATUS,
1538                                               link_status,
1539                                               DP_LINK_STATUS_SIZE);
1540 }
1541
1542 #if 0
1543 static char     *voltage_names[] = {
1544         "0.4V", "0.6V", "0.8V", "1.2V"
1545 };
1546 static char     *pre_emph_names[] = {
1547         "0dB", "3.5dB", "6dB", "9.5dB"
1548 };
1549 static char     *link_train_names[] = {
1550         "pattern 1", "pattern 2", "idle", "off"
1551 };
1552 #endif
1553
1554 /*
1555  * These are source-specific values; current Intel hardware supports
1556  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1557  */
1558
1559 static uint8_t
1560 intel_dp_voltage_max(struct intel_dp *intel_dp)
1561 {
1562         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1563
1564         if (IS_VALLEYVIEW(dev))
1565                 return DP_TRAIN_VOLTAGE_SWING_1200;
1566         else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1567                 return DP_TRAIN_VOLTAGE_SWING_800;
1568         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1569                 return DP_TRAIN_VOLTAGE_SWING_1200;
1570         else
1571                 return DP_TRAIN_VOLTAGE_SWING_800;
1572 }
1573
1574 static uint8_t
1575 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1576 {
1577         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1578
1579         if (HAS_DDI(dev)) {
1580                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1581                 case DP_TRAIN_VOLTAGE_SWING_400:
1582                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1583                 case DP_TRAIN_VOLTAGE_SWING_600:
1584                         return DP_TRAIN_PRE_EMPHASIS_6;
1585                 case DP_TRAIN_VOLTAGE_SWING_800:
1586                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1587                 case DP_TRAIN_VOLTAGE_SWING_1200:
1588                 default:
1589                         return DP_TRAIN_PRE_EMPHASIS_0;
1590                 }
1591         } else if (IS_VALLEYVIEW(dev)) {
1592                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1593                 case DP_TRAIN_VOLTAGE_SWING_400:
1594                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1595                 case DP_TRAIN_VOLTAGE_SWING_600:
1596                         return DP_TRAIN_PRE_EMPHASIS_6;
1597                 case DP_TRAIN_VOLTAGE_SWING_800:
1598                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1599                 case DP_TRAIN_VOLTAGE_SWING_1200:
1600                 default:
1601                         return DP_TRAIN_PRE_EMPHASIS_0;
1602                 }
1603         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1604                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1605                 case DP_TRAIN_VOLTAGE_SWING_400:
1606                         return DP_TRAIN_PRE_EMPHASIS_6;
1607                 case DP_TRAIN_VOLTAGE_SWING_600:
1608                 case DP_TRAIN_VOLTAGE_SWING_800:
1609                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1610                 default:
1611                         return DP_TRAIN_PRE_EMPHASIS_0;
1612                 }
1613         } else {
1614                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1615                 case DP_TRAIN_VOLTAGE_SWING_400:
1616                         return DP_TRAIN_PRE_EMPHASIS_6;
1617                 case DP_TRAIN_VOLTAGE_SWING_600:
1618                         return DP_TRAIN_PRE_EMPHASIS_6;
1619                 case DP_TRAIN_VOLTAGE_SWING_800:
1620                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1621                 case DP_TRAIN_VOLTAGE_SWING_1200:
1622                 default:
1623                         return DP_TRAIN_PRE_EMPHASIS_0;
1624                 }
1625         }
1626 }
1627
1628 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1629 {
1630         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1633         unsigned long demph_reg_value, preemph_reg_value,
1634                 uniqtranscale_reg_value;
1635         uint8_t train_set = intel_dp->train_set[0];
1636         int port = vlv_dport_to_channel(dport);
1637
1638         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1639
1640         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1641         case DP_TRAIN_PRE_EMPHASIS_0:
1642                 preemph_reg_value = 0x0004000;
1643                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1644                 case DP_TRAIN_VOLTAGE_SWING_400:
1645                         demph_reg_value = 0x2B405555;
1646                         uniqtranscale_reg_value = 0x552AB83A;
1647                         break;
1648                 case DP_TRAIN_VOLTAGE_SWING_600:
1649                         demph_reg_value = 0x2B404040;
1650                         uniqtranscale_reg_value = 0x5548B83A;
1651                         break;
1652                 case DP_TRAIN_VOLTAGE_SWING_800:
1653                         demph_reg_value = 0x2B245555;
1654                         uniqtranscale_reg_value = 0x5560B83A;
1655                         break;
1656                 case DP_TRAIN_VOLTAGE_SWING_1200:
1657                         demph_reg_value = 0x2B405555;
1658                         uniqtranscale_reg_value = 0x5598DA3A;
1659                         break;
1660                 default:
1661                         return 0;
1662                 }
1663                 break;
1664         case DP_TRAIN_PRE_EMPHASIS_3_5:
1665                 preemph_reg_value = 0x0002000;
1666                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1667                 case DP_TRAIN_VOLTAGE_SWING_400:
1668                         demph_reg_value = 0x2B404040;
1669                         uniqtranscale_reg_value = 0x5552B83A;
1670                         break;
1671                 case DP_TRAIN_VOLTAGE_SWING_600:
1672                         demph_reg_value = 0x2B404848;
1673                         uniqtranscale_reg_value = 0x5580B83A;
1674                         break;
1675                 case DP_TRAIN_VOLTAGE_SWING_800:
1676                         demph_reg_value = 0x2B404040;
1677                         uniqtranscale_reg_value = 0x55ADDA3A;
1678                         break;
1679                 default:
1680                         return 0;
1681                 }
1682                 break;
1683         case DP_TRAIN_PRE_EMPHASIS_6:
1684                 preemph_reg_value = 0x0000000;
1685                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1686                 case DP_TRAIN_VOLTAGE_SWING_400:
1687                         demph_reg_value = 0x2B305555;
1688                         uniqtranscale_reg_value = 0x5570B83A;
1689                         break;
1690                 case DP_TRAIN_VOLTAGE_SWING_600:
1691                         demph_reg_value = 0x2B2B4040;
1692                         uniqtranscale_reg_value = 0x55ADDA3A;
1693                         break;
1694                 default:
1695                         return 0;
1696                 }
1697                 break;
1698         case DP_TRAIN_PRE_EMPHASIS_9_5:
1699                 preemph_reg_value = 0x0006000;
1700                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1701                 case DP_TRAIN_VOLTAGE_SWING_400:
1702                         demph_reg_value = 0x1B405555;
1703                         uniqtranscale_reg_value = 0x55ADDA3A;
1704                         break;
1705                 default:
1706                         return 0;
1707                 }
1708                 break;
1709         default:
1710                 return 0;
1711         }
1712
1713         intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1714         intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1715         intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1716                          uniqtranscale_reg_value);
1717         intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1718         intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1719         intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1720         intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1721
1722         return 0;
1723 }
1724
1725 static void
1726 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1727 {
1728         uint8_t v = 0;
1729         uint8_t p = 0;
1730         int lane;
1731         uint8_t voltage_max;
1732         uint8_t preemph_max;
1733
1734         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1735                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1736                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1737
1738                 if (this_v > v)
1739                         v = this_v;
1740                 if (this_p > p)
1741                         p = this_p;
1742         }
1743
1744         voltage_max = intel_dp_voltage_max(intel_dp);
1745         if (v >= voltage_max)
1746                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1747
1748         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1749         if (p >= preemph_max)
1750                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1751
1752         for (lane = 0; lane < 4; lane++)
1753                 intel_dp->train_set[lane] = v | p;
1754 }
1755
1756 static uint32_t
1757 intel_gen4_signal_levels(uint8_t train_set)
1758 {
1759         uint32_t        signal_levels = 0;
1760
1761         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1762         case DP_TRAIN_VOLTAGE_SWING_400:
1763         default:
1764                 signal_levels |= DP_VOLTAGE_0_4;
1765                 break;
1766         case DP_TRAIN_VOLTAGE_SWING_600:
1767                 signal_levels |= DP_VOLTAGE_0_6;
1768                 break;
1769         case DP_TRAIN_VOLTAGE_SWING_800:
1770                 signal_levels |= DP_VOLTAGE_0_8;
1771                 break;
1772         case DP_TRAIN_VOLTAGE_SWING_1200:
1773                 signal_levels |= DP_VOLTAGE_1_2;
1774                 break;
1775         }
1776         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1777         case DP_TRAIN_PRE_EMPHASIS_0:
1778         default:
1779                 signal_levels |= DP_PRE_EMPHASIS_0;
1780                 break;
1781         case DP_TRAIN_PRE_EMPHASIS_3_5:
1782                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1783                 break;
1784         case DP_TRAIN_PRE_EMPHASIS_6:
1785                 signal_levels |= DP_PRE_EMPHASIS_6;
1786                 break;
1787         case DP_TRAIN_PRE_EMPHASIS_9_5:
1788                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1789                 break;
1790         }
1791         return signal_levels;
1792 }
1793
1794 /* Gen6's DP voltage swing and pre-emphasis control */
1795 static uint32_t
1796 intel_gen6_edp_signal_levels(uint8_t train_set)
1797 {
1798         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1799                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1800         switch (signal_levels) {
1801         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1802         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1803                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1804         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1805                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1806         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1807         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1808                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1809         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1810         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1811                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1812         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1813         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1814                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1815         default:
1816                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1817                               "0x%x\n", signal_levels);
1818                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1819         }
1820 }
1821
1822 /* Gen7's DP voltage swing and pre-emphasis control */
1823 static uint32_t
1824 intel_gen7_edp_signal_levels(uint8_t train_set)
1825 {
1826         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1827                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1828         switch (signal_levels) {
1829         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1830                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1831         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1832                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1833         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1834                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1835
1836         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1837                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1838         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1839                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1840
1841         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1842                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1843         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1844                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1845
1846         default:
1847                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1848                               "0x%x\n", signal_levels);
1849                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1850         }
1851 }
1852
1853 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1854 static uint32_t
1855 intel_hsw_signal_levels(uint8_t train_set)
1856 {
1857         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1858                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1859         switch (signal_levels) {
1860         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1861                 return DDI_BUF_EMP_400MV_0DB_HSW;
1862         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1863                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1864         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1865                 return DDI_BUF_EMP_400MV_6DB_HSW;
1866         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1867                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1868
1869         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1870                 return DDI_BUF_EMP_600MV_0DB_HSW;
1871         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1872                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1873         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1874                 return DDI_BUF_EMP_600MV_6DB_HSW;
1875
1876         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1877                 return DDI_BUF_EMP_800MV_0DB_HSW;
1878         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1879                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1880         default:
1881                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1882                               "0x%x\n", signal_levels);
1883                 return DDI_BUF_EMP_400MV_0DB_HSW;
1884         }
1885 }
1886
1887 /* Properly updates "DP" with the correct signal levels. */
1888 static void
1889 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1890 {
1891         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1892         struct drm_device *dev = intel_dig_port->base.base.dev;
1893         uint32_t signal_levels, mask;
1894         uint8_t train_set = intel_dp->train_set[0];
1895
1896         if (HAS_DDI(dev)) {
1897                 signal_levels = intel_hsw_signal_levels(train_set);
1898                 mask = DDI_BUF_EMP_MASK;
1899         } else if (IS_VALLEYVIEW(dev)) {
1900                 signal_levels = intel_vlv_signal_levels(intel_dp);
1901                 mask = 0;
1902         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1903                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1904                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1905         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1906                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1907                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1908         } else {
1909                 signal_levels = intel_gen4_signal_levels(train_set);
1910                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1911         }
1912
1913         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1914
1915         *DP = (*DP & ~mask) | signal_levels;
1916 }
1917
1918 static bool
1919 intel_dp_set_link_train(struct intel_dp *intel_dp,
1920                         uint32_t dp_reg_value,
1921                         uint8_t dp_train_pat)
1922 {
1923         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1924         struct drm_device *dev = intel_dig_port->base.base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         enum port port = intel_dig_port->port;
1927         int ret;
1928         uint32_t temp;
1929
1930         if (HAS_DDI(dev)) {
1931                 temp = I915_READ(DP_TP_CTL(port));
1932
1933                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1934                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1935                 else
1936                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1937
1938                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1939                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1940                 case DP_TRAINING_PATTERN_DISABLE:
1941
1942                         if (port != PORT_A) {
1943                                 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1944                                 I915_WRITE(DP_TP_CTL(port), temp);
1945
1946                                 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1947                                               DP_TP_STATUS_IDLE_DONE), 1))
1948                                         DRM_ERROR("Timed out waiting for DP idle patterns\n");
1949
1950                                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1951                         }
1952
1953                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1954
1955                         break;
1956                 case DP_TRAINING_PATTERN_1:
1957                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1958                         break;
1959                 case DP_TRAINING_PATTERN_2:
1960                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1961                         break;
1962                 case DP_TRAINING_PATTERN_3:
1963                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1964                         break;
1965                 }
1966                 I915_WRITE(DP_TP_CTL(port), temp);
1967
1968         } else if (HAS_PCH_CPT(dev) &&
1969                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1970                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1971
1972                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1973                 case DP_TRAINING_PATTERN_DISABLE:
1974                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1975                         break;
1976                 case DP_TRAINING_PATTERN_1:
1977                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1978                         break;
1979                 case DP_TRAINING_PATTERN_2:
1980                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1981                         break;
1982                 case DP_TRAINING_PATTERN_3:
1983                         DRM_ERROR("DP training pattern 3 not supported\n");
1984                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1985                         break;
1986                 }
1987
1988         } else {
1989                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1990
1991                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1992                 case DP_TRAINING_PATTERN_DISABLE:
1993                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1994                         break;
1995                 case DP_TRAINING_PATTERN_1:
1996                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1997                         break;
1998                 case DP_TRAINING_PATTERN_2:
1999                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2000                         break;
2001                 case DP_TRAINING_PATTERN_3:
2002                         DRM_ERROR("DP training pattern 3 not supported\n");
2003                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2004                         break;
2005                 }
2006         }
2007
2008         I915_WRITE(intel_dp->output_reg, dp_reg_value);
2009         POSTING_READ(intel_dp->output_reg);
2010
2011         intel_dp_aux_native_write_1(intel_dp,
2012                                     DP_TRAINING_PATTERN_SET,
2013                                     dp_train_pat);
2014
2015         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2016             DP_TRAINING_PATTERN_DISABLE) {
2017                 ret = intel_dp_aux_native_write(intel_dp,
2018                                                 DP_TRAINING_LANE0_SET,
2019                                                 intel_dp->train_set,
2020                                                 intel_dp->lane_count);
2021                 if (ret != intel_dp->lane_count)
2022                         return false;
2023         }
2024
2025         return true;
2026 }
2027
2028 /* Enable corresponding port and start training pattern 1 */
2029 void
2030 intel_dp_start_link_train(struct intel_dp *intel_dp)
2031 {
2032         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2033         struct drm_device *dev = encoder->dev;
2034         int i;
2035         uint8_t voltage;
2036         bool clock_recovery = false;
2037         int voltage_tries, loop_tries;
2038         uint32_t DP = intel_dp->DP;
2039
2040         if (HAS_DDI(dev))
2041                 intel_ddi_prepare_link_retrain(encoder);
2042
2043         /* Write the link configuration data */
2044         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2045                                   intel_dp->link_configuration,
2046                                   DP_LINK_CONFIGURATION_SIZE);
2047
2048         DP |= DP_PORT_EN;
2049
2050         memset(intel_dp->train_set, 0, 4);
2051         voltage = 0xff;
2052         voltage_tries = 0;
2053         loop_tries = 0;
2054         clock_recovery = false;
2055         for (;;) {
2056                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2057                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2058
2059                 intel_dp_set_signal_levels(intel_dp, &DP);
2060
2061                 /* Set training pattern 1 */
2062                 if (!intel_dp_set_link_train(intel_dp, DP,
2063                                              DP_TRAINING_PATTERN_1 |
2064                                              DP_LINK_SCRAMBLING_DISABLE))
2065                         break;
2066
2067                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2068                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2069                         DRM_ERROR("failed to get link status\n");
2070                         break;
2071                 }
2072
2073                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2074                         DRM_DEBUG_KMS("clock recovery OK\n");
2075                         clock_recovery = true;
2076                         break;
2077                 }
2078
2079                 /* Check to see if we've tried the max voltage */
2080                 for (i = 0; i < intel_dp->lane_count; i++)
2081                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2082                                 break;
2083                 if (i == intel_dp->lane_count) {
2084                         ++loop_tries;
2085                         if (loop_tries == 5) {
2086                                 DRM_DEBUG_KMS("too many full retries, give up\n");
2087                                 break;
2088                         }
2089                         memset(intel_dp->train_set, 0, 4);
2090                         voltage_tries = 0;
2091                         continue;
2092                 }
2093
2094                 /* Check to see if we've tried the same voltage 5 times */
2095                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2096                         ++voltage_tries;
2097                         if (voltage_tries == 5) {
2098                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2099                                 break;
2100                         }
2101                 } else
2102                         voltage_tries = 0;
2103                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2104
2105                 /* Compute new intel_dp->train_set as requested by target */
2106                 intel_get_adjust_train(intel_dp, link_status);
2107         }
2108
2109         intel_dp->DP = DP;
2110 }
2111
2112 void
2113 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2114 {
2115         bool channel_eq = false;
2116         int tries, cr_tries;
2117         uint32_t DP = intel_dp->DP;
2118
2119         /* channel equalization */
2120         tries = 0;
2121         cr_tries = 0;
2122         channel_eq = false;
2123         for (;;) {
2124                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2125
2126                 if (cr_tries > 5) {
2127                         DRM_ERROR("failed to train DP, aborting\n");
2128                         intel_dp_link_down(intel_dp);
2129                         break;
2130                 }
2131
2132                 intel_dp_set_signal_levels(intel_dp, &DP);
2133
2134                 /* channel eq pattern */
2135                 if (!intel_dp_set_link_train(intel_dp, DP,
2136                                              DP_TRAINING_PATTERN_2 |
2137                                              DP_LINK_SCRAMBLING_DISABLE))
2138                         break;
2139
2140                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2141                 if (!intel_dp_get_link_status(intel_dp, link_status))
2142                         break;
2143
2144                 /* Make sure clock is still ok */
2145                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2146                         intel_dp_start_link_train(intel_dp);
2147                         cr_tries++;
2148                         continue;
2149                 }
2150
2151                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2152                         channel_eq = true;
2153                         break;
2154                 }
2155
2156                 /* Try 5 times, then try clock recovery if that fails */
2157                 if (tries > 5) {
2158                         intel_dp_link_down(intel_dp);
2159                         intel_dp_start_link_train(intel_dp);
2160                         tries = 0;
2161                         cr_tries++;
2162                         continue;
2163                 }
2164
2165                 /* Compute new intel_dp->train_set as requested by target */
2166                 intel_get_adjust_train(intel_dp, link_status);
2167                 ++tries;
2168         }
2169
2170         if (channel_eq)
2171                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2172
2173         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2174 }
2175
2176 static void
2177 intel_dp_link_down(struct intel_dp *intel_dp)
2178 {
2179         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2180         struct drm_device *dev = intel_dig_port->base.base.dev;
2181         struct drm_i915_private *dev_priv = dev->dev_private;
2182         struct intel_crtc *intel_crtc =
2183                 to_intel_crtc(intel_dig_port->base.base.crtc);
2184         uint32_t DP = intel_dp->DP;
2185
2186         /*
2187          * DDI code has a strict mode set sequence and we should try to respect
2188          * it, otherwise we might hang the machine in many different ways. So we
2189          * really should be disabling the port only on a complete crtc_disable
2190          * sequence. This function is just called under two conditions on DDI
2191          * code:
2192          * - Link train failed while doing crtc_enable, and on this case we
2193          *   really should respect the mode set sequence and wait for a
2194          *   crtc_disable.
2195          * - Someone turned the monitor off and intel_dp_check_link_status
2196          *   called us. We don't need to disable the whole port on this case, so
2197          *   when someone turns the monitor on again,
2198          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2199          *   train.
2200          */
2201         if (HAS_DDI(dev))
2202                 return;
2203
2204         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2205                 return;
2206
2207         DRM_DEBUG_KMS("\n");
2208
2209         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2210                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2211                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2212         } else {
2213                 DP &= ~DP_LINK_TRAIN_MASK;
2214                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2215         }
2216         POSTING_READ(intel_dp->output_reg);
2217
2218         /* We don't really know why we're doing this */
2219         intel_wait_for_vblank(dev, intel_crtc->pipe);
2220
2221         if (HAS_PCH_IBX(dev) &&
2222             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2223                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2224
2225                 /* Hardware workaround: leaving our transcoder select
2226                  * set to transcoder B while it's off will prevent the
2227                  * corresponding HDMI output on transcoder A.
2228                  *
2229                  * Combine this with another hardware workaround:
2230                  * transcoder select bit can only be cleared while the
2231                  * port is enabled.
2232                  */
2233                 DP &= ~DP_PIPEB_SELECT;
2234                 I915_WRITE(intel_dp->output_reg, DP);
2235
2236                 /* Changes to enable or select take place the vblank
2237                  * after being written.
2238                  */
2239                 if (WARN_ON(crtc == NULL)) {
2240                         /* We should never try to disable a port without a crtc
2241                          * attached. For paranoia keep the code around for a
2242                          * bit. */
2243                         POSTING_READ(intel_dp->output_reg);
2244                         msleep(50);
2245                 } else
2246                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2247         }
2248
2249         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2250         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2251         POSTING_READ(intel_dp->output_reg);
2252         msleep(intel_dp->panel_power_down_delay);
2253 }
2254
2255 static bool
2256 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2257 {
2258         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2259
2260         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2261                                            sizeof(intel_dp->dpcd)) == 0)
2262                 return false; /* aux transfer failed */
2263
2264         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2265                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2266         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2267
2268         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2269                 return false; /* DPCD not present */
2270
2271         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2272               DP_DWN_STRM_PORT_PRESENT))
2273                 return true; /* native DP sink */
2274
2275         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2276                 return true; /* no per-port downstream info */
2277
2278         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2279                                            intel_dp->downstream_ports,
2280                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2281                 return false; /* downstream port status fetch failed */
2282
2283         return true;
2284 }
2285
2286 static void
2287 intel_dp_probe_oui(struct intel_dp *intel_dp)
2288 {
2289         u8 buf[3];
2290
2291         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2292                 return;
2293
2294         ironlake_edp_panel_vdd_on(intel_dp);
2295
2296         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2297                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2298                               buf[0], buf[1], buf[2]);
2299
2300         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2301                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2302                               buf[0], buf[1], buf[2]);
2303
2304         ironlake_edp_panel_vdd_off(intel_dp, false);
2305 }
2306
2307 static bool
2308 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2309 {
2310         int ret;
2311
2312         ret = intel_dp_aux_native_read_retry(intel_dp,
2313                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2314                                              sink_irq_vector, 1);
2315         if (!ret)
2316                 return false;
2317
2318         return true;
2319 }
2320
2321 static void
2322 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2323 {
2324         /* NAK by default */
2325         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2326 }
2327
2328 /*
2329  * According to DP spec
2330  * 5.1.2:
2331  *  1. Read DPCD
2332  *  2. Configure link according to Receiver Capabilities
2333  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2334  *  4. Check link status on receipt of hot-plug interrupt
2335  */
2336
2337 void
2338 intel_dp_check_link_status(struct intel_dp *intel_dp)
2339 {
2340         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2341         u8 sink_irq_vector;
2342         u8 link_status[DP_LINK_STATUS_SIZE];
2343
2344         if (!intel_encoder->connectors_active)
2345                 return;
2346
2347         if (WARN_ON(!intel_encoder->base.crtc))
2348                 return;
2349
2350         /* Try to read receiver status if the link appears to be up */
2351         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2352                 intel_dp_link_down(intel_dp);
2353                 return;
2354         }
2355
2356         /* Now read the DPCD to see if it's actually running */
2357         if (!intel_dp_get_dpcd(intel_dp)) {
2358                 intel_dp_link_down(intel_dp);
2359                 return;
2360         }
2361
2362         /* Try to read the source of the interrupt */
2363         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2364             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2365                 /* Clear interrupt source */
2366                 intel_dp_aux_native_write_1(intel_dp,
2367                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2368                                             sink_irq_vector);
2369
2370                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2371                         intel_dp_handle_test_request(intel_dp);
2372                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2373                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2374         }
2375
2376         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2377                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2378                               drm_get_encoder_name(&intel_encoder->base));
2379                 intel_dp_start_link_train(intel_dp);
2380                 intel_dp_complete_link_train(intel_dp);
2381         }
2382 }
2383
2384 /* XXX this is probably wrong for multiple downstream ports */
2385 static enum drm_connector_status
2386 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2387 {
2388         uint8_t *dpcd = intel_dp->dpcd;
2389         bool hpd;
2390         uint8_t type;
2391
2392         if (!intel_dp_get_dpcd(intel_dp))
2393                 return connector_status_disconnected;
2394
2395         /* if there's no downstream port, we're done */
2396         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2397                 return connector_status_connected;
2398
2399         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2400         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2401         if (hpd) {
2402                 uint8_t reg;
2403                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2404                                                     &reg, 1))
2405                         return connector_status_unknown;
2406                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2407                                               : connector_status_disconnected;
2408         }
2409
2410         /* If no HPD, poke DDC gently */
2411         if (drm_probe_ddc(&intel_dp->adapter))
2412                 return connector_status_connected;
2413
2414         /* Well we tried, say unknown for unreliable port types */
2415         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2416         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2417                 return connector_status_unknown;
2418
2419         /* Anything else is out of spec, warn and ignore */
2420         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2421         return connector_status_disconnected;
2422 }
2423
2424 static enum drm_connector_status
2425 ironlake_dp_detect(struct intel_dp *intel_dp)
2426 {
2427         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2428         struct drm_i915_private *dev_priv = dev->dev_private;
2429         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2430         enum drm_connector_status status;
2431
2432         /* Can't disconnect eDP, but you can close the lid... */
2433         if (is_edp(intel_dp)) {
2434                 status = intel_panel_detect(dev);
2435                 if (status == connector_status_unknown)
2436                         status = connector_status_connected;
2437                 return status;
2438         }
2439
2440         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2441                 return connector_status_disconnected;
2442
2443         return intel_dp_detect_dpcd(intel_dp);
2444 }
2445
2446 static enum drm_connector_status
2447 g4x_dp_detect(struct intel_dp *intel_dp)
2448 {
2449         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2450         struct drm_i915_private *dev_priv = dev->dev_private;
2451         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2452         uint32_t bit;
2453
2454         /* Can't disconnect eDP, but you can close the lid... */
2455         if (is_edp(intel_dp)) {
2456                 enum drm_connector_status status;
2457
2458                 status = intel_panel_detect(dev);
2459                 if (status == connector_status_unknown)
2460                         status = connector_status_connected;
2461                 return status;
2462         }
2463
2464         switch (intel_dig_port->port) {
2465         case PORT_B:
2466                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2467                 break;
2468         case PORT_C:
2469                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2470                 break;
2471         case PORT_D:
2472                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2473                 break;
2474         default:
2475                 return connector_status_unknown;
2476         }
2477
2478         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2479                 return connector_status_disconnected;
2480
2481         return intel_dp_detect_dpcd(intel_dp);
2482 }
2483
2484 static struct edid *
2485 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2486 {
2487         struct intel_connector *intel_connector = to_intel_connector(connector);
2488
2489         /* use cached edid if we have one */
2490         if (intel_connector->edid) {
2491                 struct edid *edid;
2492                 int size;
2493
2494                 /* invalid edid */
2495                 if (IS_ERR(intel_connector->edid))
2496                         return NULL;
2497
2498                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2499                 edid = kmalloc(size, GFP_KERNEL);
2500                 if (!edid)
2501                         return NULL;
2502
2503                 memcpy(edid, intel_connector->edid, size);
2504                 return edid;
2505         }
2506
2507         return drm_get_edid(connector, adapter);
2508 }
2509
2510 static int
2511 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2512 {
2513         struct intel_connector *intel_connector = to_intel_connector(connector);
2514
2515         /* use cached edid if we have one */
2516         if (intel_connector->edid) {
2517                 /* invalid edid */
2518                 if (IS_ERR(intel_connector->edid))
2519                         return 0;
2520
2521                 return intel_connector_update_modes(connector,
2522                                                     intel_connector->edid);
2523         }
2524
2525         return intel_ddc_get_modes(connector, adapter);
2526 }
2527
2528 static enum drm_connector_status
2529 intel_dp_detect(struct drm_connector *connector, bool force)
2530 {
2531         struct intel_dp *intel_dp = intel_attached_dp(connector);
2532         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2533         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2534         struct drm_device *dev = connector->dev;
2535         enum drm_connector_status status;
2536         struct edid *edid = NULL;
2537
2538         intel_dp->has_audio = false;
2539
2540         if (HAS_PCH_SPLIT(dev))
2541                 status = ironlake_dp_detect(intel_dp);
2542         else
2543                 status = g4x_dp_detect(intel_dp);
2544
2545         if (status != connector_status_connected)
2546                 return status;
2547
2548         intel_dp_probe_oui(intel_dp);
2549
2550         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2551                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2552         } else {
2553                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2554                 if (edid) {
2555                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2556                         kfree(edid);
2557                 }
2558         }
2559
2560         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2561                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2562         return connector_status_connected;
2563 }
2564
2565 static int intel_dp_get_modes(struct drm_connector *connector)
2566 {
2567         struct intel_dp *intel_dp = intel_attached_dp(connector);
2568         struct intel_connector *intel_connector = to_intel_connector(connector);
2569         struct drm_device *dev = connector->dev;
2570         int ret;
2571
2572         /* We should parse the EDID data and find out if it has an audio sink
2573          */
2574
2575         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2576         if (ret)
2577                 return ret;
2578
2579         /* if eDP has no EDID, fall back to fixed mode */
2580         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2581                 struct drm_display_mode *mode;
2582                 mode = drm_mode_duplicate(dev,
2583                                           intel_connector->panel.fixed_mode);
2584                 if (mode) {
2585                         drm_mode_probed_add(connector, mode);
2586                         return 1;
2587                 }
2588         }
2589         return 0;
2590 }
2591
2592 static bool
2593 intel_dp_detect_audio(struct drm_connector *connector)
2594 {
2595         struct intel_dp *intel_dp = intel_attached_dp(connector);
2596         struct edid *edid;
2597         bool has_audio = false;
2598
2599         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2600         if (edid) {
2601                 has_audio = drm_detect_monitor_audio(edid);
2602                 kfree(edid);
2603         }
2604
2605         return has_audio;
2606 }
2607
2608 static int
2609 intel_dp_set_property(struct drm_connector *connector,
2610                       struct drm_property *property,
2611                       uint64_t val)
2612 {
2613         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2614         struct intel_connector *intel_connector = to_intel_connector(connector);
2615         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2616         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2617         int ret;
2618
2619         ret = drm_object_property_set_value(&connector->base, property, val);
2620         if (ret)
2621                 return ret;
2622
2623         if (property == dev_priv->force_audio_property) {
2624                 int i = val;
2625                 bool has_audio;
2626
2627                 if (i == intel_dp->force_audio)
2628                         return 0;
2629
2630                 intel_dp->force_audio = i;
2631
2632                 if (i == HDMI_AUDIO_AUTO)
2633                         has_audio = intel_dp_detect_audio(connector);
2634                 else
2635                         has_audio = (i == HDMI_AUDIO_ON);
2636
2637                 if (has_audio == intel_dp->has_audio)
2638                         return 0;
2639
2640                 intel_dp->has_audio = has_audio;
2641                 goto done;
2642         }
2643
2644         if (property == dev_priv->broadcast_rgb_property) {
2645                 switch (val) {
2646                 case INTEL_BROADCAST_RGB_AUTO:
2647                         intel_dp->color_range_auto = true;
2648                         break;
2649                 case INTEL_BROADCAST_RGB_FULL:
2650                         intel_dp->color_range_auto = false;
2651                         intel_dp->color_range = 0;
2652                         break;
2653                 case INTEL_BROADCAST_RGB_LIMITED:
2654                         intel_dp->color_range_auto = false;
2655                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2656                         break;
2657                 default:
2658                         return -EINVAL;
2659                 }
2660                 goto done;
2661         }
2662
2663         if (is_edp(intel_dp) &&
2664             property == connector->dev->mode_config.scaling_mode_property) {
2665                 if (val == DRM_MODE_SCALE_NONE) {
2666                         DRM_DEBUG_KMS("no scaling not supported\n");
2667                         return -EINVAL;
2668                 }
2669
2670                 if (intel_connector->panel.fitting_mode == val) {
2671                         /* the eDP scaling property is not changed */
2672                         return 0;
2673                 }
2674                 intel_connector->panel.fitting_mode = val;
2675
2676                 goto done;
2677         }
2678
2679         return -EINVAL;
2680
2681 done:
2682         if (intel_encoder->base.crtc)
2683                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2684
2685         return 0;
2686 }
2687
2688 static void
2689 intel_dp_destroy(struct drm_connector *connector)
2690 {
2691         struct intel_dp *intel_dp = intel_attached_dp(connector);
2692         struct intel_connector *intel_connector = to_intel_connector(connector);
2693
2694         if (!IS_ERR_OR_NULL(intel_connector->edid))
2695                 kfree(intel_connector->edid);
2696
2697         if (is_edp(intel_dp))
2698                 intel_panel_fini(&intel_connector->panel);
2699
2700         drm_sysfs_connector_remove(connector);
2701         drm_connector_cleanup(connector);
2702         kfree(connector);
2703 }
2704
2705 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2706 {
2707         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2708         struct intel_dp *intel_dp = &intel_dig_port->dp;
2709
2710         i2c_del_adapter(&intel_dp->adapter);
2711         drm_encoder_cleanup(encoder);
2712         if (is_edp(intel_dp)) {
2713                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2714                 ironlake_panel_vdd_off_sync(intel_dp);
2715         }
2716         kfree(intel_dig_port);
2717 }
2718
2719 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2720         .mode_set = intel_dp_mode_set,
2721 };
2722
2723 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2724         .dpms = intel_connector_dpms,
2725         .detect = intel_dp_detect,
2726         .fill_modes = drm_helper_probe_single_connector_modes,
2727         .set_property = intel_dp_set_property,
2728         .destroy = intel_dp_destroy,
2729 };
2730
2731 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2732         .get_modes = intel_dp_get_modes,
2733         .mode_valid = intel_dp_mode_valid,
2734         .best_encoder = intel_best_encoder,
2735 };
2736
2737 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2738         .destroy = intel_dp_encoder_destroy,
2739 };
2740
2741 static void
2742 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2743 {
2744         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2745
2746         intel_dp_check_link_status(intel_dp);
2747 }
2748
2749 /* Return which DP Port should be selected for Transcoder DP control */
2750 int
2751 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct intel_encoder *intel_encoder;
2755         struct intel_dp *intel_dp;
2756
2757         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2758                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2759
2760                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2761                     intel_encoder->type == INTEL_OUTPUT_EDP)
2762                         return intel_dp->output_reg;
2763         }
2764
2765         return -1;
2766 }
2767
2768 /* check the VBT to see whether the eDP is on DP-D port */
2769 bool intel_dpd_is_edp(struct drm_device *dev)
2770 {
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         struct child_device_config *p_child;
2773         int i;
2774
2775         if (!dev_priv->child_dev_num)
2776                 return false;
2777
2778         for (i = 0; i < dev_priv->child_dev_num; i++) {
2779                 p_child = dev_priv->child_dev + i;
2780
2781                 if (p_child->dvo_port == PORT_IDPD &&
2782                     p_child->device_type == DEVICE_TYPE_eDP)
2783                         return true;
2784         }
2785         return false;
2786 }
2787
2788 static void
2789 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2790 {
2791         struct intel_connector *intel_connector = to_intel_connector(connector);
2792
2793         intel_attach_force_audio_property(connector);
2794         intel_attach_broadcast_rgb_property(connector);
2795         intel_dp->color_range_auto = true;
2796
2797         if (is_edp(intel_dp)) {
2798                 drm_mode_create_scaling_mode_property(connector->dev);
2799                 drm_object_attach_property(
2800                         &connector->base,
2801                         connector->dev->mode_config.scaling_mode_property,
2802                         DRM_MODE_SCALE_ASPECT);
2803                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2804         }
2805 }
2806
2807 static void
2808 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2809                                     struct intel_dp *intel_dp,
2810                                     struct edp_power_seq *out)
2811 {
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813         struct edp_power_seq cur, vbt, spec, final;
2814         u32 pp_on, pp_off, pp_div, pp;
2815         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2816
2817         if (HAS_PCH_SPLIT(dev)) {
2818                 pp_control_reg = PCH_PP_CONTROL;
2819                 pp_on_reg = PCH_PP_ON_DELAYS;
2820                 pp_off_reg = PCH_PP_OFF_DELAYS;
2821                 pp_div_reg = PCH_PP_DIVISOR;
2822         } else {
2823                 pp_control_reg = PIPEA_PP_CONTROL;
2824                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2825                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2826                 pp_div_reg = PIPEA_PP_DIVISOR;
2827         }
2828
2829         /* Workaround: Need to write PP_CONTROL with the unlock key as
2830          * the very first thing. */
2831         pp = ironlake_get_pp_control(intel_dp);
2832         I915_WRITE(pp_control_reg, pp);
2833
2834         pp_on = I915_READ(pp_on_reg);
2835         pp_off = I915_READ(pp_off_reg);
2836         pp_div = I915_READ(pp_div_reg);
2837
2838         /* Pull timing values out of registers */
2839         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2840                 PANEL_POWER_UP_DELAY_SHIFT;
2841
2842         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2843                 PANEL_LIGHT_ON_DELAY_SHIFT;
2844
2845         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2846                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2847
2848         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2849                 PANEL_POWER_DOWN_DELAY_SHIFT;
2850
2851         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2852                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2853
2854         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2855                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2856
2857         vbt = dev_priv->edp.pps;
2858
2859         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2860          * our hw here, which are all in 100usec. */
2861         spec.t1_t3 = 210 * 10;
2862         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2863         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2864         spec.t10 = 500 * 10;
2865         /* This one is special and actually in units of 100ms, but zero
2866          * based in the hw (so we need to add 100 ms). But the sw vbt
2867          * table multiplies it with 1000 to make it in units of 100usec,
2868          * too. */
2869         spec.t11_t12 = (510 + 100) * 10;
2870
2871         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2872                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2873
2874         /* Use the max of the register settings and vbt. If both are
2875          * unset, fall back to the spec limits. */
2876 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2877                                        spec.field : \
2878                                        max(cur.field, vbt.field))
2879         assign_final(t1_t3);
2880         assign_final(t8);
2881         assign_final(t9);
2882         assign_final(t10);
2883         assign_final(t11_t12);
2884 #undef assign_final
2885
2886 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2887         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2888         intel_dp->backlight_on_delay = get_delay(t8);
2889         intel_dp->backlight_off_delay = get_delay(t9);
2890         intel_dp->panel_power_down_delay = get_delay(t10);
2891         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2892 #undef get_delay
2893
2894         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2895                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2896                       intel_dp->panel_power_cycle_delay);
2897
2898         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2899                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2900
2901         if (out)
2902                 *out = final;
2903 }
2904
2905 static void
2906 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2907                                               struct intel_dp *intel_dp,
2908                                               struct edp_power_seq *seq)
2909 {
2910         struct drm_i915_private *dev_priv = dev->dev_private;
2911         u32 pp_on, pp_off, pp_div, port_sel = 0;
2912         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2913         int pp_on_reg, pp_off_reg, pp_div_reg;
2914
2915         if (HAS_PCH_SPLIT(dev)) {
2916                 pp_on_reg = PCH_PP_ON_DELAYS;
2917                 pp_off_reg = PCH_PP_OFF_DELAYS;
2918                 pp_div_reg = PCH_PP_DIVISOR;
2919         } else {
2920                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2921                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2922                 pp_div_reg = PIPEA_PP_DIVISOR;
2923         }
2924
2925         if (IS_VALLEYVIEW(dev))
2926                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2927
2928         /* And finally store the new values in the power sequencer. */
2929         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2930                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2931         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2932                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2933         /* Compute the divisor for the pp clock, simply match the Bspec
2934          * formula. */
2935         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2936         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2937                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2938
2939         /* Haswell doesn't have any port selection bits for the panel
2940          * power sequencer any more. */
2941         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2942                 if (is_cpu_edp(intel_dp))
2943                         port_sel = PANEL_POWER_PORT_DP_A;
2944                 else
2945                         port_sel = PANEL_POWER_PORT_DP_D;
2946         }
2947
2948         pp_on |= port_sel;
2949
2950         I915_WRITE(pp_on_reg, pp_on);
2951         I915_WRITE(pp_off_reg, pp_off);
2952         I915_WRITE(pp_div_reg, pp_div);
2953
2954         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2955                       I915_READ(pp_on_reg),
2956                       I915_READ(pp_off_reg),
2957                       I915_READ(pp_div_reg));
2958 }
2959
2960 void
2961 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2962                         struct intel_connector *intel_connector)
2963 {
2964         struct drm_connector *connector = &intel_connector->base;
2965         struct intel_dp *intel_dp = &intel_dig_port->dp;
2966         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2967         struct drm_device *dev = intel_encoder->base.dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         struct drm_display_mode *fixed_mode = NULL;
2970         struct edp_power_seq power_seq = { 0 };
2971         enum port port = intel_dig_port->port;
2972         const char *name = NULL;
2973         int type;
2974
2975         /* Preserve the current hw state. */
2976         intel_dp->DP = I915_READ(intel_dp->output_reg);
2977         intel_dp->attached_connector = intel_connector;
2978
2979         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2980                 if (intel_dpd_is_edp(dev))
2981                         intel_dp->is_pch_edp = true;
2982
2983         type = DRM_MODE_CONNECTOR_DisplayPort;
2984         /*
2985          * FIXME : We need to initialize built-in panels before external panels.
2986          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2987          */
2988         switch (port) {
2989         case PORT_A:
2990                 type = DRM_MODE_CONNECTOR_eDP;
2991                 break;
2992         case PORT_C:
2993                 if (IS_VALLEYVIEW(dev))
2994                         type = DRM_MODE_CONNECTOR_eDP;
2995                 break;
2996         case PORT_D:
2997                 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
2998                         type = DRM_MODE_CONNECTOR_eDP;
2999                 break;
3000         default:        /* silence GCC warning */
3001                 break;
3002         }
3003
3004         /*
3005          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3006          * for DP the encoder type can be set by the caller to
3007          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3008          */
3009         if (type == DRM_MODE_CONNECTOR_eDP)
3010                 intel_encoder->type = INTEL_OUTPUT_EDP;
3011
3012         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3013         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3014
3015         connector->interlace_allowed = true;
3016         connector->doublescan_allowed = 0;
3017
3018         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3019                           ironlake_panel_vdd_work);
3020
3021         intel_connector_attach_encoder(intel_connector, intel_encoder);
3022         drm_sysfs_connector_add(connector);
3023
3024         if (HAS_DDI(dev))
3025                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3026         else
3027                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3028
3029         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3030         if (HAS_DDI(dev)) {
3031                 switch (intel_dig_port->port) {
3032                 case PORT_A:
3033                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3034                         break;
3035                 case PORT_B:
3036                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3037                         break;
3038                 case PORT_C:
3039                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3040                         break;
3041                 case PORT_D:
3042                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3043                         break;
3044                 default:
3045                         BUG();
3046                 }
3047         }
3048
3049         /* Set up the DDC bus. */
3050         switch (port) {
3051         case PORT_A:
3052                 intel_encoder->hpd_pin = HPD_PORT_A;
3053                 name = "DPDDC-A";
3054                 break;
3055         case PORT_B:
3056                 intel_encoder->hpd_pin = HPD_PORT_B;
3057                 name = "DPDDC-B";
3058                 break;
3059         case PORT_C:
3060                 intel_encoder->hpd_pin = HPD_PORT_C;
3061                 name = "DPDDC-C";
3062                 break;
3063         case PORT_D:
3064                 intel_encoder->hpd_pin = HPD_PORT_D;
3065                 name = "DPDDC-D";
3066                 break;
3067         default:
3068                 BUG();
3069         }
3070
3071         if (is_edp(intel_dp))
3072                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3073
3074         intel_dp_i2c_init(intel_dp, intel_connector, name);
3075
3076         /* Cache DPCD and EDID for edp. */
3077         if (is_edp(intel_dp)) {
3078                 bool ret;
3079                 struct drm_display_mode *scan;
3080                 struct edid *edid;
3081
3082                 ironlake_edp_panel_vdd_on(intel_dp);
3083                 ret = intel_dp_get_dpcd(intel_dp);
3084                 ironlake_edp_panel_vdd_off(intel_dp, false);
3085
3086                 if (ret) {
3087                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3088                                 dev_priv->no_aux_handshake =
3089                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3090                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3091                 } else {
3092                         /* if this fails, presume the device is a ghost */
3093                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
3094                         intel_dp_encoder_destroy(&intel_encoder->base);
3095                         intel_dp_destroy(connector);
3096                         return;
3097                 }
3098
3099                 /* We now know it's not a ghost, init power sequence regs. */
3100                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3101                                                               &power_seq);
3102
3103                 ironlake_edp_panel_vdd_on(intel_dp);
3104                 edid = drm_get_edid(connector, &intel_dp->adapter);
3105                 if (edid) {
3106                         if (drm_add_edid_modes(connector, edid)) {
3107                                 drm_mode_connector_update_edid_property(connector, edid);
3108                                 drm_edid_to_eld(connector, edid);
3109                         } else {
3110                                 kfree(edid);
3111                                 edid = ERR_PTR(-EINVAL);
3112                         }
3113                 } else {
3114                         edid = ERR_PTR(-ENOENT);
3115                 }
3116                 intel_connector->edid = edid;
3117
3118                 /* prefer fixed mode from EDID if available */
3119                 list_for_each_entry(scan, &connector->probed_modes, head) {
3120                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3121                                 fixed_mode = drm_mode_duplicate(dev, scan);
3122                                 break;
3123                         }
3124                 }
3125
3126                 /* fallback to VBT if available for eDP */
3127                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3128                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3129                         if (fixed_mode)
3130                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3131                 }
3132
3133                 ironlake_edp_panel_vdd_off(intel_dp, false);
3134         }
3135
3136         if (is_edp(intel_dp)) {
3137                 intel_panel_init(&intel_connector->panel, fixed_mode);
3138                 intel_panel_setup_backlight(connector);
3139         }
3140
3141         intel_dp_add_properties(intel_dp, connector);
3142
3143         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3144          * 0xd.  Failure to do so will result in spurious interrupts being
3145          * generated on the port when a cable is not attached.
3146          */
3147         if (IS_G4X(dev) && !IS_GM45(dev)) {
3148                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3149                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3150         }
3151 }
3152
3153 void
3154 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3155 {
3156         struct intel_digital_port *intel_dig_port;
3157         struct intel_encoder *intel_encoder;
3158         struct drm_encoder *encoder;
3159         struct intel_connector *intel_connector;
3160
3161         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3162         if (!intel_dig_port)
3163                 return;
3164
3165         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3166         if (!intel_connector) {
3167                 kfree(intel_dig_port);
3168                 return;
3169         }
3170
3171         intel_encoder = &intel_dig_port->base;
3172         encoder = &intel_encoder->base;
3173
3174         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3175                          DRM_MODE_ENCODER_TMDS);
3176         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3177
3178         intel_encoder->compute_config = intel_dp_compute_config;
3179         intel_encoder->enable = intel_enable_dp;
3180         intel_encoder->pre_enable = intel_pre_enable_dp;
3181         intel_encoder->disable = intel_disable_dp;
3182         intel_encoder->post_disable = intel_post_disable_dp;
3183         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3184         if (IS_VALLEYVIEW(dev))
3185                 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3186
3187         intel_dig_port->port = port;
3188         intel_dig_port->dp.output_reg = output_reg;
3189
3190         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3191         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3192         intel_encoder->cloneable = false;
3193         intel_encoder->hot_plug = intel_dp_hot_plug;
3194
3195         intel_dp_init_connector(intel_dig_port, intel_connector);
3196 }