drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll g4x_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 111 {
 112         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 113 }
 114
 115 static void intel_dp_link_down(struct intel_encoder *encoder,
 116                                const struct intel_crtc_state *old_crtc_state);
 117 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 118 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 119 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 120                                            const struct intel_crtc_state *crtc_state);
 121 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 122                                       enum pipe pipe);
 123 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 124
 125 /* update sink rates from dpcd */
 126 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 127 {
 128         static const int dp_rates[] = {
 129                 162000, 270000, 540000, 810000
 130         };
 131         int i, max_rate;
 132
 133         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 134
 135         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 136                 if (dp_rates[i] > max_rate)
 137                         break;
 138                 intel_dp->sink_rates[i] = dp_rates[i];
 139         }
 140
 141         intel_dp->num_sink_rates = i;
 142 }
 143
 144 /* Get length of rates array potentially limited by max_rate. */
 145 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 146 {
 147         int i;
 148
 149         /* Limit results by potentially reduced max rate */
 150         for (i = 0; i < len; i++) {
 151                 if (rates[len - i - 1] <= max_rate)
 152                         return len - i;
 153         }
 154
 155         return 0;
 156 }
 157
 158 /* Get length of common rates array potentially limited by max_rate. */
 159 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 160                                           int max_rate)
 161 {
 162         return intel_dp_rate_limit_len(intel_dp->common_rates,
 163                                        intel_dp->num_common_rates, max_rate);
 164 }
 165
 166 /* Theoretical max between source and sink */
 167 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 168 {
 169         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 170 }
 171
 172 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 176         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 177         u32 lane_info;
 178
 179         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 180                 return 4;
 181
 182         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 183                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 184                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 185
 186         switch (lane_info) {
 187         default:
 188                 MISSING_CASE(lane_info);
 189         case 1:
 190         case 2:
 191         case 4:
 192         case 8:
 193                 return 1;
 194         case 3:
 195         case 12:
 196                 return 2;
 197         case 15:
 198                 return 4;
 199         }
 200 }
 201
 202 /* Theoretical max between source and sink */
 203 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 204 {
 205         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 206         int source_max = intel_dig_port->max_lanes;
 207         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 208         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 209
 210         return min3(source_max, sink_max, fia_max);
 211 }
 212
 213 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->max_link_lane_count;
 216 }
 217
 218 int
 219 intel_dp_link_required(int pixel_clock, int bpp)
 220 {
 221         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 222         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 223 }
 224
 225 void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
 226 {
 227         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 228         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 229         enum port port = intel_dig_port->base.port;
 230         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 231         u32 ln0, ln1, lane_info;
 232
 233         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
 234                 return;
 235
 236         ln0 = I915_READ(MG_DP_MODE(port, 0));
 237         ln1 = I915_READ(MG_DP_MODE(port, 1));
 238
 239         switch (intel_dig_port->tc_type) {
 240         case TC_PORT_TYPEC:
 241                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 242                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 243
 244                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 245                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 246                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 247
 248                 switch (lane_info) {
 249                 case 0x1:
 250                 case 0x4:
 251                         break;
 252                 case 0x2:
 253                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
 254                         break;
 255                 case 0x3:
 256                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 257                                MG_DP_MODE_CFG_DP_X2_MODE;
 258                         break;
 259                 case 0x8:
 260                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
 261                         break;
 262                 case 0xC:
 263                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 264                                MG_DP_MODE_CFG_DP_X2_MODE;
 265                         break;
 266                 case 0xF:
 267                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 268                                MG_DP_MODE_CFG_DP_X2_MODE;
 269                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 270                                MG_DP_MODE_CFG_DP_X2_MODE;
 271                         break;
 272                 default:
 273                         MISSING_CASE(lane_info);
 274                 }
 275                 break;
 276
 277         case TC_PORT_LEGACY:
 278                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 279                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 280                 break;
 281
 282         default:
 283                 MISSING_CASE(intel_dig_port->tc_type);
 284                 return;
 285         }
 286
 287         I915_WRITE(MG_DP_MODE(port, 0), ln0);
 288         I915_WRITE(MG_DP_MODE(port, 1), ln1);
 289 }
 290
 291 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
 292 {
 293         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 294         enum port port = dig_port->base.port;
 295         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 296         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 297         u32 val;
 298         int i;
 299
 300         if (tc_port == PORT_TC_NONE)
 301                 return;
 302
 303         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 304                 val = I915_READ(mg_regs[i]);
 305                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
 306                        MG_DP_MODE_CFG_TRPWR_GATING |
 307                        MG_DP_MODE_CFG_CLNPWR_GATING |
 308                        MG_DP_MODE_CFG_DIGPWR_GATING |
 309                        MG_DP_MODE_CFG_GAONPWR_GATING;
 310                 I915_WRITE(mg_regs[i], val);
 311         }
 312
 313         val = I915_READ(MG_MISC_SUS0(tc_port));
 314         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
 315                MG_MISC_SUS0_CFG_TR2PWR_GATING |
 316                MG_MISC_SUS0_CFG_CL2PWR_GATING |
 317                MG_MISC_SUS0_CFG_GAONPWR_GATING |
 318                MG_MISC_SUS0_CFG_TRPWR_GATING |
 319                MG_MISC_SUS0_CFG_CL1PWR_GATING |
 320                MG_MISC_SUS0_CFG_DGPWR_GATING;
 321         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 322 }
 323
 324 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
 325 {
 326         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 327         enum port port = dig_port->base.port;
 328         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 329         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 330         u32 val;
 331         int i;
 332
 333         if (tc_port == PORT_TC_NONE)
 334                 return;
 335
 336         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 337                 val = I915_READ(mg_regs[i]);
 338                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
 339                          MG_DP_MODE_CFG_TRPWR_GATING |
 340                          MG_DP_MODE_CFG_CLNPWR_GATING |
 341                          MG_DP_MODE_CFG_DIGPWR_GATING |
 342                          MG_DP_MODE_CFG_GAONPWR_GATING);
 343                 I915_WRITE(mg_regs[i], val);
 344         }
 345
 346         val = I915_READ(MG_MISC_SUS0(tc_port));
 347         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
 348                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
 349                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
 350                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
 351                  MG_MISC_SUS0_CFG_TRPWR_GATING |
 352                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
 353                  MG_MISC_SUS0_CFG_DGPWR_GATING);
 354         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 355 }
 356
 357 int
 358 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 359 {
 360         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 361          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 362          * is transmitted every LS_Clk per lane, there is no need to account for
 363          * the channel encoding that is done in the PHY layer here.
 364          */
 365
 366         return max_link_clock * max_lanes;
 367 }
 368
 369 static int
 370 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 371 {
 372         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 373         struct intel_encoder *encoder = &intel_dig_port->base;
 374         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 375         int max_dotclk = dev_priv->max_dotclk_freq;
 376         int ds_max_dotclk;
 377
 378         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 379
 380         if (type != DP_DS_PORT_TYPE_VGA)
 381                 return max_dotclk;
 382
 383         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 384                                                     intel_dp->downstream_ports);
 385
 386         if (ds_max_dotclk != 0)
 387                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 388
 389         return max_dotclk;
 390 }
 391
 392 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 393 {
 394         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 395         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 396         enum port port = dig_port->base.port;
 397
 398         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 399
 400         /* Low voltage SKUs are limited to max of 5.4G */
 401         if (voltage == VOLTAGE_INFO_0_85V)
 402                 return 540000;
 403
 404         /* For this SKU 8.1G is supported in all ports */
 405         if (IS_CNL_WITH_PORT_F(dev_priv))
 406                 return 810000;
 407
 408         /* For other SKUs, max rate on ports A and D is 5.4G */
 409         if (port == PORT_A || port == PORT_D)
 410                 return 540000;
 411
 412         return 810000;
 413 }
 414
 415 static int icl_max_source_rate(struct intel_dp *intel_dp)
 416 {
 417         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 418         enum port port = dig_port->base.port;
 419
 420         if (port == PORT_B)
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static void
 427 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 428 {
 429         /* The values must be in increasing order */
 430         static const int cnl_rates[] = {
 431                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 432         };
 433         static const int bxt_rates[] = {
 434                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 435         };
 436         static const int skl_rates[] = {
 437                 162000, 216000, 270000, 324000, 432000, 540000
 438         };
 439         static const int hsw_rates[] = {
 440                 162000, 270000, 540000
 441         };
 442         static const int g4x_rates[] = {
 443                 162000, 270000
 444         };
 445         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 446         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 447         const struct ddi_vbt_port_info *info =
 448                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 449         const int *source_rates;
 450         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 451
 452         /* This should only be done once */
 453         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 454
 455         if (INTEL_GEN(dev_priv) >= 10) {
 456                 source_rates = cnl_rates;
 457                 size = ARRAY_SIZE(cnl_rates);
 458                 if (INTEL_GEN(dev_priv) == 10)
 459                         max_rate = cnl_max_source_rate(intel_dp);
 460                 else
 461                         max_rate = icl_max_source_rate(intel_dp);
 462         } else if (IS_GEN9_LP(dev_priv)) {
 463                 source_rates = bxt_rates;
 464                 size = ARRAY_SIZE(bxt_rates);
 465         } else if (IS_GEN9_BC(dev_priv)) {
 466                 source_rates = skl_rates;
 467                 size = ARRAY_SIZE(skl_rates);
 468         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 469                    IS_BROADWELL(dev_priv)) {
 470                 source_rates = hsw_rates;
 471                 size = ARRAY_SIZE(hsw_rates);
 472         } else {
 473                 source_rates = g4x_rates;
 474                 size = ARRAY_SIZE(g4x_rates);
 475         }
 476
 477         if (max_rate && vbt_max_rate)
 478                 max_rate = min(max_rate, vbt_max_rate);
 479         else if (vbt_max_rate)
 480                 max_rate = vbt_max_rate;
 481
 482         if (max_rate)
 483                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 484
 485         intel_dp->source_rates = source_rates;
 486         intel_dp->num_source_rates = size;
 487 }
 488
 489 static int intersect_rates(const int *source_rates, int source_len,
 490                            const int *sink_rates, int sink_len,
 491                            int *common_rates)
 492 {
 493         int i = 0, j = 0, k = 0;
 494
 495         while (i < source_len && j < sink_len) {
 496                 if (source_rates[i] == sink_rates[j]) {
 497                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 498                                 return k;
 499                         common_rates[k] = source_rates[i];
 500                         ++k;
 501                         ++i;
 502                         ++j;
 503                 } else if (source_rates[i] < sink_rates[j]) {
 504                         ++i;
 505                 } else {
 506                         ++j;
 507                 }
 508         }
 509         return k;
 510 }
 511
 512 /* return index of rate in rates array, or -1 if not found */
 513 static int intel_dp_rate_index(const int *rates, int len, int rate)
 514 {
 515         int i;
 516
 517         for (i = 0; i < len; i++)
 518                 if (rate == rates[i])
 519                         return i;
 520
 521         return -1;
 522 }
 523
 524 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 525 {
 526         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 527
 528         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 529                                                      intel_dp->num_source_rates,
 530                                                      intel_dp->sink_rates,
 531                                                      intel_dp->num_sink_rates,
 532                                                      intel_dp->common_rates);
 533
 534         /* Paranoia, there should always be something in common. */
 535         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 536                 intel_dp->common_rates[0] = 162000;
 537                 intel_dp->num_common_rates = 1;
 538         }
 539 }
 540
 541 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 542                                        uint8_t lane_count)
 543 {
 544         /*
 545          * FIXME: we need to synchronize the current link parameters with
 546          * hardware readout. Currently fast link training doesn't work on
 547          * boot-up.
 548          */
 549         if (link_rate == 0 ||
 550             link_rate > intel_dp->max_link_rate)
 551                 return false;
 552
 553         if (lane_count == 0 ||
 554             lane_count > intel_dp_max_lane_count(intel_dp))
 555                 return false;
 556
 557         return true;
 558 }
 559
 560 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 561                                             int link_rate, uint8_t lane_count)
 562 {
 563         int index;
 564
 565         index = intel_dp_rate_index(intel_dp->common_rates,
 566                                     intel_dp->num_common_rates,
 567                                     link_rate);
 568         if (index > 0) {
 569                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 570                 intel_dp->max_link_lane_count = lane_count;
 571         } else if (lane_count > 1) {
 572                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 573                 intel_dp->max_link_lane_count = lane_count >> 1;
 574         } else {
 575                 DRM_ERROR("Link Training Unsuccessful\n");
 576                 return -1;
 577         }
 578
 579         return 0;
 580 }
 581
 582 static enum drm_mode_status
 583 intel_dp_mode_valid(struct drm_connector *connector,
 584                     struct drm_display_mode *mode)
 585 {
 586         struct intel_dp *intel_dp = intel_attached_dp(connector);
 587         struct intel_connector *intel_connector = to_intel_connector(connector);
 588         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 589         int target_clock = mode->clock;
 590         int max_rate, mode_rate, max_lanes, max_link_clock;
 591         int max_dotclk;
 592
 593         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 594                 return MODE_NO_DBLESCAN;
 595
 596         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 597
 598         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 599                 if (mode->hdisplay > fixed_mode->hdisplay)
 600                         return MODE_PANEL;
 601
 602                 if (mode->vdisplay > fixed_mode->vdisplay)
 603                         return MODE_PANEL;
 604
 605                 target_clock = fixed_mode->clock;
 606         }
 607
 608         max_link_clock = intel_dp_max_link_rate(intel_dp);
 609         max_lanes = intel_dp_max_lane_count(intel_dp);
 610
 611         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 612         mode_rate = intel_dp_link_required(target_clock, 18);
 613
 614         if (mode_rate > max_rate || target_clock > max_dotclk)
 615                 return MODE_CLOCK_HIGH;
 616
 617         if (mode->clock < 10000)
 618                 return MODE_CLOCK_LOW;
 619
 620         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 621                 return MODE_H_ILLEGAL;
 622
 623         return MODE_OK;
 624 }
 625
 626 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 627 {
 628         int     i;
 629         uint32_t v = 0;
 630
 631         if (src_bytes > 4)
 632                 src_bytes = 4;
 633         for (i = 0; i < src_bytes; i++)
 634                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 635         return v;
 636 }
 637
 638 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 639 {
 640         int i;
 641         if (dst_bytes > 4)
 642                 dst_bytes = 4;
 643         for (i = 0; i < dst_bytes; i++)
 644                 dst[i] = src >> ((3-i) * 8);
 645 }
 646
 647 static void
 648 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 649 static void
 650 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 651                                               bool force_disable_vdd);
 652 static void
 653 intel_dp_pps_init(struct intel_dp *intel_dp);
 654
 655 static void pps_lock(struct intel_dp *intel_dp)
 656 {
 657         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 658
 659         /*
 660          * See intel_power_sequencer_reset() why we need
 661          * a power domain reference here.
 662          */
 663         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 664
 665         mutex_lock(&dev_priv->pps_mutex);
 666 }
 667
 668 static void pps_unlock(struct intel_dp *intel_dp)
 669 {
 670         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 671
 672         mutex_unlock(&dev_priv->pps_mutex);
 673
 674         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 675 }
 676
 677 static void
 678 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 679 {
 680         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 681         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 682         enum pipe pipe = intel_dp->pps_pipe;
 683         bool pll_enabled, release_cl_override = false;
 684         enum dpio_phy phy = DPIO_PHY(pipe);
 685         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 686         uint32_t DP;
 687
 688         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 689                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 690                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 691                 return;
 692
 693         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 694                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 695
 696         /* Preserve the BIOS-computed detected bit. This is
 697          * supposed to be read-only.
 698          */
 699         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 700         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 701         DP |= DP_PORT_WIDTH(1);
 702         DP |= DP_LINK_TRAIN_PAT_1;
 703
 704         if (IS_CHERRYVIEW(dev_priv))
 705                 DP |= DP_PIPE_SEL_CHV(pipe);
 706         else
 707                 DP |= DP_PIPE_SEL(pipe);
 708
 709         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 710
 711         /*
 712          * The DPLL for the pipe must be enabled for this to work.
 713          * So enable temporarily it if it's not already enabled.
 714          */
 715         if (!pll_enabled) {
 716                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 717                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 718
 719                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 720                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 721                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 722                                   pipe_name(pipe));
 723                         return;
 724                 }
 725         }
 726
 727         /*
 728          * Similar magic as in intel_dp_enable_port().
 729          * We _must_ do this port enable + disable trick
 730          * to make this power sequencer lock onto the port.
 731          * Otherwise even VDD force bit won't work.
 732          */
 733         I915_WRITE(intel_dp->output_reg, DP);
 734         POSTING_READ(intel_dp->output_reg);
 735
 736         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 737         POSTING_READ(intel_dp->output_reg);
 738
 739         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 740         POSTING_READ(intel_dp->output_reg);
 741
 742         if (!pll_enabled) {
 743                 vlv_force_pll_off(dev_priv, pipe);
 744
 745                 if (release_cl_override)
 746                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 747         }
 748 }
 749
 750 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 751 {
 752         struct intel_encoder *encoder;
 753         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 754
 755         /*
 756          * We don't have power sequencer currently.
 757          * Pick one that's not used by other ports.
 758          */
 759         for_each_intel_dp(&dev_priv->drm, encoder) {
 760                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 761
 762                 if (encoder->type == INTEL_OUTPUT_EDP) {
 763                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 764                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 765
 766                         if (intel_dp->pps_pipe != INVALID_PIPE)
 767                                 pipes &= ~(1 << intel_dp->pps_pipe);
 768                 } else {
 769                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 770
 771                         if (intel_dp->active_pipe != INVALID_PIPE)
 772                                 pipes &= ~(1 << intel_dp->active_pipe);
 773                 }
 774         }
 775
 776         if (pipes == 0)
 777                 return INVALID_PIPE;
 778
 779         return ffs(pipes) - 1;
 780 }
 781
 782 static enum pipe
 783 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 784 {
 785         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 786         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 787         enum pipe pipe;
 788
 789         lockdep_assert_held(&dev_priv->pps_mutex);
 790
 791         /* We should never land here with regular DP ports */
 792         WARN_ON(!intel_dp_is_edp(intel_dp));
 793
 794         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 795                 intel_dp->active_pipe != intel_dp->pps_pipe);
 796
 797         if (intel_dp->pps_pipe != INVALID_PIPE)
 798                 return intel_dp->pps_pipe;
 799
 800         pipe = vlv_find_free_pps(dev_priv);
 801
 802         /*
 803          * Didn't find one. This should not happen since there
 804          * are two power sequencers and up to two eDP ports.
 805          */
 806         if (WARN_ON(pipe == INVALID_PIPE))
 807                 pipe = PIPE_A;
 808
 809         vlv_steal_power_sequencer(dev_priv, pipe);
 810         intel_dp->pps_pipe = pipe;
 811
 812         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 813                       pipe_name(intel_dp->pps_pipe),
 814                       port_name(intel_dig_port->base.port));
 815
 816         /* init power sequencer on this pipe and port */
 817         intel_dp_init_panel_power_sequencer(intel_dp);
 818         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 819
 820         /*
 821          * Even vdd force doesn't work until we've made
 822          * the power sequencer lock in on the port.
 823          */
 824         vlv_power_sequencer_kick(intel_dp);
 825
 826         return intel_dp->pps_pipe;
 827 }
 828
 829 static int
 830 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 831 {
 832         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 833         int backlight_controller = dev_priv->vbt.backlight.controller;
 834
 835         lockdep_assert_held(&dev_priv->pps_mutex);
 836
 837         /* We should never land here with regular DP ports */
 838         WARN_ON(!intel_dp_is_edp(intel_dp));
 839
 840         if (!intel_dp->pps_reset)
 841                 return backlight_controller;
 842
 843         intel_dp->pps_reset = false;
 844
 845         /*
 846          * Only the HW needs to be reprogrammed, the SW state is fixed and
 847          * has been setup during connector init.
 848          */
 849         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 850
 851         return backlight_controller;
 852 }
 853
 854 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 855                                enum pipe pipe);
 856
 857 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 858                                enum pipe pipe)
 859 {
 860         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 861 }
 862
 863 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 864                                 enum pipe pipe)
 865 {
 866         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 867 }
 868
 869 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 870                          enum pipe pipe)
 871 {
 872         return true;
 873 }
 874
 875 static enum pipe
 876 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 877                      enum port port,
 878                      vlv_pipe_check pipe_check)
 879 {
 880         enum pipe pipe;
 881
 882         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 883                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 884                         PANEL_PORT_SELECT_MASK;
 885
 886                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 887                         continue;
 888
 889                 if (!pipe_check(dev_priv, pipe))
 890                         continue;
 891
 892                 return pipe;
 893         }
 894
 895         return INVALID_PIPE;
 896 }
 897
 898 static void
 899 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 900 {
 901         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 902         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 903         enum port port = intel_dig_port->base.port;
 904
 905         lockdep_assert_held(&dev_priv->pps_mutex);
 906
 907         /* try to find a pipe with this port selected */
 908         /* first pick one where the panel is on */
 909         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 910                                                   vlv_pipe_has_pp_on);
 911         /* didn't find one? pick one where vdd is on */
 912         if (intel_dp->pps_pipe == INVALID_PIPE)
 913                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 914                                                           vlv_pipe_has_vdd_on);
 915         /* didn't find one? pick one with just the correct port */
 916         if (intel_dp->pps_pipe == INVALID_PIPE)
 917                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 918                                                           vlv_pipe_any);
 919
 920         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 921         if (intel_dp->pps_pipe == INVALID_PIPE) {
 922                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 923                               port_name(port));
 924                 return;
 925         }
 926
 927         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 928                       port_name(port), pipe_name(intel_dp->pps_pipe));
 929
 930         intel_dp_init_panel_power_sequencer(intel_dp);
 931         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 932 }
 933
 934 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 935 {
 936         struct intel_encoder *encoder;
 937
 938         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 939                     !IS_GEN9_LP(dev_priv)))
 940                 return;
 941
 942         /*
 943          * We can't grab pps_mutex here due to deadlock with power_domain
 944          * mutex when power_domain functions are called while holding pps_mutex.
 945          * That also means that in order to use pps_pipe the code needs to
 946          * hold both a power domain reference and pps_mutex, and the power domain
 947          * reference get/put must be done while _not_ holding pps_mutex.
 948          * pps_{lock,unlock}() do these steps in the correct order, so one
 949          * should use them always.
 950          */
 951
 952         for_each_intel_dp(&dev_priv->drm, encoder) {
 953                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 954
 955                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 956
 957                 if (encoder->type != INTEL_OUTPUT_EDP)
 958                         continue;
 959
 960                 if (IS_GEN9_LP(dev_priv))
 961                         intel_dp->pps_reset = true;
 962                 else
 963                         intel_dp->pps_pipe = INVALID_PIPE;
 964         }
 965 }
 966
 967 struct pps_registers {
 968         i915_reg_t pp_ctrl;
 969         i915_reg_t pp_stat;
 970         i915_reg_t pp_on;
 971         i915_reg_t pp_off;
 972         i915_reg_t pp_div;
 973 };
 974
 975 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 976                                     struct pps_registers *regs)
 977 {
 978         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 979         int pps_idx = 0;
 980
 981         memset(regs, 0, sizeof(*regs));
 982
 983         if (IS_GEN9_LP(dev_priv))
 984                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 985         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 986                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 987
 988         regs->pp_ctrl = PP_CONTROL(pps_idx);
 989         regs->pp_stat = PP_STATUS(pps_idx);
 990         regs->pp_on = PP_ON_DELAYS(pps_idx);
 991         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 992         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 993             !HAS_PCH_ICP(dev_priv))
 994                 regs->pp_div = PP_DIVISOR(pps_idx);
 995 }
 996
 997 static i915_reg_t
 998 _pp_ctrl_reg(struct intel_dp *intel_dp)
 999 {
1000         struct pps_registers regs;
1001
1002         intel_pps_get_registers(intel_dp, &regs);
1003
1004         return regs.pp_ctrl;
1005 }
1006
1007 static i915_reg_t
1008 _pp_stat_reg(struct intel_dp *intel_dp)
1009 {
1010         struct pps_registers regs;
1011
1012         intel_pps_get_registers(intel_dp, &regs);
1013
1014         return regs.pp_stat;
1015 }
1016
1017 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1018    This function only applicable when panel PM state is not to be tracked */
1019 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1020                               void *unused)
1021 {
1022         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1023                                                  edp_notifier);
1024         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1025
1026         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1027                 return 0;
1028
1029         pps_lock(intel_dp);
1030
1031         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1032                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1033                 i915_reg_t pp_ctrl_reg, pp_div_reg;
1034                 u32 pp_div;
1035
1036                 pp_ctrl_reg = PP_CONTROL(pipe);
1037                 pp_div_reg  = PP_DIVISOR(pipe);
1038                 pp_div = I915_READ(pp_div_reg);
1039                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1040
1041                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1042                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1043                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
1044                 msleep(intel_dp->panel_power_cycle_delay);
1045         }
1046
1047         pps_unlock(intel_dp);
1048
1049         return 0;
1050 }
1051
1052 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1053 {
1054         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1055
1056         lockdep_assert_held(&dev_priv->pps_mutex);
1057
1058         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1059             intel_dp->pps_pipe == INVALID_PIPE)
1060                 return false;
1061
1062         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1063 }
1064
1065 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1066 {
1067         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1068
1069         lockdep_assert_held(&dev_priv->pps_mutex);
1070
1071         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1072             intel_dp->pps_pipe == INVALID_PIPE)
1073                 return false;
1074
1075         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1076 }
1077
1078 static void
1079 intel_dp_check_edp(struct intel_dp *intel_dp)
1080 {
1081         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1082
1083         if (!intel_dp_is_edp(intel_dp))
1084                 return;
1085
1086         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1087                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1088                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1089                               I915_READ(_pp_stat_reg(intel_dp)),
1090                               I915_READ(_pp_ctrl_reg(intel_dp)));
1091         }
1092 }
1093
1094 static uint32_t
1095 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1096 {
1097         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1099         uint32_t status;
1100         bool done;
1101
1102 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1103         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1104                                   msecs_to_jiffies_timeout(10));
1105         if (!done)
1106                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1107 #undef C
1108
1109         return status;
1110 }
1111
1112 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1113 {
1114         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1115
1116         if (index)
1117                 return 0;
1118
1119         /*
1120          * The clock divider is based off the hrawclk, and would like to run at
1121          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1122          */
1123         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1124 }
1125
1126 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1127 {
1128         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1129
1130         if (index)
1131                 return 0;
1132
1133         /*
1134          * The clock divider is based off the cdclk or PCH rawclk, and would
1135          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1136          * divide by 2000 and use that
1137          */
1138         if (intel_dp->aux_ch == AUX_CH_A)
1139                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1140         else
1141                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1142 }
1143
1144 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1145 {
1146         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1147
1148         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1149                 /* Workaround for non-ULT HSW */
1150                 switch (index) {
1151                 case 0: return 63;
1152                 case 1: return 72;
1153                 default: return 0;
1154                 }
1155         }
1156
1157         return ilk_get_aux_clock_divider(intel_dp, index);
1158 }
1159
1160 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1161 {
1162         /*
1163          * SKL doesn't need us to program the AUX clock divider (Hardware will
1164          * derive the clock from CDCLK automatically). We still implement the
1165          * get_aux_clock_divider vfunc to plug-in into the existing code.
1166          */
1167         return index ? 0 : 1;
1168 }
1169
1170 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1171                                      int send_bytes,
1172                                      uint32_t aux_clock_divider)
1173 {
1174         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1175         struct drm_i915_private *dev_priv =
1176                         to_i915(intel_dig_port->base.base.dev);
1177         uint32_t precharge, timeout;
1178
1179         if (IS_GEN6(dev_priv))
1180                 precharge = 3;
1181         else
1182                 precharge = 5;
1183
1184         if (IS_BROADWELL(dev_priv))
1185                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1186         else
1187                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1188
1189         return DP_AUX_CH_CTL_SEND_BUSY |
1190                DP_AUX_CH_CTL_DONE |
1191                DP_AUX_CH_CTL_INTERRUPT |
1192                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1193                timeout |
1194                DP_AUX_CH_CTL_RECEIVE_ERROR |
1195                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1196                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1197                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1198 }
1199
1200 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1201                                       int send_bytes,
1202                                       uint32_t unused)
1203 {
1204         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205         uint32_t ret;
1206
1207         ret = DP_AUX_CH_CTL_SEND_BUSY |
1208               DP_AUX_CH_CTL_DONE |
1209               DP_AUX_CH_CTL_INTERRUPT |
1210               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1211               DP_AUX_CH_CTL_TIME_OUT_MAX |
1212               DP_AUX_CH_CTL_RECEIVE_ERROR |
1213               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1214               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1215               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1216
1217         if (intel_dig_port->tc_type == TC_PORT_TBT)
1218                 ret |= DP_AUX_CH_CTL_TBT_IO;
1219
1220         return ret;
1221 }
1222
1223 static int
1224 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1225                   const uint8_t *send, int send_bytes,
1226                   uint8_t *recv, int recv_size,
1227                   u32 aux_send_ctl_flags)
1228 {
1229         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1230         struct drm_i915_private *dev_priv =
1231                         to_i915(intel_dig_port->base.base.dev);
1232         i915_reg_t ch_ctl, ch_data[5];
1233         uint32_t aux_clock_divider;
1234         int i, ret, recv_bytes;
1235         uint32_t status;
1236         int try, clock = 0;
1237         bool vdd;
1238
1239         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1240         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1241                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1242
1243         pps_lock(intel_dp);
1244
1245         /*
1246          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1247          * In such cases we want to leave VDD enabled and it's up to upper layers
1248          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1249          * ourselves.
1250          */
1251         vdd = edp_panel_vdd_on(intel_dp);
1252
1253         /* dp aux is extremely sensitive to irq latency, hence request the
1254          * lowest possible wakeup latency and so prevent the cpu from going into
1255          * deep sleep states.
1256          */
1257         pm_qos_update_request(&dev_priv->pm_qos, 0);
1258
1259         intel_dp_check_edp(intel_dp);
1260
1261         /* Try to wait for any previous AUX channel activity */
1262         for (try = 0; try < 3; try++) {
1263                 status = I915_READ_NOTRACE(ch_ctl);
1264                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1265                         break;
1266                 msleep(1);
1267         }
1268
1269         if (try == 3) {
1270                 static u32 last_status = -1;
1271                 const u32 status = I915_READ(ch_ctl);
1272
1273                 if (status != last_status) {
1274                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1275                              status);
1276                         last_status = status;
1277                 }
1278
1279                 ret = -EBUSY;
1280                 goto out;
1281         }
1282
1283         /* Only 5 data registers! */
1284         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1285                 ret = -E2BIG;
1286                 goto out;
1287         }
1288
1289         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1290                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1291                                                           send_bytes,
1292                                                           aux_clock_divider);
1293
1294                 send_ctl |= aux_send_ctl_flags;
1295
1296                 /* Must try at least 3 times according to DP spec */
1297                 for (try = 0; try < 5; try++) {
1298                         /* Load the send data into the aux channel data registers */
1299                         for (i = 0; i < send_bytes; i += 4)
1300                                 I915_WRITE(ch_data[i >> 2],
1301                                            intel_dp_pack_aux(send + i,
1302                                                              send_bytes - i));
1303
1304                         /* Send the command and wait for it to complete */
1305                         I915_WRITE(ch_ctl, send_ctl);
1306
1307                         status = intel_dp_aux_wait_done(intel_dp);
1308
1309                         /* Clear done status and any errors */
1310                         I915_WRITE(ch_ctl,
1311                                    status |
1312                                    DP_AUX_CH_CTL_DONE |
1313                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1314                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1315
1316                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1317                          *   400us delay required for errors and timeouts
1318                          *   Timeout errors from the HW already meet this
1319                          *   requirement so skip to next iteration
1320                          */
1321                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1322                                 continue;
1323
1324                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1325                                 usleep_range(400, 500);
1326                                 continue;
1327                         }
1328                         if (status & DP_AUX_CH_CTL_DONE)
1329                                 goto done;
1330                 }
1331         }
1332
1333         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1334                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1335                 ret = -EBUSY;
1336                 goto out;
1337         }
1338
1339 done:
1340         /* Check for timeout or receive error.
1341          * Timeouts occur when the sink is not connected
1342          */
1343         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1344                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1345                 ret = -EIO;
1346                 goto out;
1347         }
1348
1349         /* Timeouts occur when the device isn't connected, so they're
1350          * "normal" -- don't fill the kernel log with these */
1351         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1352                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1353                 ret = -ETIMEDOUT;
1354                 goto out;
1355         }
1356
1357         /* Unload any bytes sent back from the other side */
1358         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1359                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1360
1361         /*
1362          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1363          * We have no idea of what happened so we return -EBUSY so
1364          * drm layer takes care for the necessary retries.
1365          */
1366         if (recv_bytes == 0 || recv_bytes > 20) {
1367                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1368                               recv_bytes);
1369                 ret = -EBUSY;
1370                 goto out;
1371         }
1372
1373         if (recv_bytes > recv_size)
1374                 recv_bytes = recv_size;
1375
1376         for (i = 0; i < recv_bytes; i += 4)
1377                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1378                                     recv + i, recv_bytes - i);
1379
1380         ret = recv_bytes;
1381 out:
1382         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1383
1384         if (vdd)
1385                 edp_panel_vdd_off(intel_dp, false);
1386
1387         pps_unlock(intel_dp);
1388
1389         return ret;
1390 }
1391
1392 #define BARE_ADDRESS_SIZE       3
1393 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1394
1395 static void
1396 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1397                     const struct drm_dp_aux_msg *msg)
1398 {
1399         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1400         txbuf[1] = (msg->address >> 8) & 0xff;
1401         txbuf[2] = msg->address & 0xff;
1402         txbuf[3] = msg->size - 1;
1403 }
1404
1405 static ssize_t
1406 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1407 {
1408         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1409         uint8_t txbuf[20], rxbuf[20];
1410         size_t txsize, rxsize;
1411         int ret;
1412
1413         intel_dp_aux_header(txbuf, msg);
1414
1415         switch (msg->request & ~DP_AUX_I2C_MOT) {
1416         case DP_AUX_NATIVE_WRITE:
1417         case DP_AUX_I2C_WRITE:
1418         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1419                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1420                 rxsize = 2; /* 0 or 1 data bytes */
1421
1422                 if (WARN_ON(txsize > 20))
1423                         return -E2BIG;
1424
1425                 WARN_ON(!msg->buffer != !msg->size);
1426
1427                 if (msg->buffer)
1428                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1429
1430                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1431                                         rxbuf, rxsize, 0);
1432                 if (ret > 0) {
1433                         msg->reply = rxbuf[0] >> 4;
1434
1435                         if (ret > 1) {
1436                                 /* Number of bytes written in a short write. */
1437                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1438                         } else {
1439                                 /* Return payload size. */
1440                                 ret = msg->size;
1441                         }
1442                 }
1443                 break;
1444
1445         case DP_AUX_NATIVE_READ:
1446         case DP_AUX_I2C_READ:
1447                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1448                 rxsize = msg->size + 1;
1449
1450                 if (WARN_ON(rxsize > 20))
1451                         return -E2BIG;
1452
1453                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1454                                         rxbuf, rxsize, 0);
1455                 if (ret > 0) {
1456                         msg->reply = rxbuf[0] >> 4;
1457                         /*
1458                          * Assume happy day, and copy the data. The caller is
1459                          * expected to check msg->reply before touching it.
1460                          *
1461                          * Return payload size.
1462                          */
1463                         ret--;
1464                         memcpy(msg->buffer, rxbuf + 1, ret);
1465                 }
1466                 break;
1467
1468         default:
1469                 ret = -EINVAL;
1470                 break;
1471         }
1472
1473         return ret;
1474 }
1475
1476 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1477 {
1478         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1479         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1480         enum port port = encoder->port;
1481         const struct ddi_vbt_port_info *info =
1482                 &dev_priv->vbt.ddi_port_info[port];
1483         enum aux_ch aux_ch;
1484
1485         if (!info->alternate_aux_channel) {
1486                 aux_ch = (enum aux_ch) port;
1487
1488                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1489                               aux_ch_name(aux_ch), port_name(port));
1490                 return aux_ch;
1491         }
1492
1493         switch (info->alternate_aux_channel) {
1494         case DP_AUX_A:
1495                 aux_ch = AUX_CH_A;
1496                 break;
1497         case DP_AUX_B:
1498                 aux_ch = AUX_CH_B;
1499                 break;
1500         case DP_AUX_C:
1501                 aux_ch = AUX_CH_C;
1502                 break;
1503         case DP_AUX_D:
1504                 aux_ch = AUX_CH_D;
1505                 break;
1506         case DP_AUX_E:
1507                 aux_ch = AUX_CH_E;
1508                 break;
1509         case DP_AUX_F:
1510                 aux_ch = AUX_CH_F;
1511                 break;
1512         default:
1513                 MISSING_CASE(info->alternate_aux_channel);
1514                 aux_ch = AUX_CH_A;
1515                 break;
1516         }
1517
1518         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1519                       aux_ch_name(aux_ch), port_name(port));
1520
1521         return aux_ch;
1522 }
1523
1524 static enum intel_display_power_domain
1525 intel_aux_power_domain(struct intel_dp *intel_dp)
1526 {
1527         switch (intel_dp->aux_ch) {
1528         case AUX_CH_A:
1529                 return POWER_DOMAIN_AUX_A;
1530         case AUX_CH_B:
1531                 return POWER_DOMAIN_AUX_B;
1532         case AUX_CH_C:
1533                 return POWER_DOMAIN_AUX_C;
1534         case AUX_CH_D:
1535                 return POWER_DOMAIN_AUX_D;
1536         case AUX_CH_E:
1537                 return POWER_DOMAIN_AUX_E;
1538         case AUX_CH_F:
1539                 return POWER_DOMAIN_AUX_F;
1540         default:
1541                 MISSING_CASE(intel_dp->aux_ch);
1542                 return POWER_DOMAIN_AUX_A;
1543         }
1544 }
1545
1546 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1547 {
1548         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1549         enum aux_ch aux_ch = intel_dp->aux_ch;
1550
1551         switch (aux_ch) {
1552         case AUX_CH_B:
1553         case AUX_CH_C:
1554         case AUX_CH_D:
1555                 return DP_AUX_CH_CTL(aux_ch);
1556         default:
1557                 MISSING_CASE(aux_ch);
1558                 return DP_AUX_CH_CTL(AUX_CH_B);
1559         }
1560 }
1561
1562 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1563 {
1564         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1565         enum aux_ch aux_ch = intel_dp->aux_ch;
1566
1567         switch (aux_ch) {
1568         case AUX_CH_B:
1569         case AUX_CH_C:
1570         case AUX_CH_D:
1571                 return DP_AUX_CH_DATA(aux_ch, index);
1572         default:
1573                 MISSING_CASE(aux_ch);
1574                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1575         }
1576 }
1577
1578 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1579 {
1580         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1581         enum aux_ch aux_ch = intel_dp->aux_ch;
1582
1583         switch (aux_ch) {
1584         case AUX_CH_A:
1585                 return DP_AUX_CH_CTL(aux_ch);
1586         case AUX_CH_B:
1587         case AUX_CH_C:
1588         case AUX_CH_D:
1589                 return PCH_DP_AUX_CH_CTL(aux_ch);
1590         default:
1591                 MISSING_CASE(aux_ch);
1592                 return DP_AUX_CH_CTL(AUX_CH_A);
1593         }
1594 }
1595
1596 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1597 {
1598         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1599         enum aux_ch aux_ch = intel_dp->aux_ch;
1600
1601         switch (aux_ch) {
1602         case AUX_CH_A:
1603                 return DP_AUX_CH_DATA(aux_ch, index);
1604         case AUX_CH_B:
1605         case AUX_CH_C:
1606         case AUX_CH_D:
1607                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1608         default:
1609                 MISSING_CASE(aux_ch);
1610                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1611         }
1612 }
1613
1614 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1615 {
1616         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1617         enum aux_ch aux_ch = intel_dp->aux_ch;
1618
1619         switch (aux_ch) {
1620         case AUX_CH_A:
1621         case AUX_CH_B:
1622         case AUX_CH_C:
1623         case AUX_CH_D:
1624         case AUX_CH_E:
1625         case AUX_CH_F:
1626                 return DP_AUX_CH_CTL(aux_ch);
1627         default:
1628                 MISSING_CASE(aux_ch);
1629                 return DP_AUX_CH_CTL(AUX_CH_A);
1630         }
1631 }
1632
1633 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1634 {
1635         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1636         enum aux_ch aux_ch = intel_dp->aux_ch;
1637
1638         switch (aux_ch) {
1639         case AUX_CH_A:
1640         case AUX_CH_B:
1641         case AUX_CH_C:
1642         case AUX_CH_D:
1643         case AUX_CH_E:
1644         case AUX_CH_F:
1645                 return DP_AUX_CH_DATA(aux_ch, index);
1646         default:
1647                 MISSING_CASE(aux_ch);
1648                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1649         }
1650 }
1651
1652 static void
1653 intel_dp_aux_fini(struct intel_dp *intel_dp)
1654 {
1655         kfree(intel_dp->aux.name);
1656 }
1657
1658 static void
1659 intel_dp_aux_init(struct intel_dp *intel_dp)
1660 {
1661         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1662         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1663
1664         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1665         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1666
1667         if (INTEL_GEN(dev_priv) >= 9) {
1668                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1669                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1670         } else if (HAS_PCH_SPLIT(dev_priv)) {
1671                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1672                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1673         } else {
1674                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1675                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1676         }
1677
1678         if (INTEL_GEN(dev_priv) >= 9)
1679                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1680         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1681                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1682         else if (HAS_PCH_SPLIT(dev_priv))
1683                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1684         else
1685                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1686
1687         if (INTEL_GEN(dev_priv) >= 9)
1688                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1689         else
1690                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1691
1692         drm_dp_aux_init(&intel_dp->aux);
1693
1694         /* Failure to allocate our preferred name is not critical */
1695         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1696                                        port_name(encoder->port));
1697         intel_dp->aux.transfer = intel_dp_aux_transfer;
1698 }
1699
1700 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1701 {
1702         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1703
1704         return max_rate >= 540000;
1705 }
1706
1707 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1708 {
1709         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1710
1711         return max_rate >= 810000;
1712 }
1713
1714 static void
1715 intel_dp_set_clock(struct intel_encoder *encoder,
1716                    struct intel_crtc_state *pipe_config)
1717 {
1718         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1719         const struct dp_link_dpll *divisor = NULL;
1720         int i, count = 0;
1721
1722         if (IS_G4X(dev_priv)) {
1723                 divisor = g4x_dpll;
1724                 count = ARRAY_SIZE(g4x_dpll);
1725         } else if (HAS_PCH_SPLIT(dev_priv)) {
1726                 divisor = pch_dpll;
1727                 count = ARRAY_SIZE(pch_dpll);
1728         } else if (IS_CHERRYVIEW(dev_priv)) {
1729                 divisor = chv_dpll;
1730                 count = ARRAY_SIZE(chv_dpll);
1731         } else if (IS_VALLEYVIEW(dev_priv)) {
1732                 divisor = vlv_dpll;
1733                 count = ARRAY_SIZE(vlv_dpll);
1734         }
1735
1736         if (divisor && count) {
1737                 for (i = 0; i < count; i++) {
1738                         if (pipe_config->port_clock == divisor[i].clock) {
1739                                 pipe_config->dpll = divisor[i].dpll;
1740                                 pipe_config->clock_set = true;
1741                                 break;
1742                         }
1743                 }
1744         }
1745 }
1746
1747 static void snprintf_int_array(char *str, size_t len,
1748                                const int *array, int nelem)
1749 {
1750         int i;
1751
1752         str[0] = '\0';
1753
1754         for (i = 0; i < nelem; i++) {
1755                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1756                 if (r >= len)
1757                         return;
1758                 str += r;
1759                 len -= r;
1760         }
1761 }
1762
1763 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1764 {
1765         char str[128]; /* FIXME: too big for stack? */
1766
1767         if ((drm_debug & DRM_UT_KMS) == 0)
1768                 return;
1769
1770         snprintf_int_array(str, sizeof(str),
1771                            intel_dp->source_rates, intel_dp->num_source_rates);
1772         DRM_DEBUG_KMS("source rates: %s\n", str);
1773
1774         snprintf_int_array(str, sizeof(str),
1775                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1776         DRM_DEBUG_KMS("sink rates: %s\n", str);
1777
1778         snprintf_int_array(str, sizeof(str),
1779                            intel_dp->common_rates, intel_dp->num_common_rates);
1780         DRM_DEBUG_KMS("common rates: %s\n", str);
1781 }
1782
1783 int
1784 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1785 {
1786         int len;
1787
1788         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1789         if (WARN_ON(len <= 0))
1790                 return 162000;
1791
1792         return intel_dp->common_rates[len - 1];
1793 }
1794
1795 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1796 {
1797         int i = intel_dp_rate_index(intel_dp->sink_rates,
1798                                     intel_dp->num_sink_rates, rate);
1799
1800         if (WARN_ON(i < 0))
1801                 i = 0;
1802
1803         return i;
1804 }
1805
1806 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1807                            uint8_t *link_bw, uint8_t *rate_select)
1808 {
1809         /* eDP 1.4 rate select method. */
1810         if (intel_dp->use_rate_select) {
1811                 *link_bw = 0;
1812                 *rate_select =
1813                         intel_dp_rate_select(intel_dp, port_clock);
1814         } else {
1815                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1816                 *rate_select = 0;
1817         }
1818 }
1819
1820 struct link_config_limits {
1821         int min_clock, max_clock;
1822         int min_lane_count, max_lane_count;
1823         int min_bpp, max_bpp;
1824 };
1825
1826 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1827                                 struct intel_crtc_state *pipe_config)
1828 {
1829         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1830         struct intel_connector *intel_connector = intel_dp->attached_connector;
1831         int bpp, bpc;
1832
1833         bpp = pipe_config->pipe_bpp;
1834         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1835
1836         if (bpc > 0)
1837                 bpp = min(bpp, 3*bpc);
1838
1839         if (intel_dp_is_edp(intel_dp)) {
1840                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1841                 if (intel_connector->base.display_info.bpc == 0 &&
1842                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1843                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1844                                       dev_priv->vbt.edp.bpp);
1845                         bpp = dev_priv->vbt.edp.bpp;
1846                 }
1847         }
1848
1849         return bpp;
1850 }
1851
1852 /* Adjust link config limits based on compliance test requests. */
1853 static void
1854 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1855                                   struct intel_crtc_state *pipe_config,
1856                                   struct link_config_limits *limits)
1857 {
1858         /* For DP Compliance we override the computed bpp for the pipe */
1859         if (intel_dp->compliance.test_data.bpc != 0) {
1860                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1861
1862                 limits->min_bpp = limits->max_bpp = bpp;
1863                 pipe_config->dither_force_disable = bpp == 6 * 3;
1864
1865                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1866         }
1867
1868         /* Use values requested by Compliance Test Request */
1869         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1870                 int index;
1871
1872                 /* Validate the compliance test data since max values
1873                  * might have changed due to link train fallback.
1874                  */
1875                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1876                                                intel_dp->compliance.test_lane_count)) {
1877                         index = intel_dp_rate_index(intel_dp->common_rates,
1878                                                     intel_dp->num_common_rates,
1879                                                     intel_dp->compliance.test_link_rate);
1880                         if (index >= 0)
1881                                 limits->min_clock = limits->max_clock = index;
1882                         limits->min_lane_count = limits->max_lane_count =
1883                                 intel_dp->compliance.test_lane_count;
1884                 }
1885         }
1886 }
1887
1888 /* Optimize link config in order: max bpp, min clock, min lanes */
1889 static bool
1890 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1891                                   struct intel_crtc_state *pipe_config,
1892                                   const struct link_config_limits *limits)
1893 {
1894         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1895         int bpp, clock, lane_count;
1896         int mode_rate, link_clock, link_avail;
1897
1898         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1899                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1900                                                    bpp);
1901
1902                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1903                         for (lane_count = limits->min_lane_count;
1904                              lane_count <= limits->max_lane_count;
1905                              lane_count <<= 1) {
1906                                 link_clock = intel_dp->common_rates[clock];
1907                                 link_avail = intel_dp_max_data_rate(link_clock,
1908                                                                     lane_count);
1909
1910                                 if (mode_rate <= link_avail) {
1911                                         pipe_config->lane_count = lane_count;
1912                                         pipe_config->pipe_bpp = bpp;
1913                                         pipe_config->port_clock = link_clock;
1914
1915                                         return true;
1916                                 }
1917                         }
1918                 }
1919         }
1920
1921         return false;
1922 }
1923
1924 static bool
1925 intel_dp_compute_link_config(struct intel_encoder *encoder,
1926                              struct intel_crtc_state *pipe_config)
1927 {
1928         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1929         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1930         struct link_config_limits limits;
1931         int common_len;
1932
1933         common_len = intel_dp_common_len_rate_limit(intel_dp,
1934                                                     intel_dp->max_link_rate);
1935
1936         /* No common link rates between source and sink */
1937         WARN_ON(common_len <= 0);
1938
1939         limits.min_clock = 0;
1940         limits.max_clock = common_len - 1;
1941
1942         limits.min_lane_count = 1;
1943         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1944
1945         limits.min_bpp = 6 * 3;
1946         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1947
1948         if (intel_dp_is_edp(intel_dp)) {
1949                 /*
1950                  * Use the maximum clock and number of lanes the eDP panel
1951                  * advertizes being capable of. The panels are generally
1952                  * designed to support only a single clock and lane
1953                  * configuration, and typically these values correspond to the
1954                  * native resolution of the panel.
1955                  */
1956                 limits.min_lane_count = limits.max_lane_count;
1957                 limits.min_clock = limits.max_clock;
1958         }
1959
1960         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1961
1962         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1963                       "max rate %d max bpp %d pixel clock %iKHz\n",
1964                       limits.max_lane_count,
1965                       intel_dp->common_rates[limits.max_clock],
1966                       limits.max_bpp, adjusted_mode->crtc_clock);
1967
1968         /*
1969          * Optimize for slow and wide. This is the place to add alternative
1970          * optimization policy.
1971          */
1972         if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
1973                 return false;
1974
1975         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1976                       pipe_config->lane_count, pipe_config->port_clock,
1977                       pipe_config->pipe_bpp);
1978
1979         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1980                       intel_dp_link_required(adjusted_mode->crtc_clock,
1981                                              pipe_config->pipe_bpp),
1982                       intel_dp_max_data_rate(pipe_config->port_clock,
1983                                              pipe_config->lane_count));
1984
1985         return true;
1986 }
1987
1988 bool
1989 intel_dp_compute_config(struct intel_encoder *encoder,
1990                         struct intel_crtc_state *pipe_config,
1991                         struct drm_connector_state *conn_state)
1992 {
1993         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1994         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1995         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1996         enum port port = encoder->port;
1997         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1998         struct intel_connector *intel_connector = intel_dp->attached_connector;
1999         struct intel_digital_connector_state *intel_conn_state =
2000                 to_intel_digital_connector_state(conn_state);
2001         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
2002                                            DP_DPCD_QUIRK_LIMITED_M_N);
2003
2004         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2005                 pipe_config->has_pch_encoder = true;
2006
2007         pipe_config->has_drrs = false;
2008         if (IS_G4X(dev_priv) || port == PORT_A)
2009                 pipe_config->has_audio = false;
2010         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2011                 pipe_config->has_audio = intel_dp->has_audio;
2012         else
2013                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2014
2015         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2016                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2017                                        adjusted_mode);
2018
2019                 if (INTEL_GEN(dev_priv) >= 9) {
2020                         int ret;
2021
2022                         ret = skl_update_scaler_crtc(pipe_config);
2023                         if (ret)
2024                                 return ret;
2025                 }
2026
2027                 if (HAS_GMCH_DISPLAY(dev_priv))
2028                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2029                                                  conn_state->scaling_mode);
2030                 else
2031                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2032                                                 conn_state->scaling_mode);
2033         }
2034
2035         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2036                 return false;
2037
2038         if (HAS_GMCH_DISPLAY(dev_priv) &&
2039             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2040                 return false;
2041
2042         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2043                 return false;
2044
2045         if (!intel_dp_compute_link_config(encoder, pipe_config))
2046                 return false;
2047
2048         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2049                 /*
2050                  * See:
2051                  * CEA-861-E - 5.1 Default Encoding Parameters
2052                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2053                  */
2054                 pipe_config->limited_color_range =
2055                         pipe_config->pipe_bpp != 18 &&
2056                         drm_default_rgb_quant_range(adjusted_mode) ==
2057                         HDMI_QUANTIZATION_RANGE_LIMITED;
2058         } else {
2059                 pipe_config->limited_color_range =
2060                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2061         }
2062
2063         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
2064                                adjusted_mode->crtc_clock,
2065                                pipe_config->port_clock,
2066                                &pipe_config->dp_m_n,
2067                                reduce_m_n);
2068
2069         if (intel_connector->panel.downclock_mode != NULL &&
2070                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2071                         pipe_config->has_drrs = true;
2072                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2073                                                pipe_config->lane_count,
2074                                                intel_connector->panel.downclock_mode->clock,
2075                                                pipe_config->port_clock,
2076                                                &pipe_config->dp_m2_n2,
2077                                                reduce_m_n);
2078         }
2079
2080         if (!HAS_DDI(dev_priv))
2081                 intel_dp_set_clock(encoder, pipe_config);
2082
2083         intel_psr_compute_config(intel_dp, pipe_config);
2084
2085         return true;
2086 }
2087
2088 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2089                               int link_rate, uint8_t lane_count,
2090                               bool link_mst)
2091 {
2092         intel_dp->link_trained = false;
2093         intel_dp->link_rate = link_rate;
2094         intel_dp->lane_count = lane_count;
2095         intel_dp->link_mst = link_mst;
2096 }
2097
2098 static void intel_dp_prepare(struct intel_encoder *encoder,
2099                              const struct intel_crtc_state *pipe_config)
2100 {
2101         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2102         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103         enum port port = encoder->port;
2104         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2105         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2106
2107         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2108                                  pipe_config->lane_count,
2109                                  intel_crtc_has_type(pipe_config,
2110                                                      INTEL_OUTPUT_DP_MST));
2111
2112         /*
2113          * There are four kinds of DP registers:
2114          *
2115          *      IBX PCH
2116          *      SNB CPU
2117          *      IVB CPU
2118          *      CPT PCH
2119          *
2120          * IBX PCH and CPU are the same for almost everything,
2121          * except that the CPU DP PLL is configured in this
2122          * register
2123          *
2124          * CPT PCH is quite different, having many bits moved
2125          * to the TRANS_DP_CTL register instead. That
2126          * configuration happens (oddly) in ironlake_pch_enable
2127          */
2128
2129         /* Preserve the BIOS-computed detected bit. This is
2130          * supposed to be read-only.
2131          */
2132         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2133
2134         /* Handle DP bits in common between all three register formats */
2135         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2136         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2137
2138         /* Split out the IBX/CPU vs CPT settings */
2139
2140         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2141                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2142                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2143                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2144                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2145                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2146
2147                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2148                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2149
2150                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2151         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2152                 u32 trans_dp;
2153
2154                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2155
2156                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2157                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2158                         trans_dp |= TRANS_DP_ENH_FRAMING;
2159                 else
2160                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2161                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2162         } else {
2163                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2164                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2165
2166                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2167                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2168                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2169                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2170                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2171
2172                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2173                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2174
2175                 if (IS_CHERRYVIEW(dev_priv))
2176                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2177                 else
2178                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2179         }
2180 }
2181
2182 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2183 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2184
2185 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2186 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2187
2188 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2189 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2190
2191 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2192
2193 static void wait_panel_status(struct intel_dp *intel_dp,
2194                                        u32 mask,
2195                                        u32 value)
2196 {
2197         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2198         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2199
2200         lockdep_assert_held(&dev_priv->pps_mutex);
2201
2202         intel_pps_verify_state(intel_dp);
2203
2204         pp_stat_reg = _pp_stat_reg(intel_dp);
2205         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2206
2207         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2208                         mask, value,
2209                         I915_READ(pp_stat_reg),
2210                         I915_READ(pp_ctrl_reg));
2211
2212         if (intel_wait_for_register(dev_priv,
2213                                     pp_stat_reg, mask, value,
2214                                     5000))
2215                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2216                                 I915_READ(pp_stat_reg),
2217                                 I915_READ(pp_ctrl_reg));
2218
2219         DRM_DEBUG_KMS("Wait complete\n");
2220 }
2221
2222 static void wait_panel_on(struct intel_dp *intel_dp)
2223 {
2224         DRM_DEBUG_KMS("Wait for panel power on\n");
2225         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2226 }
2227
2228 static void wait_panel_off(struct intel_dp *intel_dp)
2229 {
2230         DRM_DEBUG_KMS("Wait for panel power off time\n");
2231         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2232 }
2233
2234 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2235 {
2236         ktime_t panel_power_on_time;
2237         s64 panel_power_off_duration;
2238
2239         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2240
2241         /* take the difference of currrent time and panel power off time
2242          * and then make panel wait for t11_t12 if needed. */
2243         panel_power_on_time = ktime_get_boottime();
2244         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2245
2246         /* When we disable the VDD override bit last we have to do the manual
2247          * wait. */
2248         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2249                 wait_remaining_ms_from_jiffies(jiffies,
2250                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2251
2252         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2253 }
2254
2255 static void wait_backlight_on(struct intel_dp *intel_dp)
2256 {
2257         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2258                                        intel_dp->backlight_on_delay);
2259 }
2260
2261 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2262 {
2263         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2264                                        intel_dp->backlight_off_delay);
2265 }
2266
2267 /* Read the current pp_control value, unlocking the register if it
2268  * is locked
2269  */
2270
2271 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2272 {
2273         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2274         u32 control;
2275
2276         lockdep_assert_held(&dev_priv->pps_mutex);
2277
2278         control = I915_READ(_pp_ctrl_reg(intel_dp));
2279         if (WARN_ON(!HAS_DDI(dev_priv) &&
2280                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2281                 control &= ~PANEL_UNLOCK_MASK;
2282                 control |= PANEL_UNLOCK_REGS;
2283         }
2284         return control;
2285 }
2286
2287 /*
2288  * Must be paired with edp_panel_vdd_off().
2289  * Must hold pps_mutex around the whole on/off sequence.
2290  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2291  */
2292 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2293 {
2294         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2296         u32 pp;
2297         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2298         bool need_to_disable = !intel_dp->want_panel_vdd;
2299
2300         lockdep_assert_held(&dev_priv->pps_mutex);
2301
2302         if (!intel_dp_is_edp(intel_dp))
2303                 return false;
2304
2305         cancel_delayed_work(&intel_dp->panel_vdd_work);
2306         intel_dp->want_panel_vdd = true;
2307
2308         if (edp_have_panel_vdd(intel_dp))
2309                 return need_to_disable;
2310
2311         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2312
2313         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2314                       port_name(intel_dig_port->base.port));
2315
2316         if (!edp_have_panel_power(intel_dp))
2317                 wait_panel_power_cycle(intel_dp);
2318
2319         pp = ironlake_get_pp_control(intel_dp);
2320         pp |= EDP_FORCE_VDD;
2321
2322         pp_stat_reg = _pp_stat_reg(intel_dp);
2323         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2324
2325         I915_WRITE(pp_ctrl_reg, pp);
2326         POSTING_READ(pp_ctrl_reg);
2327         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2328                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2329         /*
2330          * If the panel wasn't on, delay before accessing aux channel
2331          */
2332         if (!edp_have_panel_power(intel_dp)) {
2333                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2334                               port_name(intel_dig_port->base.port));
2335                 msleep(intel_dp->panel_power_up_delay);
2336         }
2337
2338         return need_to_disable;
2339 }
2340
2341 /*
2342  * Must be paired with intel_edp_panel_vdd_off() or
2343  * intel_edp_panel_off().
2344  * Nested calls to these functions are not allowed since
2345  * we drop the lock. Caller must use some higher level
2346  * locking to prevent nested calls from other threads.
2347  */
2348 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2349 {
2350         bool vdd;
2351
2352         if (!intel_dp_is_edp(intel_dp))
2353                 return;
2354
2355         pps_lock(intel_dp);
2356         vdd = edp_panel_vdd_on(intel_dp);
2357         pps_unlock(intel_dp);
2358
2359         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2360              port_name(dp_to_dig_port(intel_dp)->base.port));
2361 }
2362
2363 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2364 {
2365         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2366         struct intel_digital_port *intel_dig_port =
2367                 dp_to_dig_port(intel_dp);
2368         u32 pp;
2369         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2370
2371         lockdep_assert_held(&dev_priv->pps_mutex);
2372
2373         WARN_ON(intel_dp->want_panel_vdd);
2374
2375         if (!edp_have_panel_vdd(intel_dp))
2376                 return;
2377
2378         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2379                       port_name(intel_dig_port->base.port));
2380
2381         pp = ironlake_get_pp_control(intel_dp);
2382         pp &= ~EDP_FORCE_VDD;
2383
2384         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2385         pp_stat_reg = _pp_stat_reg(intel_dp);
2386
2387         I915_WRITE(pp_ctrl_reg, pp);
2388         POSTING_READ(pp_ctrl_reg);
2389
2390         /* Make sure sequencer is idle before allowing subsequent activity */
2391         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2392         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2393
2394         if ((pp & PANEL_POWER_ON) == 0)
2395                 intel_dp->panel_power_off_time = ktime_get_boottime();
2396
2397         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2398 }
2399
2400 static void edp_panel_vdd_work(struct work_struct *__work)
2401 {
2402         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2403                                                  struct intel_dp, panel_vdd_work);
2404
2405         pps_lock(intel_dp);
2406         if (!intel_dp->want_panel_vdd)
2407                 edp_panel_vdd_off_sync(intel_dp);
2408         pps_unlock(intel_dp);
2409 }
2410
2411 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2412 {
2413         unsigned long delay;
2414
2415         /*
2416          * Queue the timer to fire a long time from now (relative to the power
2417          * down delay) to keep the panel power up across a sequence of
2418          * operations.
2419          */
2420         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2421         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2422 }
2423
2424 /*
2425  * Must be paired with edp_panel_vdd_on().
2426  * Must hold pps_mutex around the whole on/off sequence.
2427  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2428  */
2429 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2430 {
2431         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2432
2433         lockdep_assert_held(&dev_priv->pps_mutex);
2434
2435         if (!intel_dp_is_edp(intel_dp))
2436                 return;
2437
2438         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2439              port_name(dp_to_dig_port(intel_dp)->base.port));
2440
2441         intel_dp->want_panel_vdd = false;
2442
2443         if (sync)
2444                 edp_panel_vdd_off_sync(intel_dp);
2445         else
2446                 edp_panel_vdd_schedule_off(intel_dp);
2447 }
2448
2449 static void edp_panel_on(struct intel_dp *intel_dp)
2450 {
2451         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2452         u32 pp;
2453         i915_reg_t pp_ctrl_reg;
2454
2455         lockdep_assert_held(&dev_priv->pps_mutex);
2456
2457         if (!intel_dp_is_edp(intel_dp))
2458                 return;
2459
2460         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2461                       port_name(dp_to_dig_port(intel_dp)->base.port));
2462
2463         if (WARN(edp_have_panel_power(intel_dp),
2464                  "eDP port %c panel power already on\n",
2465                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2466                 return;
2467
2468         wait_panel_power_cycle(intel_dp);
2469
2470         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2471         pp = ironlake_get_pp_control(intel_dp);
2472         if (IS_GEN5(dev_priv)) {
2473                 /* ILK workaround: disable reset around power sequence */
2474                 pp &= ~PANEL_POWER_RESET;
2475                 I915_WRITE(pp_ctrl_reg, pp);
2476                 POSTING_READ(pp_ctrl_reg);
2477         }
2478
2479         pp |= PANEL_POWER_ON;
2480         if (!IS_GEN5(dev_priv))
2481                 pp |= PANEL_POWER_RESET;
2482
2483         I915_WRITE(pp_ctrl_reg, pp);
2484         POSTING_READ(pp_ctrl_reg);
2485
2486         wait_panel_on(intel_dp);
2487         intel_dp->last_power_on = jiffies;
2488
2489         if (IS_GEN5(dev_priv)) {
2490                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2491                 I915_WRITE(pp_ctrl_reg, pp);
2492                 POSTING_READ(pp_ctrl_reg);
2493         }
2494 }
2495
2496 void intel_edp_panel_on(struct intel_dp *intel_dp)
2497 {
2498         if (!intel_dp_is_edp(intel_dp))
2499                 return;
2500
2501         pps_lock(intel_dp);
2502         edp_panel_on(intel_dp);
2503         pps_unlock(intel_dp);
2504 }
2505
2506
2507 static void edp_panel_off(struct intel_dp *intel_dp)
2508 {
2509         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2510         u32 pp;
2511         i915_reg_t pp_ctrl_reg;
2512
2513         lockdep_assert_held(&dev_priv->pps_mutex);
2514
2515         if (!intel_dp_is_edp(intel_dp))
2516                 return;
2517
2518         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2519                       port_name(dp_to_dig_port(intel_dp)->base.port));
2520
2521         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2522              port_name(dp_to_dig_port(intel_dp)->base.port));
2523
2524         pp = ironlake_get_pp_control(intel_dp);
2525         /* We need to switch off panel power _and_ force vdd, for otherwise some
2526          * panels get very unhappy and cease to work. */
2527         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2528                 EDP_BLC_ENABLE);
2529
2530         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2531
2532         intel_dp->want_panel_vdd = false;
2533
2534         I915_WRITE(pp_ctrl_reg, pp);
2535         POSTING_READ(pp_ctrl_reg);
2536
2537         wait_panel_off(intel_dp);
2538         intel_dp->panel_power_off_time = ktime_get_boottime();
2539
2540         /* We got a reference when we enabled the VDD. */
2541         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2542 }
2543
2544 void intel_edp_panel_off(struct intel_dp *intel_dp)
2545 {
2546         if (!intel_dp_is_edp(intel_dp))
2547                 return;
2548
2549         pps_lock(intel_dp);
2550         edp_panel_off(intel_dp);
2551         pps_unlock(intel_dp);
2552 }
2553
2554 /* Enable backlight in the panel power control. */
2555 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2556 {
2557         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2558         u32 pp;
2559         i915_reg_t pp_ctrl_reg;
2560
2561         /*
2562          * If we enable the backlight right away following a panel power
2563          * on, we may see slight flicker as the panel syncs with the eDP
2564          * link.  So delay a bit to make sure the image is solid before
2565          * allowing it to appear.
2566          */
2567         wait_backlight_on(intel_dp);
2568
2569         pps_lock(intel_dp);
2570
2571         pp = ironlake_get_pp_control(intel_dp);
2572         pp |= EDP_BLC_ENABLE;
2573
2574         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2575
2576         I915_WRITE(pp_ctrl_reg, pp);
2577         POSTING_READ(pp_ctrl_reg);
2578
2579         pps_unlock(intel_dp);
2580 }
2581
2582 /* Enable backlight PWM and backlight PP control. */
2583 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2584                             const struct drm_connector_state *conn_state)
2585 {
2586         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2587
2588         if (!intel_dp_is_edp(intel_dp))
2589                 return;
2590
2591         DRM_DEBUG_KMS("\n");
2592
2593         intel_panel_enable_backlight(crtc_state, conn_state);
2594         _intel_edp_backlight_on(intel_dp);
2595 }
2596
2597 /* Disable backlight in the panel power control. */
2598 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2599 {
2600         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2601         u32 pp;
2602         i915_reg_t pp_ctrl_reg;
2603
2604         if (!intel_dp_is_edp(intel_dp))
2605                 return;
2606
2607         pps_lock(intel_dp);
2608
2609         pp = ironlake_get_pp_control(intel_dp);
2610         pp &= ~EDP_BLC_ENABLE;
2611
2612         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2613
2614         I915_WRITE(pp_ctrl_reg, pp);
2615         POSTING_READ(pp_ctrl_reg);
2616
2617         pps_unlock(intel_dp);
2618
2619         intel_dp->last_backlight_off = jiffies;
2620         edp_wait_backlight_off(intel_dp);
2621 }
2622
2623 /* Disable backlight PP control and backlight PWM. */
2624 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2625 {
2626         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2627
2628         if (!intel_dp_is_edp(intel_dp))
2629                 return;
2630
2631         DRM_DEBUG_KMS("\n");
2632
2633         _intel_edp_backlight_off(intel_dp);
2634         intel_panel_disable_backlight(old_conn_state);
2635 }
2636
2637 /*
2638  * Hook for controlling the panel power control backlight through the bl_power
2639  * sysfs attribute. Take care to handle multiple calls.
2640  */
2641 static void intel_edp_backlight_power(struct intel_connector *connector,
2642                                       bool enable)
2643 {
2644         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2645         bool is_enabled;
2646
2647         pps_lock(intel_dp);
2648         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2649         pps_unlock(intel_dp);
2650
2651         if (is_enabled == enable)
2652                 return;
2653
2654         DRM_DEBUG_KMS("panel power control backlight %s\n",
2655                       enable ? "enable" : "disable");
2656
2657         if (enable)
2658                 _intel_edp_backlight_on(intel_dp);
2659         else
2660                 _intel_edp_backlight_off(intel_dp);
2661 }
2662
2663 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2664 {
2665         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2666         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2667         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2668
2669         I915_STATE_WARN(cur_state != state,
2670                         "DP port %c state assertion failure (expected %s, current %s)\n",
2671                         port_name(dig_port->base.port),
2672                         onoff(state), onoff(cur_state));
2673 }
2674 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2675
2676 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2677 {
2678         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2679
2680         I915_STATE_WARN(cur_state != state,
2681                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2682                         onoff(state), onoff(cur_state));
2683 }
2684 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2685 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2686
2687 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2688                                 const struct intel_crtc_state *pipe_config)
2689 {
2690         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2691         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2692
2693         assert_pipe_disabled(dev_priv, crtc->pipe);
2694         assert_dp_port_disabled(intel_dp);
2695         assert_edp_pll_disabled(dev_priv);
2696
2697         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2698                       pipe_config->port_clock);
2699
2700         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2701
2702         if (pipe_config->port_clock == 162000)
2703                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2704         else
2705                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2706
2707         I915_WRITE(DP_A, intel_dp->DP);
2708         POSTING_READ(DP_A);
2709         udelay(500);
2710
2711         /*
2712          * [DevILK] Work around required when enabling DP PLL
2713          * while a pipe is enabled going to FDI:
2714          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2715          * 2. Program DP PLL enable
2716          */
2717         if (IS_GEN5(dev_priv))
2718                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2719
2720         intel_dp->DP |= DP_PLL_ENABLE;
2721
2722         I915_WRITE(DP_A, intel_dp->DP);
2723         POSTING_READ(DP_A);
2724         udelay(200);
2725 }
2726
2727 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2728                                  const struct intel_crtc_state *old_crtc_state)
2729 {
2730         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2731         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2732
2733         assert_pipe_disabled(dev_priv, crtc->pipe);
2734         assert_dp_port_disabled(intel_dp);
2735         assert_edp_pll_enabled(dev_priv);
2736
2737         DRM_DEBUG_KMS("disabling eDP PLL\n");
2738
2739         intel_dp->DP &= ~DP_PLL_ENABLE;
2740
2741         I915_WRITE(DP_A, intel_dp->DP);
2742         POSTING_READ(DP_A);
2743         udelay(200);
2744 }
2745
2746 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2747 {
2748         /*
2749          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2750          * be capable of signalling downstream hpd with a long pulse.
2751          * Whether or not that means D3 is safe to use is not clear,
2752          * but let's assume so until proven otherwise.
2753          *
2754          * FIXME should really check all downstream ports...
2755          */
2756         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2757                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2758                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2759 }
2760
2761 /* If the sink supports it, try to set the power state appropriately */
2762 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2763 {
2764         int ret, i;
2765
2766         /* Should have a valid DPCD by this point */
2767         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2768                 return;
2769
2770         if (mode != DRM_MODE_DPMS_ON) {
2771                 if (downstream_hpd_needs_d0(intel_dp))
2772                         return;
2773
2774                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2775                                          DP_SET_POWER_D3);
2776         } else {
2777                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2778
2779                 /*
2780                  * When turning on, we need to retry for 1ms to give the sink
2781                  * time to wake up.
2782                  */
2783                 for (i = 0; i < 3; i++) {
2784                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2785                                                  DP_SET_POWER_D0);
2786                         if (ret == 1)
2787                                 break;
2788                         msleep(1);
2789                 }
2790
2791                 if (ret == 1 && lspcon->active)
2792                         lspcon_wait_pcon_mode(lspcon);
2793         }
2794
2795         if (ret != 1)
2796                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2797                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2798 }
2799
2800 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2801                                  enum port port, enum pipe *pipe)
2802 {
2803         enum pipe p;
2804
2805         for_each_pipe(dev_priv, p) {
2806                 u32 val = I915_READ(TRANS_DP_CTL(p));
2807
2808                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2809                         *pipe = p;
2810                         return true;
2811                 }
2812         }
2813
2814         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2815
2816         /* must initialize pipe to something for the asserts */
2817         *pipe = PIPE_A;
2818
2819         return false;
2820 }
2821
2822 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2823                            i915_reg_t dp_reg, enum port port,
2824                            enum pipe *pipe)
2825 {
2826         bool ret;
2827         u32 val;
2828
2829         val = I915_READ(dp_reg);
2830
2831         ret = val & DP_PORT_EN;
2832
2833         /* asserts want to know the pipe even if the port is disabled */
2834         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2835                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2836         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2837                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2838         else if (IS_CHERRYVIEW(dev_priv))
2839                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2840         else
2841                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2842
2843         return ret;
2844 }
2845
2846 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2847                                   enum pipe *pipe)
2848 {
2849         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2850         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2851         bool ret;
2852
2853         if (!intel_display_power_get_if_enabled(dev_priv,
2854                                                 encoder->power_domain))
2855                 return false;
2856
2857         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2858                                     encoder->port, pipe);
2859
2860         intel_display_power_put(dev_priv, encoder->power_domain);
2861
2862         return ret;
2863 }
2864
2865 static void intel_dp_get_config(struct intel_encoder *encoder,
2866                                 struct intel_crtc_state *pipe_config)
2867 {
2868         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2869         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2870         u32 tmp, flags = 0;
2871         enum port port = encoder->port;
2872         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2873
2874         if (encoder->type == INTEL_OUTPUT_EDP)
2875                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2876         else
2877                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2878
2879         tmp = I915_READ(intel_dp->output_reg);
2880
2881         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2882
2883         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2884                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2885
2886                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2887                         flags |= DRM_MODE_FLAG_PHSYNC;
2888                 else
2889                         flags |= DRM_MODE_FLAG_NHSYNC;
2890
2891                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2892                         flags |= DRM_MODE_FLAG_PVSYNC;
2893                 else
2894                         flags |= DRM_MODE_FLAG_NVSYNC;
2895         } else {
2896                 if (tmp & DP_SYNC_HS_HIGH)
2897                         flags |= DRM_MODE_FLAG_PHSYNC;
2898                 else
2899                         flags |= DRM_MODE_FLAG_NHSYNC;
2900
2901                 if (tmp & DP_SYNC_VS_HIGH)
2902                         flags |= DRM_MODE_FLAG_PVSYNC;
2903                 else
2904                         flags |= DRM_MODE_FLAG_NVSYNC;
2905         }
2906
2907         pipe_config->base.adjusted_mode.flags |= flags;
2908
2909         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2910                 pipe_config->limited_color_range = true;
2911
2912         pipe_config->lane_count =
2913                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2914
2915         intel_dp_get_m_n(crtc, pipe_config);
2916
2917         if (port == PORT_A) {
2918                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2919                         pipe_config->port_clock = 162000;
2920                 else
2921                         pipe_config->port_clock = 270000;
2922         }
2923
2924         pipe_config->base.adjusted_mode.crtc_clock =
2925                 intel_dotclock_calculate(pipe_config->port_clock,
2926                                          &pipe_config->dp_m_n);
2927
2928         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2929             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2930                 /*
2931                  * This is a big fat ugly hack.
2932                  *
2933                  * Some machines in UEFI boot mode provide us a VBT that has 18
2934                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2935                  * unknown we fail to light up. Yet the same BIOS boots up with
2936                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2937                  * max, not what it tells us to use.
2938                  *
2939                  * Note: This will still be broken if the eDP panel is not lit
2940                  * up by the BIOS, and thus we can't get the mode at module
2941                  * load.
2942                  */
2943                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2944                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2945                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2946         }
2947 }
2948
2949 static void intel_disable_dp(struct intel_encoder *encoder,
2950                              const struct intel_crtc_state *old_crtc_state,
2951                              const struct drm_connector_state *old_conn_state)
2952 {
2953         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2954
2955         intel_dp->link_trained = false;
2956
2957         if (old_crtc_state->has_audio)
2958                 intel_audio_codec_disable(encoder,
2959                                           old_crtc_state, old_conn_state);
2960
2961         /* Make sure the panel is off before trying to change the mode. But also
2962          * ensure that we have vdd while we switch off the panel. */
2963         intel_edp_panel_vdd_on(intel_dp);
2964         intel_edp_backlight_off(old_conn_state);
2965         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2966         intel_edp_panel_off(intel_dp);
2967 }
2968
2969 static void g4x_disable_dp(struct intel_encoder *encoder,
2970                            const struct intel_crtc_state *old_crtc_state,
2971                            const struct drm_connector_state *old_conn_state)
2972 {
2973         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2974 }
2975
2976 static void vlv_disable_dp(struct intel_encoder *encoder,
2977                            const struct intel_crtc_state *old_crtc_state,
2978                            const struct drm_connector_state *old_conn_state)
2979 {
2980         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2981 }
2982
2983 static void g4x_post_disable_dp(struct intel_encoder *encoder,
2984                                 const struct intel_crtc_state *old_crtc_state,
2985                                 const struct drm_connector_state *old_conn_state)
2986 {
2987         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2988         enum port port = encoder->port;
2989
2990         /*
2991          * Bspec does not list a specific disable sequence for g4x DP.
2992          * Follow the ilk+ sequence (disable pipe before the port) for
2993          * g4x DP as it does not suffer from underruns like the normal
2994          * g4x modeset sequence (disable pipe after the port).
2995          */
2996         intel_dp_link_down(encoder, old_crtc_state);
2997
2998         /* Only ilk+ has port A */
2999         if (port == PORT_A)
3000                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3001 }
3002
3003 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3004                                 const struct intel_crtc_state *old_crtc_state,
3005                                 const struct drm_connector_state *old_conn_state)
3006 {
3007         intel_dp_link_down(encoder, old_crtc_state);
3008 }
3009
3010 static void chv_post_disable_dp(struct intel_encoder *encoder,
3011                                 const struct intel_crtc_state *old_crtc_state,
3012                                 const struct drm_connector_state *old_conn_state)
3013 {
3014         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3015
3016         intel_dp_link_down(encoder, old_crtc_state);
3017
3018         mutex_lock(&dev_priv->sb_lock);
3019
3020         /* Assert data lane reset */
3021         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3022
3023         mutex_unlock(&dev_priv->sb_lock);
3024 }
3025
3026 static void
3027 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3028                          uint32_t *DP,
3029                          uint8_t dp_train_pat)
3030 {
3031         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3032         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3033         enum port port = intel_dig_port->base.port;
3034         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3035
3036         if (dp_train_pat & train_pat_mask)
3037                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3038                               dp_train_pat & train_pat_mask);
3039
3040         if (HAS_DDI(dev_priv)) {
3041                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3042
3043                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3044                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3045                 else
3046                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3047
3048                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3049                 switch (dp_train_pat & train_pat_mask) {
3050                 case DP_TRAINING_PATTERN_DISABLE:
3051                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3052
3053                         break;
3054                 case DP_TRAINING_PATTERN_1:
3055                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3056                         break;
3057                 case DP_TRAINING_PATTERN_2:
3058                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3059                         break;
3060                 case DP_TRAINING_PATTERN_3:
3061                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3062                         break;
3063                 case DP_TRAINING_PATTERN_4:
3064                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3065                         break;
3066                 }
3067                 I915_WRITE(DP_TP_CTL(port), temp);
3068
3069         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3070                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3071                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3072
3073                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3074                 case DP_TRAINING_PATTERN_DISABLE:
3075                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3076                         break;
3077                 case DP_TRAINING_PATTERN_1:
3078                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3079                         break;
3080                 case DP_TRAINING_PATTERN_2:
3081                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3082                         break;
3083                 case DP_TRAINING_PATTERN_3:
3084                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3085                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3086                         break;
3087                 }
3088
3089         } else {
3090                 *DP &= ~DP_LINK_TRAIN_MASK;
3091
3092                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3093                 case DP_TRAINING_PATTERN_DISABLE:
3094                         *DP |= DP_LINK_TRAIN_OFF;
3095                         break;
3096                 case DP_TRAINING_PATTERN_1:
3097                         *DP |= DP_LINK_TRAIN_PAT_1;
3098                         break;
3099                 case DP_TRAINING_PATTERN_2:
3100                         *DP |= DP_LINK_TRAIN_PAT_2;
3101                         break;
3102                 case DP_TRAINING_PATTERN_3:
3103                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3104                         *DP |= DP_LINK_TRAIN_PAT_2;
3105                         break;
3106                 }
3107         }
3108 }
3109
3110 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3111                                  const struct intel_crtc_state *old_crtc_state)
3112 {
3113         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3114
3115         /* enable with pattern 1 (as per spec) */
3116
3117         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3118
3119         /*
3120          * Magic for VLV/CHV. We _must_ first set up the register
3121          * without actually enabling the port, and then do another
3122          * write to enable the port. Otherwise link training will
3123          * fail when the power sequencer is freshly used for this port.
3124          */
3125         intel_dp->DP |= DP_PORT_EN;
3126         if (old_crtc_state->has_audio)
3127                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3128
3129         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3130         POSTING_READ(intel_dp->output_reg);
3131 }
3132
3133 static void intel_enable_dp(struct intel_encoder *encoder,
3134                             const struct intel_crtc_state *pipe_config,
3135                             const struct drm_connector_state *conn_state)
3136 {
3137         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3138         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3139         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3140         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3141         enum pipe pipe = crtc->pipe;
3142
3143         if (WARN_ON(dp_reg & DP_PORT_EN))
3144                 return;
3145
3146         pps_lock(intel_dp);
3147
3148         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3149                 vlv_init_panel_power_sequencer(encoder, pipe_config);
3150
3151         intel_dp_enable_port(intel_dp, pipe_config);
3152
3153         edp_panel_vdd_on(intel_dp);
3154         edp_panel_on(intel_dp);
3155         edp_panel_vdd_off(intel_dp, true);
3156
3157         pps_unlock(intel_dp);
3158
3159         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3160                 unsigned int lane_mask = 0x0;
3161
3162                 if (IS_CHERRYVIEW(dev_priv))
3163                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3164
3165                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3166                                     lane_mask);
3167         }
3168
3169         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3170         intel_dp_start_link_train(intel_dp);
3171         intel_dp_stop_link_train(intel_dp);
3172
3173         if (pipe_config->has_audio) {
3174                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3175                                  pipe_name(pipe));
3176                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3177         }
3178 }
3179
3180 static void g4x_enable_dp(struct intel_encoder *encoder,
3181                           const struct intel_crtc_state *pipe_config,
3182                           const struct drm_connector_state *conn_state)
3183 {
3184         intel_enable_dp(encoder, pipe_config, conn_state);
3185         intel_edp_backlight_on(pipe_config, conn_state);
3186 }
3187
3188 static void vlv_enable_dp(struct intel_encoder *encoder,
3189                           const struct intel_crtc_state *pipe_config,
3190                           const struct drm_connector_state *conn_state)
3191 {
3192         intel_edp_backlight_on(pipe_config, conn_state);
3193 }
3194
3195 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3196                               const struct intel_crtc_state *pipe_config,
3197                               const struct drm_connector_state *conn_state)
3198 {
3199         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3200         enum port port = encoder->port;
3201
3202         intel_dp_prepare(encoder, pipe_config);
3203
3204         /* Only ilk+ has port A */
3205         if (port == PORT_A)
3206                 ironlake_edp_pll_on(intel_dp, pipe_config);
3207 }
3208
3209 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3210 {
3211         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3212         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3213         enum pipe pipe = intel_dp->pps_pipe;
3214         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3215
3216         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3217
3218         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3219                 return;
3220
3221         edp_panel_vdd_off_sync(intel_dp);
3222
3223         /*
3224          * VLV seems to get confused when multiple power sequencers
3225          * have the same port selected (even if only one has power/vdd
3226          * enabled). The failure manifests as vlv_wait_port_ready() failing
3227          * CHV on the other hand doesn't seem to mind having the same port
3228          * selected in multiple power sequencers, but let's clear the
3229          * port select always when logically disconnecting a power sequencer
3230          * from a port.
3231          */
3232         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3233                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3234         I915_WRITE(pp_on_reg, 0);
3235         POSTING_READ(pp_on_reg);
3236
3237         intel_dp->pps_pipe = INVALID_PIPE;
3238 }
3239
3240 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3241                                       enum pipe pipe)
3242 {
3243         struct intel_encoder *encoder;
3244
3245         lockdep_assert_held(&dev_priv->pps_mutex);
3246
3247         for_each_intel_dp(&dev_priv->drm, encoder) {
3248                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3249                 enum port port = encoder->port;
3250
3251                 WARN(intel_dp->active_pipe == pipe,
3252                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3253                      pipe_name(pipe), port_name(port));
3254
3255                 if (intel_dp->pps_pipe != pipe)
3256                         continue;
3257
3258                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3259                               pipe_name(pipe), port_name(port));
3260
3261                 /* make sure vdd is off before we steal it */
3262                 vlv_detach_power_sequencer(intel_dp);
3263         }
3264 }
3265
3266 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3267                                            const struct intel_crtc_state *crtc_state)
3268 {
3269         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3270         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3271         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3272
3273         lockdep_assert_held(&dev_priv->pps_mutex);
3274
3275         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3276
3277         if (intel_dp->pps_pipe != INVALID_PIPE &&
3278             intel_dp->pps_pipe != crtc->pipe) {
3279                 /*
3280                  * If another power sequencer was being used on this
3281                  * port previously make sure to turn off vdd there while
3282                  * we still have control of it.
3283                  */
3284                 vlv_detach_power_sequencer(intel_dp);
3285         }
3286
3287         /*
3288          * We may be stealing the power
3289          * sequencer from another port.
3290          */
3291         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3292
3293         intel_dp->active_pipe = crtc->pipe;
3294
3295         if (!intel_dp_is_edp(intel_dp))
3296                 return;
3297
3298         /* now it's all ours */
3299         intel_dp->pps_pipe = crtc->pipe;
3300
3301         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3302                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3303
3304         /* init power sequencer on this pipe and port */
3305         intel_dp_init_panel_power_sequencer(intel_dp);
3306         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3307 }
3308
3309 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3310                               const struct intel_crtc_state *pipe_config,
3311                               const struct drm_connector_state *conn_state)
3312 {
3313         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3314
3315         intel_enable_dp(encoder, pipe_config, conn_state);
3316 }
3317
3318 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3319                                   const struct intel_crtc_state *pipe_config,
3320                                   const struct drm_connector_state *conn_state)
3321 {
3322         intel_dp_prepare(encoder, pipe_config);
3323
3324         vlv_phy_pre_pll_enable(encoder, pipe_config);
3325 }
3326
3327 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3328                               const struct intel_crtc_state *pipe_config,
3329                               const struct drm_connector_state *conn_state)
3330 {
3331         chv_phy_pre_encoder_enable(encoder, pipe_config);
3332
3333         intel_enable_dp(encoder, pipe_config, conn_state);
3334
3335         /* Second common lane will stay alive on its own now */
3336         chv_phy_release_cl2_override(encoder);
3337 }
3338
3339 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3340                                   const struct intel_crtc_state *pipe_config,
3341                                   const struct drm_connector_state *conn_state)
3342 {
3343         intel_dp_prepare(encoder, pipe_config);
3344
3345         chv_phy_pre_pll_enable(encoder, pipe_config);
3346 }
3347
3348 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3349                                     const struct intel_crtc_state *old_crtc_state,
3350                                     const struct drm_connector_state *old_conn_state)
3351 {
3352         chv_phy_post_pll_disable(encoder, old_crtc_state);
3353 }
3354
3355 /*
3356  * Fetch AUX CH registers 0x202 - 0x207 which contain
3357  * link status information
3358  */
3359 bool
3360 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3361 {
3362         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3363                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3364 }
3365
3366 /* These are source-specific values. */
3367 uint8_t
3368 intel_dp_voltage_max(struct intel_dp *intel_dp)
3369 {
3370         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3371         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3372         enum port port = encoder->port;
3373
3374         if (HAS_DDI(dev_priv))
3375                 return intel_ddi_dp_voltage_max(encoder);
3376         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3377                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3378         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3379                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3380         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3381                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3382         else
3383                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3384 }
3385
3386 uint8_t
3387 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3388 {
3389         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3390         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3391         enum port port = encoder->port;
3392
3393         if (HAS_DDI(dev_priv)) {
3394                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3395         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3396                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3397                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3398                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3399                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3400                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3401                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3402                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3403                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3404                 default:
3405                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3406                 }
3407         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3408                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3409                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3410                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3411                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3412                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3413                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3414                 default:
3415                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3416                 }
3417         } else {
3418                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3419                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3420                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3421                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3422                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3423                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3424                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3425                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3426                 default:
3427                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3428                 }
3429         }
3430 }
3431
3432 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3433 {
3434         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3435         unsigned long demph_reg_value, preemph_reg_value,
3436                 uniqtranscale_reg_value;
3437         uint8_t train_set = intel_dp->train_set[0];
3438
3439         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3440         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3441                 preemph_reg_value = 0x0004000;
3442                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3443                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3444                         demph_reg_value = 0x2B405555;
3445                         uniqtranscale_reg_value = 0x552AB83A;
3446                         break;
3447                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3448                         demph_reg_value = 0x2B404040;
3449                         uniqtranscale_reg_value = 0x5548B83A;
3450                         break;
3451                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3452                         demph_reg_value = 0x2B245555;
3453                         uniqtranscale_reg_value = 0x5560B83A;
3454                         break;
3455                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3456                         demph_reg_value = 0x2B405555;
3457                         uniqtranscale_reg_value = 0x5598DA3A;
3458                         break;
3459                 default:
3460                         return 0;
3461                 }
3462                 break;
3463         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3464                 preemph_reg_value = 0x0002000;
3465                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3466                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3467                         demph_reg_value = 0x2B404040;
3468                         uniqtranscale_reg_value = 0x5552B83A;
3469                         break;
3470                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3471                         demph_reg_value = 0x2B404848;
3472                         uniqtranscale_reg_value = 0x5580B83A;
3473                         break;
3474                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3475                         demph_reg_value = 0x2B404040;
3476                         uniqtranscale_reg_value = 0x55ADDA3A;
3477                         break;
3478                 default:
3479                         return 0;
3480                 }
3481                 break;
3482         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3483                 preemph_reg_value = 0x0000000;
3484                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3485                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3486                         demph_reg_value = 0x2B305555;
3487                         uniqtranscale_reg_value = 0x5570B83A;
3488                         break;
3489                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3490                         demph_reg_value = 0x2B2B4040;
3491                         uniqtranscale_reg_value = 0x55ADDA3A;
3492                         break;
3493                 default:
3494                         return 0;
3495                 }
3496                 break;
3497         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3498                 preemph_reg_value = 0x0006000;
3499                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3500                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3501                         demph_reg_value = 0x1B405555;
3502                         uniqtranscale_reg_value = 0x55ADDA3A;
3503                         break;
3504                 default:
3505                         return 0;
3506                 }
3507                 break;
3508         default:
3509                 return 0;
3510         }
3511
3512         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3513                                  uniqtranscale_reg_value, 0);
3514
3515         return 0;
3516 }
3517
3518 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3519 {
3520         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3521         u32 deemph_reg_value, margin_reg_value;
3522         bool uniq_trans_scale = false;
3523         uint8_t train_set = intel_dp->train_set[0];
3524
3525         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3526         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3527                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3528                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3529                         deemph_reg_value = 128;
3530                         margin_reg_value = 52;
3531                         break;
3532                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3533                         deemph_reg_value = 128;
3534                         margin_reg_value = 77;
3535                         break;
3536                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3537                         deemph_reg_value = 128;
3538                         margin_reg_value = 102;
3539                         break;
3540                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3541                         deemph_reg_value = 128;
3542                         margin_reg_value = 154;
3543                         uniq_trans_scale = true;
3544                         break;
3545                 default:
3546                         return 0;
3547                 }
3548                 break;
3549         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3550                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3551                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3552                         deemph_reg_value = 85;
3553                         margin_reg_value = 78;
3554                         break;
3555                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3556                         deemph_reg_value = 85;
3557                         margin_reg_value = 116;
3558                         break;
3559                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3560                         deemph_reg_value = 85;
3561                         margin_reg_value = 154;
3562                         break;
3563                 default:
3564                         return 0;
3565                 }
3566                 break;
3567         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3568                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3569                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3570                         deemph_reg_value = 64;
3571                         margin_reg_value = 104;
3572                         break;
3573                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3574                         deemph_reg_value = 64;
3575                         margin_reg_value = 154;
3576                         break;
3577                 default:
3578                         return 0;
3579                 }
3580                 break;
3581         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3582                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3583                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3584                         deemph_reg_value = 43;
3585                         margin_reg_value = 154;
3586                         break;
3587                 default:
3588                         return 0;
3589                 }
3590                 break;
3591         default:
3592                 return 0;
3593         }
3594
3595         chv_set_phy_signal_level(encoder, deemph_reg_value,
3596                                  margin_reg_value, uniq_trans_scale);
3597
3598         return 0;
3599 }
3600
3601 static uint32_t
3602 g4x_signal_levels(uint8_t train_set)
3603 {
3604         uint32_t        signal_levels = 0;
3605
3606         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3607         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3608         default:
3609                 signal_levels |= DP_VOLTAGE_0_4;
3610                 break;
3611         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3612                 signal_levels |= DP_VOLTAGE_0_6;
3613                 break;
3614         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3615                 signal_levels |= DP_VOLTAGE_0_8;
3616                 break;
3617         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3618                 signal_levels |= DP_VOLTAGE_1_2;
3619                 break;
3620         }
3621         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3622         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3623         default:
3624                 signal_levels |= DP_PRE_EMPHASIS_0;
3625                 break;
3626         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3627                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3628                 break;
3629         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3630                 signal_levels |= DP_PRE_EMPHASIS_6;
3631                 break;
3632         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3633                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3634                 break;
3635         }
3636         return signal_levels;
3637 }
3638
3639 /* SNB CPU eDP voltage swing and pre-emphasis control */
3640 static uint32_t
3641 snb_cpu_edp_signal_levels(uint8_t train_set)
3642 {
3643         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3644                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3645         switch (signal_levels) {
3646         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3647         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3648                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3649         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3650                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3651         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3652         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3653                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3654         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3655         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3656                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3657         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3658         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3659                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3660         default:
3661                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3662                               "0x%x\n", signal_levels);
3663                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3664         }
3665 }
3666
3667 /* IVB CPU eDP voltage swing and pre-emphasis control */
3668 static uint32_t
3669 ivb_cpu_edp_signal_levels(uint8_t train_set)
3670 {
3671         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3672                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3673         switch (signal_levels) {
3674         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3675                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3676         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3677                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3678         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3679                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3680
3681         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3682                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3683         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3684                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3685
3686         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3687                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3688         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3689                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3690
3691         default:
3692                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3693                               "0x%x\n", signal_levels);
3694                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3695         }
3696 }
3697
3698 void
3699 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3700 {
3701         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3702         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3703         enum port port = intel_dig_port->base.port;
3704         uint32_t signal_levels, mask = 0;
3705         uint8_t train_set = intel_dp->train_set[0];
3706
3707         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3708                 signal_levels = bxt_signal_levels(intel_dp);
3709         } else if (HAS_DDI(dev_priv)) {
3710                 signal_levels = ddi_signal_levels(intel_dp);
3711                 mask = DDI_BUF_EMP_MASK;
3712         } else if (IS_CHERRYVIEW(dev_priv)) {
3713                 signal_levels = chv_signal_levels(intel_dp);
3714         } else if (IS_VALLEYVIEW(dev_priv)) {
3715                 signal_levels = vlv_signal_levels(intel_dp);
3716         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3717                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3718                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3719         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3720                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3721                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3722         } else {
3723                 signal_levels = g4x_signal_levels(train_set);
3724                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3725         }
3726
3727         if (mask)
3728                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3729
3730         DRM_DEBUG_KMS("Using vswing level %d\n",
3731                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3732         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3733                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3734                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3735
3736         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3737
3738         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3739         POSTING_READ(intel_dp->output_reg);
3740 }
3741
3742 void
3743 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3744                                        uint8_t dp_train_pat)
3745 {
3746         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3747         struct drm_i915_private *dev_priv =
3748                 to_i915(intel_dig_port->base.base.dev);
3749
3750         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3751
3752         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3753         POSTING_READ(intel_dp->output_reg);
3754 }
3755
3756 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3757 {
3758         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3759         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3760         enum port port = intel_dig_port->base.port;
3761         uint32_t val;
3762
3763         if (!HAS_DDI(dev_priv))
3764                 return;
3765
3766         val = I915_READ(DP_TP_CTL(port));
3767         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3768         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3769         I915_WRITE(DP_TP_CTL(port), val);
3770
3771         /*
3772          * On PORT_A we can have only eDP in SST mode. There the only reason
3773          * we need to set idle transmission mode is to work around a HW issue
3774          * where we enable the pipe while not in idle link-training mode.
3775          * In this case there is requirement to wait for a minimum number of
3776          * idle patterns to be sent.
3777          */
3778         if (port == PORT_A)
3779                 return;
3780
3781         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3782                                     DP_TP_STATUS_IDLE_DONE,
3783                                     DP_TP_STATUS_IDLE_DONE,
3784                                     1))
3785                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3786 }
3787
3788 static void
3789 intel_dp_link_down(struct intel_encoder *encoder,
3790                    const struct intel_crtc_state *old_crtc_state)
3791 {
3792         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3793         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3794         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3795         enum port port = encoder->port;
3796         uint32_t DP = intel_dp->DP;
3797
3798         if (WARN_ON(HAS_DDI(dev_priv)))
3799                 return;
3800
3801         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3802                 return;
3803
3804         DRM_DEBUG_KMS("\n");
3805
3806         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3807             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3808                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3809                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3810         } else {
3811                 DP &= ~DP_LINK_TRAIN_MASK;
3812                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3813         }
3814         I915_WRITE(intel_dp->output_reg, DP);
3815         POSTING_READ(intel_dp->output_reg);
3816
3817         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3818         I915_WRITE(intel_dp->output_reg, DP);
3819         POSTING_READ(intel_dp->output_reg);
3820
3821         /*
3822          * HW workaround for IBX, we need to move the port
3823          * to transcoder A after disabling it to allow the
3824          * matching HDMI port to be enabled on transcoder A.
3825          */
3826         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3827                 /*
3828                  * We get CPU/PCH FIFO underruns on the other pipe when
3829                  * doing the workaround. Sweep them under the rug.
3830                  */
3831                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3832                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3833
3834                 /* always enable with pattern 1 (as per spec) */
3835                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3836                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3837                         DP_LINK_TRAIN_PAT_1;
3838                 I915_WRITE(intel_dp->output_reg, DP);
3839                 POSTING_READ(intel_dp->output_reg);
3840
3841                 DP &= ~DP_PORT_EN;
3842                 I915_WRITE(intel_dp->output_reg, DP);
3843                 POSTING_READ(intel_dp->output_reg);
3844
3845                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3846                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3847                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3848         }
3849
3850         msleep(intel_dp->panel_power_down_delay);
3851
3852         intel_dp->DP = DP;
3853
3854         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3855                 pps_lock(intel_dp);
3856                 intel_dp->active_pipe = INVALID_PIPE;
3857                 pps_unlock(intel_dp);
3858         }
3859 }
3860
3861 bool
3862 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3863 {
3864         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3865                              sizeof(intel_dp->dpcd)) < 0)
3866                 return false; /* aux transfer failed */
3867
3868         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3869
3870         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3871 }
3872
3873 static bool
3874 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3875 {
3876         struct drm_i915_private *dev_priv =
3877                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3878
3879         /* this function is meant to be called only once */
3880         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3881
3882         if (!intel_dp_read_dpcd(intel_dp))
3883                 return false;
3884
3885         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3886                          drm_dp_is_branch(intel_dp->dpcd));
3887
3888         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3889                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3890                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3891
3892         /*
3893          * Read the eDP display control registers.
3894          *
3895          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3896          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3897          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3898          * method). The display control registers should read zero if they're
3899          * not supported anyway.
3900          */
3901         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3902                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3903                              sizeof(intel_dp->edp_dpcd))
3904                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3905                               intel_dp->edp_dpcd);
3906
3907         /*
3908          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3909          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3910          */
3911         intel_psr_init_dpcd(intel_dp);
3912
3913         /* Read the eDP 1.4+ supported link rates. */
3914         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3915                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3916                 int i;
3917
3918                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3919                                 sink_rates, sizeof(sink_rates));
3920
3921                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3922                         int val = le16_to_cpu(sink_rates[i]);
3923
3924                         if (val == 0)
3925                                 break;
3926
3927                         /* Value read multiplied by 200kHz gives the per-lane
3928                          * link rate in kHz. The source rates are, however,
3929                          * stored in terms of LS_Clk kHz. The full conversion
3930                          * back to symbols is
3931                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3932                          */
3933                         intel_dp->sink_rates[i] = (val * 200) / 10;
3934                 }
3935                 intel_dp->num_sink_rates = i;
3936         }
3937
3938         /*
3939          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3940          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3941          */
3942         if (intel_dp->num_sink_rates)
3943                 intel_dp->use_rate_select = true;
3944         else
3945                 intel_dp_set_sink_rates(intel_dp);
3946
3947         intel_dp_set_common_rates(intel_dp);
3948
3949         return true;
3950 }
3951
3952
3953 static bool
3954 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3955 {
3956         u8 sink_count;
3957
3958         if (!intel_dp_read_dpcd(intel_dp))
3959                 return false;
3960
3961         /* Don't clobber cached eDP rates. */
3962         if (!intel_dp_is_edp(intel_dp)) {
3963                 intel_dp_set_sink_rates(intel_dp);
3964                 intel_dp_set_common_rates(intel_dp);
3965         }
3966
3967         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3968                 return false;
3969
3970         /*
3971          * Sink count can change between short pulse hpd hence
3972          * a member variable in intel_dp will track any changes
3973          * between short pulse interrupts.
3974          */
3975         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3976
3977         /*
3978          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3979          * a dongle is present but no display. Unless we require to know
3980          * if a dongle is present or not, we don't need to update
3981          * downstream port information. So, an early return here saves
3982          * time from performing other operations which are not required.
3983          */
3984         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3985                 return false;
3986
3987         if (!drm_dp_is_branch(intel_dp->dpcd))
3988                 return true; /* native DP sink */
3989
3990         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3991                 return true; /* no per-port downstream info */
3992
3993         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3994                              intel_dp->downstream_ports,
3995                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3996                 return false; /* downstream port status fetch failed */
3997
3998         return true;
3999 }
4000
4001 static bool
4002 intel_dp_can_mst(struct intel_dp *intel_dp)
4003 {
4004         u8 mstm_cap;
4005
4006         if (!i915_modparams.enable_dp_mst)
4007                 return false;
4008
4009         if (!intel_dp->can_mst)
4010                 return false;
4011
4012         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4013                 return false;
4014
4015         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4016                 return false;
4017
4018         return mstm_cap & DP_MST_CAP;
4019 }
4020
4021 static void
4022 intel_dp_configure_mst(struct intel_dp *intel_dp)
4023 {
4024         if (!i915_modparams.enable_dp_mst)
4025                 return;
4026
4027         if (!intel_dp->can_mst)
4028                 return;
4029
4030         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
4031
4032         if (intel_dp->is_mst)
4033                 DRM_DEBUG_KMS("Sink is MST capable\n");
4034         else
4035                 DRM_DEBUG_KMS("Sink is not MST capable\n");
4036
4037         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4038                                         intel_dp->is_mst);
4039 }
4040
4041 static bool
4042 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4043 {
4044         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4045                                  sink_irq_vector) == 1;
4046 }
4047
4048 static bool
4049 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4050 {
4051         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4052                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4053                 DP_DPRX_ESI_LEN;
4054 }
4055
4056 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4057 {
4058         int status = 0;
4059         int test_link_rate;
4060         uint8_t test_lane_count, test_link_bw;
4061         /* (DP CTS 1.2)
4062          * 4.3.1.11
4063          */
4064         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4065         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4066                                    &test_lane_count);
4067
4068         if (status <= 0) {
4069                 DRM_DEBUG_KMS("Lane count read failed\n");
4070                 return DP_TEST_NAK;
4071         }
4072         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4073
4074         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4075                                    &test_link_bw);
4076         if (status <= 0) {
4077                 DRM_DEBUG_KMS("Link Rate read failed\n");
4078                 return DP_TEST_NAK;
4079         }
4080         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4081
4082         /* Validate the requested link rate and lane count */
4083         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4084                                         test_lane_count))
4085                 return DP_TEST_NAK;
4086
4087         intel_dp->compliance.test_lane_count = test_lane_count;
4088         intel_dp->compliance.test_link_rate = test_link_rate;
4089
4090         return DP_TEST_ACK;
4091 }
4092
4093 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4094 {
4095         uint8_t test_pattern;
4096         uint8_t test_misc;
4097         __be16 h_width, v_height;
4098         int status = 0;
4099
4100         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4101         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4102                                    &test_pattern);
4103         if (status <= 0) {
4104                 DRM_DEBUG_KMS("Test pattern read failed\n");
4105                 return DP_TEST_NAK;
4106         }
4107         if (test_pattern != DP_COLOR_RAMP)
4108                 return DP_TEST_NAK;
4109
4110         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4111                                   &h_width, 2);
4112         if (status <= 0) {
4113                 DRM_DEBUG_KMS("H Width read failed\n");
4114                 return DP_TEST_NAK;
4115         }
4116
4117         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4118                                   &v_height, 2);
4119         if (status <= 0) {
4120                 DRM_DEBUG_KMS("V Height read failed\n");
4121                 return DP_TEST_NAK;
4122         }
4123
4124         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4125                                    &test_misc);
4126         if (status <= 0) {
4127                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4128                 return DP_TEST_NAK;
4129         }
4130         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4131                 return DP_TEST_NAK;
4132         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4133                 return DP_TEST_NAK;
4134         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4135         case DP_TEST_BIT_DEPTH_6:
4136                 intel_dp->compliance.test_data.bpc = 6;
4137                 break;
4138         case DP_TEST_BIT_DEPTH_8:
4139                 intel_dp->compliance.test_data.bpc = 8;
4140                 break;
4141         default:
4142                 return DP_TEST_NAK;
4143         }
4144
4145         intel_dp->compliance.test_data.video_pattern = test_pattern;
4146         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4147         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4148         /* Set test active flag here so userspace doesn't interrupt things */
4149         intel_dp->compliance.test_active = 1;
4150
4151         return DP_TEST_ACK;
4152 }
4153
4154 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4155 {
4156         uint8_t test_result = DP_TEST_ACK;
4157         struct intel_connector *intel_connector = intel_dp->attached_connector;
4158         struct drm_connector *connector = &intel_connector->base;
4159
4160         if (intel_connector->detect_edid == NULL ||
4161             connector->edid_corrupt ||
4162             intel_dp->aux.i2c_defer_count > 6) {
4163                 /* Check EDID read for NACKs, DEFERs and corruption
4164                  * (DP CTS 1.2 Core r1.1)
4165                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4166                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4167                  *    4.2.2.6 : EDID corruption detected
4168                  * Use failsafe mode for all cases
4169                  */
4170                 if (intel_dp->aux.i2c_nack_count > 0 ||
4171                         intel_dp->aux.i2c_defer_count > 0)
4172                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4173                                       intel_dp->aux.i2c_nack_count,
4174                                       intel_dp->aux.i2c_defer_count);
4175                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4176         } else {
4177                 struct edid *block = intel_connector->detect_edid;
4178
4179                 /* We have to write the checksum
4180                  * of the last block read
4181                  */
4182                 block += intel_connector->detect_edid->extensions;
4183
4184                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4185                                        block->checksum) <= 0)
4186                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4187
4188                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4189                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4190         }
4191
4192         /* Set test active flag here so userspace doesn't interrupt things */
4193         intel_dp->compliance.test_active = 1;
4194
4195         return test_result;
4196 }
4197
4198 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4199 {
4200         uint8_t test_result = DP_TEST_NAK;
4201         return test_result;
4202 }
4203
4204 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4205 {
4206         uint8_t response = DP_TEST_NAK;
4207         uint8_t request = 0;
4208         int status;
4209
4210         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4211         if (status <= 0) {
4212                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4213                 goto update_status;
4214         }
4215
4216         switch (request) {
4217         case DP_TEST_LINK_TRAINING:
4218                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4219                 response = intel_dp_autotest_link_training(intel_dp);
4220                 break;
4221         case DP_TEST_LINK_VIDEO_PATTERN:
4222                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4223                 response = intel_dp_autotest_video_pattern(intel_dp);
4224                 break;
4225         case DP_TEST_LINK_EDID_READ:
4226                 DRM_DEBUG_KMS("EDID test requested\n");
4227                 response = intel_dp_autotest_edid(intel_dp);
4228                 break;
4229         case DP_TEST_LINK_PHY_TEST_PATTERN:
4230                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4231                 response = intel_dp_autotest_phy_pattern(intel_dp);
4232                 break;
4233         default:
4234                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4235                 break;
4236         }
4237
4238         if (response & DP_TEST_ACK)
4239                 intel_dp->compliance.test_type = request;
4240
4241 update_status:
4242         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4243         if (status <= 0)
4244                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4245 }
4246
4247 static int
4248 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4249 {
4250         bool bret;
4251
4252         if (intel_dp->is_mst) {
4253                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4254                 int ret = 0;
4255                 int retry;
4256                 bool handled;
4257
4258                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4259                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4260 go_again:
4261                 if (bret == true) {
4262
4263                         /* check link status - esi[10] = 0x200c */
4264                         if (intel_dp->active_mst_links > 0 &&
4265                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4266                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4267                                 intel_dp_start_link_train(intel_dp);
4268                                 intel_dp_stop_link_train(intel_dp);
4269                         }
4270
4271                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4272                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4273
4274                         if (handled) {
4275                                 for (retry = 0; retry < 3; retry++) {
4276                                         int wret;
4277                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4278                                                                  DP_SINK_COUNT_ESI+1,
4279                                                                  &esi[1], 3);
4280                                         if (wret == 3) {
4281                                                 break;
4282                                         }
4283                                 }
4284
4285                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4286                                 if (bret == true) {
4287                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4288                                         goto go_again;
4289                                 }
4290                         } else
4291                                 ret = 0;
4292
4293                         return ret;
4294                 } else {
4295                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4296                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4297                         intel_dp->is_mst = false;
4298                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4299                         /* send a hotplug event */
4300                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4301                 }
4302         }
4303         return -EINVAL;
4304 }
4305
4306 static bool
4307 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4308 {
4309         u8 link_status[DP_LINK_STATUS_SIZE];
4310
4311         if (!intel_dp->link_trained)
4312                 return false;
4313
4314         if (!intel_dp_get_link_status(intel_dp, link_status))
4315                 return false;
4316
4317         /*
4318          * Validate the cached values of intel_dp->link_rate and
4319          * intel_dp->lane_count before attempting to retrain.
4320          */
4321         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4322                                         intel_dp->lane_count))
4323                 return false;
4324
4325         /* Retrain if Channel EQ or CR not ok */
4326         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4327 }
4328
4329 int intel_dp_retrain_link(struct intel_encoder *encoder,
4330                           struct drm_modeset_acquire_ctx *ctx)
4331 {
4332         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4333         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4334         struct intel_connector *connector = intel_dp->attached_connector;
4335         struct drm_connector_state *conn_state;
4336         struct intel_crtc_state *crtc_state;
4337         struct intel_crtc *crtc;
4338         int ret;
4339
4340         /* FIXME handle the MST connectors as well */
4341
4342         if (!connector || connector->base.status != connector_status_connected)
4343                 return 0;
4344
4345         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4346                                ctx);
4347         if (ret)
4348                 return ret;
4349
4350         conn_state = connector->base.state;
4351
4352         crtc = to_intel_crtc(conn_state->crtc);
4353         if (!crtc)
4354                 return 0;
4355
4356         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4357         if (ret)
4358                 return ret;
4359
4360         crtc_state = to_intel_crtc_state(crtc->base.state);
4361
4362         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4363
4364         if (!crtc_state->base.active)
4365                 return 0;
4366
4367         if (conn_state->commit &&
4368             !try_wait_for_completion(&conn_state->commit->hw_done))
4369                 return 0;
4370
4371         if (!intel_dp_needs_link_retrain(intel_dp))
4372                 return 0;
4373
4374         /* Suppress underruns caused by re-training */
4375         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4376         if (crtc->config->has_pch_encoder)
4377                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4378                                                       intel_crtc_pch_transcoder(crtc), false);
4379
4380         intel_dp_start_link_train(intel_dp);
4381         intel_dp_stop_link_train(intel_dp);
4382
4383         /* Keep underrun reporting disabled until things are stable */
4384         intel_wait_for_vblank(dev_priv, crtc->pipe);
4385
4386         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4387         if (crtc->config->has_pch_encoder)
4388                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4389                                                       intel_crtc_pch_transcoder(crtc), true);
4390
4391         return 0;
4392 }
4393
4394 /*
4395  * If display is now connected check links status,
4396  * there has been known issues of link loss triggering
4397  * long pulse.
4398  *
4399  * Some sinks (eg. ASUS PB287Q) seem to perform some
4400  * weird HPD ping pong during modesets. So we can apparently
4401  * end up with HPD going low during a modeset, and then
4402  * going back up soon after. And once that happens we must
4403  * retrain the link to get a picture. That's in case no
4404  * userspace component reacted to intermittent HPD dip.
4405  */
4406 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4407                              struct intel_connector *connector)
4408 {
4409         struct drm_modeset_acquire_ctx ctx;
4410         bool changed;
4411         int ret;
4412
4413         changed = intel_encoder_hotplug(encoder, connector);
4414
4415         drm_modeset_acquire_init(&ctx, 0);
4416
4417         for (;;) {
4418                 ret = intel_dp_retrain_link(encoder, &ctx);
4419
4420                 if (ret == -EDEADLK) {
4421                         drm_modeset_backoff(&ctx);
4422                         continue;
4423                 }
4424
4425                 break;
4426         }
4427
4428         drm_modeset_drop_locks(&ctx);
4429         drm_modeset_acquire_fini(&ctx);
4430         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4431
4432         return changed;
4433 }
4434
4435 /*
4436  * According to DP spec
4437  * 5.1.2:
4438  *  1. Read DPCD
4439  *  2. Configure link according to Receiver Capabilities
4440  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4441  *  4. Check link status on receipt of hot-plug interrupt
4442  *
4443  * intel_dp_short_pulse -  handles short pulse interrupts
4444  * when full detection is not required.
4445  * Returns %true if short pulse is handled and full detection
4446  * is NOT required and %false otherwise.
4447  */
4448 static bool
4449 intel_dp_short_pulse(struct intel_dp *intel_dp)
4450 {
4451         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4452         u8 sink_irq_vector = 0;
4453         u8 old_sink_count = intel_dp->sink_count;
4454         bool ret;
4455
4456         /*
4457          * Clearing compliance test variables to allow capturing
4458          * of values for next automated test request.
4459          */
4460         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4461
4462         /*
4463          * Now read the DPCD to see if it's actually running
4464          * If the current value of sink count doesn't match with
4465          * the value that was stored earlier or dpcd read failed
4466          * we need to do full detection
4467          */
4468         ret = intel_dp_get_dpcd(intel_dp);
4469
4470         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4471                 /* No need to proceed if we are going to do full detect */
4472                 return false;
4473         }
4474
4475         /* Try to read the source of the interrupt */
4476         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4477             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4478             sink_irq_vector != 0) {
4479                 /* Clear interrupt source */
4480                 drm_dp_dpcd_writeb(&intel_dp->aux,
4481                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4482                                    sink_irq_vector);
4483
4484                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4485                         intel_dp_handle_test_request(intel_dp);
4486                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4487                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4488         }
4489
4490         /* Handle CEC interrupts, if any */
4491         drm_dp_cec_irq(&intel_dp->aux);
4492
4493         /* defer to the hotplug work for link retraining if needed */
4494         if (intel_dp_needs_link_retrain(intel_dp))
4495                 return false;
4496
4497         intel_psr_short_pulse(intel_dp);
4498
4499         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4500                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4501                 /* Send a Hotplug Uevent to userspace to start modeset */
4502                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4503         }
4504
4505         return true;
4506 }
4507
4508 /* XXX this is probably wrong for multiple downstream ports */
4509 static enum drm_connector_status
4510 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4511 {
4512         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4513         uint8_t *dpcd = intel_dp->dpcd;
4514         uint8_t type;
4515
4516         if (lspcon->active)
4517                 lspcon_resume(lspcon);
4518
4519         if (!intel_dp_get_dpcd(intel_dp))
4520                 return connector_status_disconnected;
4521
4522         if (intel_dp_is_edp(intel_dp))
4523                 return connector_status_connected;
4524
4525         /* if there's no downstream port, we're done */
4526         if (!drm_dp_is_branch(dpcd))
4527                 return connector_status_connected;
4528
4529         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4530         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4531             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4532
4533                 return intel_dp->sink_count ?
4534                 connector_status_connected : connector_status_disconnected;
4535         }
4536
4537         if (intel_dp_can_mst(intel_dp))
4538                 return connector_status_connected;
4539
4540         /* If no HPD, poke DDC gently */
4541         if (drm_probe_ddc(&intel_dp->aux.ddc))
4542                 return connector_status_connected;
4543
4544         /* Well we tried, say unknown for unreliable port types */
4545         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4546                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4547                 if (type == DP_DS_PORT_TYPE_VGA ||
4548                     type == DP_DS_PORT_TYPE_NON_EDID)
4549                         return connector_status_unknown;
4550         } else {
4551                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4552                         DP_DWN_STRM_PORT_TYPE_MASK;
4553                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4554                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4555                         return connector_status_unknown;
4556         }
4557
4558         /* Anything else is out of spec, warn and ignore */
4559         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4560         return connector_status_disconnected;
4561 }
4562
4563 static enum drm_connector_status
4564 edp_detect(struct intel_dp *intel_dp)
4565 {
4566         return connector_status_connected;
4567 }
4568
4569 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4570 {
4571         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4572         u32 bit;
4573
4574         switch (encoder->hpd_pin) {
4575         case HPD_PORT_B:
4576                 bit = SDE_PORTB_HOTPLUG;
4577                 break;
4578         case HPD_PORT_C:
4579                 bit = SDE_PORTC_HOTPLUG;
4580                 break;
4581         case HPD_PORT_D:
4582                 bit = SDE_PORTD_HOTPLUG;
4583                 break;
4584         default:
4585                 MISSING_CASE(encoder->hpd_pin);
4586                 return false;
4587         }
4588
4589         return I915_READ(SDEISR) & bit;
4590 }
4591
4592 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4593 {
4594         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4595         u32 bit;
4596
4597         switch (encoder->hpd_pin) {
4598         case HPD_PORT_B:
4599                 bit = SDE_PORTB_HOTPLUG_CPT;
4600                 break;
4601         case HPD_PORT_C:
4602                 bit = SDE_PORTC_HOTPLUG_CPT;
4603                 break;
4604         case HPD_PORT_D:
4605                 bit = SDE_PORTD_HOTPLUG_CPT;
4606                 break;
4607         default:
4608                 MISSING_CASE(encoder->hpd_pin);
4609                 return false;
4610         }
4611
4612         return I915_READ(SDEISR) & bit;
4613 }
4614
4615 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4616 {
4617         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4618         u32 bit;
4619
4620         switch (encoder->hpd_pin) {
4621         case HPD_PORT_A:
4622                 bit = SDE_PORTA_HOTPLUG_SPT;
4623                 break;
4624         case HPD_PORT_E:
4625                 bit = SDE_PORTE_HOTPLUG_SPT;
4626                 break;
4627         default:
4628                 return cpt_digital_port_connected(encoder);
4629         }
4630
4631         return I915_READ(SDEISR) & bit;
4632 }
4633
4634 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4635 {
4636         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4637         u32 bit;
4638
4639         switch (encoder->hpd_pin) {
4640         case HPD_PORT_B:
4641                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4642                 break;
4643         case HPD_PORT_C:
4644                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4645                 break;
4646         case HPD_PORT_D:
4647                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4648                 break;
4649         default:
4650                 MISSING_CASE(encoder->hpd_pin);
4651                 return false;
4652         }
4653
4654         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4655 }
4656
4657 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4658 {
4659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4660         u32 bit;
4661
4662         switch (encoder->hpd_pin) {
4663         case HPD_PORT_B:
4664                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4665                 break;
4666         case HPD_PORT_C:
4667                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4668                 break;
4669         case HPD_PORT_D:
4670                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4671                 break;
4672         default:
4673                 MISSING_CASE(encoder->hpd_pin);
4674                 return false;
4675         }
4676
4677         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4678 }
4679
4680 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4681 {
4682         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4683
4684         if (encoder->hpd_pin == HPD_PORT_A)
4685                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4686         else
4687                 return ibx_digital_port_connected(encoder);
4688 }
4689
4690 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4691 {
4692         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4693
4694         if (encoder->hpd_pin == HPD_PORT_A)
4695                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4696         else
4697                 return cpt_digital_port_connected(encoder);
4698 }
4699
4700 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4701 {
4702         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4703
4704         if (encoder->hpd_pin == HPD_PORT_A)
4705                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4706         else
4707                 return cpt_digital_port_connected(encoder);
4708 }
4709
4710 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4711 {
4712         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4713
4714         if (encoder->hpd_pin == HPD_PORT_A)
4715                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4716         else
4717                 return cpt_digital_port_connected(encoder);
4718 }
4719
4720 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4721 {
4722         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4723         u32 bit;
4724
4725         switch (encoder->hpd_pin) {
4726         case HPD_PORT_A:
4727                 bit = BXT_DE_PORT_HP_DDIA;
4728                 break;
4729         case HPD_PORT_B:
4730                 bit = BXT_DE_PORT_HP_DDIB;
4731                 break;
4732         case HPD_PORT_C:
4733                 bit = BXT_DE_PORT_HP_DDIC;
4734                 break;
4735         default:
4736                 MISSING_CASE(encoder->hpd_pin);
4737                 return false;
4738         }
4739
4740         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4741 }
4742
4743 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
4744                                      struct intel_digital_port *intel_dig_port)
4745 {
4746         enum port port = intel_dig_port->base.port;
4747
4748         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
4749 }
4750
4751 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
4752                                     struct intel_digital_port *intel_dig_port,
4753                                     bool is_legacy, bool is_typec, bool is_tbt)
4754 {
4755         enum port port = intel_dig_port->base.port;
4756         enum tc_port_type old_type = intel_dig_port->tc_type;
4757         const char *type_str;
4758
4759         WARN_ON(is_legacy + is_typec + is_tbt != 1);
4760
4761         if (is_legacy) {
4762                 intel_dig_port->tc_type = TC_PORT_LEGACY;
4763                 type_str = "legacy";
4764         } else if (is_typec) {
4765                 intel_dig_port->tc_type = TC_PORT_TYPEC;
4766                 type_str = "typec";
4767         } else if (is_tbt) {
4768                 intel_dig_port->tc_type = TC_PORT_TBT;
4769                 type_str = "tbt";
4770         } else {
4771                 return;
4772         }
4773
4774         /* Types are not supposed to be changed at runtime. */
4775         WARN_ON(old_type != TC_PORT_UNKNOWN &&
4776                 old_type != intel_dig_port->tc_type);
4777
4778         if (old_type != intel_dig_port->tc_type)
4779                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
4780                               type_str);
4781 }
4782
4783 /*
4784  * This function implements the first part of the Connect Flow described by our
4785  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
4786  * lanes, EDID, etc) is done as needed in the typical places.
4787  *
4788  * Unlike the other ports, type-C ports are not available to use as soon as we
4789  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
4790  * display, USB, etc. As a result, handshaking through FIA is required around
4791  * connect and disconnect to cleanly transfer ownership with the controller and
4792  * set the type-C power state.
4793  *
4794  * We could opt to only do the connect flow when we actually try to use the AUX
4795  * channels or do a modeset, then immediately run the disconnect flow after
4796  * usage, but there are some implications on this for a dynamic environment:
4797  * things may go away or change behind our backs. So for now our driver is
4798  * always trying to acquire ownership of the controller as soon as it gets an
4799  * interrupt (or polls state and sees a port is connected) and only gives it
4800  * back when it sees a disconnect. Implementation of a more fine-grained model
4801  * will require a lot of coordination with user space and thorough testing for
4802  * the extra possible cases.
4803  */
4804 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
4805                                struct intel_digital_port *dig_port)
4806 {
4807         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4808         u32 val;
4809
4810         if (dig_port->tc_type != TC_PORT_LEGACY &&
4811             dig_port->tc_type != TC_PORT_TYPEC)
4812                 return true;
4813
4814         val = I915_READ(PORT_TX_DFLEXDPPMS);
4815         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
4816                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
4817                 return false;
4818         }
4819
4820         /*
4821          * This function may be called many times in a row without an HPD event
4822          * in between, so try to avoid the write when we can.
4823          */
4824         val = I915_READ(PORT_TX_DFLEXDPCSSS);
4825         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
4826                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4827                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4828         }
4829
4830         /*
4831          * Now we have to re-check the live state, in case the port recently
4832          * became disconnected. Not necessary for legacy mode.
4833          */
4834         if (dig_port->tc_type == TC_PORT_TYPEC &&
4835             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
4836                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
4837                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
4838                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4839                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4840                 return false;
4841         }
4842
4843         return true;
4844 }
4845
4846 /*
4847  * See the comment at the connect function. This implements the Disconnect
4848  * Flow.
4849  */
4850 static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
4851                                   struct intel_digital_port *dig_port)
4852 {
4853         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4854         u32 val;
4855
4856         if (dig_port->tc_type != TC_PORT_LEGACY &&
4857             dig_port->tc_type != TC_PORT_TYPEC)
4858                 return;
4859
4860         /*
4861          * This function may be called many times in a row without an HPD event
4862          * in between, so try to avoid the write when we can.
4863          */
4864         val = I915_READ(PORT_TX_DFLEXDPCSSS);
4865         if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
4866                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4867                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4868         }
4869 }
4870
4871 /*
4872  * The type-C ports are different because even when they are connected, they may
4873  * not be available/usable by the graphics driver: see the comment on
4874  * icl_tc_phy_connect(). So in our driver instead of adding the additional
4875  * concept of "usable" and make everything check for "connected and usable" we
4876  * define a port as "connected" when it is not only connected, but also when it
4877  * is usable by the rest of the driver. That maintains the old assumption that
4878  * connected ports are usable, and avoids exposing to the users objects they
4879  * can't really use.
4880  */
4881 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
4882                                   struct intel_digital_port *intel_dig_port)
4883 {
4884         enum port port = intel_dig_port->base.port;
4885         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4886         bool is_legacy, is_typec, is_tbt;
4887         u32 dpsp;
4888
4889         is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
4890
4891         /*
4892          * The spec says we shouldn't be using the ISR bits for detecting
4893          * between TC and TBT. We should use DFLEXDPSP.
4894          */
4895         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
4896         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
4897         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
4898
4899         if (!is_legacy && !is_typec && !is_tbt) {
4900                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
4901                 return false;
4902         }
4903
4904         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
4905                                 is_tbt);
4906
4907         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
4908                 return false;
4909
4910         return true;
4911 }
4912
4913 static bool icl_digital_port_connected(struct intel_encoder *encoder)
4914 {
4915         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4916         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4917
4918         switch (encoder->hpd_pin) {
4919         case HPD_PORT_A:
4920         case HPD_PORT_B:
4921                 return icl_combo_port_connected(dev_priv, dig_port);
4922         case HPD_PORT_C:
4923         case HPD_PORT_D:
4924         case HPD_PORT_E:
4925         case HPD_PORT_F:
4926                 return icl_tc_port_connected(dev_priv, dig_port);
4927         default:
4928                 MISSING_CASE(encoder->hpd_pin);
4929                 return false;
4930         }
4931 }
4932
4933 /*
4934  * intel_digital_port_connected - is the specified port connected?
4935  * @encoder: intel_encoder
4936  *
4937  * In cases where there's a connector physically connected but it can't be used
4938  * by our hardware we also return false, since the rest of the driver should
4939  * pretty much treat the port as disconnected. This is relevant for type-C
4940  * (starting on ICL) where there's ownership involved.
4941  *
4942  * Return %true if port is connected, %false otherwise.
4943  */
4944 bool intel_digital_port_connected(struct intel_encoder *encoder)
4945 {
4946         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4947
4948         if (HAS_GMCH_DISPLAY(dev_priv)) {
4949                 if (IS_GM45(dev_priv))
4950                         return gm45_digital_port_connected(encoder);
4951                 else
4952                         return g4x_digital_port_connected(encoder);
4953         }
4954
4955         if (IS_GEN5(dev_priv))
4956                 return ilk_digital_port_connected(encoder);
4957         else if (IS_GEN6(dev_priv))
4958                 return snb_digital_port_connected(encoder);
4959         else if (IS_GEN7(dev_priv))
4960                 return ivb_digital_port_connected(encoder);
4961         else if (IS_GEN8(dev_priv))
4962                 return bdw_digital_port_connected(encoder);
4963         else if (IS_GEN9_LP(dev_priv))
4964                 return bxt_digital_port_connected(encoder);
4965         else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
4966                 return spt_digital_port_connected(encoder);
4967         else
4968                 return icl_digital_port_connected(encoder);
4969 }
4970
4971 static struct edid *
4972 intel_dp_get_edid(struct intel_dp *intel_dp)
4973 {
4974         struct intel_connector *intel_connector = intel_dp->attached_connector;
4975
4976         /* use cached edid if we have one */
4977         if (intel_connector->edid) {
4978                 /* invalid edid */
4979                 if (IS_ERR(intel_connector->edid))
4980                         return NULL;
4981
4982                 return drm_edid_duplicate(intel_connector->edid);
4983         } else
4984                 return drm_get_edid(&intel_connector->base,
4985                                     &intel_dp->aux.ddc);
4986 }
4987
4988 static void
4989 intel_dp_set_edid(struct intel_dp *intel_dp)
4990 {
4991         struct intel_connector *intel_connector = intel_dp->attached_connector;
4992         struct edid *edid;
4993
4994         intel_dp_unset_edid(intel_dp);
4995         edid = intel_dp_get_edid(intel_dp);
4996         intel_connector->detect_edid = edid;
4997
4998         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4999         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5000 }
5001
5002 static void
5003 intel_dp_unset_edid(struct intel_dp *intel_dp)
5004 {
5005         struct intel_connector *intel_connector = intel_dp->attached_connector;
5006
5007         drm_dp_cec_unset_edid(&intel_dp->aux);
5008         kfree(intel_connector->detect_edid);
5009         intel_connector->detect_edid = NULL;
5010
5011         intel_dp->has_audio = false;
5012 }
5013
5014 static int
5015 intel_dp_long_pulse(struct intel_connector *connector,
5016                     struct drm_modeset_acquire_ctx *ctx)
5017 {
5018         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5019         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
5020         enum drm_connector_status status;
5021         u8 sink_irq_vector = 0;
5022
5023         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5024
5025         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5026
5027         /* Can't disconnect eDP */
5028         if (intel_dp_is_edp(intel_dp))
5029                 status = edp_detect(intel_dp);
5030         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
5031                 status = intel_dp_detect_dpcd(intel_dp);
5032         else
5033                 status = connector_status_disconnected;
5034
5035         if (status == connector_status_disconnected) {
5036                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5037
5038                 if (intel_dp->is_mst) {
5039                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5040                                       intel_dp->is_mst,
5041                                       intel_dp->mst_mgr.mst_state);
5042                         intel_dp->is_mst = false;
5043                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5044                                                         intel_dp->is_mst);
5045                 }
5046
5047                 goto out;
5048         }
5049
5050         if (intel_dp->reset_link_params) {
5051                 /* Initial max link lane count */
5052                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5053
5054                 /* Initial max link rate */
5055                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5056
5057                 intel_dp->reset_link_params = false;
5058         }
5059
5060         intel_dp_print_rates(intel_dp);
5061
5062         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5063                          drm_dp_is_branch(intel_dp->dpcd));
5064
5065         intel_dp_configure_mst(intel_dp);
5066
5067         if (intel_dp->is_mst) {
5068                 /*
5069                  * If we are in MST mode then this connector
5070                  * won't appear connected or have anything
5071                  * with EDID on it
5072                  */
5073                 status = connector_status_disconnected;
5074                 goto out;
5075         } else {
5076                 /*
5077                  * If display is now connected check links status,
5078                  * there has been known issues of link loss triggering
5079                  * long pulse.
5080                  *
5081                  * Some sinks (eg. ASUS PB287Q) seem to perform some
5082                  * weird HPD ping pong during modesets. So we can apparently
5083                  * end up with HPD going low during a modeset, and then
5084                  * going back up soon after. And once that happens we must
5085                  * retrain the link to get a picture. That's in case no
5086                  * userspace component reacted to intermittent HPD dip.
5087                  */
5088                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5089
5090                 intel_dp_retrain_link(encoder, ctx);
5091         }
5092
5093         /*
5094          * Clearing NACK and defer counts to get their exact values
5095          * while reading EDID which are required by Compliance tests
5096          * 4.2.2.4 and 4.2.2.5
5097          */
5098         intel_dp->aux.i2c_nack_count = 0;
5099         intel_dp->aux.i2c_defer_count = 0;
5100
5101         intel_dp_set_edid(intel_dp);
5102         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
5103                 status = connector_status_connected;
5104         intel_dp->detect_done = true;
5105
5106         /* Try to read the source of the interrupt */
5107         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5108             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
5109             sink_irq_vector != 0) {
5110                 /* Clear interrupt source */
5111                 drm_dp_dpcd_writeb(&intel_dp->aux,
5112                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
5113                                    sink_irq_vector);
5114
5115                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
5116                         intel_dp_handle_test_request(intel_dp);
5117                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
5118                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
5119         }
5120
5121 out:
5122         if (status != connector_status_connected && !intel_dp->is_mst)
5123                 intel_dp_unset_edid(intel_dp);
5124
5125         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5126         return status;
5127 }
5128
5129 static int
5130 intel_dp_detect(struct drm_connector *connector,
5131                 struct drm_modeset_acquire_ctx *ctx,
5132                 bool force)
5133 {
5134         struct intel_dp *intel_dp = intel_attached_dp(connector);
5135         int status = connector->status;
5136
5137         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5138                       connector->base.id, connector->name);
5139
5140         /* If full detect is not performed yet, do a full detect */
5141         if (!intel_dp->detect_done) {
5142                 struct drm_crtc *crtc;
5143                 int ret;
5144
5145                 crtc = connector->state->crtc;
5146                 if (crtc) {
5147                         ret = drm_modeset_lock(&crtc->mutex, ctx);
5148                         if (ret)
5149                                 return ret;
5150                 }
5151
5152                 status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
5153         }
5154
5155         intel_dp->detect_done = false;
5156
5157         return status;
5158 }
5159
5160 static void
5161 intel_dp_force(struct drm_connector *connector)
5162 {
5163         struct intel_dp *intel_dp = intel_attached_dp(connector);
5164         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
5165         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5166
5167         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5168                       connector->base.id, connector->name);
5169         intel_dp_unset_edid(intel_dp);
5170
5171         if (connector->status != connector_status_connected)
5172                 return;
5173
5174         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5175
5176         intel_dp_set_edid(intel_dp);
5177
5178         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5179 }
5180
5181 static int intel_dp_get_modes(struct drm_connector *connector)
5182 {
5183         struct intel_connector *intel_connector = to_intel_connector(connector);
5184         struct edid *edid;
5185
5186         edid = intel_connector->detect_edid;
5187         if (edid) {
5188                 int ret = intel_connector_update_modes(connector, edid);
5189                 if (ret)
5190                         return ret;
5191         }
5192
5193         /* if eDP has no EDID, fall back to fixed mode */
5194         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5195             intel_connector->panel.fixed_mode) {
5196                 struct drm_display_mode *mode;
5197
5198                 mode = drm_mode_duplicate(connector->dev,
5199                                           intel_connector->panel.fixed_mode);
5200                 if (mode) {
5201                         drm_mode_probed_add(connector, mode);
5202                         return 1;
5203                 }
5204         }
5205
5206         return 0;
5207 }
5208
5209 static int
5210 intel_dp_connector_register(struct drm_connector *connector)
5211 {
5212         struct intel_dp *intel_dp = intel_attached_dp(connector);
5213         struct drm_device *dev = connector->dev;
5214         int ret;
5215
5216         ret = intel_connector_register(connector);
5217         if (ret)
5218                 return ret;
5219
5220         i915_debugfs_connector_add(connector);
5221
5222         DRM_DEBUG_KMS("registering %s bus for %s\n",
5223                       intel_dp->aux.name, connector->kdev->kobj.name);
5224
5225         intel_dp->aux.dev = connector->kdev;
5226         ret = drm_dp_aux_register(&intel_dp->aux);
5227         if (!ret)
5228                 drm_dp_cec_register_connector(&intel_dp->aux,
5229                                               connector->name, dev->dev);
5230         return ret;
5231 }
5232
5233 static void
5234 intel_dp_connector_unregister(struct drm_connector *connector)
5235 {
5236         struct intel_dp *intel_dp = intel_attached_dp(connector);
5237
5238         drm_dp_cec_unregister_connector(&intel_dp->aux);
5239         drm_dp_aux_unregister(&intel_dp->aux);
5240         intel_connector_unregister(connector);
5241 }
5242
5243 static void
5244 intel_dp_connector_destroy(struct drm_connector *connector)
5245 {
5246         struct intel_connector *intel_connector = to_intel_connector(connector);
5247
5248         kfree(intel_connector->detect_edid);
5249
5250         if (!IS_ERR_OR_NULL(intel_connector->edid))
5251                 kfree(intel_connector->edid);
5252
5253         /*
5254          * Can't call intel_dp_is_edp() since the encoder may have been
5255          * destroyed already.
5256          */
5257         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5258                 intel_panel_fini(&intel_connector->panel);
5259
5260         drm_connector_cleanup(connector);
5261         kfree(connector);
5262 }
5263
5264 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5265 {
5266         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5267         struct intel_dp *intel_dp = &intel_dig_port->dp;
5268
5269         intel_dp_mst_encoder_cleanup(intel_dig_port);
5270         if (intel_dp_is_edp(intel_dp)) {
5271                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5272                 /*
5273                  * vdd might still be enabled do to the delayed vdd off.
5274                  * Make sure vdd is actually turned off here.
5275                  */
5276                 pps_lock(intel_dp);
5277                 edp_panel_vdd_off_sync(intel_dp);
5278                 pps_unlock(intel_dp);
5279
5280                 if (intel_dp->edp_notifier.notifier_call) {
5281                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5282                         intel_dp->edp_notifier.notifier_call = NULL;
5283                 }
5284         }
5285
5286         intel_dp_aux_fini(intel_dp);
5287
5288         drm_encoder_cleanup(encoder);
5289         kfree(intel_dig_port);
5290 }
5291
5292 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5293 {
5294         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5295
5296         if (!intel_dp_is_edp(intel_dp))
5297                 return;
5298
5299         /*
5300          * vdd might still be enabled do to the delayed vdd off.
5301          * Make sure vdd is actually turned off here.
5302          */
5303         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5304         pps_lock(intel_dp);
5305         edp_panel_vdd_off_sync(intel_dp);
5306         pps_unlock(intel_dp);
5307 }
5308
5309 static
5310 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5311                                 u8 *an)
5312 {
5313         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5314         static const struct drm_dp_aux_msg msg = {
5315                 .request = DP_AUX_NATIVE_WRITE,
5316                 .address = DP_AUX_HDCP_AKSV,
5317                 .size = DRM_HDCP_KSV_LEN,
5318         };
5319         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5320         ssize_t dpcd_ret;
5321         int ret;
5322
5323         /* Output An first, that's easy */
5324         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5325                                      an, DRM_HDCP_AN_LEN);
5326         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5327                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5328                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5329         }
5330
5331         /*
5332          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5333          * order to get it on the wire, we need to create the AUX header as if
5334          * we were writing the data, and then tickle the hardware to output the
5335          * data once the header is sent out.
5336          */
5337         intel_dp_aux_header(txbuf, &msg);
5338
5339         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5340                                 rxbuf, sizeof(rxbuf),
5341                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5342         if (ret < 0) {
5343                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5344                 return ret;
5345         } else if (ret == 0) {
5346                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5347                 return -EIO;
5348         }
5349
5350         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5351         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5352 }
5353
5354 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5355                                    u8 *bksv)
5356 {
5357         ssize_t ret;
5358         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5359                                DRM_HDCP_KSV_LEN);
5360         if (ret != DRM_HDCP_KSV_LEN) {
5361                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5362                 return ret >= 0 ? -EIO : ret;
5363         }
5364         return 0;
5365 }
5366
5367 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5368                                       u8 *bstatus)
5369 {
5370         ssize_t ret;
5371         /*
5372          * For some reason the HDMI and DP HDCP specs call this register
5373          * definition by different names. In the HDMI spec, it's called BSTATUS,
5374          * but in DP it's called BINFO.
5375          */
5376         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5377                                bstatus, DRM_HDCP_BSTATUS_LEN);
5378         if (ret != DRM_HDCP_BSTATUS_LEN) {
5379                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5380                 return ret >= 0 ? -EIO : ret;
5381         }
5382         return 0;
5383 }
5384
5385 static
5386 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5387                              u8 *bcaps)
5388 {
5389         ssize_t ret;
5390
5391         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5392                                bcaps, 1);
5393         if (ret != 1) {
5394                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5395                 return ret >= 0 ? -EIO : ret;
5396         }
5397
5398         return 0;
5399 }
5400
5401 static
5402 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5403                                    bool *repeater_present)
5404 {
5405         ssize_t ret;
5406         u8 bcaps;
5407
5408         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5409         if (ret)
5410                 return ret;
5411
5412         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5413         return 0;
5414 }
5415
5416 static
5417 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5418                                 u8 *ri_prime)
5419 {
5420         ssize_t ret;
5421         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5422                                ri_prime, DRM_HDCP_RI_LEN);
5423         if (ret != DRM_HDCP_RI_LEN) {
5424                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5425                 return ret >= 0 ? -EIO : ret;
5426         }
5427         return 0;
5428 }
5429
5430 static
5431 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5432                                  bool *ksv_ready)
5433 {
5434         ssize_t ret;
5435         u8 bstatus;
5436         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5437                                &bstatus, 1);
5438         if (ret != 1) {
5439                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5440                 return ret >= 0 ? -EIO : ret;
5441         }
5442         *ksv_ready = bstatus & DP_BSTATUS_READY;
5443         return 0;
5444 }
5445
5446 static
5447 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5448                                 int num_downstream, u8 *ksv_fifo)
5449 {
5450         ssize_t ret;
5451         int i;
5452
5453         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5454         for (i = 0; i < num_downstream; i += 3) {
5455                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5456                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5457                                        DP_AUX_HDCP_KSV_FIFO,
5458                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5459                                        len);
5460                 if (ret != len) {
5461                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5462                                   ret);
5463                         return ret >= 0 ? -EIO : ret;
5464                 }
5465         }
5466         return 0;
5467 }
5468
5469 static
5470 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5471                                     int i, u32 *part)
5472 {
5473         ssize_t ret;
5474
5475         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5476                 return -EINVAL;
5477
5478         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5479                                DP_AUX_HDCP_V_PRIME(i), part,
5480                                DRM_HDCP_V_PRIME_PART_LEN);
5481         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5482                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5483                 return ret >= 0 ? -EIO : ret;
5484         }
5485         return 0;
5486 }
5487
5488 static
5489 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5490                                     bool enable)
5491 {
5492         /* Not used for single stream DisplayPort setups */
5493         return 0;
5494 }
5495
5496 static
5497 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5498 {
5499         ssize_t ret;
5500         u8 bstatus;
5501
5502         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5503                                &bstatus, 1);
5504         if (ret != 1) {
5505                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5506                 return false;
5507         }
5508
5509         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5510 }
5511
5512 static
5513 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5514                           bool *hdcp_capable)
5515 {
5516         ssize_t ret;
5517         u8 bcaps;
5518
5519         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5520         if (ret)
5521                 return ret;
5522
5523         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5524         return 0;
5525 }
5526
5527 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5528         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5529         .read_bksv = intel_dp_hdcp_read_bksv,
5530         .read_bstatus = intel_dp_hdcp_read_bstatus,
5531         .repeater_present = intel_dp_hdcp_repeater_present,
5532         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5533         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5534         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5535         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5536         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5537         .check_link = intel_dp_hdcp_check_link,
5538         .hdcp_capable = intel_dp_hdcp_capable,
5539 };
5540
5541 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5542 {
5543         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5544
5545         lockdep_assert_held(&dev_priv->pps_mutex);
5546
5547         if (!edp_have_panel_vdd(intel_dp))
5548                 return;
5549
5550         /*
5551          * The VDD bit needs a power domain reference, so if the bit is
5552          * already enabled when we boot or resume, grab this reference and
5553          * schedule a vdd off, so we don't hold on to the reference
5554          * indefinitely.
5555          */
5556         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5557         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5558
5559         edp_panel_vdd_schedule_off(intel_dp);
5560 }
5561
5562 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5563 {
5564         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5565         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5566         enum pipe pipe;
5567
5568         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5569                                   encoder->port, &pipe))
5570                 return pipe;
5571
5572         return INVALID_PIPE;
5573 }
5574
5575 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5576 {
5577         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5578         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5579         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5580
5581         if (!HAS_DDI(dev_priv))
5582                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5583
5584         if (lspcon->active)
5585                 lspcon_resume(lspcon);
5586
5587         intel_dp->reset_link_params = true;
5588
5589         pps_lock(intel_dp);
5590
5591         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5592                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5593
5594         if (intel_dp_is_edp(intel_dp)) {
5595                 /* Reinit the power sequencer, in case BIOS did something with it. */
5596                 intel_dp_pps_init(intel_dp);
5597                 intel_edp_panel_vdd_sanitize(intel_dp);
5598         }
5599
5600         pps_unlock(intel_dp);
5601 }
5602
5603 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5604         .force = intel_dp_force,
5605         .fill_modes = drm_helper_probe_single_connector_modes,
5606         .atomic_get_property = intel_digital_connector_atomic_get_property,
5607         .atomic_set_property = intel_digital_connector_atomic_set_property,
5608         .late_register = intel_dp_connector_register,
5609         .early_unregister = intel_dp_connector_unregister,
5610         .destroy = intel_dp_connector_destroy,
5611         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5612         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5613 };
5614
5615 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5616         .detect_ctx = intel_dp_detect,
5617         .get_modes = intel_dp_get_modes,
5618         .mode_valid = intel_dp_mode_valid,
5619         .atomic_check = intel_digital_connector_atomic_check,
5620 };
5621
5622 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5623         .reset = intel_dp_encoder_reset,
5624         .destroy = intel_dp_encoder_destroy,
5625 };
5626
5627 enum irqreturn
5628 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5629 {
5630         struct intel_dp *intel_dp = &intel_dig_port->dp;
5631         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5632         enum irqreturn ret = IRQ_NONE;
5633
5634         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5635                 /*
5636                  * vdd off can generate a long pulse on eDP which
5637                  * would require vdd on to handle it, and thus we
5638                  * would end up in an endless cycle of
5639                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5640                  */
5641                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5642                               port_name(intel_dig_port->base.port));
5643                 return IRQ_HANDLED;
5644         }
5645
5646         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5647                       port_name(intel_dig_port->base.port),
5648                       long_hpd ? "long" : "short");
5649
5650         if (long_hpd) {
5651                 intel_dp->reset_link_params = true;
5652                 intel_dp->detect_done = false;
5653                 return IRQ_NONE;
5654         }
5655
5656         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5657
5658         if (intel_dp->is_mst) {
5659                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5660                         /*
5661                          * If we were in MST mode, and device is not
5662                          * there, get out of MST mode
5663                          */
5664                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5665                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5666                         intel_dp->is_mst = false;
5667                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5668                                                         intel_dp->is_mst);
5669                         intel_dp->detect_done = false;
5670                         goto put_power;
5671                 }
5672         }
5673
5674         if (!intel_dp->is_mst) {
5675                 bool handled;
5676
5677                 handled = intel_dp_short_pulse(intel_dp);
5678
5679                 /* Short pulse can signify loss of hdcp authentication */
5680                 intel_hdcp_check_link(intel_dp->attached_connector);
5681
5682                 if (!handled) {
5683                         intel_dp->detect_done = false;
5684                         goto put_power;
5685                 }
5686         }
5687
5688         ret = IRQ_HANDLED;
5689
5690 put_power:
5691         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5692
5693         return ret;
5694 }
5695
5696 /* check the VBT to see whether the eDP is on another port */
5697 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5698 {
5699         /*
5700          * eDP not supported on g4x. so bail out early just
5701          * for a bit extra safety in case the VBT is bonkers.
5702          */
5703         if (INTEL_GEN(dev_priv) < 5)
5704                 return false;
5705
5706         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5707                 return true;
5708
5709         return intel_bios_is_port_edp(dev_priv, port);
5710 }
5711
5712 static void
5713 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5714 {
5715         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5716         enum port port = dp_to_dig_port(intel_dp)->base.port;
5717
5718         if (!IS_G4X(dev_priv) && port != PORT_A)
5719                 intel_attach_force_audio_property(connector);
5720
5721         intel_attach_broadcast_rgb_property(connector);
5722
5723         if (intel_dp_is_edp(intel_dp)) {
5724                 u32 allowed_scalers;
5725
5726                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5727                 if (!HAS_GMCH_DISPLAY(dev_priv))
5728                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5729
5730                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5731
5732                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5733
5734         }
5735 }
5736
5737 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5738 {
5739         intel_dp->panel_power_off_time = ktime_get_boottime();
5740         intel_dp->last_power_on = jiffies;
5741         intel_dp->last_backlight_off = jiffies;
5742 }
5743
5744 static void
5745 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5746 {
5747         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5748         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5749         struct pps_registers regs;
5750
5751         intel_pps_get_registers(intel_dp, &regs);
5752
5753         /* Workaround: Need to write PP_CONTROL with the unlock key as
5754          * the very first thing. */
5755         pp_ctl = ironlake_get_pp_control(intel_dp);
5756
5757         pp_on = I915_READ(regs.pp_on);
5758         pp_off = I915_READ(regs.pp_off);
5759         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5760             !HAS_PCH_ICP(dev_priv)) {
5761                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5762                 pp_div = I915_READ(regs.pp_div);
5763         }
5764
5765         /* Pull timing values out of registers */
5766         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5767                      PANEL_POWER_UP_DELAY_SHIFT;
5768
5769         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5770                   PANEL_LIGHT_ON_DELAY_SHIFT;
5771
5772         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5773                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5774
5775         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5776                    PANEL_POWER_DOWN_DELAY_SHIFT;
5777
5778         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5779             HAS_PCH_ICP(dev_priv)) {
5780                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5781                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5782         } else {
5783                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5784                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5785         }
5786 }
5787
5788 static void
5789 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5790 {
5791         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5792                       state_name,
5793                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5794 }
5795
5796 static void
5797 intel_pps_verify_state(struct intel_dp *intel_dp)
5798 {
5799         struct edp_power_seq hw;
5800         struct edp_power_seq *sw = &intel_dp->pps_delays;
5801
5802         intel_pps_readout_hw_state(intel_dp, &hw);
5803
5804         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5805             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5806                 DRM_ERROR("PPS state mismatch\n");
5807                 intel_pps_dump_state("sw", sw);
5808                 intel_pps_dump_state("hw", &hw);
5809         }
5810 }
5811
5812 static void
5813 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5814 {
5815         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5816         struct edp_power_seq cur, vbt, spec,
5817                 *final = &intel_dp->pps_delays;
5818
5819         lockdep_assert_held(&dev_priv->pps_mutex);
5820
5821         /* already initialized? */
5822         if (final->t11_t12 != 0)
5823                 return;
5824
5825         intel_pps_readout_hw_state(intel_dp, &cur);
5826
5827         intel_pps_dump_state("cur", &cur);
5828
5829         vbt = dev_priv->vbt.edp.pps;
5830         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5831          * of 500ms appears to be too short. Ocassionally the panel
5832          * just fails to power back on. Increasing the delay to 800ms
5833          * seems sufficient to avoid this problem.
5834          */
5835         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5836                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5837                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5838                               vbt.t11_t12);
5839         }
5840         /* T11_T12 delay is special and actually in units of 100ms, but zero
5841          * based in the hw (so we need to add 100 ms). But the sw vbt
5842          * table multiplies it with 1000 to make it in units of 100usec,
5843          * too. */
5844         vbt.t11_t12 += 100 * 10;
5845
5846         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5847          * our hw here, which are all in 100usec. */
5848         spec.t1_t3 = 210 * 10;
5849         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5850         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5851         spec.t10 = 500 * 10;
5852         /* This one is special and actually in units of 100ms, but zero
5853          * based in the hw (so we need to add 100 ms). But the sw vbt
5854          * table multiplies it with 1000 to make it in units of 100usec,
5855          * too. */
5856         spec.t11_t12 = (510 + 100) * 10;
5857
5858         intel_pps_dump_state("vbt", &vbt);
5859
5860         /* Use the max of the register settings and vbt. If both are
5861          * unset, fall back to the spec limits. */
5862 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5863                                        spec.field : \
5864                                        max(cur.field, vbt.field))
5865         assign_final(t1_t3);
5866         assign_final(t8);
5867         assign_final(t9);
5868         assign_final(t10);
5869         assign_final(t11_t12);
5870 #undef assign_final
5871
5872 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5873         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5874         intel_dp->backlight_on_delay = get_delay(t8);
5875         intel_dp->backlight_off_delay = get_delay(t9);
5876         intel_dp->panel_power_down_delay = get_delay(t10);
5877         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5878 #undef get_delay
5879
5880         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5881                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5882                       intel_dp->panel_power_cycle_delay);
5883
5884         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5885                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5886
5887         /*
5888          * We override the HW backlight delays to 1 because we do manual waits
5889          * on them. For T8, even BSpec recommends doing it. For T9, if we
5890          * don't do this, we'll end up waiting for the backlight off delay
5891          * twice: once when we do the manual sleep, and once when we disable
5892          * the panel and wait for the PP_STATUS bit to become zero.
5893          */
5894         final->t8 = 1;
5895         final->t9 = 1;
5896
5897         /*
5898          * HW has only a 100msec granularity for t11_t12 so round it up
5899          * accordingly.
5900          */
5901         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5902 }
5903
5904 static void
5905 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5906                                               bool force_disable_vdd)
5907 {
5908         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5909         u32 pp_on, pp_off, pp_div, port_sel = 0;
5910         int div = dev_priv->rawclk_freq / 1000;
5911         struct pps_registers regs;
5912         enum port port = dp_to_dig_port(intel_dp)->base.port;
5913         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5914
5915         lockdep_assert_held(&dev_priv->pps_mutex);
5916
5917         intel_pps_get_registers(intel_dp, &regs);
5918
5919         /*
5920          * On some VLV machines the BIOS can leave the VDD
5921          * enabled even on power sequencers which aren't
5922          * hooked up to any port. This would mess up the
5923          * power domain tracking the first time we pick
5924          * one of these power sequencers for use since
5925          * edp_panel_vdd_on() would notice that the VDD was
5926          * already on and therefore wouldn't grab the power
5927          * domain reference. Disable VDD first to avoid this.
5928          * This also avoids spuriously turning the VDD on as
5929          * soon as the new power sequencer gets initialized.
5930          */
5931         if (force_disable_vdd) {
5932                 u32 pp = ironlake_get_pp_control(intel_dp);
5933
5934                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5935
5936                 if (pp & EDP_FORCE_VDD)
5937                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5938
5939                 pp &= ~EDP_FORCE_VDD;
5940
5941                 I915_WRITE(regs.pp_ctrl, pp);
5942         }
5943
5944         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5945                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5946         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5947                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5948         /* Compute the divisor for the pp clock, simply match the Bspec
5949          * formula. */
5950         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5951             HAS_PCH_ICP(dev_priv)) {
5952                 pp_div = I915_READ(regs.pp_ctrl);
5953                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5954                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5955                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5956         } else {
5957                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5958                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5959                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5960         }
5961
5962         /* Haswell doesn't have any port selection bits for the panel
5963          * power sequencer any more. */
5964         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5965                 port_sel = PANEL_PORT_SELECT_VLV(port);
5966         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5967                 switch (port) {
5968                 case PORT_A:
5969                         port_sel = PANEL_PORT_SELECT_DPA;
5970                         break;
5971                 case PORT_C:
5972                         port_sel = PANEL_PORT_SELECT_DPC;
5973                         break;
5974                 case PORT_D:
5975                         port_sel = PANEL_PORT_SELECT_DPD;
5976                         break;
5977                 default:
5978                         MISSING_CASE(port);
5979                         break;
5980                 }
5981         }
5982
5983         pp_on |= port_sel;
5984
5985         I915_WRITE(regs.pp_on, pp_on);
5986         I915_WRITE(regs.pp_off, pp_off);
5987         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5988             HAS_PCH_ICP(dev_priv))
5989                 I915_WRITE(regs.pp_ctrl, pp_div);
5990         else
5991                 I915_WRITE(regs.pp_div, pp_div);
5992
5993         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5994                       I915_READ(regs.pp_on),
5995                       I915_READ(regs.pp_off),
5996                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5997                        HAS_PCH_ICP(dev_priv)) ?
5998                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5999                       I915_READ(regs.pp_div));
6000 }
6001
6002 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6003 {
6004         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6005
6006         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6007                 vlv_initial_power_sequencer_setup(intel_dp);
6008         } else {
6009                 intel_dp_init_panel_power_sequencer(intel_dp);
6010                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6011         }
6012 }
6013
6014 /**
6015  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6016  * @dev_priv: i915 device
6017  * @crtc_state: a pointer to the active intel_crtc_state
6018  * @refresh_rate: RR to be programmed
6019  *
6020  * This function gets called when refresh rate (RR) has to be changed from
6021  * one frequency to another. Switches can be between high and low RR
6022  * supported by the panel or to any other RR based on media playback (in
6023  * this case, RR value needs to be passed from user space).
6024  *
6025  * The caller of this function needs to take a lock on dev_priv->drrs.
6026  */
6027 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6028                                     const struct intel_crtc_state *crtc_state,
6029                                     int refresh_rate)
6030 {
6031         struct intel_encoder *encoder;
6032         struct intel_digital_port *dig_port = NULL;
6033         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6035         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6036
6037         if (refresh_rate <= 0) {
6038                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6039                 return;
6040         }
6041
6042         if (intel_dp == NULL) {
6043                 DRM_DEBUG_KMS("DRRS not supported.\n");
6044                 return;
6045         }
6046
6047         dig_port = dp_to_dig_port(intel_dp);
6048         encoder = &dig_port->base;
6049
6050         if (!intel_crtc) {
6051                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6052                 return;
6053         }
6054
6055         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6056                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6057                 return;
6058         }
6059
6060         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6061                         refresh_rate)
6062                 index = DRRS_LOW_RR;
6063
6064         if (index == dev_priv->drrs.refresh_rate_type) {
6065                 DRM_DEBUG_KMS(
6066                         "DRRS requested for previously set RR...ignoring\n");
6067                 return;
6068         }
6069
6070         if (!crtc_state->base.active) {
6071                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6072                 return;
6073         }
6074
6075         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6076                 switch (index) {
6077                 case DRRS_HIGH_RR:
6078                         intel_dp_set_m_n(intel_crtc, M1_N1);
6079                         break;
6080                 case DRRS_LOW_RR:
6081                         intel_dp_set_m_n(intel_crtc, M2_N2);
6082                         break;
6083                 case DRRS_MAX_RR:
6084                 default:
6085                         DRM_ERROR("Unsupported refreshrate type\n");
6086                 }
6087         } else if (INTEL_GEN(dev_priv) > 6) {
6088                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6089                 u32 val;
6090
6091                 val = I915_READ(reg);
6092                 if (index > DRRS_HIGH_RR) {
6093                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6094                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6095                         else
6096                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6097                 } else {
6098                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6099                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6100                         else
6101                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6102                 }
6103                 I915_WRITE(reg, val);
6104         }
6105
6106         dev_priv->drrs.refresh_rate_type = index;
6107
6108         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6109 }
6110
6111 /**
6112  * intel_edp_drrs_enable - init drrs struct if supported
6113  * @intel_dp: DP struct
6114  * @crtc_state: A pointer to the active crtc state.
6115  *
6116  * Initializes frontbuffer_bits and drrs.dp
6117  */
6118 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6119                            const struct intel_crtc_state *crtc_state)
6120 {
6121         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6122
6123         if (!crtc_state->has_drrs) {
6124                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6125                 return;
6126         }
6127
6128         if (dev_priv->psr.enabled) {
6129                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6130                 return;
6131         }
6132
6133         mutex_lock(&dev_priv->drrs.mutex);
6134         if (WARN_ON(dev_priv->drrs.dp)) {
6135                 DRM_ERROR("DRRS already enabled\n");
6136                 goto unlock;
6137         }
6138
6139         dev_priv->drrs.busy_frontbuffer_bits = 0;
6140
6141         dev_priv->drrs.dp = intel_dp;
6142
6143 unlock:
6144         mutex_unlock(&dev_priv->drrs.mutex);
6145 }
6146
6147 /**
6148  * intel_edp_drrs_disable - Disable DRRS
6149  * @intel_dp: DP struct
6150  * @old_crtc_state: Pointer to old crtc_state.
6151  *
6152  */
6153 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6154                             const struct intel_crtc_state *old_crtc_state)
6155 {
6156         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6157
6158         if (!old_crtc_state->has_drrs)
6159                 return;
6160
6161         mutex_lock(&dev_priv->drrs.mutex);
6162         if (!dev_priv->drrs.dp) {
6163                 mutex_unlock(&dev_priv->drrs.mutex);
6164                 return;
6165         }
6166
6167         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6168                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6169                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6170
6171         dev_priv->drrs.dp = NULL;
6172         mutex_unlock(&dev_priv->drrs.mutex);
6173
6174         cancel_delayed_work_sync(&dev_priv->drrs.work);
6175 }
6176
6177 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6178 {
6179         struct drm_i915_private *dev_priv =
6180                 container_of(work, typeof(*dev_priv), drrs.work.work);
6181         struct intel_dp *intel_dp;
6182
6183         mutex_lock(&dev_priv->drrs.mutex);
6184
6185         intel_dp = dev_priv->drrs.dp;
6186
6187         if (!intel_dp)
6188                 goto unlock;
6189
6190         /*
6191          * The delayed work can race with an invalidate hence we need to
6192          * recheck.
6193          */
6194
6195         if (dev_priv->drrs.busy_frontbuffer_bits)
6196                 goto unlock;
6197
6198         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6199                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6200
6201                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6202                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6203         }
6204
6205 unlock:
6206         mutex_unlock(&dev_priv->drrs.mutex);
6207 }
6208
6209 /**
6210  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6211  * @dev_priv: i915 device
6212  * @frontbuffer_bits: frontbuffer plane tracking bits
6213  *
6214  * This function gets called everytime rendering on the given planes start.
6215  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6216  *
6217  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6218  */
6219 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6220                                unsigned int frontbuffer_bits)
6221 {
6222         struct drm_crtc *crtc;
6223         enum pipe pipe;
6224
6225         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6226                 return;
6227
6228         cancel_delayed_work(&dev_priv->drrs.work);
6229
6230         mutex_lock(&dev_priv->drrs.mutex);
6231         if (!dev_priv->drrs.dp) {
6232                 mutex_unlock(&dev_priv->drrs.mutex);
6233                 return;
6234         }
6235
6236         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6237         pipe = to_intel_crtc(crtc)->pipe;
6238
6239         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6240         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6241
6242         /* invalidate means busy screen hence upclock */
6243         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6244                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6245                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6246
6247         mutex_unlock(&dev_priv->drrs.mutex);
6248 }
6249
6250 /**
6251  * intel_edp_drrs_flush - Restart Idleness DRRS
6252  * @dev_priv: i915 device
6253  * @frontbuffer_bits: frontbuffer plane tracking bits
6254  *
6255  * This function gets called every time rendering on the given planes has
6256  * completed or flip on a crtc is completed. So DRRS should be upclocked
6257  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6258  * if no other planes are dirty.
6259  *
6260  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6261  */
6262 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6263                           unsigned int frontbuffer_bits)
6264 {
6265         struct drm_crtc *crtc;
6266         enum pipe pipe;
6267
6268         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6269                 return;
6270
6271         cancel_delayed_work(&dev_priv->drrs.work);
6272
6273         mutex_lock(&dev_priv->drrs.mutex);
6274         if (!dev_priv->drrs.dp) {
6275                 mutex_unlock(&dev_priv->drrs.mutex);
6276                 return;
6277         }
6278
6279         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6280         pipe = to_intel_crtc(crtc)->pipe;
6281
6282         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6283         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6284
6285         /* flush means busy screen hence upclock */
6286         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6287                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6288                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6289
6290         /*
6291          * flush also means no more activity hence schedule downclock, if all
6292          * other fbs are quiescent too
6293          */
6294         if (!dev_priv->drrs.busy_frontbuffer_bits)
6295                 schedule_delayed_work(&dev_priv->drrs.work,
6296                                 msecs_to_jiffies(1000));
6297         mutex_unlock(&dev_priv->drrs.mutex);
6298 }
6299
6300 /**
6301  * DOC: Display Refresh Rate Switching (DRRS)
6302  *
6303  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6304  * which enables swtching between low and high refresh rates,
6305  * dynamically, based on the usage scenario. This feature is applicable
6306  * for internal panels.
6307  *
6308  * Indication that the panel supports DRRS is given by the panel EDID, which
6309  * would list multiple refresh rates for one resolution.
6310  *
6311  * DRRS is of 2 types - static and seamless.
6312  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6313  * (may appear as a blink on screen) and is used in dock-undock scenario.
6314  * Seamless DRRS involves changing RR without any visual effect to the user
6315  * and can be used during normal system usage. This is done by programming
6316  * certain registers.
6317  *
6318  * Support for static/seamless DRRS may be indicated in the VBT based on
6319  * inputs from the panel spec.
6320  *
6321  * DRRS saves power by switching to low RR based on usage scenarios.
6322  *
6323  * The implementation is based on frontbuffer tracking implementation.  When
6324  * there is a disturbance on the screen triggered by user activity or a periodic
6325  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6326  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6327  * made.
6328  *
6329  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6330  * and intel_edp_drrs_flush() are called.
6331  *
6332  * DRRS can be further extended to support other internal panels and also
6333  * the scenario of video playback wherein RR is set based on the rate
6334  * requested by userspace.
6335  */
6336
6337 /**
6338  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6339  * @connector: eDP connector
6340  * @fixed_mode: preferred mode of panel
6341  *
6342  * This function is  called only once at driver load to initialize basic
6343  * DRRS stuff.
6344  *
6345  * Returns:
6346  * Downclock mode if panel supports it, else return NULL.
6347  * DRRS support is determined by the presence of downclock mode (apart
6348  * from VBT setting).
6349  */
6350 static struct drm_display_mode *
6351 intel_dp_drrs_init(struct intel_connector *connector,
6352                    struct drm_display_mode *fixed_mode)
6353 {
6354         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6355         struct drm_display_mode *downclock_mode = NULL;
6356
6357         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6358         mutex_init(&dev_priv->drrs.mutex);
6359
6360         if (INTEL_GEN(dev_priv) <= 6) {
6361                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6362                 return NULL;
6363         }
6364
6365         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6366                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6367                 return NULL;
6368         }
6369
6370         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6371                                                     &connector->base);
6372
6373         if (!downclock_mode) {
6374                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6375                 return NULL;
6376         }
6377
6378         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6379
6380         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6381         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6382         return downclock_mode;
6383 }
6384
6385 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6386                                      struct intel_connector *intel_connector)
6387 {
6388         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6389         struct drm_device *dev = &dev_priv->drm;
6390         struct drm_connector *connector = &intel_connector->base;
6391         struct drm_display_mode *fixed_mode = NULL;
6392         struct drm_display_mode *downclock_mode = NULL;
6393         bool has_dpcd;
6394         struct drm_display_mode *scan;
6395         struct edid *edid;
6396         enum pipe pipe = INVALID_PIPE;
6397
6398         if (!intel_dp_is_edp(intel_dp))
6399                 return true;
6400
6401         /*
6402          * On IBX/CPT we may get here with LVDS already registered. Since the
6403          * driver uses the only internal power sequencer available for both
6404          * eDP and LVDS bail out early in this case to prevent interfering
6405          * with an already powered-on LVDS power sequencer.
6406          */
6407         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6408                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6409                 DRM_INFO("LVDS was detected, not registering eDP\n");
6410
6411                 return false;
6412         }
6413
6414         pps_lock(intel_dp);
6415
6416         intel_dp_init_panel_power_timestamps(intel_dp);
6417         intel_dp_pps_init(intel_dp);
6418         intel_edp_panel_vdd_sanitize(intel_dp);
6419
6420         pps_unlock(intel_dp);
6421
6422         /* Cache DPCD and EDID for edp. */
6423         has_dpcd = intel_edp_init_dpcd(intel_dp);
6424
6425         if (!has_dpcd) {
6426                 /* if this fails, presume the device is a ghost */
6427                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6428                 goto out_vdd_off;
6429         }
6430
6431         mutex_lock(&dev->mode_config.mutex);
6432         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6433         if (edid) {
6434                 if (drm_add_edid_modes(connector, edid)) {
6435                         drm_connector_update_edid_property(connector,
6436                                                                 edid);
6437                 } else {
6438                         kfree(edid);
6439                         edid = ERR_PTR(-EINVAL);
6440                 }
6441         } else {
6442                 edid = ERR_PTR(-ENOENT);
6443         }
6444         intel_connector->edid = edid;
6445
6446         /* prefer fixed mode from EDID if available */
6447         list_for_each_entry(scan, &connector->probed_modes, head) {
6448                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6449                         fixed_mode = drm_mode_duplicate(dev, scan);
6450                         downclock_mode = intel_dp_drrs_init(
6451                                                 intel_connector, fixed_mode);
6452                         break;
6453                 }
6454         }
6455
6456         /* fallback to VBT if available for eDP */
6457         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6458                 fixed_mode = drm_mode_duplicate(dev,
6459                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6460                 if (fixed_mode) {
6461                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6462                         connector->display_info.width_mm = fixed_mode->width_mm;
6463                         connector->display_info.height_mm = fixed_mode->height_mm;
6464                 }
6465         }
6466         mutex_unlock(&dev->mode_config.mutex);
6467
6468         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6469                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6470                 register_reboot_notifier(&intel_dp->edp_notifier);
6471
6472                 /*
6473                  * Figure out the current pipe for the initial backlight setup.
6474                  * If the current pipe isn't valid, try the PPS pipe, and if that
6475                  * fails just assume pipe A.
6476                  */
6477                 pipe = vlv_active_pipe(intel_dp);
6478
6479                 if (pipe != PIPE_A && pipe != PIPE_B)
6480                         pipe = intel_dp->pps_pipe;
6481
6482                 if (pipe != PIPE_A && pipe != PIPE_B)
6483                         pipe = PIPE_A;
6484
6485                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6486                               pipe_name(pipe));
6487         }
6488
6489         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6490         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6491         intel_panel_setup_backlight(connector, pipe);
6492
6493         return true;
6494
6495 out_vdd_off:
6496         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6497         /*
6498          * vdd might still be enabled do to the delayed vdd off.
6499          * Make sure vdd is actually turned off here.
6500          */
6501         pps_lock(intel_dp);
6502         edp_panel_vdd_off_sync(intel_dp);
6503         pps_unlock(intel_dp);
6504
6505         return false;
6506 }
6507
6508 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6509 {
6510         struct intel_connector *intel_connector;
6511         struct drm_connector *connector;
6512
6513         intel_connector = container_of(work, typeof(*intel_connector),
6514                                        modeset_retry_work);
6515         connector = &intel_connector->base;
6516         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6517                       connector->name);
6518
6519         /* Grab the locks before changing connector property*/
6520         mutex_lock(&connector->dev->mode_config.mutex);
6521         /* Set connector link status to BAD and send a Uevent to notify
6522          * userspace to do a modeset.
6523          */
6524         drm_connector_set_link_status_property(connector,
6525                                                DRM_MODE_LINK_STATUS_BAD);
6526         mutex_unlock(&connector->dev->mode_config.mutex);
6527         /* Send Hotplug uevent so userspace can reprobe */
6528         drm_kms_helper_hotplug_event(connector->dev);
6529 }
6530
6531 bool
6532 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6533                         struct intel_connector *intel_connector)
6534 {
6535         struct drm_connector *connector = &intel_connector->base;
6536         struct intel_dp *intel_dp = &intel_dig_port->dp;
6537         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6538         struct drm_device *dev = intel_encoder->base.dev;
6539         struct drm_i915_private *dev_priv = to_i915(dev);
6540         enum port port = intel_encoder->port;
6541         int type;
6542
6543         /* Initialize the work for modeset in case of link train failure */
6544         INIT_WORK(&intel_connector->modeset_retry_work,
6545                   intel_dp_modeset_retry_work_fn);
6546
6547         if (WARN(intel_dig_port->max_lanes < 1,
6548                  "Not enough lanes (%d) for DP on port %c\n",
6549                  intel_dig_port->max_lanes, port_name(port)))
6550                 return false;
6551
6552         intel_dp_set_source_rates(intel_dp);
6553
6554         intel_dp->reset_link_params = true;
6555         intel_dp->pps_pipe = INVALID_PIPE;
6556         intel_dp->active_pipe = INVALID_PIPE;
6557
6558         /* intel_dp vfuncs */
6559         if (HAS_DDI(dev_priv))
6560                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6561
6562         /* Preserve the current hw state. */
6563         intel_dp->DP = I915_READ(intel_dp->output_reg);
6564         intel_dp->attached_connector = intel_connector;
6565
6566         if (intel_dp_is_port_edp(dev_priv, port))
6567                 type = DRM_MODE_CONNECTOR_eDP;
6568         else
6569                 type = DRM_MODE_CONNECTOR_DisplayPort;
6570
6571         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6572                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6573
6574         /*
6575          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6576          * for DP the encoder type can be set by the caller to
6577          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6578          */
6579         if (type == DRM_MODE_CONNECTOR_eDP)
6580                 intel_encoder->type = INTEL_OUTPUT_EDP;
6581
6582         /* eDP only on port B and/or C on vlv/chv */
6583         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6584                     intel_dp_is_edp(intel_dp) &&
6585                     port != PORT_B && port != PORT_C))
6586                 return false;
6587
6588         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6589                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6590                         port_name(port));
6591
6592         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6593         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6594
6595         if (!HAS_GMCH_DISPLAY(dev_priv))
6596                 connector->interlace_allowed = true;
6597         connector->doublescan_allowed = 0;
6598
6599         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6600
6601         intel_dp_aux_init(intel_dp);
6602
6603         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6604                           edp_panel_vdd_work);
6605
6606         intel_connector_attach_encoder(intel_connector, intel_encoder);
6607
6608         if (HAS_DDI(dev_priv))
6609                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6610         else
6611                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6612
6613         /* init MST on ports that can support it */
6614         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6615             (port == PORT_B || port == PORT_C ||
6616              port == PORT_D || port == PORT_F))
6617                 intel_dp_mst_encoder_init(intel_dig_port,
6618                                           intel_connector->base.base.id);
6619
6620         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6621                 intel_dp_aux_fini(intel_dp);
6622                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6623                 goto fail;
6624         }
6625
6626         intel_dp_add_properties(intel_dp, connector);
6627
6628         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6629                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6630                 if (ret)
6631                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6632         }
6633
6634         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6635          * 0xd.  Failure to do so will result in spurious interrupts being
6636          * generated on the port when a cable is not attached.
6637          */
6638         if (IS_G45(dev_priv)) {
6639                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6640                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6641         }
6642
6643         return true;
6644
6645 fail:
6646         drm_connector_cleanup(connector);
6647
6648         return false;
6649 }
6650
6651 bool intel_dp_init(struct drm_i915_private *dev_priv,
6652                    i915_reg_t output_reg,
6653                    enum port port)
6654 {
6655         struct intel_digital_port *intel_dig_port;
6656         struct intel_encoder *intel_encoder;
6657         struct drm_encoder *encoder;
6658         struct intel_connector *intel_connector;
6659
6660         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6661         if (!intel_dig_port)
6662                 return false;
6663
6664         intel_connector = intel_connector_alloc();
6665         if (!intel_connector)
6666                 goto err_connector_alloc;
6667
6668         intel_encoder = &intel_dig_port->base;
6669         encoder = &intel_encoder->base;
6670
6671         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6672                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6673                              "DP %c", port_name(port)))
6674                 goto err_encoder_init;
6675
6676         intel_encoder->hotplug = intel_dp_hotplug;
6677         intel_encoder->compute_config = intel_dp_compute_config;
6678         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6679         intel_encoder->get_config = intel_dp_get_config;
6680         intel_encoder->suspend = intel_dp_encoder_suspend;
6681         if (IS_CHERRYVIEW(dev_priv)) {
6682                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6683                 intel_encoder->pre_enable = chv_pre_enable_dp;
6684                 intel_encoder->enable = vlv_enable_dp;
6685                 intel_encoder->disable = vlv_disable_dp;
6686                 intel_encoder->post_disable = chv_post_disable_dp;
6687                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6688         } else if (IS_VALLEYVIEW(dev_priv)) {
6689                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6690                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6691                 intel_encoder->enable = vlv_enable_dp;
6692                 intel_encoder->disable = vlv_disable_dp;
6693                 intel_encoder->post_disable = vlv_post_disable_dp;
6694         } else {
6695                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6696                 intel_encoder->enable = g4x_enable_dp;
6697                 intel_encoder->disable = g4x_disable_dp;
6698                 intel_encoder->post_disable = g4x_post_disable_dp;
6699         }
6700
6701         intel_dig_port->dp.output_reg = output_reg;
6702         intel_dig_port->max_lanes = 4;
6703
6704         intel_encoder->type = INTEL_OUTPUT_DP;
6705         intel_encoder->power_domain = intel_port_to_power_domain(port);
6706         if (IS_CHERRYVIEW(dev_priv)) {
6707                 if (port == PORT_D)
6708                         intel_encoder->crtc_mask = 1 << 2;
6709                 else
6710                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6711         } else {
6712                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6713         }
6714         intel_encoder->cloneable = 0;
6715         intel_encoder->port = port;
6716
6717         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6718
6719         if (port != PORT_A)
6720                 intel_infoframe_init(intel_dig_port);
6721
6722         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6723                 goto err_init_connector;
6724
6725         return true;
6726
6727 err_init_connector:
6728         drm_encoder_cleanup(encoder);
6729 err_encoder_init:
6730         kfree(intel_connector);
6731 err_connector_alloc:
6732         kfree(intel_dig_port);
6733         return false;
6734 }
6735
6736 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6737 {
6738         struct intel_encoder *encoder;
6739
6740         for_each_intel_encoder(&dev_priv->drm, encoder) {
6741                 struct intel_dp *intel_dp;
6742
6743                 if (encoder->type != INTEL_OUTPUT_DDI)
6744                         continue;
6745
6746                 intel_dp = enc_to_intel_dp(&encoder->base);
6747
6748                 if (!intel_dp->can_mst)
6749                         continue;
6750
6751                 if (intel_dp->is_mst)
6752                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6753         }
6754 }
6755
6756 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6757 {
6758         struct intel_encoder *encoder;
6759
6760         for_each_intel_encoder(&dev_priv->drm, encoder) {
6761                 struct intel_dp *intel_dp;
6762                 int ret;
6763
6764                 if (encoder->type != INTEL_OUTPUT_DDI)
6765                         continue;
6766
6767                 intel_dp = enc_to_intel_dp(&encoder->base);
6768
6769                 if (!intel_dp->can_mst)
6770                         continue;
6771
6772                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
6773                 if (ret)
6774                         intel_dp_check_mst_status(intel_dp);
6775         }
6776 }