drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 159         switch (max_lane_count) {
 160         case 1: case 2: case 4:
 161                 break;
 162         default:
 163                 max_lane_count = 4;
 164         }
 165         return max_lane_count;
 166 }
 167
 168 static int
 169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 170 {
 171         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 172
 173         switch (max_link_bw) {
 174         case DP_LINK_BW_1_62:
 175         case DP_LINK_BW_2_7:
 176                 break;
 177         default:
 178                 max_link_bw = DP_LINK_BW_1_62;
 179                 break;
 180         }
 181         return max_link_bw;
 182 }
 183
 184 static int
 185 intel_dp_link_clock(uint8_t link_bw)
 186 {
 187         if (link_bw == DP_LINK_BW_2_7)
 188                 return 270000;
 189         else
 190                 return 162000;
 191 }
 192
 193 /*
 194  * The units on the numbers in the next two are... bizarre.  Examples will
 195  * make it clearer; this one parallels an example in the eDP spec.
 196  *
 197  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 198  *
 199  *     270000 * 1 * 8 / 10 == 216000
 200  *
 201  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 202  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 203  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 204  * 119000.  At 18bpp that's 2142000 kilobits per second.
 205  *
 206  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 207  * get the result in decakilobits instead of kilobits.
 208  */
 209
 210 static int
 211 intel_dp_link_required(int pixel_clock, int bpp)
 212 {
 213         return (pixel_clock * bpp + 9) / 10;
 214 }
 215
 216 static int
 217 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 218 {
 219         return (max_link_clock * max_lanes * 8) / 10;
 220 }
 221
 222 static int
 223 intel_dp_mode_valid(struct drm_connector *connector,
 224                     struct drm_display_mode *mode)
 225 {
 226         struct intel_dp *intel_dp = intel_attached_dp(connector);
 227         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 228         int max_lanes = intel_dp_max_lane_count(intel_dp);
 229         int max_rate, mode_rate;
 230
 231         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 232                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 233                         return MODE_PANEL;
 234
 235                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 236                         return MODE_PANEL;
 237         }
 238
 239         mode_rate = intel_dp_link_required(mode->clock, 24);
 240         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 241
 242         if (mode_rate > max_rate) {
 243                         mode_rate = intel_dp_link_required(mode->clock, 18);
 244                         if (mode_rate > max_rate)
 245                                 return MODE_CLOCK_HIGH;
 246                         else
 247                                 mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
 248         }
 249
 250         if (mode->clock < 10000)
 251                 return MODE_CLOCK_LOW;
 252
 253         return MODE_OK;
 254 }
 255
 256 static uint32_t
 257 pack_aux(uint8_t *src, int src_bytes)
 258 {
 259         int     i;
 260         uint32_t v = 0;
 261
 262         if (src_bytes > 4)
 263                 src_bytes = 4;
 264         for (i = 0; i < src_bytes; i++)
 265                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 266         return v;
 267 }
 268
 269 static void
 270 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 271 {
 272         int i;
 273         if (dst_bytes > 4)
 274                 dst_bytes = 4;
 275         for (i = 0; i < dst_bytes; i++)
 276                 dst[i] = src >> ((3-i) * 8);
 277 }
 278
 279 /* hrawclock is 1/4 the FSB frequency */
 280 static int
 281 intel_hrawclk(struct drm_device *dev)
 282 {
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         uint32_t clkcfg;
 285
 286         clkcfg = I915_READ(CLKCFG);
 287         switch (clkcfg & CLKCFG_FSB_MASK) {
 288         case CLKCFG_FSB_400:
 289                 return 100;
 290         case CLKCFG_FSB_533:
 291                 return 133;
 292         case CLKCFG_FSB_667:
 293                 return 166;
 294         case CLKCFG_FSB_800:
 295                 return 200;
 296         case CLKCFG_FSB_1067:
 297                 return 266;
 298         case CLKCFG_FSB_1333:
 299                 return 333;
 300         /* these two are just a guess; one of them might be right */
 301         case CLKCFG_FSB_1600:
 302         case CLKCFG_FSB_1600_ALT:
 303                 return 400;
 304         default:
 305                 return 133;
 306         }
 307 }
 308
 309 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 310 {
 311         struct drm_device *dev = intel_dp->base.base.dev;
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313
 314         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 315 }
 316
 317 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 318 {
 319         struct drm_device *dev = intel_dp->base.base.dev;
 320         struct drm_i915_private *dev_priv = dev->dev_private;
 321
 322         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 323 }
 324
 325 static void
 326 intel_dp_check_edp(struct intel_dp *intel_dp)
 327 {
 328         struct drm_device *dev = intel_dp->base.base.dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330
 331         if (!is_edp(intel_dp))
 332                 return;
 333         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 334                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 335                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 336                               I915_READ(PCH_PP_STATUS),
 337                               I915_READ(PCH_PP_CONTROL));
 338         }
 339 }
 340
 341 static int
 342 intel_dp_aux_ch(struct intel_dp *intel_dp,
 343                 uint8_t *send, int send_bytes,
 344                 uint8_t *recv, int recv_size)
 345 {
 346         uint32_t output_reg = intel_dp->output_reg;
 347         struct drm_device *dev = intel_dp->base.base.dev;
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         uint32_t ch_ctl = output_reg + 0x10;
 350         uint32_t ch_data = ch_ctl + 4;
 351         int i;
 352         int recv_bytes;
 353         uint32_t status;
 354         uint32_t aux_clock_divider;
 355         int try, precharge = 5;
 356
 357         intel_dp_check_edp(intel_dp);
 358         /* The clock divider is based off the hrawclk,
 359          * and would like to run at 2MHz. So, take the
 360          * hrawclk value and divide by 2 and use that
 361          *
 362          * Note that PCH attached eDP panels should use a 125MHz input
 363          * clock divider.
 364          */
 365         if (is_cpu_edp(intel_dp)) {
 366                 if (IS_GEN6(dev) || IS_GEN7(dev))
 367                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 368                 else
 369                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 370         } else if (HAS_PCH_SPLIT(dev))
 371                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 372         else
 373                 aux_clock_divider = intel_hrawclk(dev) / 2;
 374
 375         /* Try to wait for any previous AUX channel activity */
 376         for (try = 0; try < 3; try++) {
 377                 status = I915_READ(ch_ctl);
 378                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 379                         break;
 380                 msleep(1);
 381         }
 382
 383         if (try == 3) {
 384                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 385                      I915_READ(ch_ctl));
 386                 return -EBUSY;
 387         }
 388
 389         /* Must try at least 3 times according to DP spec */
 390         for (try = 0; try < 5; try++) {
 391                 /* Load the send data into the aux channel data registers */
 392                 for (i = 0; i < send_bytes; i += 4)
 393                         I915_WRITE(ch_data + i,
 394                                    pack_aux(send + i, send_bytes - i));
 395
 396                 /* Send the command and wait for it to complete */
 397                 I915_WRITE(ch_ctl,
 398                            DP_AUX_CH_CTL_SEND_BUSY |
 399                            DP_AUX_CH_CTL_TIME_OUT_400us |
 400                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 401                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 402                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 403                            DP_AUX_CH_CTL_DONE |
 404                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 405                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 406                 for (;;) {
 407                         status = I915_READ(ch_ctl);
 408                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 409                                 break;
 410                         udelay(100);
 411                 }
 412
 413                 /* Clear done status and any errors */
 414                 I915_WRITE(ch_ctl,
 415                            status |
 416                            DP_AUX_CH_CTL_DONE |
 417                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 418                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 419
 420                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 421                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 422                         continue;
 423                 if (status & DP_AUX_CH_CTL_DONE)
 424                         break;
 425         }
 426
 427         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 428                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 429                 return -EBUSY;
 430         }
 431
 432         /* Check for timeout or receive error.
 433          * Timeouts occur when the sink is not connected
 434          */
 435         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 436                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 437                 return -EIO;
 438         }
 439
 440         /* Timeouts occur when the device isn't connected, so they're
 441          * "normal" -- don't fill the kernel log with these */
 442         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 443                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 444                 return -ETIMEDOUT;
 445         }
 446
 447         /* Unload any bytes sent back from the other side */
 448         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 449                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 450         if (recv_bytes > recv_size)
 451                 recv_bytes = recv_size;
 452
 453         for (i = 0; i < recv_bytes; i += 4)
 454                 unpack_aux(I915_READ(ch_data + i),
 455                            recv + i, recv_bytes - i);
 456
 457         return recv_bytes;
 458 }
 459
 460 /* Write data to the aux channel in native mode */
 461 static int
 462 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 463                           uint16_t address, uint8_t *send, int send_bytes)
 464 {
 465         int ret;
 466         uint8_t msg[20];
 467         int msg_bytes;
 468         uint8_t ack;
 469
 470         intel_dp_check_edp(intel_dp);
 471         if (send_bytes > 16)
 472                 return -1;
 473         msg[0] = AUX_NATIVE_WRITE << 4;
 474         msg[1] = address >> 8;
 475         msg[2] = address & 0xff;
 476         msg[3] = send_bytes - 1;
 477         memcpy(&msg[4], send, send_bytes);
 478         msg_bytes = send_bytes + 4;
 479         for (;;) {
 480                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 481                 if (ret < 0)
 482                         return ret;
 483                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 484                         break;
 485                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 486                         udelay(100);
 487                 else
 488                         return -EIO;
 489         }
 490         return send_bytes;
 491 }
 492
 493 /* Write a single byte to the aux channel in native mode */
 494 static int
 495 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 496                             uint16_t address, uint8_t byte)
 497 {
 498         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 499 }
 500
 501 /* read bytes from a native aux channel */
 502 static int
 503 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 504                          uint16_t address, uint8_t *recv, int recv_bytes)
 505 {
 506         uint8_t msg[4];
 507         int msg_bytes;
 508         uint8_t reply[20];
 509         int reply_bytes;
 510         uint8_t ack;
 511         int ret;
 512
 513         intel_dp_check_edp(intel_dp);
 514         msg[0] = AUX_NATIVE_READ << 4;
 515         msg[1] = address >> 8;
 516         msg[2] = address & 0xff;
 517         msg[3] = recv_bytes - 1;
 518
 519         msg_bytes = 4;
 520         reply_bytes = recv_bytes + 1;
 521
 522         for (;;) {
 523                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 524                                       reply, reply_bytes);
 525                 if (ret == 0)
 526                         return -EPROTO;
 527                 if (ret < 0)
 528                         return ret;
 529                 ack = reply[0];
 530                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 531                         memcpy(recv, reply + 1, ret - 1);
 532                         return ret - 1;
 533                 }
 534                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 535                         udelay(100);
 536                 else
 537                         return -EIO;
 538         }
 539 }
 540
 541 static int
 542 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 543                     uint8_t write_byte, uint8_t *read_byte)
 544 {
 545         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 546         struct intel_dp *intel_dp = container_of(adapter,
 547                                                 struct intel_dp,
 548                                                 adapter);
 549         uint16_t address = algo_data->address;
 550         uint8_t msg[5];
 551         uint8_t reply[2];
 552         unsigned retry;
 553         int msg_bytes;
 554         int reply_bytes;
 555         int ret;
 556
 557         intel_dp_check_edp(intel_dp);
 558         /* Set up the command byte */
 559         if (mode & MODE_I2C_READ)
 560                 msg[0] = AUX_I2C_READ << 4;
 561         else
 562                 msg[0] = AUX_I2C_WRITE << 4;
 563
 564         if (!(mode & MODE_I2C_STOP))
 565                 msg[0] |= AUX_I2C_MOT << 4;
 566
 567         msg[1] = address >> 8;
 568         msg[2] = address;
 569
 570         switch (mode) {
 571         case MODE_I2C_WRITE:
 572                 msg[3] = 0;
 573                 msg[4] = write_byte;
 574                 msg_bytes = 5;
 575                 reply_bytes = 1;
 576                 break;
 577         case MODE_I2C_READ:
 578                 msg[3] = 0;
 579                 msg_bytes = 4;
 580                 reply_bytes = 2;
 581                 break;
 582         default:
 583                 msg_bytes = 3;
 584                 reply_bytes = 1;
 585                 break;
 586         }
 587
 588         for (retry = 0; retry < 5; retry++) {
 589                 ret = intel_dp_aux_ch(intel_dp,
 590                                       msg, msg_bytes,
 591                                       reply, reply_bytes);
 592                 if (ret < 0) {
 593                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 594                         return ret;
 595                 }
 596
 597                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 598                 case AUX_NATIVE_REPLY_ACK:
 599                         /* I2C-over-AUX Reply field is only valid
 600                          * when paired with AUX ACK.
 601                          */
 602                         break;
 603                 case AUX_NATIVE_REPLY_NACK:
 604                         DRM_DEBUG_KMS("aux_ch native nack\n");
 605                         return -EREMOTEIO;
 606                 case AUX_NATIVE_REPLY_DEFER:
 607                         udelay(100);
 608                         continue;
 609                 default:
 610                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 611                                   reply[0]);
 612                         return -EREMOTEIO;
 613                 }
 614
 615                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 616                 case AUX_I2C_REPLY_ACK:
 617                         if (mode == MODE_I2C_READ) {
 618                                 *read_byte = reply[1];
 619                         }
 620                         return reply_bytes - 1;
 621                 case AUX_I2C_REPLY_NACK:
 622                         DRM_DEBUG_KMS("aux_i2c nack\n");
 623                         return -EREMOTEIO;
 624                 case AUX_I2C_REPLY_DEFER:
 625                         DRM_DEBUG_KMS("aux_i2c defer\n");
 626                         udelay(100);
 627                         break;
 628                 default:
 629                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 630                         return -EREMOTEIO;
 631                 }
 632         }
 633
 634         DRM_ERROR("too many retries, giving up\n");
 635         return -EREMOTEIO;
 636 }
 637
 638 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 639 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 640
 641 static int
 642 intel_dp_i2c_init(struct intel_dp *intel_dp,
 643                   struct intel_connector *intel_connector, const char *name)
 644 {
 645         int     ret;
 646
 647         DRM_DEBUG_KMS("i2c_init %s\n", name);
 648         intel_dp->algo.running = false;
 649         intel_dp->algo.address = 0;
 650         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 651
 652         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 653         intel_dp->adapter.owner = THIS_MODULE;
 654         intel_dp->adapter.class = I2C_CLASS_DDC;
 655         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 656         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 657         intel_dp->adapter.algo_data = &intel_dp->algo;
 658         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 659
 660         ironlake_edp_panel_vdd_on(intel_dp);
 661         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 662         ironlake_edp_panel_vdd_off(intel_dp, false);
 663         return ret;
 664 }
 665
 666 static bool
 667 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 668                     struct drm_display_mode *adjusted_mode)
 669 {
 670         struct drm_device *dev = encoder->dev;
 671         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 672         int lane_count, clock;
 673         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 674         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 675         int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 676         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 677
 678         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 679                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 680                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 681                                         mode, adjusted_mode);
 682                 /*
 683                  * the mode->clock is used to calculate the Data&Link M/N
 684                  * of the pipe. For the eDP the fixed clock should be used.
 685                  */
 686                 mode->clock = intel_dp->panel_fixed_mode->clock;
 687         }
 688
 689         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 690                 for (clock = 0; clock <= max_clock; clock++) {
 691                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 692
 693                         if (intel_dp_link_required(mode->clock, bpp)
 694                                         <= link_avail) {
 695                                 intel_dp->link_bw = bws[clock];
 696                                 intel_dp->lane_count = lane_count;
 697                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 698                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 699                                                 "count %d clock %d\n",
 700                                        intel_dp->link_bw, intel_dp->lane_count,
 701                                        adjusted_mode->clock);
 702                                 return true;
 703                         }
 704                 }
 705         }
 706
 707         return false;
 708 }
 709
 710 struct intel_dp_m_n {
 711         uint32_t        tu;
 712         uint32_t        gmch_m;
 713         uint32_t        gmch_n;
 714         uint32_t        link_m;
 715         uint32_t        link_n;
 716 };
 717
 718 static void
 719 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 720 {
 721         while (*num > 0xffffff || *den > 0xffffff) {
 722                 *num >>= 1;
 723                 *den >>= 1;
 724         }
 725 }
 726
 727 static void
 728 intel_dp_compute_m_n(int bpp,
 729                      int nlanes,
 730                      int pixel_clock,
 731                      int link_clock,
 732                      struct intel_dp_m_n *m_n)
 733 {
 734         m_n->tu = 64;
 735         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 736         m_n->gmch_n = link_clock * nlanes;
 737         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 738         m_n->link_m = pixel_clock;
 739         m_n->link_n = link_clock;
 740         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 741 }
 742
 743 void
 744 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 745                  struct drm_display_mode *adjusted_mode)
 746 {
 747         struct drm_device *dev = crtc->dev;
 748         struct drm_mode_config *mode_config = &dev->mode_config;
 749         struct drm_encoder *encoder;
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 752         int lane_count = 4;
 753         struct intel_dp_m_n m_n;
 754         int pipe = intel_crtc->pipe;
 755
 756         /*
 757          * Find the lane count in the intel_encoder private
 758          */
 759         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 760                 struct intel_dp *intel_dp;
 761
 762                 if (encoder->crtc != crtc)
 763                         continue;
 764
 765                 intel_dp = enc_to_intel_dp(encoder);
 766                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 767                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 768                 {
 769                         lane_count = intel_dp->lane_count;
 770                         break;
 771                 }
 772         }
 773
 774         /*
 775          * Compute the GMCH and Link ratios. The '3' here is
 776          * the number of bytes_per_pixel post-LUT, which we always
 777          * set up for 8-bits of R/G/B, or 3 bytes total.
 778          */
 779         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 780                              mode->clock, adjusted_mode->clock, &m_n);
 781
 782         if (HAS_PCH_SPLIT(dev)) {
 783                 I915_WRITE(TRANSDATA_M1(pipe),
 784                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 785                            m_n.gmch_m);
 786                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 787                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 788                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 789         } else {
 790                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 791                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 792                            m_n.gmch_m);
 793                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 794                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 795                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 796         }
 797 }
 798
 799 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 800 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 801
 802 static void
 803 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 804                   struct drm_display_mode *adjusted_mode)
 805 {
 806         struct drm_device *dev = encoder->dev;
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 809         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 811
 812         /* Turn on the eDP PLL if needed */
 813         if (is_edp(intel_dp)) {
 814                 if (!is_pch_edp(intel_dp))
 815                         ironlake_edp_pll_on(encoder);
 816                 else
 817                         ironlake_edp_pll_off(encoder);
 818         }
 819
 820         /*
 821          * There are four kinds of DP registers:
 822          *
 823          *      IBX PCH
 824          *      SNB CPU
 825          *      IVB CPU
 826          *      CPT PCH
 827          *
 828          * IBX PCH and CPU are the same for almost everything,
 829          * except that the CPU DP PLL is configured in this
 830          * register
 831          *
 832          * CPT PCH is quite different, having many bits moved
 833          * to the TRANS_DP_CTL register instead. That
 834          * configuration happens (oddly) in ironlake_pch_enable
 835          */
 836
 837         /* Preserve the BIOS-computed detected bit. This is
 838          * supposed to be read-only.
 839          */
 840         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 841         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 842
 843         /* Handle DP bits in common between all three register formats */
 844
 845         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 846
 847         switch (intel_dp->lane_count) {
 848         case 1:
 849                 intel_dp->DP |= DP_PORT_WIDTH_1;
 850                 break;
 851         case 2:
 852                 intel_dp->DP |= DP_PORT_WIDTH_2;
 853                 break;
 854         case 4:
 855                 intel_dp->DP |= DP_PORT_WIDTH_4;
 856                 break;
 857         }
 858         if (intel_dp->has_audio) {
 859                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 860                                  pipe_name(intel_crtc->pipe));
 861                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 862                 intel_write_eld(encoder, adjusted_mode);
 863         }
 864         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 865         intel_dp->link_configuration[0] = intel_dp->link_bw;
 866         intel_dp->link_configuration[1] = intel_dp->lane_count;
 867         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 868         /*
 869          * Check for DPCD version > 1.1 and enhanced framing support
 870          */
 871         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 872             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 873                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 874         }
 875
 876         /* Split out the IBX/CPU vs CPT settings */
 877
 878         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 879                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 880                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 881                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 882                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 883                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 884
 885                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 886                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 887
 888                 intel_dp->DP |= intel_crtc->pipe << 29;
 889
 890                 /* don't miss out required setting for eDP */
 891                 intel_dp->DP |= DP_PLL_ENABLE;
 892                 if (adjusted_mode->clock < 200000)
 893                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 894                 else
 895                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 896         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 897                 intel_dp->DP |= intel_dp->color_range;
 898
 899                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 900                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 901                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 902                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 903                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 904
 905                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 906                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 907
 908                 if (intel_crtc->pipe == 1)
 909                         intel_dp->DP |= DP_PIPEB_SELECT;
 910
 911                 if (is_cpu_edp(intel_dp)) {
 912                         /* don't miss out required setting for eDP */
 913                         intel_dp->DP |= DP_PLL_ENABLE;
 914                         if (adjusted_mode->clock < 200000)
 915                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 916                         else
 917                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 918                 }
 919         } else {
 920                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 921         }
 922 }
 923
 924 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 925 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 926
 927 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 928 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 929
 930 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 931 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 932
 933 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 934                                        u32 mask,
 935                                        u32 value)
 936 {
 937         struct drm_device *dev = intel_dp->base.base.dev;
 938         struct drm_i915_private *dev_priv = dev->dev_private;
 939
 940         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 941                       mask, value,
 942                       I915_READ(PCH_PP_STATUS),
 943                       I915_READ(PCH_PP_CONTROL));
 944
 945         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 946                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 947                           I915_READ(PCH_PP_STATUS),
 948                           I915_READ(PCH_PP_CONTROL));
 949         }
 950 }
 951
 952 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 953 {
 954         DRM_DEBUG_KMS("Wait for panel power on\n");
 955         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 956 }
 957
 958 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 959 {
 960         DRM_DEBUG_KMS("Wait for panel power off time\n");
 961         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 962 }
 963
 964 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 965 {
 966         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 967         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 968 }
 969
 970
 971 /* Read the current pp_control value, unlocking the register if it
 972  * is locked
 973  */
 974
 975 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 976 {
 977         u32     control = I915_READ(PCH_PP_CONTROL);
 978
 979         control &= ~PANEL_UNLOCK_MASK;
 980         control |= PANEL_UNLOCK_REGS;
 981         return control;
 982 }
 983
 984 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 985 {
 986         struct drm_device *dev = intel_dp->base.base.dev;
 987         struct drm_i915_private *dev_priv = dev->dev_private;
 988         u32 pp;
 989
 990         if (!is_edp(intel_dp))
 991                 return;
 992         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 993
 994         WARN(intel_dp->want_panel_vdd,
 995              "eDP VDD already requested on\n");
 996
 997         intel_dp->want_panel_vdd = true;
 998
 999         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1000                 DRM_DEBUG_KMS("eDP VDD already on\n");
1001                 return;
1002         }
1003
1004         if (!ironlake_edp_have_panel_power(intel_dp))
1005                 ironlake_wait_panel_power_cycle(intel_dp);
1006
1007         pp = ironlake_get_pp_control(dev_priv);
1008         pp |= EDP_FORCE_VDD;
1009         I915_WRITE(PCH_PP_CONTROL, pp);
1010         POSTING_READ(PCH_PP_CONTROL);
1011         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1012                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1013
1014         /*
1015          * If the panel wasn't on, delay before accessing aux channel
1016          */
1017         if (!ironlake_edp_have_panel_power(intel_dp)) {
1018                 DRM_DEBUG_KMS("eDP was not running\n");
1019                 msleep(intel_dp->panel_power_up_delay);
1020         }
1021 }
1022
1023 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1024 {
1025         struct drm_device *dev = intel_dp->base.base.dev;
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027         u32 pp;
1028
1029         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1030                 pp = ironlake_get_pp_control(dev_priv);
1031                 pp &= ~EDP_FORCE_VDD;
1032                 I915_WRITE(PCH_PP_CONTROL, pp);
1033                 POSTING_READ(PCH_PP_CONTROL);
1034
1035                 /* Make sure sequencer is idle before allowing subsequent activity */
1036                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1037                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1038
1039                 msleep(intel_dp->panel_power_down_delay);
1040         }
1041 }
1042
1043 static void ironlake_panel_vdd_work(struct work_struct *__work)
1044 {
1045         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1046                                                  struct intel_dp, panel_vdd_work);
1047         struct drm_device *dev = intel_dp->base.base.dev;
1048
1049         mutex_lock(&dev->mode_config.mutex);
1050         ironlake_panel_vdd_off_sync(intel_dp);
1051         mutex_unlock(&dev->mode_config.mutex);
1052 }
1053
1054 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1055 {
1056         if (!is_edp(intel_dp))
1057                 return;
1058
1059         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1060         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1061
1062         intel_dp->want_panel_vdd = false;
1063
1064         if (sync) {
1065                 ironlake_panel_vdd_off_sync(intel_dp);
1066         } else {
1067                 /*
1068                  * Queue the timer to fire a long
1069                  * time from now (relative to the power down delay)
1070                  * to keep the panel power up across a sequence of operations
1071                  */
1072                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1073                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1074         }
1075 }
1076
1077 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1078 {
1079         struct drm_device *dev = intel_dp->base.base.dev;
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081         u32 pp;
1082
1083         if (!is_edp(intel_dp))
1084                 return;
1085
1086         DRM_DEBUG_KMS("Turn eDP power on\n");
1087
1088         if (ironlake_edp_have_panel_power(intel_dp)) {
1089                 DRM_DEBUG_KMS("eDP power already on\n");
1090                 return;
1091         }
1092
1093         ironlake_wait_panel_power_cycle(intel_dp);
1094
1095         pp = ironlake_get_pp_control(dev_priv);
1096         if (IS_GEN5(dev)) {
1097                 /* ILK workaround: disable reset around power sequence */
1098                 pp &= ~PANEL_POWER_RESET;
1099                 I915_WRITE(PCH_PP_CONTROL, pp);
1100                 POSTING_READ(PCH_PP_CONTROL);
1101         }
1102
1103         pp |= POWER_TARGET_ON;
1104         if (!IS_GEN5(dev))
1105                 pp |= PANEL_POWER_RESET;
1106
1107         I915_WRITE(PCH_PP_CONTROL, pp);
1108         POSTING_READ(PCH_PP_CONTROL);
1109
1110         ironlake_wait_panel_on(intel_dp);
1111
1112         if (IS_GEN5(dev)) {
1113                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1114                 I915_WRITE(PCH_PP_CONTROL, pp);
1115                 POSTING_READ(PCH_PP_CONTROL);
1116         }
1117 }
1118
1119 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1120 {
1121         struct drm_device *dev = intel_dp->base.base.dev;
1122         struct drm_i915_private *dev_priv = dev->dev_private;
1123         u32 pp;
1124
1125         if (!is_edp(intel_dp))
1126                 return;
1127
1128         DRM_DEBUG_KMS("Turn eDP power off\n");
1129
1130         WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1131
1132         pp = ironlake_get_pp_control(dev_priv);
1133         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1134         I915_WRITE(PCH_PP_CONTROL, pp);
1135         POSTING_READ(PCH_PP_CONTROL);
1136
1137         ironlake_wait_panel_off(intel_dp);
1138 }
1139
1140 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1141 {
1142         struct drm_device *dev = intel_dp->base.base.dev;
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144         u32 pp;
1145
1146         if (!is_edp(intel_dp))
1147                 return;
1148
1149         DRM_DEBUG_KMS("\n");
1150         /*
1151          * If we enable the backlight right away following a panel power
1152          * on, we may see slight flicker as the panel syncs with the eDP
1153          * link.  So delay a bit to make sure the image is solid before
1154          * allowing it to appear.
1155          */
1156         msleep(intel_dp->backlight_on_delay);
1157         pp = ironlake_get_pp_control(dev_priv);
1158         pp |= EDP_BLC_ENABLE;
1159         I915_WRITE(PCH_PP_CONTROL, pp);
1160         POSTING_READ(PCH_PP_CONTROL);
1161 }
1162
1163 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1164 {
1165         struct drm_device *dev = intel_dp->base.base.dev;
1166         struct drm_i915_private *dev_priv = dev->dev_private;
1167         u32 pp;
1168
1169         if (!is_edp(intel_dp))
1170                 return;
1171
1172         DRM_DEBUG_KMS("\n");
1173         pp = ironlake_get_pp_control(dev_priv);
1174         pp &= ~EDP_BLC_ENABLE;
1175         I915_WRITE(PCH_PP_CONTROL, pp);
1176         POSTING_READ(PCH_PP_CONTROL);
1177         msleep(intel_dp->backlight_off_delay);
1178 }
1179
1180 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1181 {
1182         struct drm_device *dev = encoder->dev;
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184         u32 dpa_ctl;
1185
1186         DRM_DEBUG_KMS("\n");
1187         dpa_ctl = I915_READ(DP_A);
1188         dpa_ctl |= DP_PLL_ENABLE;
1189         I915_WRITE(DP_A, dpa_ctl);
1190         POSTING_READ(DP_A);
1191         udelay(200);
1192 }
1193
1194 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1195 {
1196         struct drm_device *dev = encoder->dev;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         u32 dpa_ctl;
1199
1200         dpa_ctl = I915_READ(DP_A);
1201         dpa_ctl &= ~DP_PLL_ENABLE;
1202         I915_WRITE(DP_A, dpa_ctl);
1203         POSTING_READ(DP_A);
1204         udelay(200);
1205 }
1206
1207 /* If the sink supports it, try to set the power state appropriately */
1208 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1209 {
1210         int ret, i;
1211
1212         /* Should have a valid DPCD by this point */
1213         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1214                 return;
1215
1216         if (mode != DRM_MODE_DPMS_ON) {
1217                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1218                                                   DP_SET_POWER_D3);
1219                 if (ret != 1)
1220                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1221         } else {
1222                 /*
1223                  * When turning on, we need to retry for 1ms to give the sink
1224                  * time to wake up.
1225                  */
1226                 for (i = 0; i < 3; i++) {
1227                         ret = intel_dp_aux_native_write_1(intel_dp,
1228                                                           DP_SET_POWER,
1229                                                           DP_SET_POWER_D0);
1230                         if (ret == 1)
1231                                 break;
1232                         msleep(1);
1233                 }
1234         }
1235 }
1236
1237 static void intel_dp_prepare(struct drm_encoder *encoder)
1238 {
1239         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1240
1241         ironlake_edp_backlight_off(intel_dp);
1242         ironlake_edp_panel_off(intel_dp);
1243
1244         /* Wake up the sink first */
1245         ironlake_edp_panel_vdd_on(intel_dp);
1246         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1247         intel_dp_link_down(intel_dp);
1248         ironlake_edp_panel_vdd_off(intel_dp, false);
1249
1250         /* Make sure the panel is off before trying to
1251          * change the mode
1252          */
1253 }
1254
1255 static void intel_dp_commit(struct drm_encoder *encoder)
1256 {
1257         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1258         struct drm_device *dev = encoder->dev;
1259         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1260
1261         ironlake_edp_panel_vdd_on(intel_dp);
1262         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1263         intel_dp_start_link_train(intel_dp);
1264         ironlake_edp_panel_on(intel_dp);
1265         ironlake_edp_panel_vdd_off(intel_dp, true);
1266         intel_dp_complete_link_train(intel_dp);
1267         ironlake_edp_backlight_on(intel_dp);
1268
1269         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1270
1271         if (HAS_PCH_CPT(dev))
1272                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1273 }
1274
1275 static void
1276 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1277 {
1278         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1279         struct drm_device *dev = encoder->dev;
1280         struct drm_i915_private *dev_priv = dev->dev_private;
1281         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1282
1283         if (mode != DRM_MODE_DPMS_ON) {
1284                 ironlake_edp_backlight_off(intel_dp);
1285                 ironlake_edp_panel_off(intel_dp);
1286
1287                 ironlake_edp_panel_vdd_on(intel_dp);
1288                 intel_dp_sink_dpms(intel_dp, mode);
1289                 intel_dp_link_down(intel_dp);
1290                 ironlake_edp_panel_vdd_off(intel_dp, false);
1291
1292                 if (is_cpu_edp(intel_dp))
1293                         ironlake_edp_pll_off(encoder);
1294         } else {
1295                 if (is_cpu_edp(intel_dp))
1296                         ironlake_edp_pll_on(encoder);
1297
1298                 ironlake_edp_panel_vdd_on(intel_dp);
1299                 intel_dp_sink_dpms(intel_dp, mode);
1300                 if (!(dp_reg & DP_PORT_EN)) {
1301                         intel_dp_start_link_train(intel_dp);
1302                         ironlake_edp_panel_on(intel_dp);
1303                         ironlake_edp_panel_vdd_off(intel_dp, true);
1304                         intel_dp_complete_link_train(intel_dp);
1305                 } else
1306                         ironlake_edp_panel_vdd_off(intel_dp, false);
1307                 ironlake_edp_backlight_on(intel_dp);
1308         }
1309         intel_dp->dpms_mode = mode;
1310 }
1311
1312 /*
1313  * Native read with retry for link status and receiver capability reads for
1314  * cases where the sink may still be asleep.
1315  */
1316 static bool
1317 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1318                                uint8_t *recv, int recv_bytes)
1319 {
1320         int ret, i;
1321
1322         /*
1323          * Sinks are *supposed* to come up within 1ms from an off state,
1324          * but we're also supposed to retry 3 times per the spec.
1325          */
1326         for (i = 0; i < 3; i++) {
1327                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1328                                                recv_bytes);
1329                 if (ret == recv_bytes)
1330                         return true;
1331                 msleep(1);
1332         }
1333
1334         return false;
1335 }
1336
1337 /*
1338  * Fetch AUX CH registers 0x202 - 0x207 which contain
1339  * link status information
1340  */
1341 static bool
1342 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1343 {
1344         return intel_dp_aux_native_read_retry(intel_dp,
1345                                               DP_LANE0_1_STATUS,
1346                                               link_status,
1347                                               DP_LINK_STATUS_SIZE);
1348 }
1349
1350 static uint8_t
1351 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1352                      int r)
1353 {
1354         return link_status[r - DP_LANE0_1_STATUS];
1355 }
1356
1357 static uint8_t
1358 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1359                                  int lane)
1360 {
1361         int         s = ((lane & 1) ?
1362                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1363                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1364         uint8_t l = adjust_request[lane>>1];
1365
1366         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1367 }
1368
1369 static uint8_t
1370 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1371                                       int lane)
1372 {
1373         int         s = ((lane & 1) ?
1374                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1375                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1376         uint8_t l = adjust_request[lane>>1];
1377
1378         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1379 }
1380
1381
1382 #if 0
1383 static char     *voltage_names[] = {
1384         "0.4V", "0.6V", "0.8V", "1.2V"
1385 };
1386 static char     *pre_emph_names[] = {
1387         "0dB", "3.5dB", "6dB", "9.5dB"
1388 };
1389 static char     *link_train_names[] = {
1390         "pattern 1", "pattern 2", "idle", "off"
1391 };
1392 #endif
1393
1394 /*
1395  * These are source-specific values; current Intel hardware supports
1396  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1397  */
1398
1399 static uint8_t
1400 intel_dp_voltage_max(struct intel_dp *intel_dp)
1401 {
1402         struct drm_device *dev = intel_dp->base.base.dev;
1403
1404         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1405                 return DP_TRAIN_VOLTAGE_SWING_800;
1406         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1407                 return DP_TRAIN_VOLTAGE_SWING_1200;
1408         else
1409                 return DP_TRAIN_VOLTAGE_SWING_800;
1410 }
1411
1412 static uint8_t
1413 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1414 {
1415         struct drm_device *dev = intel_dp->base.base.dev;
1416
1417         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1418                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1419                 case DP_TRAIN_VOLTAGE_SWING_400:
1420                         return DP_TRAIN_PRE_EMPHASIS_6;
1421                 case DP_TRAIN_VOLTAGE_SWING_600:
1422                 case DP_TRAIN_VOLTAGE_SWING_800:
1423                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1424                 default:
1425                         return DP_TRAIN_PRE_EMPHASIS_0;
1426                 }
1427         } else {
1428                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1429                 case DP_TRAIN_VOLTAGE_SWING_400:
1430                         return DP_TRAIN_PRE_EMPHASIS_6;
1431                 case DP_TRAIN_VOLTAGE_SWING_600:
1432                         return DP_TRAIN_PRE_EMPHASIS_6;
1433                 case DP_TRAIN_VOLTAGE_SWING_800:
1434                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1435                 case DP_TRAIN_VOLTAGE_SWING_1200:
1436                 default:
1437                         return DP_TRAIN_PRE_EMPHASIS_0;
1438                 }
1439         }
1440 }
1441
1442 static void
1443 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1444 {
1445         uint8_t v = 0;
1446         uint8_t p = 0;
1447         int lane;
1448         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1449         uint8_t voltage_max;
1450         uint8_t preemph_max;
1451
1452         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1453                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1454                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1455
1456                 if (this_v > v)
1457                         v = this_v;
1458                 if (this_p > p)
1459                         p = this_p;
1460         }
1461
1462         voltage_max = intel_dp_voltage_max(intel_dp);
1463         if (v >= voltage_max)
1464                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1465
1466         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1467         if (p >= preemph_max)
1468                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1469
1470         for (lane = 0; lane < 4; lane++)
1471                 intel_dp->train_set[lane] = v | p;
1472 }
1473
1474 static uint32_t
1475 intel_dp_signal_levels(uint8_t train_set)
1476 {
1477         uint32_t        signal_levels = 0;
1478
1479         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1480         case DP_TRAIN_VOLTAGE_SWING_400:
1481         default:
1482                 signal_levels |= DP_VOLTAGE_0_4;
1483                 break;
1484         case DP_TRAIN_VOLTAGE_SWING_600:
1485                 signal_levels |= DP_VOLTAGE_0_6;
1486                 break;
1487         case DP_TRAIN_VOLTAGE_SWING_800:
1488                 signal_levels |= DP_VOLTAGE_0_8;
1489                 break;
1490         case DP_TRAIN_VOLTAGE_SWING_1200:
1491                 signal_levels |= DP_VOLTAGE_1_2;
1492                 break;
1493         }
1494         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1495         case DP_TRAIN_PRE_EMPHASIS_0:
1496         default:
1497                 signal_levels |= DP_PRE_EMPHASIS_0;
1498                 break;
1499         case DP_TRAIN_PRE_EMPHASIS_3_5:
1500                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1501                 break;
1502         case DP_TRAIN_PRE_EMPHASIS_6:
1503                 signal_levels |= DP_PRE_EMPHASIS_6;
1504                 break;
1505         case DP_TRAIN_PRE_EMPHASIS_9_5:
1506                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1507                 break;
1508         }
1509         return signal_levels;
1510 }
1511
1512 /* Gen6's DP voltage swing and pre-emphasis control */
1513 static uint32_t
1514 intel_gen6_edp_signal_levels(uint8_t train_set)
1515 {
1516         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1517                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1518         switch (signal_levels) {
1519         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1520         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1521                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1522         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1523                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1524         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1525         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1526                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1527         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1528         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1529                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1530         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1531         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1532                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1533         default:
1534                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1535                               "0x%x\n", signal_levels);
1536                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1537         }
1538 }
1539
1540 /* Gen7's DP voltage swing and pre-emphasis control */
1541 static uint32_t
1542 intel_gen7_edp_signal_levels(uint8_t train_set)
1543 {
1544         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1545                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1546         switch (signal_levels) {
1547         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1548                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1549         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1550                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1551         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1552                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1553
1554         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1555                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1556         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1557                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1558
1559         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1560                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1561         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1562                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1563
1564         default:
1565                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1566                               "0x%x\n", signal_levels);
1567                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1568         }
1569 }
1570
1571 static uint8_t
1572 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1573                       int lane)
1574 {
1575         int s = (lane & 1) * 4;
1576         uint8_t l = link_status[lane>>1];
1577
1578         return (l >> s) & 0xf;
1579 }
1580
1581 /* Check for clock recovery is done on all channels */
1582 static bool
1583 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1584 {
1585         int lane;
1586         uint8_t lane_status;
1587
1588         for (lane = 0; lane < lane_count; lane++) {
1589                 lane_status = intel_get_lane_status(link_status, lane);
1590                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1591                         return false;
1592         }
1593         return true;
1594 }
1595
1596 /* Check to see if channel eq is done on all channels */
1597 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1598                          DP_LANE_CHANNEL_EQ_DONE|\
1599                          DP_LANE_SYMBOL_LOCKED)
1600 static bool
1601 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1602 {
1603         uint8_t lane_align;
1604         uint8_t lane_status;
1605         int lane;
1606
1607         lane_align = intel_dp_link_status(link_status,
1608                                           DP_LANE_ALIGN_STATUS_UPDATED);
1609         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1610                 return false;
1611         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1612                 lane_status = intel_get_lane_status(link_status, lane);
1613                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1614                         return false;
1615         }
1616         return true;
1617 }
1618
1619 static bool
1620 intel_dp_set_link_train(struct intel_dp *intel_dp,
1621                         uint32_t dp_reg_value,
1622                         uint8_t dp_train_pat)
1623 {
1624         struct drm_device *dev = intel_dp->base.base.dev;
1625         struct drm_i915_private *dev_priv = dev->dev_private;
1626         int ret;
1627
1628         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1629         POSTING_READ(intel_dp->output_reg);
1630
1631         intel_dp_aux_native_write_1(intel_dp,
1632                                     DP_TRAINING_PATTERN_SET,
1633                                     dp_train_pat);
1634
1635         ret = intel_dp_aux_native_write(intel_dp,
1636                                         DP_TRAINING_LANE0_SET,
1637                                         intel_dp->train_set,
1638                                         intel_dp->lane_count);
1639         if (ret != intel_dp->lane_count)
1640                 return false;
1641
1642         return true;
1643 }
1644
1645 /* Enable corresponding port and start training pattern 1 */
1646 static void
1647 intel_dp_start_link_train(struct intel_dp *intel_dp)
1648 {
1649         struct drm_device *dev = intel_dp->base.base.dev;
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1652         int i;
1653         uint8_t voltage;
1654         bool clock_recovery = false;
1655         int voltage_tries, loop_tries;
1656         u32 reg;
1657         uint32_t DP = intel_dp->DP;
1658
1659         /*
1660          * On CPT we have to enable the port in training pattern 1, which
1661          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1662          * the port and wait for it to become active.
1663          */
1664         if (!HAS_PCH_CPT(dev)) {
1665                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1666                 POSTING_READ(intel_dp->output_reg);
1667                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1668         }
1669
1670         /* Write the link configuration data */
1671         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1672                                   intel_dp->link_configuration,
1673                                   DP_LINK_CONFIGURATION_SIZE);
1674
1675         DP |= DP_PORT_EN;
1676
1677         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1678                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1679         else
1680                 DP &= ~DP_LINK_TRAIN_MASK;
1681         memset(intel_dp->train_set, 0, 4);
1682         voltage = 0xff;
1683         voltage_tries = 0;
1684         loop_tries = 0;
1685         clock_recovery = false;
1686         for (;;) {
1687                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1688                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1689                 uint32_t    signal_levels;
1690
1691
1692                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1693                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1694                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1695                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1696                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1697                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1698                 } else {
1699                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1700                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1701                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1702                 }
1703
1704                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1705                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1706                 else
1707                         reg = DP | DP_LINK_TRAIN_PAT_1;
1708
1709                 if (!intel_dp_set_link_train(intel_dp, reg,
1710                                              DP_TRAINING_PATTERN_1 |
1711                                              DP_LINK_SCRAMBLING_DISABLE))
1712                         break;
1713                 /* Set training pattern 1 */
1714
1715                 udelay(100);
1716                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1717                         DRM_ERROR("failed to get link status\n");
1718                         break;
1719                 }
1720
1721                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1722                         DRM_DEBUG_KMS("clock recovery OK\n");
1723                         clock_recovery = true;
1724                         break;
1725                 }
1726
1727                 /* Check to see if we've tried the max voltage */
1728                 for (i = 0; i < intel_dp->lane_count; i++)
1729                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1730                                 break;
1731                 if (i == intel_dp->lane_count) {
1732                         ++loop_tries;
1733                         if (loop_tries == 5) {
1734                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1735                                 break;
1736                         }
1737                         memset(intel_dp->train_set, 0, 4);
1738                         voltage_tries = 0;
1739                         continue;
1740                 }
1741
1742                 /* Check to see if we've tried the same voltage 5 times */
1743                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1744                         ++voltage_tries;
1745                         if (voltage_tries == 5) {
1746                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1747                                 break;
1748                         }
1749                 } else
1750                         voltage_tries = 0;
1751                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1752
1753                 /* Compute new intel_dp->train_set as requested by target */
1754                 intel_get_adjust_train(intel_dp, link_status);
1755         }
1756
1757         intel_dp->DP = DP;
1758 }
1759
1760 static void
1761 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1762 {
1763         struct drm_device *dev = intel_dp->base.base.dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         bool channel_eq = false;
1766         int tries, cr_tries;
1767         u32 reg;
1768         uint32_t DP = intel_dp->DP;
1769
1770         /* channel equalization */
1771         tries = 0;
1772         cr_tries = 0;
1773         channel_eq = false;
1774         for (;;) {
1775                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1776                 uint32_t    signal_levels;
1777                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1778
1779                 if (cr_tries > 5) {
1780                         DRM_ERROR("failed to train DP, aborting\n");
1781                         intel_dp_link_down(intel_dp);
1782                         break;
1783                 }
1784
1785                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1786                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1787                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1788                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1789                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1790                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1791                 } else {
1792                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1793                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1794                 }
1795
1796                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1797                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1798                 else
1799                         reg = DP | DP_LINK_TRAIN_PAT_2;
1800
1801                 /* channel eq pattern */
1802                 if (!intel_dp_set_link_train(intel_dp, reg,
1803                                              DP_TRAINING_PATTERN_2 |
1804                                              DP_LINK_SCRAMBLING_DISABLE))
1805                         break;
1806
1807                 udelay(400);
1808                 if (!intel_dp_get_link_status(intel_dp, link_status))
1809                         break;
1810
1811                 /* Make sure clock is still ok */
1812                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1813                         intel_dp_start_link_train(intel_dp);
1814                         cr_tries++;
1815                         continue;
1816                 }
1817
1818                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1819                         channel_eq = true;
1820                         break;
1821                 }
1822
1823                 /* Try 5 times, then try clock recovery if that fails */
1824                 if (tries > 5) {
1825                         intel_dp_link_down(intel_dp);
1826                         intel_dp_start_link_train(intel_dp);
1827                         tries = 0;
1828                         cr_tries++;
1829                         continue;
1830                 }
1831
1832                 /* Compute new intel_dp->train_set as requested by target */
1833                 intel_get_adjust_train(intel_dp, link_status);
1834                 ++tries;
1835         }
1836
1837         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1838                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1839         else
1840                 reg = DP | DP_LINK_TRAIN_OFF;
1841
1842         I915_WRITE(intel_dp->output_reg, reg);
1843         POSTING_READ(intel_dp->output_reg);
1844         intel_dp_aux_native_write_1(intel_dp,
1845                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1846 }
1847
1848 static void
1849 intel_dp_link_down(struct intel_dp *intel_dp)
1850 {
1851         struct drm_device *dev = intel_dp->base.base.dev;
1852         struct drm_i915_private *dev_priv = dev->dev_private;
1853         uint32_t DP = intel_dp->DP;
1854
1855         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1856                 return;
1857
1858         DRM_DEBUG_KMS("\n");
1859
1860         if (is_edp(intel_dp)) {
1861                 DP &= ~DP_PLL_ENABLE;
1862                 I915_WRITE(intel_dp->output_reg, DP);
1863                 POSTING_READ(intel_dp->output_reg);
1864                 udelay(100);
1865         }
1866
1867         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1868                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1869                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1870         } else {
1871                 DP &= ~DP_LINK_TRAIN_MASK;
1872                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1873         }
1874         POSTING_READ(intel_dp->output_reg);
1875
1876         msleep(17);
1877
1878         if (is_edp(intel_dp)) {
1879                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1880                         DP |= DP_LINK_TRAIN_OFF_CPT;
1881                 else
1882                         DP |= DP_LINK_TRAIN_OFF;
1883         }
1884
1885         if (!HAS_PCH_CPT(dev) &&
1886             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1887                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1888
1889                 /* Hardware workaround: leaving our transcoder select
1890                  * set to transcoder B while it's off will prevent the
1891                  * corresponding HDMI output on transcoder A.
1892                  *
1893                  * Combine this with another hardware workaround:
1894                  * transcoder select bit can only be cleared while the
1895                  * port is enabled.
1896                  */
1897                 DP &= ~DP_PIPEB_SELECT;
1898                 I915_WRITE(intel_dp->output_reg, DP);
1899
1900                 /* Changes to enable or select take place the vblank
1901                  * after being written.
1902                  */
1903                 if (crtc == NULL) {
1904                         /* We can arrive here never having been attached
1905                          * to a CRTC, for instance, due to inheriting
1906                          * random state from the BIOS.
1907                          *
1908                          * If the pipe is not running, play safe and
1909                          * wait for the clocks to stabilise before
1910                          * continuing.
1911                          */
1912                         POSTING_READ(intel_dp->output_reg);
1913                         msleep(50);
1914                 } else
1915                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1916         }
1917
1918         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1919         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1920         POSTING_READ(intel_dp->output_reg);
1921         msleep(intel_dp->panel_power_down_delay);
1922 }
1923
1924 static bool
1925 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1926 {
1927         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1928                                            sizeof(intel_dp->dpcd)) &&
1929             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1930                 return true;
1931         }
1932
1933         return false;
1934 }
1935
1936 static bool
1937 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1938 {
1939         int ret;
1940
1941         ret = intel_dp_aux_native_read_retry(intel_dp,
1942                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1943                                              sink_irq_vector, 1);
1944         if (!ret)
1945                 return false;
1946
1947         return true;
1948 }
1949
1950 static void
1951 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1952 {
1953         /* NAK by default */
1954         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1955 }
1956
1957 /*
1958  * According to DP spec
1959  * 5.1.2:
1960  *  1. Read DPCD
1961  *  2. Configure link according to Receiver Capabilities
1962  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1963  *  4. Check link status on receipt of hot-plug interrupt
1964  */
1965
1966 static void
1967 intel_dp_check_link_status(struct intel_dp *intel_dp)
1968 {
1969         u8 sink_irq_vector;
1970         u8 link_status[DP_LINK_STATUS_SIZE];
1971
1972         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1973                 return;
1974
1975         if (!intel_dp->base.base.crtc)
1976                 return;
1977
1978         /* Try to read receiver status if the link appears to be up */
1979         if (!intel_dp_get_link_status(intel_dp, link_status)) {
1980                 intel_dp_link_down(intel_dp);
1981                 return;
1982         }
1983
1984         /* Now read the DPCD to see if it's actually running */
1985         if (!intel_dp_get_dpcd(intel_dp)) {
1986                 intel_dp_link_down(intel_dp);
1987                 return;
1988         }
1989
1990         /* Try to read the source of the interrupt */
1991         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1992             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1993                 /* Clear interrupt source */
1994                 intel_dp_aux_native_write_1(intel_dp,
1995                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
1996                                             sink_irq_vector);
1997
1998                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1999                         intel_dp_handle_test_request(intel_dp);
2000                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2001                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2002         }
2003
2004         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2005                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2006                               drm_get_encoder_name(&intel_dp->base.base));
2007                 intel_dp_start_link_train(intel_dp);
2008                 intel_dp_complete_link_train(intel_dp);
2009         }
2010 }
2011
2012 static enum drm_connector_status
2013 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2014 {
2015         if (intel_dp_get_dpcd(intel_dp))
2016                 return connector_status_connected;
2017         return connector_status_disconnected;
2018 }
2019
2020 static enum drm_connector_status
2021 ironlake_dp_detect(struct intel_dp *intel_dp)
2022 {
2023         enum drm_connector_status status;
2024
2025         /* Can't disconnect eDP, but you can close the lid... */
2026         if (is_edp(intel_dp)) {
2027                 status = intel_panel_detect(intel_dp->base.base.dev);
2028                 if (status == connector_status_unknown)
2029                         status = connector_status_connected;
2030                 return status;
2031         }
2032
2033         return intel_dp_detect_dpcd(intel_dp);
2034 }
2035
2036 static enum drm_connector_status
2037 g4x_dp_detect(struct intel_dp *intel_dp)
2038 {
2039         struct drm_device *dev = intel_dp->base.base.dev;
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         uint32_t temp, bit;
2042
2043         switch (intel_dp->output_reg) {
2044         case DP_B:
2045                 bit = DPB_HOTPLUG_INT_STATUS;
2046                 break;
2047         case DP_C:
2048                 bit = DPC_HOTPLUG_INT_STATUS;
2049                 break;
2050         case DP_D:
2051                 bit = DPD_HOTPLUG_INT_STATUS;
2052                 break;
2053         default:
2054                 return connector_status_unknown;
2055         }
2056
2057         temp = I915_READ(PORT_HOTPLUG_STAT);
2058
2059         if ((temp & bit) == 0)
2060                 return connector_status_disconnected;
2061
2062         return intel_dp_detect_dpcd(intel_dp);
2063 }
2064
2065 static struct edid *
2066 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2067 {
2068         struct intel_dp *intel_dp = intel_attached_dp(connector);
2069         struct edid     *edid;
2070
2071         ironlake_edp_panel_vdd_on(intel_dp);
2072         edid = drm_get_edid(connector, adapter);
2073         ironlake_edp_panel_vdd_off(intel_dp, false);
2074         return edid;
2075 }
2076
2077 static int
2078 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2079 {
2080         struct intel_dp *intel_dp = intel_attached_dp(connector);
2081         int     ret;
2082
2083         ironlake_edp_panel_vdd_on(intel_dp);
2084         ret = intel_ddc_get_modes(connector, adapter);
2085         ironlake_edp_panel_vdd_off(intel_dp, false);
2086         return ret;
2087 }
2088
2089
2090 /**
2091  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2092  *
2093  * \return true if DP port is connected.
2094  * \return false if DP port is disconnected.
2095  */
2096 static enum drm_connector_status
2097 intel_dp_detect(struct drm_connector *connector, bool force)
2098 {
2099         struct intel_dp *intel_dp = intel_attached_dp(connector);
2100         struct drm_device *dev = intel_dp->base.base.dev;
2101         enum drm_connector_status status;
2102         struct edid *edid = NULL;
2103
2104         intel_dp->has_audio = false;
2105
2106         if (HAS_PCH_SPLIT(dev))
2107                 status = ironlake_dp_detect(intel_dp);
2108         else
2109                 status = g4x_dp_detect(intel_dp);
2110
2111         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2112                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2113                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2114                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2115
2116         if (status != connector_status_connected)
2117                 return status;
2118
2119         if (intel_dp->force_audio) {
2120                 intel_dp->has_audio = intel_dp->force_audio > 0;
2121         } else {
2122                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2123                 if (edid) {
2124                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2125                         connector->display_info.raw_edid = NULL;
2126                         kfree(edid);
2127                 }
2128         }
2129
2130         return connector_status_connected;
2131 }
2132
2133 static int intel_dp_get_modes(struct drm_connector *connector)
2134 {
2135         struct intel_dp *intel_dp = intel_attached_dp(connector);
2136         struct drm_device *dev = intel_dp->base.base.dev;
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         int ret;
2139
2140         /* We should parse the EDID data and find out if it has an audio sink
2141          */
2142
2143         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2144         if (ret) {
2145                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2146                         struct drm_display_mode *newmode;
2147                         list_for_each_entry(newmode, &connector->probed_modes,
2148                                             head) {
2149                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2150                                         intel_dp->panel_fixed_mode =
2151                                                 drm_mode_duplicate(dev, newmode);
2152                                         break;
2153                                 }
2154                         }
2155                 }
2156                 return ret;
2157         }
2158
2159         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2160         if (is_edp(intel_dp)) {
2161                 /* initialize panel mode from VBT if available for eDP */
2162                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2163                         intel_dp->panel_fixed_mode =
2164                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2165                         if (intel_dp->panel_fixed_mode) {
2166                                 intel_dp->panel_fixed_mode->type |=
2167                                         DRM_MODE_TYPE_PREFERRED;
2168                         }
2169                 }
2170                 if (intel_dp->panel_fixed_mode) {
2171                         struct drm_display_mode *mode;
2172                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2173                         drm_mode_probed_add(connector, mode);
2174                         return 1;
2175                 }
2176         }
2177         return 0;
2178 }
2179
2180 static bool
2181 intel_dp_detect_audio(struct drm_connector *connector)
2182 {
2183         struct intel_dp *intel_dp = intel_attached_dp(connector);
2184         struct edid *edid;
2185         bool has_audio = false;
2186
2187         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2188         if (edid) {
2189                 has_audio = drm_detect_monitor_audio(edid);
2190
2191                 connector->display_info.raw_edid = NULL;
2192                 kfree(edid);
2193         }
2194
2195         return has_audio;
2196 }
2197
2198 static int
2199 intel_dp_set_property(struct drm_connector *connector,
2200                       struct drm_property *property,
2201                       uint64_t val)
2202 {
2203         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2204         struct intel_dp *intel_dp = intel_attached_dp(connector);
2205         int ret;
2206
2207         ret = drm_connector_property_set_value(connector, property, val);
2208         if (ret)
2209                 return ret;
2210
2211         if (property == dev_priv->force_audio_property) {
2212                 int i = val;
2213                 bool has_audio;
2214
2215                 if (i == intel_dp->force_audio)
2216                         return 0;
2217
2218                 intel_dp->force_audio = i;
2219
2220                 if (i == 0)
2221                         has_audio = intel_dp_detect_audio(connector);
2222                 else
2223                         has_audio = i > 0;
2224
2225                 if (has_audio == intel_dp->has_audio)
2226                         return 0;
2227
2228                 intel_dp->has_audio = has_audio;
2229                 goto done;
2230         }
2231
2232         if (property == dev_priv->broadcast_rgb_property) {
2233                 if (val == !!intel_dp->color_range)
2234                         return 0;
2235
2236                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2237                 goto done;
2238         }
2239
2240         return -EINVAL;
2241
2242 done:
2243         if (intel_dp->base.base.crtc) {
2244                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2245                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2246                                          crtc->x, crtc->y,
2247                                          crtc->fb);
2248         }
2249
2250         return 0;
2251 }
2252
2253 static void
2254 intel_dp_destroy(struct drm_connector *connector)
2255 {
2256         struct drm_device *dev = connector->dev;
2257
2258         if (intel_dpd_is_edp(dev))
2259                 intel_panel_destroy_backlight(dev);
2260
2261         drm_sysfs_connector_remove(connector);
2262         drm_connector_cleanup(connector);
2263         kfree(connector);
2264 }
2265
2266 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2267 {
2268         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2269
2270         i2c_del_adapter(&intel_dp->adapter);
2271         drm_encoder_cleanup(encoder);
2272         if (is_edp(intel_dp)) {
2273                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2274                 ironlake_panel_vdd_off_sync(intel_dp);
2275         }
2276         kfree(intel_dp);
2277 }
2278
2279 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2280         .dpms = intel_dp_dpms,
2281         .mode_fixup = intel_dp_mode_fixup,
2282         .prepare = intel_dp_prepare,
2283         .mode_set = intel_dp_mode_set,
2284         .commit = intel_dp_commit,
2285 };
2286
2287 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2288         .dpms = drm_helper_connector_dpms,
2289         .detect = intel_dp_detect,
2290         .fill_modes = drm_helper_probe_single_connector_modes,
2291         .set_property = intel_dp_set_property,
2292         .destroy = intel_dp_destroy,
2293 };
2294
2295 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2296         .get_modes = intel_dp_get_modes,
2297         .mode_valid = intel_dp_mode_valid,
2298         .best_encoder = intel_best_encoder,
2299 };
2300
2301 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2302         .destroy = intel_dp_encoder_destroy,
2303 };
2304
2305 static void
2306 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2307 {
2308         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2309
2310         intel_dp_check_link_status(intel_dp);
2311 }
2312
2313 /* Return which DP Port should be selected for Transcoder DP control */
2314 int
2315 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2316 {
2317         struct drm_device *dev = crtc->dev;
2318         struct drm_mode_config *mode_config = &dev->mode_config;
2319         struct drm_encoder *encoder;
2320
2321         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2322                 struct intel_dp *intel_dp;
2323
2324                 if (encoder->crtc != crtc)
2325                         continue;
2326
2327                 intel_dp = enc_to_intel_dp(encoder);
2328                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2329                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2330                         return intel_dp->output_reg;
2331         }
2332
2333         return -1;
2334 }
2335
2336 /* check the VBT to see whether the eDP is on DP-D port */
2337 bool intel_dpd_is_edp(struct drm_device *dev)
2338 {
2339         struct drm_i915_private *dev_priv = dev->dev_private;
2340         struct child_device_config *p_child;
2341         int i;
2342
2343         if (!dev_priv->child_dev_num)
2344                 return false;
2345
2346         for (i = 0; i < dev_priv->child_dev_num; i++) {
2347                 p_child = dev_priv->child_dev + i;
2348
2349                 if (p_child->dvo_port == PORT_IDPD &&
2350                     p_child->device_type == DEVICE_TYPE_eDP)
2351                         return true;
2352         }
2353         return false;
2354 }
2355
2356 static void
2357 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2358 {
2359         intel_attach_force_audio_property(connector);
2360         intel_attach_broadcast_rgb_property(connector);
2361 }
2362
2363 void
2364 intel_dp_init(struct drm_device *dev, int output_reg)
2365 {
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         struct drm_connector *connector;
2368         struct intel_dp *intel_dp;
2369         struct intel_encoder *intel_encoder;
2370         struct intel_connector *intel_connector;
2371         const char *name = NULL;
2372         int type;
2373
2374         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2375         if (!intel_dp)
2376                 return;
2377
2378         intel_dp->output_reg = output_reg;
2379         intel_dp->dpms_mode = -1;
2380
2381         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2382         if (!intel_connector) {
2383                 kfree(intel_dp);
2384                 return;
2385         }
2386         intel_encoder = &intel_dp->base;
2387
2388         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2389                 if (intel_dpd_is_edp(dev))
2390                         intel_dp->is_pch_edp = true;
2391
2392         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2393                 type = DRM_MODE_CONNECTOR_eDP;
2394                 intel_encoder->type = INTEL_OUTPUT_EDP;
2395         } else {
2396                 type = DRM_MODE_CONNECTOR_DisplayPort;
2397                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2398         }
2399
2400         connector = &intel_connector->base;
2401         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2402         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2403
2404         connector->polled = DRM_CONNECTOR_POLL_HPD;
2405
2406         if (output_reg == DP_B || output_reg == PCH_DP_B)
2407                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2408         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2409                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2410         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2411                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2412
2413         if (is_edp(intel_dp)) {
2414                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2415                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2416                                   ironlake_panel_vdd_work);
2417         }
2418
2419         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2420         connector->interlace_allowed = true;
2421         connector->doublescan_allowed = 0;
2422
2423         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2424                          DRM_MODE_ENCODER_TMDS);
2425         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2426
2427         intel_connector_attach_encoder(intel_connector, intel_encoder);
2428         drm_sysfs_connector_add(connector);
2429
2430         /* Set up the DDC bus. */
2431         switch (output_reg) {
2432                 case DP_A:
2433                         name = "DPDDC-A";
2434                         break;
2435                 case DP_B:
2436                 case PCH_DP_B:
2437                         dev_priv->hotplug_supported_mask |=
2438                                 HDMIB_HOTPLUG_INT_STATUS;
2439                         name = "DPDDC-B";
2440                         break;
2441                 case DP_C:
2442                 case PCH_DP_C:
2443                         dev_priv->hotplug_supported_mask |=
2444                                 HDMIC_HOTPLUG_INT_STATUS;
2445                         name = "DPDDC-C";
2446                         break;
2447                 case DP_D:
2448                 case PCH_DP_D:
2449                         dev_priv->hotplug_supported_mask |=
2450                                 HDMID_HOTPLUG_INT_STATUS;
2451                         name = "DPDDC-D";
2452                         break;
2453         }
2454
2455         /* Cache some DPCD data in the eDP case */
2456         if (is_edp(intel_dp)) {
2457                 bool ret;
2458                 struct edp_power_seq    cur, vbt;
2459                 u32 pp_on, pp_off, pp_div;
2460
2461                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2462                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2463                 pp_div = I915_READ(PCH_PP_DIVISOR);
2464
2465                 /* Pull timing values out of registers */
2466                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2467                         PANEL_POWER_UP_DELAY_SHIFT;
2468
2469                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2470                         PANEL_LIGHT_ON_DELAY_SHIFT;
2471
2472                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2473                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2474
2475                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2476                         PANEL_POWER_DOWN_DELAY_SHIFT;
2477
2478                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2479                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2480
2481                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2482                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2483
2484                 vbt = dev_priv->edp.pps;
2485
2486                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2487                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2488
2489 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2490
2491                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2492                 intel_dp->backlight_on_delay = get_delay(t8);
2493                 intel_dp->backlight_off_delay = get_delay(t9);
2494                 intel_dp->panel_power_down_delay = get_delay(t10);
2495                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2496
2497                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2498                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2499                               intel_dp->panel_power_cycle_delay);
2500
2501                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2502                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2503
2504                 ironlake_edp_panel_vdd_on(intel_dp);
2505                 ret = intel_dp_get_dpcd(intel_dp);
2506                 ironlake_edp_panel_vdd_off(intel_dp, false);
2507
2508                 if (ret) {
2509                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2510                                 dev_priv->no_aux_handshake =
2511                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2512                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2513                 } else {
2514                         /* if this fails, presume the device is a ghost */
2515                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2516                         intel_dp_encoder_destroy(&intel_dp->base.base);
2517                         intel_dp_destroy(&intel_connector->base);
2518                         return;
2519                 }
2520         }
2521
2522         intel_dp_i2c_init(intel_dp, intel_connector, name);
2523
2524         intel_encoder->hot_plug = intel_dp_hot_plug;
2525
2526         if (is_edp(intel_dp)) {
2527                 dev_priv->int_edp_connector = connector;
2528                 intel_panel_setup_backlight(dev);
2529         }
2530
2531         intel_dp_add_properties(intel_dp, connector);
2532
2533         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2534          * 0xd.  Failure to do so will result in spurious interrupts being
2535          * generated on the port when a cable is not attached.
2536          */
2537         if (IS_G4X(dev) && !IS_GM45(dev)) {
2538                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2539                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2540         }
2541 }