drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 static int
 113 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 114 {
 115         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 116
 117         switch (max_link_bw) {
 118         case DP_LINK_BW_1_62:
 119         case DP_LINK_BW_2_7:
 120                 break;
 121         default:
 122                 max_link_bw = DP_LINK_BW_1_62;
 123                 break;
 124         }
 125         return max_link_bw;
 126 }
 127
 128 /*
 129  * The units on the numbers in the next two are... bizarre.  Examples will
 130  * make it clearer; this one parallels an example in the eDP spec.
 131  *
 132  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 133  *
 134  *     270000 * 1 * 8 / 10 == 216000
 135  *
 136  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 137  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 138  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 139  * 119000.  At 18bpp that's 2142000 kilobits per second.
 140  *
 141  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 142  * get the result in decakilobits instead of kilobits.
 143  */
 144
 145 static int
 146 intel_dp_link_required(int pixel_clock, int bpp)
 147 {
 148         return (pixel_clock * bpp + 9) / 10;
 149 }
 150
 151 static int
 152 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 153 {
 154         return (max_link_clock * max_lanes * 8) / 10;
 155 }
 156
 157 static int
 158 intel_dp_mode_valid(struct drm_connector *connector,
 159                     struct drm_display_mode *mode)
 160 {
 161         struct intel_dp *intel_dp = intel_attached_dp(connector);
 162         struct intel_connector *intel_connector = to_intel_connector(connector);
 163         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 164         int target_clock = mode->clock;
 165         int max_rate, mode_rate, max_lanes, max_link_clock;
 166
 167         if (is_edp(intel_dp) && fixed_mode) {
 168                 if (mode->hdisplay > fixed_mode->hdisplay)
 169                         return MODE_PANEL;
 170
 171                 if (mode->vdisplay > fixed_mode->vdisplay)
 172                         return MODE_PANEL;
 173
 174                 target_clock = fixed_mode->clock;
 175         }
 176
 177         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 178         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 179
 180         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 181         mode_rate = intel_dp_link_required(target_clock, 18);
 182
 183         if (mode_rate > max_rate)
 184                 return MODE_CLOCK_HIGH;
 185
 186         if (mode->clock < 10000)
 187                 return MODE_CLOCK_LOW;
 188
 189         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 190                 return MODE_H_ILLEGAL;
 191
 192         return MODE_OK;
 193 }
 194
 195 static uint32_t
 196 pack_aux(uint8_t *src, int src_bytes)
 197 {
 198         int     i;
 199         uint32_t v = 0;
 200
 201         if (src_bytes > 4)
 202                 src_bytes = 4;
 203         for (i = 0; i < src_bytes; i++)
 204                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 205         return v;
 206 }
 207
 208 static void
 209 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 210 {
 211         int i;
 212         if (dst_bytes > 4)
 213                 dst_bytes = 4;
 214         for (i = 0; i < dst_bytes; i++)
 215                 dst[i] = src >> ((3-i) * 8);
 216 }
 217
 218 /* hrawclock is 1/4 the FSB frequency */
 219 static int
 220 intel_hrawclk(struct drm_device *dev)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         uint32_t clkcfg;
 224
 225         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 226         if (IS_VALLEYVIEW(dev))
 227                 return 200;
 228
 229         clkcfg = I915_READ(CLKCFG);
 230         switch (clkcfg & CLKCFG_FSB_MASK) {
 231         case CLKCFG_FSB_400:
 232                 return 100;
 233         case CLKCFG_FSB_533:
 234                 return 133;
 235         case CLKCFG_FSB_667:
 236                 return 166;
 237         case CLKCFG_FSB_800:
 238                 return 200;
 239         case CLKCFG_FSB_1067:
 240                 return 266;
 241         case CLKCFG_FSB_1333:
 242                 return 333;
 243         /* these two are just a guess; one of them might be right */
 244         case CLKCFG_FSB_1600:
 245         case CLKCFG_FSB_1600_ALT:
 246                 return 400;
 247         default:
 248                 return 133;
 249         }
 250 }
 251
 252 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 253 {
 254         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         u32 pp_stat_reg;
 257
 258         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 259         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 260 }
 261
 262 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 263 {
 264         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 265         struct drm_i915_private *dev_priv = dev->dev_private;
 266         u32 pp_ctrl_reg;
 267
 268         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 269         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 270 }
 271
 272 static void
 273 intel_dp_check_edp(struct intel_dp *intel_dp)
 274 {
 275         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         u32 pp_stat_reg, pp_ctrl_reg;
 278
 279         if (!is_edp(intel_dp))
 280                 return;
 281
 282         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 283         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 284
 285         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 286                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 287                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 288                                 I915_READ(pp_stat_reg),
 289                                 I915_READ(pp_ctrl_reg));
 290         }
 291 }
 292
 293 static uint32_t
 294 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_device *dev = intel_dig_port->base.base.dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 300         uint32_t status;
 301         bool done;
 302
 303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 304         if (has_aux_irq)
 305                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 306                                           msecs_to_jiffies(10));
 307         else
 308                 done = wait_for_atomic(C, 10) == 0;
 309         if (!done)
 310                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 311                           has_aux_irq);
 312 #undef C
 313
 314         return status;
 315 }
 316
 317 static int
 318 intel_dp_aux_ch(struct intel_dp *intel_dp,
 319                 uint8_t *send, int send_bytes,
 320                 uint8_t *recv, int recv_size)
 321 {
 322         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 323         struct drm_device *dev = intel_dig_port->base.base.dev;
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 326         uint32_t ch_data = ch_ctl + 4;
 327         int i, ret, recv_bytes;
 328         uint32_t status;
 329         uint32_t aux_clock_divider;
 330         int try, precharge;
 331         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 332
 333         /* dp aux is extremely sensitive to irq latency, hence request the
 334          * lowest possible wakeup latency and so prevent the cpu from going into
 335          * deep sleep states.
 336          */
 337         pm_qos_update_request(&dev_priv->pm_qos, 0);
 338
 339         intel_dp_check_edp(intel_dp);
 340         /* The clock divider is based off the hrawclk,
 341          * and would like to run at 2MHz. So, take the
 342          * hrawclk value and divide by 2 and use that
 343          *
 344          * Note that PCH attached eDP panels should use a 125MHz input
 345          * clock divider.
 346          */
 347         if (is_cpu_edp(intel_dp)) {
 348                 if (HAS_DDI(dev))
 349                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 350                 else if (IS_VALLEYVIEW(dev))
 351                         aux_clock_divider = 100;
 352                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 353                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 354                 else
 355                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 356         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 357                 /* Workaround for non-ULT HSW */
 358                 aux_clock_divider = 74;
 359         } else if (HAS_PCH_SPLIT(dev)) {
 360                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 361         } else {
 362                 aux_clock_divider = intel_hrawclk(dev) / 2;
 363         }
 364
 365         if (IS_GEN6(dev))
 366                 precharge = 3;
 367         else
 368                 precharge = 5;
 369
 370         /* Try to wait for any previous AUX channel activity */
 371         for (try = 0; try < 3; try++) {
 372                 status = I915_READ_NOTRACE(ch_ctl);
 373                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 374                         break;
 375                 msleep(1);
 376         }
 377
 378         if (try == 3) {
 379                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 380                      I915_READ(ch_ctl));
 381                 ret = -EBUSY;
 382                 goto out;
 383         }
 384
 385         /* Must try at least 3 times according to DP spec */
 386         for (try = 0; try < 5; try++) {
 387                 /* Load the send data into the aux channel data registers */
 388                 for (i = 0; i < send_bytes; i += 4)
 389                         I915_WRITE(ch_data + i,
 390                                    pack_aux(send + i, send_bytes - i));
 391
 392                 /* Send the command and wait for it to complete */
 393                 I915_WRITE(ch_ctl,
 394                            DP_AUX_CH_CTL_SEND_BUSY |
 395                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 396                            DP_AUX_CH_CTL_TIME_OUT_400us |
 397                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 398                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 399                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 400                            DP_AUX_CH_CTL_DONE |
 401                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 402                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 403
 404                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 405
 406                 /* Clear done status and any errors */
 407                 I915_WRITE(ch_ctl,
 408                            status |
 409                            DP_AUX_CH_CTL_DONE |
 410                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 411                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 412
 413                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 414                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 415                         continue;
 416                 if (status & DP_AUX_CH_CTL_DONE)
 417                         break;
 418         }
 419
 420         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 421                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 422                 ret = -EBUSY;
 423                 goto out;
 424         }
 425
 426         /* Check for timeout or receive error.
 427          * Timeouts occur when the sink is not connected
 428          */
 429         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 430                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 431                 ret = -EIO;
 432                 goto out;
 433         }
 434
 435         /* Timeouts occur when the device isn't connected, so they're
 436          * "normal" -- don't fill the kernel log with these */
 437         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 438                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 439                 ret = -ETIMEDOUT;
 440                 goto out;
 441         }
 442
 443         /* Unload any bytes sent back from the other side */
 444         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 445                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 446         if (recv_bytes > recv_size)
 447                 recv_bytes = recv_size;
 448
 449         for (i = 0; i < recv_bytes; i += 4)
 450                 unpack_aux(I915_READ(ch_data + i),
 451                            recv + i, recv_bytes - i);
 452
 453         ret = recv_bytes;
 454 out:
 455         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 456
 457         return ret;
 458 }
 459
 460 /* Write data to the aux channel in native mode */
 461 static int
 462 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 463                           uint16_t address, uint8_t *send, int send_bytes)
 464 {
 465         int ret;
 466         uint8_t msg[20];
 467         int msg_bytes;
 468         uint8_t ack;
 469
 470         intel_dp_check_edp(intel_dp);
 471         if (send_bytes > 16)
 472                 return -1;
 473         msg[0] = AUX_NATIVE_WRITE << 4;
 474         msg[1] = address >> 8;
 475         msg[2] = address & 0xff;
 476         msg[3] = send_bytes - 1;
 477         memcpy(&msg[4], send, send_bytes);
 478         msg_bytes = send_bytes + 4;
 479         for (;;) {
 480                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 481                 if (ret < 0)
 482                         return ret;
 483                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 484                         break;
 485                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 486                         udelay(100);
 487                 else
 488                         return -EIO;
 489         }
 490         return send_bytes;
 491 }
 492
 493 /* Write a single byte to the aux channel in native mode */
 494 static int
 495 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 496                             uint16_t address, uint8_t byte)
 497 {
 498         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 499 }
 500
 501 /* read bytes from a native aux channel */
 502 static int
 503 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 504                          uint16_t address, uint8_t *recv, int recv_bytes)
 505 {
 506         uint8_t msg[4];
 507         int msg_bytes;
 508         uint8_t reply[20];
 509         int reply_bytes;
 510         uint8_t ack;
 511         int ret;
 512
 513         intel_dp_check_edp(intel_dp);
 514         msg[0] = AUX_NATIVE_READ << 4;
 515         msg[1] = address >> 8;
 516         msg[2] = address & 0xff;
 517         msg[3] = recv_bytes - 1;
 518
 519         msg_bytes = 4;
 520         reply_bytes = recv_bytes + 1;
 521
 522         for (;;) {
 523                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 524                                       reply, reply_bytes);
 525                 if (ret == 0)
 526                         return -EPROTO;
 527                 if (ret < 0)
 528                         return ret;
 529                 ack = reply[0];
 530                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 531                         memcpy(recv, reply + 1, ret - 1);
 532                         return ret - 1;
 533                 }
 534                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 535                         udelay(100);
 536                 else
 537                         return -EIO;
 538         }
 539 }
 540
 541 static int
 542 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 543                     uint8_t write_byte, uint8_t *read_byte)
 544 {
 545         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 546         struct intel_dp *intel_dp = container_of(adapter,
 547                                                 struct intel_dp,
 548                                                 adapter);
 549         uint16_t address = algo_data->address;
 550         uint8_t msg[5];
 551         uint8_t reply[2];
 552         unsigned retry;
 553         int msg_bytes;
 554         int reply_bytes;
 555         int ret;
 556
 557         intel_dp_check_edp(intel_dp);
 558         /* Set up the command byte */
 559         if (mode & MODE_I2C_READ)
 560                 msg[0] = AUX_I2C_READ << 4;
 561         else
 562                 msg[0] = AUX_I2C_WRITE << 4;
 563
 564         if (!(mode & MODE_I2C_STOP))
 565                 msg[0] |= AUX_I2C_MOT << 4;
 566
 567         msg[1] = address >> 8;
 568         msg[2] = address;
 569
 570         switch (mode) {
 571         case MODE_I2C_WRITE:
 572                 msg[3] = 0;
 573                 msg[4] = write_byte;
 574                 msg_bytes = 5;
 575                 reply_bytes = 1;
 576                 break;
 577         case MODE_I2C_READ:
 578                 msg[3] = 0;
 579                 msg_bytes = 4;
 580                 reply_bytes = 2;
 581                 break;
 582         default:
 583                 msg_bytes = 3;
 584                 reply_bytes = 1;
 585                 break;
 586         }
 587
 588         for (retry = 0; retry < 5; retry++) {
 589                 ret = intel_dp_aux_ch(intel_dp,
 590                                       msg, msg_bytes,
 591                                       reply, reply_bytes);
 592                 if (ret < 0) {
 593                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 594                         return ret;
 595                 }
 596
 597                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 598                 case AUX_NATIVE_REPLY_ACK:
 599                         /* I2C-over-AUX Reply field is only valid
 600                          * when paired with AUX ACK.
 601                          */
 602                         break;
 603                 case AUX_NATIVE_REPLY_NACK:
 604                         DRM_DEBUG_KMS("aux_ch native nack\n");
 605                         return -EREMOTEIO;
 606                 case AUX_NATIVE_REPLY_DEFER:
 607                         udelay(100);
 608                         continue;
 609                 default:
 610                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 611                                   reply[0]);
 612                         return -EREMOTEIO;
 613                 }
 614
 615                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 616                 case AUX_I2C_REPLY_ACK:
 617                         if (mode == MODE_I2C_READ) {
 618                                 *read_byte = reply[1];
 619                         }
 620                         return reply_bytes - 1;
 621                 case AUX_I2C_REPLY_NACK:
 622                         DRM_DEBUG_KMS("aux_i2c nack\n");
 623                         return -EREMOTEIO;
 624                 case AUX_I2C_REPLY_DEFER:
 625                         DRM_DEBUG_KMS("aux_i2c defer\n");
 626                         udelay(100);
 627                         break;
 628                 default:
 629                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 630                         return -EREMOTEIO;
 631                 }
 632         }
 633
 634         DRM_ERROR("too many retries, giving up\n");
 635         return -EREMOTEIO;
 636 }
 637
 638 static int
 639 intel_dp_i2c_init(struct intel_dp *intel_dp,
 640                   struct intel_connector *intel_connector, const char *name)
 641 {
 642         int     ret;
 643
 644         DRM_DEBUG_KMS("i2c_init %s\n", name);
 645         intel_dp->algo.running = false;
 646         intel_dp->algo.address = 0;
 647         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 648
 649         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 650         intel_dp->adapter.owner = THIS_MODULE;
 651         intel_dp->adapter.class = I2C_CLASS_DDC;
 652         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 653         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 654         intel_dp->adapter.algo_data = &intel_dp->algo;
 655         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 656
 657         ironlake_edp_panel_vdd_on(intel_dp);
 658         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 659         ironlake_edp_panel_vdd_off(intel_dp, false);
 660         return ret;
 661 }
 662
 663 bool
 664 intel_dp_compute_config(struct intel_encoder *encoder,
 665                         struct intel_crtc_config *pipe_config)
 666 {
 667         struct drm_device *dev = encoder->base.dev;
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 670         struct drm_display_mode *mode = &pipe_config->requested_mode;
 671         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 672         struct intel_connector *intel_connector = intel_dp->attached_connector;
 673         int lane_count, clock;
 674         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 675         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 676         int bpp, mode_rate;
 677         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 678         int target_clock, link_avail, link_clock;
 679
 680         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
 681                 pipe_config->has_pch_encoder = true;
 682
 683         pipe_config->has_dp_encoder = true;
 684
 685         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 686                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 687                                        adjusted_mode);
 688                 intel_pch_panel_fitting(dev,
 689                                         intel_connector->panel.fitting_mode,
 690                                         mode, adjusted_mode);
 691         }
 692         /* We need to take the panel's fixed mode into account. */
 693         target_clock = adjusted_mode->clock;
 694
 695         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 696                 return false;
 697
 698         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 699                       "max bw %02x pixel clock %iKHz\n",
 700                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 701
 702         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 703          * bpc in between. */
 704         bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
 705         if (is_edp(intel_dp) && dev_priv->edp.bpp)
 706                 bpp = min_t(int, bpp, dev_priv->edp.bpp);
 707
 708         for (; bpp >= 6*3; bpp -= 2*3) {
 709                 mode_rate = intel_dp_link_required(target_clock, bpp);
 710
 711                 for (clock = 0; clock <= max_clock; clock++) {
 712                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 713                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 714                                 link_avail = intel_dp_max_data_rate(link_clock,
 715                                                                     lane_count);
 716
 717                                 if (mode_rate <= link_avail) {
 718                                         goto found;
 719                                 }
 720                         }
 721                 }
 722         }
 723
 724         return false;
 725
 726 found:
 727         if (intel_dp->color_range_auto) {
 728                 /*
 729                  * See:
 730                  * CEA-861-E - 5.1 Default Encoding Parameters
 731                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 732                  */
 733                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 734                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 735                 else
 736                         intel_dp->color_range = 0;
 737         }
 738
 739         if (intel_dp->color_range)
 740                 pipe_config->limited_color_range = true;
 741
 742         intel_dp->link_bw = bws[clock];
 743         intel_dp->lane_count = lane_count;
 744         adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 745         pipe_config->pipe_bpp = bpp;
 746         pipe_config->pixel_target_clock = target_clock;
 747
 748         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 749                       intel_dp->link_bw, intel_dp->lane_count,
 750                       adjusted_mode->clock, bpp);
 751         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 752                       mode_rate, link_avail);
 753
 754         intel_link_compute_m_n(bpp, lane_count,
 755                                target_clock, adjusted_mode->clock,
 756                                &pipe_config->dp_m_n);
 757
 758         return true;
 759 }
 760
 761 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 762 {
 763         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 764         intel_dp->link_configuration[0] = intel_dp->link_bw;
 765         intel_dp->link_configuration[1] = intel_dp->lane_count;
 766         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 767         /*
 768          * Check for DPCD version > 1.1 and enhanced framing support
 769          */
 770         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 771             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 772                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 773         }
 774 }
 775
 776 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 777 {
 778         struct drm_device *dev = crtc->dev;
 779         struct drm_i915_private *dev_priv = dev->dev_private;
 780         u32 dpa_ctl;
 781
 782         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 783         dpa_ctl = I915_READ(DP_A);
 784         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 785
 786         if (clock < 200000) {
 787                 /* For a long time we've carried around a ILK-DevA w/a for the
 788                  * 160MHz clock. If we're really unlucky, it's still required.
 789                  */
 790                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 791                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 792         } else {
 793                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 794         }
 795
 796         I915_WRITE(DP_A, dpa_ctl);
 797
 798         POSTING_READ(DP_A);
 799         udelay(500);
 800 }
 801
 802 static void
 803 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 804                   struct drm_display_mode *adjusted_mode)
 805 {
 806         struct drm_device *dev = encoder->dev;
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 809         struct drm_crtc *crtc = encoder->crtc;
 810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 811
 812         /*
 813          * There are four kinds of DP registers:
 814          *
 815          *      IBX PCH
 816          *      SNB CPU
 817          *      IVB CPU
 818          *      CPT PCH
 819          *
 820          * IBX PCH and CPU are the same for almost everything,
 821          * except that the CPU DP PLL is configured in this
 822          * register
 823          *
 824          * CPT PCH is quite different, having many bits moved
 825          * to the TRANS_DP_CTL register instead. That
 826          * configuration happens (oddly) in ironlake_pch_enable
 827          */
 828
 829         /* Preserve the BIOS-computed detected bit. This is
 830          * supposed to be read-only.
 831          */
 832         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 833
 834         /* Handle DP bits in common between all three register formats */
 835         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 836
 837         switch (intel_dp->lane_count) {
 838         case 1:
 839                 intel_dp->DP |= DP_PORT_WIDTH_1;
 840                 break;
 841         case 2:
 842                 intel_dp->DP |= DP_PORT_WIDTH_2;
 843                 break;
 844         case 4:
 845                 intel_dp->DP |= DP_PORT_WIDTH_4;
 846                 break;
 847         }
 848         if (intel_dp->has_audio) {
 849                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 850                                  pipe_name(intel_crtc->pipe));
 851                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 852                 intel_write_eld(encoder, adjusted_mode);
 853         }
 854
 855         intel_dp_init_link_config(intel_dp);
 856
 857         /* Split out the IBX/CPU vs CPT settings */
 858
 859         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 860                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 861                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 862                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 863                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 864                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 865
 866                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 867                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 868
 869                 intel_dp->DP |= intel_crtc->pipe << 29;
 870
 871                 /* don't miss out required setting for eDP */
 872                 if (adjusted_mode->clock < 200000)
 873                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 874                 else
 875                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 876         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 877                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 878                         intel_dp->DP |= intel_dp->color_range;
 879
 880                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 881                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 882                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 883                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 884                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 885
 886                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 887                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 888
 889                 if (intel_crtc->pipe == 1)
 890                         intel_dp->DP |= DP_PIPEB_SELECT;
 891
 892                 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 893                         /* don't miss out required setting for eDP */
 894                         if (adjusted_mode->clock < 200000)
 895                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 896                         else
 897                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 898                 }
 899         } else {
 900                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 901         }
 902
 903         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 904                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 905 }
 906
 907 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 908 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 909
 910 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 911 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 912
 913 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 914 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 915
 916 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 917                                        u32 mask,
 918                                        u32 value)
 919 {
 920         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 921         struct drm_i915_private *dev_priv = dev->dev_private;
 922         u32 pp_stat_reg, pp_ctrl_reg;
 923
 924         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 925         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 926
 927         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 928                         mask, value,
 929                         I915_READ(pp_stat_reg),
 930                         I915_READ(pp_ctrl_reg));
 931
 932         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 933                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 934                                 I915_READ(pp_stat_reg),
 935                                 I915_READ(pp_ctrl_reg));
 936         }
 937 }
 938
 939 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 940 {
 941         DRM_DEBUG_KMS("Wait for panel power on\n");
 942         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 943 }
 944
 945 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 946 {
 947         DRM_DEBUG_KMS("Wait for panel power off time\n");
 948         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 949 }
 950
 951 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 952 {
 953         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 954         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 955 }
 956
 957
 958 /* Read the current pp_control value, unlocking the register if it
 959  * is locked
 960  */
 961
 962 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 963 {
 964         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966         u32 control;
 967         u32 pp_ctrl_reg;
 968
 969         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 970         control = I915_READ(pp_ctrl_reg);
 971
 972         control &= ~PANEL_UNLOCK_MASK;
 973         control |= PANEL_UNLOCK_REGS;
 974         return control;
 975 }
 976
 977 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 978 {
 979         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 980         struct drm_i915_private *dev_priv = dev->dev_private;
 981         u32 pp;
 982         u32 pp_stat_reg, pp_ctrl_reg;
 983
 984         if (!is_edp(intel_dp))
 985                 return;
 986         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 987
 988         WARN(intel_dp->want_panel_vdd,
 989              "eDP VDD already requested on\n");
 990
 991         intel_dp->want_panel_vdd = true;
 992
 993         if (ironlake_edp_have_panel_vdd(intel_dp)) {
 994                 DRM_DEBUG_KMS("eDP VDD already on\n");
 995                 return;
 996         }
 997
 998         if (!ironlake_edp_have_panel_power(intel_dp))
 999                 ironlake_wait_panel_power_cycle(intel_dp);
1000
1001         pp = ironlake_get_pp_control(intel_dp);
1002         pp |= EDP_FORCE_VDD;
1003
1004         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1005         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1006
1007         I915_WRITE(pp_ctrl_reg, pp);
1008         POSTING_READ(pp_ctrl_reg);
1009         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1010                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1011         /*
1012          * If the panel wasn't on, delay before accessing aux channel
1013          */
1014         if (!ironlake_edp_have_panel_power(intel_dp)) {
1015                 DRM_DEBUG_KMS("eDP was not running\n");
1016                 msleep(intel_dp->panel_power_up_delay);
1017         }
1018 }
1019
1020 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1021 {
1022         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1023         struct drm_i915_private *dev_priv = dev->dev_private;
1024         u32 pp;
1025         u32 pp_stat_reg, pp_ctrl_reg;
1026
1027         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1028
1029         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1030                 pp = ironlake_get_pp_control(intel_dp);
1031                 pp &= ~EDP_FORCE_VDD;
1032
1033                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1034                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1035
1036                 I915_WRITE(pp_ctrl_reg, pp);
1037                 POSTING_READ(pp_ctrl_reg);
1038
1039                 /* Make sure sequencer is idle before allowing subsequent activity */
1040                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1041                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1042                 msleep(intel_dp->panel_power_down_delay);
1043         }
1044 }
1045
1046 static void ironlake_panel_vdd_work(struct work_struct *__work)
1047 {
1048         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1049                                                  struct intel_dp, panel_vdd_work);
1050         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1051
1052         mutex_lock(&dev->mode_config.mutex);
1053         ironlake_panel_vdd_off_sync(intel_dp);
1054         mutex_unlock(&dev->mode_config.mutex);
1055 }
1056
1057 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1058 {
1059         if (!is_edp(intel_dp))
1060                 return;
1061
1062         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1063         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1064
1065         intel_dp->want_panel_vdd = false;
1066
1067         if (sync) {
1068                 ironlake_panel_vdd_off_sync(intel_dp);
1069         } else {
1070                 /*
1071                  * Queue the timer to fire a long
1072                  * time from now (relative to the power down delay)
1073                  * to keep the panel power up across a sequence of operations
1074                  */
1075                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1076                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1077         }
1078 }
1079
1080 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1081 {
1082         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1083         struct drm_i915_private *dev_priv = dev->dev_private;
1084         u32 pp;
1085         u32 pp_ctrl_reg;
1086
1087         if (!is_edp(intel_dp))
1088                 return;
1089
1090         DRM_DEBUG_KMS("Turn eDP power on\n");
1091
1092         if (ironlake_edp_have_panel_power(intel_dp)) {
1093                 DRM_DEBUG_KMS("eDP power already on\n");
1094                 return;
1095         }
1096
1097         ironlake_wait_panel_power_cycle(intel_dp);
1098
1099         pp = ironlake_get_pp_control(intel_dp);
1100         if (IS_GEN5(dev)) {
1101                 /* ILK workaround: disable reset around power sequence */
1102                 pp &= ~PANEL_POWER_RESET;
1103                 I915_WRITE(PCH_PP_CONTROL, pp);
1104                 POSTING_READ(PCH_PP_CONTROL);
1105         }
1106
1107         pp |= POWER_TARGET_ON;
1108         if (!IS_GEN5(dev))
1109                 pp |= PANEL_POWER_RESET;
1110
1111         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1112
1113         I915_WRITE(pp_ctrl_reg, pp);
1114         POSTING_READ(pp_ctrl_reg);
1115
1116         ironlake_wait_panel_on(intel_dp);
1117
1118         if (IS_GEN5(dev)) {
1119                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1120                 I915_WRITE(PCH_PP_CONTROL, pp);
1121                 POSTING_READ(PCH_PP_CONTROL);
1122         }
1123 }
1124
1125 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1126 {
1127         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129         u32 pp;
1130         u32 pp_ctrl_reg;
1131
1132         if (!is_edp(intel_dp))
1133                 return;
1134
1135         DRM_DEBUG_KMS("Turn eDP power off\n");
1136
1137         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1138
1139         pp = ironlake_get_pp_control(intel_dp);
1140         /* We need to switch off panel power _and_ force vdd, for otherwise some
1141          * panels get very unhappy and cease to work. */
1142         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1143
1144         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1145
1146         I915_WRITE(pp_ctrl_reg, pp);
1147         POSTING_READ(pp_ctrl_reg);
1148
1149         intel_dp->want_panel_vdd = false;
1150
1151         ironlake_wait_panel_off(intel_dp);
1152 }
1153
1154 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1155 {
1156         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1157         struct drm_device *dev = intel_dig_port->base.base.dev;
1158         struct drm_i915_private *dev_priv = dev->dev_private;
1159         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1160         u32 pp;
1161         u32 pp_ctrl_reg;
1162
1163         if (!is_edp(intel_dp))
1164                 return;
1165
1166         DRM_DEBUG_KMS("\n");
1167         /*
1168          * If we enable the backlight right away following a panel power
1169          * on, we may see slight flicker as the panel syncs with the eDP
1170          * link.  So delay a bit to make sure the image is solid before
1171          * allowing it to appear.
1172          */
1173         msleep(intel_dp->backlight_on_delay);
1174         pp = ironlake_get_pp_control(intel_dp);
1175         pp |= EDP_BLC_ENABLE;
1176
1177         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1178
1179         I915_WRITE(pp_ctrl_reg, pp);
1180         POSTING_READ(pp_ctrl_reg);
1181
1182         intel_panel_enable_backlight(dev, pipe);
1183 }
1184
1185 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1186 {
1187         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1188         struct drm_i915_private *dev_priv = dev->dev_private;
1189         u32 pp;
1190         u32 pp_ctrl_reg;
1191
1192         if (!is_edp(intel_dp))
1193                 return;
1194
1195         intel_panel_disable_backlight(dev);
1196
1197         DRM_DEBUG_KMS("\n");
1198         pp = ironlake_get_pp_control(intel_dp);
1199         pp &= ~EDP_BLC_ENABLE;
1200
1201         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1202
1203         I915_WRITE(pp_ctrl_reg, pp);
1204         POSTING_READ(pp_ctrl_reg);
1205         msleep(intel_dp->backlight_off_delay);
1206 }
1207
1208 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1209 {
1210         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1211         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1212         struct drm_device *dev = crtc->dev;
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214         u32 dpa_ctl;
1215
1216         assert_pipe_disabled(dev_priv,
1217                              to_intel_crtc(crtc)->pipe);
1218
1219         DRM_DEBUG_KMS("\n");
1220         dpa_ctl = I915_READ(DP_A);
1221         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1222         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1223
1224         /* We don't adjust intel_dp->DP while tearing down the link, to
1225          * facilitate link retraining (e.g. after hotplug). Hence clear all
1226          * enable bits here to ensure that we don't enable too much. */
1227         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1228         intel_dp->DP |= DP_PLL_ENABLE;
1229         I915_WRITE(DP_A, intel_dp->DP);
1230         POSTING_READ(DP_A);
1231         udelay(200);
1232 }
1233
1234 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1235 {
1236         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1237         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1238         struct drm_device *dev = crtc->dev;
1239         struct drm_i915_private *dev_priv = dev->dev_private;
1240         u32 dpa_ctl;
1241
1242         assert_pipe_disabled(dev_priv,
1243                              to_intel_crtc(crtc)->pipe);
1244
1245         dpa_ctl = I915_READ(DP_A);
1246         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1247              "dp pll off, should be on\n");
1248         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1249
1250         /* We can't rely on the value tracked for the DP register in
1251          * intel_dp->DP because link_down must not change that (otherwise link
1252          * re-training will fail. */
1253         dpa_ctl &= ~DP_PLL_ENABLE;
1254         I915_WRITE(DP_A, dpa_ctl);
1255         POSTING_READ(DP_A);
1256         udelay(200);
1257 }
1258
1259 /* If the sink supports it, try to set the power state appropriately */
1260 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1261 {
1262         int ret, i;
1263
1264         /* Should have a valid DPCD by this point */
1265         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1266                 return;
1267
1268         if (mode != DRM_MODE_DPMS_ON) {
1269                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1270                                                   DP_SET_POWER_D3);
1271                 if (ret != 1)
1272                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1273         } else {
1274                 /*
1275                  * When turning on, we need to retry for 1ms to give the sink
1276                  * time to wake up.
1277                  */
1278                 for (i = 0; i < 3; i++) {
1279                         ret = intel_dp_aux_native_write_1(intel_dp,
1280                                                           DP_SET_POWER,
1281                                                           DP_SET_POWER_D0);
1282                         if (ret == 1)
1283                                 break;
1284                         msleep(1);
1285                 }
1286         }
1287 }
1288
1289 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1290                                   enum pipe *pipe)
1291 {
1292         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1293         struct drm_device *dev = encoder->base.dev;
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295         u32 tmp = I915_READ(intel_dp->output_reg);
1296
1297         if (!(tmp & DP_PORT_EN))
1298                 return false;
1299
1300         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1301                 *pipe = PORT_TO_PIPE_CPT(tmp);
1302         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1303                 *pipe = PORT_TO_PIPE(tmp);
1304         } else {
1305                 u32 trans_sel;
1306                 u32 trans_dp;
1307                 int i;
1308
1309                 switch (intel_dp->output_reg) {
1310                 case PCH_DP_B:
1311                         trans_sel = TRANS_DP_PORT_SEL_B;
1312                         break;
1313                 case PCH_DP_C:
1314                         trans_sel = TRANS_DP_PORT_SEL_C;
1315                         break;
1316                 case PCH_DP_D:
1317                         trans_sel = TRANS_DP_PORT_SEL_D;
1318                         break;
1319                 default:
1320                         return true;
1321                 }
1322
1323                 for_each_pipe(i) {
1324                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1325                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1326                                 *pipe = i;
1327                                 return true;
1328                         }
1329                 }
1330
1331                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1332                               intel_dp->output_reg);
1333         }
1334
1335         return true;
1336 }
1337
1338 static void intel_disable_dp(struct intel_encoder *encoder)
1339 {
1340         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1341
1342         /* Make sure the panel is off before trying to change the mode. But also
1343          * ensure that we have vdd while we switch off the panel. */
1344         ironlake_edp_panel_vdd_on(intel_dp);
1345         ironlake_edp_backlight_off(intel_dp);
1346         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1347         ironlake_edp_panel_off(intel_dp);
1348
1349         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1350         if (!is_cpu_edp(intel_dp))
1351                 intel_dp_link_down(intel_dp);
1352 }
1353
1354 static void intel_post_disable_dp(struct intel_encoder *encoder)
1355 {
1356         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1357         struct drm_device *dev = encoder->base.dev;
1358
1359         if (is_cpu_edp(intel_dp)) {
1360                 intel_dp_link_down(intel_dp);
1361                 if (!IS_VALLEYVIEW(dev))
1362                         ironlake_edp_pll_off(intel_dp);
1363         }
1364 }
1365
1366 static void intel_enable_dp(struct intel_encoder *encoder)
1367 {
1368         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1369         struct drm_device *dev = encoder->base.dev;
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1372
1373         if (WARN_ON(dp_reg & DP_PORT_EN))
1374                 return;
1375
1376         ironlake_edp_panel_vdd_on(intel_dp);
1377         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1378         intel_dp_start_link_train(intel_dp);
1379         ironlake_edp_panel_on(intel_dp);
1380         ironlake_edp_panel_vdd_off(intel_dp, true);
1381         intel_dp_complete_link_train(intel_dp);
1382         ironlake_edp_backlight_on(intel_dp);
1383 }
1384
1385 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1386 {
1387         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1388         struct drm_device *dev = encoder->base.dev;
1389
1390         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1391                 ironlake_edp_pll_on(intel_dp);
1392 }
1393
1394 /*
1395  * Native read with retry for link status and receiver capability reads for
1396  * cases where the sink may still be asleep.
1397  */
1398 static bool
1399 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1400                                uint8_t *recv, int recv_bytes)
1401 {
1402         int ret, i;
1403
1404         /*
1405          * Sinks are *supposed* to come up within 1ms from an off state,
1406          * but we're also supposed to retry 3 times per the spec.
1407          */
1408         for (i = 0; i < 3; i++) {
1409                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1410                                                recv_bytes);
1411                 if (ret == recv_bytes)
1412                         return true;
1413                 msleep(1);
1414         }
1415
1416         return false;
1417 }
1418
1419 /*
1420  * Fetch AUX CH registers 0x202 - 0x207 which contain
1421  * link status information
1422  */
1423 static bool
1424 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1425 {
1426         return intel_dp_aux_native_read_retry(intel_dp,
1427                                               DP_LANE0_1_STATUS,
1428                                               link_status,
1429                                               DP_LINK_STATUS_SIZE);
1430 }
1431
1432 #if 0
1433 static char     *voltage_names[] = {
1434         "0.4V", "0.6V", "0.8V", "1.2V"
1435 };
1436 static char     *pre_emph_names[] = {
1437         "0dB", "3.5dB", "6dB", "9.5dB"
1438 };
1439 static char     *link_train_names[] = {
1440         "pattern 1", "pattern 2", "idle", "off"
1441 };
1442 #endif
1443
1444 /*
1445  * These are source-specific values; current Intel hardware supports
1446  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1447  */
1448
1449 static uint8_t
1450 intel_dp_voltage_max(struct intel_dp *intel_dp)
1451 {
1452         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1453
1454         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1455                 return DP_TRAIN_VOLTAGE_SWING_800;
1456         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1457                 return DP_TRAIN_VOLTAGE_SWING_1200;
1458         else
1459                 return DP_TRAIN_VOLTAGE_SWING_800;
1460 }
1461
1462 static uint8_t
1463 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1464 {
1465         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1466
1467         if (HAS_DDI(dev)) {
1468                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1469                 case DP_TRAIN_VOLTAGE_SWING_400:
1470                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1471                 case DP_TRAIN_VOLTAGE_SWING_600:
1472                         return DP_TRAIN_PRE_EMPHASIS_6;
1473                 case DP_TRAIN_VOLTAGE_SWING_800:
1474                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1475                 case DP_TRAIN_VOLTAGE_SWING_1200:
1476                 default:
1477                         return DP_TRAIN_PRE_EMPHASIS_0;
1478                 }
1479         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1480                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1481                 case DP_TRAIN_VOLTAGE_SWING_400:
1482                         return DP_TRAIN_PRE_EMPHASIS_6;
1483                 case DP_TRAIN_VOLTAGE_SWING_600:
1484                 case DP_TRAIN_VOLTAGE_SWING_800:
1485                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1486                 default:
1487                         return DP_TRAIN_PRE_EMPHASIS_0;
1488                 }
1489         } else {
1490                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491                 case DP_TRAIN_VOLTAGE_SWING_400:
1492                         return DP_TRAIN_PRE_EMPHASIS_6;
1493                 case DP_TRAIN_VOLTAGE_SWING_600:
1494                         return DP_TRAIN_PRE_EMPHASIS_6;
1495                 case DP_TRAIN_VOLTAGE_SWING_800:
1496                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1497                 case DP_TRAIN_VOLTAGE_SWING_1200:
1498                 default:
1499                         return DP_TRAIN_PRE_EMPHASIS_0;
1500                 }
1501         }
1502 }
1503
1504 static void
1505 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1506 {
1507         uint8_t v = 0;
1508         uint8_t p = 0;
1509         int lane;
1510         uint8_t voltage_max;
1511         uint8_t preemph_max;
1512
1513         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1514                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1515                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1516
1517                 if (this_v > v)
1518                         v = this_v;
1519                 if (this_p > p)
1520                         p = this_p;
1521         }
1522
1523         voltage_max = intel_dp_voltage_max(intel_dp);
1524         if (v >= voltage_max)
1525                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1526
1527         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1528         if (p >= preemph_max)
1529                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1530
1531         for (lane = 0; lane < 4; lane++)
1532                 intel_dp->train_set[lane] = v | p;
1533 }
1534
1535 static uint32_t
1536 intel_gen4_signal_levels(uint8_t train_set)
1537 {
1538         uint32_t        signal_levels = 0;
1539
1540         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1541         case DP_TRAIN_VOLTAGE_SWING_400:
1542         default:
1543                 signal_levels |= DP_VOLTAGE_0_4;
1544                 break;
1545         case DP_TRAIN_VOLTAGE_SWING_600:
1546                 signal_levels |= DP_VOLTAGE_0_6;
1547                 break;
1548         case DP_TRAIN_VOLTAGE_SWING_800:
1549                 signal_levels |= DP_VOLTAGE_0_8;
1550                 break;
1551         case DP_TRAIN_VOLTAGE_SWING_1200:
1552                 signal_levels |= DP_VOLTAGE_1_2;
1553                 break;
1554         }
1555         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1556         case DP_TRAIN_PRE_EMPHASIS_0:
1557         default:
1558                 signal_levels |= DP_PRE_EMPHASIS_0;
1559                 break;
1560         case DP_TRAIN_PRE_EMPHASIS_3_5:
1561                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1562                 break;
1563         case DP_TRAIN_PRE_EMPHASIS_6:
1564                 signal_levels |= DP_PRE_EMPHASIS_6;
1565                 break;
1566         case DP_TRAIN_PRE_EMPHASIS_9_5:
1567                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1568                 break;
1569         }
1570         return signal_levels;
1571 }
1572
1573 /* Gen6's DP voltage swing and pre-emphasis control */
1574 static uint32_t
1575 intel_gen6_edp_signal_levels(uint8_t train_set)
1576 {
1577         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1578                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1579         switch (signal_levels) {
1580         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1581         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1582                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1583         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1584                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1585         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1586         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1587                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1588         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1589         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1590                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1591         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1592         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1593                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1594         default:
1595                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1596                               "0x%x\n", signal_levels);
1597                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1598         }
1599 }
1600
1601 /* Gen7's DP voltage swing and pre-emphasis control */
1602 static uint32_t
1603 intel_gen7_edp_signal_levels(uint8_t train_set)
1604 {
1605         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1606                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1607         switch (signal_levels) {
1608         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1609                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1610         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1611                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1612         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1613                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1614
1615         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1616                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1617         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1618                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1619
1620         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1621                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1622         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1623                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1624
1625         default:
1626                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1627                               "0x%x\n", signal_levels);
1628                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1629         }
1630 }
1631
1632 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1633 static uint32_t
1634 intel_hsw_signal_levels(uint8_t train_set)
1635 {
1636         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1637                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1638         switch (signal_levels) {
1639         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1640                 return DDI_BUF_EMP_400MV_0DB_HSW;
1641         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1642                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1643         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1644                 return DDI_BUF_EMP_400MV_6DB_HSW;
1645         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1646                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1647
1648         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1649                 return DDI_BUF_EMP_600MV_0DB_HSW;
1650         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1651                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1652         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1653                 return DDI_BUF_EMP_600MV_6DB_HSW;
1654
1655         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1656                 return DDI_BUF_EMP_800MV_0DB_HSW;
1657         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1658                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1659         default:
1660                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1661                               "0x%x\n", signal_levels);
1662                 return DDI_BUF_EMP_400MV_0DB_HSW;
1663         }
1664 }
1665
1666 /* Properly updates "DP" with the correct signal levels. */
1667 static void
1668 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1669 {
1670         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1671         struct drm_device *dev = intel_dig_port->base.base.dev;
1672         uint32_t signal_levels, mask;
1673         uint8_t train_set = intel_dp->train_set[0];
1674
1675         if (HAS_DDI(dev)) {
1676                 signal_levels = intel_hsw_signal_levels(train_set);
1677                 mask = DDI_BUF_EMP_MASK;
1678         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1679                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1680                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1681         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1682                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1683                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1684         } else {
1685                 signal_levels = intel_gen4_signal_levels(train_set);
1686                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1687         }
1688
1689         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1690
1691         *DP = (*DP & ~mask) | signal_levels;
1692 }
1693
1694 static bool
1695 intel_dp_set_link_train(struct intel_dp *intel_dp,
1696                         uint32_t dp_reg_value,
1697                         uint8_t dp_train_pat)
1698 {
1699         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1700         struct drm_device *dev = intel_dig_port->base.base.dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         enum port port = intel_dig_port->port;
1703         int ret;
1704         uint32_t temp;
1705
1706         if (HAS_DDI(dev)) {
1707                 temp = I915_READ(DP_TP_CTL(port));
1708
1709                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1710                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1711                 else
1712                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1713
1714                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1715                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1716                 case DP_TRAINING_PATTERN_DISABLE:
1717
1718                         if (port != PORT_A) {
1719                                 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1720                                 I915_WRITE(DP_TP_CTL(port), temp);
1721
1722                                 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1723                                               DP_TP_STATUS_IDLE_DONE), 1))
1724                                         DRM_ERROR("Timed out waiting for DP idle patterns\n");
1725
1726                                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1727                         }
1728
1729                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1730
1731                         break;
1732                 case DP_TRAINING_PATTERN_1:
1733                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1734                         break;
1735                 case DP_TRAINING_PATTERN_2:
1736                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1737                         break;
1738                 case DP_TRAINING_PATTERN_3:
1739                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1740                         break;
1741                 }
1742                 I915_WRITE(DP_TP_CTL(port), temp);
1743
1744         } else if (HAS_PCH_CPT(dev) &&
1745                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1746                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1747
1748                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1749                 case DP_TRAINING_PATTERN_DISABLE:
1750                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1751                         break;
1752                 case DP_TRAINING_PATTERN_1:
1753                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1754                         break;
1755                 case DP_TRAINING_PATTERN_2:
1756                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1757                         break;
1758                 case DP_TRAINING_PATTERN_3:
1759                         DRM_ERROR("DP training pattern 3 not supported\n");
1760                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1761                         break;
1762                 }
1763
1764         } else {
1765                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1766
1767                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1768                 case DP_TRAINING_PATTERN_DISABLE:
1769                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1770                         break;
1771                 case DP_TRAINING_PATTERN_1:
1772                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1773                         break;
1774                 case DP_TRAINING_PATTERN_2:
1775                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1776                         break;
1777                 case DP_TRAINING_PATTERN_3:
1778                         DRM_ERROR("DP training pattern 3 not supported\n");
1779                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1780                         break;
1781                 }
1782         }
1783
1784         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1785         POSTING_READ(intel_dp->output_reg);
1786
1787         intel_dp_aux_native_write_1(intel_dp,
1788                                     DP_TRAINING_PATTERN_SET,
1789                                     dp_train_pat);
1790
1791         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1792             DP_TRAINING_PATTERN_DISABLE) {
1793                 ret = intel_dp_aux_native_write(intel_dp,
1794                                                 DP_TRAINING_LANE0_SET,
1795                                                 intel_dp->train_set,
1796                                                 intel_dp->lane_count);
1797                 if (ret != intel_dp->lane_count)
1798                         return false;
1799         }
1800
1801         return true;
1802 }
1803
1804 /* Enable corresponding port and start training pattern 1 */
1805 void
1806 intel_dp_start_link_train(struct intel_dp *intel_dp)
1807 {
1808         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1809         struct drm_device *dev = encoder->dev;
1810         int i;
1811         uint8_t voltage;
1812         bool clock_recovery = false;
1813         int voltage_tries, loop_tries;
1814         uint32_t DP = intel_dp->DP;
1815
1816         if (HAS_DDI(dev))
1817                 intel_ddi_prepare_link_retrain(encoder);
1818
1819         /* Write the link configuration data */
1820         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1821                                   intel_dp->link_configuration,
1822                                   DP_LINK_CONFIGURATION_SIZE);
1823
1824         DP |= DP_PORT_EN;
1825
1826         memset(intel_dp->train_set, 0, 4);
1827         voltage = 0xff;
1828         voltage_tries = 0;
1829         loop_tries = 0;
1830         clock_recovery = false;
1831         for (;;) {
1832                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1833                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1834
1835                 intel_dp_set_signal_levels(intel_dp, &DP);
1836
1837                 /* Set training pattern 1 */
1838                 if (!intel_dp_set_link_train(intel_dp, DP,
1839                                              DP_TRAINING_PATTERN_1 |
1840                                              DP_LINK_SCRAMBLING_DISABLE))
1841                         break;
1842
1843                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1844                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1845                         DRM_ERROR("failed to get link status\n");
1846                         break;
1847                 }
1848
1849                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1850                         DRM_DEBUG_KMS("clock recovery OK\n");
1851                         clock_recovery = true;
1852                         break;
1853                 }
1854
1855                 /* Check to see if we've tried the max voltage */
1856                 for (i = 0; i < intel_dp->lane_count; i++)
1857                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1858                                 break;
1859                 if (i == intel_dp->lane_count) {
1860                         ++loop_tries;
1861                         if (loop_tries == 5) {
1862                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1863                                 break;
1864                         }
1865                         memset(intel_dp->train_set, 0, 4);
1866                         voltage_tries = 0;
1867                         continue;
1868                 }
1869
1870                 /* Check to see if we've tried the same voltage 5 times */
1871                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1872                         ++voltage_tries;
1873                         if (voltage_tries == 5) {
1874                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1875                                 break;
1876                         }
1877                 } else
1878                         voltage_tries = 0;
1879                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1880
1881                 /* Compute new intel_dp->train_set as requested by target */
1882                 intel_get_adjust_train(intel_dp, link_status);
1883         }
1884
1885         intel_dp->DP = DP;
1886 }
1887
1888 void
1889 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1890 {
1891         bool channel_eq = false;
1892         int tries, cr_tries;
1893         uint32_t DP = intel_dp->DP;
1894
1895         /* channel equalization */
1896         tries = 0;
1897         cr_tries = 0;
1898         channel_eq = false;
1899         for (;;) {
1900                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1901
1902                 if (cr_tries > 5) {
1903                         DRM_ERROR("failed to train DP, aborting\n");
1904                         intel_dp_link_down(intel_dp);
1905                         break;
1906                 }
1907
1908                 intel_dp_set_signal_levels(intel_dp, &DP);
1909
1910                 /* channel eq pattern */
1911                 if (!intel_dp_set_link_train(intel_dp, DP,
1912                                              DP_TRAINING_PATTERN_2 |
1913                                              DP_LINK_SCRAMBLING_DISABLE))
1914                         break;
1915
1916                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1917                 if (!intel_dp_get_link_status(intel_dp, link_status))
1918                         break;
1919
1920                 /* Make sure clock is still ok */
1921                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1922                         intel_dp_start_link_train(intel_dp);
1923                         cr_tries++;
1924                         continue;
1925                 }
1926
1927                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1928                         channel_eq = true;
1929                         break;
1930                 }
1931
1932                 /* Try 5 times, then try clock recovery if that fails */
1933                 if (tries > 5) {
1934                         intel_dp_link_down(intel_dp);
1935                         intel_dp_start_link_train(intel_dp);
1936                         tries = 0;
1937                         cr_tries++;
1938                         continue;
1939                 }
1940
1941                 /* Compute new intel_dp->train_set as requested by target */
1942                 intel_get_adjust_train(intel_dp, link_status);
1943                 ++tries;
1944         }
1945
1946         if (channel_eq)
1947                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1948
1949         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1950 }
1951
1952 static void
1953 intel_dp_link_down(struct intel_dp *intel_dp)
1954 {
1955         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1956         struct drm_device *dev = intel_dig_port->base.base.dev;
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         struct intel_crtc *intel_crtc =
1959                 to_intel_crtc(intel_dig_port->base.base.crtc);
1960         uint32_t DP = intel_dp->DP;
1961
1962         /*
1963          * DDI code has a strict mode set sequence and we should try to respect
1964          * it, otherwise we might hang the machine in many different ways. So we
1965          * really should be disabling the port only on a complete crtc_disable
1966          * sequence. This function is just called under two conditions on DDI
1967          * code:
1968          * - Link train failed while doing crtc_enable, and on this case we
1969          *   really should respect the mode set sequence and wait for a
1970          *   crtc_disable.
1971          * - Someone turned the monitor off and intel_dp_check_link_status
1972          *   called us. We don't need to disable the whole port on this case, so
1973          *   when someone turns the monitor on again,
1974          *   intel_ddi_prepare_link_retrain will take care of redoing the link
1975          *   train.
1976          */
1977         if (HAS_DDI(dev))
1978                 return;
1979
1980         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1981                 return;
1982
1983         DRM_DEBUG_KMS("\n");
1984
1985         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1986                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1987                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1988         } else {
1989                 DP &= ~DP_LINK_TRAIN_MASK;
1990                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1991         }
1992         POSTING_READ(intel_dp->output_reg);
1993
1994         /* We don't really know why we're doing this */
1995         intel_wait_for_vblank(dev, intel_crtc->pipe);
1996
1997         if (HAS_PCH_IBX(dev) &&
1998             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1999                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2000
2001                 /* Hardware workaround: leaving our transcoder select
2002                  * set to transcoder B while it's off will prevent the
2003                  * corresponding HDMI output on transcoder A.
2004                  *
2005                  * Combine this with another hardware workaround:
2006                  * transcoder select bit can only be cleared while the
2007                  * port is enabled.
2008                  */
2009                 DP &= ~DP_PIPEB_SELECT;
2010                 I915_WRITE(intel_dp->output_reg, DP);
2011
2012                 /* Changes to enable or select take place the vblank
2013                  * after being written.
2014                  */
2015                 if (WARN_ON(crtc == NULL)) {
2016                         /* We should never try to disable a port without a crtc
2017                          * attached. For paranoia keep the code around for a
2018                          * bit. */
2019                         POSTING_READ(intel_dp->output_reg);
2020                         msleep(50);
2021                 } else
2022                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2023         }
2024
2025         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2026         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2027         POSTING_READ(intel_dp->output_reg);
2028         msleep(intel_dp->panel_power_down_delay);
2029 }
2030
2031 static bool
2032 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2033 {
2034         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2035
2036         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2037                                            sizeof(intel_dp->dpcd)) == 0)
2038                 return false; /* aux transfer failed */
2039
2040         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2041                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2042         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2043
2044         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2045                 return false; /* DPCD not present */
2046
2047         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2048               DP_DWN_STRM_PORT_PRESENT))
2049                 return true; /* native DP sink */
2050
2051         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2052                 return true; /* no per-port downstream info */
2053
2054         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2055                                            intel_dp->downstream_ports,
2056                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2057                 return false; /* downstream port status fetch failed */
2058
2059         return true;
2060 }
2061
2062 static void
2063 intel_dp_probe_oui(struct intel_dp *intel_dp)
2064 {
2065         u8 buf[3];
2066
2067         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2068                 return;
2069
2070         ironlake_edp_panel_vdd_on(intel_dp);
2071
2072         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2073                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2074                               buf[0], buf[1], buf[2]);
2075
2076         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2077                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2078                               buf[0], buf[1], buf[2]);
2079
2080         ironlake_edp_panel_vdd_off(intel_dp, false);
2081 }
2082
2083 static bool
2084 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2085 {
2086         int ret;
2087
2088         ret = intel_dp_aux_native_read_retry(intel_dp,
2089                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2090                                              sink_irq_vector, 1);
2091         if (!ret)
2092                 return false;
2093
2094         return true;
2095 }
2096
2097 static void
2098 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2099 {
2100         /* NAK by default */
2101         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2102 }
2103
2104 /*
2105  * According to DP spec
2106  * 5.1.2:
2107  *  1. Read DPCD
2108  *  2. Configure link according to Receiver Capabilities
2109  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2110  *  4. Check link status on receipt of hot-plug interrupt
2111  */
2112
2113 void
2114 intel_dp_check_link_status(struct intel_dp *intel_dp)
2115 {
2116         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2117         u8 sink_irq_vector;
2118         u8 link_status[DP_LINK_STATUS_SIZE];
2119
2120         if (!intel_encoder->connectors_active)
2121                 return;
2122
2123         if (WARN_ON(!intel_encoder->base.crtc))
2124                 return;
2125
2126         /* Try to read receiver status if the link appears to be up */
2127         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2128                 intel_dp_link_down(intel_dp);
2129                 return;
2130         }
2131
2132         /* Now read the DPCD to see if it's actually running */
2133         if (!intel_dp_get_dpcd(intel_dp)) {
2134                 intel_dp_link_down(intel_dp);
2135                 return;
2136         }
2137
2138         /* Try to read the source of the interrupt */
2139         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2140             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2141                 /* Clear interrupt source */
2142                 intel_dp_aux_native_write_1(intel_dp,
2143                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2144                                             sink_irq_vector);
2145
2146                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2147                         intel_dp_handle_test_request(intel_dp);
2148                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2149                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2150         }
2151
2152         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2153                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2154                               drm_get_encoder_name(&intel_encoder->base));
2155                 intel_dp_start_link_train(intel_dp);
2156                 intel_dp_complete_link_train(intel_dp);
2157         }
2158 }
2159
2160 /* XXX this is probably wrong for multiple downstream ports */
2161 static enum drm_connector_status
2162 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2163 {
2164         uint8_t *dpcd = intel_dp->dpcd;
2165         bool hpd;
2166         uint8_t type;
2167
2168         if (!intel_dp_get_dpcd(intel_dp))
2169                 return connector_status_disconnected;
2170
2171         /* if there's no downstream port, we're done */
2172         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2173                 return connector_status_connected;
2174
2175         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2176         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2177         if (hpd) {
2178                 uint8_t reg;
2179                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2180                                                     &reg, 1))
2181                         return connector_status_unknown;
2182                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2183                                               : connector_status_disconnected;
2184         }
2185
2186         /* If no HPD, poke DDC gently */
2187         if (drm_probe_ddc(&intel_dp->adapter))
2188                 return connector_status_connected;
2189
2190         /* Well we tried, say unknown for unreliable port types */
2191         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2192         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2193                 return connector_status_unknown;
2194
2195         /* Anything else is out of spec, warn and ignore */
2196         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2197         return connector_status_disconnected;
2198 }
2199
2200 static enum drm_connector_status
2201 ironlake_dp_detect(struct intel_dp *intel_dp)
2202 {
2203         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2204         struct drm_i915_private *dev_priv = dev->dev_private;
2205         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2206         enum drm_connector_status status;
2207
2208         /* Can't disconnect eDP, but you can close the lid... */
2209         if (is_edp(intel_dp)) {
2210                 status = intel_panel_detect(dev);
2211                 if (status == connector_status_unknown)
2212                         status = connector_status_connected;
2213                 return status;
2214         }
2215
2216         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2217                 return connector_status_disconnected;
2218
2219         return intel_dp_detect_dpcd(intel_dp);
2220 }
2221
2222 static enum drm_connector_status
2223 g4x_dp_detect(struct intel_dp *intel_dp)
2224 {
2225         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2226         struct drm_i915_private *dev_priv = dev->dev_private;
2227         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2228         uint32_t bit;
2229
2230         /* Can't disconnect eDP, but you can close the lid... */
2231         if (is_edp(intel_dp)) {
2232                 enum drm_connector_status status;
2233
2234                 status = intel_panel_detect(dev);
2235                 if (status == connector_status_unknown)
2236                         status = connector_status_connected;
2237                 return status;
2238         }
2239
2240         switch (intel_dig_port->port) {
2241         case PORT_B:
2242                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2243                 break;
2244         case PORT_C:
2245                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2246                 break;
2247         case PORT_D:
2248                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2249                 break;
2250         default:
2251                 return connector_status_unknown;
2252         }
2253
2254         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2255                 return connector_status_disconnected;
2256
2257         return intel_dp_detect_dpcd(intel_dp);
2258 }
2259
2260 static struct edid *
2261 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2262 {
2263         struct intel_connector *intel_connector = to_intel_connector(connector);
2264
2265         /* use cached edid if we have one */
2266         if (intel_connector->edid) {
2267                 struct edid *edid;
2268                 int size;
2269
2270                 /* invalid edid */
2271                 if (IS_ERR(intel_connector->edid))
2272                         return NULL;
2273
2274                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2275                 edid = kmalloc(size, GFP_KERNEL);
2276                 if (!edid)
2277                         return NULL;
2278
2279                 memcpy(edid, intel_connector->edid, size);
2280                 return edid;
2281         }
2282
2283         return drm_get_edid(connector, adapter);
2284 }
2285
2286 static int
2287 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2288 {
2289         struct intel_connector *intel_connector = to_intel_connector(connector);
2290
2291         /* use cached edid if we have one */
2292         if (intel_connector->edid) {
2293                 /* invalid edid */
2294                 if (IS_ERR(intel_connector->edid))
2295                         return 0;
2296
2297                 return intel_connector_update_modes(connector,
2298                                                     intel_connector->edid);
2299         }
2300
2301         return intel_ddc_get_modes(connector, adapter);
2302 }
2303
2304 static enum drm_connector_status
2305 intel_dp_detect(struct drm_connector *connector, bool force)
2306 {
2307         struct intel_dp *intel_dp = intel_attached_dp(connector);
2308         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2309         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2310         struct drm_device *dev = connector->dev;
2311         enum drm_connector_status status;
2312         struct edid *edid = NULL;
2313
2314         intel_dp->has_audio = false;
2315
2316         if (HAS_PCH_SPLIT(dev))
2317                 status = ironlake_dp_detect(intel_dp);
2318         else
2319                 status = g4x_dp_detect(intel_dp);
2320
2321         if (status != connector_status_connected)
2322                 return status;
2323
2324         intel_dp_probe_oui(intel_dp);
2325
2326         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2327                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2328         } else {
2329                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2330                 if (edid) {
2331                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2332                         kfree(edid);
2333                 }
2334         }
2335
2336         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2337                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2338         return connector_status_connected;
2339 }
2340
2341 static int intel_dp_get_modes(struct drm_connector *connector)
2342 {
2343         struct intel_dp *intel_dp = intel_attached_dp(connector);
2344         struct intel_connector *intel_connector = to_intel_connector(connector);
2345         struct drm_device *dev = connector->dev;
2346         int ret;
2347
2348         /* We should parse the EDID data and find out if it has an audio sink
2349          */
2350
2351         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2352         if (ret)
2353                 return ret;
2354
2355         /* if eDP has no EDID, fall back to fixed mode */
2356         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2357                 struct drm_display_mode *mode;
2358                 mode = drm_mode_duplicate(dev,
2359                                           intel_connector->panel.fixed_mode);
2360                 if (mode) {
2361                         drm_mode_probed_add(connector, mode);
2362                         return 1;
2363                 }
2364         }
2365         return 0;
2366 }
2367
2368 static bool
2369 intel_dp_detect_audio(struct drm_connector *connector)
2370 {
2371         struct intel_dp *intel_dp = intel_attached_dp(connector);
2372         struct edid *edid;
2373         bool has_audio = false;
2374
2375         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2376         if (edid) {
2377                 has_audio = drm_detect_monitor_audio(edid);
2378                 kfree(edid);
2379         }
2380
2381         return has_audio;
2382 }
2383
2384 static int
2385 intel_dp_set_property(struct drm_connector *connector,
2386                       struct drm_property *property,
2387                       uint64_t val)
2388 {
2389         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2390         struct intel_connector *intel_connector = to_intel_connector(connector);
2391         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2392         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2393         int ret;
2394
2395         ret = drm_object_property_set_value(&connector->base, property, val);
2396         if (ret)
2397                 return ret;
2398
2399         if (property == dev_priv->force_audio_property) {
2400                 int i = val;
2401                 bool has_audio;
2402
2403                 if (i == intel_dp->force_audio)
2404                         return 0;
2405
2406                 intel_dp->force_audio = i;
2407
2408                 if (i == HDMI_AUDIO_AUTO)
2409                         has_audio = intel_dp_detect_audio(connector);
2410                 else
2411                         has_audio = (i == HDMI_AUDIO_ON);
2412
2413                 if (has_audio == intel_dp->has_audio)
2414                         return 0;
2415
2416                 intel_dp->has_audio = has_audio;
2417                 goto done;
2418         }
2419
2420         if (property == dev_priv->broadcast_rgb_property) {
2421                 bool old_auto = intel_dp->color_range_auto;
2422                 uint32_t old_range = intel_dp->color_range;
2423
2424                 switch (val) {
2425                 case INTEL_BROADCAST_RGB_AUTO:
2426                         intel_dp->color_range_auto = true;
2427                         break;
2428                 case INTEL_BROADCAST_RGB_FULL:
2429                         intel_dp->color_range_auto = false;
2430                         intel_dp->color_range = 0;
2431                         break;
2432                 case INTEL_BROADCAST_RGB_LIMITED:
2433                         intel_dp->color_range_auto = false;
2434                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2435                         break;
2436                 default:
2437                         return -EINVAL;
2438                 }
2439
2440                 if (old_auto == intel_dp->color_range_auto &&
2441                     old_range == intel_dp->color_range)
2442                         return 0;
2443
2444                 goto done;
2445         }
2446
2447         if (is_edp(intel_dp) &&
2448             property == connector->dev->mode_config.scaling_mode_property) {
2449                 if (val == DRM_MODE_SCALE_NONE) {
2450                         DRM_DEBUG_KMS("no scaling not supported\n");
2451                         return -EINVAL;
2452                 }
2453
2454                 if (intel_connector->panel.fitting_mode == val) {
2455                         /* the eDP scaling property is not changed */
2456                         return 0;
2457                 }
2458                 intel_connector->panel.fitting_mode = val;
2459
2460                 goto done;
2461         }
2462
2463         return -EINVAL;
2464
2465 done:
2466         if (intel_encoder->base.crtc)
2467                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2468
2469         return 0;
2470 }
2471
2472 static void
2473 intel_dp_destroy(struct drm_connector *connector)
2474 {
2475         struct intel_dp *intel_dp = intel_attached_dp(connector);
2476         struct intel_connector *intel_connector = to_intel_connector(connector);
2477
2478         if (!IS_ERR_OR_NULL(intel_connector->edid))
2479                 kfree(intel_connector->edid);
2480
2481         if (is_edp(intel_dp))
2482                 intel_panel_fini(&intel_connector->panel);
2483
2484         drm_sysfs_connector_remove(connector);
2485         drm_connector_cleanup(connector);
2486         kfree(connector);
2487 }
2488
2489 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2490 {
2491         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2492         struct intel_dp *intel_dp = &intel_dig_port->dp;
2493
2494         i2c_del_adapter(&intel_dp->adapter);
2495         drm_encoder_cleanup(encoder);
2496         if (is_edp(intel_dp)) {
2497                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2498                 ironlake_panel_vdd_off_sync(intel_dp);
2499         }
2500         kfree(intel_dig_port);
2501 }
2502
2503 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2504         .mode_set = intel_dp_mode_set,
2505 };
2506
2507 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2508         .dpms = intel_connector_dpms,
2509         .detect = intel_dp_detect,
2510         .fill_modes = drm_helper_probe_single_connector_modes,
2511         .set_property = intel_dp_set_property,
2512         .destroy = intel_dp_destroy,
2513 };
2514
2515 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2516         .get_modes = intel_dp_get_modes,
2517         .mode_valid = intel_dp_mode_valid,
2518         .best_encoder = intel_best_encoder,
2519 };
2520
2521 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2522         .destroy = intel_dp_encoder_destroy,
2523 };
2524
2525 static void
2526 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2527 {
2528         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2529
2530         intel_dp_check_link_status(intel_dp);
2531 }
2532
2533 /* Return which DP Port should be selected for Transcoder DP control */
2534 int
2535 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2536 {
2537         struct drm_device *dev = crtc->dev;
2538         struct intel_encoder *intel_encoder;
2539         struct intel_dp *intel_dp;
2540
2541         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2542                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2543
2544                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2545                     intel_encoder->type == INTEL_OUTPUT_EDP)
2546                         return intel_dp->output_reg;
2547         }
2548
2549         return -1;
2550 }
2551
2552 /* check the VBT to see whether the eDP is on DP-D port */
2553 bool intel_dpd_is_edp(struct drm_device *dev)
2554 {
2555         struct drm_i915_private *dev_priv = dev->dev_private;
2556         struct child_device_config *p_child;
2557         int i;
2558
2559         if (!dev_priv->child_dev_num)
2560                 return false;
2561
2562         for (i = 0; i < dev_priv->child_dev_num; i++) {
2563                 p_child = dev_priv->child_dev + i;
2564
2565                 if (p_child->dvo_port == PORT_IDPD &&
2566                     p_child->device_type == DEVICE_TYPE_eDP)
2567                         return true;
2568         }
2569         return false;
2570 }
2571
2572 static void
2573 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2574 {
2575         struct intel_connector *intel_connector = to_intel_connector(connector);
2576
2577         intel_attach_force_audio_property(connector);
2578         intel_attach_broadcast_rgb_property(connector);
2579         intel_dp->color_range_auto = true;
2580
2581         if (is_edp(intel_dp)) {
2582                 drm_mode_create_scaling_mode_property(connector->dev);
2583                 drm_object_attach_property(
2584                         &connector->base,
2585                         connector->dev->mode_config.scaling_mode_property,
2586                         DRM_MODE_SCALE_ASPECT);
2587                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2588         }
2589 }
2590
2591 static void
2592 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2593                                     struct intel_dp *intel_dp,
2594                                     struct edp_power_seq *out)
2595 {
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct edp_power_seq cur, vbt, spec, final;
2598         u32 pp_on, pp_off, pp_div, pp;
2599         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2600
2601         if (HAS_PCH_SPLIT(dev)) {
2602                 pp_control_reg = PCH_PP_CONTROL;
2603                 pp_on_reg = PCH_PP_ON_DELAYS;
2604                 pp_off_reg = PCH_PP_OFF_DELAYS;
2605                 pp_div_reg = PCH_PP_DIVISOR;
2606         } else {
2607                 pp_control_reg = PIPEA_PP_CONTROL;
2608                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2609                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2610                 pp_div_reg = PIPEA_PP_DIVISOR;
2611         }
2612
2613         /* Workaround: Need to write PP_CONTROL with the unlock key as
2614          * the very first thing. */
2615         pp = ironlake_get_pp_control(intel_dp);
2616         I915_WRITE(pp_control_reg, pp);
2617
2618         pp_on = I915_READ(pp_on_reg);
2619         pp_off = I915_READ(pp_off_reg);
2620         pp_div = I915_READ(pp_div_reg);
2621
2622         /* Pull timing values out of registers */
2623         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2624                 PANEL_POWER_UP_DELAY_SHIFT;
2625
2626         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2627                 PANEL_LIGHT_ON_DELAY_SHIFT;
2628
2629         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2630                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2631
2632         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2633                 PANEL_POWER_DOWN_DELAY_SHIFT;
2634
2635         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2636                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2637
2638         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2639                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2640
2641         vbt = dev_priv->edp.pps;
2642
2643         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2644          * our hw here, which are all in 100usec. */
2645         spec.t1_t3 = 210 * 10;
2646         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2647         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2648         spec.t10 = 500 * 10;
2649         /* This one is special and actually in units of 100ms, but zero
2650          * based in the hw (so we need to add 100 ms). But the sw vbt
2651          * table multiplies it with 1000 to make it in units of 100usec,
2652          * too. */
2653         spec.t11_t12 = (510 + 100) * 10;
2654
2655         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2656                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2657
2658         /* Use the max of the register settings and vbt. If both are
2659          * unset, fall back to the spec limits. */
2660 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2661                                        spec.field : \
2662                                        max(cur.field, vbt.field))
2663         assign_final(t1_t3);
2664         assign_final(t8);
2665         assign_final(t9);
2666         assign_final(t10);
2667         assign_final(t11_t12);
2668 #undef assign_final
2669
2670 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2671         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2672         intel_dp->backlight_on_delay = get_delay(t8);
2673         intel_dp->backlight_off_delay = get_delay(t9);
2674         intel_dp->panel_power_down_delay = get_delay(t10);
2675         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2676 #undef get_delay
2677
2678         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2679                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2680                       intel_dp->panel_power_cycle_delay);
2681
2682         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2683                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2684
2685         if (out)
2686                 *out = final;
2687 }
2688
2689 static void
2690 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2691                                               struct intel_dp *intel_dp,
2692                                               struct edp_power_seq *seq)
2693 {
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         u32 pp_on, pp_off, pp_div, port_sel = 0;
2696         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2697         int pp_on_reg, pp_off_reg, pp_div_reg;
2698
2699         if (HAS_PCH_SPLIT(dev)) {
2700                 pp_on_reg = PCH_PP_ON_DELAYS;
2701                 pp_off_reg = PCH_PP_OFF_DELAYS;
2702                 pp_div_reg = PCH_PP_DIVISOR;
2703         } else {
2704                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2705                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2706                 pp_div_reg = PIPEA_PP_DIVISOR;
2707         }
2708
2709         if (IS_VALLEYVIEW(dev))
2710                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2711
2712         /* And finally store the new values in the power sequencer. */
2713         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2714                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2715         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2716                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2717         /* Compute the divisor for the pp clock, simply match the Bspec
2718          * formula. */
2719         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2720         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2721                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2722
2723         /* Haswell doesn't have any port selection bits for the panel
2724          * power sequencer any more. */
2725         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2726                 if (is_cpu_edp(intel_dp))
2727                         port_sel = PANEL_POWER_PORT_DP_A;
2728                 else
2729                         port_sel = PANEL_POWER_PORT_DP_D;
2730         }
2731
2732         pp_on |= port_sel;
2733
2734         I915_WRITE(pp_on_reg, pp_on);
2735         I915_WRITE(pp_off_reg, pp_off);
2736         I915_WRITE(pp_div_reg, pp_div);
2737
2738         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2739                       I915_READ(pp_on_reg),
2740                       I915_READ(pp_off_reg),
2741                       I915_READ(pp_div_reg));
2742 }
2743
2744 void
2745 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2746                         struct intel_connector *intel_connector)
2747 {
2748         struct drm_connector *connector = &intel_connector->base;
2749         struct intel_dp *intel_dp = &intel_dig_port->dp;
2750         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2751         struct drm_device *dev = intel_encoder->base.dev;
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         struct drm_display_mode *fixed_mode = NULL;
2754         struct edp_power_seq power_seq = { 0 };
2755         enum port port = intel_dig_port->port;
2756         const char *name = NULL;
2757         int type;
2758
2759         /* Preserve the current hw state. */
2760         intel_dp->DP = I915_READ(intel_dp->output_reg);
2761         intel_dp->attached_connector = intel_connector;
2762
2763         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2764                 if (intel_dpd_is_edp(dev))
2765                         intel_dp->is_pch_edp = true;
2766
2767         /*
2768          * FIXME : We need to initialize built-in panels before external panels.
2769          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2770          */
2771         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2772                 type = DRM_MODE_CONNECTOR_eDP;
2773                 intel_encoder->type = INTEL_OUTPUT_EDP;
2774         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2775                 type = DRM_MODE_CONNECTOR_eDP;
2776                 intel_encoder->type = INTEL_OUTPUT_EDP;
2777         } else {
2778                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2779                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2780                  * rewrite it.
2781                  */
2782                 type = DRM_MODE_CONNECTOR_DisplayPort;
2783         }
2784
2785         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2786         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2787
2788         connector->interlace_allowed = true;
2789         connector->doublescan_allowed = 0;
2790
2791         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2792                           ironlake_panel_vdd_work);
2793
2794         intel_connector_attach_encoder(intel_connector, intel_encoder);
2795         drm_sysfs_connector_add(connector);
2796
2797         if (HAS_DDI(dev))
2798                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2799         else
2800                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2801
2802         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2803         if (HAS_DDI(dev)) {
2804                 switch (intel_dig_port->port) {
2805                 case PORT_A:
2806                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2807                         break;
2808                 case PORT_B:
2809                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2810                         break;
2811                 case PORT_C:
2812                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2813                         break;
2814                 case PORT_D:
2815                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2816                         break;
2817                 default:
2818                         BUG();
2819                 }
2820         }
2821
2822         /* Set up the DDC bus. */
2823         switch (port) {
2824         case PORT_A:
2825                 intel_encoder->hpd_pin = HPD_PORT_A;
2826                 name = "DPDDC-A";
2827                 break;
2828         case PORT_B:
2829                 intel_encoder->hpd_pin = HPD_PORT_B;
2830                 name = "DPDDC-B";
2831                 break;
2832         case PORT_C:
2833                 intel_encoder->hpd_pin = HPD_PORT_C;
2834                 name = "DPDDC-C";
2835                 break;
2836         case PORT_D:
2837                 intel_encoder->hpd_pin = HPD_PORT_D;
2838                 name = "DPDDC-D";
2839                 break;
2840         default:
2841                 BUG();
2842         }
2843
2844         if (is_edp(intel_dp))
2845                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2846
2847         intel_dp_i2c_init(intel_dp, intel_connector, name);
2848
2849         /* Cache DPCD and EDID for edp. */
2850         if (is_edp(intel_dp)) {
2851                 bool ret;
2852                 struct drm_display_mode *scan;
2853                 struct edid *edid;
2854
2855                 ironlake_edp_panel_vdd_on(intel_dp);
2856                 ret = intel_dp_get_dpcd(intel_dp);
2857                 ironlake_edp_panel_vdd_off(intel_dp, false);
2858
2859                 if (ret) {
2860                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2861                                 dev_priv->no_aux_handshake =
2862                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2863                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2864                 } else {
2865                         /* if this fails, presume the device is a ghost */
2866                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2867                         intel_dp_encoder_destroy(&intel_encoder->base);
2868                         intel_dp_destroy(connector);
2869                         return;
2870                 }
2871
2872                 /* We now know it's not a ghost, init power sequence regs. */
2873                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2874                                                               &power_seq);
2875
2876                 ironlake_edp_panel_vdd_on(intel_dp);
2877                 edid = drm_get_edid(connector, &intel_dp->adapter);
2878                 if (edid) {
2879                         if (drm_add_edid_modes(connector, edid)) {
2880                                 drm_mode_connector_update_edid_property(connector, edid);
2881                                 drm_edid_to_eld(connector, edid);
2882                         } else {
2883                                 kfree(edid);
2884                                 edid = ERR_PTR(-EINVAL);
2885                         }
2886                 } else {
2887                         edid = ERR_PTR(-ENOENT);
2888                 }
2889                 intel_connector->edid = edid;
2890
2891                 /* prefer fixed mode from EDID if available */
2892                 list_for_each_entry(scan, &connector->probed_modes, head) {
2893                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2894                                 fixed_mode = drm_mode_duplicate(dev, scan);
2895                                 break;
2896                         }
2897                 }
2898
2899                 /* fallback to VBT if available for eDP */
2900                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2901                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2902                         if (fixed_mode)
2903                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2904                 }
2905
2906                 ironlake_edp_panel_vdd_off(intel_dp, false);
2907         }
2908
2909         if (is_edp(intel_dp)) {
2910                 intel_panel_init(&intel_connector->panel, fixed_mode);
2911                 intel_panel_setup_backlight(connector);
2912         }
2913
2914         intel_dp_add_properties(intel_dp, connector);
2915
2916         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2917          * 0xd.  Failure to do so will result in spurious interrupts being
2918          * generated on the port when a cable is not attached.
2919          */
2920         if (IS_G4X(dev) && !IS_GM45(dev)) {
2921                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2922                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2923         }
2924 }
2925
2926 void
2927 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2928 {
2929         struct intel_digital_port *intel_dig_port;
2930         struct intel_encoder *intel_encoder;
2931         struct drm_encoder *encoder;
2932         struct intel_connector *intel_connector;
2933
2934         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2935         if (!intel_dig_port)
2936                 return;
2937
2938         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2939         if (!intel_connector) {
2940                 kfree(intel_dig_port);
2941                 return;
2942         }
2943
2944         intel_encoder = &intel_dig_port->base;
2945         encoder = &intel_encoder->base;
2946
2947         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2948                          DRM_MODE_ENCODER_TMDS);
2949         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2950
2951         intel_encoder->compute_config = intel_dp_compute_config;
2952         intel_encoder->enable = intel_enable_dp;
2953         intel_encoder->pre_enable = intel_pre_enable_dp;
2954         intel_encoder->disable = intel_disable_dp;
2955         intel_encoder->post_disable = intel_post_disable_dp;
2956         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2957
2958         intel_dig_port->port = port;
2959         intel_dig_port->dp.output_reg = output_reg;
2960
2961         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2962         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2963         intel_encoder->cloneable = false;
2964         intel_encoder->hot_plug = intel_dp_hot_plug;
2965
2966         intel_dp_init_connector(intel_dig_port, intel_connector);
2967 }