2 * Copyright © 2006-2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
36 I915_MAX_PIPES = _PIPE_EDP
39 #define pipe_name(p) ((p) + 'A')
52 static inline const char *transcoder_name(enum transcoder transcoder)
63 case TRANSCODER_DSI_A:
65 case TRANSCODER_DSI_C:
72 static inline bool transcoder_is_dsi(enum transcoder transcoder)
74 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
78 * Global legacy plane identifier. Valid only for primary/sprite
79 * planes on pre-g4x, and only for primary planes on g4x-bdw.
87 #define plane_name(p) ((p) + 'A')
88 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
91 * Per-pipe plane identifier.
92 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
93 * number of planes per CRTC. Not all platforms really have this many planes,
94 * which means some arrays of size I915_MAX_PLANES may have unused entries
95 * between the topmost sprite plane and the cursor plane.
97 * This is expected to be passed to various register macros
98 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
110 #define for_each_plane_id_on_crtc(__crtc, __p) \
111 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
112 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
127 #define port_name(p) ((p) + 'A')
151 #define I915_NUM_PHYS_VLV 2
162 #define aux_ch_name(a) ((a) + 'A')
164 enum intel_display_power_domain {
168 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
169 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
170 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
171 POWER_DOMAIN_TRANSCODER_A,
172 POWER_DOMAIN_TRANSCODER_B,
173 POWER_DOMAIN_TRANSCODER_C,
174 POWER_DOMAIN_TRANSCODER_EDP,
175 POWER_DOMAIN_TRANSCODER_DSI_A,
176 POWER_DOMAIN_TRANSCODER_DSI_C,
177 POWER_DOMAIN_PORT_DDI_A_LANES,
178 POWER_DOMAIN_PORT_DDI_B_LANES,
179 POWER_DOMAIN_PORT_DDI_C_LANES,
180 POWER_DOMAIN_PORT_DDI_D_LANES,
181 POWER_DOMAIN_PORT_DDI_E_LANES,
182 POWER_DOMAIN_PORT_DDI_F_LANES,
183 POWER_DOMAIN_PORT_DDI_A_IO,
184 POWER_DOMAIN_PORT_DDI_B_IO,
185 POWER_DOMAIN_PORT_DDI_C_IO,
186 POWER_DOMAIN_PORT_DDI_D_IO,
187 POWER_DOMAIN_PORT_DDI_E_IO,
188 POWER_DOMAIN_PORT_DDI_F_IO,
189 POWER_DOMAIN_PORT_DSI,
190 POWER_DOMAIN_PORT_CRT,
191 POWER_DOMAIN_PORT_OTHER,
201 POWER_DOMAIN_AUX_IO_A,
203 POWER_DOMAIN_MODESET,
210 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
211 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
212 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
213 #define POWER_DOMAIN_TRANSCODER(tran) \
214 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
215 (tran) + POWER_DOMAIN_TRANSCODER_A)
217 /* Used by dp and fdi links */
218 struct intel_link_m_n {
226 #define for_each_pipe(__dev_priv, __p) \
227 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
230 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
231 for_each_if((__mask) & BIT(__p))
233 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
234 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
235 for_each_if ((__mask) & (1 << (__t)))
237 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
239 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
242 #define for_each_sprite(__dev_priv, __p, __s) \
244 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
247 #define for_each_port_masked(__port, __ports_mask) \
248 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
249 for_each_if((__ports_mask) & BIT(__port))
251 #define for_each_crtc(dev, crtc) \
252 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
254 #define for_each_intel_plane(dev, intel_plane) \
255 list_for_each_entry(intel_plane, \
256 &(dev)->mode_config.plane_list, \
259 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
260 list_for_each_entry(intel_plane, \
261 &(dev)->mode_config.plane_list, \
263 for_each_if((plane_mask) & \
264 BIT(drm_plane_index(&intel_plane->base)))
266 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
267 list_for_each_entry(intel_plane, \
268 &(dev)->mode_config.plane_list, \
270 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
272 #define for_each_intel_crtc(dev, intel_crtc) \
273 list_for_each_entry(intel_crtc, \
274 &(dev)->mode_config.crtc_list, \
277 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
278 list_for_each_entry(intel_crtc, \
279 &(dev)->mode_config.crtc_list, \
281 for_each_if((crtc_mask) & BIT(drm_crtc_index(&intel_crtc->base)))
283 #define for_each_intel_encoder(dev, intel_encoder) \
284 list_for_each_entry(intel_encoder, \
285 &(dev)->mode_config.encoder_list, \
288 #define for_each_intel_connector_iter(intel_connector, iter) \
289 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
291 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
292 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
293 for_each_if((intel_encoder)->base.crtc == (__crtc))
295 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
296 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
297 for_each_if((intel_connector)->base.encoder == (__encoder))
299 #define for_each_power_domain(domain, mask) \
300 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
301 for_each_if(BIT_ULL(domain) & (mask))
303 #define for_each_power_well(__dev_priv, __power_well) \
304 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
305 (__power_well) - (__dev_priv)->power_domains.power_wells < \
306 (__dev_priv)->power_domains.power_well_count; \
309 #define for_each_power_well_rev(__dev_priv, __power_well) \
310 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
311 (__dev_priv)->power_domains.power_well_count - 1; \
312 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
315 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
316 for_each_power_well(__dev_priv, __power_well) \
317 for_each_if((__power_well)->domains & (__domain_mask))
319 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
320 for_each_power_well_rev(__dev_priv, __power_well) \
321 for_each_if((__power_well)->domains & (__domain_mask))
323 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
325 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
326 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
327 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
331 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
333 (__i) < (__state)->base.dev->mode_config.num_crtc && \
334 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
335 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
339 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
341 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
342 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
343 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
344 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
348 void intel_link_compute_m_n(int bpp, int nlanes,
349 int pixel_clock, int link_clock,
350 struct intel_link_m_n *m_n,