drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 364                               unsigned int reg)
 365 {
 366         unsigned int val;
 367
 368         /* use the module option value if specified */
 369         if (i915_lvds_channel_mode > 0)
 370                 return i915_lvds_channel_mode == 2;
 371
 372         if (dev_priv->lvds_val)
 373                 val = dev_priv->lvds_val;
 374         else {
 375                 /* BIOS should set the proper LVDS register value at boot, but
 376                  * in reality, it doesn't set the value when the lid is closed;
 377                  * we need to check "the value to be set" in VBT when LVDS
 378                  * register is uninitialized.
 379                  */
 380                 val = I915_READ(reg);
 381                 if (!(val & ~LVDS_DETECTED))
 382                         val = dev_priv->bios_lvds_val;
 383                 dev_priv->lvds_val = val;
 384         }
 385         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 386 }
 387
 388 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 389                                                 int refclk)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 397                         /* LVDS dual channel */
 398                         if (refclk == 100000)
 399                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 400                         else
 401                                 limit = &intel_limits_ironlake_dual_lvds;
 402                 } else {
 403                         if (refclk == 100000)
 404                                 limit = &intel_limits_ironlake_single_lvds_100m;
 405                         else
 406                                 limit = &intel_limits_ironlake_single_lvds;
 407                 }
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 409                         HAS_eDP)
 410                 limit = &intel_limits_ironlake_display_port;
 411         else
 412                 limit = &intel_limits_ironlake_dac;
 413
 414         return limit;
 415 }
 416
 417 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 418 {
 419         struct drm_device *dev = crtc->dev;
 420         struct drm_i915_private *dev_priv = dev->dev_private;
 421         const intel_limit_t *limit;
 422
 423         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 424                 if (is_dual_link_lvds(dev_priv, LVDS))
 425                         /* LVDS with dual channel */
 426                         limit = &intel_limits_g4x_dual_channel_lvds;
 427                 else
 428                         /* LVDS with dual channel */
 429                         limit = &intel_limits_g4x_single_channel_lvds;
 430         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 431                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 432                 limit = &intel_limits_g4x_hdmi;
 433         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 434                 limit = &intel_limits_g4x_sdvo;
 435         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 436                 limit = &intel_limits_g4x_display_port;
 437         } else /* The option is for other outputs */
 438                 limit = &intel_limits_i9xx_sdvo;
 439
 440         return limit;
 441 }
 442
 443 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 444 {
 445         struct drm_device *dev = crtc->dev;
 446         const intel_limit_t *limit;
 447
 448         if (HAS_PCH_SPLIT(dev))
 449                 limit = intel_ironlake_limit(crtc, refclk);
 450         else if (IS_G4X(dev)) {
 451                 limit = intel_g4x_limit(crtc);
 452         } else if (IS_PINEVIEW(dev)) {
 453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 454                         limit = &intel_limits_pineview_lvds;
 455                 else
 456                         limit = &intel_limits_pineview_sdvo;
 457         } else if (!IS_GEN2(dev)) {
 458                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 459                         limit = &intel_limits_i9xx_lvds;
 460                 else
 461                         limit = &intel_limits_i9xx_sdvo;
 462         } else {
 463                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 464                         limit = &intel_limits_i8xx_lvds;
 465                 else
 466                         limit = &intel_limits_i8xx_dvo;
 467         }
 468         return limit;
 469 }
 470
 471 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 472 static void pineview_clock(int refclk, intel_clock_t *clock)
 473 {
 474         clock->m = clock->m2 + 2;
 475         clock->p = clock->p1 * clock->p2;
 476         clock->vco = refclk * clock->m / clock->n;
 477         clock->dot = clock->vco / clock->p;
 478 }
 479
 480 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 481 {
 482         if (IS_PINEVIEW(dev)) {
 483                 pineview_clock(refclk, clock);
 484                 return;
 485         }
 486         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 487         clock->p = clock->p1 * clock->p2;
 488         clock->vco = refclk * clock->m / (clock->n + 2);
 489         clock->dot = clock->vco / clock->p;
 490 }
 491
 492 /**
 493  * Returns whether any output on the specified pipe is of the specified type
 494  */
 495 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 496 {
 497         struct drm_device *dev = crtc->dev;
 498         struct drm_mode_config *mode_config = &dev->mode_config;
 499         struct intel_encoder *encoder;
 500
 501         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 502                 if (encoder->base.crtc == crtc && encoder->type == type)
 503                         return true;
 504
 505         return false;
 506 }
 507
 508 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 509 /**
 510  * Returns whether the given set of divisors are valid for a given refclk with
 511  * the given connectors.
 512  */
 513
 514 static bool intel_PLL_is_valid(struct drm_device *dev,
 515                                const intel_limit_t *limit,
 516                                const intel_clock_t *clock)
 517 {
 518         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 519                 INTELPllInvalid("p1 out of range\n");
 520         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 521                 INTELPllInvalid("p out of range\n");
 522         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 523                 INTELPllInvalid("m2 out of range\n");
 524         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 525                 INTELPllInvalid("m1 out of range\n");
 526         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 527                 INTELPllInvalid("m1 <= m2\n");
 528         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 529                 INTELPllInvalid("m out of range\n");
 530         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 531                 INTELPllInvalid("n out of range\n");
 532         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 533                 INTELPllInvalid("vco out of range\n");
 534         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 535          * connector, etc., rather than just a single range.
 536          */
 537         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 538                 INTELPllInvalid("dot out of range\n");
 539
 540         return true;
 541 }
 542
 543 static bool
 544 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 545                     int target, int refclk, intel_clock_t *match_clock,
 546                     intel_clock_t *best_clock)
 547
 548 {
 549         struct drm_device *dev = crtc->dev;
 550         struct drm_i915_private *dev_priv = dev->dev_private;
 551         intel_clock_t clock;
 552         int err = target;
 553
 554         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 555             (I915_READ(LVDS)) != 0) {
 556                 /*
 557                  * For LVDS, if the panel is on, just rely on its current
 558                  * settings for dual-channel.  We haven't figured out how to
 559                  * reliably set up different single/dual channel state, if we
 560                  * even can.
 561                  */
 562                 if (is_dual_link_lvds(dev_priv, LVDS))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         /* m1 is always 0 in Pineview */
 580                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 581                                 break;
 582                         for (clock.n = limit->n.min;
 583                              clock.n <= limit->n.max; clock.n++) {
 584                                 for (clock.p1 = limit->p1.min;
 585                                         clock.p1 <= limit->p1.max; clock.p1++) {
 586                                         int this_err;
 587
 588                                         intel_clock(dev, refclk, &clock);
 589                                         if (!intel_PLL_is_valid(dev, limit,
 590                                                                 &clock))
 591                                                 continue;
 592                                         if (match_clock &&
 593                                             clock.p != match_clock->p)
 594                                                 continue;
 595
 596                                         this_err = abs(clock.dot - target);
 597                                         if (this_err < err) {
 598                                                 *best_clock = clock;
 599                                                 err = this_err;
 600                                         }
 601                                 }
 602                         }
 603                 }
 604         }
 605
 606         return (err != target);
 607 }
 608
 609 static bool
 610 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 611                         int target, int refclk, intel_clock_t *match_clock,
 612                         intel_clock_t *best_clock)
 613 {
 614         struct drm_device *dev = crtc->dev;
 615         struct drm_i915_private *dev_priv = dev->dev_private;
 616         intel_clock_t clock;
 617         int max_n;
 618         bool found;
 619         /* approximately equals target * 0.00585 */
 620         int err_most = (target >> 8) + (target >> 9);
 621         found = false;
 622
 623         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 624                 int lvds_reg;
 625
 626                 if (HAS_PCH_SPLIT(dev))
 627                         lvds_reg = PCH_LVDS;
 628                 else
 629                         lvds_reg = LVDS;
 630                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 631                     LVDS_CLKB_POWER_UP)
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         intel_clock(dev, refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659                                         if (match_clock &&
 660                                             clock.p != match_clock->p)
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                            int target, int refclk, intel_clock_t *match_clock,
 680                            intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684
 685         if (target < 200000) {
 686                 clock.n = 1;
 687                 clock.p1 = 2;
 688                 clock.p2 = 10;
 689                 clock.m1 = 12;
 690                 clock.m2 = 9;
 691         } else {
 692                 clock.n = 2;
 693                 clock.p1 = 1;
 694                 clock.p2 = 10;
 695                 clock.m1 = 14;
 696                 clock.m2 = 8;
 697         }
 698         intel_clock(dev, refclk, &clock);
 699         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 700         return true;
 701 }
 702
 703 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 704 static bool
 705 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 706                       int target, int refclk, intel_clock_t *match_clock,
 707                       intel_clock_t *best_clock)
 708 {
 709         intel_clock_t clock;
 710         if (target < 200000) {
 711                 clock.p1 = 2;
 712                 clock.p2 = 10;
 713                 clock.n = 2;
 714                 clock.m1 = 23;
 715                 clock.m2 = 8;
 716         } else {
 717                 clock.p1 = 1;
 718                 clock.p2 = 10;
 719                 clock.n = 1;
 720                 clock.m1 = 14;
 721                 clock.m2 = 2;
 722         }
 723         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 724         clock.p = (clock.p1 * clock.p2);
 725         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 726         clock.vco = 0;
 727         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 728         return true;
 729 }
 730
 731 /**
 732  * intel_wait_for_vblank - wait for vblank on a given pipe
 733  * @dev: drm device
 734  * @pipe: pipe to wait for
 735  *
 736  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 737  * mode setting code.
 738  */
 739 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 740 {
 741         struct drm_i915_private *dev_priv = dev->dev_private;
 742         int pipestat_reg = PIPESTAT(pipe);
 743
 744         /* Clear existing vblank status. Note this will clear any other
 745          * sticky status fields as well.
 746          *
 747          * This races with i915_driver_irq_handler() with the result
 748          * that either function could miss a vblank event.  Here it is not
 749          * fatal, as we will either wait upon the next vblank interrupt or
 750          * timeout.  Generally speaking intel_wait_for_vblank() is only
 751          * called during modeset at which time the GPU should be idle and
 752          * should *not* be performing page flips and thus not waiting on
 753          * vblanks...
 754          * Currently, the result of us stealing a vblank from the irq
 755          * handler is that a single frame will be skipped during swapbuffers.
 756          */
 757         I915_WRITE(pipestat_reg,
 758                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 759
 760         /* Wait for vblank interrupt bit to set */
 761         if (wait_for(I915_READ(pipestat_reg) &
 762                      PIPE_VBLANK_INTERRUPT_STATUS,
 763                      50))
 764                 DRM_DEBUG_KMS("vblank wait timed out\n");
 765 }
 766
 767 /*
 768  * intel_wait_for_pipe_off - wait for pipe to turn off
 769  * @dev: drm device
 770  * @pipe: pipe to wait for
 771  *
 772  * After disabling a pipe, we can't wait for vblank in the usual way,
 773  * spinning on the vblank interrupt status bit, since we won't actually
 774  * see an interrupt when the pipe is disabled.
 775  *
 776  * On Gen4 and above:
 777  *   wait for the pipe register state bit to turn off
 778  *
 779  * Otherwise:
 780  *   wait for the display line value to settle (it usually
 781  *   ends up stopping at the start of the next frame).
 782  *
 783  */
 784 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 785 {
 786         struct drm_i915_private *dev_priv = dev->dev_private;
 787
 788         if (INTEL_INFO(dev)->gen >= 4) {
 789                 int reg = PIPECONF(pipe);
 790
 791                 /* Wait for the Pipe State to go off */
 792                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 793                              100))
 794                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 795         } else {
 796                 u32 last_line;
 797                 int reg = PIPEDSL(pipe);
 798                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 799
 800                 /* Wait for the display line to settle */
 801                 do {
 802                         last_line = I915_READ(reg) & DSL_LINEMASK;
 803                         mdelay(5);
 804                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 805                          time_after(timeout, jiffies));
 806                 if (time_after(jiffies, timeout))
 807                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 808         }
 809 }
 810
 811 static const char *state_string(bool enabled)
 812 {
 813         return enabled ? "on" : "off";
 814 }
 815
 816 /* Only for pre-ILK configs */
 817 static void assert_pll(struct drm_i915_private *dev_priv,
 818                        enum pipe pipe, bool state)
 819 {
 820         int reg;
 821         u32 val;
 822         bool cur_state;
 823
 824         reg = DPLL(pipe);
 825         val = I915_READ(reg);
 826         cur_state = !!(val & DPLL_VCO_ENABLE);
 827         WARN(cur_state != state,
 828              "PLL state assertion failure (expected %s, current %s)\n",
 829              state_string(state), state_string(cur_state));
 830 }
 831 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 832 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 833
 834 /* For ILK+ */
 835 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 836                            enum pipe pipe, bool state)
 837 {
 838         int reg;
 839         u32 val;
 840         bool cur_state;
 841
 842         if (HAS_PCH_CPT(dev_priv->dev)) {
 843                 u32 pch_dpll;
 844
 845                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 846
 847                 /* Make sure the selected PLL is enabled to the transcoder */
 848                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 849                      "transcoder %d PLL not enabled\n", pipe);
 850
 851                 /* Convert the transcoder pipe number to a pll pipe number */
 852                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 853         }
 854
 855         reg = PCH_DPLL(pipe);
 856         val = I915_READ(reg);
 857         cur_state = !!(val & DPLL_VCO_ENABLE);
 858         WARN(cur_state != state,
 859              "PCH PLL state assertion failure (expected %s, current %s)\n",
 860              state_string(state), state_string(cur_state));
 861 }
 862 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 863 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 864
 865 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 866                           enum pipe pipe, bool state)
 867 {
 868         int reg;
 869         u32 val;
 870         bool cur_state;
 871
 872         reg = FDI_TX_CTL(pipe);
 873         val = I915_READ(reg);
 874         cur_state = !!(val & FDI_TX_ENABLE);
 875         WARN(cur_state != state,
 876              "FDI TX state assertion failure (expected %s, current %s)\n",
 877              state_string(state), state_string(cur_state));
 878 }
 879 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 880 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 881
 882 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 883                           enum pipe pipe, bool state)
 884 {
 885         int reg;
 886         u32 val;
 887         bool cur_state;
 888
 889         reg = FDI_RX_CTL(pipe);
 890         val = I915_READ(reg);
 891         cur_state = !!(val & FDI_RX_ENABLE);
 892         WARN(cur_state != state,
 893              "FDI RX state assertion failure (expected %s, current %s)\n",
 894              state_string(state), state_string(cur_state));
 895 }
 896 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 897 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 898
 899 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 900                                       enum pipe pipe)
 901 {
 902         int reg;
 903         u32 val;
 904
 905         /* ILK FDI PLL is always enabled */
 906         if (dev_priv->info->gen == 5)
 907                 return;
 908
 909         reg = FDI_TX_CTL(pipe);
 910         val = I915_READ(reg);
 911         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 912 }
 913
 914 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 915                                       enum pipe pipe)
 916 {
 917         int reg;
 918         u32 val;
 919
 920         reg = FDI_RX_CTL(pipe);
 921         val = I915_READ(reg);
 922         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 923 }
 924
 925 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 926                                   enum pipe pipe)
 927 {
 928         int pp_reg, lvds_reg;
 929         u32 val;
 930         enum pipe panel_pipe = PIPE_A;
 931         bool locked = true;
 932
 933         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 934                 pp_reg = PCH_PP_CONTROL;
 935                 lvds_reg = PCH_LVDS;
 936         } else {
 937                 pp_reg = PP_CONTROL;
 938                 lvds_reg = LVDS;
 939         }
 940
 941         val = I915_READ(pp_reg);
 942         if (!(val & PANEL_POWER_ON) ||
 943             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 944                 locked = false;
 945
 946         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 947                 panel_pipe = PIPE_B;
 948
 949         WARN(panel_pipe == pipe && locked,
 950              "panel assertion failure, pipe %c regs locked\n",
 951              pipe_name(pipe));
 952 }
 953
 954 void assert_pipe(struct drm_i915_private *dev_priv,
 955                  enum pipe pipe, bool state)
 956 {
 957         int reg;
 958         u32 val;
 959         bool cur_state;
 960
 961         /* if we need the pipe A quirk it must be always on */
 962         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 963                 state = true;
 964
 965         reg = PIPECONF(pipe);
 966         val = I915_READ(reg);
 967         cur_state = !!(val & PIPECONF_ENABLE);
 968         WARN(cur_state != state,
 969              "pipe %c assertion failure (expected %s, current %s)\n",
 970              pipe_name(pipe), state_string(state), state_string(cur_state));
 971 }
 972
 973 static void assert_plane(struct drm_i915_private *dev_priv,
 974                          enum plane plane, bool state)
 975 {
 976         int reg;
 977         u32 val;
 978         bool cur_state;
 979
 980         reg = DSPCNTR(plane);
 981         val = I915_READ(reg);
 982         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 983         WARN(cur_state != state,
 984              "plane %c assertion failure (expected %s, current %s)\n",
 985              plane_name(plane), state_string(state), state_string(cur_state));
 986 }
 987
 988 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
 989 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
 990
 991 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 992                                    enum pipe pipe)
 993 {
 994         int reg, i;
 995         u32 val;
 996         int cur_pipe;
 997
 998         /* Planes are fixed to pipes on ILK+ */
 999         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1000                 reg = DSPCNTR(pipe);
1001                 val = I915_READ(reg);
1002                 WARN((val & DISPLAY_PLANE_ENABLE),
1003                      "plane %c assertion failure, should be disabled but not\n",
1004                      plane_name(pipe));
1005                 return;
1006         }
1007
1008         /* Need to check both planes against the pipe */
1009         for (i = 0; i < 2; i++) {
1010                 reg = DSPCNTR(i);
1011                 val = I915_READ(reg);
1012                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1013                         DISPPLANE_SEL_PIPE_SHIFT;
1014                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1015                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1016                      plane_name(i), pipe_name(pipe));
1017         }
1018 }
1019
1020 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1021 {
1022         u32 val;
1023         bool enabled;
1024
1025         val = I915_READ(PCH_DREF_CONTROL);
1026         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1027                             DREF_SUPERSPREAD_SOURCE_MASK));
1028         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1032                                        enum pipe pipe)
1033 {
1034         int reg;
1035         u32 val;
1036         bool enabled;
1037
1038         reg = TRANSCONF(pipe);
1039         val = I915_READ(reg);
1040         enabled = !!(val & TRANS_ENABLE);
1041         WARN(enabled,
1042              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1043              pipe_name(pipe));
1044 }
1045
1046 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1047                             enum pipe pipe, u32 port_sel, u32 val)
1048 {
1049         if ((val & DP_PORT_EN) == 0)
1050                 return false;
1051
1052         if (HAS_PCH_CPT(dev_priv->dev)) {
1053                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1054                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1055                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1056                         return false;
1057         } else {
1058                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1059                         return false;
1060         }
1061         return true;
1062 }
1063
1064 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1065                               enum pipe pipe, u32 val)
1066 {
1067         if ((val & PORT_ENABLE) == 0)
1068                 return false;
1069
1070         if (HAS_PCH_CPT(dev_priv->dev)) {
1071                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1072                         return false;
1073         } else {
1074                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1075                         return false;
1076         }
1077         return true;
1078 }
1079
1080 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1081                               enum pipe pipe, u32 val)
1082 {
1083         if ((val & LVDS_PORT_EN) == 0)
1084                 return false;
1085
1086         if (HAS_PCH_CPT(dev_priv->dev)) {
1087                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1088                         return false;
1089         } else {
1090                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1091                         return false;
1092         }
1093         return true;
1094 }
1095
1096 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1097                               enum pipe pipe, u32 val)
1098 {
1099         if ((val & ADPA_DAC_ENABLE) == 0)
1100                 return false;
1101         if (HAS_PCH_CPT(dev_priv->dev)) {
1102                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1103                         return false;
1104         } else {
1105                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1106                         return false;
1107         }
1108         return true;
1109 }
1110
1111 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1112                                    enum pipe pipe, int reg, u32 port_sel)
1113 {
1114         u32 val = I915_READ(reg);
1115         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1116              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1117              reg, pipe_name(pipe));
1118 }
1119
1120 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1121                                      enum pipe pipe, int reg)
1122 {
1123         u32 val = I915_READ(reg);
1124         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1125              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1126              reg, pipe_name(pipe));
1127 }
1128
1129 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1130                                       enum pipe pipe)
1131 {
1132         int reg;
1133         u32 val;
1134
1135         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1136         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1137         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1138
1139         reg = PCH_ADPA;
1140         val = I915_READ(reg);
1141         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1142              "PCH VGA enabled on transcoder %c, should be disabled\n",
1143              pipe_name(pipe));
1144
1145         reg = PCH_LVDS;
1146         val = I915_READ(reg);
1147         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1148              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1149              pipe_name(pipe));
1150
1151         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1152         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1153         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1154 }
1155
1156 /**
1157  * intel_enable_pll - enable a PLL
1158  * @dev_priv: i915 private structure
1159  * @pipe: pipe PLL to enable
1160  *
1161  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1162  * make sure the PLL reg is writable first though, since the panel write
1163  * protect mechanism may be enabled.
1164  *
1165  * Note!  This is for pre-ILK only.
1166  */
1167 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1168 {
1169         int reg;
1170         u32 val;
1171
1172         /* No really, not for ILK+ */
1173         BUG_ON(dev_priv->info->gen >= 5);
1174
1175         /* PLL is protected by panel, make sure we can write it */
1176         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1177                 assert_panel_unlocked(dev_priv, pipe);
1178
1179         reg = DPLL(pipe);
1180         val = I915_READ(reg);
1181         val |= DPLL_VCO_ENABLE;
1182
1183         /* We do this three times for luck */
1184         I915_WRITE(reg, val);
1185         POSTING_READ(reg);
1186         udelay(150); /* wait for warmup */
1187         I915_WRITE(reg, val);
1188         POSTING_READ(reg);
1189         udelay(150); /* wait for warmup */
1190         I915_WRITE(reg, val);
1191         POSTING_READ(reg);
1192         udelay(150); /* wait for warmup */
1193 }
1194
1195 /**
1196  * intel_disable_pll - disable a PLL
1197  * @dev_priv: i915 private structure
1198  * @pipe: pipe PLL to disable
1199  *
1200  * Disable the PLL for @pipe, making sure the pipe is off first.
1201  *
1202  * Note!  This is for pre-ILK only.
1203  */
1204 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1205 {
1206         int reg;
1207         u32 val;
1208
1209         /* Don't disable pipe A or pipe A PLLs if needed */
1210         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1211                 return;
1212
1213         /* Make sure the pipe isn't still relying on us */
1214         assert_pipe_disabled(dev_priv, pipe);
1215
1216         reg = DPLL(pipe);
1217         val = I915_READ(reg);
1218         val &= ~DPLL_VCO_ENABLE;
1219         I915_WRITE(reg, val);
1220         POSTING_READ(reg);
1221 }
1222
1223 /**
1224  * intel_enable_pch_pll - enable PCH PLL
1225  * @dev_priv: i915 private structure
1226  * @pipe: pipe PLL to enable
1227  *
1228  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1229  * drives the transcoder clock.
1230  */
1231 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1232                                  enum pipe pipe)
1233 {
1234         int reg;
1235         u32 val;
1236
1237         if (pipe > 1)
1238                 return;
1239
1240         /* PCH only available on ILK+ */
1241         BUG_ON(dev_priv->info->gen < 5);
1242
1243         /* PCH refclock must be enabled first */
1244         assert_pch_refclk_enabled(dev_priv);
1245
1246         reg = PCH_DPLL(pipe);
1247         val = I915_READ(reg);
1248         val |= DPLL_VCO_ENABLE;
1249         I915_WRITE(reg, val);
1250         POSTING_READ(reg);
1251         udelay(200);
1252 }
1253
1254 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1255                                   enum pipe pipe)
1256 {
1257         int reg;
1258         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1259                 pll_sel = TRANSC_DPLL_ENABLE;
1260
1261         if (pipe > 1)
1262                 return;
1263
1264         /* PCH only available on ILK+ */
1265         BUG_ON(dev_priv->info->gen < 5);
1266
1267         /* Make sure transcoder isn't still depending on us */
1268         assert_transcoder_disabled(dev_priv, pipe);
1269
1270         if (pipe == 0)
1271                 pll_sel |= TRANSC_DPLLA_SEL;
1272         else if (pipe == 1)
1273                 pll_sel |= TRANSC_DPLLB_SEL;
1274
1275
1276         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1277                 return;
1278
1279         reg = PCH_DPLL(pipe);
1280         val = I915_READ(reg);
1281         val &= ~DPLL_VCO_ENABLE;
1282         I915_WRITE(reg, val);
1283         POSTING_READ(reg);
1284         udelay(200);
1285 }
1286
1287 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1288                                     enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val, pipeconf_val;
1292         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1293
1294         /* PCH only available on ILK+ */
1295         BUG_ON(dev_priv->info->gen < 5);
1296
1297         /* Make sure PCH DPLL is enabled */
1298         assert_pch_pll_enabled(dev_priv, pipe);
1299
1300         /* FDI must be feeding us bits for PCH ports */
1301         assert_fdi_tx_enabled(dev_priv, pipe);
1302         assert_fdi_rx_enabled(dev_priv, pipe);
1303
1304         reg = TRANSCONF(pipe);
1305         val = I915_READ(reg);
1306         pipeconf_val = I915_READ(PIPECONF(pipe));
1307
1308         if (HAS_PCH_IBX(dev_priv->dev)) {
1309                 /*
1310                  * make the BPC in transcoder be consistent with
1311                  * that in pipeconf reg.
1312                  */
1313                 val &= ~PIPE_BPC_MASK;
1314                 val |= pipeconf_val & PIPE_BPC_MASK;
1315         }
1316
1317         val &= ~TRANS_INTERLACE_MASK;
1318         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1319                 if (HAS_PCH_IBX(dev_priv->dev) &&
1320                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1321                         val |= TRANS_LEGACY_INTERLACED_ILK;
1322                 else
1323                         val |= TRANS_INTERLACED;
1324         else
1325                 val |= TRANS_PROGRESSIVE;
1326
1327         I915_WRITE(reg, val | TRANS_ENABLE);
1328         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1329                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1330 }
1331
1332 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1333                                      enum pipe pipe)
1334 {
1335         int reg;
1336         u32 val;
1337
1338         /* FDI relies on the transcoder */
1339         assert_fdi_tx_disabled(dev_priv, pipe);
1340         assert_fdi_rx_disabled(dev_priv, pipe);
1341
1342         /* Ports must be off as well */
1343         assert_pch_ports_disabled(dev_priv, pipe);
1344
1345         reg = TRANSCONF(pipe);
1346         val = I915_READ(reg);
1347         val &= ~TRANS_ENABLE;
1348         I915_WRITE(reg, val);
1349         /* wait for PCH transcoder off, transcoder state */
1350         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1351                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1352 }
1353
1354 /**
1355  * intel_enable_pipe - enable a pipe, asserting requirements
1356  * @dev_priv: i915 private structure
1357  * @pipe: pipe to enable
1358  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1359  *
1360  * Enable @pipe, making sure that various hardware specific requirements
1361  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1362  *
1363  * @pipe should be %PIPE_A or %PIPE_B.
1364  *
1365  * Will wait until the pipe is actually running (i.e. first vblank) before
1366  * returning.
1367  */
1368 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1369                               bool pch_port)
1370 {
1371         int reg;
1372         u32 val;
1373
1374         /*
1375          * A pipe without a PLL won't actually be able to drive bits from
1376          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1377          * need the check.
1378          */
1379         if (!HAS_PCH_SPLIT(dev_priv->dev))
1380                 assert_pll_enabled(dev_priv, pipe);
1381         else {
1382                 if (pch_port) {
1383                         /* if driving the PCH, we need FDI enabled */
1384                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1385                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1386                 }
1387                 /* FIXME: assert CPU port conditions for SNB+ */
1388         }
1389
1390         reg = PIPECONF(pipe);
1391         val = I915_READ(reg);
1392         if (val & PIPECONF_ENABLE)
1393                 return;
1394
1395         I915_WRITE(reg, val | PIPECONF_ENABLE);
1396         intel_wait_for_vblank(dev_priv->dev, pipe);
1397 }
1398
1399 /**
1400  * intel_disable_pipe - disable a pipe, asserting requirements
1401  * @dev_priv: i915 private structure
1402  * @pipe: pipe to disable
1403  *
1404  * Disable @pipe, making sure that various hardware specific requirements
1405  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1406  *
1407  * @pipe should be %PIPE_A or %PIPE_B.
1408  *
1409  * Will wait until the pipe has shut down before returning.
1410  */
1411 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1412                                enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         /*
1418          * Make sure planes won't keep trying to pump pixels to us,
1419          * or we might hang the display.
1420          */
1421         assert_planes_disabled(dev_priv, pipe);
1422
1423         /* Don't disable pipe A or pipe A PLLs if needed */
1424         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1425                 return;
1426
1427         reg = PIPECONF(pipe);
1428         val = I915_READ(reg);
1429         if ((val & PIPECONF_ENABLE) == 0)
1430                 return;
1431
1432         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1433         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1434 }
1435
1436 /*
1437  * Plane regs are double buffered, going from enabled->disabled needs a
1438  * trigger in order to latch.  The display address reg provides this.
1439  */
1440 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1441                                       enum plane plane)
1442 {
1443         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1444         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1445 }
1446
1447 /**
1448  * intel_enable_plane - enable a display plane on a given pipe
1449  * @dev_priv: i915 private structure
1450  * @plane: plane to enable
1451  * @pipe: pipe being fed
1452  *
1453  * Enable @plane on @pipe, making sure that @pipe is running first.
1454  */
1455 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1456                                enum plane plane, enum pipe pipe)
1457 {
1458         int reg;
1459         u32 val;
1460
1461         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1462         assert_pipe_enabled(dev_priv, pipe);
1463
1464         reg = DSPCNTR(plane);
1465         val = I915_READ(reg);
1466         if (val & DISPLAY_PLANE_ENABLE)
1467                 return;
1468
1469         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1470         intel_flush_display_plane(dev_priv, plane);
1471         intel_wait_for_vblank(dev_priv->dev, pipe);
1472 }
1473
1474 /**
1475  * intel_disable_plane - disable a display plane
1476  * @dev_priv: i915 private structure
1477  * @plane: plane to disable
1478  * @pipe: pipe consuming the data
1479  *
1480  * Disable @plane; should be an independent operation.
1481  */
1482 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1483                                 enum plane plane, enum pipe pipe)
1484 {
1485         int reg;
1486         u32 val;
1487
1488         reg = DSPCNTR(plane);
1489         val = I915_READ(reg);
1490         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1491                 return;
1492
1493         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1494         intel_flush_display_plane(dev_priv, plane);
1495         intel_wait_for_vblank(dev_priv->dev, pipe);
1496 }
1497
1498 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1499                            enum pipe pipe, int reg, u32 port_sel)
1500 {
1501         u32 val = I915_READ(reg);
1502         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1503                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1504                 I915_WRITE(reg, val & ~DP_PORT_EN);
1505         }
1506 }
1507
1508 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1509                              enum pipe pipe, int reg)
1510 {
1511         u32 val = I915_READ(reg);
1512         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1513                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1514                               reg, pipe);
1515                 I915_WRITE(reg, val & ~PORT_ENABLE);
1516         }
1517 }
1518
1519 /* Disable any ports connected to this transcoder */
1520 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1521                                     enum pipe pipe)
1522 {
1523         u32 reg, val;
1524
1525         val = I915_READ(PCH_PP_CONTROL);
1526         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1527
1528         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1529         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1530         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1531
1532         reg = PCH_ADPA;
1533         val = I915_READ(reg);
1534         if (adpa_pipe_enabled(dev_priv, val, pipe))
1535                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1536
1537         reg = PCH_LVDS;
1538         val = I915_READ(reg);
1539         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1540                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1541                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1542                 POSTING_READ(reg);
1543                 udelay(100);
1544         }
1545
1546         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1547         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1548         disable_pch_hdmi(dev_priv, pipe, HDMID);
1549 }
1550
1551 static void i8xx_disable_fbc(struct drm_device *dev)
1552 {
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         u32 fbc_ctl;
1555
1556         /* Disable compression */
1557         fbc_ctl = I915_READ(FBC_CONTROL);
1558         if ((fbc_ctl & FBC_CTL_EN) == 0)
1559                 return;
1560
1561         fbc_ctl &= ~FBC_CTL_EN;
1562         I915_WRITE(FBC_CONTROL, fbc_ctl);
1563
1564         /* Wait for compressing bit to clear */
1565         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1566                 DRM_DEBUG_KMS("FBC idle timed out\n");
1567                 return;
1568         }
1569
1570         DRM_DEBUG_KMS("disabled FBC\n");
1571 }
1572
1573 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1574 {
1575         struct drm_device *dev = crtc->dev;
1576         struct drm_i915_private *dev_priv = dev->dev_private;
1577         struct drm_framebuffer *fb = crtc->fb;
1578         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1579         struct drm_i915_gem_object *obj = intel_fb->obj;
1580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581         int cfb_pitch;
1582         int plane, i;
1583         u32 fbc_ctl, fbc_ctl2;
1584
1585         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1586         if (fb->pitches[0] < cfb_pitch)
1587                 cfb_pitch = fb->pitches[0];
1588
1589         /* FBC_CTL wants 64B units */
1590         cfb_pitch = (cfb_pitch / 64) - 1;
1591         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1592
1593         /* Clear old tags */
1594         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1595                 I915_WRITE(FBC_TAG + (i * 4), 0);
1596
1597         /* Set it up... */
1598         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1599         fbc_ctl2 |= plane;
1600         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1601         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1602
1603         /* enable it... */
1604         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1605         if (IS_I945GM(dev))
1606                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1607         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1608         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1609         fbc_ctl |= obj->fence_reg;
1610         I915_WRITE(FBC_CONTROL, fbc_ctl);
1611
1612         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1613                       cfb_pitch, crtc->y, intel_crtc->plane);
1614 }
1615
1616 static bool i8xx_fbc_enabled(struct drm_device *dev)
1617 {
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1621 }
1622
1623 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1624 {
1625         struct drm_device *dev = crtc->dev;
1626         struct drm_i915_private *dev_priv = dev->dev_private;
1627         struct drm_framebuffer *fb = crtc->fb;
1628         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1629         struct drm_i915_gem_object *obj = intel_fb->obj;
1630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1631         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1632         unsigned long stall_watermark = 200;
1633         u32 dpfc_ctl;
1634
1635         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1636         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1637         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1638
1639         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1640                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1641                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1642         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1643
1644         /* enable it... */
1645         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1646
1647         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1648 }
1649
1650 static void g4x_disable_fbc(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 dpfc_ctl;
1654
1655         /* Disable compression */
1656         dpfc_ctl = I915_READ(DPFC_CONTROL);
1657         if (dpfc_ctl & DPFC_CTL_EN) {
1658                 dpfc_ctl &= ~DPFC_CTL_EN;
1659                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1660
1661                 DRM_DEBUG_KMS("disabled FBC\n");
1662         }
1663 }
1664
1665 static bool g4x_fbc_enabled(struct drm_device *dev)
1666 {
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668
1669         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1670 }
1671
1672 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1673 {
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         u32 blt_ecoskpd;
1676
1677         /* Make sure blitter notifies FBC of writes */
1678         gen6_gt_force_wake_get(dev_priv);
1679         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1680         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1681                 GEN6_BLITTER_LOCK_SHIFT;
1682         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1683         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1684         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1685         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1686                          GEN6_BLITTER_LOCK_SHIFT);
1687         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1688         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1689         gen6_gt_force_wake_put(dev_priv);
1690 }
1691
1692 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1693 {
1694         struct drm_device *dev = crtc->dev;
1695         struct drm_i915_private *dev_priv = dev->dev_private;
1696         struct drm_framebuffer *fb = crtc->fb;
1697         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1698         struct drm_i915_gem_object *obj = intel_fb->obj;
1699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1700         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1701         unsigned long stall_watermark = 200;
1702         u32 dpfc_ctl;
1703
1704         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1705         dpfc_ctl &= DPFC_RESERVED;
1706         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1707         /* Set persistent mode for front-buffer rendering, ala X. */
1708         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1709         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1710         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1711
1712         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1713                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1714                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1715         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1716         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1717         /* enable it... */
1718         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1719
1720         if (IS_GEN6(dev)) {
1721                 I915_WRITE(SNB_DPFC_CTL_SA,
1722                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1723                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1724                 sandybridge_blit_fbc_update(dev);
1725         }
1726
1727         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1728 }
1729
1730 static void ironlake_disable_fbc(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         u32 dpfc_ctl;
1734
1735         /* Disable compression */
1736         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1737         if (dpfc_ctl & DPFC_CTL_EN) {
1738                 dpfc_ctl &= ~DPFC_CTL_EN;
1739                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1740
1741                 DRM_DEBUG_KMS("disabled FBC\n");
1742         }
1743 }
1744
1745 static bool ironlake_fbc_enabled(struct drm_device *dev)
1746 {
1747         struct drm_i915_private *dev_priv = dev->dev_private;
1748
1749         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1750 }
1751
1752 bool intel_fbc_enabled(struct drm_device *dev)
1753 {
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755
1756         if (!dev_priv->display.fbc_enabled)
1757                 return false;
1758
1759         return dev_priv->display.fbc_enabled(dev);
1760 }
1761
1762 static void intel_fbc_work_fn(struct work_struct *__work)
1763 {
1764         struct intel_fbc_work *work =
1765                 container_of(to_delayed_work(__work),
1766                              struct intel_fbc_work, work);
1767         struct drm_device *dev = work->crtc->dev;
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769
1770         mutex_lock(&dev->struct_mutex);
1771         if (work == dev_priv->fbc_work) {
1772                 /* Double check that we haven't switched fb without cancelling
1773                  * the prior work.
1774                  */
1775                 if (work->crtc->fb == work->fb) {
1776                         dev_priv->display.enable_fbc(work->crtc,
1777                                                      work->interval);
1778
1779                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1780                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1781                         dev_priv->cfb_y = work->crtc->y;
1782                 }
1783
1784                 dev_priv->fbc_work = NULL;
1785         }
1786         mutex_unlock(&dev->struct_mutex);
1787
1788         kfree(work);
1789 }
1790
1791 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1792 {
1793         if (dev_priv->fbc_work == NULL)
1794                 return;
1795
1796         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1797
1798         /* Synchronisation is provided by struct_mutex and checking of
1799          * dev_priv->fbc_work, so we can perform the cancellation
1800          * entirely asynchronously.
1801          */
1802         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1803                 /* tasklet was killed before being run, clean up */
1804                 kfree(dev_priv->fbc_work);
1805
1806         /* Mark the work as no longer wanted so that if it does
1807          * wake-up (because the work was already running and waiting
1808          * for our mutex), it will discover that is no longer
1809          * necessary to run.
1810          */
1811         dev_priv->fbc_work = NULL;
1812 }
1813
1814 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1815 {
1816         struct intel_fbc_work *work;
1817         struct drm_device *dev = crtc->dev;
1818         struct drm_i915_private *dev_priv = dev->dev_private;
1819
1820         if (!dev_priv->display.enable_fbc)
1821                 return;
1822
1823         intel_cancel_fbc_work(dev_priv);
1824
1825         work = kzalloc(sizeof *work, GFP_KERNEL);
1826         if (work == NULL) {
1827                 dev_priv->display.enable_fbc(crtc, interval);
1828                 return;
1829         }
1830
1831         work->crtc = crtc;
1832         work->fb = crtc->fb;
1833         work->interval = interval;
1834         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1835
1836         dev_priv->fbc_work = work;
1837
1838         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1839
1840         /* Delay the actual enabling to let pageflipping cease and the
1841          * display to settle before starting the compression. Note that
1842          * this delay also serves a second purpose: it allows for a
1843          * vblank to pass after disabling the FBC before we attempt
1844          * to modify the control registers.
1845          *
1846          * A more complicated solution would involve tracking vblanks
1847          * following the termination of the page-flipping sequence
1848          * and indeed performing the enable as a co-routine and not
1849          * waiting synchronously upon the vblank.
1850          */
1851         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1852 }
1853
1854 void intel_disable_fbc(struct drm_device *dev)
1855 {
1856         struct drm_i915_private *dev_priv = dev->dev_private;
1857
1858         intel_cancel_fbc_work(dev_priv);
1859
1860         if (!dev_priv->display.disable_fbc)
1861                 return;
1862
1863         dev_priv->display.disable_fbc(dev);
1864         dev_priv->cfb_plane = -1;
1865 }
1866
1867 /**
1868  * intel_update_fbc - enable/disable FBC as needed
1869  * @dev: the drm_device
1870  *
1871  * Set up the framebuffer compression hardware at mode set time.  We
1872  * enable it if possible:
1873  *   - plane A only (on pre-965)
1874  *   - no pixel mulitply/line duplication
1875  *   - no alpha buffer discard
1876  *   - no dual wide
1877  *   - framebuffer <= 2048 in width, 1536 in height
1878  *
1879  * We can't assume that any compression will take place (worst case),
1880  * so the compressed buffer has to be the same size as the uncompressed
1881  * one.  It also must reside (along with the line length buffer) in
1882  * stolen memory.
1883  *
1884  * We need to enable/disable FBC on a global basis.
1885  */
1886 static void intel_update_fbc(struct drm_device *dev)
1887 {
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889         struct drm_crtc *crtc = NULL, *tmp_crtc;
1890         struct intel_crtc *intel_crtc;
1891         struct drm_framebuffer *fb;
1892         struct intel_framebuffer *intel_fb;
1893         struct drm_i915_gem_object *obj;
1894         int enable_fbc;
1895
1896         DRM_DEBUG_KMS("\n");
1897
1898         if (!i915_powersave)
1899                 return;
1900
1901         if (!I915_HAS_FBC(dev))
1902                 return;
1903
1904         /*
1905          * If FBC is already on, we just have to verify that we can
1906          * keep it that way...
1907          * Need to disable if:
1908          *   - more than one pipe is active
1909          *   - changing FBC params (stride, fence, mode)
1910          *   - new fb is too large to fit in compressed buffer
1911          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1912          */
1913         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1914                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1915                         if (crtc) {
1916                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1917                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1918                                 goto out_disable;
1919                         }
1920                         crtc = tmp_crtc;
1921                 }
1922         }
1923
1924         if (!crtc || crtc->fb == NULL) {
1925                 DRM_DEBUG_KMS("no output, disabling\n");
1926                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1927                 goto out_disable;
1928         }
1929
1930         intel_crtc = to_intel_crtc(crtc);
1931         fb = crtc->fb;
1932         intel_fb = to_intel_framebuffer(fb);
1933         obj = intel_fb->obj;
1934
1935         enable_fbc = i915_enable_fbc;
1936         if (enable_fbc < 0) {
1937                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1938                 enable_fbc = 1;
1939                 if (INTEL_INFO(dev)->gen <= 6)
1940                         enable_fbc = 0;
1941         }
1942         if (!enable_fbc) {
1943                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1944                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1945                 goto out_disable;
1946         }
1947         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1948                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1949                               "compression\n");
1950                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1951                 goto out_disable;
1952         }
1953         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1954             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1955                 DRM_DEBUG_KMS("mode incompatible with compression, "
1956                               "disabling\n");
1957                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1958                 goto out_disable;
1959         }
1960         if ((crtc->mode.hdisplay > 2048) ||
1961             (crtc->mode.vdisplay > 1536)) {
1962                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1963                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1964                 goto out_disable;
1965         }
1966         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1967                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1968                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1969                 goto out_disable;
1970         }
1971
1972         /* The use of a CPU fence is mandatory in order to detect writes
1973          * by the CPU to the scanout and trigger updates to the FBC.
1974          */
1975         if (obj->tiling_mode != I915_TILING_X ||
1976             obj->fence_reg == I915_FENCE_REG_NONE) {
1977                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1978                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1979                 goto out_disable;
1980         }
1981
1982         /* If the kernel debugger is active, always disable compression */
1983         if (in_dbg_master())
1984                 goto out_disable;
1985
1986         /* If the scanout has not changed, don't modify the FBC settings.
1987          * Note that we make the fundamental assumption that the fb->obj
1988          * cannot be unpinned (and have its GTT offset and fence revoked)
1989          * without first being decoupled from the scanout and FBC disabled.
1990          */
1991         if (dev_priv->cfb_plane == intel_crtc->plane &&
1992             dev_priv->cfb_fb == fb->base.id &&
1993             dev_priv->cfb_y == crtc->y)
1994                 return;
1995
1996         if (intel_fbc_enabled(dev)) {
1997                 /* We update FBC along two paths, after changing fb/crtc
1998                  * configuration (modeswitching) and after page-flipping
1999                  * finishes. For the latter, we know that not only did
2000                  * we disable the FBC at the start of the page-flip
2001                  * sequence, but also more than one vblank has passed.
2002                  *
2003                  * For the former case of modeswitching, it is possible
2004                  * to switch between two FBC valid configurations
2005                  * instantaneously so we do need to disable the FBC
2006                  * before we can modify its control registers. We also
2007                  * have to wait for the next vblank for that to take
2008                  * effect. However, since we delay enabling FBC we can
2009                  * assume that a vblank has passed since disabling and
2010                  * that we can safely alter the registers in the deferred
2011                  * callback.
2012                  *
2013                  * In the scenario that we go from a valid to invalid
2014                  * and then back to valid FBC configuration we have
2015                  * no strict enforcement that a vblank occurred since
2016                  * disabling the FBC. However, along all current pipe
2017                  * disabling paths we do need to wait for a vblank at
2018                  * some point. And we wait before enabling FBC anyway.
2019                  */
2020                 DRM_DEBUG_KMS("disabling active FBC for update\n");
2021                 intel_disable_fbc(dev);
2022         }
2023
2024         intel_enable_fbc(crtc, 500);
2025         return;
2026
2027 out_disable:
2028         /* Multiple disables should be harmless */
2029         if (intel_fbc_enabled(dev)) {
2030                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2031                 intel_disable_fbc(dev);
2032         }
2033 }
2034
2035 int
2036 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2037                            struct drm_i915_gem_object *obj,
2038                            struct intel_ring_buffer *pipelined)
2039 {
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         u32 alignment;
2042         int ret;
2043
2044         switch (obj->tiling_mode) {
2045         case I915_TILING_NONE:
2046                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2047                         alignment = 128 * 1024;
2048                 else if (INTEL_INFO(dev)->gen >= 4)
2049                         alignment = 4 * 1024;
2050                 else
2051                         alignment = 64 * 1024;
2052                 break;
2053         case I915_TILING_X:
2054                 /* pin() will align the object as required by fence */
2055                 alignment = 0;
2056                 break;
2057         case I915_TILING_Y:
2058                 /* FIXME: Is this true? */
2059                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2060                 return -EINVAL;
2061         default:
2062                 BUG();
2063         }
2064
2065         dev_priv->mm.interruptible = false;
2066         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2067         if (ret)
2068                 goto err_interruptible;
2069
2070         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2071          * fence, whereas 965+ only requires a fence if using
2072          * framebuffer compression.  For simplicity, we always install
2073          * a fence as the cost is not that onerous.
2074          */
2075         if (obj->tiling_mode != I915_TILING_NONE) {
2076                 ret = i915_gem_object_get_fence(obj, pipelined);
2077                 if (ret)
2078                         goto err_unpin;
2079
2080                 i915_gem_object_pin_fence(obj);
2081         }
2082
2083         dev_priv->mm.interruptible = true;
2084         return 0;
2085
2086 err_unpin:
2087         i915_gem_object_unpin(obj);
2088 err_interruptible:
2089         dev_priv->mm.interruptible = true;
2090         return ret;
2091 }
2092
2093 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2094 {
2095         i915_gem_object_unpin_fence(obj);
2096         i915_gem_object_unpin(obj);
2097 }
2098
2099 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2100                              int x, int y)
2101 {
2102         struct drm_device *dev = crtc->dev;
2103         struct drm_i915_private *dev_priv = dev->dev_private;
2104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2105         struct intel_framebuffer *intel_fb;
2106         struct drm_i915_gem_object *obj;
2107         int plane = intel_crtc->plane;
2108         unsigned long Start, Offset;
2109         u32 dspcntr;
2110         u32 reg;
2111
2112         switch (plane) {
2113         case 0:
2114         case 1:
2115                 break;
2116         default:
2117                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2118                 return -EINVAL;
2119         }
2120
2121         intel_fb = to_intel_framebuffer(fb);
2122         obj = intel_fb->obj;
2123
2124         reg = DSPCNTR(plane);
2125         dspcntr = I915_READ(reg);
2126         /* Mask out pixel format bits in case we change it */
2127         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2128         switch (fb->bits_per_pixel) {
2129         case 8:
2130                 dspcntr |= DISPPLANE_8BPP;
2131                 break;
2132         case 16:
2133                 if (fb->depth == 15)
2134                         dspcntr |= DISPPLANE_15_16BPP;
2135                 else
2136                         dspcntr |= DISPPLANE_16BPP;
2137                 break;
2138         case 24:
2139         case 32:
2140                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2141                 break;
2142         default:
2143                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2144                 return -EINVAL;
2145         }
2146         if (INTEL_INFO(dev)->gen >= 4) {
2147                 if (obj->tiling_mode != I915_TILING_NONE)
2148                         dspcntr |= DISPPLANE_TILED;
2149                 else
2150                         dspcntr &= ~DISPPLANE_TILED;
2151         }
2152
2153         I915_WRITE(reg, dspcntr);
2154
2155         Start = obj->gtt_offset;
2156         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2157
2158         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2159                       Start, Offset, x, y, fb->pitches[0]);
2160         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2161         if (INTEL_INFO(dev)->gen >= 4) {
2162                 I915_WRITE(DSPSURF(plane), Start);
2163                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164                 I915_WRITE(DSPADDR(plane), Offset);
2165         } else
2166                 I915_WRITE(DSPADDR(plane), Start + Offset);
2167         POSTING_READ(reg);
2168
2169         return 0;
2170 }
2171
2172 static int ironlake_update_plane(struct drm_crtc *crtc,
2173                                  struct drm_framebuffer *fb, int x, int y)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178         struct intel_framebuffer *intel_fb;
2179         struct drm_i915_gem_object *obj;
2180         int plane = intel_crtc->plane;
2181         unsigned long Start, Offset;
2182         u32 dspcntr;
2183         u32 reg;
2184
2185         switch (plane) {
2186         case 0:
2187         case 1:
2188         case 2:
2189                 break;
2190         default:
2191                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2192                 return -EINVAL;
2193         }
2194
2195         intel_fb = to_intel_framebuffer(fb);
2196         obj = intel_fb->obj;
2197
2198         reg = DSPCNTR(plane);
2199         dspcntr = I915_READ(reg);
2200         /* Mask out pixel format bits in case we change it */
2201         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2202         switch (fb->bits_per_pixel) {
2203         case 8:
2204                 dspcntr |= DISPPLANE_8BPP;
2205                 break;
2206         case 16:
2207                 if (fb->depth != 16)
2208                         return -EINVAL;
2209
2210                 dspcntr |= DISPPLANE_16BPP;
2211                 break;
2212         case 24:
2213         case 32:
2214                 if (fb->depth == 24)
2215                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2216                 else if (fb->depth == 30)
2217                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2218                 else
2219                         return -EINVAL;
2220                 break;
2221         default:
2222                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2223                 return -EINVAL;
2224         }
2225
2226         if (obj->tiling_mode != I915_TILING_NONE)
2227                 dspcntr |= DISPPLANE_TILED;
2228         else
2229                 dspcntr &= ~DISPPLANE_TILED;
2230
2231         /* must disable */
2232         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2233
2234         I915_WRITE(reg, dspcntr);
2235
2236         Start = obj->gtt_offset;
2237         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2238
2239         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2240                       Start, Offset, x, y, fb->pitches[0]);
2241         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2242         I915_WRITE(DSPSURF(plane), Start);
2243         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2244         I915_WRITE(DSPADDR(plane), Offset);
2245         POSTING_READ(reg);
2246
2247         return 0;
2248 }
2249
2250 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2251 static int
2252 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2253                            int x, int y, enum mode_set_atomic state)
2254 {
2255         struct drm_device *dev = crtc->dev;
2256         struct drm_i915_private *dev_priv = dev->dev_private;
2257         int ret;
2258
2259         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2260         if (ret)
2261                 return ret;
2262
2263         intel_update_fbc(dev);
2264         intel_increase_pllclock(crtc);
2265
2266         return 0;
2267 }
2268
2269 static int
2270 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2271                     struct drm_framebuffer *old_fb)
2272 {
2273         struct drm_device *dev = crtc->dev;
2274         struct drm_i915_master_private *master_priv;
2275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2276         int ret;
2277
2278         /* no fb bound */
2279         if (!crtc->fb) {
2280                 DRM_ERROR("No FB bound\n");
2281                 return 0;
2282         }
2283
2284         switch (intel_crtc->plane) {
2285         case 0:
2286         case 1:
2287                 break;
2288         case 2:
2289                 if (IS_IVYBRIDGE(dev))
2290                         break;
2291                 /* fall through otherwise */
2292         default:
2293                 DRM_ERROR("no plane for crtc\n");
2294                 return -EINVAL;
2295         }
2296
2297         mutex_lock(&dev->struct_mutex);
2298         ret = intel_pin_and_fence_fb_obj(dev,
2299                                          to_intel_framebuffer(crtc->fb)->obj,
2300                                          NULL);
2301         if (ret != 0) {
2302                 mutex_unlock(&dev->struct_mutex);
2303                 DRM_ERROR("pin & fence failed\n");
2304                 return ret;
2305         }
2306
2307         if (old_fb) {
2308                 struct drm_i915_private *dev_priv = dev->dev_private;
2309                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2310
2311                 wait_event(dev_priv->pending_flip_queue,
2312                            atomic_read(&dev_priv->mm.wedged) ||
2313                            atomic_read(&obj->pending_flip) == 0);
2314
2315                 /* Big Hammer, we also need to ensure that any pending
2316                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2317                  * current scanout is retired before unpinning the old
2318                  * framebuffer.
2319                  *
2320                  * This should only fail upon a hung GPU, in which case we
2321                  * can safely continue.
2322                  */
2323                 ret = i915_gem_object_finish_gpu(obj);
2324                 (void) ret;
2325         }
2326
2327         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2328                                          LEAVE_ATOMIC_MODE_SET);
2329         if (ret) {
2330                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2331                 mutex_unlock(&dev->struct_mutex);
2332                 DRM_ERROR("failed to update base address\n");
2333                 return ret;
2334         }
2335
2336         if (old_fb) {
2337                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2339         }
2340
2341         mutex_unlock(&dev->struct_mutex);
2342
2343         if (!dev->primary->master)
2344                 return 0;
2345
2346         master_priv = dev->primary->master->driver_priv;
2347         if (!master_priv->sarea_priv)
2348                 return 0;
2349
2350         if (intel_crtc->pipe) {
2351                 master_priv->sarea_priv->pipeB_x = x;
2352                 master_priv->sarea_priv->pipeB_y = y;
2353         } else {
2354                 master_priv->sarea_priv->pipeA_x = x;
2355                 master_priv->sarea_priv->pipeA_y = y;
2356         }
2357
2358         return 0;
2359 }
2360
2361 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2362 {
2363         struct drm_device *dev = crtc->dev;
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         u32 dpa_ctl;
2366
2367         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2368         dpa_ctl = I915_READ(DP_A);
2369         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2370
2371         if (clock < 200000) {
2372                 u32 temp;
2373                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2374                 /* workaround for 160Mhz:
2375                    1) program 0x4600c bits 15:0 = 0x8124
2376                    2) program 0x46010 bit 0 = 1
2377                    3) program 0x46034 bit 24 = 1
2378                    4) program 0x64000 bit 14 = 1
2379                    */
2380                 temp = I915_READ(0x4600c);
2381                 temp &= 0xffff0000;
2382                 I915_WRITE(0x4600c, temp | 0x8124);
2383
2384                 temp = I915_READ(0x46010);
2385                 I915_WRITE(0x46010, temp | 1);
2386
2387                 temp = I915_READ(0x46034);
2388                 I915_WRITE(0x46034, temp | (1 << 24));
2389         } else {
2390                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2391         }
2392         I915_WRITE(DP_A, dpa_ctl);
2393
2394         POSTING_READ(DP_A);
2395         udelay(500);
2396 }
2397
2398 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         u32 reg, temp;
2405
2406         /* enable normal train */
2407         reg = FDI_TX_CTL(pipe);
2408         temp = I915_READ(reg);
2409         if (IS_IVYBRIDGE(dev)) {
2410                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2411                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2412         } else {
2413                 temp &= ~FDI_LINK_TRAIN_NONE;
2414                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2415         }
2416         I915_WRITE(reg, temp);
2417
2418         reg = FDI_RX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         if (HAS_PCH_CPT(dev)) {
2421                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2422                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2423         } else {
2424                 temp &= ~FDI_LINK_TRAIN_NONE;
2425                 temp |= FDI_LINK_TRAIN_NONE;
2426         }
2427         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2428
2429         /* wait one idle pattern time */
2430         POSTING_READ(reg);
2431         udelay(1000);
2432
2433         /* IVB wants error correction enabled */
2434         if (IS_IVYBRIDGE(dev))
2435                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2436                            FDI_FE_ERRC_ENABLE);
2437 }
2438
2439 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         u32 flags = I915_READ(SOUTH_CHICKEN1);
2443
2444         flags |= FDI_PHASE_SYNC_OVR(pipe);
2445         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2446         flags |= FDI_PHASE_SYNC_EN(pipe);
2447         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2448         POSTING_READ(SOUTH_CHICKEN1);
2449 }
2450
2451 /* The FDI link training functions for ILK/Ibexpeak. */
2452 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2453 {
2454         struct drm_device *dev = crtc->dev;
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457         int pipe = intel_crtc->pipe;
2458         int plane = intel_crtc->plane;
2459         u32 reg, temp, tries;
2460
2461         /* FDI needs bits from pipe & plane first */
2462         assert_pipe_enabled(dev_priv, pipe);
2463         assert_plane_enabled(dev_priv, plane);
2464
2465         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2466            for train result */
2467         reg = FDI_RX_IMR(pipe);
2468         temp = I915_READ(reg);
2469         temp &= ~FDI_RX_SYMBOL_LOCK;
2470         temp &= ~FDI_RX_BIT_LOCK;
2471         I915_WRITE(reg, temp);
2472         I915_READ(reg);
2473         udelay(150);
2474
2475         /* enable CPU FDI TX and PCH FDI RX */
2476         reg = FDI_TX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~(7 << 19);
2479         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2480         temp &= ~FDI_LINK_TRAIN_NONE;
2481         temp |= FDI_LINK_TRAIN_PATTERN_1;
2482         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2483
2484         reg = FDI_RX_CTL(pipe);
2485         temp = I915_READ(reg);
2486         temp &= ~FDI_LINK_TRAIN_NONE;
2487         temp |= FDI_LINK_TRAIN_PATTERN_1;
2488         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2489
2490         POSTING_READ(reg);
2491         udelay(150);
2492
2493         /* Ironlake workaround, enable clock pointer after FDI enable*/
2494         if (HAS_PCH_IBX(dev)) {
2495                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2496                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2497                            FDI_RX_PHASE_SYNC_POINTER_EN);
2498         }
2499
2500         reg = FDI_RX_IIR(pipe);
2501         for (tries = 0; tries < 5; tries++) {
2502                 temp = I915_READ(reg);
2503                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504
2505                 if ((temp & FDI_RX_BIT_LOCK)) {
2506                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2507                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2508                         break;
2509                 }
2510         }
2511         if (tries == 5)
2512                 DRM_ERROR("FDI train 1 fail!\n");
2513
2514         /* Train 2 */
2515         reg = FDI_TX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         temp &= ~FDI_LINK_TRAIN_NONE;
2518         temp |= FDI_LINK_TRAIN_PATTERN_2;
2519         I915_WRITE(reg, temp);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_2;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         reg = FDI_RX_IIR(pipe);
2531         for (tries = 0; tries < 5; tries++) {
2532                 temp = I915_READ(reg);
2533                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2534
2535                 if (temp & FDI_RX_SYMBOL_LOCK) {
2536                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2538                         break;
2539                 }
2540         }
2541         if (tries == 5)
2542                 DRM_ERROR("FDI train 2 fail!\n");
2543
2544         DRM_DEBUG_KMS("FDI train done\n");
2545
2546 }
2547
2548 static const int snb_b_fdi_train_param[] = {
2549         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2550         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2551         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2552         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2553 };
2554
2555 /* The FDI link training functions for SNB/Cougarpoint. */
2556 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2557 {
2558         struct drm_device *dev = crtc->dev;
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2561         int pipe = intel_crtc->pipe;
2562         u32 reg, temp, i, retry;
2563
2564         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2565            for train result */
2566         reg = FDI_RX_IMR(pipe);
2567         temp = I915_READ(reg);
2568         temp &= ~FDI_RX_SYMBOL_LOCK;
2569         temp &= ~FDI_RX_BIT_LOCK;
2570         I915_WRITE(reg, temp);
2571
2572         POSTING_READ(reg);
2573         udelay(150);
2574
2575         /* enable CPU FDI TX and PCH FDI RX */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~(7 << 19);
2579         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2580         temp &= ~FDI_LINK_TRAIN_NONE;
2581         temp |= FDI_LINK_TRAIN_PATTERN_1;
2582         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583         /* SNB-B */
2584         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
2587         reg = FDI_RX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         if (HAS_PCH_CPT(dev)) {
2590                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2592         } else {
2593                 temp &= ~FDI_LINK_TRAIN_NONE;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2595         }
2596         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         if (HAS_PCH_CPT(dev))
2602                 cpt_phase_pointer_enable(dev, pipe);
2603
2604         for (i = 0; i < 4; i++) {
2605                 reg = FDI_TX_CTL(pipe);
2606                 temp = I915_READ(reg);
2607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608                 temp |= snb_b_fdi_train_param[i];
2609                 I915_WRITE(reg, temp);
2610
2611                 POSTING_READ(reg);
2612                 udelay(500);
2613
2614                 for (retry = 0; retry < 5; retry++) {
2615                         reg = FDI_RX_IIR(pipe);
2616                         temp = I915_READ(reg);
2617                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618                         if (temp & FDI_RX_BIT_LOCK) {
2619                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621                                 break;
2622                         }
2623                         udelay(50);
2624                 }
2625                 if (retry < 5)
2626                         break;
2627         }
2628         if (i == 4)
2629                 DRM_ERROR("FDI train 1 fail!\n");
2630
2631         /* Train 2 */
2632         reg = FDI_TX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_NONE;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2;
2636         if (IS_GEN6(dev)) {
2637                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638                 /* SNB-B */
2639                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         }
2641         I915_WRITE(reg, temp);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         if (HAS_PCH_CPT(dev)) {
2646                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2648         } else {
2649                 temp &= ~FDI_LINK_TRAIN_NONE;
2650                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         for (i = 0; i < 4; i++) {
2658                 reg = FDI_TX_CTL(pipe);
2659                 temp = I915_READ(reg);
2660                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661                 temp |= snb_b_fdi_train_param[i];
2662                 I915_WRITE(reg, temp);
2663
2664                 POSTING_READ(reg);
2665                 udelay(500);
2666
2667                 for (retry = 0; retry < 5; retry++) {
2668                         reg = FDI_RX_IIR(pipe);
2669                         temp = I915_READ(reg);
2670                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2671                         if (temp & FDI_RX_SYMBOL_LOCK) {
2672                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2673                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2674                                 break;
2675                         }
2676                         udelay(50);
2677                 }
2678                 if (retry < 5)
2679                         break;
2680         }
2681         if (i == 4)
2682                 DRM_ERROR("FDI train 2 fail!\n");
2683
2684         DRM_DEBUG_KMS("FDI train done.\n");
2685 }
2686
2687 /* Manual link training for Ivy Bridge A0 parts */
2688 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2689 {
2690         struct drm_device *dev = crtc->dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693         int pipe = intel_crtc->pipe;
2694         u32 reg, temp, i;
2695
2696         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2697            for train result */
2698         reg = FDI_RX_IMR(pipe);
2699         temp = I915_READ(reg);
2700         temp &= ~FDI_RX_SYMBOL_LOCK;
2701         temp &= ~FDI_RX_BIT_LOCK;
2702         I915_WRITE(reg, temp);
2703
2704         POSTING_READ(reg);
2705         udelay(150);
2706
2707         /* enable CPU FDI TX and PCH FDI RX */
2708         reg = FDI_TX_CTL(pipe);
2709         temp = I915_READ(reg);
2710         temp &= ~(7 << 19);
2711         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2712         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2713         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2714         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2715         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2716         temp |= FDI_COMPOSITE_SYNC;
2717         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2718
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         temp &= ~FDI_LINK_TRAIN_AUTO;
2722         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2724         temp |= FDI_COMPOSITE_SYNC;
2725         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2726
2727         POSTING_READ(reg);
2728         udelay(150);
2729
2730         if (HAS_PCH_CPT(dev))
2731                 cpt_phase_pointer_enable(dev, pipe);
2732
2733         for (i = 0; i < 4; i++) {
2734                 reg = FDI_TX_CTL(pipe);
2735                 temp = I915_READ(reg);
2736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737                 temp |= snb_b_fdi_train_param[i];
2738                 I915_WRITE(reg, temp);
2739
2740                 POSTING_READ(reg);
2741                 udelay(500);
2742
2743                 reg = FDI_RX_IIR(pipe);
2744                 temp = I915_READ(reg);
2745                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2746
2747                 if (temp & FDI_RX_BIT_LOCK ||
2748                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2749                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2750                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2751                         break;
2752                 }
2753         }
2754         if (i == 4)
2755                 DRM_ERROR("FDI train 1 fail!\n");
2756
2757         /* Train 2 */
2758         reg = FDI_TX_CTL(pipe);
2759         temp = I915_READ(reg);
2760         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2761         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2762         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2763         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2764         I915_WRITE(reg, temp);
2765
2766         reg = FDI_RX_CTL(pipe);
2767         temp = I915_READ(reg);
2768         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2770         I915_WRITE(reg, temp);
2771
2772         POSTING_READ(reg);
2773         udelay(150);
2774
2775         for (i = 0; i < 4; i++) {
2776                 reg = FDI_TX_CTL(pipe);
2777                 temp = I915_READ(reg);
2778                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779                 temp |= snb_b_fdi_train_param[i];
2780                 I915_WRITE(reg, temp);
2781
2782                 POSTING_READ(reg);
2783                 udelay(500);
2784
2785                 reg = FDI_RX_IIR(pipe);
2786                 temp = I915_READ(reg);
2787                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2788
2789                 if (temp & FDI_RX_SYMBOL_LOCK) {
2790                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2791                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2792                         break;
2793                 }
2794         }
2795         if (i == 4)
2796                 DRM_ERROR("FDI train 2 fail!\n");
2797
2798         DRM_DEBUG_KMS("FDI train done.\n");
2799 }
2800
2801 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2802 {
2803         struct drm_device *dev = crtc->dev;
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806         int pipe = intel_crtc->pipe;
2807         u32 reg, temp;
2808
2809         /* Write the TU size bits so error detection works */
2810         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2811                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~((0x7 << 19) | (0x7 << 16));
2817         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* Enable CPU FDI TX PLL, always on for Ironlake */
2832         reg = FDI_TX_CTL(pipe);
2833         temp = I915_READ(reg);
2834         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2835                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2836
2837                 POSTING_READ(reg);
2838                 udelay(100);
2839         }
2840 }
2841
2842 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2843 {
2844         struct drm_i915_private *dev_priv = dev->dev_private;
2845         u32 flags = I915_READ(SOUTH_CHICKEN1);
2846
2847         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2848         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2849         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2850         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2851         POSTING_READ(SOUTH_CHICKEN1);
2852 }
2853 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2854 {
2855         struct drm_device *dev = crtc->dev;
2856         struct drm_i915_private *dev_priv = dev->dev_private;
2857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2858         int pipe = intel_crtc->pipe;
2859         u32 reg, temp;
2860
2861         /* disable CPU FDI tx and PCH FDI rx */
2862         reg = FDI_TX_CTL(pipe);
2863         temp = I915_READ(reg);
2864         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2865         POSTING_READ(reg);
2866
2867         reg = FDI_RX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         temp &= ~(0x7 << 16);
2870         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2871         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2872
2873         POSTING_READ(reg);
2874         udelay(100);
2875
2876         /* Ironlake workaround, disable clock pointer after downing FDI */
2877         if (HAS_PCH_IBX(dev)) {
2878                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2879                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2880                            I915_READ(FDI_RX_CHICKEN(pipe) &
2881                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2882         } else if (HAS_PCH_CPT(dev)) {
2883                 cpt_phase_pointer_disable(dev, pipe);
2884         }
2885
2886         /* still set train pattern 1 */
2887         reg = FDI_TX_CTL(pipe);
2888         temp = I915_READ(reg);
2889         temp &= ~FDI_LINK_TRAIN_NONE;
2890         temp |= FDI_LINK_TRAIN_PATTERN_1;
2891         I915_WRITE(reg, temp);
2892
2893         reg = FDI_RX_CTL(pipe);
2894         temp = I915_READ(reg);
2895         if (HAS_PCH_CPT(dev)) {
2896                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2897                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2898         } else {
2899                 temp &= ~FDI_LINK_TRAIN_NONE;
2900                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2901         }
2902         /* BPC in FDI rx is consistent with that in PIPECONF */
2903         temp &= ~(0x07 << 16);
2904         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2905         I915_WRITE(reg, temp);
2906
2907         POSTING_READ(reg);
2908         udelay(100);
2909 }
2910
2911 /*
2912  * When we disable a pipe, we need to clear any pending scanline wait events
2913  * to avoid hanging the ring, which we assume we are waiting on.
2914  */
2915 static void intel_clear_scanline_wait(struct drm_device *dev)
2916 {
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         struct intel_ring_buffer *ring;
2919         u32 tmp;
2920
2921         if (IS_GEN2(dev))
2922                 /* Can't break the hang on i8xx */
2923                 return;
2924
2925         ring = LP_RING(dev_priv);
2926         tmp = I915_READ_CTL(ring);
2927         if (tmp & RING_WAIT)
2928                 I915_WRITE_CTL(ring, tmp);
2929 }
2930
2931 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2932 {
2933         struct drm_i915_gem_object *obj;
2934         struct drm_i915_private *dev_priv;
2935
2936         if (crtc->fb == NULL)
2937                 return;
2938
2939         obj = to_intel_framebuffer(crtc->fb)->obj;
2940         dev_priv = crtc->dev->dev_private;
2941         wait_event(dev_priv->pending_flip_queue,
2942                    atomic_read(&obj->pending_flip) == 0);
2943 }
2944
2945 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_mode_config *mode_config = &dev->mode_config;
2949         struct intel_encoder *encoder;
2950
2951         /*
2952          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2953          * must be driven by its own crtc; no sharing is possible.
2954          */
2955         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2956                 if (encoder->base.crtc != crtc)
2957                         continue;
2958
2959                 switch (encoder->type) {
2960                 case INTEL_OUTPUT_EDP:
2961                         if (!intel_encoder_is_pch_edp(&encoder->base))
2962                                 return false;
2963                         continue;
2964                 }
2965         }
2966
2967         return true;
2968 }
2969
2970 /*
2971  * Enable PCH resources required for PCH ports:
2972  *   - PCH PLLs
2973  *   - FDI training & RX/TX
2974  *   - update transcoder timings
2975  *   - DP transcoding bits
2976  *   - transcoder
2977  */
2978 static void ironlake_pch_enable(struct drm_crtc *crtc)
2979 {
2980         struct drm_device *dev = crtc->dev;
2981         struct drm_i915_private *dev_priv = dev->dev_private;
2982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2983         int pipe = intel_crtc->pipe;
2984         u32 reg, temp, transc_sel;
2985
2986         /* For PCH output, training FDI link */
2987         dev_priv->display.fdi_link_train(crtc);
2988
2989         intel_enable_pch_pll(dev_priv, pipe);
2990
2991         if (HAS_PCH_CPT(dev)) {
2992                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2993                         TRANSC_DPLLB_SEL;
2994
2995                 /* Be sure PCH DPLL SEL is set */
2996                 temp = I915_READ(PCH_DPLL_SEL);
2997                 if (pipe == 0) {
2998                         temp &= ~(TRANSA_DPLLB_SEL);
2999                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3000                 } else if (pipe == 1) {
3001                         temp &= ~(TRANSB_DPLLB_SEL);
3002                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3003                 } else if (pipe == 2) {
3004                         temp &= ~(TRANSC_DPLLB_SEL);
3005                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3006                 }
3007                 I915_WRITE(PCH_DPLL_SEL, temp);
3008         }
3009
3010         /* set transcoder timing, panel must allow it */
3011         assert_panel_unlocked(dev_priv, pipe);
3012         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3013         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3014         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3015
3016         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3017         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3018         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3019         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3020
3021         intel_fdi_normal_train(crtc);
3022
3023         /* For PCH DP, enable TRANS_DP_CTL */
3024         if (HAS_PCH_CPT(dev) &&
3025             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3026              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3027                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3028                 reg = TRANS_DP_CTL(pipe);
3029                 temp = I915_READ(reg);
3030                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3031                           TRANS_DP_SYNC_MASK |
3032                           TRANS_DP_BPC_MASK);
3033                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3034                          TRANS_DP_ENH_FRAMING);
3035                 temp |= bpc << 9; /* same format but at 11:9 */
3036
3037                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3038                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3039                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3040                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3041
3042                 switch (intel_trans_dp_port_sel(crtc)) {
3043                 case PCH_DP_B:
3044                         temp |= TRANS_DP_PORT_SEL_B;
3045                         break;
3046                 case PCH_DP_C:
3047                         temp |= TRANS_DP_PORT_SEL_C;
3048                         break;
3049                 case PCH_DP_D:
3050                         temp |= TRANS_DP_PORT_SEL_D;
3051                         break;
3052                 default:
3053                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3054                         temp |= TRANS_DP_PORT_SEL_B;
3055                         break;
3056                 }
3057
3058                 I915_WRITE(reg, temp);
3059         }
3060
3061         intel_enable_transcoder(dev_priv, pipe);
3062 }
3063
3064 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3065 {
3066         struct drm_i915_private *dev_priv = dev->dev_private;
3067         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3068         u32 temp;
3069
3070         temp = I915_READ(dslreg);
3071         udelay(500);
3072         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3073                 /* Without this, mode sets may fail silently on FDI */
3074                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3075                 udelay(250);
3076                 I915_WRITE(tc2reg, 0);
3077                 if (wait_for(I915_READ(dslreg) != temp, 5))
3078                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3079         }
3080 }
3081
3082 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         int plane = intel_crtc->plane;
3089         u32 temp;
3090         bool is_pch_port;
3091
3092         if (intel_crtc->active)
3093                 return;
3094
3095         intel_crtc->active = true;
3096         intel_update_watermarks(dev);
3097
3098         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3099                 temp = I915_READ(PCH_LVDS);
3100                 if ((temp & LVDS_PORT_EN) == 0)
3101                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3102         }
3103
3104         is_pch_port = intel_crtc_driving_pch(crtc);
3105
3106         if (is_pch_port)
3107                 ironlake_fdi_pll_enable(crtc);
3108         else
3109                 ironlake_fdi_disable(crtc);
3110
3111         /* Enable panel fitting for LVDS */
3112         if (dev_priv->pch_pf_size &&
3113             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3114                 /* Force use of hard-coded filter coefficients
3115                  * as some pre-programmed values are broken,
3116                  * e.g. x201.
3117                  */
3118                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3119                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3120                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3121         }
3122
3123         /*
3124          * On ILK+ LUT must be loaded before the pipe is running but with
3125          * clocks enabled
3126          */
3127         intel_crtc_load_lut(crtc);
3128
3129         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3130         intel_enable_plane(dev_priv, plane, pipe);
3131
3132         if (is_pch_port)
3133                 ironlake_pch_enable(crtc);
3134
3135         mutex_lock(&dev->struct_mutex);
3136         intel_update_fbc(dev);
3137         mutex_unlock(&dev->struct_mutex);
3138
3139         intel_crtc_update_cursor(crtc, true);
3140 }
3141
3142 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3147         int pipe = intel_crtc->pipe;
3148         int plane = intel_crtc->plane;
3149         u32 reg, temp;
3150
3151         if (!intel_crtc->active)
3152                 return;
3153
3154         intel_crtc_wait_for_pending_flips(crtc);
3155         drm_vblank_off(dev, pipe);
3156         intel_crtc_update_cursor(crtc, false);
3157
3158         intel_disable_plane(dev_priv, plane, pipe);
3159
3160         if (dev_priv->cfb_plane == plane)
3161                 intel_disable_fbc(dev);
3162
3163         intel_disable_pipe(dev_priv, pipe);
3164
3165         /* Disable PF */
3166         I915_WRITE(PF_CTL(pipe), 0);
3167         I915_WRITE(PF_WIN_SZ(pipe), 0);
3168
3169         ironlake_fdi_disable(crtc);
3170
3171         /* This is a horrible layering violation; we should be doing this in
3172          * the connector/encoder ->prepare instead, but we don't always have
3173          * enough information there about the config to know whether it will
3174          * actually be necessary or just cause undesired flicker.
3175          */
3176         intel_disable_pch_ports(dev_priv, pipe);
3177
3178         intel_disable_transcoder(dev_priv, pipe);
3179
3180         if (HAS_PCH_CPT(dev)) {
3181                 /* disable TRANS_DP_CTL */
3182                 reg = TRANS_DP_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3185                 temp |= TRANS_DP_PORT_SEL_NONE;
3186                 I915_WRITE(reg, temp);
3187
3188                 /* disable DPLL_SEL */
3189                 temp = I915_READ(PCH_DPLL_SEL);
3190                 switch (pipe) {
3191                 case 0:
3192                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3193                         break;
3194                 case 1:
3195                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3196                         break;
3197                 case 2:
3198                         /* C shares PLL A or B */
3199                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3200                         break;
3201                 default:
3202                         BUG(); /* wtf */
3203                 }
3204                 I915_WRITE(PCH_DPLL_SEL, temp);
3205         }
3206
3207         /* disable PCH DPLL */
3208         if (!intel_crtc->no_pll)
3209                 intel_disable_pch_pll(dev_priv, pipe);
3210
3211         /* Switch from PCDclk to Rawclk */
3212         reg = FDI_RX_CTL(pipe);
3213         temp = I915_READ(reg);
3214         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3215
3216         /* Disable CPU FDI TX PLL */
3217         reg = FDI_TX_CTL(pipe);
3218         temp = I915_READ(reg);
3219         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3220
3221         POSTING_READ(reg);
3222         udelay(100);
3223
3224         reg = FDI_RX_CTL(pipe);
3225         temp = I915_READ(reg);
3226         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3227
3228         /* Wait for the clocks to turn off. */
3229         POSTING_READ(reg);
3230         udelay(100);
3231
3232         intel_crtc->active = false;
3233         intel_update_watermarks(dev);
3234
3235         mutex_lock(&dev->struct_mutex);
3236         intel_update_fbc(dev);
3237         intel_clear_scanline_wait(dev);
3238         mutex_unlock(&dev->struct_mutex);
3239 }
3240
3241 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3242 {
3243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244         int pipe = intel_crtc->pipe;
3245         int plane = intel_crtc->plane;
3246
3247         /* XXX: When our outputs are all unaware of DPMS modes other than off
3248          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3249          */
3250         switch (mode) {
3251         case DRM_MODE_DPMS_ON:
3252         case DRM_MODE_DPMS_STANDBY:
3253         case DRM_MODE_DPMS_SUSPEND:
3254                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3255                 ironlake_crtc_enable(crtc);
3256                 break;
3257
3258         case DRM_MODE_DPMS_OFF:
3259                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3260                 ironlake_crtc_disable(crtc);
3261                 break;
3262         }
3263 }
3264
3265 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3266 {
3267         if (!enable && intel_crtc->overlay) {
3268                 struct drm_device *dev = intel_crtc->base.dev;
3269                 struct drm_i915_private *dev_priv = dev->dev_private;
3270
3271                 mutex_lock(&dev->struct_mutex);
3272                 dev_priv->mm.interruptible = false;
3273                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3274                 dev_priv->mm.interruptible = true;
3275                 mutex_unlock(&dev->struct_mutex);
3276         }
3277
3278         /* Let userspace switch the overlay on again. In most cases userspace
3279          * has to recompute where to put it anyway.
3280          */
3281 }
3282
3283 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3284 {
3285         struct drm_device *dev = crtc->dev;
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288         int pipe = intel_crtc->pipe;
3289         int plane = intel_crtc->plane;
3290
3291         if (intel_crtc->active)
3292                 return;
3293
3294         intel_crtc->active = true;
3295         intel_update_watermarks(dev);
3296
3297         intel_enable_pll(dev_priv, pipe);
3298         intel_enable_pipe(dev_priv, pipe, false);
3299         intel_enable_plane(dev_priv, plane, pipe);
3300
3301         intel_crtc_load_lut(crtc);
3302         intel_update_fbc(dev);
3303
3304         /* Give the overlay scaler a chance to enable if it's on this pipe */
3305         intel_crtc_dpms_overlay(intel_crtc, true);
3306         intel_crtc_update_cursor(crtc, true);
3307 }
3308
3309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3310 {
3311         struct drm_device *dev = crtc->dev;
3312         struct drm_i915_private *dev_priv = dev->dev_private;
3313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314         int pipe = intel_crtc->pipe;
3315         int plane = intel_crtc->plane;
3316
3317         if (!intel_crtc->active)
3318                 return;
3319
3320         /* Give the overlay scaler a chance to disable if it's on this pipe */
3321         intel_crtc_wait_for_pending_flips(crtc);
3322         drm_vblank_off(dev, pipe);
3323         intel_crtc_dpms_overlay(intel_crtc, false);
3324         intel_crtc_update_cursor(crtc, false);
3325
3326         if (dev_priv->cfb_plane == plane)
3327                 intel_disable_fbc(dev);
3328
3329         intel_disable_plane(dev_priv, plane, pipe);
3330         intel_disable_pipe(dev_priv, pipe);
3331         intel_disable_pll(dev_priv, pipe);
3332
3333         intel_crtc->active = false;
3334         intel_update_fbc(dev);
3335         intel_update_watermarks(dev);
3336         intel_clear_scanline_wait(dev);
3337 }
3338
3339 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3340 {
3341         /* XXX: When our outputs are all unaware of DPMS modes other than off
3342          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3343          */
3344         switch (mode) {
3345         case DRM_MODE_DPMS_ON:
3346         case DRM_MODE_DPMS_STANDBY:
3347         case DRM_MODE_DPMS_SUSPEND:
3348                 i9xx_crtc_enable(crtc);
3349                 break;
3350         case DRM_MODE_DPMS_OFF:
3351                 i9xx_crtc_disable(crtc);
3352                 break;
3353         }
3354 }
3355
3356 /**
3357  * Sets the power management mode of the pipe and plane.
3358  */
3359 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3360 {
3361         struct drm_device *dev = crtc->dev;
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363         struct drm_i915_master_private *master_priv;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         int pipe = intel_crtc->pipe;
3366         bool enabled;
3367
3368         if (intel_crtc->dpms_mode == mode)
3369                 return;
3370
3371         intel_crtc->dpms_mode = mode;
3372
3373         dev_priv->display.dpms(crtc, mode);
3374
3375         if (!dev->primary->master)
3376                 return;
3377
3378         master_priv = dev->primary->master->driver_priv;
3379         if (!master_priv->sarea_priv)
3380                 return;
3381
3382         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3383
3384         switch (pipe) {
3385         case 0:
3386                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3387                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3388                 break;
3389         case 1:
3390                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3391                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3392                 break;
3393         default:
3394                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3395                 break;
3396         }
3397 }
3398
3399 static void intel_crtc_disable(struct drm_crtc *crtc)
3400 {
3401         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3402         struct drm_device *dev = crtc->dev;
3403
3404         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3405         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3406         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3407
3408         if (crtc->fb) {
3409                 mutex_lock(&dev->struct_mutex);
3410                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3411                 mutex_unlock(&dev->struct_mutex);
3412         }
3413 }
3414
3415 /* Prepare for a mode set.
3416  *
3417  * Note we could be a lot smarter here.  We need to figure out which outputs
3418  * will be enabled, which disabled (in short, how the config will changes)
3419  * and perform the minimum necessary steps to accomplish that, e.g. updating
3420  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3421  * panel fitting is in the proper state, etc.
3422  */
3423 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3424 {
3425         i9xx_crtc_disable(crtc);
3426 }
3427
3428 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3429 {
3430         i9xx_crtc_enable(crtc);
3431 }
3432
3433 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3434 {
3435         ironlake_crtc_disable(crtc);
3436 }
3437
3438 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3439 {
3440         ironlake_crtc_enable(crtc);
3441 }
3442
3443 void intel_encoder_prepare(struct drm_encoder *encoder)
3444 {
3445         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3446         /* lvds has its own version of prepare see intel_lvds_prepare */
3447         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3448 }
3449
3450 void intel_encoder_commit(struct drm_encoder *encoder)
3451 {
3452         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3453         struct drm_device *dev = encoder->dev;
3454         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3455         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3456
3457         /* lvds has its own version of commit see intel_lvds_commit */
3458         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3459
3460         if (HAS_PCH_CPT(dev))
3461                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3462 }
3463
3464 void intel_encoder_destroy(struct drm_encoder *encoder)
3465 {
3466         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3467
3468         drm_encoder_cleanup(encoder);
3469         kfree(intel_encoder);
3470 }
3471
3472 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3473                                   struct drm_display_mode *mode,
3474                                   struct drm_display_mode *adjusted_mode)
3475 {
3476         struct drm_device *dev = crtc->dev;
3477
3478         if (HAS_PCH_SPLIT(dev)) {
3479                 /* FDI link clock is fixed at 2.7G */
3480                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3481                         return false;
3482         }
3483
3484         /* All interlaced capable intel hw wants timings in frames. */
3485         drm_mode_set_crtcinfo(adjusted_mode, 0);
3486
3487         return true;
3488 }
3489
3490 static int i945_get_display_clock_speed(struct drm_device *dev)
3491 {
3492         return 400000;
3493 }
3494
3495 static int i915_get_display_clock_speed(struct drm_device *dev)
3496 {
3497         return 333000;
3498 }
3499
3500 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3501 {
3502         return 200000;
3503 }
3504
3505 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3506 {
3507         u16 gcfgc = 0;
3508
3509         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3510
3511         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3512                 return 133000;
3513         else {
3514                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3515                 case GC_DISPLAY_CLOCK_333_MHZ:
3516                         return 333000;
3517                 default:
3518                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3519                         return 190000;
3520                 }
3521         }
3522 }
3523
3524 static int i865_get_display_clock_speed(struct drm_device *dev)
3525 {
3526         return 266000;
3527 }
3528
3529 static int i855_get_display_clock_speed(struct drm_device *dev)
3530 {
3531         u16 hpllcc = 0;
3532         /* Assume that the hardware is in the high speed state.  This
3533          * should be the default.
3534          */
3535         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3536         case GC_CLOCK_133_200:
3537         case GC_CLOCK_100_200:
3538                 return 200000;
3539         case GC_CLOCK_166_250:
3540                 return 250000;
3541         case GC_CLOCK_100_133:
3542                 return 133000;
3543         }
3544
3545         /* Shouldn't happen */
3546         return 0;
3547 }
3548
3549 static int i830_get_display_clock_speed(struct drm_device *dev)
3550 {
3551         return 133000;
3552 }
3553
3554 struct fdi_m_n {
3555         u32        tu;
3556         u32        gmch_m;
3557         u32        gmch_n;
3558         u32        link_m;
3559         u32        link_n;
3560 };
3561
3562 static void
3563 fdi_reduce_ratio(u32 *num, u32 *den)
3564 {
3565         while (*num > 0xffffff || *den > 0xffffff) {
3566                 *num >>= 1;
3567                 *den >>= 1;
3568         }
3569 }
3570
3571 static void
3572 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3573                      int link_clock, struct fdi_m_n *m_n)
3574 {
3575         m_n->tu = 64; /* default size */
3576
3577         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3578         m_n->gmch_m = bits_per_pixel * pixel_clock;
3579         m_n->gmch_n = link_clock * nlanes * 8;
3580         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3581
3582         m_n->link_m = pixel_clock;
3583         m_n->link_n = link_clock;
3584         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3585 }
3586
3587
3588 struct intel_watermark_params {
3589         unsigned long fifo_size;
3590         unsigned long max_wm;
3591         unsigned long default_wm;
3592         unsigned long guard_size;
3593         unsigned long cacheline_size;
3594 };
3595
3596 /* Pineview has different values for various configs */
3597 static const struct intel_watermark_params pineview_display_wm = {
3598         PINEVIEW_DISPLAY_FIFO,
3599         PINEVIEW_MAX_WM,
3600         PINEVIEW_DFT_WM,
3601         PINEVIEW_GUARD_WM,
3602         PINEVIEW_FIFO_LINE_SIZE
3603 };
3604 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3605         PINEVIEW_DISPLAY_FIFO,
3606         PINEVIEW_MAX_WM,
3607         PINEVIEW_DFT_HPLLOFF_WM,
3608         PINEVIEW_GUARD_WM,
3609         PINEVIEW_FIFO_LINE_SIZE
3610 };
3611 static const struct intel_watermark_params pineview_cursor_wm = {
3612         PINEVIEW_CURSOR_FIFO,
3613         PINEVIEW_CURSOR_MAX_WM,
3614         PINEVIEW_CURSOR_DFT_WM,
3615         PINEVIEW_CURSOR_GUARD_WM,
3616         PINEVIEW_FIFO_LINE_SIZE,
3617 };
3618 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3619         PINEVIEW_CURSOR_FIFO,
3620         PINEVIEW_CURSOR_MAX_WM,
3621         PINEVIEW_CURSOR_DFT_WM,
3622         PINEVIEW_CURSOR_GUARD_WM,
3623         PINEVIEW_FIFO_LINE_SIZE
3624 };
3625 static const struct intel_watermark_params g4x_wm_info = {
3626         G4X_FIFO_SIZE,
3627         G4X_MAX_WM,
3628         G4X_MAX_WM,
3629         2,
3630         G4X_FIFO_LINE_SIZE,
3631 };
3632 static const struct intel_watermark_params g4x_cursor_wm_info = {
3633         I965_CURSOR_FIFO,
3634         I965_CURSOR_MAX_WM,
3635         I965_CURSOR_DFT_WM,
3636         2,
3637         G4X_FIFO_LINE_SIZE,
3638 };
3639 static const struct intel_watermark_params valleyview_wm_info = {
3640         VALLEYVIEW_FIFO_SIZE,
3641         VALLEYVIEW_MAX_WM,
3642         VALLEYVIEW_MAX_WM,
3643         2,
3644         G4X_FIFO_LINE_SIZE,
3645 };
3646 static const struct intel_watermark_params valleyview_cursor_wm_info = {
3647         I965_CURSOR_FIFO,
3648         VALLEYVIEW_CURSOR_MAX_WM,
3649         I965_CURSOR_DFT_WM,
3650         2,
3651         G4X_FIFO_LINE_SIZE,
3652 };
3653 static const struct intel_watermark_params i965_cursor_wm_info = {
3654         I965_CURSOR_FIFO,
3655         I965_CURSOR_MAX_WM,
3656         I965_CURSOR_DFT_WM,
3657         2,
3658         I915_FIFO_LINE_SIZE,
3659 };
3660 static const struct intel_watermark_params i945_wm_info = {
3661         I945_FIFO_SIZE,
3662         I915_MAX_WM,
3663         1,
3664         2,
3665         I915_FIFO_LINE_SIZE
3666 };
3667 static const struct intel_watermark_params i915_wm_info = {
3668         I915_FIFO_SIZE,
3669         I915_MAX_WM,
3670         1,
3671         2,
3672         I915_FIFO_LINE_SIZE
3673 };
3674 static const struct intel_watermark_params i855_wm_info = {
3675         I855GM_FIFO_SIZE,
3676         I915_MAX_WM,
3677         1,
3678         2,
3679         I830_FIFO_LINE_SIZE
3680 };
3681 static const struct intel_watermark_params i830_wm_info = {
3682         I830_FIFO_SIZE,
3683         I915_MAX_WM,
3684         1,
3685         2,
3686         I830_FIFO_LINE_SIZE
3687 };
3688
3689 static const struct intel_watermark_params ironlake_display_wm_info = {
3690         ILK_DISPLAY_FIFO,
3691         ILK_DISPLAY_MAXWM,
3692         ILK_DISPLAY_DFTWM,
3693         2,
3694         ILK_FIFO_LINE_SIZE
3695 };
3696 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3697         ILK_CURSOR_FIFO,
3698         ILK_CURSOR_MAXWM,
3699         ILK_CURSOR_DFTWM,
3700         2,
3701         ILK_FIFO_LINE_SIZE
3702 };
3703 static const struct intel_watermark_params ironlake_display_srwm_info = {
3704         ILK_DISPLAY_SR_FIFO,
3705         ILK_DISPLAY_MAX_SRWM,
3706         ILK_DISPLAY_DFT_SRWM,
3707         2,
3708         ILK_FIFO_LINE_SIZE
3709 };
3710 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3711         ILK_CURSOR_SR_FIFO,
3712         ILK_CURSOR_MAX_SRWM,
3713         ILK_CURSOR_DFT_SRWM,
3714         2,
3715         ILK_FIFO_LINE_SIZE
3716 };
3717
3718 static const struct intel_watermark_params sandybridge_display_wm_info = {
3719         SNB_DISPLAY_FIFO,
3720         SNB_DISPLAY_MAXWM,
3721         SNB_DISPLAY_DFTWM,
3722         2,
3723         SNB_FIFO_LINE_SIZE
3724 };
3725 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3726         SNB_CURSOR_FIFO,
3727         SNB_CURSOR_MAXWM,
3728         SNB_CURSOR_DFTWM,
3729         2,
3730         SNB_FIFO_LINE_SIZE
3731 };
3732 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3733         SNB_DISPLAY_SR_FIFO,
3734         SNB_DISPLAY_MAX_SRWM,
3735         SNB_DISPLAY_DFT_SRWM,
3736         2,
3737         SNB_FIFO_LINE_SIZE
3738 };
3739 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3740         SNB_CURSOR_SR_FIFO,
3741         SNB_CURSOR_MAX_SRWM,
3742         SNB_CURSOR_DFT_SRWM,
3743         2,
3744         SNB_FIFO_LINE_SIZE
3745 };
3746
3747
3748 /**
3749  * intel_calculate_wm - calculate watermark level
3750  * @clock_in_khz: pixel clock
3751  * @wm: chip FIFO params
3752  * @pixel_size: display pixel size
3753  * @latency_ns: memory latency for the platform
3754  *
3755  * Calculate the watermark level (the level at which the display plane will
3756  * start fetching from memory again).  Each chip has a different display
3757  * FIFO size and allocation, so the caller needs to figure that out and pass
3758  * in the correct intel_watermark_params structure.
3759  *
3760  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3761  * on the pixel size.  When it reaches the watermark level, it'll start
3762  * fetching FIFO line sized based chunks from memory until the FIFO fills
3763  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3764  * will occur, and a display engine hang could result.
3765  */
3766 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3767                                         const struct intel_watermark_params *wm,
3768                                         int fifo_size,
3769                                         int pixel_size,
3770                                         unsigned long latency_ns)
3771 {
3772         long entries_required, wm_size;
3773
3774         /*
3775          * Note: we need to make sure we don't overflow for various clock &
3776          * latency values.
3777          * clocks go from a few thousand to several hundred thousand.
3778          * latency is usually a few thousand
3779          */
3780         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3781                 1000;
3782         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3783
3784         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3785
3786         wm_size = fifo_size - (entries_required + wm->guard_size);
3787
3788         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3789
3790         /* Don't promote wm_size to unsigned... */
3791         if (wm_size > (long)wm->max_wm)
3792                 wm_size = wm->max_wm;
3793         if (wm_size <= 0)
3794                 wm_size = wm->default_wm;
3795         return wm_size;
3796 }
3797
3798 struct cxsr_latency {
3799         int is_desktop;
3800         int is_ddr3;
3801         unsigned long fsb_freq;
3802         unsigned long mem_freq;
3803         unsigned long display_sr;
3804         unsigned long display_hpll_disable;
3805         unsigned long cursor_sr;
3806         unsigned long cursor_hpll_disable;
3807 };
3808
3809 static const struct cxsr_latency cxsr_latency_table[] = {
3810         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3811         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3812         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3813         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3814         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3815
3816         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3817         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3818         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3819         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3820         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3821
3822         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3823         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3824         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3825         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3826         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3827
3828         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3829         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3830         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3831         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3832         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3833
3834         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3835         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3836         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3837         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3838         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3839
3840         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3841         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3842         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3843         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3844         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3845 };
3846
3847 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3848                                                          int is_ddr3,
3849                                                          int fsb,
3850                                                          int mem)
3851 {
3852         const struct cxsr_latency *latency;
3853         int i;
3854
3855         if (fsb == 0 || mem == 0)
3856                 return NULL;
3857
3858         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3859                 latency = &cxsr_latency_table[i];
3860                 if (is_desktop == latency->is_desktop &&
3861                     is_ddr3 == latency->is_ddr3 &&
3862                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3863                         return latency;
3864         }
3865
3866         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3867
3868         return NULL;
3869 }
3870
3871 static void pineview_disable_cxsr(struct drm_device *dev)
3872 {
3873         struct drm_i915_private *dev_priv = dev->dev_private;
3874
3875         /* deactivate cxsr */
3876         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3877 }
3878
3879 /*
3880  * Latency for FIFO fetches is dependent on several factors:
3881  *   - memory configuration (speed, channels)
3882  *   - chipset
3883  *   - current MCH state
3884  * It can be fairly high in some situations, so here we assume a fairly
3885  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3886  * set this value too high, the FIFO will fetch frequently to stay full)
3887  * and power consumption (set it too low to save power and we might see
3888  * FIFO underruns and display "flicker").
3889  *
3890  * A value of 5us seems to be a good balance; safe for very low end
3891  * platforms but not overly aggressive on lower latency configs.
3892  */
3893 static const int latency_ns = 5000;
3894
3895 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3896 {
3897         struct drm_i915_private *dev_priv = dev->dev_private;
3898         uint32_t dsparb = I915_READ(DSPARB);
3899         int size;
3900
3901         size = dsparb & 0x7f;
3902         if (plane)
3903                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3904
3905         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3906                       plane ? "B" : "A", size);
3907
3908         return size;
3909 }
3910
3911 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3912 {
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         uint32_t dsparb = I915_READ(DSPARB);
3915         int size;
3916
3917         size = dsparb & 0x1ff;
3918         if (plane)
3919                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3920         size >>= 1; /* Convert to cachelines */
3921
3922         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3923                       plane ? "B" : "A", size);
3924
3925         return size;
3926 }
3927
3928 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3929 {
3930         struct drm_i915_private *dev_priv = dev->dev_private;
3931         uint32_t dsparb = I915_READ(DSPARB);
3932         int size;
3933
3934         size = dsparb & 0x7f;
3935         size >>= 2; /* Convert to cachelines */
3936
3937         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3938                       plane ? "B" : "A",
3939                       size);
3940
3941         return size;
3942 }
3943
3944 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3945 {
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         uint32_t dsparb = I915_READ(DSPARB);
3948         int size;
3949
3950         size = dsparb & 0x7f;
3951         size >>= 1; /* Convert to cachelines */
3952
3953         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3954                       plane ? "B" : "A", size);
3955
3956         return size;
3957 }
3958
3959 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3960 {
3961         struct drm_crtc *crtc, *enabled = NULL;
3962
3963         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3964                 if (crtc->enabled && crtc->fb) {
3965                         if (enabled)
3966                                 return NULL;
3967                         enabled = crtc;
3968                 }
3969         }
3970
3971         return enabled;
3972 }
3973
3974 static void pineview_update_wm(struct drm_device *dev)
3975 {
3976         struct drm_i915_private *dev_priv = dev->dev_private;
3977         struct drm_crtc *crtc;
3978         const struct cxsr_latency *latency;
3979         u32 reg;
3980         unsigned long wm;
3981
3982         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3983                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3984         if (!latency) {
3985                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3986                 pineview_disable_cxsr(dev);
3987                 return;
3988         }
3989
3990         crtc = single_enabled_crtc(dev);
3991         if (crtc) {
3992                 int clock = crtc->mode.clock;
3993                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3994
3995                 /* Display SR */
3996                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3997                                         pineview_display_wm.fifo_size,
3998                                         pixel_size, latency->display_sr);
3999                 reg = I915_READ(DSPFW1);
4000                 reg &= ~DSPFW_SR_MASK;
4001                 reg |= wm << DSPFW_SR_SHIFT;
4002                 I915_WRITE(DSPFW1, reg);
4003                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4004
4005                 /* cursor SR */
4006                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4007                                         pineview_display_wm.fifo_size,
4008                                         pixel_size, latency->cursor_sr);
4009                 reg = I915_READ(DSPFW3);
4010                 reg &= ~DSPFW_CURSOR_SR_MASK;
4011                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4012                 I915_WRITE(DSPFW3, reg);
4013
4014                 /* Display HPLL off SR */
4015                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4016                                         pineview_display_hplloff_wm.fifo_size,
4017                                         pixel_size, latency->display_hpll_disable);
4018                 reg = I915_READ(DSPFW3);
4019                 reg &= ~DSPFW_HPLL_SR_MASK;
4020                 reg |= wm & DSPFW_HPLL_SR_MASK;
4021                 I915_WRITE(DSPFW3, reg);
4022
4023                 /* cursor HPLL off SR */
4024                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4025                                         pineview_display_hplloff_wm.fifo_size,
4026                                         pixel_size, latency->cursor_hpll_disable);
4027                 reg = I915_READ(DSPFW3);
4028                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4029                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4030                 I915_WRITE(DSPFW3, reg);
4031                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4032
4033                 /* activate cxsr */
4034                 I915_WRITE(DSPFW3,
4035                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4036                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4037         } else {
4038                 pineview_disable_cxsr(dev);
4039                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4040         }
4041 }
4042
4043 static bool g4x_compute_wm0(struct drm_device *dev,
4044                             int plane,
4045                             const struct intel_watermark_params *display,
4046                             int display_latency_ns,
4047                             const struct intel_watermark_params *cursor,
4048                             int cursor_latency_ns,
4049                             int *plane_wm,
4050                             int *cursor_wm)
4051 {
4052         struct drm_crtc *crtc;
4053         int htotal, hdisplay, clock, pixel_size;
4054         int line_time_us, line_count;
4055         int entries, tlb_miss;
4056
4057         crtc = intel_get_crtc_for_plane(dev, plane);
4058         if (crtc->fb == NULL || !crtc->enabled) {
4059                 *cursor_wm = cursor->guard_size;
4060                 *plane_wm = display->guard_size;
4061                 return false;
4062         }
4063
4064         htotal = crtc->mode.htotal;
4065         hdisplay = crtc->mode.hdisplay;
4066         clock = crtc->mode.clock;
4067         pixel_size = crtc->fb->bits_per_pixel / 8;
4068
4069         /* Use the small buffer method to calculate plane watermark */
4070         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4071         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4072         if (tlb_miss > 0)
4073                 entries += tlb_miss;
4074         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4075         *plane_wm = entries + display->guard_size;
4076         if (*plane_wm > (int)display->max_wm)
4077                 *plane_wm = display->max_wm;
4078
4079         /* Use the large buffer method to calculate cursor watermark */
4080         line_time_us = ((htotal * 1000) / clock);
4081         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4082         entries = line_count * 64 * pixel_size;
4083         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4084         if (tlb_miss > 0)
4085                 entries += tlb_miss;
4086         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4087         *cursor_wm = entries + cursor->guard_size;
4088         if (*cursor_wm > (int)cursor->max_wm)
4089                 *cursor_wm = (int)cursor->max_wm;
4090
4091         return true;
4092 }
4093
4094 /*
4095  * Check the wm result.
4096  *
4097  * If any calculated watermark values is larger than the maximum value that
4098  * can be programmed into the associated watermark register, that watermark
4099  * must be disabled.
4100  */
4101 static bool g4x_check_srwm(struct drm_device *dev,
4102                            int display_wm, int cursor_wm,
4103                            const struct intel_watermark_params *display,
4104                            const struct intel_watermark_params *cursor)
4105 {
4106         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4107                       display_wm, cursor_wm);
4108
4109         if (display_wm > display->max_wm) {
4110                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4111                               display_wm, display->max_wm);
4112                 return false;
4113         }
4114
4115         if (cursor_wm > cursor->max_wm) {
4116                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4117                               cursor_wm, cursor->max_wm);
4118                 return false;
4119         }
4120
4121         if (!(display_wm || cursor_wm)) {
4122                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4123                 return false;
4124         }
4125
4126         return true;
4127 }
4128
4129 static bool g4x_compute_srwm(struct drm_device *dev,
4130                              int plane,
4131                              int latency_ns,
4132                              const struct intel_watermark_params *display,
4133                              const struct intel_watermark_params *cursor,
4134                              int *display_wm, int *cursor_wm)
4135 {
4136         struct drm_crtc *crtc;
4137         int hdisplay, htotal, pixel_size, clock;
4138         unsigned long line_time_us;
4139         int line_count, line_size;
4140         int small, large;
4141         int entries;
4142
4143         if (!latency_ns) {
4144                 *display_wm = *cursor_wm = 0;
4145                 return false;
4146         }
4147
4148         crtc = intel_get_crtc_for_plane(dev, plane);
4149         hdisplay = crtc->mode.hdisplay;
4150         htotal = crtc->mode.htotal;
4151         clock = crtc->mode.clock;
4152         pixel_size = crtc->fb->bits_per_pixel / 8;
4153
4154         line_time_us = (htotal * 1000) / clock;
4155         line_count = (latency_ns / line_time_us + 1000) / 1000;
4156         line_size = hdisplay * pixel_size;
4157
4158         /* Use the minimum of the small and large buffer method for primary */
4159         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4160         large = line_count * line_size;
4161
4162         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4163         *display_wm = entries + display->guard_size;
4164
4165         /* calculate the self-refresh watermark for display cursor */
4166         entries = line_count * pixel_size * 64;
4167         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4168         *cursor_wm = entries + cursor->guard_size;
4169
4170         return g4x_check_srwm(dev,
4171                               *display_wm, *cursor_wm,
4172                               display, cursor);
4173 }
4174
4175 #define single_plane_enabled(mask) is_power_of_2(mask)
4176
4177 static void valleyview_update_wm(struct drm_device *dev)
4178 {
4179         static const int sr_latency_ns = 12000;
4180         struct drm_i915_private *dev_priv = dev->dev_private;
4181         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4182         int plane_sr, cursor_sr;
4183         unsigned int enabled = 0;
4184
4185         if (g4x_compute_wm0(dev, 0,
4186                             &valleyview_wm_info, latency_ns,
4187                             &valleyview_cursor_wm_info, latency_ns,
4188                             &planea_wm, &cursora_wm))
4189                 enabled |= 1;
4190
4191         if (g4x_compute_wm0(dev, 1,
4192                             &valleyview_wm_info, latency_ns,
4193                             &valleyview_cursor_wm_info, latency_ns,
4194                             &planeb_wm, &cursorb_wm))
4195                 enabled |= 2;
4196
4197         plane_sr = cursor_sr = 0;
4198         if (single_plane_enabled(enabled) &&
4199             g4x_compute_srwm(dev, ffs(enabled) - 1,
4200                              sr_latency_ns,
4201                              &valleyview_wm_info,
4202                              &valleyview_cursor_wm_info,
4203                              &plane_sr, &cursor_sr))
4204                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
4205         else
4206                 I915_WRITE(FW_BLC_SELF_VLV,
4207                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
4208
4209         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4210                       planea_wm, cursora_wm,
4211                       planeb_wm, cursorb_wm,
4212                       plane_sr, cursor_sr);
4213
4214         I915_WRITE(DSPFW1,
4215                    (plane_sr << DSPFW_SR_SHIFT) |
4216                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4217                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4218                    planea_wm);
4219         I915_WRITE(DSPFW2,
4220                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4221                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4222         I915_WRITE(DSPFW3,
4223                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
4224 }
4225
4226 static void g4x_update_wm(struct drm_device *dev)
4227 {
4228         static const int sr_latency_ns = 12000;
4229         struct drm_i915_private *dev_priv = dev->dev_private;
4230         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4231         int plane_sr, cursor_sr;
4232         unsigned int enabled = 0;
4233
4234         if (g4x_compute_wm0(dev, 0,
4235                             &g4x_wm_info, latency_ns,
4236                             &g4x_cursor_wm_info, latency_ns,
4237                             &planea_wm, &cursora_wm))
4238                 enabled |= 1;
4239
4240         if (g4x_compute_wm0(dev, 1,
4241                             &g4x_wm_info, latency_ns,
4242                             &g4x_cursor_wm_info, latency_ns,
4243                             &planeb_wm, &cursorb_wm))
4244                 enabled |= 2;
4245
4246         plane_sr = cursor_sr = 0;
4247         if (single_plane_enabled(enabled) &&
4248             g4x_compute_srwm(dev, ffs(enabled) - 1,
4249                              sr_latency_ns,
4250                              &g4x_wm_info,
4251                              &g4x_cursor_wm_info,
4252                              &plane_sr, &cursor_sr))
4253                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4254         else
4255                 I915_WRITE(FW_BLC_SELF,
4256                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4257
4258         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4259                       planea_wm, cursora_wm,
4260                       planeb_wm, cursorb_wm,
4261                       plane_sr, cursor_sr);
4262
4263         I915_WRITE(DSPFW1,
4264                    (plane_sr << DSPFW_SR_SHIFT) |
4265                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4266                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4267                    planea_wm);
4268         I915_WRITE(DSPFW2,
4269                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4270                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4271         /* HPLL off in SR has some issues on G4x... disable it */
4272         I915_WRITE(DSPFW3,
4273                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4274                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4275 }
4276
4277 static void i965_update_wm(struct drm_device *dev)
4278 {
4279         struct drm_i915_private *dev_priv = dev->dev_private;
4280         struct drm_crtc *crtc;
4281         int srwm = 1;
4282         int cursor_sr = 16;
4283
4284         /* Calc sr entries for one plane configs */
4285         crtc = single_enabled_crtc(dev);
4286         if (crtc) {
4287                 /* self-refresh has much higher latency */
4288                 static const int sr_latency_ns = 12000;
4289                 int clock = crtc->mode.clock;
4290                 int htotal = crtc->mode.htotal;
4291                 int hdisplay = crtc->mode.hdisplay;
4292                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4293                 unsigned long line_time_us;
4294                 int entries;
4295
4296                 line_time_us = ((htotal * 1000) / clock);
4297
4298                 /* Use ns/us then divide to preserve precision */
4299                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4300                         pixel_size * hdisplay;
4301                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4302                 srwm = I965_FIFO_SIZE - entries;
4303                 if (srwm < 0)
4304                         srwm = 1;
4305                 srwm &= 0x1ff;
4306                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4307                               entries, srwm);
4308
4309                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4310                         pixel_size * 64;
4311                 entries = DIV_ROUND_UP(entries,
4312                                           i965_cursor_wm_info.cacheline_size);
4313                 cursor_sr = i965_cursor_wm_info.fifo_size -
4314                         (entries + i965_cursor_wm_info.guard_size);
4315
4316                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4317                         cursor_sr = i965_cursor_wm_info.max_wm;
4318
4319                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4320                               "cursor %d\n", srwm, cursor_sr);
4321
4322                 if (IS_CRESTLINE(dev))
4323                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4324         } else {
4325                 /* Turn off self refresh if both pipes are enabled */
4326                 if (IS_CRESTLINE(dev))
4327                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4328                                    & ~FW_BLC_SELF_EN);
4329         }
4330
4331         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4332                       srwm);
4333
4334         /* 965 has limitations... */
4335         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4336                    (8 << 16) | (8 << 8) | (8 << 0));
4337         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4338         /* update cursor SR watermark */
4339         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4340 }
4341
4342 static void i9xx_update_wm(struct drm_device *dev)
4343 {
4344         struct drm_i915_private *dev_priv = dev->dev_private;
4345         const struct intel_watermark_params *wm_info;
4346         uint32_t fwater_lo;
4347         uint32_t fwater_hi;
4348         int cwm, srwm = 1;
4349         int fifo_size;
4350         int planea_wm, planeb_wm;
4351         struct drm_crtc *crtc, *enabled = NULL;
4352
4353         if (IS_I945GM(dev))
4354                 wm_info = &i945_wm_info;
4355         else if (!IS_GEN2(dev))
4356                 wm_info = &i915_wm_info;
4357         else
4358                 wm_info = &i855_wm_info;
4359
4360         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4361         crtc = intel_get_crtc_for_plane(dev, 0);
4362         if (crtc->enabled && crtc->fb) {
4363                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4364                                                wm_info, fifo_size,
4365                                                crtc->fb->bits_per_pixel / 8,
4366                                                latency_ns);
4367                 enabled = crtc;
4368         } else
4369                 planea_wm = fifo_size - wm_info->guard_size;
4370
4371         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4372         crtc = intel_get_crtc_for_plane(dev, 1);
4373         if (crtc->enabled && crtc->fb) {
4374                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4375                                                wm_info, fifo_size,
4376                                                crtc->fb->bits_per_pixel / 8,
4377                                                latency_ns);
4378                 if (enabled == NULL)
4379                         enabled = crtc;
4380                 else
4381                         enabled = NULL;
4382         } else
4383                 planeb_wm = fifo_size - wm_info->guard_size;
4384
4385         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4386
4387         /*
4388          * Overlay gets an aggressive default since video jitter is bad.
4389          */
4390         cwm = 2;
4391
4392         /* Play safe and disable self-refresh before adjusting watermarks. */
4393         if (IS_I945G(dev) || IS_I945GM(dev))
4394                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4395         else if (IS_I915GM(dev))
4396                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4397
4398         /* Calc sr entries for one plane configs */
4399         if (HAS_FW_BLC(dev) && enabled) {
4400                 /* self-refresh has much higher latency */
4401                 static const int sr_latency_ns = 6000;
4402                 int clock = enabled->mode.clock;
4403                 int htotal = enabled->mode.htotal;
4404                 int hdisplay = enabled->mode.hdisplay;
4405                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4406                 unsigned long line_time_us;
4407                 int entries;
4408
4409                 line_time_us = (htotal * 1000) / clock;
4410
4411                 /* Use ns/us then divide to preserve precision */
4412                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4413                         pixel_size * hdisplay;
4414                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4415                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4416                 srwm = wm_info->fifo_size - entries;
4417                 if (srwm < 0)
4418                         srwm = 1;
4419
4420                 if (IS_I945G(dev) || IS_I945GM(dev))
4421                         I915_WRITE(FW_BLC_SELF,
4422                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4423                 else if (IS_I915GM(dev))
4424                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4425         }
4426
4427         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4428                       planea_wm, planeb_wm, cwm, srwm);
4429
4430         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4431         fwater_hi = (cwm & 0x1f);
4432
4433         /* Set request length to 8 cachelines per fetch */
4434         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4435         fwater_hi = fwater_hi | (1 << 8);
4436
4437         I915_WRITE(FW_BLC, fwater_lo);
4438         I915_WRITE(FW_BLC2, fwater_hi);
4439
4440         if (HAS_FW_BLC(dev)) {
4441                 if (enabled) {
4442                         if (IS_I945G(dev) || IS_I945GM(dev))
4443                                 I915_WRITE(FW_BLC_SELF,
4444                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4445                         else if (IS_I915GM(dev))
4446                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4447                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4448                 } else
4449                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4450         }
4451 }
4452
4453 static void i830_update_wm(struct drm_device *dev)
4454 {
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456         struct drm_crtc *crtc;
4457         uint32_t fwater_lo;
4458         int planea_wm;
4459
4460         crtc = single_enabled_crtc(dev);
4461         if (crtc == NULL)
4462                 return;
4463
4464         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4465                                        dev_priv->display.get_fifo_size(dev, 0),
4466                                        crtc->fb->bits_per_pixel / 8,
4467                                        latency_ns);
4468         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4469         fwater_lo |= (3<<8) | planea_wm;
4470
4471         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4472
4473         I915_WRITE(FW_BLC, fwater_lo);
4474 }
4475
4476 #define ILK_LP0_PLANE_LATENCY           700
4477 #define ILK_LP0_CURSOR_LATENCY          1300
4478
4479 /*
4480  * Check the wm result.
4481  *
4482  * If any calculated watermark values is larger than the maximum value that
4483  * can be programmed into the associated watermark register, that watermark
4484  * must be disabled.
4485  */
4486 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4487                                 int fbc_wm, int display_wm, int cursor_wm,
4488                                 const struct intel_watermark_params *display,
4489                                 const struct intel_watermark_params *cursor)
4490 {
4491         struct drm_i915_private *dev_priv = dev->dev_private;
4492
4493         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4494                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4495
4496         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4497                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4498                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4499
4500                 /* fbc has it's own way to disable FBC WM */
4501                 I915_WRITE(DISP_ARB_CTL,
4502                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4503                 return false;
4504         }
4505
4506         if (display_wm > display->max_wm) {
4507                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4508                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4509                 return false;
4510         }
4511
4512         if (cursor_wm > cursor->max_wm) {
4513                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4514                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4515                 return false;
4516         }
4517
4518         if (!(fbc_wm || display_wm || cursor_wm)) {
4519                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4520                 return false;
4521         }
4522
4523         return true;
4524 }
4525
4526 /*
4527  * Compute watermark values of WM[1-3],
4528  */
4529 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4530                                   int latency_ns,
4531                                   const struct intel_watermark_params *display,
4532                                   const struct intel_watermark_params *cursor,
4533                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4534 {
4535         struct drm_crtc *crtc;
4536         unsigned long line_time_us;
4537         int hdisplay, htotal, pixel_size, clock;
4538         int line_count, line_size;
4539         int small, large;
4540         int entries;
4541
4542         if (!latency_ns) {
4543                 *fbc_wm = *display_wm = *cursor_wm = 0;
4544                 return false;
4545         }
4546
4547         crtc = intel_get_crtc_for_plane(dev, plane);
4548         hdisplay = crtc->mode.hdisplay;
4549         htotal = crtc->mode.htotal;
4550         clock = crtc->mode.clock;
4551         pixel_size = crtc->fb->bits_per_pixel / 8;
4552
4553         line_time_us = (htotal * 1000) / clock;
4554         line_count = (latency_ns / line_time_us + 1000) / 1000;
4555         line_size = hdisplay * pixel_size;
4556
4557         /* Use the minimum of the small and large buffer method for primary */
4558         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4559         large = line_count * line_size;
4560
4561         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4562         *display_wm = entries + display->guard_size;
4563
4564         /*
4565          * Spec says:
4566          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4567          */
4568         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4569
4570         /* calculate the self-refresh watermark for display cursor */
4571         entries = line_count * pixel_size * 64;
4572         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4573         *cursor_wm = entries + cursor->guard_size;
4574
4575         return ironlake_check_srwm(dev, level,
4576                                    *fbc_wm, *display_wm, *cursor_wm,
4577                                    display, cursor);
4578 }
4579
4580 static void ironlake_update_wm(struct drm_device *dev)
4581 {
4582         struct drm_i915_private *dev_priv = dev->dev_private;
4583         int fbc_wm, plane_wm, cursor_wm;
4584         unsigned int enabled;
4585
4586         enabled = 0;
4587         if (g4x_compute_wm0(dev, 0,
4588                             &ironlake_display_wm_info,
4589                             ILK_LP0_PLANE_LATENCY,
4590                             &ironlake_cursor_wm_info,
4591                             ILK_LP0_CURSOR_LATENCY,
4592                             &plane_wm, &cursor_wm)) {
4593                 I915_WRITE(WM0_PIPEA_ILK,
4594                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4595                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4596                               " plane %d, " "cursor: %d\n",
4597                               plane_wm, cursor_wm);
4598                 enabled |= 1;
4599         }
4600
4601         if (g4x_compute_wm0(dev, 1,
4602                             &ironlake_display_wm_info,
4603                             ILK_LP0_PLANE_LATENCY,
4604                             &ironlake_cursor_wm_info,
4605                             ILK_LP0_CURSOR_LATENCY,
4606                             &plane_wm, &cursor_wm)) {
4607                 I915_WRITE(WM0_PIPEB_ILK,
4608                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4609                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4610                               " plane %d, cursor: %d\n",
4611                               plane_wm, cursor_wm);
4612                 enabled |= 2;
4613         }
4614
4615         /*
4616          * Calculate and update the self-refresh watermark only when one
4617          * display plane is used.
4618          */
4619         I915_WRITE(WM3_LP_ILK, 0);
4620         I915_WRITE(WM2_LP_ILK, 0);
4621         I915_WRITE(WM1_LP_ILK, 0);
4622
4623         if (!single_plane_enabled(enabled))
4624                 return;
4625         enabled = ffs(enabled) - 1;
4626
4627         /* WM1 */
4628         if (!ironlake_compute_srwm(dev, 1, enabled,
4629                                    ILK_READ_WM1_LATENCY() * 500,
4630                                    &ironlake_display_srwm_info,
4631                                    &ironlake_cursor_srwm_info,
4632                                    &fbc_wm, &plane_wm, &cursor_wm))
4633                 return;
4634
4635         I915_WRITE(WM1_LP_ILK,
4636                    WM1_LP_SR_EN |
4637                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4638                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4639                    (plane_wm << WM1_LP_SR_SHIFT) |
4640                    cursor_wm);
4641
4642         /* WM2 */
4643         if (!ironlake_compute_srwm(dev, 2, enabled,
4644                                    ILK_READ_WM2_LATENCY() * 500,
4645                                    &ironlake_display_srwm_info,
4646                                    &ironlake_cursor_srwm_info,
4647                                    &fbc_wm, &plane_wm, &cursor_wm))
4648                 return;
4649
4650         I915_WRITE(WM2_LP_ILK,
4651                    WM2_LP_EN |
4652                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4653                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4654                    (plane_wm << WM1_LP_SR_SHIFT) |
4655                    cursor_wm);
4656
4657         /*
4658          * WM3 is unsupported on ILK, probably because we don't have latency
4659          * data for that power state
4660          */
4661 }
4662
4663 void sandybridge_update_wm(struct drm_device *dev)
4664 {
4665         struct drm_i915_private *dev_priv = dev->dev_private;
4666         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4667         u32 val;
4668         int fbc_wm, plane_wm, cursor_wm;
4669         unsigned int enabled;
4670
4671         enabled = 0;
4672         if (g4x_compute_wm0(dev, 0,
4673                             &sandybridge_display_wm_info, latency,
4674                             &sandybridge_cursor_wm_info, latency,
4675                             &plane_wm, &cursor_wm)) {
4676                 val = I915_READ(WM0_PIPEA_ILK);
4677                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4678                 I915_WRITE(WM0_PIPEA_ILK, val |
4679                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4680                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4681                               " plane %d, " "cursor: %d\n",
4682                               plane_wm, cursor_wm);
4683                 enabled |= 1;
4684         }
4685
4686         if (g4x_compute_wm0(dev, 1,
4687                             &sandybridge_display_wm_info, latency,
4688                             &sandybridge_cursor_wm_info, latency,
4689                             &plane_wm, &cursor_wm)) {
4690                 val = I915_READ(WM0_PIPEB_ILK);
4691                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4692                 I915_WRITE(WM0_PIPEB_ILK, val |
4693                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4694                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4695                               " plane %d, cursor: %d\n",
4696                               plane_wm, cursor_wm);
4697                 enabled |= 2;
4698         }
4699
4700         /* IVB has 3 pipes */
4701         if (IS_IVYBRIDGE(dev) &&
4702             g4x_compute_wm0(dev, 2,
4703                             &sandybridge_display_wm_info, latency,
4704                             &sandybridge_cursor_wm_info, latency,
4705                             &plane_wm, &cursor_wm)) {
4706                 val = I915_READ(WM0_PIPEC_IVB);
4707                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4708                 I915_WRITE(WM0_PIPEC_IVB, val |
4709                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4710                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4711                               " plane %d, cursor: %d\n",
4712                               plane_wm, cursor_wm);
4713                 enabled |= 3;
4714         }
4715
4716         /*
4717          * Calculate and update the self-refresh watermark only when one
4718          * display plane is used.
4719          *
4720          * SNB support 3 levels of watermark.
4721          *
4722          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4723          * and disabled in the descending order
4724          *
4725          */
4726         I915_WRITE(WM3_LP_ILK, 0);
4727         I915_WRITE(WM2_LP_ILK, 0);
4728         I915_WRITE(WM1_LP_ILK, 0);
4729
4730         if (!single_plane_enabled(enabled) ||
4731             dev_priv->sprite_scaling_enabled)
4732                 return;
4733         enabled = ffs(enabled) - 1;
4734
4735         /* WM1 */
4736         if (!ironlake_compute_srwm(dev, 1, enabled,
4737                                    SNB_READ_WM1_LATENCY() * 500,
4738                                    &sandybridge_display_srwm_info,
4739                                    &sandybridge_cursor_srwm_info,
4740                                    &fbc_wm, &plane_wm, &cursor_wm))
4741                 return;
4742
4743         I915_WRITE(WM1_LP_ILK,
4744                    WM1_LP_SR_EN |
4745                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4746                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4747                    (plane_wm << WM1_LP_SR_SHIFT) |
4748                    cursor_wm);
4749
4750         /* WM2 */
4751         if (!ironlake_compute_srwm(dev, 2, enabled,
4752                                    SNB_READ_WM2_LATENCY() * 500,
4753                                    &sandybridge_display_srwm_info,
4754                                    &sandybridge_cursor_srwm_info,
4755                                    &fbc_wm, &plane_wm, &cursor_wm))
4756                 return;
4757
4758         I915_WRITE(WM2_LP_ILK,
4759                    WM2_LP_EN |
4760                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4761                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4762                    (plane_wm << WM1_LP_SR_SHIFT) |
4763                    cursor_wm);
4764
4765         /* WM3 */
4766         if (!ironlake_compute_srwm(dev, 3, enabled,
4767                                    SNB_READ_WM3_LATENCY() * 500,
4768                                    &sandybridge_display_srwm_info,
4769                                    &sandybridge_cursor_srwm_info,
4770                                    &fbc_wm, &plane_wm, &cursor_wm))
4771                 return;
4772
4773         I915_WRITE(WM3_LP_ILK,
4774                    WM3_LP_EN |
4775                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4776                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4777                    (plane_wm << WM1_LP_SR_SHIFT) |
4778                    cursor_wm);
4779 }
4780
4781 static bool
4782 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4783                               uint32_t sprite_width, int pixel_size,
4784                               const struct intel_watermark_params *display,
4785                               int display_latency_ns, int *sprite_wm)
4786 {
4787         struct drm_crtc *crtc;
4788         int clock;
4789         int entries, tlb_miss;
4790
4791         crtc = intel_get_crtc_for_plane(dev, plane);
4792         if (crtc->fb == NULL || !crtc->enabled) {
4793                 *sprite_wm = display->guard_size;
4794                 return false;
4795         }
4796
4797         clock = crtc->mode.clock;
4798
4799         /* Use the small buffer method to calculate the sprite watermark */
4800         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4801         tlb_miss = display->fifo_size*display->cacheline_size -
4802                 sprite_width * 8;
4803         if (tlb_miss > 0)
4804                 entries += tlb_miss;
4805         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4806         *sprite_wm = entries + display->guard_size;
4807         if (*sprite_wm > (int)display->max_wm)
4808                 *sprite_wm = display->max_wm;
4809
4810         return true;
4811 }
4812
4813 static bool
4814 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4815                                 uint32_t sprite_width, int pixel_size,
4816                                 const struct intel_watermark_params *display,
4817                                 int latency_ns, int *sprite_wm)
4818 {
4819         struct drm_crtc *crtc;
4820         unsigned long line_time_us;
4821         int clock;
4822         int line_count, line_size;
4823         int small, large;
4824         int entries;
4825
4826         if (!latency_ns) {
4827                 *sprite_wm = 0;
4828                 return false;
4829         }
4830
4831         crtc = intel_get_crtc_for_plane(dev, plane);
4832         clock = crtc->mode.clock;
4833
4834         line_time_us = (sprite_width * 1000) / clock;
4835         line_count = (latency_ns / line_time_us + 1000) / 1000;
4836         line_size = sprite_width * pixel_size;
4837
4838         /* Use the minimum of the small and large buffer method for primary */
4839         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4840         large = line_count * line_size;
4841
4842         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4843         *sprite_wm = entries + display->guard_size;
4844
4845         return *sprite_wm > 0x3ff ? false : true;
4846 }
4847
4848 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4849                                          uint32_t sprite_width, int pixel_size)
4850 {
4851         struct drm_i915_private *dev_priv = dev->dev_private;
4852         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4853         u32 val;
4854         int sprite_wm, reg;
4855         int ret;
4856
4857         switch (pipe) {
4858         case 0:
4859                 reg = WM0_PIPEA_ILK;
4860                 break;
4861         case 1:
4862                 reg = WM0_PIPEB_ILK;
4863                 break;
4864         case 2:
4865                 reg = WM0_PIPEC_IVB;
4866                 break;
4867         default:
4868                 return; /* bad pipe */
4869         }
4870
4871         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4872                                             &sandybridge_display_wm_info,
4873                                             latency, &sprite_wm);
4874         if (!ret) {
4875                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4876                               pipe);
4877                 return;
4878         }
4879
4880         val = I915_READ(reg);
4881         val &= ~WM0_PIPE_SPRITE_MASK;
4882         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4883         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4884
4885
4886         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4887                                               pixel_size,
4888                                               &sandybridge_display_srwm_info,
4889                                               SNB_READ_WM1_LATENCY() * 500,
4890                                               &sprite_wm);
4891         if (!ret) {
4892                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4893                               pipe);
4894                 return;
4895         }
4896         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4897
4898         /* Only IVB has two more LP watermarks for sprite */
4899         if (!IS_IVYBRIDGE(dev))
4900                 return;
4901
4902         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4903                                               pixel_size,
4904                                               &sandybridge_display_srwm_info,
4905                                               SNB_READ_WM2_LATENCY() * 500,
4906                                               &sprite_wm);
4907         if (!ret) {
4908                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4909                               pipe);
4910                 return;
4911         }
4912         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4913
4914         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4915                                               pixel_size,
4916                                               &sandybridge_display_srwm_info,
4917                                               SNB_READ_WM3_LATENCY() * 500,
4918                                               &sprite_wm);
4919         if (!ret) {
4920                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4921                               pipe);
4922                 return;
4923         }
4924         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4925 }
4926
4927 /**
4928  * intel_update_watermarks - update FIFO watermark values based on current modes
4929  *
4930  * Calculate watermark values for the various WM regs based on current mode
4931  * and plane configuration.
4932  *
4933  * There are several cases to deal with here:
4934  *   - normal (i.e. non-self-refresh)
4935  *   - self-refresh (SR) mode
4936  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4937  *   - lines are small relative to FIFO size (buffer can hold more than 2
4938  *     lines), so need to account for TLB latency
4939  *
4940  *   The normal calculation is:
4941  *     watermark = dotclock * bytes per pixel * latency
4942  *   where latency is platform & configuration dependent (we assume pessimal
4943  *   values here).
4944  *
4945  *   The SR calculation is:
4946  *     watermark = (trunc(latency/line time)+1) * surface width *
4947  *       bytes per pixel
4948  *   where
4949  *     line time = htotal / dotclock
4950  *     surface width = hdisplay for normal plane and 64 for cursor
4951  *   and latency is assumed to be high, as above.
4952  *
4953  * The final value programmed to the register should always be rounded up,
4954  * and include an extra 2 entries to account for clock crossings.
4955  *
4956  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4957  * to set the non-SR watermarks to 8.
4958  */
4959 static void intel_update_watermarks(struct drm_device *dev)
4960 {
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962
4963         if (dev_priv->display.update_wm)
4964                 dev_priv->display.update_wm(dev);
4965 }
4966
4967 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4968                                     uint32_t sprite_width, int pixel_size)
4969 {
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971
4972         if (dev_priv->display.update_sprite_wm)
4973                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4974                                                    pixel_size);
4975 }
4976
4977 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4978 {
4979         if (i915_panel_use_ssc >= 0)
4980                 return i915_panel_use_ssc != 0;
4981         return dev_priv->lvds_use_ssc
4982                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4983 }
4984
4985 /**
4986  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4987  * @crtc: CRTC structure
4988  * @mode: requested mode
4989  *
4990  * A pipe may be connected to one or more outputs.  Based on the depth of the
4991  * attached framebuffer, choose a good color depth to use on the pipe.
4992  *
4993  * If possible, match the pipe depth to the fb depth.  In some cases, this
4994  * isn't ideal, because the connected output supports a lesser or restricted
4995  * set of depths.  Resolve that here:
4996  *    LVDS typically supports only 6bpc, so clamp down in that case
4997  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4998  *    Displays may support a restricted set as well, check EDID and clamp as
4999  *      appropriate.
5000  *    DP may want to dither down to 6bpc to fit larger modes
5001  *
5002  * RETURNS:
5003  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
5004  * true if they don't match).
5005  */
5006 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
5007                                          unsigned int *pipe_bpp,
5008                                          struct drm_display_mode *mode)
5009 {
5010         struct drm_device *dev = crtc->dev;
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         struct drm_encoder *encoder;
5013         struct drm_connector *connector;
5014         unsigned int display_bpc = UINT_MAX, bpc;
5015
5016         /* Walk the encoders & connectors on this crtc, get min bpc */
5017         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5018                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5019
5020                 if (encoder->crtc != crtc)
5021                         continue;
5022
5023                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5024                         unsigned int lvds_bpc;
5025
5026                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5027                             LVDS_A3_POWER_UP)
5028                                 lvds_bpc = 8;
5029                         else
5030                                 lvds_bpc = 6;
5031
5032                         if (lvds_bpc < display_bpc) {
5033                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5034                                 display_bpc = lvds_bpc;
5035                         }
5036                         continue;
5037                 }
5038
5039                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5040                         /* Use VBT settings if we have an eDP panel */
5041                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5042
5043                         if (edp_bpc < display_bpc) {
5044                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5045                                 display_bpc = edp_bpc;
5046                         }
5047                         continue;
5048                 }
5049
5050                 /* Not one of the known troublemakers, check the EDID */
5051                 list_for_each_entry(connector, &dev->mode_config.connector_list,
5052                                     head) {
5053                         if (connector->encoder != encoder)
5054                                 continue;
5055
5056                         /* Don't use an invalid EDID bpc value */
5057                         if (connector->display_info.bpc &&
5058                             connector->display_info.bpc < display_bpc) {
5059                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5060                                 display_bpc = connector->display_info.bpc;
5061                         }
5062                 }
5063
5064                 /*
5065                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5066                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5067                  */
5068                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5069                         if (display_bpc > 8 && display_bpc < 12) {
5070                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5071                                 display_bpc = 12;
5072                         } else {
5073                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5074                                 display_bpc = 8;
5075                         }
5076                 }
5077         }
5078
5079         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5080                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5081                 display_bpc = 6;
5082         }
5083
5084         /*
5085          * We could just drive the pipe at the highest bpc all the time and
5086          * enable dithering as needed, but that costs bandwidth.  So choose
5087          * the minimum value that expresses the full color range of the fb but
5088          * also stays within the max display bpc discovered above.
5089          */
5090
5091         switch (crtc->fb->depth) {
5092         case 8:
5093                 bpc = 8; /* since we go through a colormap */
5094                 break;
5095         case 15:
5096         case 16:
5097                 bpc = 6; /* min is 18bpp */
5098                 break;
5099         case 24:
5100                 bpc = 8;
5101                 break;
5102         case 30:
5103                 bpc = 10;
5104                 break;
5105         case 48:
5106                 bpc = 12;
5107                 break;
5108         default:
5109                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5110                 bpc = min((unsigned int)8, display_bpc);
5111                 break;
5112         }
5113
5114         display_bpc = min(display_bpc, bpc);
5115
5116         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5117                       bpc, display_bpc);
5118
5119         *pipe_bpp = display_bpc * 3;
5120
5121         return display_bpc != bpc;
5122 }
5123
5124 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5125 {
5126         struct drm_device *dev = crtc->dev;
5127         struct drm_i915_private *dev_priv = dev->dev_private;
5128         int refclk;
5129
5130         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5131             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5132                 refclk = dev_priv->lvds_ssc_freq * 1000;
5133                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5134                               refclk / 1000);
5135         } else if (!IS_GEN2(dev)) {
5136                 refclk = 96000;
5137         } else {
5138                 refclk = 48000;
5139         }
5140
5141         return refclk;
5142 }
5143
5144 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5145                                       intel_clock_t *clock)
5146 {
5147         /* SDVO TV has fixed PLL values depend on its clock range,
5148            this mirrors vbios setting. */
5149         if (adjusted_mode->clock >= 100000
5150             && adjusted_mode->clock < 140500) {
5151                 clock->p1 = 2;
5152                 clock->p2 = 10;
5153                 clock->n = 3;
5154                 clock->m1 = 16;
5155                 clock->m2 = 8;
5156         } else if (adjusted_mode->clock >= 140500
5157                    && adjusted_mode->clock <= 200000) {
5158                 clock->p1 = 1;
5159                 clock->p2 = 10;
5160                 clock->n = 6;
5161                 clock->m1 = 12;
5162                 clock->m2 = 8;
5163         }
5164 }
5165
5166 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5167                                      intel_clock_t *clock,
5168                                      intel_clock_t *reduced_clock)
5169 {
5170         struct drm_device *dev = crtc->dev;
5171         struct drm_i915_private *dev_priv = dev->dev_private;
5172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173         int pipe = intel_crtc->pipe;
5174         u32 fp, fp2 = 0;
5175
5176         if (IS_PINEVIEW(dev)) {
5177                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5178                 if (reduced_clock)
5179                         fp2 = (1 << reduced_clock->n) << 16 |
5180                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5181         } else {
5182                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5183                 if (reduced_clock)
5184                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5185                                 reduced_clock->m2;
5186         }
5187
5188         I915_WRITE(FP0(pipe), fp);
5189
5190         intel_crtc->lowfreq_avail = false;
5191         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5192             reduced_clock && i915_powersave) {
5193                 I915_WRITE(FP1(pipe), fp2);
5194                 intel_crtc->lowfreq_avail = true;
5195         } else {
5196                 I915_WRITE(FP1(pipe), fp);
5197         }
5198 }
5199
5200 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5201                               struct drm_display_mode *adjusted_mode)
5202 {
5203         struct drm_device *dev = crtc->dev;
5204         struct drm_i915_private *dev_priv = dev->dev_private;
5205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206         int pipe = intel_crtc->pipe;
5207         u32 temp, lvds_sync = 0;
5208
5209         temp = I915_READ(LVDS);
5210         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5211         if (pipe == 1) {
5212                 temp |= LVDS_PIPEB_SELECT;
5213         } else {
5214                 temp &= ~LVDS_PIPEB_SELECT;
5215         }
5216         /* set the corresponsding LVDS_BORDER bit */
5217         temp |= dev_priv->lvds_border_bits;
5218         /* Set the B0-B3 data pairs corresponding to whether we're going to
5219          * set the DPLLs for dual-channel mode or not.
5220          */
5221         if (clock->p2 == 7)
5222                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5223         else
5224                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5225
5226         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5227          * appropriately here, but we need to look more thoroughly into how
5228          * panels behave in the two modes.
5229          */
5230         /* set the dithering flag on LVDS as needed */
5231         if (INTEL_INFO(dev)->gen >= 4) {
5232                 if (dev_priv->lvds_dither)
5233                         temp |= LVDS_ENABLE_DITHER;
5234                 else
5235                         temp &= ~LVDS_ENABLE_DITHER;
5236         }
5237         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5238                 lvds_sync |= LVDS_HSYNC_POLARITY;
5239         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5240                 lvds_sync |= LVDS_VSYNC_POLARITY;
5241         if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5242             != lvds_sync) {
5243                 char flags[2] = "-+";
5244                 DRM_INFO("Changing LVDS panel from "
5245                          "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5246                          flags[!(temp & LVDS_HSYNC_POLARITY)],
5247                          flags[!(temp & LVDS_VSYNC_POLARITY)],
5248                          flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5249                          flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5250                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5251                 temp |= lvds_sync;
5252         }
5253         I915_WRITE(LVDS, temp);
5254 }
5255
5256 static void i9xx_update_pll(struct drm_crtc *crtc,
5257                             struct drm_display_mode *mode,
5258                             struct drm_display_mode *adjusted_mode,
5259                             intel_clock_t *clock, intel_clock_t *reduced_clock,
5260                             int num_connectors)
5261 {
5262         struct drm_device *dev = crtc->dev;
5263         struct drm_i915_private *dev_priv = dev->dev_private;
5264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5265         int pipe = intel_crtc->pipe;
5266         u32 dpll;
5267         bool is_sdvo;
5268
5269         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5270                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5271
5272         dpll = DPLL_VGA_MODE_DIS;
5273
5274         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5275                 dpll |= DPLLB_MODE_LVDS;
5276         else
5277                 dpll |= DPLLB_MODE_DAC_SERIAL;
5278         if (is_sdvo) {
5279                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5280                 if (pixel_multiplier > 1) {
5281                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5282                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5283                 }
5284                 dpll |= DPLL_DVO_HIGH_SPEED;
5285         }
5286         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5287                 dpll |= DPLL_DVO_HIGH_SPEED;
5288
5289         /* compute bitmask from p1 value */
5290         if (IS_PINEVIEW(dev))
5291                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5292         else {
5293                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5294                 if (IS_G4X(dev) && reduced_clock)
5295                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5296         }
5297         switch (clock->p2) {
5298         case 5:
5299                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5300                 break;
5301         case 7:
5302                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5303                 break;
5304         case 10:
5305                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5306                 break;
5307         case 14:
5308                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5309                 break;
5310         }
5311         if (INTEL_INFO(dev)->gen >= 4)
5312                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5313
5314         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5315                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5316         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5317                 /* XXX: just matching BIOS for now */
5318                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5319                 dpll |= 3;
5320         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5321                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5322                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5323         else
5324                 dpll |= PLL_REF_INPUT_DREFCLK;
5325
5326         dpll |= DPLL_VCO_ENABLE;
5327         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5328         POSTING_READ(DPLL(pipe));
5329         udelay(150);
5330
5331         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5332          * This is an exception to the general rule that mode_set doesn't turn
5333          * things on.
5334          */
5335         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5336                 intel_update_lvds(crtc, clock, adjusted_mode);
5337
5338         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5339                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5340
5341         I915_WRITE(DPLL(pipe), dpll);
5342
5343         /* Wait for the clocks to stabilize. */
5344         POSTING_READ(DPLL(pipe));
5345         udelay(150);
5346
5347         if (INTEL_INFO(dev)->gen >= 4) {
5348                 u32 temp = 0;
5349                 if (is_sdvo) {
5350                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5351                         if (temp > 1)
5352                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5353                         else
5354                                 temp = 0;
5355                 }
5356                 I915_WRITE(DPLL_MD(pipe), temp);
5357         } else {
5358                 /* The pixel multiplier can only be updated once the
5359                  * DPLL is enabled and the clocks are stable.
5360                  *
5361                  * So write it again.
5362                  */
5363                 I915_WRITE(DPLL(pipe), dpll);
5364         }
5365 }
5366
5367 static void i8xx_update_pll(struct drm_crtc *crtc,
5368                             struct drm_display_mode *adjusted_mode,
5369                             intel_clock_t *clock,
5370                             int num_connectors)
5371 {
5372         struct drm_device *dev = crtc->dev;
5373         struct drm_i915_private *dev_priv = dev->dev_private;
5374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375         int pipe = intel_crtc->pipe;
5376         u32 dpll;
5377
5378         dpll = DPLL_VGA_MODE_DIS;
5379
5380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
5381                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5382         } else {
5383                 if (clock->p1 == 2)
5384                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5385                 else
5386                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5387                 if (clock->p2 == 4)
5388                         dpll |= PLL_P2_DIVIDE_BY_4;
5389         }
5390
5391         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5392                 /* XXX: just matching BIOS for now */
5393                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5394                 dpll |= 3;
5395         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5396                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5397                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5398         else
5399                 dpll |= PLL_REF_INPUT_DREFCLK;
5400
5401         dpll |= DPLL_VCO_ENABLE;
5402         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5403         POSTING_READ(DPLL(pipe));
5404         udelay(150);
5405
5406         I915_WRITE(DPLL(pipe), dpll);
5407
5408         /* Wait for the clocks to stabilize. */
5409         POSTING_READ(DPLL(pipe));
5410         udelay(150);
5411
5412         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5413          * This is an exception to the general rule that mode_set doesn't turn
5414          * things on.
5415          */
5416         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5417                 intel_update_lvds(crtc, clock, adjusted_mode);
5418
5419         /* The pixel multiplier can only be updated once the
5420          * DPLL is enabled and the clocks are stable.
5421          *
5422          * So write it again.
5423          */
5424         I915_WRITE(DPLL(pipe), dpll);
5425 }
5426
5427 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5428                               struct drm_display_mode *mode,
5429                               struct drm_display_mode *adjusted_mode,
5430                               int x, int y,
5431                               struct drm_framebuffer *old_fb)
5432 {
5433         struct drm_device *dev = crtc->dev;
5434         struct drm_i915_private *dev_priv = dev->dev_private;
5435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5436         int pipe = intel_crtc->pipe;
5437         int plane = intel_crtc->plane;
5438         int refclk, num_connectors = 0;
5439         intel_clock_t clock, reduced_clock;
5440         u32 dspcntr, pipeconf, vsyncshift;
5441         bool ok, has_reduced_clock = false, is_sdvo = false;
5442         bool is_lvds = false, is_tv = false, is_dp = false;
5443         struct drm_mode_config *mode_config = &dev->mode_config;
5444         struct intel_encoder *encoder;
5445         const intel_limit_t *limit;
5446         int ret;
5447
5448         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5449                 if (encoder->base.crtc != crtc)
5450                         continue;
5451
5452                 switch (encoder->type) {
5453                 case INTEL_OUTPUT_LVDS:
5454                         is_lvds = true;
5455                         break;
5456                 case INTEL_OUTPUT_SDVO:
5457                 case INTEL_OUTPUT_HDMI:
5458                         is_sdvo = true;
5459                         if (encoder->needs_tv_clock)
5460                                 is_tv = true;
5461                         break;
5462                 case INTEL_OUTPUT_TVOUT:
5463                         is_tv = true;
5464                         break;
5465                 case INTEL_OUTPUT_DISPLAYPORT:
5466                         is_dp = true;
5467                         break;
5468                 }
5469
5470                 num_connectors++;
5471         }
5472
5473         refclk = i9xx_get_refclk(crtc, num_connectors);
5474
5475         /*
5476          * Returns a set of divisors for the desired target clock with the given
5477          * refclk, or FALSE.  The returned values represent the clock equation:
5478          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5479          */
5480         limit = intel_limit(crtc, refclk);
5481         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5482                              &clock);
5483         if (!ok) {
5484                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5485                 return -EINVAL;
5486         }
5487
5488         /* Ensure that the cursor is valid for the new mode before changing... */
5489         intel_crtc_update_cursor(crtc, true);
5490
5491         if (is_lvds && dev_priv->lvds_downclock_avail) {
5492                 /*
5493                  * Ensure we match the reduced clock's P to the target clock.
5494                  * If the clocks don't match, we can't switch the display clock
5495                  * by using the FP0/FP1. In such case we will disable the LVDS
5496                  * downclock feature.
5497                 */
5498                 has_reduced_clock = limit->find_pll(limit, crtc,
5499                                                     dev_priv->lvds_downclock,
5500                                                     refclk,
5501                                                     &clock,
5502                                                     &reduced_clock);
5503         }
5504
5505         if (is_sdvo && is_tv)
5506                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5507
5508         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5509                                  &reduced_clock : NULL);
5510
5511         if (IS_GEN2(dev))
5512                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
5513         else
5514                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
5515                                 has_reduced_clock ? &reduced_clock : NULL,
5516                                 num_connectors);
5517
5518         /* setup pipeconf */
5519         pipeconf = I915_READ(PIPECONF(pipe));
5520
5521         /* Set up the display plane register */
5522         dspcntr = DISPPLANE_GAMMA_ENABLE;
5523
5524         if (pipe == 0)
5525                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5526         else
5527                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5528
5529         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5530                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5531                  * core speed.
5532                  *
5533                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5534                  * pipe == 0 check?
5535                  */
5536                 if (mode->clock >
5537                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5538                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5539                 else
5540                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5541         }
5542
5543         /* default to 8bpc */
5544         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5545         if (is_dp) {
5546                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5547                         pipeconf |= PIPECONF_BPP_6 |
5548                                     PIPECONF_DITHER_EN |
5549                                     PIPECONF_DITHER_TYPE_SP;
5550                 }
5551         }
5552
5553         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5554         drm_mode_debug_printmodeline(mode);
5555
5556         if (HAS_PIPE_CXSR(dev)) {
5557                 if (intel_crtc->lowfreq_avail) {
5558                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5559                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5560                 } else {
5561                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5562                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5563                 }
5564         }
5565
5566         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5567         if (!IS_GEN2(dev) &&
5568             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5569                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5570                 /* the chip adds 2 halflines automatically */
5571                 adjusted_mode->crtc_vtotal -= 1;
5572                 adjusted_mode->crtc_vblank_end -= 1;
5573                 vsyncshift = adjusted_mode->crtc_hsync_start
5574                              - adjusted_mode->crtc_htotal/2;
5575         } else {
5576                 pipeconf |= PIPECONF_PROGRESSIVE;
5577                 vsyncshift = 0;
5578         }
5579
5580         if (!IS_GEN3(dev))
5581                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5582
5583         I915_WRITE(HTOTAL(pipe),
5584                    (adjusted_mode->crtc_hdisplay - 1) |
5585                    ((adjusted_mode->crtc_htotal - 1) << 16));
5586         I915_WRITE(HBLANK(pipe),
5587                    (adjusted_mode->crtc_hblank_start - 1) |
5588                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5589         I915_WRITE(HSYNC(pipe),
5590                    (adjusted_mode->crtc_hsync_start - 1) |
5591                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5592
5593         I915_WRITE(VTOTAL(pipe),
5594                    (adjusted_mode->crtc_vdisplay - 1) |
5595                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5596         I915_WRITE(VBLANK(pipe),
5597                    (adjusted_mode->crtc_vblank_start - 1) |
5598                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5599         I915_WRITE(VSYNC(pipe),
5600                    (adjusted_mode->crtc_vsync_start - 1) |
5601                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5602
5603         /* pipesrc and dspsize control the size that is scaled from,
5604          * which should always be the user's requested size.
5605          */
5606         I915_WRITE(DSPSIZE(plane),
5607                    ((mode->vdisplay - 1) << 16) |
5608                    (mode->hdisplay - 1));
5609         I915_WRITE(DSPPOS(plane), 0);
5610         I915_WRITE(PIPESRC(pipe),
5611                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5612
5613         I915_WRITE(PIPECONF(pipe), pipeconf);
5614         POSTING_READ(PIPECONF(pipe));
5615         intel_enable_pipe(dev_priv, pipe, false);
5616
5617         intel_wait_for_vblank(dev, pipe);
5618
5619         I915_WRITE(DSPCNTR(plane), dspcntr);
5620         POSTING_READ(DSPCNTR(plane));
5621         intel_enable_plane(dev_priv, plane, pipe);
5622
5623         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5624
5625         intel_update_watermarks(dev);
5626
5627         return ret;
5628 }
5629
5630 /*
5631  * Initialize reference clocks when the driver loads
5632  */
5633 void ironlake_init_pch_refclk(struct drm_device *dev)
5634 {
5635         struct drm_i915_private *dev_priv = dev->dev_private;
5636         struct drm_mode_config *mode_config = &dev->mode_config;
5637         struct intel_encoder *encoder;
5638         u32 temp;
5639         bool has_lvds = false;
5640         bool has_cpu_edp = false;
5641         bool has_pch_edp = false;
5642         bool has_panel = false;
5643         bool has_ck505 = false;
5644         bool can_ssc = false;
5645
5646         /* We need to take the global config into account */
5647         list_for_each_entry(encoder, &mode_config->encoder_list,
5648                             base.head) {
5649                 switch (encoder->type) {
5650                 case INTEL_OUTPUT_LVDS:
5651                         has_panel = true;
5652                         has_lvds = true;
5653                         break;
5654                 case INTEL_OUTPUT_EDP:
5655                         has_panel = true;
5656                         if (intel_encoder_is_pch_edp(&encoder->base))
5657                                 has_pch_edp = true;
5658                         else
5659                                 has_cpu_edp = true;
5660                         break;
5661                 }
5662         }
5663
5664         if (HAS_PCH_IBX(dev)) {
5665                 has_ck505 = dev_priv->display_clock_mode;
5666                 can_ssc = has_ck505;
5667         } else {
5668                 has_ck505 = false;
5669                 can_ssc = true;
5670         }
5671
5672         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5673                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5674                       has_ck505);
5675
5676         /* Ironlake: try to setup display ref clock before DPLL
5677          * enabling. This is only under driver's control after
5678          * PCH B stepping, previous chipset stepping should be
5679          * ignoring this setting.
5680          */
5681         temp = I915_READ(PCH_DREF_CONTROL);
5682         /* Always enable nonspread source */
5683         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5684
5685         if (has_ck505)
5686                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5687         else
5688                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5689
5690         if (has_panel) {
5691                 temp &= ~DREF_SSC_SOURCE_MASK;
5692                 temp |= DREF_SSC_SOURCE_ENABLE;
5693
5694                 /* SSC must be turned on before enabling the CPU output  */
5695                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5696                         DRM_DEBUG_KMS("Using SSC on panel\n");
5697                         temp |= DREF_SSC1_ENABLE;
5698                 }
5699
5700                 /* Get SSC going before enabling the outputs */
5701                 I915_WRITE(PCH_DREF_CONTROL, temp);
5702                 POSTING_READ(PCH_DREF_CONTROL);
5703                 udelay(200);
5704
5705                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5706
5707                 /* Enable CPU source on CPU attached eDP */
5708                 if (has_cpu_edp) {
5709                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5710                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5711                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5712                         }
5713                         else
5714                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5715                 } else
5716                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5717
5718                 I915_WRITE(PCH_DREF_CONTROL, temp);
5719                 POSTING_READ(PCH_DREF_CONTROL);
5720                 udelay(200);
5721         } else {
5722                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5723
5724                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5725
5726                 /* Turn off CPU output */
5727                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5728
5729                 I915_WRITE(PCH_DREF_CONTROL, temp);
5730                 POSTING_READ(PCH_DREF_CONTROL);
5731                 udelay(200);
5732
5733                 /* Turn off the SSC source */
5734                 temp &= ~DREF_SSC_SOURCE_MASK;
5735                 temp |= DREF_SSC_SOURCE_DISABLE;
5736
5737                 /* Turn off SSC1 */
5738                 temp &= ~ DREF_SSC1_ENABLE;
5739
5740                 I915_WRITE(PCH_DREF_CONTROL, temp);
5741                 POSTING_READ(PCH_DREF_CONTROL);
5742                 udelay(200);
5743         }
5744 }
5745
5746 static int ironlake_get_refclk(struct drm_crtc *crtc)
5747 {
5748         struct drm_device *dev = crtc->dev;
5749         struct drm_i915_private *dev_priv = dev->dev_private;
5750         struct intel_encoder *encoder;
5751         struct drm_mode_config *mode_config = &dev->mode_config;
5752         struct intel_encoder *edp_encoder = NULL;
5753         int num_connectors = 0;
5754         bool is_lvds = false;
5755
5756         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5757                 if (encoder->base.crtc != crtc)
5758                         continue;
5759
5760                 switch (encoder->type) {
5761                 case INTEL_OUTPUT_LVDS:
5762                         is_lvds = true;
5763                         break;
5764                 case INTEL_OUTPUT_EDP:
5765                         edp_encoder = encoder;
5766                         break;
5767                 }
5768                 num_connectors++;
5769         }
5770
5771         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5772                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5773                               dev_priv->lvds_ssc_freq);
5774                 return dev_priv->lvds_ssc_freq * 1000;
5775         }
5776
5777         return 120000;
5778 }
5779
5780 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5781                                   struct drm_display_mode *mode,
5782                                   struct drm_display_mode *adjusted_mode,
5783                                   int x, int y,
5784                                   struct drm_framebuffer *old_fb)
5785 {
5786         struct drm_device *dev = crtc->dev;
5787         struct drm_i915_private *dev_priv = dev->dev_private;
5788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5789         int pipe = intel_crtc->pipe;
5790         int plane = intel_crtc->plane;
5791         int refclk, num_connectors = 0;
5792         intel_clock_t clock, reduced_clock;
5793         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5794         bool ok, has_reduced_clock = false, is_sdvo = false;
5795         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5796         struct intel_encoder *has_edp_encoder = NULL;
5797         struct drm_mode_config *mode_config = &dev->mode_config;
5798         struct intel_encoder *encoder;
5799         const intel_limit_t *limit;
5800         int ret;
5801         struct fdi_m_n m_n = {0};
5802         u32 temp;
5803         u32 lvds_sync = 0;
5804         int target_clock, pixel_multiplier, lane, link_bw, factor;
5805         unsigned int pipe_bpp;
5806         bool dither;
5807
5808         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5809                 if (encoder->base.crtc != crtc)
5810                         continue;
5811
5812                 switch (encoder->type) {
5813                 case INTEL_OUTPUT_LVDS:
5814                         is_lvds = true;
5815                         break;
5816                 case INTEL_OUTPUT_SDVO:
5817                 case INTEL_OUTPUT_HDMI:
5818                         is_sdvo = true;
5819                         if (encoder->needs_tv_clock)
5820                                 is_tv = true;
5821                         break;
5822                 case INTEL_OUTPUT_TVOUT:
5823                         is_tv = true;
5824                         break;
5825                 case INTEL_OUTPUT_ANALOG:
5826                         is_crt = true;
5827                         break;
5828                 case INTEL_OUTPUT_DISPLAYPORT:
5829                         is_dp = true;
5830                         break;
5831                 case INTEL_OUTPUT_EDP:
5832                         has_edp_encoder = encoder;
5833                         break;
5834                 }
5835
5836                 num_connectors++;
5837         }
5838
5839         refclk = ironlake_get_refclk(crtc);
5840
5841         /*
5842          * Returns a set of divisors for the desired target clock with the given
5843          * refclk, or FALSE.  The returned values represent the clock equation:
5844          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5845          */
5846         limit = intel_limit(crtc, refclk);
5847         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5848                              &clock);
5849         if (!ok) {
5850                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5851                 return -EINVAL;
5852         }
5853
5854         /* Ensure that the cursor is valid for the new mode before changing... */
5855         intel_crtc_update_cursor(crtc, true);
5856
5857         if (is_lvds && dev_priv->lvds_downclock_avail) {
5858                 /*
5859                  * Ensure we match the reduced clock's P to the target clock.
5860                  * If the clocks don't match, we can't switch the display clock
5861                  * by using the FP0/FP1. In such case we will disable the LVDS
5862                  * downclock feature.
5863                 */
5864                 has_reduced_clock = limit->find_pll(limit, crtc,
5865                                                     dev_priv->lvds_downclock,
5866                                                     refclk,
5867                                                     &clock,
5868                                                     &reduced_clock);
5869         }
5870         /* SDVO TV has fixed PLL values depend on its clock range,
5871            this mirrors vbios setting. */
5872         if (is_sdvo && is_tv) {
5873                 if (adjusted_mode->clock >= 100000
5874                     && adjusted_mode->clock < 140500) {
5875                         clock.p1 = 2;
5876                         clock.p2 = 10;
5877                         clock.n = 3;
5878                         clock.m1 = 16;
5879                         clock.m2 = 8;
5880                 } else if (adjusted_mode->clock >= 140500
5881                            && adjusted_mode->clock <= 200000) {
5882                         clock.p1 = 1;
5883                         clock.p2 = 10;
5884                         clock.n = 6;
5885                         clock.m1 = 12;
5886                         clock.m2 = 8;
5887                 }
5888         }
5889
5890         /* FDI link */
5891         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5892         lane = 0;
5893         /* CPU eDP doesn't require FDI link, so just set DP M/N
5894            according to current link config */
5895         if (has_edp_encoder &&
5896             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5897                 target_clock = mode->clock;
5898                 intel_edp_link_config(has_edp_encoder,
5899                                       &lane, &link_bw);
5900         } else {
5901                 /* [e]DP over FDI requires target mode clock
5902                    instead of link clock */
5903                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5904                         target_clock = mode->clock;
5905                 else
5906                         target_clock = adjusted_mode->clock;
5907
5908                 /* FDI is a binary signal running at ~2.7GHz, encoding
5909                  * each output octet as 10 bits. The actual frequency
5910                  * is stored as a divider into a 100MHz clock, and the
5911                  * mode pixel clock is stored in units of 1KHz.
5912                  * Hence the bw of each lane in terms of the mode signal
5913                  * is:
5914                  */
5915                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5916         }
5917
5918         /* determine panel color depth */
5919         temp = I915_READ(PIPECONF(pipe));
5920         temp &= ~PIPE_BPC_MASK;
5921         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5922         switch (pipe_bpp) {
5923         case 18:
5924                 temp |= PIPE_6BPC;
5925                 break;
5926         case 24:
5927                 temp |= PIPE_8BPC;
5928                 break;
5929         case 30:
5930                 temp |= PIPE_10BPC;
5931                 break;
5932         case 36:
5933                 temp |= PIPE_12BPC;
5934                 break;
5935         default:
5936                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5937                         pipe_bpp);
5938                 temp |= PIPE_8BPC;
5939                 pipe_bpp = 24;
5940                 break;
5941         }
5942
5943         intel_crtc->bpp = pipe_bpp;
5944         I915_WRITE(PIPECONF(pipe), temp);
5945
5946         if (!lane) {
5947                 /*
5948                  * Account for spread spectrum to avoid
5949                  * oversubscribing the link. Max center spread
5950                  * is 2.5%; use 5% for safety's sake.
5951                  */
5952                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5953                 lane = bps / (link_bw * 8) + 1;
5954         }
5955
5956         intel_crtc->fdi_lanes = lane;
5957
5958         if (pixel_multiplier > 1)
5959                 link_bw *= pixel_multiplier;
5960         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5961                              &m_n);
5962
5963         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5964         if (has_reduced_clock)
5965                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5966                         reduced_clock.m2;
5967
5968         /* Enable autotuning of the PLL clock (if permissible) */
5969         factor = 21;
5970         if (is_lvds) {
5971                 if ((intel_panel_use_ssc(dev_priv) &&
5972                      dev_priv->lvds_ssc_freq == 100) ||
5973                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5974                         factor = 25;
5975         } else if (is_sdvo && is_tv)
5976                 factor = 20;
5977
5978         if (clock.m < factor * clock.n)
5979                 fp |= FP_CB_TUNE;
5980
5981         dpll = 0;
5982
5983         if (is_lvds)
5984                 dpll |= DPLLB_MODE_LVDS;
5985         else
5986                 dpll |= DPLLB_MODE_DAC_SERIAL;
5987         if (is_sdvo) {
5988                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5989                 if (pixel_multiplier > 1) {
5990                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5991                 }
5992                 dpll |= DPLL_DVO_HIGH_SPEED;
5993         }
5994         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5995                 dpll |= DPLL_DVO_HIGH_SPEED;
5996
5997         /* compute bitmask from p1 value */
5998         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5999         /* also FPA1 */
6000         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6001
6002         switch (clock.p2) {
6003         case 5:
6004                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6005                 break;
6006         case 7:
6007                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6008                 break;
6009         case 10:
6010                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6011                 break;
6012         case 14:
6013                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6014                 break;
6015         }
6016
6017         if (is_sdvo && is_tv)
6018                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6019         else if (is_tv)
6020                 /* XXX: just matching BIOS for now */
6021                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
6022                 dpll |= 3;
6023         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6024                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6025         else
6026                 dpll |= PLL_REF_INPUT_DREFCLK;
6027
6028         /* setup pipeconf */
6029         pipeconf = I915_READ(PIPECONF(pipe));
6030
6031         /* Set up the display plane register */
6032         dspcntr = DISPPLANE_GAMMA_ENABLE;
6033
6034         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
6035         drm_mode_debug_printmodeline(mode);
6036
6037         /* PCH eDP needs FDI, but CPU eDP does not */
6038         if (!intel_crtc->no_pll) {
6039                 if (!has_edp_encoder ||
6040                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6041                         I915_WRITE(PCH_FP0(pipe), fp);
6042                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
6043
6044                         POSTING_READ(PCH_DPLL(pipe));
6045                         udelay(150);
6046                 }
6047         } else {
6048                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
6049                     fp == I915_READ(PCH_FP0(0))) {
6050                         intel_crtc->use_pll_a = true;
6051                         DRM_DEBUG_KMS("using pipe a dpll\n");
6052                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
6053                            fp == I915_READ(PCH_FP0(1))) {
6054                         intel_crtc->use_pll_a = false;
6055                         DRM_DEBUG_KMS("using pipe b dpll\n");
6056                 } else {
6057                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
6058                         return -EINVAL;
6059                 }
6060         }
6061
6062         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
6063          * This is an exception to the general rule that mode_set doesn't turn
6064          * things on.
6065          */
6066         if (is_lvds) {
6067                 temp = I915_READ(PCH_LVDS);
6068                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
6069                 if (HAS_PCH_CPT(dev)) {
6070                         temp &= ~PORT_TRANS_SEL_MASK;
6071                         temp |= PORT_TRANS_SEL_CPT(pipe);
6072                 } else {
6073                         if (pipe == 1)
6074                                 temp |= LVDS_PIPEB_SELECT;
6075                         else
6076                                 temp &= ~LVDS_PIPEB_SELECT;
6077                 }
6078
6079                 /* set the corresponsding LVDS_BORDER bit */
6080                 temp |= dev_priv->lvds_border_bits;
6081                 /* Set the B0-B3 data pairs corresponding to whether we're going to
6082                  * set the DPLLs for dual-channel mode or not.
6083                  */
6084                 if (clock.p2 == 7)
6085                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6086                 else
6087                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6088
6089                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6090                  * appropriately here, but we need to look more thoroughly into how
6091                  * panels behave in the two modes.
6092                  */
6093                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6094                         lvds_sync |= LVDS_HSYNC_POLARITY;
6095                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6096                         lvds_sync |= LVDS_VSYNC_POLARITY;
6097                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6098                     != lvds_sync) {
6099                         char flags[2] = "-+";
6100                         DRM_INFO("Changing LVDS panel from "
6101                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6102                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
6103                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
6104                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6105                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6106                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6107                         temp |= lvds_sync;
6108                 }
6109                 I915_WRITE(PCH_LVDS, temp);
6110         }
6111
6112         pipeconf &= ~PIPECONF_DITHER_EN;
6113         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
6114         if ((is_lvds && dev_priv->lvds_dither) || dither) {
6115                 pipeconf |= PIPECONF_DITHER_EN;
6116                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6117         }
6118         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6119                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6120         } else {
6121                 /* For non-DP output, clear any trans DP clock recovery setting.*/
6122                 I915_WRITE(TRANSDATA_M1(pipe), 0);
6123                 I915_WRITE(TRANSDATA_N1(pipe), 0);
6124                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6125                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6126         }
6127
6128         if (!intel_crtc->no_pll &&
6129             (!has_edp_encoder ||
6130              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6131                 I915_WRITE(PCH_DPLL(pipe), dpll);
6132
6133                 /* Wait for the clocks to stabilize. */
6134                 POSTING_READ(PCH_DPLL(pipe));
6135                 udelay(150);
6136
6137                 /* The pixel multiplier can only be updated once the
6138                  * DPLL is enabled and the clocks are stable.
6139                  *
6140                  * So write it again.
6141                  */
6142                 I915_WRITE(PCH_DPLL(pipe), dpll);
6143         }
6144
6145         intel_crtc->lowfreq_avail = false;
6146         if (!intel_crtc->no_pll) {
6147                 if (is_lvds && has_reduced_clock && i915_powersave) {
6148                         I915_WRITE(PCH_FP1(pipe), fp2);
6149                         intel_crtc->lowfreq_avail = true;
6150                         if (HAS_PIPE_CXSR(dev)) {
6151                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6152                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6153                         }
6154                 } else {
6155                         I915_WRITE(PCH_FP1(pipe), fp);
6156                         if (HAS_PIPE_CXSR(dev)) {
6157                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6158                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6159                         }
6160                 }
6161         }
6162
6163         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6164         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6165                 pipeconf |= PIPECONF_INTERLACED_ILK;
6166                 /* the chip adds 2 halflines automatically */
6167                 adjusted_mode->crtc_vtotal -= 1;
6168                 adjusted_mode->crtc_vblank_end -= 1;
6169                 I915_WRITE(VSYNCSHIFT(pipe),
6170                            adjusted_mode->crtc_hsync_start
6171                            - adjusted_mode->crtc_htotal/2);
6172         } else {
6173                 pipeconf |= PIPECONF_PROGRESSIVE;
6174                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6175         }
6176
6177         I915_WRITE(HTOTAL(pipe),
6178                    (adjusted_mode->crtc_hdisplay - 1) |
6179                    ((adjusted_mode->crtc_htotal - 1) << 16));
6180         I915_WRITE(HBLANK(pipe),
6181                    (adjusted_mode->crtc_hblank_start - 1) |
6182                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6183         I915_WRITE(HSYNC(pipe),
6184                    (adjusted_mode->crtc_hsync_start - 1) |
6185                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6186
6187         I915_WRITE(VTOTAL(pipe),
6188                    (adjusted_mode->crtc_vdisplay - 1) |
6189                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6190         I915_WRITE(VBLANK(pipe),
6191                    (adjusted_mode->crtc_vblank_start - 1) |
6192                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6193         I915_WRITE(VSYNC(pipe),
6194                    (adjusted_mode->crtc_vsync_start - 1) |
6195                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6196
6197         /* pipesrc controls the size that is scaled from, which should
6198          * always be the user's requested size.
6199          */
6200         I915_WRITE(PIPESRC(pipe),
6201                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6202
6203         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6204         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6205         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6206         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6207
6208         if (has_edp_encoder &&
6209             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6210                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6211         }
6212
6213         I915_WRITE(PIPECONF(pipe), pipeconf);
6214         POSTING_READ(PIPECONF(pipe));
6215
6216         intel_wait_for_vblank(dev, pipe);
6217
6218         I915_WRITE(DSPCNTR(plane), dspcntr);
6219         POSTING_READ(DSPCNTR(plane));
6220
6221         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6222
6223         intel_update_watermarks(dev);
6224
6225         return ret;
6226 }
6227
6228 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6229                                struct drm_display_mode *mode,
6230                                struct drm_display_mode *adjusted_mode,
6231                                int x, int y,
6232                                struct drm_framebuffer *old_fb)
6233 {
6234         struct drm_device *dev = crtc->dev;
6235         struct drm_i915_private *dev_priv = dev->dev_private;
6236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237         int pipe = intel_crtc->pipe;
6238         int ret;
6239
6240         drm_vblank_pre_modeset(dev, pipe);
6241
6242         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6243                                               x, y, old_fb);
6244         drm_vblank_post_modeset(dev, pipe);
6245
6246         if (ret)
6247                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6248         else
6249                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6250
6251         return ret;
6252 }
6253
6254 static bool intel_eld_uptodate(struct drm_connector *connector,
6255                                int reg_eldv, uint32_t bits_eldv,
6256                                int reg_elda, uint32_t bits_elda,
6257                                int reg_edid)
6258 {
6259         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6260         uint8_t *eld = connector->eld;
6261         uint32_t i;
6262
6263         i = I915_READ(reg_eldv);
6264         i &= bits_eldv;
6265
6266         if (!eld[0])
6267                 return !i;
6268
6269         if (!i)
6270                 return false;
6271
6272         i = I915_READ(reg_elda);
6273         i &= ~bits_elda;
6274         I915_WRITE(reg_elda, i);
6275
6276         for (i = 0; i < eld[2]; i++)
6277                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6278                         return false;
6279
6280         return true;
6281 }
6282
6283 static void g4x_write_eld(struct drm_connector *connector,
6284                           struct drm_crtc *crtc)
6285 {
6286         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6287         uint8_t *eld = connector->eld;
6288         uint32_t eldv;
6289         uint32_t len;
6290         uint32_t i;
6291
6292         i = I915_READ(G4X_AUD_VID_DID);
6293
6294         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6295                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6296         else
6297                 eldv = G4X_ELDV_DEVCTG;
6298
6299         if (intel_eld_uptodate(connector,
6300                                G4X_AUD_CNTL_ST, eldv,
6301                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6302                                G4X_HDMIW_HDMIEDID))
6303                 return;
6304
6305         i = I915_READ(G4X_AUD_CNTL_ST);
6306         i &= ~(eldv | G4X_ELD_ADDR);
6307         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6308         I915_WRITE(G4X_AUD_CNTL_ST, i);
6309
6310         if (!eld[0])
6311                 return;
6312
6313         len = min_t(uint8_t, eld[2], len);
6314         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6315         for (i = 0; i < len; i++)
6316                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6317
6318         i = I915_READ(G4X_AUD_CNTL_ST);
6319         i |= eldv;
6320         I915_WRITE(G4X_AUD_CNTL_ST, i);
6321 }
6322
6323 static void ironlake_write_eld(struct drm_connector *connector,
6324                                      struct drm_crtc *crtc)
6325 {
6326         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6327         uint8_t *eld = connector->eld;
6328         uint32_t eldv;
6329         uint32_t i;
6330         int len;
6331         int hdmiw_hdmiedid;
6332         int aud_config;
6333         int aud_cntl_st;
6334         int aud_cntrl_st2;
6335
6336         if (HAS_PCH_IBX(connector->dev)) {
6337                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6338                 aud_config = IBX_AUD_CONFIG_A;
6339                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6340                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6341         } else {
6342                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6343                 aud_config = CPT_AUD_CONFIG_A;
6344                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6345                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6346         }
6347
6348         i = to_intel_crtc(crtc)->pipe;
6349         hdmiw_hdmiedid += i * 0x100;
6350         aud_cntl_st += i * 0x100;
6351         aud_config += i * 0x100;
6352
6353         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6354
6355         i = I915_READ(aud_cntl_st);
6356         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6357         if (!i) {
6358                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6359                 /* operate blindly on all ports */
6360                 eldv = IBX_ELD_VALIDB;
6361                 eldv |= IBX_ELD_VALIDB << 4;
6362                 eldv |= IBX_ELD_VALIDB << 8;
6363         } else {
6364                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6365                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6366         }
6367
6368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6369                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6370                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6371                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6372         } else
6373                 I915_WRITE(aud_config, 0);
6374
6375         if (intel_eld_uptodate(connector,
6376                                aud_cntrl_st2, eldv,
6377                                aud_cntl_st, IBX_ELD_ADDRESS,
6378                                hdmiw_hdmiedid))
6379                 return;
6380
6381         i = I915_READ(aud_cntrl_st2);
6382         i &= ~eldv;
6383         I915_WRITE(aud_cntrl_st2, i);
6384
6385         if (!eld[0])
6386                 return;
6387
6388         i = I915_READ(aud_cntl_st);
6389         i &= ~IBX_ELD_ADDRESS;
6390         I915_WRITE(aud_cntl_st, i);
6391
6392         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6393         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6394         for (i = 0; i < len; i++)
6395                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6396
6397         i = I915_READ(aud_cntrl_st2);
6398         i |= eldv;
6399         I915_WRITE(aud_cntrl_st2, i);
6400 }
6401
6402 void intel_write_eld(struct drm_encoder *encoder,
6403                      struct drm_display_mode *mode)
6404 {
6405         struct drm_crtc *crtc = encoder->crtc;
6406         struct drm_connector *connector;
6407         struct drm_device *dev = encoder->dev;
6408         struct drm_i915_private *dev_priv = dev->dev_private;
6409
6410         connector = drm_select_eld(encoder, mode);
6411         if (!connector)
6412                 return;
6413
6414         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6415                          connector->base.id,
6416                          drm_get_connector_name(connector),
6417                          connector->encoder->base.id,
6418                          drm_get_encoder_name(connector->encoder));
6419
6420         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6421
6422         if (dev_priv->display.write_eld)
6423                 dev_priv->display.write_eld(connector, crtc);
6424 }
6425
6426 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6427 void intel_crtc_load_lut(struct drm_crtc *crtc)
6428 {
6429         struct drm_device *dev = crtc->dev;
6430         struct drm_i915_private *dev_priv = dev->dev_private;
6431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432         int palreg = PALETTE(intel_crtc->pipe);
6433         int i;
6434
6435         /* The clocks have to be on to load the palette. */
6436         if (!crtc->enabled)
6437                 return;
6438
6439         /* use legacy palette for Ironlake */
6440         if (HAS_PCH_SPLIT(dev))
6441                 palreg = LGC_PALETTE(intel_crtc->pipe);
6442
6443         for (i = 0; i < 256; i++) {
6444                 I915_WRITE(palreg + 4 * i,
6445                            (intel_crtc->lut_r[i] << 16) |
6446                            (intel_crtc->lut_g[i] << 8) |
6447                            intel_crtc->lut_b[i]);
6448         }
6449 }
6450
6451 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6452 {
6453         struct drm_device *dev = crtc->dev;
6454         struct drm_i915_private *dev_priv = dev->dev_private;
6455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6456         bool visible = base != 0;
6457         u32 cntl;
6458
6459         if (intel_crtc->cursor_visible == visible)
6460                 return;
6461
6462         cntl = I915_READ(_CURACNTR);
6463         if (visible) {
6464                 /* On these chipsets we can only modify the base whilst
6465                  * the cursor is disabled.
6466                  */
6467                 I915_WRITE(_CURABASE, base);
6468
6469                 cntl &= ~(CURSOR_FORMAT_MASK);
6470                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6471                 cntl |= CURSOR_ENABLE |
6472                         CURSOR_GAMMA_ENABLE |
6473                         CURSOR_FORMAT_ARGB;
6474         } else
6475                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6476         I915_WRITE(_CURACNTR, cntl);
6477
6478         intel_crtc->cursor_visible = visible;
6479 }
6480
6481 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6482 {
6483         struct drm_device *dev = crtc->dev;
6484         struct drm_i915_private *dev_priv = dev->dev_private;
6485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6486         int pipe = intel_crtc->pipe;
6487         bool visible = base != 0;
6488
6489         if (intel_crtc->cursor_visible != visible) {
6490                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6491                 if (base) {
6492                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6493                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6494                         cntl |= pipe << 28; /* Connect to correct pipe */
6495                 } else {
6496                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6497                         cntl |= CURSOR_MODE_DISABLE;
6498                 }
6499                 I915_WRITE(CURCNTR(pipe), cntl);
6500
6501                 intel_crtc->cursor_visible = visible;
6502         }
6503         /* and commit changes on next vblank */
6504         I915_WRITE(CURBASE(pipe), base);
6505 }
6506
6507 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6508 {
6509         struct drm_device *dev = crtc->dev;
6510         struct drm_i915_private *dev_priv = dev->dev_private;
6511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6512         int pipe = intel_crtc->pipe;
6513         bool visible = base != 0;
6514
6515         if (intel_crtc->cursor_visible != visible) {
6516                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6517                 if (base) {
6518                         cntl &= ~CURSOR_MODE;
6519                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6520                 } else {
6521                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6522                         cntl |= CURSOR_MODE_DISABLE;
6523                 }
6524                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6525
6526                 intel_crtc->cursor_visible = visible;
6527         }
6528         /* and commit changes on next vblank */
6529         I915_WRITE(CURBASE_IVB(pipe), base);
6530 }
6531
6532 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6533 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6534                                      bool on)
6535 {
6536         struct drm_device *dev = crtc->dev;
6537         struct drm_i915_private *dev_priv = dev->dev_private;
6538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6539         int pipe = intel_crtc->pipe;
6540         int x = intel_crtc->cursor_x;
6541         int y = intel_crtc->cursor_y;
6542         u32 base, pos;
6543         bool visible;
6544
6545         pos = 0;
6546
6547         if (on && crtc->enabled && crtc->fb) {
6548                 base = intel_crtc->cursor_addr;
6549                 if (x > (int) crtc->fb->width)
6550                         base = 0;
6551
6552                 if (y > (int) crtc->fb->height)
6553                         base = 0;
6554         } else
6555                 base = 0;
6556
6557         if (x < 0) {
6558                 if (x + intel_crtc->cursor_width < 0)
6559                         base = 0;
6560
6561                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6562                 x = -x;
6563         }
6564         pos |= x << CURSOR_X_SHIFT;
6565
6566         if (y < 0) {
6567                 if (y + intel_crtc->cursor_height < 0)
6568                         base = 0;
6569
6570                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6571                 y = -y;
6572         }
6573         pos |= y << CURSOR_Y_SHIFT;
6574
6575         visible = base != 0;
6576         if (!visible && !intel_crtc->cursor_visible)
6577                 return;
6578
6579         if (IS_IVYBRIDGE(dev)) {
6580                 I915_WRITE(CURPOS_IVB(pipe), pos);
6581                 ivb_update_cursor(crtc, base);
6582         } else {
6583                 I915_WRITE(CURPOS(pipe), pos);
6584                 if (IS_845G(dev) || IS_I865G(dev))
6585                         i845_update_cursor(crtc, base);
6586                 else
6587                         i9xx_update_cursor(crtc, base);
6588         }
6589
6590         if (visible)
6591                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6592 }
6593
6594 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6595                                  struct drm_file *file,
6596                                  uint32_t handle,
6597                                  uint32_t width, uint32_t height)
6598 {
6599         struct drm_device *dev = crtc->dev;
6600         struct drm_i915_private *dev_priv = dev->dev_private;
6601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602         struct drm_i915_gem_object *obj;
6603         uint32_t addr;
6604         int ret;
6605
6606         DRM_DEBUG_KMS("\n");
6607
6608         /* if we want to turn off the cursor ignore width and height */
6609         if (!handle) {
6610                 DRM_DEBUG_KMS("cursor off\n");
6611                 addr = 0;
6612                 obj = NULL;
6613                 mutex_lock(&dev->struct_mutex);
6614                 goto finish;
6615         }
6616
6617         /* Currently we only support 64x64 cursors */
6618         if (width != 64 || height != 64) {
6619                 DRM_ERROR("we currently only support 64x64 cursors\n");
6620                 return -EINVAL;
6621         }
6622
6623         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6624         if (&obj->base == NULL)
6625                 return -ENOENT;
6626
6627         if (obj->base.size < width * height * 4) {
6628                 DRM_ERROR("buffer is to small\n");
6629                 ret = -ENOMEM;
6630                 goto fail;
6631         }
6632
6633         /* we only need to pin inside GTT if cursor is non-phy */
6634         mutex_lock(&dev->struct_mutex);
6635         if (!dev_priv->info->cursor_needs_physical) {
6636                 if (obj->tiling_mode) {
6637                         DRM_ERROR("cursor cannot be tiled\n");
6638                         ret = -EINVAL;
6639                         goto fail_locked;
6640                 }
6641
6642                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6643                 if (ret) {
6644                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6645                         goto fail_locked;
6646                 }
6647
6648                 ret = i915_gem_object_put_fence(obj);
6649                 if (ret) {
6650                         DRM_ERROR("failed to release fence for cursor");
6651                         goto fail_unpin;
6652                 }
6653
6654                 addr = obj->gtt_offset;
6655         } else {
6656                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6657                 ret = i915_gem_attach_phys_object(dev, obj,
6658                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6659                                                   align);
6660                 if (ret) {
6661                         DRM_ERROR("failed to attach phys object\n");
6662                         goto fail_locked;
6663                 }
6664                 addr = obj->phys_obj->handle->busaddr;
6665         }
6666
6667         if (IS_GEN2(dev))
6668                 I915_WRITE(CURSIZE, (height << 12) | width);
6669
6670  finish:
6671         if (intel_crtc->cursor_bo) {
6672                 if (dev_priv->info->cursor_needs_physical) {
6673                         if (intel_crtc->cursor_bo != obj)
6674                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6675                 } else
6676                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6677                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6678         }
6679
6680         mutex_unlock(&dev->struct_mutex);
6681
6682         intel_crtc->cursor_addr = addr;
6683         intel_crtc->cursor_bo = obj;
6684         intel_crtc->cursor_width = width;
6685         intel_crtc->cursor_height = height;
6686
6687         intel_crtc_update_cursor(crtc, true);
6688
6689         return 0;
6690 fail_unpin:
6691         i915_gem_object_unpin(obj);
6692 fail_locked:
6693         mutex_unlock(&dev->struct_mutex);
6694 fail:
6695         drm_gem_object_unreference_unlocked(&obj->base);
6696         return ret;
6697 }
6698
6699 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6700 {
6701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6702
6703         intel_crtc->cursor_x = x;
6704         intel_crtc->cursor_y = y;
6705
6706         intel_crtc_update_cursor(crtc, true);
6707
6708         return 0;
6709 }
6710
6711 /** Sets the color ramps on behalf of RandR */
6712 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6713                                  u16 blue, int regno)
6714 {
6715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6716
6717         intel_crtc->lut_r[regno] = red >> 8;
6718         intel_crtc->lut_g[regno] = green >> 8;
6719         intel_crtc->lut_b[regno] = blue >> 8;
6720 }
6721
6722 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6723                              u16 *blue, int regno)
6724 {
6725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6726
6727         *red = intel_crtc->lut_r[regno] << 8;
6728         *green = intel_crtc->lut_g[regno] << 8;
6729         *blue = intel_crtc->lut_b[regno] << 8;
6730 }
6731
6732 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6733                                  u16 *blue, uint32_t start, uint32_t size)
6734 {
6735         int end = (start + size > 256) ? 256 : start + size, i;
6736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737
6738         for (i = start; i < end; i++) {
6739                 intel_crtc->lut_r[i] = red[i] >> 8;
6740                 intel_crtc->lut_g[i] = green[i] >> 8;
6741                 intel_crtc->lut_b[i] = blue[i] >> 8;
6742         }
6743
6744         intel_crtc_load_lut(crtc);
6745 }
6746
6747 /**
6748  * Get a pipe with a simple mode set on it for doing load-based monitor
6749  * detection.
6750  *
6751  * It will be up to the load-detect code to adjust the pipe as appropriate for
6752  * its requirements.  The pipe will be connected to no other encoders.
6753  *
6754  * Currently this code will only succeed if there is a pipe with no encoders
6755  * configured for it.  In the future, it could choose to temporarily disable
6756  * some outputs to free up a pipe for its use.
6757  *
6758  * \return crtc, or NULL if no pipes are available.
6759  */
6760
6761 /* VESA 640x480x72Hz mode to set on the pipe */
6762 static struct drm_display_mode load_detect_mode = {
6763         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6764                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6765 };
6766
6767 static struct drm_framebuffer *
6768 intel_framebuffer_create(struct drm_device *dev,
6769                          struct drm_mode_fb_cmd2 *mode_cmd,
6770                          struct drm_i915_gem_object *obj)
6771 {
6772         struct intel_framebuffer *intel_fb;
6773         int ret;
6774
6775         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6776         if (!intel_fb) {
6777                 drm_gem_object_unreference_unlocked(&obj->base);
6778                 return ERR_PTR(-ENOMEM);
6779         }
6780
6781         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6782         if (ret) {
6783                 drm_gem_object_unreference_unlocked(&obj->base);
6784                 kfree(intel_fb);
6785                 return ERR_PTR(ret);
6786         }
6787
6788         return &intel_fb->base;
6789 }
6790
6791 static u32
6792 intel_framebuffer_pitch_for_width(int width, int bpp)
6793 {
6794         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6795         return ALIGN(pitch, 64);
6796 }
6797
6798 static u32
6799 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6800 {
6801         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6802         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6803 }
6804
6805 static struct drm_framebuffer *
6806 intel_framebuffer_create_for_mode(struct drm_device *dev,
6807                                   struct drm_display_mode *mode,
6808                                   int depth, int bpp)
6809 {
6810         struct drm_i915_gem_object *obj;
6811         struct drm_mode_fb_cmd2 mode_cmd;
6812
6813         obj = i915_gem_alloc_object(dev,
6814                                     intel_framebuffer_size_for_mode(mode, bpp));
6815         if (obj == NULL)
6816                 return ERR_PTR(-ENOMEM);
6817
6818         mode_cmd.width = mode->hdisplay;
6819         mode_cmd.height = mode->vdisplay;
6820         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6821                                                                 bpp);
6822         mode_cmd.pixel_format = 0;
6823
6824         return intel_framebuffer_create(dev, &mode_cmd, obj);
6825 }
6826
6827 static struct drm_framebuffer *
6828 mode_fits_in_fbdev(struct drm_device *dev,
6829                    struct drm_display_mode *mode)
6830 {
6831         struct drm_i915_private *dev_priv = dev->dev_private;
6832         struct drm_i915_gem_object *obj;
6833         struct drm_framebuffer *fb;
6834
6835         if (dev_priv->fbdev == NULL)
6836                 return NULL;
6837
6838         obj = dev_priv->fbdev->ifb.obj;
6839         if (obj == NULL)
6840                 return NULL;
6841
6842         fb = &dev_priv->fbdev->ifb.base;
6843         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6844                                                                fb->bits_per_pixel))
6845                 return NULL;
6846
6847         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6848                 return NULL;
6849
6850         return fb;
6851 }
6852
6853 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6854                                 struct drm_connector *connector,
6855                                 struct drm_display_mode *mode,
6856                                 struct intel_load_detect_pipe *old)
6857 {
6858         struct intel_crtc *intel_crtc;
6859         struct drm_crtc *possible_crtc;
6860         struct drm_encoder *encoder = &intel_encoder->base;
6861         struct drm_crtc *crtc = NULL;
6862         struct drm_device *dev = encoder->dev;
6863         struct drm_framebuffer *old_fb;
6864         int i = -1;
6865
6866         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6867                       connector->base.id, drm_get_connector_name(connector),
6868                       encoder->base.id, drm_get_encoder_name(encoder));
6869
6870         /*
6871          * Algorithm gets a little messy:
6872          *
6873          *   - if the connector already has an assigned crtc, use it (but make
6874          *     sure it's on first)
6875          *
6876          *   - try to find the first unused crtc that can drive this connector,
6877          *     and use that if we find one
6878          */
6879
6880         /* See if we already have a CRTC for this connector */
6881         if (encoder->crtc) {
6882                 crtc = encoder->crtc;
6883
6884                 intel_crtc = to_intel_crtc(crtc);
6885                 old->dpms_mode = intel_crtc->dpms_mode;
6886                 old->load_detect_temp = false;
6887
6888                 /* Make sure the crtc and connector are running */
6889                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6890                         struct drm_encoder_helper_funcs *encoder_funcs;
6891                         struct drm_crtc_helper_funcs *crtc_funcs;
6892
6893                         crtc_funcs = crtc->helper_private;
6894                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6895
6896                         encoder_funcs = encoder->helper_private;
6897                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6898                 }
6899
6900                 return true;
6901         }
6902
6903         /* Find an unused one (if possible) */
6904         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6905                 i++;
6906                 if (!(encoder->possible_crtcs & (1 << i)))
6907                         continue;
6908                 if (!possible_crtc->enabled) {
6909                         crtc = possible_crtc;
6910                         break;
6911                 }
6912         }
6913
6914         /*
6915          * If we didn't find an unused CRTC, don't use any.
6916          */
6917         if (!crtc) {
6918                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6919                 return false;
6920         }
6921
6922         encoder->crtc = crtc;
6923         connector->encoder = encoder;
6924
6925         intel_crtc = to_intel_crtc(crtc);
6926         old->dpms_mode = intel_crtc->dpms_mode;
6927         old->load_detect_temp = true;
6928         old->release_fb = NULL;
6929
6930         if (!mode)
6931                 mode = &load_detect_mode;
6932
6933         old_fb = crtc->fb;
6934
6935         /* We need a framebuffer large enough to accommodate all accesses
6936          * that the plane may generate whilst we perform load detection.
6937          * We can not rely on the fbcon either being present (we get called
6938          * during its initialisation to detect all boot displays, or it may
6939          * not even exist) or that it is large enough to satisfy the
6940          * requested mode.
6941          */
6942         crtc->fb = mode_fits_in_fbdev(dev, mode);
6943         if (crtc->fb == NULL) {
6944                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6945                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6946                 old->release_fb = crtc->fb;
6947         } else
6948                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6949         if (IS_ERR(crtc->fb)) {
6950                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6951                 crtc->fb = old_fb;
6952                 return false;
6953         }
6954
6955         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6956                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6957                 if (old->release_fb)
6958                         old->release_fb->funcs->destroy(old->release_fb);
6959                 crtc->fb = old_fb;
6960                 return false;
6961         }
6962
6963         /* let the connector get through one full cycle before testing */
6964         intel_wait_for_vblank(dev, intel_crtc->pipe);
6965
6966         return true;
6967 }
6968
6969 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6970                                     struct drm_connector *connector,
6971                                     struct intel_load_detect_pipe *old)
6972 {
6973         struct drm_encoder *encoder = &intel_encoder->base;
6974         struct drm_device *dev = encoder->dev;
6975         struct drm_crtc *crtc = encoder->crtc;
6976         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6977         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6978
6979         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6980                       connector->base.id, drm_get_connector_name(connector),
6981                       encoder->base.id, drm_get_encoder_name(encoder));
6982
6983         if (old->load_detect_temp) {
6984                 connector->encoder = NULL;
6985                 drm_helper_disable_unused_functions(dev);
6986
6987                 if (old->release_fb)
6988                         old->release_fb->funcs->destroy(old->release_fb);
6989
6990                 return;
6991         }
6992
6993         /* Switch crtc and encoder back off if necessary */
6994         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6995                 encoder_funcs->dpms(encoder, old->dpms_mode);
6996                 crtc_funcs->dpms(crtc, old->dpms_mode);
6997         }
6998 }
6999
7000 /* Returns the clock of the currently programmed mode of the given pipe. */
7001 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
7002 {
7003         struct drm_i915_private *dev_priv = dev->dev_private;
7004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7005         int pipe = intel_crtc->pipe;
7006         u32 dpll = I915_READ(DPLL(pipe));
7007         u32 fp;
7008         intel_clock_t clock;
7009
7010         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7011                 fp = I915_READ(FP0(pipe));
7012         else
7013                 fp = I915_READ(FP1(pipe));
7014
7015         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7016         if (IS_PINEVIEW(dev)) {
7017                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7018                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7019         } else {
7020                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7021                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7022         }
7023
7024         if (!IS_GEN2(dev)) {
7025                 if (IS_PINEVIEW(dev))
7026                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7027                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7028                 else
7029                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7030                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7031
7032                 switch (dpll & DPLL_MODE_MASK) {
7033                 case DPLLB_MODE_DAC_SERIAL:
7034                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7035                                 5 : 10;
7036                         break;
7037                 case DPLLB_MODE_LVDS:
7038                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7039                                 7 : 14;
7040                         break;
7041                 default:
7042                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7043                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7044                         return 0;
7045                 }
7046
7047                 /* XXX: Handle the 100Mhz refclk */
7048                 intel_clock(dev, 96000, &clock);
7049         } else {
7050                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7051
7052                 if (is_lvds) {
7053                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7054                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7055                         clock.p2 = 14;
7056
7057                         if ((dpll & PLL_REF_INPUT_MASK) ==
7058                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7059                                 /* XXX: might not be 66MHz */
7060                                 intel_clock(dev, 66000, &clock);
7061                         } else
7062                                 intel_clock(dev, 48000, &clock);
7063                 } else {
7064                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7065                                 clock.p1 = 2;
7066                         else {
7067                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7068                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7069                         }
7070                         if (dpll & PLL_P2_DIVIDE_BY_4)
7071                                 clock.p2 = 4;
7072                         else
7073                                 clock.p2 = 2;
7074
7075                         intel_clock(dev, 48000, &clock);
7076                 }
7077         }
7078
7079         /* XXX: It would be nice to validate the clocks, but we can't reuse
7080          * i830PllIsValid() because it relies on the xf86_config connector
7081          * configuration being accurate, which it isn't necessarily.
7082          */
7083
7084         return clock.dot;
7085 }
7086
7087 /** Returns the currently programmed mode of the given pipe. */
7088 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7089                                              struct drm_crtc *crtc)
7090 {
7091         struct drm_i915_private *dev_priv = dev->dev_private;
7092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7093         int pipe = intel_crtc->pipe;
7094         struct drm_display_mode *mode;
7095         int htot = I915_READ(HTOTAL(pipe));
7096         int hsync = I915_READ(HSYNC(pipe));
7097         int vtot = I915_READ(VTOTAL(pipe));
7098         int vsync = I915_READ(VSYNC(pipe));
7099
7100         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7101         if (!mode)
7102                 return NULL;
7103
7104         mode->clock = intel_crtc_clock_get(dev, crtc);
7105         mode->hdisplay = (htot & 0xffff) + 1;
7106         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7107         mode->hsync_start = (hsync & 0xffff) + 1;
7108         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7109         mode->vdisplay = (vtot & 0xffff) + 1;
7110         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7111         mode->vsync_start = (vsync & 0xffff) + 1;
7112         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7113
7114         drm_mode_set_name(mode);
7115         drm_mode_set_crtcinfo(mode, 0);
7116
7117         return mode;
7118 }
7119
7120 #define GPU_IDLE_TIMEOUT 500 /* ms */
7121
7122 /* When this timer fires, we've been idle for awhile */
7123 static void intel_gpu_idle_timer(unsigned long arg)
7124 {
7125         struct drm_device *dev = (struct drm_device *)arg;
7126         drm_i915_private_t *dev_priv = dev->dev_private;
7127
7128         if (!list_empty(&dev_priv->mm.active_list)) {
7129                 /* Still processing requests, so just re-arm the timer. */
7130                 mod_timer(&dev_priv->idle_timer, jiffies +
7131                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7132                 return;
7133         }
7134
7135         dev_priv->busy = false;
7136         queue_work(dev_priv->wq, &dev_priv->idle_work);
7137 }
7138
7139 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7140
7141 static void intel_crtc_idle_timer(unsigned long arg)
7142 {
7143         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7144         struct drm_crtc *crtc = &intel_crtc->base;
7145         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7146         struct intel_framebuffer *intel_fb;
7147
7148         intel_fb = to_intel_framebuffer(crtc->fb);
7149         if (intel_fb && intel_fb->obj->active) {
7150                 /* The framebuffer is still being accessed by the GPU. */
7151                 mod_timer(&intel_crtc->idle_timer, jiffies +
7152                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7153                 return;
7154         }
7155
7156         intel_crtc->busy = false;
7157         queue_work(dev_priv->wq, &dev_priv->idle_work);
7158 }
7159
7160 static void intel_increase_pllclock(struct drm_crtc *crtc)
7161 {
7162         struct drm_device *dev = crtc->dev;
7163         drm_i915_private_t *dev_priv = dev->dev_private;
7164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165         int pipe = intel_crtc->pipe;
7166         int dpll_reg = DPLL(pipe);
7167         int dpll;
7168
7169         if (HAS_PCH_SPLIT(dev))
7170                 return;
7171
7172         if (!dev_priv->lvds_downclock_avail)
7173                 return;
7174
7175         dpll = I915_READ(dpll_reg);
7176         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7177                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7178
7179                 assert_panel_unlocked(dev_priv, pipe);
7180
7181                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7182                 I915_WRITE(dpll_reg, dpll);
7183                 intel_wait_for_vblank(dev, pipe);
7184
7185                 dpll = I915_READ(dpll_reg);
7186                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7187                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7188         }
7189
7190         /* Schedule downclock */
7191         mod_timer(&intel_crtc->idle_timer, jiffies +
7192                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7193 }
7194
7195 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7196 {
7197         struct drm_device *dev = crtc->dev;
7198         drm_i915_private_t *dev_priv = dev->dev_private;
7199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7200         int pipe = intel_crtc->pipe;
7201         int dpll_reg = DPLL(pipe);
7202         int dpll = I915_READ(dpll_reg);
7203
7204         if (HAS_PCH_SPLIT(dev))
7205                 return;
7206
7207         if (!dev_priv->lvds_downclock_avail)
7208                 return;
7209
7210         /*
7211          * Since this is called by a timer, we should never get here in
7212          * the manual case.
7213          */
7214         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7215                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7216
7217                 assert_panel_unlocked(dev_priv, pipe);
7218
7219                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7220                 I915_WRITE(dpll_reg, dpll);
7221                 intel_wait_for_vblank(dev, pipe);
7222                 dpll = I915_READ(dpll_reg);
7223                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7224                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7225         }
7226
7227 }
7228
7229 /**
7230  * intel_idle_update - adjust clocks for idleness
7231  * @work: work struct
7232  *
7233  * Either the GPU or display (or both) went idle.  Check the busy status
7234  * here and adjust the CRTC and GPU clocks as necessary.
7235  */
7236 static void intel_idle_update(struct work_struct *work)
7237 {
7238         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7239                                                     idle_work);
7240         struct drm_device *dev = dev_priv->dev;
7241         struct drm_crtc *crtc;
7242         struct intel_crtc *intel_crtc;
7243
7244         if (!i915_powersave)
7245                 return;
7246
7247         mutex_lock(&dev->struct_mutex);
7248
7249         i915_update_gfx_val(dev_priv);
7250
7251         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7252                 /* Skip inactive CRTCs */
7253                 if (!crtc->fb)
7254                         continue;
7255
7256                 intel_crtc = to_intel_crtc(crtc);
7257                 if (!intel_crtc->busy)
7258                         intel_decrease_pllclock(crtc);
7259         }
7260
7261
7262         mutex_unlock(&dev->struct_mutex);
7263 }
7264
7265 /**
7266  * intel_mark_busy - mark the GPU and possibly the display busy
7267  * @dev: drm device
7268  * @obj: object we're operating on
7269  *
7270  * Callers can use this function to indicate that the GPU is busy processing
7271  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7272  * buffer), we'll also mark the display as busy, so we know to increase its
7273  * clock frequency.
7274  */
7275 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7276 {
7277         drm_i915_private_t *dev_priv = dev->dev_private;
7278         struct drm_crtc *crtc = NULL;
7279         struct intel_framebuffer *intel_fb;
7280         struct intel_crtc *intel_crtc;
7281
7282         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7283                 return;
7284
7285         if (!dev_priv->busy)
7286                 dev_priv->busy = true;
7287         else
7288                 mod_timer(&dev_priv->idle_timer, jiffies +
7289                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7290
7291         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7292                 if (!crtc->fb)
7293                         continue;
7294
7295                 intel_crtc = to_intel_crtc(crtc);
7296                 intel_fb = to_intel_framebuffer(crtc->fb);
7297                 if (intel_fb->obj == obj) {
7298                         if (!intel_crtc->busy) {
7299                                 /* Non-busy -> busy, upclock */
7300                                 intel_increase_pllclock(crtc);
7301                                 intel_crtc->busy = true;
7302                         } else {
7303                                 /* Busy -> busy, put off timer */
7304                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7305                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7306                         }
7307                 }
7308         }
7309 }
7310
7311 static void intel_crtc_destroy(struct drm_crtc *crtc)
7312 {
7313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314         struct drm_device *dev = crtc->dev;
7315         struct intel_unpin_work *work;
7316         unsigned long flags;
7317
7318         spin_lock_irqsave(&dev->event_lock, flags);
7319         work = intel_crtc->unpin_work;
7320         intel_crtc->unpin_work = NULL;
7321         spin_unlock_irqrestore(&dev->event_lock, flags);
7322
7323         if (work) {
7324                 cancel_work_sync(&work->work);
7325                 kfree(work);
7326         }
7327
7328         drm_crtc_cleanup(crtc);
7329
7330         kfree(intel_crtc);
7331 }
7332
7333 static void intel_unpin_work_fn(struct work_struct *__work)
7334 {
7335         struct intel_unpin_work *work =
7336                 container_of(__work, struct intel_unpin_work, work);
7337
7338         mutex_lock(&work->dev->struct_mutex);
7339         intel_unpin_fb_obj(work->old_fb_obj);
7340         drm_gem_object_unreference(&work->pending_flip_obj->base);
7341         drm_gem_object_unreference(&work->old_fb_obj->base);
7342
7343         intel_update_fbc(work->dev);
7344         mutex_unlock(&work->dev->struct_mutex);
7345         kfree(work);
7346 }
7347
7348 static void do_intel_finish_page_flip(struct drm_device *dev,
7349                                       struct drm_crtc *crtc)
7350 {
7351         drm_i915_private_t *dev_priv = dev->dev_private;
7352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7353         struct intel_unpin_work *work;
7354         struct drm_i915_gem_object *obj;
7355         struct drm_pending_vblank_event *e;
7356         struct timeval tnow, tvbl;
7357         unsigned long flags;
7358
7359         /* Ignore early vblank irqs */
7360         if (intel_crtc == NULL)
7361                 return;
7362
7363         do_gettimeofday(&tnow);
7364
7365         spin_lock_irqsave(&dev->event_lock, flags);
7366         work = intel_crtc->unpin_work;
7367         if (work == NULL || !work->pending) {
7368                 spin_unlock_irqrestore(&dev->event_lock, flags);
7369                 return;
7370         }
7371
7372         intel_crtc->unpin_work = NULL;
7373
7374         if (work->event) {
7375                 e = work->event;
7376                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7377
7378                 /* Called before vblank count and timestamps have
7379                  * been updated for the vblank interval of flip
7380                  * completion? Need to increment vblank count and
7381                  * add one videorefresh duration to returned timestamp
7382                  * to account for this. We assume this happened if we
7383                  * get called over 0.9 frame durations after the last
7384                  * timestamped vblank.
7385                  *
7386                  * This calculation can not be used with vrefresh rates
7387                  * below 5Hz (10Hz to be on the safe side) without
7388                  * promoting to 64 integers.
7389                  */
7390                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7391                     9 * crtc->framedur_ns) {
7392                         e->event.sequence++;
7393                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7394                                              crtc->framedur_ns);
7395                 }
7396
7397                 e->event.tv_sec = tvbl.tv_sec;
7398                 e->event.tv_usec = tvbl.tv_usec;
7399
7400                 list_add_tail(&e->base.link,
7401                               &e->base.file_priv->event_list);
7402                 wake_up_interruptible(&e->base.file_priv->event_wait);
7403         }
7404
7405         drm_vblank_put(dev, intel_crtc->pipe);
7406
7407         spin_unlock_irqrestore(&dev->event_lock, flags);
7408
7409         obj = work->old_fb_obj;
7410
7411         atomic_clear_mask(1 << intel_crtc->plane,
7412                           &obj->pending_flip.counter);
7413         if (atomic_read(&obj->pending_flip) == 0)
7414                 wake_up(&dev_priv->pending_flip_queue);
7415
7416         schedule_work(&work->work);
7417
7418         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7419 }
7420
7421 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7422 {
7423         drm_i915_private_t *dev_priv = dev->dev_private;
7424         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7425
7426         do_intel_finish_page_flip(dev, crtc);
7427 }
7428
7429 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7430 {
7431         drm_i915_private_t *dev_priv = dev->dev_private;
7432         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7433
7434         do_intel_finish_page_flip(dev, crtc);
7435 }
7436
7437 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7438 {
7439         drm_i915_private_t *dev_priv = dev->dev_private;
7440         struct intel_crtc *intel_crtc =
7441                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7442         unsigned long flags;
7443
7444         spin_lock_irqsave(&dev->event_lock, flags);
7445         if (intel_crtc->unpin_work) {
7446                 if ((++intel_crtc->unpin_work->pending) > 1)
7447                         DRM_ERROR("Prepared flip multiple times\n");
7448         } else {
7449                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7450         }
7451         spin_unlock_irqrestore(&dev->event_lock, flags);
7452 }
7453
7454 static int intel_gen2_queue_flip(struct drm_device *dev,
7455                                  struct drm_crtc *crtc,
7456                                  struct drm_framebuffer *fb,
7457                                  struct drm_i915_gem_object *obj)
7458 {
7459         struct drm_i915_private *dev_priv = dev->dev_private;
7460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7461         unsigned long offset;
7462         u32 flip_mask;
7463         int ret;
7464
7465         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7466         if (ret)
7467                 goto out;
7468
7469         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7470         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7471
7472         ret = BEGIN_LP_RING(6);
7473         if (ret)
7474                 goto out;
7475
7476         /* Can't queue multiple flips, so wait for the previous
7477          * one to finish before executing the next.
7478          */
7479         if (intel_crtc->plane)
7480                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7481         else
7482                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7483         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7484         OUT_RING(MI_NOOP);
7485         OUT_RING(MI_DISPLAY_FLIP |
7486                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7487         OUT_RING(fb->pitches[0]);
7488         OUT_RING(obj->gtt_offset + offset);
7489         OUT_RING(0); /* aux display base address, unused */
7490         ADVANCE_LP_RING();
7491 out:
7492         return ret;
7493 }
7494
7495 static int intel_gen3_queue_flip(struct drm_device *dev,
7496                                  struct drm_crtc *crtc,
7497                                  struct drm_framebuffer *fb,
7498                                  struct drm_i915_gem_object *obj)
7499 {
7500         struct drm_i915_private *dev_priv = dev->dev_private;
7501         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7502         unsigned long offset;
7503         u32 flip_mask;
7504         int ret;
7505
7506         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7507         if (ret)
7508                 goto out;
7509
7510         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7511         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7512
7513         ret = BEGIN_LP_RING(6);
7514         if (ret)
7515                 goto out;
7516
7517         if (intel_crtc->plane)
7518                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7519         else
7520                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7521         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7522         OUT_RING(MI_NOOP);
7523         OUT_RING(MI_DISPLAY_FLIP_I915 |
7524                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7525         OUT_RING(fb->pitches[0]);
7526         OUT_RING(obj->gtt_offset + offset);
7527         OUT_RING(MI_NOOP);
7528
7529         ADVANCE_LP_RING();
7530 out:
7531         return ret;
7532 }
7533
7534 static int intel_gen4_queue_flip(struct drm_device *dev,
7535                                  struct drm_crtc *crtc,
7536                                  struct drm_framebuffer *fb,
7537                                  struct drm_i915_gem_object *obj)
7538 {
7539         struct drm_i915_private *dev_priv = dev->dev_private;
7540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7541         uint32_t pf, pipesrc;
7542         int ret;
7543
7544         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7545         if (ret)
7546                 goto out;
7547
7548         ret = BEGIN_LP_RING(4);
7549         if (ret)
7550                 goto out;
7551
7552         /* i965+ uses the linear or tiled offsets from the
7553          * Display Registers (which do not change across a page-flip)
7554          * so we need only reprogram the base address.
7555          */
7556         OUT_RING(MI_DISPLAY_FLIP |
7557                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7558         OUT_RING(fb->pitches[0]);
7559         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7560
7561         /* XXX Enabling the panel-fitter across page-flip is so far
7562          * untested on non-native modes, so ignore it for now.
7563          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7564          */
7565         pf = 0;
7566         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7567         OUT_RING(pf | pipesrc);
7568         ADVANCE_LP_RING();
7569 out:
7570         return ret;
7571 }
7572
7573 static int intel_gen6_queue_flip(struct drm_device *dev,
7574                                  struct drm_crtc *crtc,
7575                                  struct drm_framebuffer *fb,
7576                                  struct drm_i915_gem_object *obj)
7577 {
7578         struct drm_i915_private *dev_priv = dev->dev_private;
7579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7580         uint32_t pf, pipesrc;
7581         int ret;
7582
7583         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7584         if (ret)
7585                 goto out;
7586
7587         ret = BEGIN_LP_RING(4);
7588         if (ret)
7589                 goto out;
7590
7591         OUT_RING(MI_DISPLAY_FLIP |
7592                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7593         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7594         OUT_RING(obj->gtt_offset);
7595
7596         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7597         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7598         OUT_RING(pf | pipesrc);
7599         ADVANCE_LP_RING();
7600 out:
7601         return ret;
7602 }
7603
7604 /*
7605  * On gen7 we currently use the blit ring because (in early silicon at least)
7606  * the render ring doesn't give us interrpts for page flip completion, which
7607  * means clients will hang after the first flip is queued.  Fortunately the
7608  * blit ring generates interrupts properly, so use it instead.
7609  */
7610 static int intel_gen7_queue_flip(struct drm_device *dev,
7611                                  struct drm_crtc *crtc,
7612                                  struct drm_framebuffer *fb,
7613                                  struct drm_i915_gem_object *obj)
7614 {
7615         struct drm_i915_private *dev_priv = dev->dev_private;
7616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7617         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7618         int ret;
7619
7620         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7621         if (ret)
7622                 goto out;
7623
7624         ret = intel_ring_begin(ring, 4);
7625         if (ret)
7626                 goto out;
7627
7628         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7629         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7630         intel_ring_emit(ring, (obj->gtt_offset));
7631         intel_ring_emit(ring, (MI_NOOP));
7632         intel_ring_advance(ring);
7633 out:
7634         return ret;
7635 }
7636
7637 static int intel_default_queue_flip(struct drm_device *dev,
7638                                     struct drm_crtc *crtc,
7639                                     struct drm_framebuffer *fb,
7640                                     struct drm_i915_gem_object *obj)
7641 {
7642         return -ENODEV;
7643 }
7644
7645 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7646                                 struct drm_framebuffer *fb,
7647                                 struct drm_pending_vblank_event *event)
7648 {
7649         struct drm_device *dev = crtc->dev;
7650         struct drm_i915_private *dev_priv = dev->dev_private;
7651         struct intel_framebuffer *intel_fb;
7652         struct drm_i915_gem_object *obj;
7653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7654         struct intel_unpin_work *work;
7655         unsigned long flags;
7656         int ret;
7657
7658         work = kzalloc(sizeof *work, GFP_KERNEL);
7659         if (work == NULL)
7660                 return -ENOMEM;
7661
7662         work->event = event;
7663         work->dev = crtc->dev;
7664         intel_fb = to_intel_framebuffer(crtc->fb);
7665         work->old_fb_obj = intel_fb->obj;
7666         INIT_WORK(&work->work, intel_unpin_work_fn);
7667
7668         ret = drm_vblank_get(dev, intel_crtc->pipe);
7669         if (ret)
7670                 goto free_work;
7671
7672         /* We borrow the event spin lock for protecting unpin_work */
7673         spin_lock_irqsave(&dev->event_lock, flags);
7674         if (intel_crtc->unpin_work) {
7675                 spin_unlock_irqrestore(&dev->event_lock, flags);
7676                 kfree(work);
7677                 drm_vblank_put(dev, intel_crtc->pipe);
7678
7679                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7680                 return -EBUSY;
7681         }
7682         intel_crtc->unpin_work = work;
7683         spin_unlock_irqrestore(&dev->event_lock, flags);
7684
7685         intel_fb = to_intel_framebuffer(fb);
7686         obj = intel_fb->obj;
7687
7688         mutex_lock(&dev->struct_mutex);
7689
7690         /* Reference the objects for the scheduled work. */
7691         drm_gem_object_reference(&work->old_fb_obj->base);
7692         drm_gem_object_reference(&obj->base);
7693
7694         crtc->fb = fb;
7695
7696         work->pending_flip_obj = obj;
7697
7698         work->enable_stall_check = true;
7699
7700         /* Block clients from rendering to the new back buffer until
7701          * the flip occurs and the object is no longer visible.
7702          */
7703         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7704
7705         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7706         if (ret)
7707                 goto cleanup_pending;
7708
7709         intel_disable_fbc(dev);
7710         mutex_unlock(&dev->struct_mutex);
7711
7712         trace_i915_flip_request(intel_crtc->plane, obj);
7713
7714         return 0;
7715
7716 cleanup_pending:
7717         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7718         drm_gem_object_unreference(&work->old_fb_obj->base);
7719         drm_gem_object_unreference(&obj->base);
7720         mutex_unlock(&dev->struct_mutex);
7721
7722         spin_lock_irqsave(&dev->event_lock, flags);
7723         intel_crtc->unpin_work = NULL;
7724         spin_unlock_irqrestore(&dev->event_lock, flags);
7725
7726         drm_vblank_put(dev, intel_crtc->pipe);
7727 free_work:
7728         kfree(work);
7729
7730         return ret;
7731 }
7732
7733 static void intel_sanitize_modesetting(struct drm_device *dev,
7734                                        int pipe, int plane)
7735 {
7736         struct drm_i915_private *dev_priv = dev->dev_private;
7737         u32 reg, val;
7738
7739         if (HAS_PCH_SPLIT(dev))
7740                 return;
7741
7742         /* Who knows what state these registers were left in by the BIOS or
7743          * grub?
7744          *
7745          * If we leave the registers in a conflicting state (e.g. with the
7746          * display plane reading from the other pipe than the one we intend
7747          * to use) then when we attempt to teardown the active mode, we will
7748          * not disable the pipes and planes in the correct order -- leaving
7749          * a plane reading from a disabled pipe and possibly leading to
7750          * undefined behaviour.
7751          */
7752
7753         reg = DSPCNTR(plane);
7754         val = I915_READ(reg);
7755
7756         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7757                 return;
7758         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7759                 return;
7760
7761         /* This display plane is active and attached to the other CPU pipe. */
7762         pipe = !pipe;
7763
7764         /* Disable the plane and wait for it to stop reading from the pipe. */
7765         intel_disable_plane(dev_priv, plane, pipe);
7766         intel_disable_pipe(dev_priv, pipe);
7767 }
7768
7769 static void intel_crtc_reset(struct drm_crtc *crtc)
7770 {
7771         struct drm_device *dev = crtc->dev;
7772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7773
7774         /* Reset flags back to the 'unknown' status so that they
7775          * will be correctly set on the initial modeset.
7776          */
7777         intel_crtc->dpms_mode = -1;
7778
7779         /* We need to fix up any BIOS configuration that conflicts with
7780          * our expectations.
7781          */
7782         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7783 }
7784
7785 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7786         .dpms = intel_crtc_dpms,
7787         .mode_fixup = intel_crtc_mode_fixup,
7788         .mode_set = intel_crtc_mode_set,
7789         .mode_set_base = intel_pipe_set_base,
7790         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7791         .load_lut = intel_crtc_load_lut,
7792         .disable = intel_crtc_disable,
7793 };
7794
7795 static const struct drm_crtc_funcs intel_crtc_funcs = {
7796         .reset = intel_crtc_reset,
7797         .cursor_set = intel_crtc_cursor_set,
7798         .cursor_move = intel_crtc_cursor_move,
7799         .gamma_set = intel_crtc_gamma_set,
7800         .set_config = drm_crtc_helper_set_config,
7801         .destroy = intel_crtc_destroy,
7802         .page_flip = intel_crtc_page_flip,
7803 };
7804
7805 static void intel_crtc_init(struct drm_device *dev, int pipe)
7806 {
7807         drm_i915_private_t *dev_priv = dev->dev_private;
7808         struct intel_crtc *intel_crtc;
7809         int i;
7810
7811         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7812         if (intel_crtc == NULL)
7813                 return;
7814
7815         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7816
7817         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7818         for (i = 0; i < 256; i++) {
7819                 intel_crtc->lut_r[i] = i;
7820                 intel_crtc->lut_g[i] = i;
7821                 intel_crtc->lut_b[i] = i;
7822         }
7823
7824         /* Swap pipes & planes for FBC on pre-965 */
7825         intel_crtc->pipe = pipe;
7826         intel_crtc->plane = pipe;
7827         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7828                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7829                 intel_crtc->plane = !pipe;
7830         }
7831
7832         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7833                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7834         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7835         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7836
7837         intel_crtc_reset(&intel_crtc->base);
7838         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7839         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7840
7841         if (HAS_PCH_SPLIT(dev)) {
7842                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7843                         intel_crtc->no_pll = true;
7844                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7845                 intel_helper_funcs.commit = ironlake_crtc_commit;
7846         } else {
7847                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7848                 intel_helper_funcs.commit = i9xx_crtc_commit;
7849         }
7850
7851         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7852
7853         intel_crtc->busy = false;
7854
7855         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7856                     (unsigned long)intel_crtc);
7857 }
7858
7859 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7860                                 struct drm_file *file)
7861 {
7862         drm_i915_private_t *dev_priv = dev->dev_private;
7863         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7864         struct drm_mode_object *drmmode_obj;
7865         struct intel_crtc *crtc;
7866
7867         if (!dev_priv) {
7868                 DRM_ERROR("called with no initialization\n");
7869                 return -EINVAL;
7870         }
7871
7872         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7873                         DRM_MODE_OBJECT_CRTC);
7874
7875         if (!drmmode_obj) {
7876                 DRM_ERROR("no such CRTC id\n");
7877                 return -EINVAL;
7878         }
7879
7880         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7881         pipe_from_crtc_id->pipe = crtc->pipe;
7882
7883         return 0;
7884 }
7885
7886 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7887 {
7888         struct intel_encoder *encoder;
7889         int index_mask = 0;
7890         int entry = 0;
7891
7892         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7893                 if (type_mask & encoder->clone_mask)
7894                         index_mask |= (1 << entry);
7895                 entry++;
7896         }
7897
7898         return index_mask;
7899 }
7900
7901 static bool has_edp_a(struct drm_device *dev)
7902 {
7903         struct drm_i915_private *dev_priv = dev->dev_private;
7904
7905         if (!IS_MOBILE(dev))
7906                 return false;
7907
7908         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7909                 return false;
7910
7911         if (IS_GEN5(dev) &&
7912             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7913                 return false;
7914
7915         return true;
7916 }
7917
7918 static void intel_setup_outputs(struct drm_device *dev)
7919 {
7920         struct drm_i915_private *dev_priv = dev->dev_private;
7921         struct intel_encoder *encoder;
7922         bool dpd_is_edp = false;
7923         bool has_lvds;
7924
7925         has_lvds = intel_lvds_init(dev);
7926         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7927                 /* disable the panel fitter on everything but LVDS */
7928                 I915_WRITE(PFIT_CONTROL, 0);
7929         }
7930
7931         if (HAS_PCH_SPLIT(dev)) {
7932                 dpd_is_edp = intel_dpd_is_edp(dev);
7933
7934                 if (has_edp_a(dev))
7935                         intel_dp_init(dev, DP_A);
7936
7937                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7938                         intel_dp_init(dev, PCH_DP_D);
7939         }
7940
7941         intel_crt_init(dev);
7942
7943         if (HAS_PCH_SPLIT(dev)) {
7944                 int found;
7945
7946                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7947                         /* PCH SDVOB multiplex with HDMIB */
7948                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7949                         if (!found)
7950                                 intel_hdmi_init(dev, HDMIB);
7951                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7952                                 intel_dp_init(dev, PCH_DP_B);
7953                 }
7954
7955                 if (I915_READ(HDMIC) & PORT_DETECTED)
7956                         intel_hdmi_init(dev, HDMIC);
7957
7958                 if (I915_READ(HDMID) & PORT_DETECTED)
7959                         intel_hdmi_init(dev, HDMID);
7960
7961                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7962                         intel_dp_init(dev, PCH_DP_C);
7963
7964                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7965                         intel_dp_init(dev, PCH_DP_D);
7966
7967         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7968                 bool found = false;
7969
7970                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7971                         DRM_DEBUG_KMS("probing SDVOB\n");
7972                         found = intel_sdvo_init(dev, SDVOB, true);
7973                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7974                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7975                                 intel_hdmi_init(dev, SDVOB);
7976                         }
7977
7978                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7979                                 DRM_DEBUG_KMS("probing DP_B\n");
7980                                 intel_dp_init(dev, DP_B);
7981                         }
7982                 }
7983
7984                 /* Before G4X SDVOC doesn't have its own detect register */
7985
7986                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7987                         DRM_DEBUG_KMS("probing SDVOC\n");
7988                         found = intel_sdvo_init(dev, SDVOC, false);
7989                 }
7990
7991                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7992
7993                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7994                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7995                                 intel_hdmi_init(dev, SDVOC);
7996                         }
7997                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7998                                 DRM_DEBUG_KMS("probing DP_C\n");
7999                                 intel_dp_init(dev, DP_C);
8000                         }
8001                 }
8002
8003                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8004                     (I915_READ(DP_D) & DP_DETECTED)) {
8005                         DRM_DEBUG_KMS("probing DP_D\n");
8006                         intel_dp_init(dev, DP_D);
8007                 }
8008         } else if (IS_GEN2(dev))
8009                 intel_dvo_init(dev);
8010
8011         if (SUPPORTS_TV(dev))
8012                 intel_tv_init(dev);
8013
8014         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8015                 encoder->base.possible_crtcs = encoder->crtc_mask;
8016                 encoder->base.possible_clones =
8017                         intel_encoder_clones(dev, encoder->clone_mask);
8018         }
8019
8020         /* disable all the possible outputs/crtcs before entering KMS mode */
8021         drm_helper_disable_unused_functions(dev);
8022
8023         if (HAS_PCH_SPLIT(dev))
8024                 ironlake_init_pch_refclk(dev);
8025 }
8026
8027 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8028 {
8029         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8030
8031         drm_framebuffer_cleanup(fb);
8032         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8033
8034         kfree(intel_fb);
8035 }
8036
8037 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8038                                                 struct drm_file *file,
8039                                                 unsigned int *handle)
8040 {
8041         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8042         struct drm_i915_gem_object *obj = intel_fb->obj;
8043
8044         return drm_gem_handle_create(file, &obj->base, handle);
8045 }
8046
8047 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8048         .destroy = intel_user_framebuffer_destroy,
8049         .create_handle = intel_user_framebuffer_create_handle,
8050 };
8051
8052 int intel_framebuffer_init(struct drm_device *dev,
8053                            struct intel_framebuffer *intel_fb,
8054                            struct drm_mode_fb_cmd2 *mode_cmd,
8055                            struct drm_i915_gem_object *obj)
8056 {
8057         int ret;
8058
8059         if (obj->tiling_mode == I915_TILING_Y)
8060                 return -EINVAL;
8061
8062         if (mode_cmd->pitches[0] & 63)
8063                 return -EINVAL;
8064
8065         switch (mode_cmd->pixel_format) {
8066         case DRM_FORMAT_RGB332:
8067         case DRM_FORMAT_RGB565:
8068         case DRM_FORMAT_XRGB8888:
8069         case DRM_FORMAT_ARGB8888:
8070         case DRM_FORMAT_XRGB2101010:
8071         case DRM_FORMAT_ARGB2101010:
8072                 /* RGB formats are common across chipsets */
8073                 break;
8074         case DRM_FORMAT_YUYV:
8075         case DRM_FORMAT_UYVY:
8076         case DRM_FORMAT_YVYU:
8077         case DRM_FORMAT_VYUY:
8078                 break;
8079         default:
8080                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8081                                 mode_cmd->pixel_format);
8082                 return -EINVAL;
8083         }
8084
8085         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8086         if (ret) {
8087                 DRM_ERROR("framebuffer init failed %d\n", ret);
8088                 return ret;
8089         }
8090
8091         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8092         intel_fb->obj = obj;
8093         return 0;
8094 }
8095
8096 static struct drm_framebuffer *
8097 intel_user_framebuffer_create(struct drm_device *dev,
8098                               struct drm_file *filp,
8099                               struct drm_mode_fb_cmd2 *mode_cmd)
8100 {
8101         struct drm_i915_gem_object *obj;
8102
8103         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8104                                                 mode_cmd->handles[0]));
8105         if (&obj->base == NULL)
8106                 return ERR_PTR(-ENOENT);
8107
8108         return intel_framebuffer_create(dev, mode_cmd, obj);
8109 }
8110
8111 static const struct drm_mode_config_funcs intel_mode_funcs = {
8112         .fb_create = intel_user_framebuffer_create,
8113         .output_poll_changed = intel_fb_output_poll_changed,
8114 };
8115
8116 static struct drm_i915_gem_object *
8117 intel_alloc_context_page(struct drm_device *dev)
8118 {
8119         struct drm_i915_gem_object *ctx;
8120         int ret;
8121
8122         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8123
8124         ctx = i915_gem_alloc_object(dev, 4096);
8125         if (!ctx) {
8126                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8127                 return NULL;
8128         }
8129
8130         ret = i915_gem_object_pin(ctx, 4096, true);
8131         if (ret) {
8132                 DRM_ERROR("failed to pin power context: %d\n", ret);
8133                 goto err_unref;
8134         }
8135
8136         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8137         if (ret) {
8138                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8139                 goto err_unpin;
8140         }
8141
8142         return ctx;
8143
8144 err_unpin:
8145         i915_gem_object_unpin(ctx);
8146 err_unref:
8147         drm_gem_object_unreference(&ctx->base);
8148         mutex_unlock(&dev->struct_mutex);
8149         return NULL;
8150 }
8151
8152 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8153 {
8154         struct drm_i915_private *dev_priv = dev->dev_private;
8155         u16 rgvswctl;
8156
8157         rgvswctl = I915_READ16(MEMSWCTL);
8158         if (rgvswctl & MEMCTL_CMD_STS) {
8159                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8160                 return false; /* still busy with another command */
8161         }
8162
8163         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8164                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8165         I915_WRITE16(MEMSWCTL, rgvswctl);
8166         POSTING_READ16(MEMSWCTL);
8167
8168         rgvswctl |= MEMCTL_CMD_STS;
8169         I915_WRITE16(MEMSWCTL, rgvswctl);
8170
8171         return true;
8172 }
8173
8174 void ironlake_enable_drps(struct drm_device *dev)
8175 {
8176         struct drm_i915_private *dev_priv = dev->dev_private;
8177         u32 rgvmodectl = I915_READ(MEMMODECTL);
8178         u8 fmax, fmin, fstart, vstart;
8179
8180         /* Enable temp reporting */
8181         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8182         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8183
8184         /* 100ms RC evaluation intervals */
8185         I915_WRITE(RCUPEI, 100000);
8186         I915_WRITE(RCDNEI, 100000);
8187
8188         /* Set max/min thresholds to 90ms and 80ms respectively */
8189         I915_WRITE(RCBMAXAVG, 90000);
8190         I915_WRITE(RCBMINAVG, 80000);
8191
8192         I915_WRITE(MEMIHYST, 1);
8193
8194         /* Set up min, max, and cur for interrupt handling */
8195         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8196         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8197         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8198                 MEMMODE_FSTART_SHIFT;
8199
8200         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8201                 PXVFREQ_PX_SHIFT;
8202
8203         dev_priv->fmax = fmax; /* IPS callback will increase this */
8204         dev_priv->fstart = fstart;
8205
8206         dev_priv->max_delay = fstart;
8207         dev_priv->min_delay = fmin;
8208         dev_priv->cur_delay = fstart;
8209
8210         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8211                          fmax, fmin, fstart);
8212
8213         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8214
8215         /*
8216          * Interrupts will be enabled in ironlake_irq_postinstall
8217          */
8218
8219         I915_WRITE(VIDSTART, vstart);
8220         POSTING_READ(VIDSTART);
8221
8222         rgvmodectl |= MEMMODE_SWMODE_EN;
8223         I915_WRITE(MEMMODECTL, rgvmodectl);
8224
8225         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8226                 DRM_ERROR("stuck trying to change perf mode\n");
8227         msleep(1);
8228
8229         ironlake_set_drps(dev, fstart);
8230
8231         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8232                 I915_READ(0x112e0);
8233         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8234         dev_priv->last_count2 = I915_READ(0x112f4);
8235         getrawmonotonic(&dev_priv->last_time2);
8236 }
8237
8238 void ironlake_disable_drps(struct drm_device *dev)
8239 {
8240         struct drm_i915_private *dev_priv = dev->dev_private;
8241         u16 rgvswctl = I915_READ16(MEMSWCTL);
8242
8243         /* Ack interrupts, disable EFC interrupt */
8244         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8245         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8246         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8247         I915_WRITE(DEIIR, DE_PCU_EVENT);
8248         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8249
8250         /* Go back to the starting frequency */
8251         ironlake_set_drps(dev, dev_priv->fstart);
8252         msleep(1);
8253         rgvswctl |= MEMCTL_CMD_STS;
8254         I915_WRITE(MEMSWCTL, rgvswctl);
8255         msleep(1);
8256
8257 }
8258
8259 void gen6_set_rps(struct drm_device *dev, u8 val)
8260 {
8261         struct drm_i915_private *dev_priv = dev->dev_private;
8262         u32 swreq;
8263
8264         swreq = (val & 0x3ff) << 25;
8265         I915_WRITE(GEN6_RPNSWREQ, swreq);
8266 }
8267
8268 void gen6_disable_rps(struct drm_device *dev)
8269 {
8270         struct drm_i915_private *dev_priv = dev->dev_private;
8271
8272         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8273         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8274         I915_WRITE(GEN6_PMIER, 0);
8275         /* Complete PM interrupt masking here doesn't race with the rps work
8276          * item again unmasking PM interrupts because that is using a different
8277          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8278          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8279
8280         spin_lock_irq(&dev_priv->rps_lock);
8281         dev_priv->pm_iir = 0;
8282         spin_unlock_irq(&dev_priv->rps_lock);
8283
8284         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8285 }
8286
8287 static unsigned long intel_pxfreq(u32 vidfreq)
8288 {
8289         unsigned long freq;
8290         int div = (vidfreq & 0x3f0000) >> 16;
8291         int post = (vidfreq & 0x3000) >> 12;
8292         int pre = (vidfreq & 0x7);
8293
8294         if (!pre)
8295                 return 0;
8296
8297         freq = ((div * 133333) / ((1<<post) * pre));
8298
8299         return freq;
8300 }
8301
8302 void intel_init_emon(struct drm_device *dev)
8303 {
8304         struct drm_i915_private *dev_priv = dev->dev_private;
8305         u32 lcfuse;
8306         u8 pxw[16];
8307         int i;
8308
8309         /* Disable to program */
8310         I915_WRITE(ECR, 0);
8311         POSTING_READ(ECR);
8312
8313         /* Program energy weights for various events */
8314         I915_WRITE(SDEW, 0x15040d00);
8315         I915_WRITE(CSIEW0, 0x007f0000);
8316         I915_WRITE(CSIEW1, 0x1e220004);
8317         I915_WRITE(CSIEW2, 0x04000004);
8318
8319         for (i = 0; i < 5; i++)
8320                 I915_WRITE(PEW + (i * 4), 0);
8321         for (i = 0; i < 3; i++)
8322                 I915_WRITE(DEW + (i * 4), 0);
8323
8324         /* Program P-state weights to account for frequency power adjustment */
8325         for (i = 0; i < 16; i++) {
8326                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8327                 unsigned long freq = intel_pxfreq(pxvidfreq);
8328                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8329                         PXVFREQ_PX_SHIFT;
8330                 unsigned long val;
8331
8332                 val = vid * vid;
8333                 val *= (freq / 1000);
8334                 val *= 255;
8335                 val /= (127*127*900);
8336                 if (val > 0xff)
8337                         DRM_ERROR("bad pxval: %ld\n", val);
8338                 pxw[i] = val;
8339         }
8340         /* Render standby states get 0 weight */
8341         pxw[14] = 0;
8342         pxw[15] = 0;
8343
8344         for (i = 0; i < 4; i++) {
8345                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8346                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8347                 I915_WRITE(PXW + (i * 4), val);
8348         }
8349
8350         /* Adjust magic regs to magic values (more experimental results) */
8351         I915_WRITE(OGW0, 0);
8352         I915_WRITE(OGW1, 0);
8353         I915_WRITE(EG0, 0x00007f00);
8354         I915_WRITE(EG1, 0x0000000e);
8355         I915_WRITE(EG2, 0x000e0000);
8356         I915_WRITE(EG3, 0x68000300);
8357         I915_WRITE(EG4, 0x42000000);
8358         I915_WRITE(EG5, 0x00140031);
8359         I915_WRITE(EG6, 0);
8360         I915_WRITE(EG7, 0);
8361
8362         for (i = 0; i < 8; i++)
8363                 I915_WRITE(PXWL + (i * 4), 0);
8364
8365         /* Enable PMON + select events */
8366         I915_WRITE(ECR, 0x80000019);
8367
8368         lcfuse = I915_READ(LCFUSE02);
8369
8370         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8371 }
8372
8373 static bool intel_enable_rc6(struct drm_device *dev)
8374 {
8375         /*
8376          * Respect the kernel parameter if it is set
8377          */
8378         if (i915_enable_rc6 >= 0)
8379                 return i915_enable_rc6;
8380
8381         /*
8382          * Disable RC6 on Ironlake
8383          */
8384         if (INTEL_INFO(dev)->gen == 5)
8385                 return 0;
8386
8387         /*
8388          * Disable rc6 on Sandybridge
8389          */
8390         if (INTEL_INFO(dev)->gen == 6) {
8391                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8392                 return 0;
8393         }
8394         DRM_DEBUG_DRIVER("RC6 enabled\n");
8395         return 1;
8396 }
8397
8398 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8399 {
8400         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8401         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8402         u32 pcu_mbox, rc6_mask = 0;
8403         u32 gtfifodbg;
8404         int cur_freq, min_freq, max_freq;
8405         int i;
8406
8407         /* Here begins a magic sequence of register writes to enable
8408          * auto-downclocking.
8409          *
8410          * Perhaps there might be some value in exposing these to
8411          * userspace...
8412          */
8413         I915_WRITE(GEN6_RC_STATE, 0);
8414         mutex_lock(&dev_priv->dev->struct_mutex);
8415
8416         /* Clear the DBG now so we don't confuse earlier errors */
8417         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8418                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8419                 I915_WRITE(GTFIFODBG, gtfifodbg);
8420         }
8421
8422         gen6_gt_force_wake_get(dev_priv);
8423
8424         /* disable the counters and set deterministic thresholds */
8425         I915_WRITE(GEN6_RC_CONTROL, 0);
8426
8427         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8428         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8429         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8430         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8431         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8432
8433         for (i = 0; i < I915_NUM_RINGS; i++)
8434                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8435
8436         I915_WRITE(GEN6_RC_SLEEP, 0);
8437         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8438         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8439         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8440         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8441
8442         if (intel_enable_rc6(dev_priv->dev))
8443                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8444                         GEN6_RC_CTL_RC6_ENABLE;
8445
8446         I915_WRITE(GEN6_RC_CONTROL,
8447                    rc6_mask |
8448                    GEN6_RC_CTL_EI_MODE(1) |
8449                    GEN6_RC_CTL_HW_ENABLE);
8450
8451         I915_WRITE(GEN6_RPNSWREQ,
8452                    GEN6_FREQUENCY(10) |
8453                    GEN6_OFFSET(0) |
8454                    GEN6_AGGRESSIVE_TURBO);
8455         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8456                    GEN6_FREQUENCY(12));
8457
8458         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8459         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8460                    18 << 24 |
8461                    6 << 16);
8462         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8463         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8464         I915_WRITE(GEN6_RP_UP_EI, 100000);
8465         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8466         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8467         I915_WRITE(GEN6_RP_CONTROL,
8468                    GEN6_RP_MEDIA_TURBO |
8469                    GEN6_RP_MEDIA_HW_MODE |
8470                    GEN6_RP_MEDIA_IS_GFX |
8471                    GEN6_RP_ENABLE |
8472                    GEN6_RP_UP_BUSY_AVG |
8473                    GEN6_RP_DOWN_IDLE_CONT);
8474
8475         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8476                      500))
8477                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8478
8479         I915_WRITE(GEN6_PCODE_DATA, 0);
8480         I915_WRITE(GEN6_PCODE_MAILBOX,
8481                    GEN6_PCODE_READY |
8482                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8483         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8484                      500))
8485                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8486
8487         min_freq = (rp_state_cap & 0xff0000) >> 16;
8488         max_freq = rp_state_cap & 0xff;
8489         cur_freq = (gt_perf_status & 0xff00) >> 8;
8490
8491         /* Check for overclock support */
8492         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8493                      500))
8494                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8495         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8496         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8497         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8498                      500))
8499                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8500         if (pcu_mbox & (1<<31)) { /* OC supported */
8501                 max_freq = pcu_mbox & 0xff;
8502                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8503         }
8504
8505         /* In units of 100MHz */
8506         dev_priv->max_delay = max_freq;
8507         dev_priv->min_delay = min_freq;
8508         dev_priv->cur_delay = cur_freq;
8509
8510         /* requires MSI enabled */
8511         I915_WRITE(GEN6_PMIER,
8512                    GEN6_PM_MBOX_EVENT |
8513                    GEN6_PM_THERMAL_EVENT |
8514                    GEN6_PM_RP_DOWN_TIMEOUT |
8515                    GEN6_PM_RP_UP_THRESHOLD |
8516                    GEN6_PM_RP_DOWN_THRESHOLD |
8517                    GEN6_PM_RP_UP_EI_EXPIRED |
8518                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8519         spin_lock_irq(&dev_priv->rps_lock);
8520         WARN_ON(dev_priv->pm_iir != 0);
8521         I915_WRITE(GEN6_PMIMR, 0);
8522         spin_unlock_irq(&dev_priv->rps_lock);
8523         /* enable all PM interrupts */
8524         I915_WRITE(GEN6_PMINTRMSK, 0);
8525
8526         gen6_gt_force_wake_put(dev_priv);
8527         mutex_unlock(&dev_priv->dev->struct_mutex);
8528 }
8529
8530 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8531 {
8532         int min_freq = 15;
8533         int gpu_freq, ia_freq, max_ia_freq;
8534         int scaling_factor = 180;
8535
8536         max_ia_freq = cpufreq_quick_get_max(0);
8537         /*
8538          * Default to measured freq if none found, PCU will ensure we don't go
8539          * over
8540          */
8541         if (!max_ia_freq)
8542                 max_ia_freq = tsc_khz;
8543
8544         /* Convert from kHz to MHz */
8545         max_ia_freq /= 1000;
8546
8547         mutex_lock(&dev_priv->dev->struct_mutex);
8548
8549         /*
8550          * For each potential GPU frequency, load a ring frequency we'd like
8551          * to use for memory access.  We do this by specifying the IA frequency
8552          * the PCU should use as a reference to determine the ring frequency.
8553          */
8554         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8555              gpu_freq--) {
8556                 int diff = dev_priv->max_delay - gpu_freq;
8557
8558                 /*
8559                  * For GPU frequencies less than 750MHz, just use the lowest
8560                  * ring freq.
8561                  */
8562                 if (gpu_freq < min_freq)
8563                         ia_freq = 800;
8564                 else
8565                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8566                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8567
8568                 I915_WRITE(GEN6_PCODE_DATA,
8569                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8570                            gpu_freq);
8571                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8572                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8573                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8574                               GEN6_PCODE_READY) == 0, 10)) {
8575                         DRM_ERROR("pcode write of freq table timed out\n");
8576                         continue;
8577                 }
8578         }
8579
8580         mutex_unlock(&dev_priv->dev->struct_mutex);
8581 }
8582
8583 static void ironlake_init_clock_gating(struct drm_device *dev)
8584 {
8585         struct drm_i915_private *dev_priv = dev->dev_private;
8586         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8587
8588         /* Required for FBC */
8589         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8590                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8591                 DPFDUNIT_CLOCK_GATE_DISABLE;
8592         /* Required for CxSR */
8593         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8594
8595         I915_WRITE(PCH_3DCGDIS0,
8596                    MARIUNIT_CLOCK_GATE_DISABLE |
8597                    SVSMUNIT_CLOCK_GATE_DISABLE);
8598         I915_WRITE(PCH_3DCGDIS1,
8599                    VFMUNIT_CLOCK_GATE_DISABLE);
8600
8601         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8602
8603         /*
8604          * According to the spec the following bits should be set in
8605          * order to enable memory self-refresh
8606          * The bit 22/21 of 0x42004
8607          * The bit 5 of 0x42020
8608          * The bit 15 of 0x45000
8609          */
8610         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8611                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8612                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8613         I915_WRITE(ILK_DSPCLK_GATE,
8614                    (I915_READ(ILK_DSPCLK_GATE) |
8615                     ILK_DPARB_CLK_GATE));
8616         I915_WRITE(DISP_ARB_CTL,
8617                    (I915_READ(DISP_ARB_CTL) |
8618                     DISP_FBC_WM_DIS));
8619         I915_WRITE(WM3_LP_ILK, 0);
8620         I915_WRITE(WM2_LP_ILK, 0);
8621         I915_WRITE(WM1_LP_ILK, 0);
8622
8623         /*
8624          * Based on the document from hardware guys the following bits
8625          * should be set unconditionally in order to enable FBC.
8626          * The bit 22 of 0x42000
8627          * The bit 22 of 0x42004
8628          * The bit 7,8,9 of 0x42020.
8629          */
8630         if (IS_IRONLAKE_M(dev)) {
8631                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8632                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8633                            ILK_FBCQ_DIS);
8634                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8635                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8636                            ILK_DPARB_GATE);
8637                 I915_WRITE(ILK_DSPCLK_GATE,
8638                            I915_READ(ILK_DSPCLK_GATE) |
8639                            ILK_DPFC_DIS1 |
8640                            ILK_DPFC_DIS2 |
8641                            ILK_CLK_FBC);
8642         }
8643
8644         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8645                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8646                    ILK_ELPIN_409_SELECT);
8647         I915_WRITE(_3D_CHICKEN2,
8648                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8649                    _3D_CHICKEN2_WM_READ_PIPELINED);
8650 }
8651
8652 static void gen6_init_clock_gating(struct drm_device *dev)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         int pipe;
8656         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8657
8658         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8659
8660         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8661                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8662                    ILK_ELPIN_409_SELECT);
8663
8664         I915_WRITE(WM3_LP_ILK, 0);
8665         I915_WRITE(WM2_LP_ILK, 0);
8666         I915_WRITE(WM1_LP_ILK, 0);
8667
8668         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8669          * gating disable must be set.  Failure to set it results in
8670          * flickering pixels due to Z write ordering failures after
8671          * some amount of runtime in the Mesa "fire" demo, and Unigine
8672          * Sanctuary and Tropics, and apparently anything else with
8673          * alpha test or pixel discard.
8674          *
8675          * According to the spec, bit 11 (RCCUNIT) must also be set,
8676          * but we didn't debug actual testcases to find it out.
8677          */
8678         I915_WRITE(GEN6_UCGCTL2,
8679                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8680                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8681
8682         /*
8683          * According to the spec the following bits should be
8684          * set in order to enable memory self-refresh and fbc:
8685          * The bit21 and bit22 of 0x42000
8686          * The bit21 and bit22 of 0x42004
8687          * The bit5 and bit7 of 0x42020
8688          * The bit14 of 0x70180
8689          * The bit14 of 0x71180
8690          */
8691         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8692                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8693                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8694         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8695                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8696                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8697         I915_WRITE(ILK_DSPCLK_GATE,
8698                    I915_READ(ILK_DSPCLK_GATE) |
8699                    ILK_DPARB_CLK_GATE  |
8700                    ILK_DPFD_CLK_GATE);
8701
8702         for_each_pipe(pipe) {
8703                 I915_WRITE(DSPCNTR(pipe),
8704                            I915_READ(DSPCNTR(pipe)) |
8705                            DISPPLANE_TRICKLE_FEED_DISABLE);
8706                 intel_flush_display_plane(dev_priv, pipe);
8707         }
8708 }
8709
8710 static void ivybridge_init_clock_gating(struct drm_device *dev)
8711 {
8712         struct drm_i915_private *dev_priv = dev->dev_private;
8713         int pipe;
8714         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8715
8716         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8717
8718         I915_WRITE(WM3_LP_ILK, 0);
8719         I915_WRITE(WM2_LP_ILK, 0);
8720         I915_WRITE(WM1_LP_ILK, 0);
8721
8722         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8723
8724         I915_WRITE(IVB_CHICKEN3,
8725                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8726                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8727
8728         for_each_pipe(pipe) {
8729                 I915_WRITE(DSPCNTR(pipe),
8730                            I915_READ(DSPCNTR(pipe)) |
8731                            DISPPLANE_TRICKLE_FEED_DISABLE);
8732                 intel_flush_display_plane(dev_priv, pipe);
8733         }
8734 }
8735
8736 static void g4x_init_clock_gating(struct drm_device *dev)
8737 {
8738         struct drm_i915_private *dev_priv = dev->dev_private;
8739         uint32_t dspclk_gate;
8740
8741         I915_WRITE(RENCLK_GATE_D1, 0);
8742         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8743                    GS_UNIT_CLOCK_GATE_DISABLE |
8744                    CL_UNIT_CLOCK_GATE_DISABLE);
8745         I915_WRITE(RAMCLK_GATE_D, 0);
8746         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8747                 OVRUNIT_CLOCK_GATE_DISABLE |
8748                 OVCUNIT_CLOCK_GATE_DISABLE;
8749         if (IS_GM45(dev))
8750                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8751         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8752 }
8753
8754 static void crestline_init_clock_gating(struct drm_device *dev)
8755 {
8756         struct drm_i915_private *dev_priv = dev->dev_private;
8757
8758         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8759         I915_WRITE(RENCLK_GATE_D2, 0);
8760         I915_WRITE(DSPCLK_GATE_D, 0);
8761         I915_WRITE(RAMCLK_GATE_D, 0);
8762         I915_WRITE16(DEUC, 0);
8763 }
8764
8765 static void broadwater_init_clock_gating(struct drm_device *dev)
8766 {
8767         struct drm_i915_private *dev_priv = dev->dev_private;
8768
8769         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8770                    I965_RCC_CLOCK_GATE_DISABLE |
8771                    I965_RCPB_CLOCK_GATE_DISABLE |
8772                    I965_ISC_CLOCK_GATE_DISABLE |
8773                    I965_FBC_CLOCK_GATE_DISABLE);
8774         I915_WRITE(RENCLK_GATE_D2, 0);
8775 }
8776
8777 static void gen3_init_clock_gating(struct drm_device *dev)
8778 {
8779         struct drm_i915_private *dev_priv = dev->dev_private;
8780         u32 dstate = I915_READ(D_STATE);
8781
8782         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8783                 DSTATE_DOT_CLOCK_GATING;
8784         I915_WRITE(D_STATE, dstate);
8785 }
8786
8787 static void i85x_init_clock_gating(struct drm_device *dev)
8788 {
8789         struct drm_i915_private *dev_priv = dev->dev_private;
8790
8791         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8792 }
8793
8794 static void i830_init_clock_gating(struct drm_device *dev)
8795 {
8796         struct drm_i915_private *dev_priv = dev->dev_private;
8797
8798         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8799 }
8800
8801 static void ibx_init_clock_gating(struct drm_device *dev)
8802 {
8803         struct drm_i915_private *dev_priv = dev->dev_private;
8804
8805         /*
8806          * On Ibex Peak and Cougar Point, we need to disable clock
8807          * gating for the panel power sequencer or it will fail to
8808          * start up when no ports are active.
8809          */
8810         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8811 }
8812
8813 static void cpt_init_clock_gating(struct drm_device *dev)
8814 {
8815         struct drm_i915_private *dev_priv = dev->dev_private;
8816         int pipe;
8817
8818         /*
8819          * On Ibex Peak and Cougar Point, we need to disable clock
8820          * gating for the panel power sequencer or it will fail to
8821          * start up when no ports are active.
8822          */
8823         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8824         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8825                    DPLS_EDP_PPS_FIX_DIS);
8826         /* Without this, mode sets may fail silently on FDI */
8827         for_each_pipe(pipe)
8828                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8829 }
8830
8831 static void ironlake_teardown_rc6(struct drm_device *dev)
8832 {
8833         struct drm_i915_private *dev_priv = dev->dev_private;
8834
8835         if (dev_priv->renderctx) {
8836                 i915_gem_object_unpin(dev_priv->renderctx);
8837                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8838                 dev_priv->renderctx = NULL;
8839         }
8840
8841         if (dev_priv->pwrctx) {
8842                 i915_gem_object_unpin(dev_priv->pwrctx);
8843                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8844                 dev_priv->pwrctx = NULL;
8845         }
8846 }
8847
8848 static void ironlake_disable_rc6(struct drm_device *dev)
8849 {
8850         struct drm_i915_private *dev_priv = dev->dev_private;
8851
8852         if (I915_READ(PWRCTXA)) {
8853                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8854                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8855                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8856                          50);
8857
8858                 I915_WRITE(PWRCTXA, 0);
8859                 POSTING_READ(PWRCTXA);
8860
8861                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8862                 POSTING_READ(RSTDBYCTL);
8863         }
8864
8865         ironlake_teardown_rc6(dev);
8866 }
8867
8868 static int ironlake_setup_rc6(struct drm_device *dev)
8869 {
8870         struct drm_i915_private *dev_priv = dev->dev_private;
8871
8872         if (dev_priv->renderctx == NULL)
8873                 dev_priv->renderctx = intel_alloc_context_page(dev);
8874         if (!dev_priv->renderctx)
8875                 return -ENOMEM;
8876
8877         if (dev_priv->pwrctx == NULL)
8878                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8879         if (!dev_priv->pwrctx) {
8880                 ironlake_teardown_rc6(dev);
8881                 return -ENOMEM;
8882         }
8883
8884         return 0;
8885 }
8886
8887 void ironlake_enable_rc6(struct drm_device *dev)
8888 {
8889         struct drm_i915_private *dev_priv = dev->dev_private;
8890         int ret;
8891
8892         /* rc6 disabled by default due to repeated reports of hanging during
8893          * boot and resume.
8894          */
8895         if (!intel_enable_rc6(dev))
8896                 return;
8897
8898         mutex_lock(&dev->struct_mutex);
8899         ret = ironlake_setup_rc6(dev);
8900         if (ret) {
8901                 mutex_unlock(&dev->struct_mutex);
8902                 return;
8903         }
8904
8905         /*
8906          * GPU can automatically power down the render unit if given a page
8907          * to save state.
8908          */
8909         ret = BEGIN_LP_RING(6);
8910         if (ret) {
8911                 ironlake_teardown_rc6(dev);
8912                 mutex_unlock(&dev->struct_mutex);
8913                 return;
8914         }
8915
8916         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8917         OUT_RING(MI_SET_CONTEXT);
8918         OUT_RING(dev_priv->renderctx->gtt_offset |
8919                  MI_MM_SPACE_GTT |
8920                  MI_SAVE_EXT_STATE_EN |
8921                  MI_RESTORE_EXT_STATE_EN |
8922                  MI_RESTORE_INHIBIT);
8923         OUT_RING(MI_SUSPEND_FLUSH);
8924         OUT_RING(MI_NOOP);
8925         OUT_RING(MI_FLUSH);
8926         ADVANCE_LP_RING();
8927
8928         /*
8929          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8930          * does an implicit flush, combined with MI_FLUSH above, it should be
8931          * safe to assume that renderctx is valid
8932          */
8933         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8934         if (ret) {
8935                 DRM_ERROR("failed to enable ironlake power power savings\n");
8936                 ironlake_teardown_rc6(dev);
8937                 mutex_unlock(&dev->struct_mutex);
8938                 return;
8939         }
8940
8941         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8942         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8943         mutex_unlock(&dev->struct_mutex);
8944 }
8945
8946 void intel_init_clock_gating(struct drm_device *dev)
8947 {
8948         struct drm_i915_private *dev_priv = dev->dev_private;
8949
8950         dev_priv->display.init_clock_gating(dev);
8951
8952         if (dev_priv->display.init_pch_clock_gating)
8953                 dev_priv->display.init_pch_clock_gating(dev);
8954 }
8955
8956 /* Set up chip specific display functions */
8957 static void intel_init_display(struct drm_device *dev)
8958 {
8959         struct drm_i915_private *dev_priv = dev->dev_private;
8960
8961         /* We always want a DPMS function */
8962         if (HAS_PCH_SPLIT(dev)) {
8963                 dev_priv->display.dpms = ironlake_crtc_dpms;
8964                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8965                 dev_priv->display.update_plane = ironlake_update_plane;
8966         } else {
8967                 dev_priv->display.dpms = i9xx_crtc_dpms;
8968                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8969                 dev_priv->display.update_plane = i9xx_update_plane;
8970         }
8971
8972         if (I915_HAS_FBC(dev)) {
8973                 if (HAS_PCH_SPLIT(dev)) {
8974                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8975                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8976                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8977                 } else if (IS_GM45(dev)) {
8978                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8979                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8980                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8981                 } else if (IS_CRESTLINE(dev)) {
8982                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8983                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8984                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8985                 }
8986                 /* 855GM needs testing */
8987         }
8988
8989         /* Returns the core display clock speed */
8990         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8991                 dev_priv->display.get_display_clock_speed =
8992                         i945_get_display_clock_speed;
8993         else if (IS_I915G(dev))
8994                 dev_priv->display.get_display_clock_speed =
8995                         i915_get_display_clock_speed;
8996         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8997                 dev_priv->display.get_display_clock_speed =
8998                         i9xx_misc_get_display_clock_speed;
8999         else if (IS_I915GM(dev))
9000                 dev_priv->display.get_display_clock_speed =
9001                         i915gm_get_display_clock_speed;
9002         else if (IS_I865G(dev))
9003                 dev_priv->display.get_display_clock_speed =
9004                         i865_get_display_clock_speed;
9005         else if (IS_I85X(dev))
9006                 dev_priv->display.get_display_clock_speed =
9007                         i855_get_display_clock_speed;
9008         else /* 852, 830 */
9009                 dev_priv->display.get_display_clock_speed =
9010                         i830_get_display_clock_speed;
9011
9012         /* For FIFO watermark updates */
9013         if (HAS_PCH_SPLIT(dev)) {
9014                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9015                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9016
9017                 /* IVB configs may use multi-threaded forcewake */
9018                 if (IS_IVYBRIDGE(dev)) {
9019                         u32     ecobus;
9020
9021                         /* A small trick here - if the bios hasn't configured MT forcewake,
9022                          * and if the device is in RC6, then force_wake_mt_get will not wake
9023                          * the device and the ECOBUS read will return zero. Which will be
9024                          * (correctly) interpreted by the test below as MT forcewake being
9025                          * disabled.
9026                          */
9027                         mutex_lock(&dev->struct_mutex);
9028                         __gen6_gt_force_wake_mt_get(dev_priv);
9029                         ecobus = I915_READ_NOTRACE(ECOBUS);
9030                         __gen6_gt_force_wake_mt_put(dev_priv);
9031                         mutex_unlock(&dev->struct_mutex);
9032
9033                         if (ecobus & FORCEWAKE_MT_ENABLE) {
9034                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9035                                 dev_priv->display.force_wake_get =
9036                                         __gen6_gt_force_wake_mt_get;
9037                                 dev_priv->display.force_wake_put =
9038                                         __gen6_gt_force_wake_mt_put;
9039                         }
9040                 }
9041
9042                 if (HAS_PCH_IBX(dev))
9043                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9044                 else if (HAS_PCH_CPT(dev))
9045                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9046
9047                 if (IS_GEN5(dev)) {
9048                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9049                                 dev_priv->display.update_wm = ironlake_update_wm;
9050                         else {
9051                                 DRM_DEBUG_KMS("Failed to get proper latency. "
9052                                               "Disable CxSR\n");
9053                                 dev_priv->display.update_wm = NULL;
9054                         }
9055                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9056                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
9057                         dev_priv->display.write_eld = ironlake_write_eld;
9058                 } else if (IS_GEN6(dev)) {
9059                         if (SNB_READ_WM0_LATENCY()) {
9060                                 dev_priv->display.update_wm = sandybridge_update_wm;
9061                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9062                         } else {
9063                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9064                                               "Disable CxSR\n");
9065                                 dev_priv->display.update_wm = NULL;
9066                         }
9067                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9068                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9069                         dev_priv->display.write_eld = ironlake_write_eld;
9070                 } else if (IS_IVYBRIDGE(dev)) {
9071                         /* FIXME: detect B0+ stepping and use auto training */
9072                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9073                         if (SNB_READ_WM0_LATENCY()) {
9074                                 dev_priv->display.update_wm = sandybridge_update_wm;
9075                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9076                         } else {
9077                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9078                                               "Disable CxSR\n");
9079                                 dev_priv->display.update_wm = NULL;
9080                         }
9081                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9082                         dev_priv->display.write_eld = ironlake_write_eld;
9083                 } else
9084                         dev_priv->display.update_wm = NULL;
9085         } else if (IS_VALLEYVIEW(dev)) {
9086                 dev_priv->display.update_wm = valleyview_update_wm;
9087         } else if (IS_PINEVIEW(dev)) {
9088                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9089                                             dev_priv->is_ddr3,
9090                                             dev_priv->fsb_freq,
9091                                             dev_priv->mem_freq)) {
9092                         DRM_INFO("failed to find known CxSR latency "
9093                                  "(found ddr%s fsb freq %d, mem freq %d), "
9094                                  "disabling CxSR\n",
9095                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9096                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9097                         /* Disable CxSR and never update its watermark again */
9098                         pineview_disable_cxsr(dev);
9099                         dev_priv->display.update_wm = NULL;
9100                 } else
9101                         dev_priv->display.update_wm = pineview_update_wm;
9102                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9103         } else if (IS_G4X(dev)) {
9104                 dev_priv->display.write_eld = g4x_write_eld;
9105                 dev_priv->display.update_wm = g4x_update_wm;
9106                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9107         } else if (IS_GEN4(dev)) {
9108                 dev_priv->display.update_wm = i965_update_wm;
9109                 if (IS_CRESTLINE(dev))
9110                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9111                 else if (IS_BROADWATER(dev))
9112                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9113         } else if (IS_GEN3(dev)) {
9114                 dev_priv->display.update_wm = i9xx_update_wm;
9115                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9116                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9117         } else if (IS_I865G(dev)) {
9118                 dev_priv->display.update_wm = i830_update_wm;
9119                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9120                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9121         } else if (IS_I85X(dev)) {
9122                 dev_priv->display.update_wm = i9xx_update_wm;
9123                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9124                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9125         } else {
9126                 dev_priv->display.update_wm = i830_update_wm;
9127                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9128                 if (IS_845G(dev))
9129                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9130                 else
9131                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9132         }
9133
9134         /* Default just returns -ENODEV to indicate unsupported */
9135         dev_priv->display.queue_flip = intel_default_queue_flip;
9136
9137         switch (INTEL_INFO(dev)->gen) {
9138         case 2:
9139                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9140                 break;
9141
9142         case 3:
9143                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9144                 break;
9145
9146         case 4:
9147         case 5:
9148                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9149                 break;
9150
9151         case 6:
9152                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9153                 break;
9154         case 7:
9155                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9156                 break;
9157         }
9158 }
9159
9160 /*
9161  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9162  * resume, or other times.  This quirk makes sure that's the case for
9163  * affected systems.
9164  */
9165 static void quirk_pipea_force(struct drm_device *dev)
9166 {
9167         struct drm_i915_private *dev_priv = dev->dev_private;
9168
9169         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9170         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9171 }
9172
9173 /*
9174  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9175  */
9176 static void quirk_ssc_force_disable(struct drm_device *dev)
9177 {
9178         struct drm_i915_private *dev_priv = dev->dev_private;
9179         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9180 }
9181
9182 /*
9183  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9184  * brightness value
9185  */
9186 static void quirk_invert_brightness(struct drm_device *dev)
9187 {
9188         struct drm_i915_private *dev_priv = dev->dev_private;
9189         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9190 }
9191
9192 struct intel_quirk {
9193         int device;
9194         int subsystem_vendor;
9195         int subsystem_device;
9196         void (*hook)(struct drm_device *dev);
9197 };
9198
9199 struct intel_quirk intel_quirks[] = {
9200         /* HP Mini needs pipe A force quirk (LP: #322104) */
9201         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9202
9203         /* Thinkpad R31 needs pipe A force quirk */
9204         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9205         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9206         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9207
9208         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9209         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9210         /* ThinkPad X40 needs pipe A force quirk */
9211
9212         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9213         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9214
9215         /* 855 & before need to leave pipe A & dpll A up */
9216         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9217         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9218
9219         /* Lenovo U160 cannot use SSC on LVDS */
9220         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9221
9222         /* Sony Vaio Y cannot use SSC on LVDS */
9223         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9224
9225         /* Acer Aspire 5734Z must invert backlight brightness */
9226         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9227 };
9228
9229 static void intel_init_quirks(struct drm_device *dev)
9230 {
9231         struct pci_dev *d = dev->pdev;
9232         int i;
9233
9234         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9235                 struct intel_quirk *q = &intel_quirks[i];
9236
9237                 if (d->device == q->device &&
9238                     (d->subsystem_vendor == q->subsystem_vendor ||
9239                      q->subsystem_vendor == PCI_ANY_ID) &&
9240                     (d->subsystem_device == q->subsystem_device ||
9241                      q->subsystem_device == PCI_ANY_ID))
9242                         q->hook(dev);
9243         }
9244 }
9245
9246 /* Disable the VGA plane that we never use */
9247 static void i915_disable_vga(struct drm_device *dev)
9248 {
9249         struct drm_i915_private *dev_priv = dev->dev_private;
9250         u8 sr1;
9251         u32 vga_reg;
9252
9253         if (HAS_PCH_SPLIT(dev))
9254                 vga_reg = CPU_VGACNTRL;
9255         else
9256                 vga_reg = VGACNTRL;
9257
9258         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9259         outb(1, VGA_SR_INDEX);
9260         sr1 = inb(VGA_SR_DATA);
9261         outb(sr1 | 1<<5, VGA_SR_DATA);
9262         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9263         udelay(300);
9264
9265         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9266         POSTING_READ(vga_reg);
9267 }
9268
9269 void intel_modeset_init(struct drm_device *dev)
9270 {
9271         struct drm_i915_private *dev_priv = dev->dev_private;
9272         int i, ret;
9273
9274         drm_mode_config_init(dev);
9275
9276         dev->mode_config.min_width = 0;
9277         dev->mode_config.min_height = 0;
9278
9279         dev->mode_config.preferred_depth = 24;
9280         dev->mode_config.prefer_shadow = 1;
9281
9282         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9283
9284         intel_init_quirks(dev);
9285
9286         intel_init_display(dev);
9287
9288         if (IS_GEN2(dev)) {
9289                 dev->mode_config.max_width = 2048;
9290                 dev->mode_config.max_height = 2048;
9291         } else if (IS_GEN3(dev)) {
9292                 dev->mode_config.max_width = 4096;
9293                 dev->mode_config.max_height = 4096;
9294         } else {
9295                 dev->mode_config.max_width = 8192;
9296                 dev->mode_config.max_height = 8192;
9297         }
9298         dev->mode_config.fb_base = dev->agp->base;
9299
9300         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9301                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9302
9303         for (i = 0; i < dev_priv->num_pipe; i++) {
9304                 intel_crtc_init(dev, i);
9305                 ret = intel_plane_init(dev, i);
9306                 if (ret)
9307                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9308         }
9309
9310         /* Just disable it once at startup */
9311         i915_disable_vga(dev);
9312         intel_setup_outputs(dev);
9313
9314         intel_init_clock_gating(dev);
9315
9316         if (IS_IRONLAKE_M(dev)) {
9317                 ironlake_enable_drps(dev);
9318                 intel_init_emon(dev);
9319         }
9320
9321         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9322                 gen6_enable_rps(dev_priv);
9323                 gen6_update_ring_freq(dev_priv);
9324         }
9325
9326         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9327         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9328                     (unsigned long)dev);
9329 }
9330
9331 void intel_modeset_gem_init(struct drm_device *dev)
9332 {
9333         if (IS_IRONLAKE_M(dev))
9334                 ironlake_enable_rc6(dev);
9335
9336         intel_setup_overlay(dev);
9337 }
9338
9339 void intel_modeset_cleanup(struct drm_device *dev)
9340 {
9341         struct drm_i915_private *dev_priv = dev->dev_private;
9342         struct drm_crtc *crtc;
9343         struct intel_crtc *intel_crtc;
9344
9345         drm_kms_helper_poll_fini(dev);
9346         mutex_lock(&dev->struct_mutex);
9347
9348         intel_unregister_dsm_handler();
9349
9350
9351         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9352                 /* Skip inactive CRTCs */
9353                 if (!crtc->fb)
9354                         continue;
9355
9356                 intel_crtc = to_intel_crtc(crtc);
9357                 intel_increase_pllclock(crtc);
9358         }
9359
9360         intel_disable_fbc(dev);
9361
9362         if (IS_IRONLAKE_M(dev))
9363                 ironlake_disable_drps(dev);
9364         if (IS_GEN6(dev) || IS_GEN7(dev))
9365                 gen6_disable_rps(dev);
9366
9367         if (IS_IRONLAKE_M(dev))
9368                 ironlake_disable_rc6(dev);
9369
9370         mutex_unlock(&dev->struct_mutex);
9371
9372         /* Disable the irq before mode object teardown, for the irq might
9373          * enqueue unpin/hotplug work. */
9374         drm_irq_uninstall(dev);
9375         cancel_work_sync(&dev_priv->hotplug_work);
9376         cancel_work_sync(&dev_priv->rps_work);
9377
9378         /* flush any delayed tasks or pending work */
9379         flush_scheduled_work();
9380
9381         /* Shut off idle work before the crtcs get freed. */
9382         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9383                 intel_crtc = to_intel_crtc(crtc);
9384                 del_timer_sync(&intel_crtc->idle_timer);
9385         }
9386         del_timer_sync(&dev_priv->idle_timer);
9387         cancel_work_sync(&dev_priv->idle_work);
9388
9389         drm_mode_config_cleanup(dev);
9390 }
9391
9392 /*
9393  * Return which encoder is currently attached for connector.
9394  */
9395 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9396 {
9397         return &intel_attached_encoder(connector)->base;
9398 }
9399
9400 void intel_connector_attach_encoder(struct intel_connector *connector,
9401                                     struct intel_encoder *encoder)
9402 {
9403         connector->encoder = encoder;
9404         drm_mode_connector_attach_encoder(&connector->base,
9405                                           &encoder->base);
9406 }
9407
9408 /*
9409  * set vga decode state - true == enable VGA decode
9410  */
9411 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9412 {
9413         struct drm_i915_private *dev_priv = dev->dev_private;
9414         u16 gmch_ctrl;
9415
9416         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9417         if (state)
9418                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9419         else
9420                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9421         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9422         return 0;
9423 }
9424
9425 #ifdef CONFIG_DEBUG_FS
9426 #include <linux/seq_file.h>
9427
9428 struct intel_display_error_state {
9429         struct intel_cursor_error_state {
9430                 u32 control;
9431                 u32 position;
9432                 u32 base;
9433                 u32 size;
9434         } cursor[2];
9435
9436         struct intel_pipe_error_state {
9437                 u32 conf;
9438                 u32 source;
9439
9440                 u32 htotal;
9441                 u32 hblank;
9442                 u32 hsync;
9443                 u32 vtotal;
9444                 u32 vblank;
9445                 u32 vsync;
9446         } pipe[2];
9447
9448         struct intel_plane_error_state {
9449                 u32 control;
9450                 u32 stride;
9451                 u32 size;
9452                 u32 pos;
9453                 u32 addr;
9454                 u32 surface;
9455                 u32 tile_offset;
9456         } plane[2];
9457 };
9458
9459 struct intel_display_error_state *
9460 intel_display_capture_error_state(struct drm_device *dev)
9461 {
9462         drm_i915_private_t *dev_priv = dev->dev_private;
9463         struct intel_display_error_state *error;
9464         int i;
9465
9466         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9467         if (error == NULL)
9468                 return NULL;
9469
9470         for (i = 0; i < 2; i++) {
9471                 error->cursor[i].control = I915_READ(CURCNTR(i));
9472                 error->cursor[i].position = I915_READ(CURPOS(i));
9473                 error->cursor[i].base = I915_READ(CURBASE(i));
9474
9475                 error->plane[i].control = I915_READ(DSPCNTR(i));
9476                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9477                 error->plane[i].size = I915_READ(DSPSIZE(i));
9478                 error->plane[i].pos = I915_READ(DSPPOS(i));
9479                 error->plane[i].addr = I915_READ(DSPADDR(i));
9480                 if (INTEL_INFO(dev)->gen >= 4) {
9481                         error->plane[i].surface = I915_READ(DSPSURF(i));
9482                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9483                 }
9484
9485                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9486                 error->pipe[i].source = I915_READ(PIPESRC(i));
9487                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9488                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9489                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9490                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9491                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9492                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9493         }
9494
9495         return error;
9496 }
9497
9498 void
9499 intel_display_print_error_state(struct seq_file *m,
9500                                 struct drm_device *dev,
9501                                 struct intel_display_error_state *error)
9502 {
9503         int i;
9504
9505         for (i = 0; i < 2; i++) {
9506                 seq_printf(m, "Pipe [%d]:\n", i);
9507                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9508                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9509                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9510                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9511                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9512                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9513                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9514                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9515
9516                 seq_printf(m, "Plane [%d]:\n", i);
9517                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9518                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9519                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9520                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9521                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9522                 if (INTEL_INFO(dev)->gen >= 4) {
9523                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9524                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9525                 }
9526
9527                 seq_printf(m, "Cursor [%d]:\n", i);
9528                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9529                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9530                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9531         }
9532 }
9533 #endif