drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_dmabuf.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct drm_device *dev,
 101                                   struct intel_framebuffer *ifb,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd,
 103                                   struct drm_i915_gem_object *obj);
 104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 108                                          struct intel_link_m_n *m_n,
 109                                          struct intel_link_m_n *m2_n2);
 110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 113 static void vlv_prepare_pll(struct intel_crtc *crtc,
 114                             const struct intel_crtc_state *pipe_config);
 115 static void chv_prepare_pll(struct intel_crtc *crtc,
 116                             const struct intel_crtc_state *pipe_config);
 117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 120         struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 617             !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 622             !IS_BROXTON(dev_priv)) {
 623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 624                         INTELPllInvalid("p out of range\n");
 625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 626                         INTELPllInvalid("m out of range\n");
 627         }
 628
 629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 630                 INTELPllInvalid("vco out of range\n");
 631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 632          * connector, etc., rather than just a single range.
 633          */
 634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 635                 INTELPllInvalid("dot out of range\n");
 636
 637         return true;
 638 }
 639
 640 static int
 641 i9xx_select_p2_div(const struct intel_limit *limit,
 642                    const struct intel_crtc_state *crtc_state,
 643                    int target)
 644 {
 645         struct drm_device *dev = crtc_state->base.crtc->dev;
 646
 647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 648                 /*
 649                  * For LVDS just rely on its current settings for dual-channel.
 650                  * We haven't figured out how to reliably set up different
 651                  * single/dual channel state, if we even can.
 652                  */
 653                 if (intel_is_dual_link_lvds(dev))
 654                         return limit->p2.p2_fast;
 655                 else
 656                         return limit->p2.p2_slow;
 657         } else {
 658                 if (target < limit->p2.dot_limit)
 659                         return limit->p2.p2_slow;
 660                 else
 661                         return limit->p2.p2_fast;
 662         }
 663 }
 664
 665 /*
 666  * Returns a set of divisors for the desired target clock with the given
 667  * refclk, or FALSE.  The returned values represent the clock equation:
 668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 669  *
 670  * Target and reference clocks are specified in kHz.
 671  *
 672  * If match_clock is provided, then best_clock P divider must match the P
 673  * divider from @match_clock used for LVDS downclocking.
 674  */
 675 static bool
 676 i9xx_find_best_dpll(const struct intel_limit *limit,
 677                     struct intel_crtc_state *crtc_state,
 678                     int target, int refclk, struct dpll *match_clock,
 679                     struct dpll *best_clock)
 680 {
 681         struct drm_device *dev = crtc_state->base.crtc->dev;
 682         struct dpll clock;
 683         int err = target;
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 688
 689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 690              clock.m1++) {
 691                 for (clock.m2 = limit->m2.min;
 692                      clock.m2 <= limit->m2.max; clock.m2++) {
 693                         if (clock.m2 >= clock.m1)
 694                                 break;
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         i9xx_calc_dpll_params(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(to_i915(dev),
 703                                                                 limit,
 704                                                                 &clock))
 705                                                 continue;
 706                                         if (match_clock &&
 707                                             clock.p != match_clock->p)
 708                                                 continue;
 709
 710                                         this_err = abs(clock.dot - target);
 711                                         if (this_err < err) {
 712                                                 *best_clock = clock;
 713                                                 err = this_err;
 714                                         }
 715                                 }
 716                         }
 717                 }
 718         }
 719
 720         return (err != target);
 721 }
 722
 723 /*
 724  * Returns a set of divisors for the desired target clock with the given
 725  * refclk, or FALSE.  The returned values represent the clock equation:
 726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 727  *
 728  * Target and reference clocks are specified in kHz.
 729  *
 730  * If match_clock is provided, then best_clock P divider must match the P
 731  * divider from @match_clock used for LVDS downclocking.
 732  */
 733 static bool
 734 pnv_find_best_dpll(const struct intel_limit *limit,
 735                    struct intel_crtc_state *crtc_state,
 736                    int target, int refclk, struct dpll *match_clock,
 737                    struct dpll *best_clock)
 738 {
 739         struct drm_device *dev = crtc_state->base.crtc->dev;
 740         struct dpll clock;
 741         int err = target;
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 748              clock.m1++) {
 749                 for (clock.m2 = limit->m2.min;
 750                      clock.m2 <= limit->m2.max; clock.m2++) {
 751                         for (clock.n = limit->n.min;
 752                              clock.n <= limit->n.max; clock.n++) {
 753                                 for (clock.p1 = limit->p1.min;
 754                                         clock.p1 <= limit->p1.max; clock.p1++) {
 755                                         int this_err;
 756
 757                                         pnv_calc_dpll_params(refclk, &clock);
 758                                         if (!intel_PLL_is_valid(to_i915(dev),
 759                                                                 limit,
 760                                                                 &clock))
 761                                                 continue;
 762                                         if (match_clock &&
 763                                             clock.p != match_clock->p)
 764                                                 continue;
 765
 766                                         this_err = abs(clock.dot - target);
 767                                         if (this_err < err) {
 768                                                 *best_clock = clock;
 769                                                 err = this_err;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return (err != target);
 777 }
 778
 779 /*
 780  * Returns a set of divisors for the desired target clock with the given
 781  * refclk, or FALSE.  The returned values represent the clock equation:
 782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 783  *
 784  * Target and reference clocks are specified in kHz.
 785  *
 786  * If match_clock is provided, then best_clock P divider must match the P
 787  * divider from @match_clock used for LVDS downclocking.
 788  */
 789 static bool
 790 g4x_find_best_dpll(const struct intel_limit *limit,
 791                    struct intel_crtc_state *crtc_state,
 792                    int target, int refclk, struct dpll *match_clock,
 793                    struct dpll *best_clock)
 794 {
 795         struct drm_device *dev = crtc_state->base.crtc->dev;
 796         struct dpll clock;
 797         int max_n;
 798         bool found = false;
 799         /* approximately equals target * 0.00585 */
 800         int err_most = (target >> 8) + (target >> 9);
 801
 802         memset(best_clock, 0, sizeof(*best_clock));
 803
 804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 805
 806         max_n = limit->n.max;
 807         /* based on hardware requirement, prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirement, prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         i9xx_calc_dpll_params(refclk, &clock);
 819                                         if (!intel_PLL_is_valid(to_i915(dev),
 820                                                                 limit,
 821                                                                 &clock))
 822                                                 continue;
 823
 824                                         this_err = abs(clock.dot - target);
 825                                         if (this_err < err_most) {
 826                                                 *best_clock = clock;
 827                                                 err_most = this_err;
 828                                                 max_n = clock.n;
 829                                                 found = true;
 830                                         }
 831                                 }
 832                         }
 833                 }
 834         }
 835         return found;
 836 }
 837
 838 /*
 839  * Check if the calculated PLL configuration is more optimal compared to the
 840  * best configuration and error found so far. Return the calculated error.
 841  */
 842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 843                                const struct dpll *calculated_clock,
 844                                const struct dpll *best_clock,
 845                                unsigned int best_error_ppm,
 846                                unsigned int *error_ppm)
 847 {
 848         /*
 849          * For CHV ignore the error and consider only the P value.
 850          * Prefer a bigger P value based on HW requirements.
 851          */
 852         if (IS_CHERRYVIEW(to_i915(dev))) {
 853                 *error_ppm = 0;
 854
 855                 return calculated_clock->p > best_clock->p;
 856         }
 857
 858         if (WARN_ON_ONCE(!target_freq))
 859                 return false;
 860
 861         *error_ppm = div_u64(1000000ULL *
 862                                 abs(target_freq - calculated_clock->dot),
 863                              target_freq);
 864         /*
 865          * Prefer a better P value over a better (smaller) error if the error
 866          * is small. Ensure this preference for future configurations too by
 867          * setting the error to 0.
 868          */
 869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 870                 *error_ppm = 0;
 871
 872                 return true;
 873         }
 874
 875         return *error_ppm + 10 < best_error_ppm;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 vlv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         struct dpll clock;
 892         unsigned int bestppm = 1000000;
 893         /* min update 19.2 MHz */
 894         int max_n = min(limit->n.max, refclk / 19200);
 895         bool found = false;
 896
 897         target *= 5; /* fast clock */
 898
 899         memset(best_clock, 0, sizeof(*best_clock));
 900
 901         /* based on hardware requirement, prefer smaller n to precision */
 902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 906                                 clock.p = clock.p1 * clock.p2;
 907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 909                                         unsigned int ppm;
 910
 911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 912                                                                      refclk * clock.m1);
 913
 914                                         vlv_calc_dpll_params(refclk, &clock);
 915
 916                                         if (!intel_PLL_is_valid(to_i915(dev),
 917                                                                 limit,
 918                                                                 &clock))
 919                                                 continue;
 920
 921                                         if (!vlv_PLL_is_optimal(dev, target,
 922                                                                 &clock,
 923                                                                 best_clock,
 924                                                                 bestppm, &ppm))
 925                                                 continue;
 926
 927                                         *best_clock = clock;
 928                                         bestppm = ppm;
 929                                         found = true;
 930                                 }
 931                         }
 932                 }
 933         }
 934
 935         return found;
 936 }
 937
 938 /*
 939  * Returns a set of divisors for the desired target clock with the given
 940  * refclk, or FALSE.  The returned values represent the clock equation:
 941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 942  */
 943 static bool
 944 chv_find_best_dpll(const struct intel_limit *limit,
 945                    struct intel_crtc_state *crtc_state,
 946                    int target, int refclk, struct dpll *match_clock,
 947                    struct dpll *best_clock)
 948 {
 949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 950         struct drm_device *dev = crtc->base.dev;
 951         unsigned int best_error_ppm;
 952         struct dpll clock;
 953         uint64_t m2;
 954         int found = false;
 955
 956         memset(best_clock, 0, sizeof(*best_clock));
 957         best_error_ppm = 1000000;
 958
 959         /*
 960          * Based on hardware doc, the n always set to 1, and m1 always
 961          * set to 2.  If requires to support 200Mhz refclk, we need to
 962          * revisit this because n may not 1 anymore.
 963          */
 964         clock.n = 1, clock.m1 = 2;
 965         target *= 5;    /* fast clock */
 966
 967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 968                 for (clock.p2 = limit->p2.p2_fast;
 969                                 clock.p2 >= limit->p2.p2_slow;
 970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 971                         unsigned int error_ppm;
 972
 973                         clock.p = clock.p1 * clock.p2;
 974
 975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 976                                         clock.n) << 22, refclk * clock.m1);
 977
 978                         if (m2 > INT_MAX/clock.m1)
 979                                 continue;
 980
 981                         clock.m2 = m2;
 982
 983                         chv_calc_dpll_params(refclk, &clock);
 984
 985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 986                                 continue;
 987
 988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 989                                                 best_error_ppm, &error_ppm))
 990                                 continue;
 991
 992                         *best_clock = clock;
 993                         best_error_ppm = error_ppm;
 994                         found = true;
 995                 }
 996         }
 997
 998         return found;
 999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct drm_crtc *crtc)
1012 {
1013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1014
1015         /* Be paranoid as we can arrive here with only partial
1016          * state retrieved from the hardware during setup.
1017          *
1018          * We can ditch the adjusted_mode.crtc_clock check as soon
1019          * as Haswell has gained clock readout/fastboot support.
1020          *
1021          * We can ditch the crtc->primary->fb check as soon as we can
1022          * properly reconstruct framebuffers.
1023          *
1024          * FIXME: The intel_crtc->active here should be switched to
1025          * crtc->state->active once we have proper CRTC states wired up
1026          * for atomic.
1027          */
1028         return intel_crtc->active && crtc->primary->state->fb &&
1029                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1030 }
1031
1032 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1033                                              enum pipe pipe)
1034 {
1035         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1037
1038         return intel_crtc->config->cpu_transcoder;
1039 }
1040
1041 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1042 {
1043         struct drm_i915_private *dev_priv = to_i915(dev);
1044         i915_reg_t reg = PIPEDSL(pipe);
1045         u32 line1, line2;
1046         u32 line_mask;
1047
1048         if (IS_GEN2(dev))
1049                 line_mask = DSL_LINEMASK_GEN2;
1050         else
1051                 line_mask = DSL_LINEMASK_GEN3;
1052
1053         line1 = I915_READ(reg) & line_mask;
1054         msleep(5);
1055         line2 = I915_READ(reg) & line_mask;
1056
1057         return line1 == line2;
1058 }
1059
1060 /*
1061  * intel_wait_for_pipe_off - wait for pipe to turn off
1062  * @crtc: crtc whose pipe to wait for
1063  *
1064  * After disabling a pipe, we can't wait for vblank in the usual way,
1065  * spinning on the vblank interrupt status bit, since we won't actually
1066  * see an interrupt when the pipe is disabled.
1067  *
1068  * On Gen4 and above:
1069  *   wait for the pipe register state bit to turn off
1070  *
1071  * Otherwise:
1072  *   wait for the display line value to settle (it usually
1073  *   ends up stopping at the start of the next frame).
1074  *
1075  */
1076 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1077 {
1078         struct drm_device *dev = crtc->base.dev;
1079         struct drm_i915_private *dev_priv = to_i915(dev);
1080         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1081         enum pipe pipe = crtc->pipe;
1082
1083         if (INTEL_INFO(dev)->gen >= 4) {
1084                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1085
1086                 /* Wait for the Pipe State to go off */
1087                 if (intel_wait_for_register(dev_priv,
1088                                             reg, I965_PIPECONF_ACTIVE, 0,
1089                                             100))
1090                         WARN(1, "pipe_off wait timed out\n");
1091         } else {
1092                 /* Wait for the display line to settle */
1093                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1094                         WARN(1, "pipe_off wait timed out\n");
1095         }
1096 }
1097
1098 /* Only for pre-ILK configs */
1099 void assert_pll(struct drm_i915_private *dev_priv,
1100                 enum pipe pipe, bool state)
1101 {
1102         u32 val;
1103         bool cur_state;
1104
1105         val = I915_READ(DPLL(pipe));
1106         cur_state = !!(val & DPLL_VCO_ENABLE);
1107         I915_STATE_WARN(cur_state != state,
1108              "PLL state assertion failure (expected %s, current %s)\n",
1109                         onoff(state), onoff(cur_state));
1110 }
1111
1112 /* XXX: the dsi pll is shared between MIPI DSI ports */
1113 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1114 {
1115         u32 val;
1116         bool cur_state;
1117
1118         mutex_lock(&dev_priv->sb_lock);
1119         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1120         mutex_unlock(&dev_priv->sb_lock);
1121
1122         cur_state = val & DSI_PLL_VCO_EN;
1123         I915_STATE_WARN(cur_state != state,
1124              "DSI PLL state assertion failure (expected %s, current %s)\n",
1125                         onoff(state), onoff(cur_state));
1126 }
1127
1128 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1129                           enum pipe pipe, bool state)
1130 {
1131         bool cur_state;
1132         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133                                                                       pipe);
1134
1135         if (HAS_DDI(dev_priv)) {
1136                 /* DDI does not have a specific FDI_TX register */
1137                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1138                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1139         } else {
1140                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1141                 cur_state = !!(val & FDI_TX_ENABLE);
1142         }
1143         I915_STATE_WARN(cur_state != state,
1144              "FDI TX state assertion failure (expected %s, current %s)\n",
1145                         onoff(state), onoff(cur_state));
1146 }
1147 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1148 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1149
1150 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1151                           enum pipe pipe, bool state)
1152 {
1153         u32 val;
1154         bool cur_state;
1155
1156         val = I915_READ(FDI_RX_CTL(pipe));
1157         cur_state = !!(val & FDI_RX_ENABLE);
1158         I915_STATE_WARN(cur_state != state,
1159              "FDI RX state assertion failure (expected %s, current %s)\n",
1160                         onoff(state), onoff(cur_state));
1161 }
1162 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1163 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1164
1165 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         u32 val;
1169
1170         /* ILK FDI PLL is always enabled */
1171         if (IS_GEN5(dev_priv))
1172                 return;
1173
1174         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1175         if (HAS_DDI(dev_priv))
1176                 return;
1177
1178         val = I915_READ(FDI_TX_CTL(pipe));
1179         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 }
1181
1182 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1183                        enum pipe pipe, bool state)
1184 {
1185         u32 val;
1186         bool cur_state;
1187
1188         val = I915_READ(FDI_RX_CTL(pipe));
1189         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190         I915_STATE_WARN(cur_state != state,
1191              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192                         onoff(state), onoff(cur_state));
1193 }
1194
1195 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1196 {
1197         i915_reg_t pp_reg;
1198         u32 val;
1199         enum pipe panel_pipe = PIPE_A;
1200         bool locked = true;
1201
1202         if (WARN_ON(HAS_DDI(dev_priv)))
1203                 return;
1204
1205         if (HAS_PCH_SPLIT(dev_priv)) {
1206                 u32 port_sel;
1207
1208                 pp_reg = PP_CONTROL(0);
1209                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1210
1211                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1212                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1213                         panel_pipe = PIPE_B;
1214                 /* XXX: else fix for eDP */
1215         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1216                 /* presumably write lock depends on pipe, not port select */
1217                 pp_reg = PP_CONTROL(pipe);
1218                 panel_pipe = pipe;
1219         } else {
1220                 pp_reg = PP_CONTROL(0);
1221                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1222                         panel_pipe = PIPE_B;
1223         }
1224
1225         val = I915_READ(pp_reg);
1226         if (!(val & PANEL_POWER_ON) ||
1227             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1228                 locked = false;
1229
1230         I915_STATE_WARN(panel_pipe == pipe && locked,
1231              "panel assertion failure, pipe %c regs locked\n",
1232              pipe_name(pipe));
1233 }
1234
1235 static void assert_cursor(struct drm_i915_private *dev_priv,
1236                           enum pipe pipe, bool state)
1237 {
1238         bool cur_state;
1239
1240         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1241                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1242         else
1243                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1244
1245         I915_STATE_WARN(cur_state != state,
1246              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1247                         pipe_name(pipe), onoff(state), onoff(cur_state));
1248 }
1249 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1250 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1251
1252 void assert_pipe(struct drm_i915_private *dev_priv,
1253                  enum pipe pipe, bool state)
1254 {
1255         bool cur_state;
1256         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1257                                                                       pipe);
1258         enum intel_display_power_domain power_domain;
1259
1260         /* if we need the pipe quirk it must be always on */
1261         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1262             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1263                 state = true;
1264
1265         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1266         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1267                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1268                 cur_state = !!(val & PIPECONF_ENABLE);
1269
1270                 intel_display_power_put(dev_priv, power_domain);
1271         } else {
1272                 cur_state = false;
1273         }
1274
1275         I915_STATE_WARN(cur_state != state,
1276              "pipe %c assertion failure (expected %s, current %s)\n",
1277                         pipe_name(pipe), onoff(state), onoff(cur_state));
1278 }
1279
1280 static void assert_plane(struct drm_i915_private *dev_priv,
1281                          enum plane plane, bool state)
1282 {
1283         u32 val;
1284         bool cur_state;
1285
1286         val = I915_READ(DSPCNTR(plane));
1287         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1288         I915_STATE_WARN(cur_state != state,
1289              "plane %c assertion failure (expected %s, current %s)\n",
1290                         plane_name(plane), onoff(state), onoff(cur_state));
1291 }
1292
1293 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1294 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1295
1296 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1297                                    enum pipe pipe)
1298 {
1299         struct drm_device *dev = &dev_priv->drm;
1300         int i;
1301
1302         /* Primary planes are fixed to pipes on gen4+ */
1303         if (INTEL_INFO(dev)->gen >= 4) {
1304                 u32 val = I915_READ(DSPCNTR(pipe));
1305                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1306                      "plane %c assertion failure, should be disabled but not\n",
1307                      plane_name(pipe));
1308                 return;
1309         }
1310
1311         /* Need to check both planes against the pipe */
1312         for_each_pipe(dev_priv, i) {
1313                 u32 val = I915_READ(DSPCNTR(i));
1314                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1315                         DISPPLANE_SEL_PIPE_SHIFT;
1316                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1317                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1318                      plane_name(i), pipe_name(pipe));
1319         }
1320 }
1321
1322 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1323                                     enum pipe pipe)
1324 {
1325         struct drm_device *dev = &dev_priv->drm;
1326         int sprite;
1327
1328         if (INTEL_INFO(dev)->gen >= 9) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1331                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1332                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite, pipe_name(pipe));
1334                 }
1335         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1336                 for_each_sprite(dev_priv, pipe, sprite) {
1337                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1338                         I915_STATE_WARN(val & SP_ENABLE,
1339                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340                              sprite_name(pipe, sprite), pipe_name(pipe));
1341                 }
1342         } else if (INTEL_INFO(dev)->gen >= 7) {
1343                 u32 val = I915_READ(SPRCTL(pipe));
1344                 I915_STATE_WARN(val & SPRITE_ENABLE,
1345                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1346                      plane_name(pipe), pipe_name(pipe));
1347         } else if (INTEL_INFO(dev)->gen >= 5) {
1348                 u32 val = I915_READ(DVSCNTR(pipe));
1349                 I915_STATE_WARN(val & DVS_ENABLE,
1350                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351                      plane_name(pipe), pipe_name(pipe));
1352         }
1353 }
1354
1355 static void assert_vblank_disabled(struct drm_crtc *crtc)
1356 {
1357         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1358                 drm_crtc_vblank_put(crtc);
1359 }
1360
1361 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1362                                     enum pipe pipe)
1363 {
1364         u32 val;
1365         bool enabled;
1366
1367         val = I915_READ(PCH_TRANSCONF(pipe));
1368         enabled = !!(val & TRANS_ENABLE);
1369         I915_STATE_WARN(enabled,
1370              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1371              pipe_name(pipe));
1372 }
1373
1374 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1375                             enum pipe pipe, u32 port_sel, u32 val)
1376 {
1377         if ((val & DP_PORT_EN) == 0)
1378                 return false;
1379
1380         if (HAS_PCH_CPT(dev_priv)) {
1381                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1382                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383                         return false;
1384         } else if (IS_CHERRYVIEW(dev_priv)) {
1385                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386                         return false;
1387         } else {
1388                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1389                         return false;
1390         }
1391         return true;
1392 }
1393
1394 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1395                               enum pipe pipe, u32 val)
1396 {
1397         if ((val & SDVO_ENABLE) == 0)
1398                 return false;
1399
1400         if (HAS_PCH_CPT(dev_priv)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1402                         return false;
1403         } else if (IS_CHERRYVIEW(dev_priv)) {
1404                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405                         return false;
1406         } else {
1407                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1408                         return false;
1409         }
1410         return true;
1411 }
1412
1413 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1414                               enum pipe pipe, u32 val)
1415 {
1416         if ((val & LVDS_PORT_EN) == 0)
1417                 return false;
1418
1419         if (HAS_PCH_CPT(dev_priv)) {
1420                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421                         return false;
1422         } else {
1423                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1424                         return false;
1425         }
1426         return true;
1427 }
1428
1429 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1430                               enum pipe pipe, u32 val)
1431 {
1432         if ((val & ADPA_DAC_ENABLE) == 0)
1433                 return false;
1434         if (HAS_PCH_CPT(dev_priv)) {
1435                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436                         return false;
1437         } else {
1438                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1439                         return false;
1440         }
1441         return true;
1442 }
1443
1444 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1445                                    enum pipe pipe, i915_reg_t reg,
1446                                    u32 port_sel)
1447 {
1448         u32 val = I915_READ(reg);
1449         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1450              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1451              i915_mmio_reg_offset(reg), pipe_name(pipe));
1452
1453         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1454              && (val & DP_PIPEB_SELECT),
1455              "IBX PCH dp port still using transcoder B\n");
1456 }
1457
1458 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1459                                      enum pipe pipe, i915_reg_t reg)
1460 {
1461         u32 val = I915_READ(reg);
1462         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1463              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1464              i915_mmio_reg_offset(reg), pipe_name(pipe));
1465
1466         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1467              && (val & SDVO_PIPE_B_SELECT),
1468              "IBX PCH hdmi port still using transcoder B\n");
1469 }
1470
1471 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1472                                       enum pipe pipe)
1473 {
1474         u32 val;
1475
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1477         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1478         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1479
1480         val = I915_READ(PCH_ADPA);
1481         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1482              "PCH VGA enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484
1485         val = I915_READ(PCH_LVDS);
1486         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1487              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1488              pipe_name(pipe));
1489
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1491         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1492         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1493 }
1494
1495 static void _vlv_enable_pll(struct intel_crtc *crtc,
1496                             const struct intel_crtc_state *pipe_config)
1497 {
1498         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1499         enum pipe pipe = crtc->pipe;
1500
1501         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1502         POSTING_READ(DPLL(pipe));
1503         udelay(150);
1504
1505         if (intel_wait_for_register(dev_priv,
1506                                     DPLL(pipe),
1507                                     DPLL_LOCK_VLV,
1508                                     DPLL_LOCK_VLV,
1509                                     1))
1510                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1511 }
1512
1513 static void vlv_enable_pll(struct intel_crtc *crtc,
1514                            const struct intel_crtc_state *pipe_config)
1515 {
1516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1517         enum pipe pipe = crtc->pipe;
1518
1519         assert_pipe_disabled(dev_priv, pipe);
1520
1521         /* PLL is protected by panel, make sure we can write it */
1522         assert_panel_unlocked(dev_priv, pipe);
1523
1524         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1525                 _vlv_enable_pll(crtc, pipe_config);
1526
1527         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1528         POSTING_READ(DPLL_MD(pipe));
1529 }
1530
1531
1532 static void _chv_enable_pll(struct intel_crtc *crtc,
1533                             const struct intel_crtc_state *pipe_config)
1534 {
1535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536         enum pipe pipe = crtc->pipe;
1537         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1538         u32 tmp;
1539
1540         mutex_lock(&dev_priv->sb_lock);
1541
1542         /* Enable back the 10bit clock to display controller */
1543         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1544         tmp |= DPIO_DCLKP_EN;
1545         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1546
1547         mutex_unlock(&dev_priv->sb_lock);
1548
1549         /*
1550          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1551          */
1552         udelay(1);
1553
1554         /* Enable PLL */
1555         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1556
1557         /* Check PLL is locked */
1558         if (intel_wait_for_register(dev_priv,
1559                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1560                                     1))
1561                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc,
1565                            const struct intel_crtc_state *pipe_config)
1566 {
1567         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1568         enum pipe pipe = crtc->pipe;
1569
1570         assert_pipe_disabled(dev_priv, pipe);
1571
1572         /* PLL is protected by panel, make sure we can write it */
1573         assert_panel_unlocked(dev_priv, pipe);
1574
1575         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1576                 _chv_enable_pll(crtc, pipe_config);
1577
1578         if (pipe != PIPE_A) {
1579                 /*
1580                  * WaPixelRepeatModeFixForC0:chv
1581                  *
1582                  * DPLLCMD is AWOL. Use chicken bits to propagate
1583                  * the value from DPLLBMD to either pipe B or C.
1584                  */
1585                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1586                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1587                 I915_WRITE(CBR4_VLV, 0);
1588                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1589
1590                 /*
1591                  * DPLLB VGA mode also seems to cause problems.
1592                  * We should always have it disabled.
1593                  */
1594                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1595         } else {
1596                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1597                 POSTING_READ(DPLL_MD(pipe));
1598         }
1599 }
1600
1601 static int intel_num_dvo_pipes(struct drm_device *dev)
1602 {
1603         struct intel_crtc *crtc;
1604         int count = 0;
1605
1606         for_each_intel_crtc(dev, crtc) {
1607                 count += crtc->base.state->active &&
1608                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1609         }
1610
1611         return count;
1612 }
1613
1614 static void i9xx_enable_pll(struct intel_crtc *crtc)
1615 {
1616         struct drm_device *dev = crtc->base.dev;
1617         struct drm_i915_private *dev_priv = to_i915(dev);
1618         i915_reg_t reg = DPLL(crtc->pipe);
1619         u32 dpll = crtc->config->dpll_hw_state.dpll;
1620
1621         assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623         /* PLL is protected by panel, make sure we can write it */
1624         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1625                 assert_panel_unlocked(dev_priv, crtc->pipe);
1626
1627         /* Enable DVO 2x clock on both PLLs if necessary */
1628         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) {
1629                 /*
1630                  * It appears to be important that we don't enable this
1631                  * for the current pipe before otherwise configuring the
1632                  * PLL. No idea how this should be handled if multiple
1633                  * DVO outputs are enabled simultaneosly.
1634                  */
1635                 dpll |= DPLL_DVO_2X_MODE;
1636                 I915_WRITE(DPLL(!crtc->pipe),
1637                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1638         }
1639
1640         /*
1641          * Apparently we need to have VGA mode enabled prior to changing
1642          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1643          * dividers, even though the register value does change.
1644          */
1645         I915_WRITE(reg, 0);
1646
1647         I915_WRITE(reg, dpll);
1648
1649         /* Wait for the clocks to stabilize. */
1650         POSTING_READ(reg);
1651         udelay(150);
1652
1653         if (INTEL_INFO(dev)->gen >= 4) {
1654                 I915_WRITE(DPLL_MD(crtc->pipe),
1655                            crtc->config->dpll_hw_state.dpll_md);
1656         } else {
1657                 /* The pixel multiplier can only be updated once the
1658                  * DPLL is enabled and the clocks are stable.
1659                  *
1660                  * So write it again.
1661                  */
1662                 I915_WRITE(reg, dpll);
1663         }
1664
1665         /* We do this three times for luck */
1666         I915_WRITE(reg, dpll);
1667         POSTING_READ(reg);
1668         udelay(150); /* wait for warmup */
1669         I915_WRITE(reg, dpll);
1670         POSTING_READ(reg);
1671         udelay(150); /* wait for warmup */
1672         I915_WRITE(reg, dpll);
1673         POSTING_READ(reg);
1674         udelay(150); /* wait for warmup */
1675 }
1676
1677 /**
1678  * i9xx_disable_pll - disable a PLL
1679  * @dev_priv: i915 private structure
1680  * @pipe: pipe PLL to disable
1681  *
1682  * Disable the PLL for @pipe, making sure the pipe is off first.
1683  *
1684  * Note!  This is for pre-ILK only.
1685  */
1686 static void i9xx_disable_pll(struct intel_crtc *crtc)
1687 {
1688         struct drm_device *dev = crtc->base.dev;
1689         struct drm_i915_private *dev_priv = to_i915(dev);
1690         enum pipe pipe = crtc->pipe;
1691
1692         /* Disable DVO 2x clock on both PLLs if necessary */
1693         if (IS_I830(dev_priv) &&
1694             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1695             !intel_num_dvo_pipes(dev)) {
1696                 I915_WRITE(DPLL(PIPE_B),
1697                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1698                 I915_WRITE(DPLL(PIPE_A),
1699                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1700         }
1701
1702         /* Don't disable pipe or pipe PLLs if needed */
1703         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1704             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1705                 return;
1706
1707         /* Make sure the pipe isn't still relying on us */
1708         assert_pipe_disabled(dev_priv, pipe);
1709
1710         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1711         POSTING_READ(DPLL(pipe));
1712 }
1713
1714 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1715 {
1716         u32 val;
1717
1718         /* Make sure the pipe isn't still relying on us */
1719         assert_pipe_disabled(dev_priv, pipe);
1720
1721         val = DPLL_INTEGRATED_REF_CLK_VLV |
1722                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1723         if (pipe != PIPE_A)
1724                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1725
1726         I915_WRITE(DPLL(pipe), val);
1727         POSTING_READ(DPLL(pipe));
1728 }
1729
1730 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1731 {
1732         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1733         u32 val;
1734
1735         /* Make sure the pipe isn't still relying on us */
1736         assert_pipe_disabled(dev_priv, pipe);
1737
1738         val = DPLL_SSC_REF_CLK_CHV |
1739                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1740         if (pipe != PIPE_A)
1741                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1742
1743         I915_WRITE(DPLL(pipe), val);
1744         POSTING_READ(DPLL(pipe));
1745
1746         mutex_lock(&dev_priv->sb_lock);
1747
1748         /* Disable 10bit clock to display controller */
1749         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1750         val &= ~DPIO_DCLKP_EN;
1751         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1752
1753         mutex_unlock(&dev_priv->sb_lock);
1754 }
1755
1756 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1757                          struct intel_digital_port *dport,
1758                          unsigned int expected_mask)
1759 {
1760         u32 port_mask;
1761         i915_reg_t dpll_reg;
1762
1763         switch (dport->port) {
1764         case PORT_B:
1765                 port_mask = DPLL_PORTB_READY_MASK;
1766                 dpll_reg = DPLL(0);
1767                 break;
1768         case PORT_C:
1769                 port_mask = DPLL_PORTC_READY_MASK;
1770                 dpll_reg = DPLL(0);
1771                 expected_mask <<= 4;
1772                 break;
1773         case PORT_D:
1774                 port_mask = DPLL_PORTD_READY_MASK;
1775                 dpll_reg = DPIO_PHY_STATUS;
1776                 break;
1777         default:
1778                 BUG();
1779         }
1780
1781         if (intel_wait_for_register(dev_priv,
1782                                     dpll_reg, port_mask, expected_mask,
1783                                     1000))
1784                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1785                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1786 }
1787
1788 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789                                            enum pipe pipe)
1790 {
1791         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1793         i915_reg_t reg;
1794         uint32_t val, pipeconf_val;
1795
1796         /* Make sure PCH DPLL is enabled */
1797         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1798
1799         /* FDI must be feeding us bits for PCH ports */
1800         assert_fdi_tx_enabled(dev_priv, pipe);
1801         assert_fdi_rx_enabled(dev_priv, pipe);
1802
1803         if (HAS_PCH_CPT(dev_priv)) {
1804                 /* Workaround: Set the timing override bit before enabling the
1805                  * pch transcoder. */
1806                 reg = TRANS_CHICKEN2(pipe);
1807                 val = I915_READ(reg);
1808                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1809                 I915_WRITE(reg, val);
1810         }
1811
1812         reg = PCH_TRANSCONF(pipe);
1813         val = I915_READ(reg);
1814         pipeconf_val = I915_READ(PIPECONF(pipe));
1815
1816         if (HAS_PCH_IBX(dev_priv)) {
1817                 /*
1818                  * Make the BPC in transcoder be consistent with
1819                  * that in pipeconf reg. For HDMI we must use 8bpc
1820                  * here for both 8bpc and 12bpc.
1821                  */
1822                 val &= ~PIPECONF_BPC_MASK;
1823                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1824                         val |= PIPECONF_8BPC;
1825                 else
1826                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1827         }
1828
1829         val &= ~TRANS_INTERLACE_MASK;
1830         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1831                 if (HAS_PCH_IBX(dev_priv) &&
1832                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1833                         val |= TRANS_LEGACY_INTERLACED_ILK;
1834                 else
1835                         val |= TRANS_INTERLACED;
1836         else
1837                 val |= TRANS_PROGRESSIVE;
1838
1839         I915_WRITE(reg, val | TRANS_ENABLE);
1840         if (intel_wait_for_register(dev_priv,
1841                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1842                                     100))
1843                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1844 }
1845
1846 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1847                                       enum transcoder cpu_transcoder)
1848 {
1849         u32 val, pipeconf_val;
1850
1851         /* FDI must be feeding us bits for PCH ports */
1852         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1853         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1854
1855         /* Workaround: set timing override bit. */
1856         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1857         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1859
1860         val = TRANS_ENABLE;
1861         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1862
1863         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1864             PIPECONF_INTERLACED_ILK)
1865                 val |= TRANS_INTERLACED;
1866         else
1867                 val |= TRANS_PROGRESSIVE;
1868
1869         I915_WRITE(LPT_TRANSCONF, val);
1870         if (intel_wait_for_register(dev_priv,
1871                                     LPT_TRANSCONF,
1872                                     TRANS_STATE_ENABLE,
1873                                     TRANS_STATE_ENABLE,
1874                                     100))
1875                 DRM_ERROR("Failed to enable PCH transcoder\n");
1876 }
1877
1878 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1879                                             enum pipe pipe)
1880 {
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev_priv)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123         return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134         return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (intel_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185         struct drm_device *dev = fb->dev;
2186         struct drm_i915_private *dev_priv = to_i915(dev);
2187         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188         struct i915_ggtt_view view;
2189         struct i915_vma *vma;
2190         u32 alignment;
2191
2192         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196         intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198         /* Note that the w/a also requires 64 PTE of padding following the
2199          * bo. We currently fill all unused PTE with the shadow page and so
2200          * we should always have valid PTE following the scanout preventing
2201          * the VT-d warning.
2202          */
2203         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204                 alignment = 256 * 1024;
2205
2206         /*
2207          * Global gtt pte registers are special registers which actually forward
2208          * writes to a chunk of system memory. Which means that there is no risk
2209          * that the register values disappear as soon as we call
2210          * intel_runtime_pm_put(), so it is correct to wrap only the
2211          * pin/unpin/fence and not more.
2212          */
2213         intel_runtime_pm_get(dev_priv);
2214
2215         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216         if (IS_ERR(vma))
2217                 goto err;
2218
2219         if (i915_vma_is_map_and_fenceable(vma)) {
2220                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221                  * fence, whereas 965+ only requires a fence if using
2222                  * framebuffer compression.  For simplicity, we always, when
2223                  * possible, install a fence as the cost is not that onerous.
2224                  *
2225                  * If we fail to fence the tiled scanout, then either the
2226                  * modeset will reject the change (which is highly unlikely as
2227                  * the affected systems, all but one, do not have unmappable
2228                  * space) or we will not be able to enable full powersaving
2229                  * techniques (also likely not to apply due to various limits
2230                  * FBC and the like impose on the size of the buffer, which
2231                  * presumably we violated anyway with this unmappable buffer).
2232                  * Anyway, it is presumably better to stumble onwards with
2233                  * something and try to run the system in a "less than optimal"
2234                  * mode that matches the user configuration.
2235                  */
2236                 if (i915_vma_get_fence(vma) == 0)
2237                         i915_vma_pin_fence(vma);
2238         }
2239
2240 err:
2241         intel_runtime_pm_put(dev_priv);
2242         return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         struct i915_ggtt_view view;
2249         struct i915_vma *vma;
2250
2251         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254         vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256         i915_vma_unpin_fence(vma);
2257         i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261                           unsigned int rotation)
2262 {
2263         if (intel_rotation_90_or_270(rotation))
2264                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265         else
2266                 return fb->pitches[plane];
2267 }
2268
2269 /*
2270  * Convert the x/y offsets into a linear offset.
2271  * Only valid with 0/180 degree rotation, which is fine since linear
2272  * offset is only used with linear buffers on pre-hsw and tiled buffers
2273  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274  */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276                           const struct intel_plane_state *state,
2277                           int plane)
2278 {
2279         const struct drm_framebuffer *fb = state->base.fb;
2280         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281         unsigned int pitch = fb->pitches[plane];
2282
2283         return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287  * Add the x/y offsets derived from fb->offsets[] to the user
2288  * specified plane src x/y offsets. The resulting x/y offsets
2289  * specify the start of scanout from the beginning of the gtt mapping.
2290  */
2291 void intel_add_fb_offsets(int *x, int *y,
2292                           const struct intel_plane_state *state,
2293                           int plane)
2294
2295 {
2296         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297         unsigned int rotation = state->base.rotation;
2298
2299         if (intel_rotation_90_or_270(rotation)) {
2300                 *x += intel_fb->rotated[plane].x;
2301                 *y += intel_fb->rotated[plane].y;
2302         } else {
2303                 *x += intel_fb->normal[plane].x;
2304                 *y += intel_fb->normal[plane].y;
2305         }
2306 }
2307
2308 /*
2309  * Input tile dimensions and pitch must already be
2310  * rotated to match x and y, and in pixel units.
2311  */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313                                      unsigned int tile_width,
2314                                      unsigned int tile_height,
2315                                      unsigned int tile_size,
2316                                      unsigned int pitch_tiles,
2317                                      u32 old_offset,
2318                                      u32 new_offset)
2319 {
2320         unsigned int pitch_pixels = pitch_tiles * tile_width;
2321         unsigned int tiles;
2322
2323         WARN_ON(old_offset & (tile_size - 1));
2324         WARN_ON(new_offset & (tile_size - 1));
2325         WARN_ON(new_offset > old_offset);
2326
2327         tiles = (old_offset - new_offset) / tile_size;
2328
2329         *y += tiles / pitch_tiles * tile_height;
2330         *x += tiles % pitch_tiles * tile_width;
2331
2332         /* minimize x in case it got needlessly big */
2333         *y += *x / pitch_pixels * tile_height;
2334         *x %= pitch_pixels;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Adjust the tile offset by moving the difference into
2341  * the x/y offsets.
2342  */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344                                     const struct intel_plane_state *state, int plane,
2345                                     u32 old_offset, u32 new_offset)
2346 {
2347         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348         const struct drm_framebuffer *fb = state->base.fb;
2349         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350         unsigned int rotation = state->base.rotation;
2351         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353         WARN_ON(new_offset > old_offset);
2354
2355         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int pitch_tiles;
2358
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361                                 fb->modifier[plane], cpp);
2362
2363                 if (intel_rotation_90_or_270(rotation)) {
2364                         pitch_tiles = pitch / tile_height;
2365                         swap(tile_width, tile_height);
2366                 } else {
2367                         pitch_tiles = pitch / (tile_width * cpp);
2368                 }
2369
2370                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371                                           tile_size, pitch_tiles,
2372                                           old_offset, new_offset);
2373         } else {
2374                 old_offset += *y * pitch + *x * cpp;
2375
2376                 *y = (old_offset - new_offset) / pitch;
2377                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378         }
2379
2380         return new_offset;
2381 }
2382
2383 /*
2384  * Computes the linear offset to the base tile and adjusts
2385  * x, y. bytes per pixel is assumed to be a power-of-two.
2386  *
2387  * In the 90/270 rotated case, x and y are assumed
2388  * to be already rotated to match the rotated GTT view, and
2389  * pitch is the tile_height aligned framebuffer height.
2390  *
2391  * This function is used when computing the derived information
2392  * under intel_framebuffer, so using any of that information
2393  * here is not allowed. Anything under drm_framebuffer can be
2394  * used. This is why the user has to pass in the pitch since it
2395  * is specified in the rotated orientation.
2396  */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398                                       int *x, int *y,
2399                                       const struct drm_framebuffer *fb, int plane,
2400                                       unsigned int pitch,
2401                                       unsigned int rotation,
2402                                       u32 alignment)
2403 {
2404         uint64_t fb_modifier = fb->modifier[plane];
2405         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406         u32 offset, offset_aligned;
2407
2408         if (alignment)
2409                 alignment--;
2410
2411         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412                 unsigned int tile_size, tile_width, tile_height;
2413                 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415                 tile_size = intel_tile_size(dev_priv);
2416                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417                                 fb_modifier, cpp);
2418
2419                 if (intel_rotation_90_or_270(rotation)) {
2420                         pitch_tiles = pitch / tile_height;
2421                         swap(tile_width, tile_height);
2422                 } else {
2423                         pitch_tiles = pitch / (tile_width * cpp);
2424                 }
2425
2426                 tile_rows = *y / tile_height;
2427                 *y %= tile_height;
2428
2429                 tiles = *x / tile_width;
2430                 *x %= tile_width;
2431
2432                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433                 offset_aligned = offset & ~alignment;
2434
2435                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436                                           tile_size, pitch_tiles,
2437                                           offset, offset_aligned);
2438         } else {
2439                 offset = *y * pitch + *x * cpp;
2440                 offset_aligned = offset & ~alignment;
2441
2442                 *y = (offset & alignment) / pitch;
2443                 *x = ((offset & alignment) - *y * pitch) / cpp;
2444         }
2445
2446         return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450                               const struct intel_plane_state *state,
2451                               int plane)
2452 {
2453         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454         const struct drm_framebuffer *fb = state->base.fb;
2455         unsigned int rotation = state->base.rotation;
2456         int pitch = intel_fb_pitch(fb, plane, rotation);
2457         u32 alignment;
2458
2459         /* AUX_DIST needs only 4K alignment */
2460         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461                 alignment = 4096;
2462         else
2463                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466                                           rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471                                   const struct drm_framebuffer *fb, int plane)
2472 {
2473         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474         unsigned int pitch = fb->pitches[plane];
2475         u32 linear_offset = fb->offsets[plane];
2476
2477         *y = linear_offset / pitch;
2478         *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483         switch (fb_modifier) {
2484         case I915_FORMAT_MOD_X_TILED:
2485                 return I915_TILING_X;
2486         case I915_FORMAT_MOD_Y_TILED:
2487                 return I915_TILING_Y;
2488         default:
2489                 return I915_TILING_NONE;
2490         }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495                    struct drm_framebuffer *fb)
2496 {
2497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499         u32 gtt_offset_rotated = 0;
2500         unsigned int max_size = 0;
2501         uint32_t format = fb->pixel_format;
2502         int i, num_planes = drm_format_num_planes(format);
2503         unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505         for (i = 0; i < num_planes; i++) {
2506                 unsigned int width, height;
2507                 unsigned int cpp, size;
2508                 u32 offset;
2509                 int x, y;
2510
2511                 cpp = drm_format_plane_cpp(format, i);
2512                 width = drm_format_plane_width(fb->width, format, i);
2513                 height = drm_format_plane_height(fb->height, format, i);
2514
2515                 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517                 /*
2518                  * The fence (if used) is aligned to the start of the object
2519                  * so having the framebuffer wrap around across the edge of the
2520                  * fenced region doesn't really work. We have no API to configure
2521                  * the fence start offset within the object (nor could we probably
2522                  * on gen2/3). So it's just easier if we just require that the
2523                  * fb layout agrees with the fence layout. We already check that the
2524                  * fb stride matches the fence stride elsewhere.
2525                  */
2526                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527                     (x + width) * cpp > fb->pitches[i]) {
2528                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529                                   i, fb->offsets[i]);
2530                         return -EINVAL;
2531                 }
2532
2533                 /*
2534                  * First pixel of the framebuffer from
2535                  * the start of the normal gtt mapping.
2536                  */
2537                 intel_fb->normal[i].x = x;
2538                 intel_fb->normal[i].y = y;
2539
2540                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541                                                     fb, 0, fb->pitches[i],
2542                                                     DRM_ROTATE_0, tile_size);
2543                 offset /= tile_size;
2544
2545                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546                         unsigned int tile_width, tile_height;
2547                         unsigned int pitch_tiles;
2548                         struct drm_rect r;
2549
2550                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551                                         fb->modifier[i], cpp);
2552
2553                         rot_info->plane[i].offset = offset;
2554                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558                         intel_fb->rotated[i].pitch =
2559                                 rot_info->plane[i].height * tile_height;
2560
2561                         /* how many tiles does this plane need */
2562                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563                         /*
2564                          * If the plane isn't horizontally tile aligned,
2565                          * we need one more tile.
2566                          */
2567                         if (x != 0)
2568                                 size++;
2569
2570                         /* rotate the x/y offsets to match the GTT view */
2571                         r.x1 = x;
2572                         r.y1 = y;
2573                         r.x2 = x + width;
2574                         r.y2 = y + height;
2575                         drm_rect_rotate(&r,
2576                                         rot_info->plane[i].width * tile_width,
2577                                         rot_info->plane[i].height * tile_height,
2578                                         DRM_ROTATE_270);
2579                         x = r.x1;
2580                         y = r.y1;
2581
2582                         /* rotate the tile dimensions to match the GTT view */
2583                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584                         swap(tile_width, tile_height);
2585
2586                         /*
2587                          * We only keep the x/y offsets, so push all of the
2588                          * gtt offset into the x/y offsets.
2589                          */
2590                         _intel_adjust_tile_offset(&x, &y, tile_size,
2591                                                   tile_width, tile_height, pitch_tiles,
2592                                                   gtt_offset_rotated * tile_size, 0);
2593
2594                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596                         /*
2597                          * First pixel of the framebuffer from
2598                          * the start of the rotated gtt mapping.
2599                          */
2600                         intel_fb->rotated[i].x = x;
2601                         intel_fb->rotated[i].y = y;
2602                 } else {
2603                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604                                             x * cpp, tile_size);
2605                 }
2606
2607                 /* how many tiles in total needed in the bo */
2608                 max_size = max(max_size, offset + size);
2609         }
2610
2611         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614                 return -EINVAL;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622         switch (format) {
2623         case DISPPLANE_8BPP:
2624                 return DRM_FORMAT_C8;
2625         case DISPPLANE_BGRX555:
2626                 return DRM_FORMAT_XRGB1555;
2627         case DISPPLANE_BGRX565:
2628                 return DRM_FORMAT_RGB565;
2629         default:
2630         case DISPPLANE_BGRX888:
2631                 return DRM_FORMAT_XRGB8888;
2632         case DISPPLANE_RGBX888:
2633                 return DRM_FORMAT_XBGR8888;
2634         case DISPPLANE_BGRX101010:
2635                 return DRM_FORMAT_XRGB2101010;
2636         case DISPPLANE_RGBX101010:
2637                 return DRM_FORMAT_XBGR2101010;
2638         }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643         switch (format) {
2644         case PLANE_CTL_FORMAT_RGB_565:
2645                 return DRM_FORMAT_RGB565;
2646         default:
2647         case PLANE_CTL_FORMAT_XRGB_8888:
2648                 if (rgb_order) {
2649                         if (alpha)
2650                                 return DRM_FORMAT_ABGR8888;
2651                         else
2652                                 return DRM_FORMAT_XBGR8888;
2653                 } else {
2654                         if (alpha)
2655                                 return DRM_FORMAT_ARGB8888;
2656                         else
2657                                 return DRM_FORMAT_XRGB8888;
2658                 }
2659         case PLANE_CTL_FORMAT_XRGB_2101010:
2660                 if (rgb_order)
2661                         return DRM_FORMAT_XBGR2101010;
2662                 else
2663                         return DRM_FORMAT_XRGB2101010;
2664         }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669                               struct intel_initial_plane_config *plane_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674         struct drm_i915_gem_object *obj = NULL;
2675         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676         struct drm_framebuffer *fb = &plane_config->fb->base;
2677         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679                                     PAGE_SIZE);
2680
2681         size_aligned -= base_aligned;
2682
2683         if (plane_config->size == 0)
2684                 return false;
2685
2686         /* If the FB is too big, just don't use it since fbdev is not very
2687          * important and we should probably use that space with FBC or other
2688          * features. */
2689         if (size_aligned * 2 > ggtt->stolen_usable_size)
2690                 return false;
2691
2692         mutex_lock(&dev->struct_mutex);
2693
2694         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695                                                              base_aligned,
2696                                                              base_aligned,
2697                                                              size_aligned);
2698         if (!obj) {
2699                 mutex_unlock(&dev->struct_mutex);
2700                 return false;
2701         }
2702
2703         if (plane_config->tiling == I915_TILING_X)
2704                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706         mode_cmd.pixel_format = fb->pixel_format;
2707         mode_cmd.width = fb->width;
2708         mode_cmd.height = fb->height;
2709         mode_cmd.pitches[0] = fb->pitches[0];
2710         mode_cmd.modifier[0] = fb->modifier[0];
2711         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714                                    &mode_cmd, obj)) {
2715                 DRM_DEBUG_KMS("intel fb init failed\n");
2716                 goto out_unref_obj;
2717         }
2718
2719         mutex_unlock(&dev->struct_mutex);
2720
2721         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722         return true;
2723
2724 out_unref_obj:
2725         i915_gem_object_put(obj);
2726         mutex_unlock(&dev->struct_mutex);
2727         return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734         if (plane->fb == plane->state->fb)
2735                 return;
2736
2737         if (plane->state->fb)
2738                 drm_framebuffer_unreference(plane->state->fb);
2739         plane->state->fb = plane->fb;
2740         if (plane->state->fb)
2741                 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746                              struct intel_initial_plane_config *plane_config)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = to_i915(dev);
2750         struct drm_crtc *c;
2751         struct intel_crtc *i;
2752         struct drm_i915_gem_object *obj;
2753         struct drm_plane *primary = intel_crtc->base.primary;
2754         struct drm_plane_state *plane_state = primary->state;
2755         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756         struct intel_plane *intel_plane = to_intel_plane(primary);
2757         struct intel_plane_state *intel_state =
2758                 to_intel_plane_state(plane_state);
2759         struct drm_framebuffer *fb;
2760
2761         if (!plane_config->fb)
2762                 return;
2763
2764         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765                 fb = &plane_config->fb->base;
2766                 goto valid_fb;
2767         }
2768
2769         kfree(plane_config->fb);
2770
2771         /*
2772          * Failed to alloc the obj, check to see if we should share
2773          * an fb with another CRTC instead
2774          */
2775         for_each_crtc(dev, c) {
2776                 i = to_intel_crtc(c);
2777
2778                 if (c == &intel_crtc->base)
2779                         continue;
2780
2781                 if (!i->active)
2782                         continue;
2783
2784                 fb = c->primary->fb;
2785                 if (!fb)
2786                         continue;
2787
2788                 obj = intel_fb_obj(fb);
2789                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790                         drm_framebuffer_reference(fb);
2791                         goto valid_fb;
2792                 }
2793         }
2794
2795         /*
2796          * We've failed to reconstruct the BIOS FB.  Current display state
2797          * indicates that the primary plane is visible, but has a NULL FB,
2798          * which will lead to problems later if we don't fix it up.  The
2799          * simplest solution is to just disable the primary plane now and
2800          * pretend the BIOS never had it enabled.
2801          */
2802         to_intel_plane_state(plane_state)->base.visible = false;
2803         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805         intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807         return;
2808
2809 valid_fb:
2810         plane_state->src_x = 0;
2811         plane_state->src_y = 0;
2812         plane_state->src_w = fb->width << 16;
2813         plane_state->src_h = fb->height << 16;
2814
2815         plane_state->crtc_x = 0;
2816         plane_state->crtc_y = 0;
2817         plane_state->crtc_w = fb->width;
2818         plane_state->crtc_h = fb->height;
2819
2820         intel_state->base.src.x1 = plane_state->src_x;
2821         intel_state->base.src.y1 = plane_state->src_y;
2822         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824         intel_state->base.dst.x1 = plane_state->crtc_x;
2825         intel_state->base.dst.y1 = plane_state->crtc_y;
2826         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829         obj = intel_fb_obj(fb);
2830         if (i915_gem_object_is_tiled(obj))
2831                 dev_priv->preserve_bios_swizzle = true;
2832
2833         drm_framebuffer_reference(fb);
2834         primary->fb = primary->state->fb = fb;
2835         primary->crtc = primary->state->crtc = &intel_crtc->base;
2836         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838                   &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842                                unsigned int rotation)
2843 {
2844         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846         switch (fb->modifier[plane]) {
2847         case DRM_FORMAT_MOD_NONE:
2848         case I915_FORMAT_MOD_X_TILED:
2849                 switch (cpp) {
2850                 case 8:
2851                         return 4096;
2852                 case 4:
2853                 case 2:
2854                 case 1:
2855                         return 8192;
2856                 default:
2857                         MISSING_CASE(cpp);
2858                         break;
2859                 }
2860                 break;
2861         case I915_FORMAT_MOD_Y_TILED:
2862         case I915_FORMAT_MOD_Yf_TILED:
2863                 switch (cpp) {
2864                 case 8:
2865                         return 2048;
2866                 case 4:
2867                         return 4096;
2868                 case 2:
2869                 case 1:
2870                         return 8192;
2871                 default:
2872                         MISSING_CASE(cpp);
2873                         break;
2874                 }
2875                 break;
2876         default:
2877                 MISSING_CASE(fb->modifier[plane]);
2878         }
2879
2880         return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886         const struct drm_framebuffer *fb = plane_state->base.fb;
2887         unsigned int rotation = plane_state->base.rotation;
2888         int x = plane_state->base.src.x1 >> 16;
2889         int y = plane_state->base.src.y1 >> 16;
2890         int w = drm_rect_width(&plane_state->base.src) >> 16;
2891         int h = drm_rect_height(&plane_state->base.src) >> 16;
2892         int max_width = skl_max_plane_width(fb, 0, rotation);
2893         int max_height = 4096;
2894         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896         if (w > max_width || h > max_height) {
2897                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898                               w, h, max_width, max_height);
2899                 return -EINVAL;
2900         }
2901
2902         intel_add_fb_offsets(&x, &y, plane_state, 0);
2903         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907         /*
2908          * AUX surface offset is specified as the distance from the
2909          * main surface offset, and it must be non-negative. Make
2910          * sure that is what we will get.
2911          */
2912         if (offset > aux_offset)
2913                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914                                                   offset, aux_offset & ~(alignment - 1));
2915
2916         /*
2917          * When using an X-tiled surface, the plane blows up
2918          * if the x offset + width exceed the stride.
2919          *
2920          * TODO: linear and Y-tiled seem fine, Yf untested,
2921          */
2922         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925                 while ((x + w) * cpp > fb->pitches[0]) {
2926                         if (offset == 0) {
2927                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928                                 return -EINVAL;
2929                         }
2930
2931                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932                                                           offset, offset - alignment);
2933                 }
2934         }
2935
2936         plane_state->main.offset = offset;
2937         plane_state->main.x = x;
2938         plane_state->main.y = y;
2939
2940         return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945         const struct drm_framebuffer *fb = plane_state->base.fb;
2946         unsigned int rotation = plane_state->base.rotation;
2947         int max_width = skl_max_plane_width(fb, 1, rotation);
2948         int max_height = 4096;
2949         int x = plane_state->base.src.x1 >> 17;
2950         int y = plane_state->base.src.y1 >> 17;
2951         int w = drm_rect_width(&plane_state->base.src) >> 17;
2952         int h = drm_rect_height(&plane_state->base.src) >> 17;
2953         u32 offset;
2954
2955         intel_add_fb_offsets(&x, &y, plane_state, 1);
2956         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958         /* FIXME not quite sure how/if these apply to the chroma plane */
2959         if (w > max_width || h > max_height) {
2960                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961                               w, h, max_width, max_height);
2962                 return -EINVAL;
2963         }
2964
2965         plane_state->aux.offset = offset;
2966         plane_state->aux.x = x;
2967         plane_state->aux.y = y;
2968
2969         return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974         const struct drm_framebuffer *fb = plane_state->base.fb;
2975         unsigned int rotation = plane_state->base.rotation;
2976         int ret;
2977
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (intel_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width, fb->height, DRM_ROTATE_270);
2982
2983         /*
2984          * Handle the AUX surface first since
2985          * the main surface setup depends on it.
2986          */
2987         if (fb->pixel_format == DRM_FORMAT_NV12) {
2988                 ret = skl_check_nv12_aux_surface(plane_state);
2989                 if (ret)
2990                         return ret;
2991         } else {
2992                 plane_state->aux.offset = ~0xfff;
2993                 plane_state->aux.x = 0;
2994                 plane_state->aux.y = 0;
2995         }
2996
2997         ret = skl_check_main_surface(plane_state);
2998         if (ret)
2999                 return ret;
3000
3001         return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005                                       const struct intel_crtc_state *crtc_state,
3006                                       const struct intel_plane_state *plane_state)
3007 {
3008         struct drm_device *dev = primary->dev;
3009         struct drm_i915_private *dev_priv = to_i915(dev);
3010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011         struct drm_framebuffer *fb = plane_state->base.fb;
3012         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013         int plane = intel_crtc->plane;
3014         u32 linear_offset;
3015         u32 dspcntr;
3016         i915_reg_t reg = DSPCNTR(plane);
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x = plane_state->base.src.x1 >> 16;
3019         int y = plane_state->base.src.y1 >> 16;
3020
3021         dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023         dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025         if (INTEL_INFO(dev)->gen < 4) {
3026                 if (intel_crtc->pipe == PIPE_B)
3027                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029                 /* pipesrc and dspsize control the size that is scaled from,
3030                  * which should always be the user's requested size.
3031                  */
3032                 I915_WRITE(DSPSIZE(plane),
3033                            ((crtc_state->pipe_src_h - 1) << 16) |
3034                            (crtc_state->pipe_src_w - 1));
3035                 I915_WRITE(DSPPOS(plane), 0);
3036         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3037                 I915_WRITE(PRIMSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(PRIMPOS(plane), 0);
3041                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042         }
3043
3044         switch (fb->pixel_format) {
3045         case DRM_FORMAT_C8:
3046                 dspcntr |= DISPPLANE_8BPP;
3047                 break;
3048         case DRM_FORMAT_XRGB1555:
3049                 dspcntr |= DISPPLANE_BGRX555;
3050                 break;
3051         case DRM_FORMAT_RGB565:
3052                 dspcntr |= DISPPLANE_BGRX565;
3053                 break;
3054         case DRM_FORMAT_XRGB8888:
3055                 dspcntr |= DISPPLANE_BGRX888;
3056                 break;
3057         case DRM_FORMAT_XBGR8888:
3058                 dspcntr |= DISPPLANE_RGBX888;
3059                 break;
3060         case DRM_FORMAT_XRGB2101010:
3061                 dspcntr |= DISPPLANE_BGRX101010;
3062                 break;
3063         case DRM_FORMAT_XBGR2101010:
3064                 dspcntr |= DISPPLANE_RGBX101010;
3065                 break;
3066         default:
3067                 BUG();
3068         }
3069
3070         if (INTEL_GEN(dev_priv) >= 4 &&
3071             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072                 dspcntr |= DISPPLANE_TILED;
3073
3074         if (IS_G4X(dev_priv))
3075                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077         intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079         if (INTEL_INFO(dev)->gen >= 4)
3080                 intel_crtc->dspaddr_offset =
3081                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083         if (rotation == DRM_ROTATE_180) {
3084                 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086                 x += (crtc_state->pipe_src_w - 1);
3087                 y += (crtc_state->pipe_src_h - 1);
3088         }
3089
3090         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092         if (INTEL_INFO(dev)->gen < 4)
3093                 intel_crtc->dspaddr_offset = linear_offset;
3094
3095         intel_crtc->adjusted_x = x;
3096         intel_crtc->adjusted_y = y;
3097
3098         I915_WRITE(reg, dspcntr);
3099
3100         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101         if (INTEL_INFO(dev)->gen >= 4) {
3102                 I915_WRITE(DSPSURF(plane),
3103                            intel_fb_gtt_offset(fb, rotation) +
3104                            intel_crtc->dspaddr_offset);
3105                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107         } else
3108                 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3177                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179         intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181         intel_crtc->dspaddr_offset =
3182                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184         if (rotation == DRM_ROTATE_180) {
3185                 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187                 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3188                         x += (crtc_state->pipe_src_w - 1);
3189                         y += (crtc_state->pipe_src_h - 1);
3190                 }
3191         }
3192
3193         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195         intel_crtc->adjusted_x = x;
3196         intel_crtc->adjusted_y = y;
3197
3198         I915_WRITE(reg, dspcntr);
3199
3200         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201         I915_WRITE(DSPSURF(plane),
3202                    intel_fb_gtt_offset(fb, rotation) +
3203                    intel_crtc->dspaddr_offset);
3204         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3205                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206         } else {
3207                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209         }
3210         POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214                               uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217                 return 64;
3218         } else {
3219                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222         }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226                         unsigned int rotation)
3227 {
3228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229         struct i915_ggtt_view view;
3230         struct i915_vma *vma;
3231
3232         intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234         vma = i915_gem_object_to_ggtt(obj, &view);
3235         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236                  view.type))
3237                 return -1;
3238
3239         return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244         struct drm_device *dev = intel_crtc->base.dev;
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253  * This function detaches (aka. unbinds) unused scalers in hardware
3254  */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257         struct intel_crtc_scaler_state *scaler_state;
3258         int i;
3259
3260         scaler_state = &intel_crtc->config->scaler_state;
3261
3262         /* loop through and disable scalers that aren't in use */
3263         for (i = 0; i < intel_crtc->num_scalers; i++) {
3264                 if (!scaler_state->scalers[i].in_use)
3265                         skl_detach_scaler(intel_crtc, i);
3266         }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270                      unsigned int rotation)
3271 {
3272         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273         u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275         /*
3276          * The stride is either expressed as a multiple of 64 bytes chunks for
3277          * linear buffers or in number of tiles for tiled buffers.
3278          */
3279         if (intel_rotation_90_or_270(rotation)) {
3280                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283         } else {
3284                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285                                                     fb->pixel_format);
3286         }
3287
3288         return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293         switch (pixel_format) {
3294         case DRM_FORMAT_C8:
3295                 return PLANE_CTL_FORMAT_INDEXED;
3296         case DRM_FORMAT_RGB565:
3297                 return PLANE_CTL_FORMAT_RGB_565;
3298         case DRM_FORMAT_XBGR8888:
3299                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300         case DRM_FORMAT_XRGB8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888;
3302         /*
3303          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304          * to be already pre-multiplied. We need to add a knob (or a different
3305          * DRM_FORMAT) for user-space to configure that.
3306          */
3307         case DRM_FORMAT_ABGR8888:
3308                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310         case DRM_FORMAT_ARGB8888:
3311                 return PLANE_CTL_FORMAT_XRGB_8888 |
3312                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313         case DRM_FORMAT_XRGB2101010:
3314                 return PLANE_CTL_FORMAT_XRGB_2101010;
3315         case DRM_FORMAT_XBGR2101010:
3316                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317         case DRM_FORMAT_YUYV:
3318                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319         case DRM_FORMAT_YVYU:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321         case DRM_FORMAT_UYVY:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323         case DRM_FORMAT_VYUY:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325         default:
3326                 MISSING_CASE(pixel_format);
3327         }
3328
3329         return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334         switch (fb_modifier) {
3335         case DRM_FORMAT_MOD_NONE:
3336                 break;
3337         case I915_FORMAT_MOD_X_TILED:
3338                 return PLANE_CTL_TILED_X;
3339         case I915_FORMAT_MOD_Y_TILED:
3340                 return PLANE_CTL_TILED_Y;
3341         case I915_FORMAT_MOD_Yf_TILED:
3342                 return PLANE_CTL_TILED_YF;
3343         default:
3344                 MISSING_CASE(fb_modifier);
3345         }
3346
3347         return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352         switch (rotation) {
3353         case DRM_ROTATE_0:
3354                 break;
3355         /*
3356          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357          * while i915 HW rotation is clockwise, thats why this swapping.
3358          */
3359         case DRM_ROTATE_90:
3360                 return PLANE_CTL_ROTATE_270;
3361         case DRM_ROTATE_180:
3362                 return PLANE_CTL_ROTATE_180;
3363         case DRM_ROTATE_270:
3364                 return PLANE_CTL_ROTATE_90;
3365         default:
3366                 MISSING_CASE(rotation);
3367         }
3368
3369         return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373                                          const struct intel_crtc_state *crtc_state,
3374                                          const struct intel_plane_state *plane_state)
3375 {
3376         struct drm_device *dev = plane->dev;
3377         struct drm_i915_private *dev_priv = to_i915(dev);
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379         struct drm_framebuffer *fb = plane_state->base.fb;
3380         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3381         int pipe = intel_crtc->pipe;
3382         u32 plane_ctl;
3383         unsigned int rotation = plane_state->base.rotation;
3384         u32 stride = skl_plane_stride(fb, 0, rotation);
3385         u32 surf_addr = plane_state->main.offset;
3386         int scaler_id = plane_state->scaler_id;
3387         int src_x = plane_state->main.x;
3388         int src_y = plane_state->main.y;
3389         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391         int dst_x = plane_state->base.dst.x1;
3392         int dst_y = plane_state->base.dst.y1;
3393         int dst_w = drm_rect_width(&plane_state->base.dst);
3394         int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396         plane_ctl = PLANE_CTL_ENABLE |
3397                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3398                     PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403         plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405         /* Sizes are 0 based */
3406         src_w--;
3407         src_h--;
3408         dst_w--;
3409         dst_h--;
3410
3411         intel_crtc->dspaddr_offset = surf_addr;
3412
3413         intel_crtc->adjusted_x = src_x;
3414         intel_crtc->adjusted_y = src_y;
3415
3416         if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3417                 skl_write_plane_wm(intel_crtc, wm, 0);
3418
3419         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3420         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3421         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3422         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3423
3424         if (scaler_id >= 0) {
3425                 uint32_t ps_ctrl = 0;
3426
3427                 WARN_ON(!dst_w || !dst_h);
3428                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3429                         crtc_state->scaler_state.scalers[scaler_id].mode;
3430                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3431                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3432                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3433                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3434                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3435         } else {
3436                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3437         }
3438
3439         I915_WRITE(PLANE_SURF(pipe, 0),
3440                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3441
3442         POSTING_READ(PLANE_SURF(pipe, 0));
3443 }
3444
3445 static void skylake_disable_primary_plane(struct drm_plane *primary,
3446                                           struct drm_crtc *crtc)
3447 {
3448         struct drm_device *dev = crtc->dev;
3449         struct drm_i915_private *dev_priv = to_i915(dev);
3450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3451         int pipe = intel_crtc->pipe;
3452
3453         /*
3454          * We only populate skl_results on watermark updates, and if the
3455          * plane's visiblity isn't actually changing neither is its watermarks.
3456          */
3457         if (!crtc->primary->state->visible)
3458                 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3459
3460         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3461         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3462         POSTING_READ(PLANE_SURF(pipe, 0));
3463 }
3464
3465 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3466 static int
3467 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3468                            int x, int y, enum mode_set_atomic state)
3469 {
3470         /* Support for kgdboc is disabled, this needs a major rework. */
3471         DRM_ERROR("legacy panic handler not supported any more.\n");
3472
3473         return -ENODEV;
3474 }
3475
3476 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3477 {
3478         struct intel_crtc *crtc;
3479
3480         for_each_intel_crtc(&dev_priv->drm, crtc)
3481                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3482 }
3483
3484 static void intel_update_primary_planes(struct drm_device *dev)
3485 {
3486         struct drm_crtc *crtc;
3487
3488         for_each_crtc(dev, crtc) {
3489                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3490                 struct intel_plane_state *plane_state =
3491                         to_intel_plane_state(plane->base.state);
3492
3493                 if (plane_state->base.visible)
3494                         plane->update_plane(&plane->base,
3495                                             to_intel_crtc_state(crtc->state),
3496                                             plane_state);
3497         }
3498 }
3499
3500 static int
3501 __intel_display_resume(struct drm_device *dev,
3502                        struct drm_atomic_state *state)
3503 {
3504         struct drm_crtc_state *crtc_state;
3505         struct drm_crtc *crtc;
3506         int i, ret;
3507
3508         intel_modeset_setup_hw_state(dev);
3509         i915_redisable_vga(dev);
3510
3511         if (!state)
3512                 return 0;
3513
3514         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3515                 /*
3516                  * Force recalculation even if we restore
3517                  * current state. With fast modeset this may not result
3518                  * in a modeset when the state is compatible.
3519                  */
3520                 crtc_state->mode_changed = true;
3521         }
3522
3523         /* ignore any reset values/BIOS leftovers in the WM registers */
3524         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3525
3526         ret = drm_atomic_commit(state);
3527
3528         WARN_ON(ret == -EDEADLK);
3529         return ret;
3530 }
3531
3532 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3533 {
3534         return intel_has_gpu_reset(dev_priv) &&
3535                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3536 }
3537
3538 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3539 {
3540         struct drm_device *dev = &dev_priv->drm;
3541         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3542         struct drm_atomic_state *state;
3543         int ret;
3544
3545         /*
3546          * Need mode_config.mutex so that we don't
3547          * trample ongoing ->detect() and whatnot.
3548          */
3549         mutex_lock(&dev->mode_config.mutex);
3550         drm_modeset_acquire_init(ctx, 0);
3551         while (1) {
3552                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3553                 if (ret != -EDEADLK)
3554                         break;
3555
3556                 drm_modeset_backoff(ctx);
3557         }
3558
3559         /* reset doesn't touch the display, but flips might get nuked anyway, */
3560         if (!i915.force_reset_modeset_test &&
3561             !gpu_reset_clobbers_display(dev_priv))
3562                 return;
3563
3564         /*
3565          * Disabling the crtcs gracefully seems nicer. Also the
3566          * g33 docs say we should at least disable all the planes.
3567          */
3568         state = drm_atomic_helper_duplicate_state(dev, ctx);
3569         if (IS_ERR(state)) {
3570                 ret = PTR_ERR(state);
3571                 state = NULL;
3572                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3573                 goto err;
3574         }
3575
3576         ret = drm_atomic_helper_disable_all(dev, ctx);
3577         if (ret) {
3578                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3579                 goto err;
3580         }
3581
3582         dev_priv->modeset_restore_state = state;
3583         state->acquire_ctx = ctx;
3584         return;
3585
3586 err:
3587         drm_atomic_state_free(state);
3588 }
3589
3590 void intel_finish_reset(struct drm_i915_private *dev_priv)
3591 {
3592         struct drm_device *dev = &dev_priv->drm;
3593         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3594         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3595         int ret;
3596
3597         /*
3598          * Flips in the rings will be nuked by the reset,
3599          * so complete all pending flips so that user space
3600          * will get its events and not get stuck.
3601          */
3602         intel_complete_page_flips(dev_priv);
3603
3604         dev_priv->modeset_restore_state = NULL;
3605
3606         /* reset doesn't touch the display */
3607         if (!gpu_reset_clobbers_display(dev_priv)) {
3608                 if (!state) {
3609                         /*
3610                          * Flips in the rings have been nuked by the reset,
3611                          * so update the base address of all primary
3612                          * planes to the the last fb to make sure we're
3613                          * showing the correct fb after a reset.
3614                          *
3615                          * FIXME: Atomic will make this obsolete since we won't schedule
3616                          * CS-based flips (which might get lost in gpu resets) any more.
3617                          */
3618                         intel_update_primary_planes(dev);
3619                 } else {
3620                         ret = __intel_display_resume(dev, state);
3621                         if (ret)
3622                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3623                 }
3624         } else {
3625                 /*
3626                  * The display has been reset as well,
3627                  * so need a full re-initialization.
3628                  */
3629                 intel_runtime_pm_disable_interrupts(dev_priv);
3630                 intel_runtime_pm_enable_interrupts(dev_priv);
3631
3632                 intel_pps_unlock_regs_wa(dev_priv);
3633                 intel_modeset_init_hw(dev);
3634
3635                 spin_lock_irq(&dev_priv->irq_lock);
3636                 if (dev_priv->display.hpd_irq_setup)
3637                         dev_priv->display.hpd_irq_setup(dev_priv);
3638                 spin_unlock_irq(&dev_priv->irq_lock);
3639
3640                 ret = __intel_display_resume(dev, state);
3641                 if (ret)
3642                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3643
3644                 intel_hpd_init(dev_priv);
3645         }
3646
3647         drm_modeset_drop_locks(ctx);
3648         drm_modeset_acquire_fini(ctx);
3649         mutex_unlock(&dev->mode_config.mutex);
3650 }
3651
3652 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3653 {
3654         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3655
3656         if (i915_reset_in_progress(error))
3657                 return true;
3658
3659         if (crtc->reset_count != i915_reset_count(error))
3660                 return true;
3661
3662         return false;
3663 }
3664
3665 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3666 {
3667         struct drm_device *dev = crtc->dev;
3668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3669         bool pending;
3670
3671         if (abort_flip_on_reset(intel_crtc))
3672                 return false;
3673
3674         spin_lock_irq(&dev->event_lock);
3675         pending = to_intel_crtc(crtc)->flip_work != NULL;
3676         spin_unlock_irq(&dev->event_lock);
3677
3678         return pending;
3679 }
3680
3681 static void intel_update_pipe_config(struct intel_crtc *crtc,
3682                                      struct intel_crtc_state *old_crtc_state)
3683 {
3684         struct drm_device *dev = crtc->base.dev;
3685         struct drm_i915_private *dev_priv = to_i915(dev);
3686         struct intel_crtc_state *pipe_config =
3687                 to_intel_crtc_state(crtc->base.state);
3688
3689         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3690         crtc->base.mode = crtc->base.state->mode;
3691
3692         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3693                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3694                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3695
3696         /*
3697          * Update pipe size and adjust fitter if needed: the reason for this is
3698          * that in compute_mode_changes we check the native mode (not the pfit
3699          * mode) to see if we can flip rather than do a full mode set. In the
3700          * fastboot case, we'll flip, but if we don't update the pipesrc and
3701          * pfit state, we'll end up with a big fb scanned out into the wrong
3702          * sized surface.
3703          */
3704
3705         I915_WRITE(PIPESRC(crtc->pipe),
3706                    ((pipe_config->pipe_src_w - 1) << 16) |
3707                    (pipe_config->pipe_src_h - 1));
3708
3709         /* on skylake this is done by detaching scalers */
3710         if (INTEL_INFO(dev)->gen >= 9) {
3711                 skl_detach_scalers(crtc);
3712
3713                 if (pipe_config->pch_pfit.enabled)
3714                         skylake_pfit_enable(crtc);
3715         } else if (HAS_PCH_SPLIT(dev_priv)) {
3716                 if (pipe_config->pch_pfit.enabled)
3717                         ironlake_pfit_enable(crtc);
3718                 else if (old_crtc_state->pch_pfit.enabled)
3719                         ironlake_pfit_disable(crtc, true);
3720         }
3721 }
3722
3723 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3724 {
3725         struct drm_device *dev = crtc->dev;
3726         struct drm_i915_private *dev_priv = to_i915(dev);
3727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728         int pipe = intel_crtc->pipe;
3729         i915_reg_t reg;
3730         u32 temp;
3731
3732         /* enable normal train */
3733         reg = FDI_TX_CTL(pipe);
3734         temp = I915_READ(reg);
3735         if (IS_IVYBRIDGE(dev_priv)) {
3736                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3737                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3738         } else {
3739                 temp &= ~FDI_LINK_TRAIN_NONE;
3740                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3741         }
3742         I915_WRITE(reg, temp);
3743
3744         reg = FDI_RX_CTL(pipe);
3745         temp = I915_READ(reg);
3746         if (HAS_PCH_CPT(dev_priv)) {
3747                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3748                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3749         } else {
3750                 temp &= ~FDI_LINK_TRAIN_NONE;
3751                 temp |= FDI_LINK_TRAIN_NONE;
3752         }
3753         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3754
3755         /* wait one idle pattern time */
3756         POSTING_READ(reg);
3757         udelay(1000);
3758
3759         /* IVB wants error correction enabled */
3760         if (IS_IVYBRIDGE(dev_priv))
3761                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3762                            FDI_FE_ERRC_ENABLE);
3763 }
3764
3765 /* The FDI link training functions for ILK/Ibexpeak. */
3766 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3767 {
3768         struct drm_device *dev = crtc->dev;
3769         struct drm_i915_private *dev_priv = to_i915(dev);
3770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3771         int pipe = intel_crtc->pipe;
3772         i915_reg_t reg;
3773         u32 temp, tries;
3774
3775         /* FDI needs bits from pipe first */
3776         assert_pipe_enabled(dev_priv, pipe);
3777
3778         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3779            for train result */
3780         reg = FDI_RX_IMR(pipe);
3781         temp = I915_READ(reg);
3782         temp &= ~FDI_RX_SYMBOL_LOCK;
3783         temp &= ~FDI_RX_BIT_LOCK;
3784         I915_WRITE(reg, temp);
3785         I915_READ(reg);
3786         udelay(150);
3787
3788         /* enable CPU FDI TX and PCH FDI RX */
3789         reg = FDI_TX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3792         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3793         temp &= ~FDI_LINK_TRAIN_NONE;
3794         temp |= FDI_LINK_TRAIN_PATTERN_1;
3795         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3796
3797         reg = FDI_RX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         temp &= ~FDI_LINK_TRAIN_NONE;
3800         temp |= FDI_LINK_TRAIN_PATTERN_1;
3801         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3802
3803         POSTING_READ(reg);
3804         udelay(150);
3805
3806         /* Ironlake workaround, enable clock pointer after FDI enable*/
3807         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3808         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3809                    FDI_RX_PHASE_SYNC_POINTER_EN);
3810
3811         reg = FDI_RX_IIR(pipe);
3812         for (tries = 0; tries < 5; tries++) {
3813                 temp = I915_READ(reg);
3814                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3815
3816                 if ((temp & FDI_RX_BIT_LOCK)) {
3817                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3818                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3819                         break;
3820                 }
3821         }
3822         if (tries == 5)
3823                 DRM_ERROR("FDI train 1 fail!\n");
3824
3825         /* Train 2 */
3826         reg = FDI_TX_CTL(pipe);
3827         temp = I915_READ(reg);
3828         temp &= ~FDI_LINK_TRAIN_NONE;
3829         temp |= FDI_LINK_TRAIN_PATTERN_2;
3830         I915_WRITE(reg, temp);
3831
3832         reg = FDI_RX_CTL(pipe);
3833         temp = I915_READ(reg);
3834         temp &= ~FDI_LINK_TRAIN_NONE;
3835         temp |= FDI_LINK_TRAIN_PATTERN_2;
3836         I915_WRITE(reg, temp);
3837
3838         POSTING_READ(reg);
3839         udelay(150);
3840
3841         reg = FDI_RX_IIR(pipe);
3842         for (tries = 0; tries < 5; tries++) {
3843                 temp = I915_READ(reg);
3844                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3845
3846                 if (temp & FDI_RX_SYMBOL_LOCK) {
3847                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3848                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3849                         break;
3850                 }
3851         }
3852         if (tries == 5)
3853                 DRM_ERROR("FDI train 2 fail!\n");
3854
3855         DRM_DEBUG_KMS("FDI train done\n");
3856
3857 }
3858
3859 static const int snb_b_fdi_train_param[] = {
3860         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3861         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3862         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3863         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3864 };
3865
3866 /* The FDI link training functions for SNB/Cougarpoint. */
3867 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3868 {
3869         struct drm_device *dev = crtc->dev;
3870         struct drm_i915_private *dev_priv = to_i915(dev);
3871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3872         int pipe = intel_crtc->pipe;
3873         i915_reg_t reg;
3874         u32 temp, i, retry;
3875
3876         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3877            for train result */
3878         reg = FDI_RX_IMR(pipe);
3879         temp = I915_READ(reg);
3880         temp &= ~FDI_RX_SYMBOL_LOCK;
3881         temp &= ~FDI_RX_BIT_LOCK;
3882         I915_WRITE(reg, temp);
3883
3884         POSTING_READ(reg);
3885         udelay(150);
3886
3887         /* enable CPU FDI TX and PCH FDI RX */
3888         reg = FDI_TX_CTL(pipe);
3889         temp = I915_READ(reg);
3890         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3891         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3892         temp &= ~FDI_LINK_TRAIN_NONE;
3893         temp |= FDI_LINK_TRAIN_PATTERN_1;
3894         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3895         /* SNB-B */
3896         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3897         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3898
3899         I915_WRITE(FDI_RX_MISC(pipe),
3900                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3901
3902         reg = FDI_RX_CTL(pipe);
3903         temp = I915_READ(reg);
3904         if (HAS_PCH_CPT(dev_priv)) {
3905                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3906                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3907         } else {
3908                 temp &= ~FDI_LINK_TRAIN_NONE;
3909                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3910         }
3911         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3912
3913         POSTING_READ(reg);
3914         udelay(150);
3915
3916         for (i = 0; i < 4; i++) {
3917                 reg = FDI_TX_CTL(pipe);
3918                 temp = I915_READ(reg);
3919                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3920                 temp |= snb_b_fdi_train_param[i];
3921                 I915_WRITE(reg, temp);
3922
3923                 POSTING_READ(reg);
3924                 udelay(500);
3925
3926                 for (retry = 0; retry < 5; retry++) {
3927                         reg = FDI_RX_IIR(pipe);
3928                         temp = I915_READ(reg);
3929                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3930                         if (temp & FDI_RX_BIT_LOCK) {
3931                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3932                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3933                                 break;
3934                         }
3935                         udelay(50);
3936                 }
3937                 if (retry < 5)
3938                         break;
3939         }
3940         if (i == 4)
3941                 DRM_ERROR("FDI train 1 fail!\n");
3942
3943         /* Train 2 */
3944         reg = FDI_TX_CTL(pipe);
3945         temp = I915_READ(reg);
3946         temp &= ~FDI_LINK_TRAIN_NONE;
3947         temp |= FDI_LINK_TRAIN_PATTERN_2;
3948         if (IS_GEN6(dev)) {
3949                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3950                 /* SNB-B */
3951                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3952         }
3953         I915_WRITE(reg, temp);
3954
3955         reg = FDI_RX_CTL(pipe);
3956         temp = I915_READ(reg);
3957         if (HAS_PCH_CPT(dev_priv)) {
3958                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3959                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3960         } else {
3961                 temp &= ~FDI_LINK_TRAIN_NONE;
3962                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3963         }
3964         I915_WRITE(reg, temp);
3965
3966         POSTING_READ(reg);
3967         udelay(150);
3968
3969         for (i = 0; i < 4; i++) {
3970                 reg = FDI_TX_CTL(pipe);
3971                 temp = I915_READ(reg);
3972                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3973                 temp |= snb_b_fdi_train_param[i];
3974                 I915_WRITE(reg, temp);
3975
3976                 POSTING_READ(reg);
3977                 udelay(500);
3978
3979                 for (retry = 0; retry < 5; retry++) {
3980                         reg = FDI_RX_IIR(pipe);
3981                         temp = I915_READ(reg);
3982                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3983                         if (temp & FDI_RX_SYMBOL_LOCK) {
3984                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3985                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3986                                 break;
3987                         }
3988                         udelay(50);
3989                 }
3990                 if (retry < 5)
3991                         break;
3992         }
3993         if (i == 4)
3994                 DRM_ERROR("FDI train 2 fail!\n");
3995
3996         DRM_DEBUG_KMS("FDI train done.\n");
3997 }
3998
3999 /* Manual link training for Ivy Bridge A0 parts */
4000 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4001 {
4002         struct drm_device *dev = crtc->dev;
4003         struct drm_i915_private *dev_priv = to_i915(dev);
4004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4005         int pipe = intel_crtc->pipe;
4006         i915_reg_t reg;
4007         u32 temp, i, j;
4008
4009         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4010            for train result */
4011         reg = FDI_RX_IMR(pipe);
4012         temp = I915_READ(reg);
4013         temp &= ~FDI_RX_SYMBOL_LOCK;
4014         temp &= ~FDI_RX_BIT_LOCK;
4015         I915_WRITE(reg, temp);
4016
4017         POSTING_READ(reg);
4018         udelay(150);
4019
4020         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4021                       I915_READ(FDI_RX_IIR(pipe)));
4022
4023         /* Try each vswing and preemphasis setting twice before moving on */
4024         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4025                 /* disable first in case we need to retry */
4026                 reg = FDI_TX_CTL(pipe);
4027                 temp = I915_READ(reg);
4028                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4029                 temp &= ~FDI_TX_ENABLE;
4030                 I915_WRITE(reg, temp);
4031
4032                 reg = FDI_RX_CTL(pipe);
4033                 temp = I915_READ(reg);
4034                 temp &= ~FDI_LINK_TRAIN_AUTO;
4035                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4036                 temp &= ~FDI_RX_ENABLE;
4037                 I915_WRITE(reg, temp);
4038
4039                 /* enable CPU FDI TX and PCH FDI RX */
4040                 reg = FDI_TX_CTL(pipe);
4041                 temp = I915_READ(reg);
4042                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4043                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4044                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4045                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4046                 temp |= snb_b_fdi_train_param[j/2];
4047                 temp |= FDI_COMPOSITE_SYNC;
4048                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4049
4050                 I915_WRITE(FDI_RX_MISC(pipe),
4051                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4052
4053                 reg = FDI_RX_CTL(pipe);
4054                 temp = I915_READ(reg);
4055                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4056                 temp |= FDI_COMPOSITE_SYNC;
4057                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4058
4059                 POSTING_READ(reg);
4060                 udelay(1); /* should be 0.5us */
4061
4062                 for (i = 0; i < 4; i++) {
4063                         reg = FDI_RX_IIR(pipe);
4064                         temp = I915_READ(reg);
4065                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4066
4067                         if (temp & FDI_RX_BIT_LOCK ||
4068                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4069                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4070                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4071                                               i);
4072                                 break;
4073                         }
4074                         udelay(1); /* should be 0.5us */
4075                 }
4076                 if (i == 4) {
4077                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4078                         continue;
4079                 }
4080
4081                 /* Train 2 */
4082                 reg = FDI_TX_CTL(pipe);
4083                 temp = I915_READ(reg);
4084                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4085                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4086                 I915_WRITE(reg, temp);
4087
4088                 reg = FDI_RX_CTL(pipe);
4089                 temp = I915_READ(reg);
4090                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4091                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4092                 I915_WRITE(reg, temp);
4093
4094                 POSTING_READ(reg);
4095                 udelay(2); /* should be 1.5us */
4096
4097                 for (i = 0; i < 4; i++) {
4098                         reg = FDI_RX_IIR(pipe);
4099                         temp = I915_READ(reg);
4100                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4101
4102                         if (temp & FDI_RX_SYMBOL_LOCK ||
4103                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4104                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4105                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4106                                               i);
4107                                 goto train_done;
4108                         }
4109                         udelay(2); /* should be 1.5us */
4110                 }
4111                 if (i == 4)
4112                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4113         }
4114
4115 train_done:
4116         DRM_DEBUG_KMS("FDI train done.\n");
4117 }
4118
4119 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4120 {
4121         struct drm_device *dev = intel_crtc->base.dev;
4122         struct drm_i915_private *dev_priv = to_i915(dev);
4123         int pipe = intel_crtc->pipe;
4124         i915_reg_t reg;
4125         u32 temp;
4126
4127         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4128         reg = FDI_RX_CTL(pipe);
4129         temp = I915_READ(reg);
4130         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4131         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4132         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4133         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4134
4135         POSTING_READ(reg);
4136         udelay(200);
4137
4138         /* Switch from Rawclk to PCDclk */
4139         temp = I915_READ(reg);
4140         I915_WRITE(reg, temp | FDI_PCDCLK);
4141
4142         POSTING_READ(reg);
4143         udelay(200);
4144
4145         /* Enable CPU FDI TX PLL, always on for Ironlake */
4146         reg = FDI_TX_CTL(pipe);
4147         temp = I915_READ(reg);
4148         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4149                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4150
4151                 POSTING_READ(reg);
4152                 udelay(100);
4153         }
4154 }
4155
4156 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4157 {
4158         struct drm_device *dev = intel_crtc->base.dev;
4159         struct drm_i915_private *dev_priv = to_i915(dev);
4160         int pipe = intel_crtc->pipe;
4161         i915_reg_t reg;
4162         u32 temp;
4163
4164         /* Switch from PCDclk to Rawclk */
4165         reg = FDI_RX_CTL(pipe);
4166         temp = I915_READ(reg);
4167         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4168
4169         /* Disable CPU FDI TX PLL */
4170         reg = FDI_TX_CTL(pipe);
4171         temp = I915_READ(reg);
4172         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4173
4174         POSTING_READ(reg);
4175         udelay(100);
4176
4177         reg = FDI_RX_CTL(pipe);
4178         temp = I915_READ(reg);
4179         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4180
4181         /* Wait for the clocks to turn off. */
4182         POSTING_READ(reg);
4183         udelay(100);
4184 }
4185
4186 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4187 {
4188         struct drm_device *dev = crtc->dev;
4189         struct drm_i915_private *dev_priv = to_i915(dev);
4190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4191         int pipe = intel_crtc->pipe;
4192         i915_reg_t reg;
4193         u32 temp;
4194
4195         /* disable CPU FDI tx and PCH FDI rx */
4196         reg = FDI_TX_CTL(pipe);
4197         temp = I915_READ(reg);
4198         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4199         POSTING_READ(reg);
4200
4201         reg = FDI_RX_CTL(pipe);
4202         temp = I915_READ(reg);
4203         temp &= ~(0x7 << 16);
4204         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4205         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4206
4207         POSTING_READ(reg);
4208         udelay(100);
4209
4210         /* Ironlake workaround, disable clock pointer after downing FDI */
4211         if (HAS_PCH_IBX(dev_priv))
4212                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4213
4214         /* still set train pattern 1 */
4215         reg = FDI_TX_CTL(pipe);
4216         temp = I915_READ(reg);
4217         temp &= ~FDI_LINK_TRAIN_NONE;
4218         temp |= FDI_LINK_TRAIN_PATTERN_1;
4219         I915_WRITE(reg, temp);
4220
4221         reg = FDI_RX_CTL(pipe);
4222         temp = I915_READ(reg);
4223         if (HAS_PCH_CPT(dev_priv)) {
4224                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4225                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4226         } else {
4227                 temp &= ~FDI_LINK_TRAIN_NONE;
4228                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4229         }
4230         /* BPC in FDI rx is consistent with that in PIPECONF */
4231         temp &= ~(0x07 << 16);
4232         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4233         I915_WRITE(reg, temp);
4234
4235         POSTING_READ(reg);
4236         udelay(100);
4237 }
4238
4239 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4240 {
4241         struct intel_crtc *crtc;
4242
4243         /* Note that we don't need to be called with mode_config.lock here
4244          * as our list of CRTC objects is static for the lifetime of the
4245          * device and so cannot disappear as we iterate. Similarly, we can
4246          * happily treat the predicates as racy, atomic checks as userspace
4247          * cannot claim and pin a new fb without at least acquring the
4248          * struct_mutex and so serialising with us.
4249          */
4250         for_each_intel_crtc(dev, crtc) {
4251                 if (atomic_read(&crtc->unpin_work_count) == 0)
4252                         continue;
4253
4254                 if (crtc->flip_work)
4255                         intel_wait_for_vblank(dev, crtc->pipe);
4256
4257                 return true;
4258         }
4259
4260         return false;
4261 }
4262
4263 static void page_flip_completed(struct intel_crtc *intel_crtc)
4264 {
4265         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4266         struct intel_flip_work *work = intel_crtc->flip_work;
4267
4268         intel_crtc->flip_work = NULL;
4269
4270         if (work->event)
4271                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4272
4273         drm_crtc_vblank_put(&intel_crtc->base);
4274
4275         wake_up_all(&dev_priv->pending_flip_queue);
4276         queue_work(dev_priv->wq, &work->unpin_work);
4277
4278         trace_i915_flip_complete(intel_crtc->plane,
4279                                  work->pending_flip_obj);
4280 }
4281
4282 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4283 {
4284         struct drm_device *dev = crtc->dev;
4285         struct drm_i915_private *dev_priv = to_i915(dev);
4286         long ret;
4287
4288         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4289
4290         ret = wait_event_interruptible_timeout(
4291                                         dev_priv->pending_flip_queue,
4292                                         !intel_crtc_has_pending_flip(crtc),
4293                                         60*HZ);
4294
4295         if (ret < 0)
4296                 return ret;
4297
4298         if (ret == 0) {
4299                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4300                 struct intel_flip_work *work;
4301
4302                 spin_lock_irq(&dev->event_lock);
4303                 work = intel_crtc->flip_work;
4304                 if (work && !is_mmio_work(work)) {
4305                         WARN_ONCE(1, "Removing stuck page flip\n");
4306                         page_flip_completed(intel_crtc);
4307                 }
4308                 spin_unlock_irq(&dev->event_lock);
4309         }
4310
4311         return 0;
4312 }
4313
4314 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4315 {
4316         u32 temp;
4317
4318         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4319
4320         mutex_lock(&dev_priv->sb_lock);
4321
4322         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4323         temp |= SBI_SSCCTL_DISABLE;
4324         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4325
4326         mutex_unlock(&dev_priv->sb_lock);
4327 }
4328
4329 /* Program iCLKIP clock to the desired frequency */
4330 static void lpt_program_iclkip(struct drm_crtc *crtc)
4331 {
4332         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4333         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4334         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4335         u32 temp;
4336
4337         lpt_disable_iclkip(dev_priv);
4338
4339         /* The iCLK virtual clock root frequency is in MHz,
4340          * but the adjusted_mode->crtc_clock in in KHz. To get the
4341          * divisors, it is necessary to divide one by another, so we
4342          * convert the virtual clock precision to KHz here for higher
4343          * precision.
4344          */
4345         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4346                 u32 iclk_virtual_root_freq = 172800 * 1000;
4347                 u32 iclk_pi_range = 64;
4348                 u32 desired_divisor;
4349
4350                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4351                                                     clock << auxdiv);
4352                 divsel = (desired_divisor / iclk_pi_range) - 2;
4353                 phaseinc = desired_divisor % iclk_pi_range;
4354
4355                 /*
4356                  * Near 20MHz is a corner case which is
4357                  * out of range for the 7-bit divisor
4358                  */
4359                 if (divsel <= 0x7f)
4360                         break;
4361         }
4362
4363         /* This should not happen with any sane values */
4364         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4365                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4366         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4367                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4368
4369         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4370                         clock,
4371                         auxdiv,
4372                         divsel,
4373                         phasedir,
4374                         phaseinc);
4375
4376         mutex_lock(&dev_priv->sb_lock);
4377
4378         /* Program SSCDIVINTPHASE6 */
4379         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4380         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4381         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4382         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4383         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4384         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4385         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4386         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4387
4388         /* Program SSCAUXDIV */
4389         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4390         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4391         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4392         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4393
4394         /* Enable modulator and associated divider */
4395         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4396         temp &= ~SBI_SSCCTL_DISABLE;
4397         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4398
4399         mutex_unlock(&dev_priv->sb_lock);
4400
4401         /* Wait for initialization time */
4402         udelay(24);
4403
4404         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4405 }
4406
4407 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4408 {
4409         u32 divsel, phaseinc, auxdiv;
4410         u32 iclk_virtual_root_freq = 172800 * 1000;
4411         u32 iclk_pi_range = 64;
4412         u32 desired_divisor;
4413         u32 temp;
4414
4415         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4416                 return 0;
4417
4418         mutex_lock(&dev_priv->sb_lock);
4419
4420         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4421         if (temp & SBI_SSCCTL_DISABLE) {
4422                 mutex_unlock(&dev_priv->sb_lock);
4423                 return 0;
4424         }
4425
4426         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4427         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4428                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4429         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4430                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4431
4432         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4433         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4434                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4435
4436         mutex_unlock(&dev_priv->sb_lock);
4437
4438         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4439
4440         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4441                                  desired_divisor << auxdiv);
4442 }
4443
4444 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4445                                                 enum pipe pch_transcoder)
4446 {
4447         struct drm_device *dev = crtc->base.dev;
4448         struct drm_i915_private *dev_priv = to_i915(dev);
4449         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4450
4451         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4452                    I915_READ(HTOTAL(cpu_transcoder)));
4453         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4454                    I915_READ(HBLANK(cpu_transcoder)));
4455         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4456                    I915_READ(HSYNC(cpu_transcoder)));
4457
4458         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4459                    I915_READ(VTOTAL(cpu_transcoder)));
4460         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4461                    I915_READ(VBLANK(cpu_transcoder)));
4462         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4463                    I915_READ(VSYNC(cpu_transcoder)));
4464         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4465                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4466 }
4467
4468 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4469 {
4470         struct drm_i915_private *dev_priv = to_i915(dev);
4471         uint32_t temp;
4472
4473         temp = I915_READ(SOUTH_CHICKEN1);
4474         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4475                 return;
4476
4477         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4478         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4479
4480         temp &= ~FDI_BC_BIFURCATION_SELECT;
4481         if (enable)
4482                 temp |= FDI_BC_BIFURCATION_SELECT;
4483
4484         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4485         I915_WRITE(SOUTH_CHICKEN1, temp);
4486         POSTING_READ(SOUTH_CHICKEN1);
4487 }
4488
4489 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4490 {
4491         struct drm_device *dev = intel_crtc->base.dev;
4492
4493         switch (intel_crtc->pipe) {
4494         case PIPE_A:
4495                 break;
4496         case PIPE_B:
4497                 if (intel_crtc->config->fdi_lanes > 2)
4498                         cpt_set_fdi_bc_bifurcation(dev, false);
4499                 else
4500                         cpt_set_fdi_bc_bifurcation(dev, true);
4501
4502                 break;
4503         case PIPE_C:
4504                 cpt_set_fdi_bc_bifurcation(dev, true);
4505
4506                 break;
4507         default:
4508                 BUG();
4509         }
4510 }
4511
4512 /* Return which DP Port should be selected for Transcoder DP control */
4513 static enum port
4514 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4515 {
4516         struct drm_device *dev = crtc->dev;
4517         struct intel_encoder *encoder;
4518
4519         for_each_encoder_on_crtc(dev, crtc, encoder) {
4520                 if (encoder->type == INTEL_OUTPUT_DP ||
4521                     encoder->type == INTEL_OUTPUT_EDP)
4522                         return enc_to_dig_port(&encoder->base)->port;
4523         }
4524
4525         return -1;
4526 }
4527
4528 /*
4529  * Enable PCH resources required for PCH ports:
4530  *   - PCH PLLs
4531  *   - FDI training & RX/TX
4532  *   - update transcoder timings
4533  *   - DP transcoding bits
4534  *   - transcoder
4535  */
4536 static void ironlake_pch_enable(struct drm_crtc *crtc)
4537 {
4538         struct drm_device *dev = crtc->dev;
4539         struct drm_i915_private *dev_priv = to_i915(dev);
4540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541         int pipe = intel_crtc->pipe;
4542         u32 temp;
4543
4544         assert_pch_transcoder_disabled(dev_priv, pipe);
4545
4546         if (IS_IVYBRIDGE(dev_priv))
4547                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4548
4549         /* Write the TU size bits before fdi link training, so that error
4550          * detection works. */
4551         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4552                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4553
4554         /* For PCH output, training FDI link */
4555         dev_priv->display.fdi_link_train(crtc);
4556
4557         /* We need to program the right clock selection before writing the pixel
4558          * mutliplier into the DPLL. */
4559         if (HAS_PCH_CPT(dev_priv)) {
4560                 u32 sel;
4561
4562                 temp = I915_READ(PCH_DPLL_SEL);
4563                 temp |= TRANS_DPLL_ENABLE(pipe);
4564                 sel = TRANS_DPLLB_SEL(pipe);
4565                 if (intel_crtc->config->shared_dpll ==
4566                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4567                         temp |= sel;
4568                 else
4569                         temp &= ~sel;
4570                 I915_WRITE(PCH_DPLL_SEL, temp);
4571         }
4572
4573         /* XXX: pch pll's can be enabled any time before we enable the PCH
4574          * transcoder, and we actually should do this to not upset any PCH
4575          * transcoder that already use the clock when we share it.
4576          *
4577          * Note that enable_shared_dpll tries to do the right thing, but
4578          * get_shared_dpll unconditionally resets the pll - we need that to have
4579          * the right LVDS enable sequence. */
4580         intel_enable_shared_dpll(intel_crtc);
4581
4582         /* set transcoder timing, panel must allow it */
4583         assert_panel_unlocked(dev_priv, pipe);
4584         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4585
4586         intel_fdi_normal_train(crtc);
4587
4588         /* For PCH DP, enable TRANS_DP_CTL */
4589         if (HAS_PCH_CPT(dev_priv) &&
4590             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4591                 const struct drm_display_mode *adjusted_mode =
4592                         &intel_crtc->config->base.adjusted_mode;
4593                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4594                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4595                 temp = I915_READ(reg);
4596                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4597                           TRANS_DP_SYNC_MASK |
4598                           TRANS_DP_BPC_MASK);
4599                 temp |= TRANS_DP_OUTPUT_ENABLE;
4600                 temp |= bpc << 9; /* same format but at 11:9 */
4601
4602                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4603                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4604                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4605                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4606
4607                 switch (intel_trans_dp_port_sel(crtc)) {
4608                 case PORT_B:
4609                         temp |= TRANS_DP_PORT_SEL_B;
4610                         break;
4611                 case PORT_C:
4612                         temp |= TRANS_DP_PORT_SEL_C;
4613                         break;
4614                 case PORT_D:
4615                         temp |= TRANS_DP_PORT_SEL_D;
4616                         break;
4617                 default:
4618                         BUG();
4619                 }
4620
4621                 I915_WRITE(reg, temp);
4622         }
4623
4624         ironlake_enable_pch_transcoder(dev_priv, pipe);
4625 }
4626
4627 static void lpt_pch_enable(struct drm_crtc *crtc)
4628 {
4629         struct drm_device *dev = crtc->dev;
4630         struct drm_i915_private *dev_priv = to_i915(dev);
4631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4633
4634         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4635
4636         lpt_program_iclkip(crtc);
4637
4638         /* Set transcoder timing. */
4639         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4640
4641         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4642 }
4643
4644 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4645 {
4646         struct drm_i915_private *dev_priv = to_i915(dev);
4647         i915_reg_t dslreg = PIPEDSL(pipe);
4648         u32 temp;
4649
4650         temp = I915_READ(dslreg);
4651         udelay(500);
4652         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4653                 if (wait_for(I915_READ(dslreg) != temp, 5))
4654                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4655         }
4656 }
4657
4658 static int
4659 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4660                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4661                   int src_w, int src_h, int dst_w, int dst_h)
4662 {
4663         struct intel_crtc_scaler_state *scaler_state =
4664                 &crtc_state->scaler_state;
4665         struct intel_crtc *intel_crtc =
4666                 to_intel_crtc(crtc_state->base.crtc);
4667         int need_scaling;
4668
4669         need_scaling = intel_rotation_90_or_270(rotation) ?
4670                 (src_h != dst_w || src_w != dst_h):
4671                 (src_w != dst_w || src_h != dst_h);
4672
4673         /*
4674          * if plane is being disabled or scaler is no more required or force detach
4675          *  - free scaler binded to this plane/crtc
4676          *  - in order to do this, update crtc->scaler_usage
4677          *
4678          * Here scaler state in crtc_state is set free so that
4679          * scaler can be assigned to other user. Actual register
4680          * update to free the scaler is done in plane/panel-fit programming.
4681          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4682          */
4683         if (force_detach || !need_scaling) {
4684                 if (*scaler_id >= 0) {
4685                         scaler_state->scaler_users &= ~(1 << scaler_user);
4686                         scaler_state->scalers[*scaler_id].in_use = 0;
4687
4688                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4689                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4690                                 intel_crtc->pipe, scaler_user, *scaler_id,
4691                                 scaler_state->scaler_users);
4692                         *scaler_id = -1;
4693                 }
4694                 return 0;
4695         }
4696
4697         /* range checks */
4698         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4699                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4700
4701                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4702                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4703                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4704                         "size is out of scaler range\n",
4705                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4706                 return -EINVAL;
4707         }
4708
4709         /* mark this plane as a scaler user in crtc_state */
4710         scaler_state->scaler_users |= (1 << scaler_user);
4711         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4712                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4713                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4714                 scaler_state->scaler_users);
4715
4716         return 0;
4717 }
4718
4719 /**
4720  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4721  *
4722  * @state: crtc's scaler state
4723  *
4724  * Return
4725  *     0 - scaler_usage updated successfully
4726  *    error - requested scaling cannot be supported or other error condition
4727  */
4728 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4729 {
4730         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4731         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4732
4733         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4734                       intel_crtc->base.base.id, intel_crtc->base.name,
4735                       intel_crtc->pipe, SKL_CRTC_INDEX);
4736
4737         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4738                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4739                 state->pipe_src_w, state->pipe_src_h,
4740                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4741 }
4742
4743 /**
4744  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4745  *
4746  * @state: crtc's scaler state
4747  * @plane_state: atomic plane state to update
4748  *
4749  * Return
4750  *     0 - scaler_usage updated successfully
4751  *    error - requested scaling cannot be supported or other error condition
4752  */
4753 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4754                                    struct intel_plane_state *plane_state)
4755 {
4756
4757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4758         struct intel_plane *intel_plane =
4759                 to_intel_plane(plane_state->base.plane);
4760         struct drm_framebuffer *fb = plane_state->base.fb;
4761         int ret;
4762
4763         bool force_detach = !fb || !plane_state->base.visible;
4764
4765         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4766                       intel_plane->base.base.id, intel_plane->base.name,
4767                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4768
4769         ret = skl_update_scaler(crtc_state, force_detach,
4770                                 drm_plane_index(&intel_plane->base),
4771                                 &plane_state->scaler_id,
4772                                 plane_state->base.rotation,
4773                                 drm_rect_width(&plane_state->base.src) >> 16,
4774                                 drm_rect_height(&plane_state->base.src) >> 16,
4775                                 drm_rect_width(&plane_state->base.dst),
4776                                 drm_rect_height(&plane_state->base.dst));
4777
4778         if (ret || plane_state->scaler_id < 0)
4779                 return ret;
4780
4781         /* check colorkey */
4782         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4783                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4784                               intel_plane->base.base.id,
4785                               intel_plane->base.name);
4786                 return -EINVAL;
4787         }
4788
4789         /* Check src format */
4790         switch (fb->pixel_format) {
4791         case DRM_FORMAT_RGB565:
4792         case DRM_FORMAT_XBGR8888:
4793         case DRM_FORMAT_XRGB8888:
4794         case DRM_FORMAT_ABGR8888:
4795         case DRM_FORMAT_ARGB8888:
4796         case DRM_FORMAT_XRGB2101010:
4797         case DRM_FORMAT_XBGR2101010:
4798         case DRM_FORMAT_YUYV:
4799         case DRM_FORMAT_YVYU:
4800         case DRM_FORMAT_UYVY:
4801         case DRM_FORMAT_VYUY:
4802                 break;
4803         default:
4804                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4805                               intel_plane->base.base.id, intel_plane->base.name,
4806                               fb->base.id, fb->pixel_format);
4807                 return -EINVAL;
4808         }
4809
4810         return 0;
4811 }
4812
4813 static void skylake_scaler_disable(struct intel_crtc *crtc)
4814 {
4815         int i;
4816
4817         for (i = 0; i < crtc->num_scalers; i++)
4818                 skl_detach_scaler(crtc, i);
4819 }
4820
4821 static void skylake_pfit_enable(struct intel_crtc *crtc)
4822 {
4823         struct drm_device *dev = crtc->base.dev;
4824         struct drm_i915_private *dev_priv = to_i915(dev);
4825         int pipe = crtc->pipe;
4826         struct intel_crtc_scaler_state *scaler_state =
4827                 &crtc->config->scaler_state;
4828
4829         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4830
4831         if (crtc->config->pch_pfit.enabled) {
4832                 int id;
4833
4834                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4835                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4836                         return;
4837                 }
4838
4839                 id = scaler_state->scaler_id;
4840                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4841                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4842                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4843                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4844
4845                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4846         }
4847 }
4848
4849 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4850 {
4851         struct drm_device *dev = crtc->base.dev;
4852         struct drm_i915_private *dev_priv = to_i915(dev);
4853         int pipe = crtc->pipe;
4854
4855         if (crtc->config->pch_pfit.enabled) {
4856                 /* Force use of hard-coded filter coefficients
4857                  * as some pre-programmed values are broken,
4858                  * e.g. x201.
4859                  */
4860                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4861                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4862                                                  PF_PIPE_SEL_IVB(pipe));
4863                 else
4864                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4865                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4866                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4867         }
4868 }
4869
4870 void hsw_enable_ips(struct intel_crtc *crtc)
4871 {
4872         struct drm_device *dev = crtc->base.dev;
4873         struct drm_i915_private *dev_priv = to_i915(dev);
4874
4875         if (!crtc->config->ips_enabled)
4876                 return;
4877
4878         /*
4879          * We can only enable IPS after we enable a plane and wait for a vblank
4880          * This function is called from post_plane_update, which is run after
4881          * a vblank wait.
4882          */
4883
4884         assert_plane_enabled(dev_priv, crtc->plane);
4885         if (IS_BROADWELL(dev_priv)) {
4886                 mutex_lock(&dev_priv->rps.hw_lock);
4887                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4888                 mutex_unlock(&dev_priv->rps.hw_lock);
4889                 /* Quoting Art Runyan: "its not safe to expect any particular
4890                  * value in IPS_CTL bit 31 after enabling IPS through the
4891                  * mailbox." Moreover, the mailbox may return a bogus state,
4892                  * so we need to just enable it and continue on.
4893                  */
4894         } else {
4895                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4896                 /* The bit only becomes 1 in the next vblank, so this wait here
4897                  * is essentially intel_wait_for_vblank. If we don't have this
4898                  * and don't wait for vblanks until the end of crtc_enable, then
4899                  * the HW state readout code will complain that the expected
4900                  * IPS_CTL value is not the one we read. */
4901                 if (intel_wait_for_register(dev_priv,
4902                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4903                                             50))
4904                         DRM_ERROR("Timed out waiting for IPS enable\n");
4905         }
4906 }
4907
4908 void hsw_disable_ips(struct intel_crtc *crtc)
4909 {
4910         struct drm_device *dev = crtc->base.dev;
4911         struct drm_i915_private *dev_priv = to_i915(dev);
4912
4913         if (!crtc->config->ips_enabled)
4914                 return;
4915
4916         assert_plane_enabled(dev_priv, crtc->plane);
4917         if (IS_BROADWELL(dev_priv)) {
4918                 mutex_lock(&dev_priv->rps.hw_lock);
4919                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4920                 mutex_unlock(&dev_priv->rps.hw_lock);
4921                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4922                 if (intel_wait_for_register(dev_priv,
4923                                             IPS_CTL, IPS_ENABLE, 0,
4924                                             42))
4925                         DRM_ERROR("Timed out waiting for IPS disable\n");
4926         } else {
4927                 I915_WRITE(IPS_CTL, 0);
4928                 POSTING_READ(IPS_CTL);
4929         }
4930
4931         /* We need to wait for a vblank before we can disable the plane. */
4932         intel_wait_for_vblank(dev, crtc->pipe);
4933 }
4934
4935 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4936 {
4937         if (intel_crtc->overlay) {
4938                 struct drm_device *dev = intel_crtc->base.dev;
4939                 struct drm_i915_private *dev_priv = to_i915(dev);
4940
4941                 mutex_lock(&dev->struct_mutex);
4942                 dev_priv->mm.interruptible = false;
4943                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4944                 dev_priv->mm.interruptible = true;
4945                 mutex_unlock(&dev->struct_mutex);
4946         }
4947
4948         /* Let userspace switch the overlay on again. In most cases userspace
4949          * has to recompute where to put it anyway.
4950          */
4951 }
4952
4953 /**
4954  * intel_post_enable_primary - Perform operations after enabling primary plane
4955  * @crtc: the CRTC whose primary plane was just enabled
4956  *
4957  * Performs potentially sleeping operations that must be done after the primary
4958  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4959  * called due to an explicit primary plane update, or due to an implicit
4960  * re-enable that is caused when a sprite plane is updated to no longer
4961  * completely hide the primary plane.
4962  */
4963 static void
4964 intel_post_enable_primary(struct drm_crtc *crtc)
4965 {
4966         struct drm_device *dev = crtc->dev;
4967         struct drm_i915_private *dev_priv = to_i915(dev);
4968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969         int pipe = intel_crtc->pipe;
4970
4971         /*
4972          * FIXME IPS should be fine as long as one plane is
4973          * enabled, but in practice it seems to have problems
4974          * when going from primary only to sprite only and vice
4975          * versa.
4976          */
4977         hsw_enable_ips(intel_crtc);
4978
4979         /*
4980          * Gen2 reports pipe underruns whenever all planes are disabled.
4981          * So don't enable underrun reporting before at least some planes
4982          * are enabled.
4983          * FIXME: Need to fix the logic to work when we turn off all planes
4984          * but leave the pipe running.
4985          */
4986         if (IS_GEN2(dev))
4987                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988
4989         /* Underruns don't always raise interrupts, so check manually. */
4990         intel_check_cpu_fifo_underruns(dev_priv);
4991         intel_check_pch_fifo_underruns(dev_priv);
4992 }
4993
4994 /* FIXME move all this to pre_plane_update() with proper state tracking */
4995 static void
4996 intel_pre_disable_primary(struct drm_crtc *crtc)
4997 {
4998         struct drm_device *dev = crtc->dev;
4999         struct drm_i915_private *dev_priv = to_i915(dev);
5000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5001         int pipe = intel_crtc->pipe;
5002
5003         /*
5004          * Gen2 reports pipe underruns whenever all planes are disabled.
5005          * So diasble underrun reporting before all the planes get disabled.
5006          * FIXME: Need to fix the logic to work when we turn off all planes
5007          * but leave the pipe running.
5008          */
5009         if (IS_GEN2(dev))
5010                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5011
5012         /*
5013          * FIXME IPS should be fine as long as one plane is
5014          * enabled, but in practice it seems to have problems
5015          * when going from primary only to sprite only and vice
5016          * versa.
5017          */
5018         hsw_disable_ips(intel_crtc);
5019 }
5020
5021 /* FIXME get rid of this and use pre_plane_update */
5022 static void
5023 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct drm_i915_private *dev_priv = to_i915(dev);
5027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028         int pipe = intel_crtc->pipe;
5029
5030         intel_pre_disable_primary(crtc);
5031
5032         /*
5033          * Vblank time updates from the shadow to live plane control register
5034          * are blocked if the memory self-refresh mode is active at that
5035          * moment. So to make sure the plane gets truly disabled, disable
5036          * first the self-refresh mode. The self-refresh enable bit in turn
5037          * will be checked/applied by the HW only at the next frame start
5038          * event which is after the vblank start event, so we need to have a
5039          * wait-for-vblank between disabling the plane and the pipe.
5040          */
5041         if (HAS_GMCH_DISPLAY(dev_priv)) {
5042                 intel_set_memory_cxsr(dev_priv, false);
5043                 dev_priv->wm.vlv.cxsr = false;
5044                 intel_wait_for_vblank(dev, pipe);
5045         }
5046 }
5047
5048 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5049 {
5050         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5051         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5052         struct intel_crtc_state *pipe_config =
5053                 to_intel_crtc_state(crtc->base.state);
5054         struct drm_plane *primary = crtc->base.primary;
5055         struct drm_plane_state *old_pri_state =
5056                 drm_atomic_get_existing_plane_state(old_state, primary);
5057
5058         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5059
5060         crtc->wm.cxsr_allowed = true;
5061
5062         if (pipe_config->update_wm_post && pipe_config->base.active)
5063                 intel_update_watermarks(&crtc->base);
5064
5065         if (old_pri_state) {
5066                 struct intel_plane_state *primary_state =
5067                         to_intel_plane_state(primary->state);
5068                 struct intel_plane_state *old_primary_state =
5069                         to_intel_plane_state(old_pri_state);
5070
5071                 intel_fbc_post_update(crtc);
5072
5073                 if (primary_state->base.visible &&
5074                     (needs_modeset(&pipe_config->base) ||
5075                      !old_primary_state->base.visible))
5076                         intel_post_enable_primary(&crtc->base);
5077         }
5078 }
5079
5080 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5081 {
5082         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5083         struct drm_device *dev = crtc->base.dev;
5084         struct drm_i915_private *dev_priv = to_i915(dev);
5085         struct intel_crtc_state *pipe_config =
5086                 to_intel_crtc_state(crtc->base.state);
5087         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5088         struct drm_plane *primary = crtc->base.primary;
5089         struct drm_plane_state *old_pri_state =
5090                 drm_atomic_get_existing_plane_state(old_state, primary);
5091         bool modeset = needs_modeset(&pipe_config->base);
5092
5093         if (old_pri_state) {
5094                 struct intel_plane_state *primary_state =
5095                         to_intel_plane_state(primary->state);
5096                 struct intel_plane_state *old_primary_state =
5097                         to_intel_plane_state(old_pri_state);
5098
5099                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5100
5101                 if (old_primary_state->base.visible &&
5102                     (modeset || !primary_state->base.visible))
5103                         intel_pre_disable_primary(&crtc->base);
5104         }
5105
5106         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5107                 crtc->wm.cxsr_allowed = false;
5108
5109                 /*
5110                  * Vblank time updates from the shadow to live plane control register
5111                  * are blocked if the memory self-refresh mode is active at that
5112                  * moment. So to make sure the plane gets truly disabled, disable
5113                  * first the self-refresh mode. The self-refresh enable bit in turn
5114                  * will be checked/applied by the HW only at the next frame start
5115                  * event which is after the vblank start event, so we need to have a
5116                  * wait-for-vblank between disabling the plane and the pipe.
5117                  */
5118                 if (old_crtc_state->base.active) {
5119                         intel_set_memory_cxsr(dev_priv, false);
5120                         dev_priv->wm.vlv.cxsr = false;
5121                         intel_wait_for_vblank(dev, crtc->pipe);
5122                 }
5123         }
5124
5125         /*
5126          * IVB workaround: must disable low power watermarks for at least
5127          * one frame before enabling scaling.  LP watermarks can be re-enabled
5128          * when scaling is disabled.
5129          *
5130          * WaCxSRDisabledForSpriteScaling:ivb
5131          */
5132         if (pipe_config->disable_lp_wm) {
5133                 ilk_disable_lp_wm(dev);
5134                 intel_wait_for_vblank(dev, crtc->pipe);
5135         }
5136
5137         /*
5138          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5139          * watermark programming here.
5140          */
5141         if (needs_modeset(&pipe_config->base))
5142                 return;
5143
5144         /*
5145          * For platforms that support atomic watermarks, program the
5146          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5147          * will be the intermediate values that are safe for both pre- and
5148          * post- vblank; when vblank happens, the 'active' values will be set
5149          * to the final 'target' values and we'll do this again to get the
5150          * optimal watermarks.  For gen9+ platforms, the values we program here
5151          * will be the final target values which will get automatically latched
5152          * at vblank time; no further programming will be necessary.
5153          *
5154          * If a platform hasn't been transitioned to atomic watermarks yet,
5155          * we'll continue to update watermarks the old way, if flags tell
5156          * us to.
5157          */
5158         if (dev_priv->display.initial_watermarks != NULL)
5159                 dev_priv->display.initial_watermarks(pipe_config);
5160         else if (pipe_config->update_wm_pre)
5161                 intel_update_watermarks(&crtc->base);
5162 }
5163
5164 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5165 {
5166         struct drm_device *dev = crtc->dev;
5167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168         struct drm_plane *p;
5169         int pipe = intel_crtc->pipe;
5170
5171         intel_crtc_dpms_overlay_disable(intel_crtc);
5172
5173         drm_for_each_plane_mask(p, dev, plane_mask)
5174                 to_intel_plane(p)->disable_plane(p, crtc);
5175
5176         /*
5177          * FIXME: Once we grow proper nuclear flip support out of this we need
5178          * to compute the mask of flip planes precisely. For the time being
5179          * consider this a flip to a NULL plane.
5180          */
5181         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5182 }
5183
5184 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5185                                           struct intel_crtc_state *crtc_state,
5186                                           struct drm_atomic_state *old_state)
5187 {
5188         struct drm_connector_state *old_conn_state;
5189         struct drm_connector *conn;
5190         int i;
5191
5192         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5193                 struct drm_connector_state *conn_state = conn->state;
5194                 struct intel_encoder *encoder =
5195                         to_intel_encoder(conn_state->best_encoder);
5196
5197                 if (conn_state->crtc != crtc)
5198                         continue;
5199
5200                 if (encoder->pre_pll_enable)
5201                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5202         }
5203 }
5204
5205 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5206                                       struct intel_crtc_state *crtc_state,
5207                                       struct drm_atomic_state *old_state)
5208 {
5209         struct drm_connector_state *old_conn_state;
5210         struct drm_connector *conn;
5211         int i;
5212
5213         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5214                 struct drm_connector_state *conn_state = conn->state;
5215                 struct intel_encoder *encoder =
5216                         to_intel_encoder(conn_state->best_encoder);
5217
5218                 if (conn_state->crtc != crtc)
5219                         continue;
5220
5221                 if (encoder->pre_enable)
5222                         encoder->pre_enable(encoder, crtc_state, conn_state);
5223         }
5224 }
5225
5226 static void intel_encoders_enable(struct drm_crtc *crtc,
5227                                   struct intel_crtc_state *crtc_state,
5228                                   struct drm_atomic_state *old_state)
5229 {
5230         struct drm_connector_state *old_conn_state;
5231         struct drm_connector *conn;
5232         int i;
5233
5234         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5235                 struct drm_connector_state *conn_state = conn->state;
5236                 struct intel_encoder *encoder =
5237                         to_intel_encoder(conn_state->best_encoder);
5238
5239                 if (conn_state->crtc != crtc)
5240                         continue;
5241
5242                 encoder->enable(encoder, crtc_state, conn_state);
5243                 intel_opregion_notify_encoder(encoder, true);
5244         }
5245 }
5246
5247 static void intel_encoders_disable(struct drm_crtc *crtc,
5248                                    struct intel_crtc_state *old_crtc_state,
5249                                    struct drm_atomic_state *old_state)
5250 {
5251         struct drm_connector_state *old_conn_state;
5252         struct drm_connector *conn;
5253         int i;
5254
5255         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5256                 struct intel_encoder *encoder =
5257                         to_intel_encoder(old_conn_state->best_encoder);
5258
5259                 if (old_conn_state->crtc != crtc)
5260                         continue;
5261
5262                 intel_opregion_notify_encoder(encoder, false);
5263                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5264         }
5265 }
5266
5267 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5268                                         struct intel_crtc_state *old_crtc_state,
5269                                         struct drm_atomic_state *old_state)
5270 {
5271         struct drm_connector_state *old_conn_state;
5272         struct drm_connector *conn;
5273         int i;
5274
5275         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5276                 struct intel_encoder *encoder =
5277                         to_intel_encoder(old_conn_state->best_encoder);
5278
5279                 if (old_conn_state->crtc != crtc)
5280                         continue;
5281
5282                 if (encoder->post_disable)
5283                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5284         }
5285 }
5286
5287 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5288                                             struct intel_crtc_state *old_crtc_state,
5289                                             struct drm_atomic_state *old_state)
5290 {
5291         struct drm_connector_state *old_conn_state;
5292         struct drm_connector *conn;
5293         int i;
5294
5295         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5296                 struct intel_encoder *encoder =
5297                         to_intel_encoder(old_conn_state->best_encoder);
5298
5299                 if (old_conn_state->crtc != crtc)
5300                         continue;
5301
5302                 if (encoder->post_pll_disable)
5303                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5304         }
5305 }
5306
5307 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5308                                  struct drm_atomic_state *old_state)
5309 {
5310         struct drm_crtc *crtc = pipe_config->base.crtc;
5311         struct drm_device *dev = crtc->dev;
5312         struct drm_i915_private *dev_priv = to_i915(dev);
5313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5314         int pipe = intel_crtc->pipe;
5315
5316         if (WARN_ON(intel_crtc->active))
5317                 return;
5318
5319         /*
5320          * Sometimes spurious CPU pipe underruns happen during FDI
5321          * training, at least with VGA+HDMI cloning. Suppress them.
5322          *
5323          * On ILK we get an occasional spurious CPU pipe underruns
5324          * between eDP port A enable and vdd enable. Also PCH port
5325          * enable seems to result in the occasional CPU pipe underrun.
5326          *
5327          * Spurious PCH underruns also occur during PCH enabling.
5328          */
5329         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5330                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5331         if (intel_crtc->config->has_pch_encoder)
5332                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5333
5334         if (intel_crtc->config->has_pch_encoder)
5335                 intel_prepare_shared_dpll(intel_crtc);
5336
5337         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5338                 intel_dp_set_m_n(intel_crtc, M1_N1);
5339
5340         intel_set_pipe_timings(intel_crtc);
5341         intel_set_pipe_src_size(intel_crtc);
5342
5343         if (intel_crtc->config->has_pch_encoder) {
5344                 intel_cpu_transcoder_set_m_n(intel_crtc,
5345                                      &intel_crtc->config->fdi_m_n, NULL);
5346         }
5347
5348         ironlake_set_pipeconf(crtc);
5349
5350         intel_crtc->active = true;
5351
5352         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5353
5354         if (intel_crtc->config->has_pch_encoder) {
5355                 /* Note: FDI PLL enabling _must_ be done before we enable the
5356                  * cpu pipes, hence this is separate from all the other fdi/pch
5357                  * enabling. */
5358                 ironlake_fdi_pll_enable(intel_crtc);
5359         } else {
5360                 assert_fdi_tx_disabled(dev_priv, pipe);
5361                 assert_fdi_rx_disabled(dev_priv, pipe);
5362         }
5363
5364         ironlake_pfit_enable(intel_crtc);
5365
5366         /*
5367          * On ILK+ LUT must be loaded before the pipe is running but with
5368          * clocks enabled
5369          */
5370         intel_color_load_luts(&pipe_config->base);
5371
5372         if (dev_priv->display.initial_watermarks != NULL)
5373                 dev_priv->display.initial_watermarks(intel_crtc->config);
5374         intel_enable_pipe(intel_crtc);
5375
5376         if (intel_crtc->config->has_pch_encoder)
5377                 ironlake_pch_enable(crtc);
5378
5379         assert_vblank_disabled(crtc);
5380         drm_crtc_vblank_on(crtc);
5381
5382         intel_encoders_enable(crtc, pipe_config, old_state);
5383
5384         if (HAS_PCH_CPT(dev_priv))
5385                 cpt_verify_modeset(dev, intel_crtc->pipe);
5386
5387         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5388         if (intel_crtc->config->has_pch_encoder)
5389                 intel_wait_for_vblank(dev, pipe);
5390         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5391         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5392 }
5393
5394 /* IPS only exists on ULT machines and is tied to pipe A. */
5395 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5396 {
5397         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5398 }
5399
5400 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5401                                 struct drm_atomic_state *old_state)
5402 {
5403         struct drm_crtc *crtc = pipe_config->base.crtc;
5404         struct drm_device *dev = crtc->dev;
5405         struct drm_i915_private *dev_priv = to_i915(dev);
5406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5407         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5408         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5409
5410         if (WARN_ON(intel_crtc->active))
5411                 return;
5412
5413         if (intel_crtc->config->has_pch_encoder)
5414                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5415                                                       false);
5416
5417         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5418
5419         if (intel_crtc->config->shared_dpll)
5420                 intel_enable_shared_dpll(intel_crtc);
5421
5422         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5423                 intel_dp_set_m_n(intel_crtc, M1_N1);
5424
5425         if (!transcoder_is_dsi(cpu_transcoder))
5426                 intel_set_pipe_timings(intel_crtc);
5427
5428         intel_set_pipe_src_size(intel_crtc);
5429
5430         if (cpu_transcoder != TRANSCODER_EDP &&
5431             !transcoder_is_dsi(cpu_transcoder)) {
5432                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5433                            intel_crtc->config->pixel_multiplier - 1);
5434         }
5435
5436         if (intel_crtc->config->has_pch_encoder) {
5437                 intel_cpu_transcoder_set_m_n(intel_crtc,
5438                                      &intel_crtc->config->fdi_m_n, NULL);
5439         }
5440
5441         if (!transcoder_is_dsi(cpu_transcoder))
5442                 haswell_set_pipeconf(crtc);
5443
5444         haswell_set_pipemisc(crtc);
5445
5446         intel_color_set_csc(&pipe_config->base);
5447
5448         intel_crtc->active = true;
5449
5450         if (intel_crtc->config->has_pch_encoder)
5451                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5452         else
5453                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5454
5455         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5456
5457         if (intel_crtc->config->has_pch_encoder)
5458                 dev_priv->display.fdi_link_train(crtc);
5459
5460         if (!transcoder_is_dsi(cpu_transcoder))
5461                 intel_ddi_enable_pipe_clock(intel_crtc);
5462
5463         if (INTEL_INFO(dev)->gen >= 9)
5464                 skylake_pfit_enable(intel_crtc);
5465         else
5466                 ironlake_pfit_enable(intel_crtc);
5467
5468         /*
5469          * On ILK+ LUT must be loaded before the pipe is running but with
5470          * clocks enabled
5471          */
5472         intel_color_load_luts(&pipe_config->base);
5473
5474         intel_ddi_set_pipe_settings(crtc);
5475         if (!transcoder_is_dsi(cpu_transcoder))
5476                 intel_ddi_enable_transcoder_func(crtc);
5477
5478         if (dev_priv->display.initial_watermarks != NULL)
5479                 dev_priv->display.initial_watermarks(pipe_config);
5480         else
5481                 intel_update_watermarks(crtc);
5482
5483         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5484         if (!transcoder_is_dsi(cpu_transcoder))
5485                 intel_enable_pipe(intel_crtc);
5486
5487         if (intel_crtc->config->has_pch_encoder)
5488                 lpt_pch_enable(crtc);
5489
5490         if (intel_crtc->config->dp_encoder_is_mst)
5491                 intel_ddi_set_vc_payload_alloc(crtc, true);
5492
5493         assert_vblank_disabled(crtc);
5494         drm_crtc_vblank_on(crtc);
5495
5496         intel_encoders_enable(crtc, pipe_config, old_state);
5497
5498         if (intel_crtc->config->has_pch_encoder) {
5499                 intel_wait_for_vblank(dev, pipe);
5500                 intel_wait_for_vblank(dev, pipe);
5501                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5502                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5503                                                       true);
5504         }
5505
5506         /* If we change the relative order between pipe/planes enabling, we need
5507          * to change the workaround. */
5508         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5509         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5510                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5511                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5512         }
5513 }
5514
5515 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5516 {
5517         struct drm_device *dev = crtc->base.dev;
5518         struct drm_i915_private *dev_priv = to_i915(dev);
5519         int pipe = crtc->pipe;
5520
5521         /* To avoid upsetting the power well on haswell only disable the pfit if
5522          * it's in use. The hw state code will make sure we get this right. */
5523         if (force || crtc->config->pch_pfit.enabled) {
5524                 I915_WRITE(PF_CTL(pipe), 0);
5525                 I915_WRITE(PF_WIN_POS(pipe), 0);
5526                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5527         }
5528 }
5529
5530 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5531                                   struct drm_atomic_state *old_state)
5532 {
5533         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5534         struct drm_device *dev = crtc->dev;
5535         struct drm_i915_private *dev_priv = to_i915(dev);
5536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5537         int pipe = intel_crtc->pipe;
5538
5539         /*
5540          * Sometimes spurious CPU pipe underruns happen when the
5541          * pipe is already disabled, but FDI RX/TX is still enabled.
5542          * Happens at least with VGA+HDMI cloning. Suppress them.
5543          */
5544         if (intel_crtc->config->has_pch_encoder) {
5545                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5546                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5547         }
5548
5549         intel_encoders_disable(crtc, old_crtc_state, old_state);
5550
5551         drm_crtc_vblank_off(crtc);
5552         assert_vblank_disabled(crtc);
5553
5554         intel_disable_pipe(intel_crtc);
5555
5556         ironlake_pfit_disable(intel_crtc, false);
5557
5558         if (intel_crtc->config->has_pch_encoder)
5559                 ironlake_fdi_disable(crtc);
5560
5561         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5562
5563         if (intel_crtc->config->has_pch_encoder) {
5564                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5565
5566                 if (HAS_PCH_CPT(dev_priv)) {
5567                         i915_reg_t reg;
5568                         u32 temp;
5569
5570                         /* disable TRANS_DP_CTL */
5571                         reg = TRANS_DP_CTL(pipe);
5572                         temp = I915_READ(reg);
5573                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5574                                   TRANS_DP_PORT_SEL_MASK);
5575                         temp |= TRANS_DP_PORT_SEL_NONE;
5576                         I915_WRITE(reg, temp);
5577
5578                         /* disable DPLL_SEL */
5579                         temp = I915_READ(PCH_DPLL_SEL);
5580                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5581                         I915_WRITE(PCH_DPLL_SEL, temp);
5582                 }
5583
5584                 ironlake_fdi_pll_disable(intel_crtc);
5585         }
5586
5587         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5588         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5589 }
5590
5591 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5592                                  struct drm_atomic_state *old_state)
5593 {
5594         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5595         struct drm_device *dev = crtc->dev;
5596         struct drm_i915_private *dev_priv = to_i915(dev);
5597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5598         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5599
5600         if (intel_crtc->config->has_pch_encoder)
5601                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5602                                                       false);
5603
5604         intel_encoders_disable(crtc, old_crtc_state, old_state);
5605
5606         drm_crtc_vblank_off(crtc);
5607         assert_vblank_disabled(crtc);
5608
5609         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5610         if (!transcoder_is_dsi(cpu_transcoder))
5611                 intel_disable_pipe(intel_crtc);
5612
5613         if (intel_crtc->config->dp_encoder_is_mst)
5614                 intel_ddi_set_vc_payload_alloc(crtc, false);
5615
5616         if (!transcoder_is_dsi(cpu_transcoder))
5617                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5618
5619         if (INTEL_INFO(dev)->gen >= 9)
5620                 skylake_scaler_disable(intel_crtc);
5621         else
5622                 ironlake_pfit_disable(intel_crtc, false);
5623
5624         if (!transcoder_is_dsi(cpu_transcoder))
5625                 intel_ddi_disable_pipe_clock(intel_crtc);
5626
5627         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5628
5629         if (old_crtc_state->has_pch_encoder)
5630                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5631                                                       true);
5632 }
5633
5634 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5635 {
5636         struct drm_device *dev = crtc->base.dev;
5637         struct drm_i915_private *dev_priv = to_i915(dev);
5638         struct intel_crtc_state *pipe_config = crtc->config;
5639
5640         if (!pipe_config->gmch_pfit.control)
5641                 return;
5642
5643         /*
5644          * The panel fitter should only be adjusted whilst the pipe is disabled,
5645          * according to register description and PRM.
5646          */
5647         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5648         assert_pipe_disabled(dev_priv, crtc->pipe);
5649
5650         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5651         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5652
5653         /* Border color in case we don't scale up to the full screen. Black by
5654          * default, change to something else for debugging. */
5655         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5656 }
5657
5658 static enum intel_display_power_domain port_to_power_domain(enum port port)
5659 {
5660         switch (port) {
5661         case PORT_A:
5662                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5663         case PORT_B:
5664                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5665         case PORT_C:
5666                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5667         case PORT_D:
5668                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5669         case PORT_E:
5670                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5671         default:
5672                 MISSING_CASE(port);
5673                 return POWER_DOMAIN_PORT_OTHER;
5674         }
5675 }
5676
5677 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5678 {
5679         switch (port) {
5680         case PORT_A:
5681                 return POWER_DOMAIN_AUX_A;
5682         case PORT_B:
5683                 return POWER_DOMAIN_AUX_B;
5684         case PORT_C:
5685                 return POWER_DOMAIN_AUX_C;
5686         case PORT_D:
5687                 return POWER_DOMAIN_AUX_D;
5688         case PORT_E:
5689                 /* FIXME: Check VBT for actual wiring of PORT E */
5690                 return POWER_DOMAIN_AUX_D;
5691         default:
5692                 MISSING_CASE(port);
5693                 return POWER_DOMAIN_AUX_A;
5694         }
5695 }
5696
5697 enum intel_display_power_domain
5698 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5699 {
5700         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5701         struct intel_digital_port *intel_dig_port;
5702
5703         switch (intel_encoder->type) {
5704         case INTEL_OUTPUT_UNKNOWN:
5705                 /* Only DDI platforms should ever use this output type */
5706                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5707         case INTEL_OUTPUT_DP:
5708         case INTEL_OUTPUT_HDMI:
5709         case INTEL_OUTPUT_EDP:
5710                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5711                 return port_to_power_domain(intel_dig_port->port);
5712         case INTEL_OUTPUT_DP_MST:
5713                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5714                 return port_to_power_domain(intel_dig_port->port);
5715         case INTEL_OUTPUT_ANALOG:
5716                 return POWER_DOMAIN_PORT_CRT;
5717         case INTEL_OUTPUT_DSI:
5718                 return POWER_DOMAIN_PORT_DSI;
5719         default:
5720                 return POWER_DOMAIN_PORT_OTHER;
5721         }
5722 }
5723
5724 enum intel_display_power_domain
5725 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5726 {
5727         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5728         struct intel_digital_port *intel_dig_port;
5729
5730         switch (intel_encoder->type) {
5731         case INTEL_OUTPUT_UNKNOWN:
5732         case INTEL_OUTPUT_HDMI:
5733                 /*
5734                  * Only DDI platforms should ever use these output types.
5735                  * We can get here after the HDMI detect code has already set
5736                  * the type of the shared encoder. Since we can't be sure
5737                  * what's the status of the given connectors, play safe and
5738                  * run the DP detection too.
5739                  */
5740                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5741         case INTEL_OUTPUT_DP:
5742         case INTEL_OUTPUT_EDP:
5743                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5744                 return port_to_aux_power_domain(intel_dig_port->port);
5745         case INTEL_OUTPUT_DP_MST:
5746                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5747                 return port_to_aux_power_domain(intel_dig_port->port);
5748         default:
5749                 MISSING_CASE(intel_encoder->type);
5750                 return POWER_DOMAIN_AUX_A;
5751         }
5752 }
5753
5754 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5755                                             struct intel_crtc_state *crtc_state)
5756 {
5757         struct drm_device *dev = crtc->dev;
5758         struct drm_encoder *encoder;
5759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760         enum pipe pipe = intel_crtc->pipe;
5761         unsigned long mask;
5762         enum transcoder transcoder = crtc_state->cpu_transcoder;
5763
5764         if (!crtc_state->base.active)
5765                 return 0;
5766
5767         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5768         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5769         if (crtc_state->pch_pfit.enabled ||
5770             crtc_state->pch_pfit.force_thru)
5771                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5772
5773         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5774                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5775
5776                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5777         }
5778
5779         if (crtc_state->shared_dpll)
5780                 mask |= BIT(POWER_DOMAIN_PLLS);
5781
5782         return mask;
5783 }
5784
5785 static unsigned long
5786 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5787                                struct intel_crtc_state *crtc_state)
5788 {
5789         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791         enum intel_display_power_domain domain;
5792         unsigned long domains, new_domains, old_domains;
5793
5794         old_domains = intel_crtc->enabled_power_domains;
5795         intel_crtc->enabled_power_domains = new_domains =
5796                 get_crtc_power_domains(crtc, crtc_state);
5797
5798         domains = new_domains & ~old_domains;
5799
5800         for_each_power_domain(domain, domains)
5801                 intel_display_power_get(dev_priv, domain);
5802
5803         return old_domains & ~new_domains;
5804 }
5805
5806 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5807                                       unsigned long domains)
5808 {
5809         enum intel_display_power_domain domain;
5810
5811         for_each_power_domain(domain, domains)
5812                 intel_display_power_put(dev_priv, domain);
5813 }
5814
5815 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5816 {
5817         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5818
5819         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5820             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5821                 return max_cdclk_freq;
5822         else if (IS_CHERRYVIEW(dev_priv))
5823                 return max_cdclk_freq*95/100;
5824         else if (INTEL_INFO(dev_priv)->gen < 4)
5825                 return 2*max_cdclk_freq*90/100;
5826         else
5827                 return max_cdclk_freq*90/100;
5828 }
5829
5830 static int skl_calc_cdclk(int max_pixclk, int vco);
5831
5832 static void intel_update_max_cdclk(struct drm_device *dev)
5833 {
5834         struct drm_i915_private *dev_priv = to_i915(dev);
5835
5836         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5837                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5838                 int max_cdclk, vco;
5839
5840                 vco = dev_priv->skl_preferred_vco_freq;
5841                 WARN_ON(vco != 8100000 && vco != 8640000);
5842
5843                 /*
5844                  * Use the lower (vco 8640) cdclk values as a
5845                  * first guess. skl_calc_cdclk() will correct it
5846                  * if the preferred vco is 8100 instead.
5847                  */
5848                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5849                         max_cdclk = 617143;
5850                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5851                         max_cdclk = 540000;
5852                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5853                         max_cdclk = 432000;
5854                 else
5855                         max_cdclk = 308571;
5856
5857                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5858         } else if (IS_BROXTON(dev_priv)) {
5859                 dev_priv->max_cdclk_freq = 624000;
5860         } else if (IS_BROADWELL(dev_priv))  {
5861                 /*
5862                  * FIXME with extra cooling we can allow
5863                  * 540 MHz for ULX and 675 Mhz for ULT.
5864                  * How can we know if extra cooling is
5865                  * available? PCI ID, VTB, something else?
5866                  */
5867                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5868                         dev_priv->max_cdclk_freq = 450000;
5869                 else if (IS_BDW_ULX(dev_priv))
5870                         dev_priv->max_cdclk_freq = 450000;
5871                 else if (IS_BDW_ULT(dev_priv))
5872                         dev_priv->max_cdclk_freq = 540000;
5873                 else
5874                         dev_priv->max_cdclk_freq = 675000;
5875         } else if (IS_CHERRYVIEW(dev_priv)) {
5876                 dev_priv->max_cdclk_freq = 320000;
5877         } else if (IS_VALLEYVIEW(dev)) {
5878                 dev_priv->max_cdclk_freq = 400000;
5879         } else {
5880                 /* otherwise assume cdclk is fixed */
5881                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5882         }
5883
5884         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5885
5886         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5887                          dev_priv->max_cdclk_freq);
5888
5889         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5890                          dev_priv->max_dotclk_freq);
5891 }
5892
5893 static void intel_update_cdclk(struct drm_device *dev)
5894 {
5895         struct drm_i915_private *dev_priv = to_i915(dev);
5896
5897         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5898
5899         if (INTEL_GEN(dev_priv) >= 9)
5900                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5901                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5902                                  dev_priv->cdclk_pll.ref);
5903         else
5904                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5905                                  dev_priv->cdclk_freq);
5906
5907         /*
5908          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5909          * Programmng [sic] note: bit[9:2] should be programmed to the number
5910          * of cdclk that generates 4MHz reference clock freq which is used to
5911          * generate GMBus clock. This will vary with the cdclk freq.
5912          */
5913         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5914                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5915 }
5916
5917 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5918 static int skl_cdclk_decimal(int cdclk)
5919 {
5920         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5921 }
5922
5923 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5924 {
5925         int ratio;
5926
5927         if (cdclk == dev_priv->cdclk_pll.ref)
5928                 return 0;
5929
5930         switch (cdclk) {
5931         default:
5932                 MISSING_CASE(cdclk);
5933         case 144000:
5934         case 288000:
5935         case 384000:
5936         case 576000:
5937                 ratio = 60;
5938                 break;
5939         case 624000:
5940                 ratio = 65;
5941                 break;
5942         }
5943
5944         return dev_priv->cdclk_pll.ref * ratio;
5945 }
5946
5947 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5948 {
5949         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5950
5951         /* Timeout 200us */
5952         if (intel_wait_for_register(dev_priv,
5953                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5954                                     1))
5955                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5956
5957         dev_priv->cdclk_pll.vco = 0;
5958 }
5959
5960 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5961 {
5962         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5963         u32 val;
5964
5965         val = I915_READ(BXT_DE_PLL_CTL);
5966         val &= ~BXT_DE_PLL_RATIO_MASK;
5967         val |= BXT_DE_PLL_RATIO(ratio);
5968         I915_WRITE(BXT_DE_PLL_CTL, val);
5969
5970         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5971
5972         /* Timeout 200us */
5973         if (intel_wait_for_register(dev_priv,
5974                                     BXT_DE_PLL_ENABLE,
5975                                     BXT_DE_PLL_LOCK,
5976                                     BXT_DE_PLL_LOCK,
5977                                     1))
5978                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5979
5980         dev_priv->cdclk_pll.vco = vco;
5981 }
5982
5983 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5984 {
5985         u32 val, divider;
5986         int vco, ret;
5987
5988         vco = bxt_de_pll_vco(dev_priv, cdclk);
5989
5990         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5991
5992         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5993         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5994         case 8:
5995                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5996                 break;
5997         case 4:
5998                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5999                 break;
6000         case 3:
6001                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6002                 break;
6003         case 2:
6004                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6005                 break;
6006         default:
6007                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6008                 WARN_ON(vco != 0);
6009
6010                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6011                 break;
6012         }
6013
6014         /* Inform power controller of upcoming frequency change */
6015         mutex_lock(&dev_priv->rps.hw_lock);
6016         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6017                                       0x80000000);
6018         mutex_unlock(&dev_priv->rps.hw_lock);
6019
6020         if (ret) {
6021                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6022                           ret, cdclk);
6023                 return;
6024         }
6025
6026         if (dev_priv->cdclk_pll.vco != 0 &&
6027             dev_priv->cdclk_pll.vco != vco)
6028                 bxt_de_pll_disable(dev_priv);
6029
6030         if (dev_priv->cdclk_pll.vco != vco)
6031                 bxt_de_pll_enable(dev_priv, vco);
6032
6033         val = divider | skl_cdclk_decimal(cdclk);
6034         /*
6035          * FIXME if only the cd2x divider needs changing, it could be done
6036          * without shutting off the pipe (if only one pipe is active).
6037          */
6038         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6039         /*
6040          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6041          * enable otherwise.
6042          */
6043         if (cdclk >= 500000)
6044                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6045         I915_WRITE(CDCLK_CTL, val);
6046
6047         mutex_lock(&dev_priv->rps.hw_lock);
6048         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6049                                       DIV_ROUND_UP(cdclk, 25000));
6050         mutex_unlock(&dev_priv->rps.hw_lock);
6051
6052         if (ret) {
6053                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6054                           ret, cdclk);
6055                 return;
6056         }
6057
6058         intel_update_cdclk(&dev_priv->drm);
6059 }
6060
6061 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6062 {
6063         u32 cdctl, expected;
6064
6065         intel_update_cdclk(&dev_priv->drm);
6066
6067         if (dev_priv->cdclk_pll.vco == 0 ||
6068             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6069                 goto sanitize;
6070
6071         /* DPLL okay; verify the cdclock
6072          *
6073          * Some BIOS versions leave an incorrect decimal frequency value and
6074          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6075          * so sanitize this register.
6076          */
6077         cdctl = I915_READ(CDCLK_CTL);
6078         /*
6079          * Let's ignore the pipe field, since BIOS could have configured the
6080          * dividers both synching to an active pipe, or asynchronously
6081          * (PIPE_NONE).
6082          */
6083         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6084
6085         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6086                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6087         /*
6088          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6089          * enable otherwise.
6090          */
6091         if (dev_priv->cdclk_freq >= 500000)
6092                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6093
6094         if (cdctl == expected)
6095                 /* All well; nothing to sanitize */
6096                 return;
6097
6098 sanitize:
6099         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6100
6101         /* force cdclk programming */
6102         dev_priv->cdclk_freq = 0;
6103
6104         /* force full PLL disable + enable */
6105         dev_priv->cdclk_pll.vco = -1;
6106 }
6107
6108 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6109 {
6110         bxt_sanitize_cdclk(dev_priv);
6111
6112         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6113                 return;
6114
6115         /*
6116          * FIXME:
6117          * - The initial CDCLK needs to be read from VBT.
6118          *   Need to make this change after VBT has changes for BXT.
6119          */
6120         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6121 }
6122
6123 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6124 {
6125         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6126 }
6127
6128 static int skl_calc_cdclk(int max_pixclk, int vco)
6129 {
6130         if (vco == 8640000) {
6131                 if (max_pixclk > 540000)
6132                         return 617143;
6133                 else if (max_pixclk > 432000)
6134                         return 540000;
6135                 else if (max_pixclk > 308571)
6136                         return 432000;
6137                 else
6138                         return 308571;
6139         } else {
6140                 if (max_pixclk > 540000)
6141                         return 675000;
6142                 else if (max_pixclk > 450000)
6143                         return 540000;
6144                 else if (max_pixclk > 337500)
6145                         return 450000;
6146                 else
6147                         return 337500;
6148         }
6149 }
6150
6151 static void
6152 skl_dpll0_update(struct drm_i915_private *dev_priv)
6153 {
6154         u32 val;
6155
6156         dev_priv->cdclk_pll.ref = 24000;
6157         dev_priv->cdclk_pll.vco = 0;
6158
6159         val = I915_READ(LCPLL1_CTL);
6160         if ((val & LCPLL_PLL_ENABLE) == 0)
6161                 return;
6162
6163         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6164                 return;
6165
6166         val = I915_READ(DPLL_CTRL1);
6167
6168         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6169                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6170                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6171                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6172                 return;
6173
6174         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6175         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6176         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6177         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6178         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6179                 dev_priv->cdclk_pll.vco = 8100000;
6180                 break;
6181         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6182         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6183                 dev_priv->cdclk_pll.vco = 8640000;
6184                 break;
6185         default:
6186                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6187                 break;
6188         }
6189 }
6190
6191 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6192 {
6193         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6194
6195         dev_priv->skl_preferred_vco_freq = vco;
6196
6197         if (changed)
6198                 intel_update_max_cdclk(&dev_priv->drm);
6199 }
6200
6201 static void
6202 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6203 {
6204         int min_cdclk = skl_calc_cdclk(0, vco);
6205         u32 val;
6206
6207         WARN_ON(vco != 8100000 && vco != 8640000);
6208
6209         /* select the minimum CDCLK before enabling DPLL 0 */
6210         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6211         I915_WRITE(CDCLK_CTL, val);
6212         POSTING_READ(CDCLK_CTL);
6213
6214         /*
6215          * We always enable DPLL0 with the lowest link rate possible, but still
6216          * taking into account the VCO required to operate the eDP panel at the
6217          * desired frequency. The usual DP link rates operate with a VCO of
6218          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6219          * The modeset code is responsible for the selection of the exact link
6220          * rate later on, with the constraint of choosing a frequency that
6221          * works with vco.
6222          */
6223         val = I915_READ(DPLL_CTRL1);
6224
6225         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6226                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6227         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6228         if (vco == 8640000)
6229                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6230                                             SKL_DPLL0);
6231         else
6232                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6233                                             SKL_DPLL0);
6234
6235         I915_WRITE(DPLL_CTRL1, val);
6236         POSTING_READ(DPLL_CTRL1);
6237
6238         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6239
6240         if (intel_wait_for_register(dev_priv,
6241                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6242                                     5))
6243                 DRM_ERROR("DPLL0 not locked\n");
6244
6245         dev_priv->cdclk_pll.vco = vco;
6246
6247         /* We'll want to keep using the current vco from now on. */
6248         skl_set_preferred_cdclk_vco(dev_priv, vco);
6249 }
6250
6251 static void
6252 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6253 {
6254         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6255         if (intel_wait_for_register(dev_priv,
6256                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6257                                    1))
6258                 DRM_ERROR("Couldn't disable DPLL0\n");
6259
6260         dev_priv->cdclk_pll.vco = 0;
6261 }
6262
6263 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6264 {
6265         int ret;
6266         u32 val;
6267
6268         /* inform PCU we want to change CDCLK */
6269         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6270         mutex_lock(&dev_priv->rps.hw_lock);
6271         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6272         mutex_unlock(&dev_priv->rps.hw_lock);
6273
6274         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6275 }
6276
6277 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6278 {
6279         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6280 }
6281
6282 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6283 {
6284         struct drm_device *dev = &dev_priv->drm;
6285         u32 freq_select, pcu_ack;
6286
6287         WARN_ON((cdclk == 24000) != (vco == 0));
6288
6289         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6290
6291         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6292                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6293                 return;
6294         }
6295
6296         /* set CDCLK_CTL */
6297         switch (cdclk) {
6298         case 450000:
6299         case 432000:
6300                 freq_select = CDCLK_FREQ_450_432;
6301                 pcu_ack = 1;
6302                 break;
6303         case 540000:
6304                 freq_select = CDCLK_FREQ_540;
6305                 pcu_ack = 2;
6306                 break;
6307         case 308571:
6308         case 337500:
6309         default:
6310                 freq_select = CDCLK_FREQ_337_308;
6311                 pcu_ack = 0;
6312                 break;
6313         case 617143:
6314         case 675000:
6315                 freq_select = CDCLK_FREQ_675_617;
6316                 pcu_ack = 3;
6317                 break;
6318         }
6319
6320         if (dev_priv->cdclk_pll.vco != 0 &&
6321             dev_priv->cdclk_pll.vco != vco)
6322                 skl_dpll0_disable(dev_priv);
6323
6324         if (dev_priv->cdclk_pll.vco != vco)
6325                 skl_dpll0_enable(dev_priv, vco);
6326
6327         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6328         POSTING_READ(CDCLK_CTL);
6329
6330         /* inform PCU of the change */
6331         mutex_lock(&dev_priv->rps.hw_lock);
6332         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6333         mutex_unlock(&dev_priv->rps.hw_lock);
6334
6335         intel_update_cdclk(dev);
6336 }
6337
6338 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6339
6340 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6341 {
6342         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6343 }
6344
6345 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6346 {
6347         int cdclk, vco;
6348
6349         skl_sanitize_cdclk(dev_priv);
6350
6351         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6352                 /*
6353                  * Use the current vco as our initial
6354                  * guess as to what the preferred vco is.
6355                  */
6356                 if (dev_priv->skl_preferred_vco_freq == 0)
6357                         skl_set_preferred_cdclk_vco(dev_priv,
6358                                                     dev_priv->cdclk_pll.vco);
6359                 return;
6360         }
6361
6362         vco = dev_priv->skl_preferred_vco_freq;
6363         if (vco == 0)
6364                 vco = 8100000;
6365         cdclk = skl_calc_cdclk(0, vco);
6366
6367         skl_set_cdclk(dev_priv, cdclk, vco);
6368 }
6369
6370 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6371 {
6372         uint32_t cdctl, expected;
6373
6374         /*
6375          * check if the pre-os intialized the display
6376          * There is SWF18 scratchpad register defined which is set by the
6377          * pre-os which can be used by the OS drivers to check the status
6378          */
6379         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6380                 goto sanitize;
6381
6382         intel_update_cdclk(&dev_priv->drm);
6383         /* Is PLL enabled and locked ? */
6384         if (dev_priv->cdclk_pll.vco == 0 ||
6385             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6386                 goto sanitize;
6387
6388         /* DPLL okay; verify the cdclock
6389          *
6390          * Noticed in some instances that the freq selection is correct but
6391          * decimal part is programmed wrong from BIOS where pre-os does not
6392          * enable display. Verify the same as well.
6393          */
6394         cdctl = I915_READ(CDCLK_CTL);
6395         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6396                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6397         if (cdctl == expected)
6398                 /* All well; nothing to sanitize */
6399                 return;
6400
6401 sanitize:
6402         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6403
6404         /* force cdclk programming */
6405         dev_priv->cdclk_freq = 0;
6406         /* force full PLL disable + enable */
6407         dev_priv->cdclk_pll.vco = -1;
6408 }
6409
6410 /* Adjust CDclk dividers to allow high res or save power if possible */
6411 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6412 {
6413         struct drm_i915_private *dev_priv = to_i915(dev);
6414         u32 val, cmd;
6415
6416         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6417                                         != dev_priv->cdclk_freq);
6418
6419         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6420                 cmd = 2;
6421         else if (cdclk == 266667)
6422                 cmd = 1;
6423         else
6424                 cmd = 0;
6425
6426         mutex_lock(&dev_priv->rps.hw_lock);
6427         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6428         val &= ~DSPFREQGUAR_MASK;
6429         val |= (cmd << DSPFREQGUAR_SHIFT);
6430         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6431         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6432                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6433                      50)) {
6434                 DRM_ERROR("timed out waiting for CDclk change\n");
6435         }
6436         mutex_unlock(&dev_priv->rps.hw_lock);
6437
6438         mutex_lock(&dev_priv->sb_lock);
6439
6440         if (cdclk == 400000) {
6441                 u32 divider;
6442
6443                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6444
6445                 /* adjust cdclk divider */
6446                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6447                 val &= ~CCK_FREQUENCY_VALUES;
6448                 val |= divider;
6449                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6450
6451                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6452                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6453                              50))
6454                         DRM_ERROR("timed out waiting for CDclk change\n");
6455         }
6456
6457         /* adjust self-refresh exit latency value */
6458         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6459         val &= ~0x7f;
6460
6461         /*
6462          * For high bandwidth configs, we set a higher latency in the bunit
6463          * so that the core display fetch happens in time to avoid underruns.
6464          */
6465         if (cdclk == 400000)
6466                 val |= 4500 / 250; /* 4.5 usec */
6467         else
6468                 val |= 3000 / 250; /* 3.0 usec */
6469         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6470
6471         mutex_unlock(&dev_priv->sb_lock);
6472
6473         intel_update_cdclk(dev);
6474 }
6475
6476 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6477 {
6478         struct drm_i915_private *dev_priv = to_i915(dev);
6479         u32 val, cmd;
6480
6481         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6482                                                 != dev_priv->cdclk_freq);
6483
6484         switch (cdclk) {
6485         case 333333:
6486         case 320000:
6487         case 266667:
6488         case 200000:
6489                 break;
6490         default:
6491                 MISSING_CASE(cdclk);
6492                 return;
6493         }
6494
6495         /*
6496          * Specs are full of misinformation, but testing on actual
6497          * hardware has shown that we just need to write the desired
6498          * CCK divider into the Punit register.
6499          */
6500         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6501
6502         mutex_lock(&dev_priv->rps.hw_lock);
6503         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6504         val &= ~DSPFREQGUAR_MASK_CHV;
6505         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6506         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6507         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6508                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6509                      50)) {
6510                 DRM_ERROR("timed out waiting for CDclk change\n");
6511         }
6512         mutex_unlock(&dev_priv->rps.hw_lock);
6513
6514         intel_update_cdclk(dev);
6515 }
6516
6517 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6518                                  int max_pixclk)
6519 {
6520         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6521         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6522
6523         /*
6524          * Really only a few cases to deal with, as only 4 CDclks are supported:
6525          *   200MHz
6526          *   267MHz
6527          *   320/333MHz (depends on HPLL freq)
6528          *   400MHz (VLV only)
6529          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6530          * of the lower bin and adjust if needed.
6531          *
6532          * We seem to get an unstable or solid color picture at 200MHz.
6533          * Not sure what's wrong. For now use 200MHz only when all pipes
6534          * are off.
6535          */
6536         if (!IS_CHERRYVIEW(dev_priv) &&
6537             max_pixclk > freq_320*limit/100)
6538                 return 400000;
6539         else if (max_pixclk > 266667*limit/100)
6540                 return freq_320;
6541         else if (max_pixclk > 0)
6542                 return 266667;
6543         else
6544                 return 200000;
6545 }
6546
6547 static int bxt_calc_cdclk(int max_pixclk)
6548 {
6549         if (max_pixclk > 576000)
6550                 return 624000;
6551         else if (max_pixclk > 384000)
6552                 return 576000;
6553         else if (max_pixclk > 288000)
6554                 return 384000;
6555         else if (max_pixclk > 144000)
6556                 return 288000;
6557         else
6558                 return 144000;
6559 }
6560
6561 /* Compute the max pixel clock for new configuration. */
6562 static int intel_mode_max_pixclk(struct drm_device *dev,
6563                                  struct drm_atomic_state *state)
6564 {
6565         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6566         struct drm_i915_private *dev_priv = to_i915(dev);
6567         struct drm_crtc *crtc;
6568         struct drm_crtc_state *crtc_state;
6569         unsigned max_pixclk = 0, i;
6570         enum pipe pipe;
6571
6572         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6573                sizeof(intel_state->min_pixclk));
6574
6575         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6576                 int pixclk = 0;
6577
6578                 if (crtc_state->enable)
6579                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6580
6581                 intel_state->min_pixclk[i] = pixclk;
6582         }
6583
6584         for_each_pipe(dev_priv, pipe)
6585                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6586
6587         return max_pixclk;
6588 }
6589
6590 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6591 {
6592         struct drm_device *dev = state->dev;
6593         struct drm_i915_private *dev_priv = to_i915(dev);
6594         int max_pixclk = intel_mode_max_pixclk(dev, state);
6595         struct intel_atomic_state *intel_state =
6596                 to_intel_atomic_state(state);
6597
6598         intel_state->cdclk = intel_state->dev_cdclk =
6599                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6600
6601         if (!intel_state->active_crtcs)
6602                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6603
6604         return 0;
6605 }
6606
6607 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6608 {
6609         int max_pixclk = ilk_max_pixel_rate(state);
6610         struct intel_atomic_state *intel_state =
6611                 to_intel_atomic_state(state);
6612
6613         intel_state->cdclk = intel_state->dev_cdclk =
6614                 bxt_calc_cdclk(max_pixclk);
6615
6616         if (!intel_state->active_crtcs)
6617                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6618
6619         return 0;
6620 }
6621
6622 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6623 {
6624         unsigned int credits, default_credits;
6625
6626         if (IS_CHERRYVIEW(dev_priv))
6627                 default_credits = PFI_CREDIT(12);
6628         else
6629                 default_credits = PFI_CREDIT(8);
6630
6631         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6632                 /* CHV suggested value is 31 or 63 */
6633                 if (IS_CHERRYVIEW(dev_priv))
6634                         credits = PFI_CREDIT_63;
6635                 else
6636                         credits = PFI_CREDIT(15);
6637         } else {
6638                 credits = default_credits;
6639         }
6640
6641         /*
6642          * WA - write default credits before re-programming
6643          * FIXME: should we also set the resend bit here?
6644          */
6645         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6646                    default_credits);
6647
6648         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6649                    credits | PFI_CREDIT_RESEND);
6650
6651         /*
6652          * FIXME is this guaranteed to clear
6653          * immediately or should we poll for it?
6654          */
6655         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6656 }
6657
6658 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6659 {
6660         struct drm_device *dev = old_state->dev;
6661         struct drm_i915_private *dev_priv = to_i915(dev);
6662         struct intel_atomic_state *old_intel_state =
6663                 to_intel_atomic_state(old_state);
6664         unsigned req_cdclk = old_intel_state->dev_cdclk;
6665
6666         /*
6667          * FIXME: We can end up here with all power domains off, yet
6668          * with a CDCLK frequency other than the minimum. To account
6669          * for this take the PIPE-A power domain, which covers the HW
6670          * blocks needed for the following programming. This can be
6671          * removed once it's guaranteed that we get here either with
6672          * the minimum CDCLK set, or the required power domains
6673          * enabled.
6674          */
6675         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6676
6677         if (IS_CHERRYVIEW(dev_priv))
6678                 cherryview_set_cdclk(dev, req_cdclk);
6679         else
6680                 valleyview_set_cdclk(dev, req_cdclk);
6681
6682         vlv_program_pfi_credits(dev_priv);
6683
6684         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6685 }
6686
6687 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6688                                    struct drm_atomic_state *old_state)
6689 {
6690         struct drm_crtc *crtc = pipe_config->base.crtc;
6691         struct drm_device *dev = crtc->dev;
6692         struct drm_i915_private *dev_priv = to_i915(dev);
6693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6694         int pipe = intel_crtc->pipe;
6695
6696         if (WARN_ON(intel_crtc->active))
6697                 return;
6698
6699         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6700                 intel_dp_set_m_n(intel_crtc, M1_N1);
6701
6702         intel_set_pipe_timings(intel_crtc);
6703         intel_set_pipe_src_size(intel_crtc);
6704
6705         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6706                 struct drm_i915_private *dev_priv = to_i915(dev);
6707
6708                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6709                 I915_WRITE(CHV_CANVAS(pipe), 0);
6710         }
6711
6712         i9xx_set_pipeconf(intel_crtc);
6713
6714         intel_crtc->active = true;
6715
6716         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6717
6718         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6719
6720         if (IS_CHERRYVIEW(dev_priv)) {
6721                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6722                 chv_enable_pll(intel_crtc, intel_crtc->config);
6723         } else {
6724                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6725                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6726         }
6727
6728         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6729
6730         i9xx_pfit_enable(intel_crtc);
6731
6732         intel_color_load_luts(&pipe_config->base);
6733
6734         intel_update_watermarks(crtc);
6735         intel_enable_pipe(intel_crtc);
6736
6737         assert_vblank_disabled(crtc);
6738         drm_crtc_vblank_on(crtc);
6739
6740         intel_encoders_enable(crtc, pipe_config, old_state);
6741 }
6742
6743 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6744 {
6745         struct drm_device *dev = crtc->base.dev;
6746         struct drm_i915_private *dev_priv = to_i915(dev);
6747
6748         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6749         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6750 }
6751
6752 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6753                              struct drm_atomic_state *old_state)
6754 {
6755         struct drm_crtc *crtc = pipe_config->base.crtc;
6756         struct drm_device *dev = crtc->dev;
6757         struct drm_i915_private *dev_priv = to_i915(dev);
6758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6759         enum pipe pipe = intel_crtc->pipe;
6760
6761         if (WARN_ON(intel_crtc->active))
6762                 return;
6763
6764         i9xx_set_pll_dividers(intel_crtc);
6765
6766         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6767                 intel_dp_set_m_n(intel_crtc, M1_N1);
6768
6769         intel_set_pipe_timings(intel_crtc);
6770         intel_set_pipe_src_size(intel_crtc);
6771
6772         i9xx_set_pipeconf(intel_crtc);
6773
6774         intel_crtc->active = true;
6775
6776         if (!IS_GEN2(dev))
6777                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6778
6779         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6780
6781         i9xx_enable_pll(intel_crtc);
6782
6783         i9xx_pfit_enable(intel_crtc);
6784
6785         intel_color_load_luts(&pipe_config->base);
6786
6787         intel_update_watermarks(crtc);
6788         intel_enable_pipe(intel_crtc);
6789
6790         assert_vblank_disabled(crtc);
6791         drm_crtc_vblank_on(crtc);
6792
6793         intel_encoders_enable(crtc, pipe_config, old_state);
6794 }
6795
6796 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6797 {
6798         struct drm_device *dev = crtc->base.dev;
6799         struct drm_i915_private *dev_priv = to_i915(dev);
6800
6801         if (!crtc->config->gmch_pfit.control)
6802                 return;
6803
6804         assert_pipe_disabled(dev_priv, crtc->pipe);
6805
6806         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6807                          I915_READ(PFIT_CONTROL));
6808         I915_WRITE(PFIT_CONTROL, 0);
6809 }
6810
6811 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6812                               struct drm_atomic_state *old_state)
6813 {
6814         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6815         struct drm_device *dev = crtc->dev;
6816         struct drm_i915_private *dev_priv = to_i915(dev);
6817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6818         int pipe = intel_crtc->pipe;
6819
6820         /*
6821          * On gen2 planes are double buffered but the pipe isn't, so we must
6822          * wait for planes to fully turn off before disabling the pipe.
6823          */
6824         if (IS_GEN2(dev))
6825                 intel_wait_for_vblank(dev, pipe);
6826
6827         intel_encoders_disable(crtc, old_crtc_state, old_state);
6828
6829         drm_crtc_vblank_off(crtc);
6830         assert_vblank_disabled(crtc);
6831
6832         intel_disable_pipe(intel_crtc);
6833
6834         i9xx_pfit_disable(intel_crtc);
6835
6836         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6837
6838         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6839                 if (IS_CHERRYVIEW(dev_priv))
6840                         chv_disable_pll(dev_priv, pipe);
6841                 else if (IS_VALLEYVIEW(dev))
6842                         vlv_disable_pll(dev_priv, pipe);
6843                 else
6844                         i9xx_disable_pll(intel_crtc);
6845         }
6846
6847         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6848
6849         if (!IS_GEN2(dev))
6850                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6851 }
6852
6853 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6854 {
6855         struct intel_encoder *encoder;
6856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6857         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6858         enum intel_display_power_domain domain;
6859         unsigned long domains;
6860         struct drm_atomic_state *state;
6861         struct intel_crtc_state *crtc_state;
6862         int ret;
6863
6864         if (!intel_crtc->active)
6865                 return;
6866
6867         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6868                 WARN_ON(intel_crtc->flip_work);
6869
6870                 intel_pre_disable_primary_noatomic(crtc);
6871
6872                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6873                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6874         }
6875
6876         state = drm_atomic_state_alloc(crtc->dev);
6877         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6878
6879         /* Everything's already locked, -EDEADLK can't happen. */
6880         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6881         ret = drm_atomic_add_affected_connectors(state, crtc);
6882
6883         WARN_ON(IS_ERR(crtc_state) || ret);
6884
6885         dev_priv->display.crtc_disable(crtc_state, state);
6886
6887         drm_atomic_state_free(state);
6888
6889         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6890                       crtc->base.id, crtc->name);
6891
6892         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6893         crtc->state->active = false;
6894         intel_crtc->active = false;
6895         crtc->enabled = false;
6896         crtc->state->connector_mask = 0;
6897         crtc->state->encoder_mask = 0;
6898
6899         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6900                 encoder->base.crtc = NULL;
6901
6902         intel_fbc_disable(intel_crtc);
6903         intel_update_watermarks(crtc);
6904         intel_disable_shared_dpll(intel_crtc);
6905
6906         domains = intel_crtc->enabled_power_domains;
6907         for_each_power_domain(domain, domains)
6908                 intel_display_power_put(dev_priv, domain);
6909         intel_crtc->enabled_power_domains = 0;
6910
6911         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6912         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6913 }
6914
6915 /*
6916  * turn all crtc's off, but do not adjust state
6917  * This has to be paired with a call to intel_modeset_setup_hw_state.
6918  */
6919 int intel_display_suspend(struct drm_device *dev)
6920 {
6921         struct drm_i915_private *dev_priv = to_i915(dev);
6922         struct drm_atomic_state *state;
6923         int ret;
6924
6925         state = drm_atomic_helper_suspend(dev);
6926         ret = PTR_ERR_OR_ZERO(state);
6927         if (ret)
6928                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6929         else
6930                 dev_priv->modeset_restore_state = state;
6931         return ret;
6932 }
6933
6934 void intel_encoder_destroy(struct drm_encoder *encoder)
6935 {
6936         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6937
6938         drm_encoder_cleanup(encoder);
6939         kfree(intel_encoder);
6940 }
6941
6942 /* Cross check the actual hw state with our own modeset state tracking (and it's
6943  * internal consistency). */
6944 static void intel_connector_verify_state(struct intel_connector *connector)
6945 {
6946         struct drm_crtc *crtc = connector->base.state->crtc;
6947
6948         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6949                       connector->base.base.id,
6950                       connector->base.name);
6951
6952         if (connector->get_hw_state(connector)) {
6953                 struct intel_encoder *encoder = connector->encoder;
6954                 struct drm_connector_state *conn_state = connector->base.state;
6955
6956                 I915_STATE_WARN(!crtc,
6957                          "connector enabled without attached crtc\n");
6958
6959                 if (!crtc)
6960                         return;
6961
6962                 I915_STATE_WARN(!crtc->state->active,
6963                       "connector is active, but attached crtc isn't\n");
6964
6965                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6966                         return;
6967
6968                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6969                         "atomic encoder doesn't match attached encoder\n");
6970
6971                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6972                         "attached encoder crtc differs from connector crtc\n");
6973         } else {
6974                 I915_STATE_WARN(crtc && crtc->state->active,
6975                         "attached crtc is active, but connector isn't\n");
6976                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6977                         "best encoder set without crtc!\n");
6978         }
6979 }
6980
6981 int intel_connector_init(struct intel_connector *connector)
6982 {
6983         drm_atomic_helper_connector_reset(&connector->base);
6984
6985         if (!connector->base.state)
6986                 return -ENOMEM;
6987
6988         return 0;
6989 }
6990
6991 struct intel_connector *intel_connector_alloc(void)
6992 {
6993         struct intel_connector *connector;
6994
6995         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6996         if (!connector)
6997                 return NULL;
6998
6999         if (intel_connector_init(connector) < 0) {
7000                 kfree(connector);
7001                 return NULL;
7002         }
7003
7004         return connector;
7005 }
7006
7007 /* Simple connector->get_hw_state implementation for encoders that support only
7008  * one connector and no cloning and hence the encoder state determines the state
7009  * of the connector. */
7010 bool intel_connector_get_hw_state(struct intel_connector *connector)
7011 {
7012         enum pipe pipe = 0;
7013         struct intel_encoder *encoder = connector->encoder;
7014
7015         return encoder->get_hw_state(encoder, &pipe);
7016 }
7017
7018 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7019 {
7020         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7021                 return crtc_state->fdi_lanes;
7022
7023         return 0;
7024 }
7025
7026 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7027                                      struct intel_crtc_state *pipe_config)
7028 {
7029         struct drm_i915_private *dev_priv = to_i915(dev);
7030         struct drm_atomic_state *state = pipe_config->base.state;
7031         struct intel_crtc *other_crtc;
7032         struct intel_crtc_state *other_crtc_state;
7033
7034         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7035                       pipe_name(pipe), pipe_config->fdi_lanes);
7036         if (pipe_config->fdi_lanes > 4) {
7037                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7038                               pipe_name(pipe), pipe_config->fdi_lanes);
7039                 return -EINVAL;
7040         }
7041
7042         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7043                 if (pipe_config->fdi_lanes > 2) {
7044                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7045                                       pipe_config->fdi_lanes);
7046                         return -EINVAL;
7047                 } else {
7048                         return 0;
7049                 }
7050         }
7051
7052         if (INTEL_INFO(dev)->num_pipes == 2)
7053                 return 0;
7054
7055         /* Ivybridge 3 pipe is really complicated */
7056         switch (pipe) {
7057         case PIPE_A:
7058                 return 0;
7059         case PIPE_B:
7060                 if (pipe_config->fdi_lanes <= 2)
7061                         return 0;
7062
7063                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7064                 other_crtc_state =
7065                         intel_atomic_get_crtc_state(state, other_crtc);
7066                 if (IS_ERR(other_crtc_state))
7067                         return PTR_ERR(other_crtc_state);
7068
7069                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7070                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7071                                       pipe_name(pipe), pipe_config->fdi_lanes);
7072                         return -EINVAL;
7073                 }
7074                 return 0;
7075         case PIPE_C:
7076                 if (pipe_config->fdi_lanes > 2) {
7077                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7078                                       pipe_name(pipe), pipe_config->fdi_lanes);
7079                         return -EINVAL;
7080                 }
7081
7082                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7083                 other_crtc_state =
7084                         intel_atomic_get_crtc_state(state, other_crtc);
7085                 if (IS_ERR(other_crtc_state))
7086                         return PTR_ERR(other_crtc_state);
7087
7088                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7089                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7090                         return -EINVAL;
7091                 }
7092                 return 0;
7093         default:
7094                 BUG();
7095         }
7096 }
7097
7098 #define RETRY 1
7099 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7100                                        struct intel_crtc_state *pipe_config)
7101 {
7102         struct drm_device *dev = intel_crtc->base.dev;
7103         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7104         int lane, link_bw, fdi_dotclock, ret;
7105         bool needs_recompute = false;
7106
7107 retry:
7108         /* FDI is a binary signal running at ~2.7GHz, encoding
7109          * each output octet as 10 bits. The actual frequency
7110          * is stored as a divider into a 100MHz clock, and the
7111          * mode pixel clock is stored in units of 1KHz.
7112          * Hence the bw of each lane in terms of the mode signal
7113          * is:
7114          */
7115         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7116
7117         fdi_dotclock = adjusted_mode->crtc_clock;
7118
7119         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7120                                            pipe_config->pipe_bpp);
7121
7122         pipe_config->fdi_lanes = lane;
7123
7124         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7125                                link_bw, &pipe_config->fdi_m_n);
7126
7127         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7128         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7129                 pipe_config->pipe_bpp -= 2*3;
7130                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7131                               pipe_config->pipe_bpp);
7132                 needs_recompute = true;
7133                 pipe_config->bw_constrained = true;
7134
7135                 goto retry;
7136         }
7137
7138         if (needs_recompute)
7139                 return RETRY;
7140
7141         return ret;
7142 }
7143
7144 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7145                                      struct intel_crtc_state *pipe_config)
7146 {
7147         if (pipe_config->pipe_bpp > 24)
7148                 return false;
7149
7150         /* HSW can handle pixel rate up to cdclk? */
7151         if (IS_HASWELL(dev_priv))
7152                 return true;
7153
7154         /*
7155          * We compare against max which means we must take
7156          * the increased cdclk requirement into account when
7157          * calculating the new cdclk.
7158          *
7159          * Should measure whether using a lower cdclk w/o IPS
7160          */
7161         return ilk_pipe_pixel_rate(pipe_config) <=
7162                 dev_priv->max_cdclk_freq * 95 / 100;
7163 }
7164
7165 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7166                                    struct intel_crtc_state *pipe_config)
7167 {
7168         struct drm_device *dev = crtc->base.dev;
7169         struct drm_i915_private *dev_priv = to_i915(dev);
7170
7171         pipe_config->ips_enabled = i915.enable_ips &&
7172                 hsw_crtc_supports_ips(crtc) &&
7173                 pipe_config_supports_ips(dev_priv, pipe_config);
7174 }
7175
7176 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7177 {
7178         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7179
7180         /* GDG double wide on either pipe, otherwise pipe A only */
7181         return INTEL_INFO(dev_priv)->gen < 4 &&
7182                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7183 }
7184
7185 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7186                                      struct intel_crtc_state *pipe_config)
7187 {
7188         struct drm_device *dev = crtc->base.dev;
7189         struct drm_i915_private *dev_priv = to_i915(dev);
7190         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7191         int clock_limit = dev_priv->max_dotclk_freq;
7192
7193         if (INTEL_INFO(dev)->gen < 4) {
7194                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7195
7196                 /*
7197                  * Enable double wide mode when the dot clock
7198                  * is > 90% of the (display) core speed.
7199                  */
7200                 if (intel_crtc_supports_double_wide(crtc) &&
7201                     adjusted_mode->crtc_clock > clock_limit) {
7202                         clock_limit = dev_priv->max_dotclk_freq;
7203                         pipe_config->double_wide = true;
7204                 }
7205         }
7206
7207         if (adjusted_mode->crtc_clock > clock_limit) {
7208                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7209                               adjusted_mode->crtc_clock, clock_limit,
7210                               yesno(pipe_config->double_wide));
7211                 return -EINVAL;
7212         }
7213
7214         /*
7215          * Pipe horizontal size must be even in:
7216          * - DVO ganged mode
7217          * - LVDS dual channel mode
7218          * - Double wide pipe
7219          */
7220         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7221              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7222                 pipe_config->pipe_src_w &= ~1;
7223
7224         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7225          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7226          */
7227         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7228                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7229                 return -EINVAL;
7230
7231         if (HAS_IPS(dev_priv))
7232                 hsw_compute_ips_config(crtc, pipe_config);
7233
7234         if (pipe_config->has_pch_encoder)
7235                 return ironlake_fdi_compute_config(crtc, pipe_config);
7236
7237         return 0;
7238 }
7239
7240 static int skylake_get_display_clock_speed(struct drm_device *dev)
7241 {
7242         struct drm_i915_private *dev_priv = to_i915(dev);
7243         uint32_t cdctl;
7244
7245         skl_dpll0_update(dev_priv);
7246
7247         if (dev_priv->cdclk_pll.vco == 0)
7248                 return dev_priv->cdclk_pll.ref;
7249
7250         cdctl = I915_READ(CDCLK_CTL);
7251
7252         if (dev_priv->cdclk_pll.vco == 8640000) {
7253                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7254                 case CDCLK_FREQ_450_432:
7255                         return 432000;
7256                 case CDCLK_FREQ_337_308:
7257                         return 308571;
7258                 case CDCLK_FREQ_540:
7259                         return 540000;
7260                 case CDCLK_FREQ_675_617:
7261                         return 617143;
7262                 default:
7263                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7264                 }
7265         } else {
7266                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7267                 case CDCLK_FREQ_450_432:
7268                         return 450000;
7269                 case CDCLK_FREQ_337_308:
7270                         return 337500;
7271                 case CDCLK_FREQ_540:
7272                         return 540000;
7273                 case CDCLK_FREQ_675_617:
7274                         return 675000;
7275                 default:
7276                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7277                 }
7278         }
7279
7280         return dev_priv->cdclk_pll.ref;
7281 }
7282
7283 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7284 {
7285         u32 val;
7286
7287         dev_priv->cdclk_pll.ref = 19200;
7288         dev_priv->cdclk_pll.vco = 0;
7289
7290         val = I915_READ(BXT_DE_PLL_ENABLE);
7291         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7292                 return;
7293
7294         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7295                 return;
7296
7297         val = I915_READ(BXT_DE_PLL_CTL);
7298         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7299                 dev_priv->cdclk_pll.ref;
7300 }
7301
7302 static int broxton_get_display_clock_speed(struct drm_device *dev)
7303 {
7304         struct drm_i915_private *dev_priv = to_i915(dev);
7305         u32 divider;
7306         int div, vco;
7307
7308         bxt_de_pll_update(dev_priv);
7309
7310         vco = dev_priv->cdclk_pll.vco;
7311         if (vco == 0)
7312                 return dev_priv->cdclk_pll.ref;
7313
7314         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7315
7316         switch (divider) {
7317         case BXT_CDCLK_CD2X_DIV_SEL_1:
7318                 div = 2;
7319                 break;
7320         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7321                 div = 3;
7322                 break;
7323         case BXT_CDCLK_CD2X_DIV_SEL_2:
7324                 div = 4;
7325                 break;
7326         case BXT_CDCLK_CD2X_DIV_SEL_4:
7327                 div = 8;
7328                 break;
7329         default:
7330                 MISSING_CASE(divider);
7331                 return dev_priv->cdclk_pll.ref;
7332         }
7333
7334         return DIV_ROUND_CLOSEST(vco, div);
7335 }
7336
7337 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7338 {
7339         struct drm_i915_private *dev_priv = to_i915(dev);
7340         uint32_t lcpll = I915_READ(LCPLL_CTL);
7341         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7342
7343         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7344                 return 800000;
7345         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7346                 return 450000;
7347         else if (freq == LCPLL_CLK_FREQ_450)
7348                 return 450000;
7349         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7350                 return 540000;
7351         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7352                 return 337500;
7353         else
7354                 return 675000;
7355 }
7356
7357 static int haswell_get_display_clock_speed(struct drm_device *dev)
7358 {
7359         struct drm_i915_private *dev_priv = to_i915(dev);
7360         uint32_t lcpll = I915_READ(LCPLL_CTL);
7361         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7362
7363         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7364                 return 800000;
7365         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7366                 return 450000;
7367         else if (freq == LCPLL_CLK_FREQ_450)
7368                 return 450000;
7369         else if (IS_HSW_ULT(dev_priv))
7370                 return 337500;
7371         else
7372                 return 540000;
7373 }
7374
7375 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7376 {
7377         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7378                                       CCK_DISPLAY_CLOCK_CONTROL);
7379 }
7380
7381 static int ilk_get_display_clock_speed(struct drm_device *dev)
7382 {
7383         return 450000;
7384 }
7385
7386 static int i945_get_display_clock_speed(struct drm_device *dev)
7387 {
7388         return 400000;
7389 }
7390
7391 static int i915_get_display_clock_speed(struct drm_device *dev)
7392 {
7393         return 333333;
7394 }
7395
7396 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7397 {
7398         return 200000;
7399 }
7400
7401 static int pnv_get_display_clock_speed(struct drm_device *dev)
7402 {
7403         struct pci_dev *pdev = dev->pdev;
7404         u16 gcfgc = 0;
7405
7406         pci_read_config_word(pdev, GCFGC, &gcfgc);
7407
7408         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7409         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7410                 return 266667;
7411         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7412                 return 333333;
7413         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7414                 return 444444;
7415         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7416                 return 200000;
7417         default:
7418                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7419         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7420                 return 133333;
7421         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7422                 return 166667;
7423         }
7424 }
7425
7426 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7427 {
7428         struct pci_dev *pdev = dev->pdev;
7429         u16 gcfgc = 0;
7430
7431         pci_read_config_word(pdev, GCFGC, &gcfgc);
7432
7433         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7434                 return 133333;
7435         else {
7436                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7437                 case GC_DISPLAY_CLOCK_333_MHZ:
7438                         return 333333;
7439                 default:
7440                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7441                         return 190000;
7442                 }
7443         }
7444 }
7445
7446 static int i865_get_display_clock_speed(struct drm_device *dev)
7447 {
7448         return 266667;
7449 }
7450
7451 static int i85x_get_display_clock_speed(struct drm_device *dev)
7452 {
7453         struct pci_dev *pdev = dev->pdev;
7454         u16 hpllcc = 0;
7455
7456         /*
7457          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7458          * encoding is different :(
7459          * FIXME is this the right way to detect 852GM/852GMV?
7460          */
7461         if (pdev->revision == 0x1)
7462                 return 133333;
7463
7464         pci_bus_read_config_word(pdev->bus,
7465                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7466
7467         /* Assume that the hardware is in the high speed state.  This
7468          * should be the default.
7469          */
7470         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7471         case GC_CLOCK_133_200:
7472         case GC_CLOCK_133_200_2:
7473         case GC_CLOCK_100_200:
7474                 return 200000;
7475         case GC_CLOCK_166_250:
7476                 return 250000;
7477         case GC_CLOCK_100_133:
7478                 return 133333;
7479         case GC_CLOCK_133_266:
7480         case GC_CLOCK_133_266_2:
7481         case GC_CLOCK_166_266:
7482                 return 266667;
7483         }
7484
7485         /* Shouldn't happen */
7486         return 0;
7487 }
7488
7489 static int i830_get_display_clock_speed(struct drm_device *dev)
7490 {
7491         return 133333;
7492 }
7493
7494 static unsigned int intel_hpll_vco(struct drm_device *dev)
7495 {
7496         struct drm_i915_private *dev_priv = to_i915(dev);
7497         static const unsigned int blb_vco[8] = {
7498                 [0] = 3200000,
7499                 [1] = 4000000,
7500                 [2] = 5333333,
7501                 [3] = 4800000,
7502                 [4] = 6400000,
7503         };
7504         static const unsigned int pnv_vco[8] = {
7505                 [0] = 3200000,
7506                 [1] = 4000000,
7507                 [2] = 5333333,
7508                 [3] = 4800000,
7509                 [4] = 2666667,
7510         };
7511         static const unsigned int cl_vco[8] = {
7512                 [0] = 3200000,
7513                 [1] = 4000000,
7514                 [2] = 5333333,
7515                 [3] = 6400000,
7516                 [4] = 3333333,
7517                 [5] = 3566667,
7518                 [6] = 4266667,
7519         };
7520         static const unsigned int elk_vco[8] = {
7521                 [0] = 3200000,
7522                 [1] = 4000000,
7523                 [2] = 5333333,
7524                 [3] = 4800000,
7525         };
7526         static const unsigned int ctg_vco[8] = {
7527                 [0] = 3200000,
7528                 [1] = 4000000,
7529                 [2] = 5333333,
7530                 [3] = 6400000,
7531                 [4] = 2666667,
7532                 [5] = 4266667,
7533         };
7534         const unsigned int *vco_table;
7535         unsigned int vco;
7536         uint8_t tmp = 0;
7537
7538         /* FIXME other chipsets? */
7539         if (IS_GM45(dev_priv))
7540                 vco_table = ctg_vco;
7541         else if (IS_G4X(dev_priv))
7542                 vco_table = elk_vco;
7543         else if (IS_CRESTLINE(dev))
7544                 vco_table = cl_vco;
7545         else if (IS_PINEVIEW(dev))
7546                 vco_table = pnv_vco;
7547         else if (IS_G33(dev))
7548                 vco_table = blb_vco;
7549         else
7550                 return 0;
7551
7552         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7553
7554         vco = vco_table[tmp & 0x7];
7555         if (vco == 0)
7556                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7557         else
7558                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7559
7560         return vco;
7561 }
7562
7563 static int gm45_get_display_clock_speed(struct drm_device *dev)
7564 {
7565         struct pci_dev *pdev = dev->pdev;
7566         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7567         uint16_t tmp = 0;
7568
7569         pci_read_config_word(pdev, GCFGC, &tmp);
7570
7571         cdclk_sel = (tmp >> 12) & 0x1;
7572
7573         switch (vco) {
7574         case 2666667:
7575         case 4000000:
7576         case 5333333:
7577                 return cdclk_sel ? 333333 : 222222;
7578         case 3200000:
7579                 return cdclk_sel ? 320000 : 228571;
7580         default:
7581                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7582                 return 222222;
7583         }
7584 }
7585
7586 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7587 {
7588         struct pci_dev *pdev = dev->pdev;
7589         static const uint8_t div_3200[] = { 16, 10,  8 };
7590         static const uint8_t div_4000[] = { 20, 12, 10 };
7591         static const uint8_t div_5333[] = { 24, 16, 14 };
7592         const uint8_t *div_table;
7593         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7594         uint16_t tmp = 0;
7595
7596         pci_read_config_word(pdev, GCFGC, &tmp);
7597
7598         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7599
7600         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7601                 goto fail;
7602
7603         switch (vco) {
7604         case 3200000:
7605                 div_table = div_3200;
7606                 break;
7607         case 4000000:
7608                 div_table = div_4000;
7609                 break;
7610         case 5333333:
7611                 div_table = div_5333;
7612                 break;
7613         default:
7614                 goto fail;
7615         }
7616
7617         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7618
7619 fail:
7620         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7621         return 200000;
7622 }
7623
7624 static int g33_get_display_clock_speed(struct drm_device *dev)
7625 {
7626         struct pci_dev *pdev = dev->pdev;
7627         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7628         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7629         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7630         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7631         const uint8_t *div_table;
7632         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7633         uint16_t tmp = 0;
7634
7635         pci_read_config_word(pdev, GCFGC, &tmp);
7636
7637         cdclk_sel = (tmp >> 4) & 0x7;
7638
7639         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7640                 goto fail;
7641
7642         switch (vco) {
7643         case 3200000:
7644                 div_table = div_3200;
7645                 break;
7646         case 4000000:
7647                 div_table = div_4000;
7648                 break;
7649         case 4800000:
7650                 div_table = div_4800;
7651                 break;
7652         case 5333333:
7653                 div_table = div_5333;
7654                 break;
7655         default:
7656                 goto fail;
7657         }
7658
7659         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7660
7661 fail:
7662         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7663         return 190476;
7664 }
7665
7666 static void
7667 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7668 {
7669         while (*num > DATA_LINK_M_N_MASK ||
7670                *den > DATA_LINK_M_N_MASK) {
7671                 *num >>= 1;
7672                 *den >>= 1;
7673         }
7674 }
7675
7676 static void compute_m_n(unsigned int m, unsigned int n,
7677                         uint32_t *ret_m, uint32_t *ret_n)
7678 {
7679         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7680         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7681         intel_reduce_m_n_ratio(ret_m, ret_n);
7682 }
7683
7684 void
7685 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7686                        int pixel_clock, int link_clock,
7687                        struct intel_link_m_n *m_n)
7688 {
7689         m_n->tu = 64;
7690
7691         compute_m_n(bits_per_pixel * pixel_clock,
7692                     link_clock * nlanes * 8,
7693                     &m_n->gmch_m, &m_n->gmch_n);
7694
7695         compute_m_n(pixel_clock, link_clock,
7696                     &m_n->link_m, &m_n->link_n);
7697 }
7698
7699 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7700 {
7701         if (i915.panel_use_ssc >= 0)
7702                 return i915.panel_use_ssc != 0;
7703         return dev_priv->vbt.lvds_use_ssc
7704                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7705 }
7706
7707 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7708 {
7709         return (1 << dpll->n) << 16 | dpll->m2;
7710 }
7711
7712 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7713 {
7714         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7715 }
7716
7717 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7718                                      struct intel_crtc_state *crtc_state,
7719                                      struct dpll *reduced_clock)
7720 {
7721         struct drm_device *dev = crtc->base.dev;
7722         u32 fp, fp2 = 0;
7723
7724         if (IS_PINEVIEW(dev)) {
7725                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7726                 if (reduced_clock)
7727                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7728         } else {
7729                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7730                 if (reduced_clock)
7731                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7732         }
7733
7734         crtc_state->dpll_hw_state.fp0 = fp;
7735
7736         crtc->lowfreq_avail = false;
7737         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7738             reduced_clock) {
7739                 crtc_state->dpll_hw_state.fp1 = fp2;
7740                 crtc->lowfreq_avail = true;
7741         } else {
7742                 crtc_state->dpll_hw_state.fp1 = fp;
7743         }
7744 }
7745
7746 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7747                 pipe)
7748 {
7749         u32 reg_val;
7750
7751         /*
7752          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7753          * and set it to a reasonable value instead.
7754          */
7755         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7756         reg_val &= 0xffffff00;
7757         reg_val |= 0x00000030;
7758         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7759
7760         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7761         reg_val &= 0x8cffffff;
7762         reg_val = 0x8c000000;
7763         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7764
7765         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7766         reg_val &= 0xffffff00;
7767         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7768
7769         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7770         reg_val &= 0x00ffffff;
7771         reg_val |= 0xb0000000;
7772         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7773 }
7774
7775 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7776                                          struct intel_link_m_n *m_n)
7777 {
7778         struct drm_device *dev = crtc->base.dev;
7779         struct drm_i915_private *dev_priv = to_i915(dev);
7780         int pipe = crtc->pipe;
7781
7782         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7783         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7784         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7785         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7786 }
7787
7788 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7789                                          struct intel_link_m_n *m_n,
7790                                          struct intel_link_m_n *m2_n2)
7791 {
7792         struct drm_device *dev = crtc->base.dev;
7793         struct drm_i915_private *dev_priv = to_i915(dev);
7794         int pipe = crtc->pipe;
7795         enum transcoder transcoder = crtc->config->cpu_transcoder;
7796
7797         if (INTEL_INFO(dev)->gen >= 5) {
7798                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7799                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7800                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7801                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7802                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7803                  * for gen < 8) and if DRRS is supported (to make sure the
7804                  * registers are not unnecessarily accessed).
7805                  */
7806                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7807                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7808                         I915_WRITE(PIPE_DATA_M2(transcoder),
7809                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7810                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7811                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7812                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7813                 }
7814         } else {
7815                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7816                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7817                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7818                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7819         }
7820 }
7821
7822 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7823 {
7824         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7825
7826         if (m_n == M1_N1) {
7827                 dp_m_n = &crtc->config->dp_m_n;
7828                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7829         } else if (m_n == M2_N2) {
7830
7831                 /*
7832                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7833                  * needs to be programmed into M1_N1.
7834                  */
7835                 dp_m_n = &crtc->config->dp_m2_n2;
7836         } else {
7837                 DRM_ERROR("Unsupported divider value\n");
7838                 return;
7839         }
7840
7841         if (crtc->config->has_pch_encoder)
7842                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7843         else
7844                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7845 }
7846
7847 static void vlv_compute_dpll(struct intel_crtc *crtc,
7848                              struct intel_crtc_state *pipe_config)
7849 {
7850         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7851                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7852         if (crtc->pipe != PIPE_A)
7853                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7854
7855         /* DPLL not used with DSI, but still need the rest set up */
7856         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7857                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7858                         DPLL_EXT_BUFFER_ENABLE_VLV;
7859
7860         pipe_config->dpll_hw_state.dpll_md =
7861                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7862 }
7863
7864 static void chv_compute_dpll(struct intel_crtc *crtc,
7865                              struct intel_crtc_state *pipe_config)
7866 {
7867         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7868                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7869         if (crtc->pipe != PIPE_A)
7870                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7871
7872         /* DPLL not used with DSI, but still need the rest set up */
7873         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7874                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7875
7876         pipe_config->dpll_hw_state.dpll_md =
7877                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7878 }
7879
7880 static void vlv_prepare_pll(struct intel_crtc *crtc,
7881                             const struct intel_crtc_state *pipe_config)
7882 {
7883         struct drm_device *dev = crtc->base.dev;
7884         struct drm_i915_private *dev_priv = to_i915(dev);
7885         enum pipe pipe = crtc->pipe;
7886         u32 mdiv;
7887         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7888         u32 coreclk, reg_val;
7889
7890         /* Enable Refclk */
7891         I915_WRITE(DPLL(pipe),
7892                    pipe_config->dpll_hw_state.dpll &
7893                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7894
7895         /* No need to actually set up the DPLL with DSI */
7896         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7897                 return;
7898
7899         mutex_lock(&dev_priv->sb_lock);
7900
7901         bestn = pipe_config->dpll.n;
7902         bestm1 = pipe_config->dpll.m1;
7903         bestm2 = pipe_config->dpll.m2;
7904         bestp1 = pipe_config->dpll.p1;
7905         bestp2 = pipe_config->dpll.p2;
7906
7907         /* See eDP HDMI DPIO driver vbios notes doc */
7908
7909         /* PLL B needs special handling */
7910         if (pipe == PIPE_B)
7911                 vlv_pllb_recal_opamp(dev_priv, pipe);
7912
7913         /* Set up Tx target for periodic Rcomp update */
7914         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7915
7916         /* Disable target IRef on PLL */
7917         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7918         reg_val &= 0x00ffffff;
7919         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7920
7921         /* Disable fast lock */
7922         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7923
7924         /* Set idtafcrecal before PLL is enabled */
7925         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7926         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7927         mdiv |= ((bestn << DPIO_N_SHIFT));
7928         mdiv |= (1 << DPIO_K_SHIFT);
7929
7930         /*
7931          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7932          * but we don't support that).
7933          * Note: don't use the DAC post divider as it seems unstable.
7934          */
7935         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7936         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7937
7938         mdiv |= DPIO_ENABLE_CALIBRATION;
7939         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7940
7941         /* Set HBR and RBR LPF coefficients */
7942         if (pipe_config->port_clock == 162000 ||
7943             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7944             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7945                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7946                                  0x009f0003);
7947         else
7948                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7949                                  0x00d0000f);
7950
7951         if (intel_crtc_has_dp_encoder(pipe_config)) {
7952                 /* Use SSC source */
7953                 if (pipe == PIPE_A)
7954                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7955                                          0x0df40000);
7956                 else
7957                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7958                                          0x0df70000);
7959         } else { /* HDMI or VGA */
7960                 /* Use bend source */
7961                 if (pipe == PIPE_A)
7962                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7963                                          0x0df70000);
7964                 else
7965                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7966                                          0x0df40000);
7967         }
7968
7969         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7970         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7971         if (intel_crtc_has_dp_encoder(crtc->config))
7972                 coreclk |= 0x01000000;
7973         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7974
7975         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7976         mutex_unlock(&dev_priv->sb_lock);
7977 }
7978
7979 static void chv_prepare_pll(struct intel_crtc *crtc,
7980                             const struct intel_crtc_state *pipe_config)
7981 {
7982         struct drm_device *dev = crtc->base.dev;
7983         struct drm_i915_private *dev_priv = to_i915(dev);
7984         enum pipe pipe = crtc->pipe;
7985         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7986         u32 loopfilter, tribuf_calcntr;
7987         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7988         u32 dpio_val;
7989         int vco;
7990
7991         /* Enable Refclk and SSC */
7992         I915_WRITE(DPLL(pipe),
7993                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7994
7995         /* No need to actually set up the DPLL with DSI */
7996         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7997                 return;
7998
7999         bestn = pipe_config->dpll.n;
8000         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8001         bestm1 = pipe_config->dpll.m1;
8002         bestm2 = pipe_config->dpll.m2 >> 22;
8003         bestp1 = pipe_config->dpll.p1;
8004         bestp2 = pipe_config->dpll.p2;
8005         vco = pipe_config->dpll.vco;
8006         dpio_val = 0;
8007         loopfilter = 0;
8008
8009         mutex_lock(&dev_priv->sb_lock);
8010
8011         /* p1 and p2 divider */
8012         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8013                         5 << DPIO_CHV_S1_DIV_SHIFT |
8014                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8015                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8016                         1 << DPIO_CHV_K_DIV_SHIFT);
8017
8018         /* Feedback post-divider - m2 */
8019         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8020
8021         /* Feedback refclk divider - n and m1 */
8022         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8023                         DPIO_CHV_M1_DIV_BY_2 |
8024                         1 << DPIO_CHV_N_DIV_SHIFT);
8025
8026         /* M2 fraction division */
8027         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8028
8029         /* M2 fraction division enable */
8030         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8031         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8032         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8033         if (bestm2_frac)
8034                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8035         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8036
8037         /* Program digital lock detect threshold */
8038         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8039         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8040                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8041         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8042         if (!bestm2_frac)
8043                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8044         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8045
8046         /* Loop filter */
8047         if (vco == 5400000) {
8048                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8049                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8050                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8051                 tribuf_calcntr = 0x9;
8052         } else if (vco <= 6200000) {
8053                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8054                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8055                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8056                 tribuf_calcntr = 0x9;
8057         } else if (vco <= 6480000) {
8058                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8059                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8060                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8061                 tribuf_calcntr = 0x8;
8062         } else {
8063                 /* Not supported. Apply the same limits as in the max case */
8064                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8065                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8066                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8067                 tribuf_calcntr = 0;
8068         }
8069         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8070
8071         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8072         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8073         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8074         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8075
8076         /* AFC Recal */
8077         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8078                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8079                         DPIO_AFC_RECAL);
8080
8081         mutex_unlock(&dev_priv->sb_lock);
8082 }
8083
8084 /**
8085  * vlv_force_pll_on - forcibly enable just the PLL
8086  * @dev_priv: i915 private structure
8087  * @pipe: pipe PLL to enable
8088  * @dpll: PLL configuration
8089  *
8090  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8091  * in cases where we need the PLL enabled even when @pipe is not going to
8092  * be enabled.
8093  */
8094 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8095                      const struct dpll *dpll)
8096 {
8097         struct intel_crtc *crtc =
8098                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8099         struct intel_crtc_state *pipe_config;
8100
8101         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8102         if (!pipe_config)
8103                 return -ENOMEM;
8104
8105         pipe_config->base.crtc = &crtc->base;
8106         pipe_config->pixel_multiplier = 1;
8107         pipe_config->dpll = *dpll;
8108
8109         if (IS_CHERRYVIEW(to_i915(dev))) {
8110                 chv_compute_dpll(crtc, pipe_config);
8111                 chv_prepare_pll(crtc, pipe_config);
8112                 chv_enable_pll(crtc, pipe_config);
8113         } else {
8114                 vlv_compute_dpll(crtc, pipe_config);
8115                 vlv_prepare_pll(crtc, pipe_config);
8116                 vlv_enable_pll(crtc, pipe_config);
8117         }
8118
8119         kfree(pipe_config);
8120
8121         return 0;
8122 }
8123
8124 /**
8125  * vlv_force_pll_off - forcibly disable just the PLL
8126  * @dev_priv: i915 private structure
8127  * @pipe: pipe PLL to disable
8128  *
8129  * Disable the PLL for @pipe. To be used in cases where we need
8130  * the PLL enabled even when @pipe is not going to be enabled.
8131  */
8132 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8133 {
8134         if (IS_CHERRYVIEW(to_i915(dev)))
8135                 chv_disable_pll(to_i915(dev), pipe);
8136         else
8137                 vlv_disable_pll(to_i915(dev), pipe);
8138 }
8139
8140 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8141                               struct intel_crtc_state *crtc_state,
8142                               struct dpll *reduced_clock)
8143 {
8144         struct drm_device *dev = crtc->base.dev;
8145         struct drm_i915_private *dev_priv = to_i915(dev);
8146         u32 dpll;
8147         struct dpll *clock = &crtc_state->dpll;
8148
8149         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8150
8151         dpll = DPLL_VGA_MODE_DIS;
8152
8153         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8154                 dpll |= DPLLB_MODE_LVDS;
8155         else
8156                 dpll |= DPLLB_MODE_DAC_SERIAL;
8157
8158         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
8159                 dpll |= (crtc_state->pixel_multiplier - 1)
8160                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8161         }
8162
8163         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8164             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8165                 dpll |= DPLL_SDVO_HIGH_SPEED;
8166
8167         if (intel_crtc_has_dp_encoder(crtc_state))
8168                 dpll |= DPLL_SDVO_HIGH_SPEED;
8169
8170         /* compute bitmask from p1 value */
8171         if (IS_PINEVIEW(dev))
8172                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8173         else {
8174                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8175                 if (IS_G4X(dev_priv) && reduced_clock)
8176                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8177         }
8178         switch (clock->p2) {
8179         case 5:
8180                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8181                 break;
8182         case 7:
8183                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8184                 break;
8185         case 10:
8186                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8187                 break;
8188         case 14:
8189                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8190                 break;
8191         }
8192         if (INTEL_INFO(dev)->gen >= 4)
8193                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8194
8195         if (crtc_state->sdvo_tv_clock)
8196                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8197         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8198                  intel_panel_use_ssc(dev_priv))
8199                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8200         else
8201                 dpll |= PLL_REF_INPUT_DREFCLK;
8202
8203         dpll |= DPLL_VCO_ENABLE;
8204         crtc_state->dpll_hw_state.dpll = dpll;
8205
8206         if (INTEL_INFO(dev)->gen >= 4) {
8207                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8208                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8209                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8210         }
8211 }
8212
8213 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8214                               struct intel_crtc_state *crtc_state,
8215                               struct dpll *reduced_clock)
8216 {
8217         struct drm_device *dev = crtc->base.dev;
8218         struct drm_i915_private *dev_priv = to_i915(dev);
8219         u32 dpll;
8220         struct dpll *clock = &crtc_state->dpll;
8221
8222         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8223
8224         dpll = DPLL_VGA_MODE_DIS;
8225
8226         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8227                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8228         } else {
8229                 if (clock->p1 == 2)
8230                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8231                 else
8232                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8233                 if (clock->p2 == 4)
8234                         dpll |= PLL_P2_DIVIDE_BY_4;
8235         }
8236
8237         if (!IS_I830(dev_priv) &&
8238             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8239                 dpll |= DPLL_DVO_2X_MODE;
8240
8241         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8242             intel_panel_use_ssc(dev_priv))
8243                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8244         else
8245                 dpll |= PLL_REF_INPUT_DREFCLK;
8246
8247         dpll |= DPLL_VCO_ENABLE;
8248         crtc_state->dpll_hw_state.dpll = dpll;
8249 }
8250
8251 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8252 {
8253         struct drm_device *dev = intel_crtc->base.dev;
8254         struct drm_i915_private *dev_priv = to_i915(dev);
8255         enum pipe pipe = intel_crtc->pipe;
8256         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8257         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8258         uint32_t crtc_vtotal, crtc_vblank_end;
8259         int vsyncshift = 0;
8260
8261         /* We need to be careful not to changed the adjusted mode, for otherwise
8262          * the hw state checker will get angry at the mismatch. */
8263         crtc_vtotal = adjusted_mode->crtc_vtotal;
8264         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8265
8266         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8267                 /* the chip adds 2 halflines automatically */
8268                 crtc_vtotal -= 1;
8269                 crtc_vblank_end -= 1;
8270
8271                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8272                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8273                 else
8274                         vsyncshift = adjusted_mode->crtc_hsync_start -
8275                                 adjusted_mode->crtc_htotal / 2;
8276                 if (vsyncshift < 0)
8277                         vsyncshift += adjusted_mode->crtc_htotal;
8278         }
8279
8280         if (INTEL_INFO(dev)->gen > 3)
8281                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8282
8283         I915_WRITE(HTOTAL(cpu_transcoder),
8284                    (adjusted_mode->crtc_hdisplay - 1) |
8285                    ((adjusted_mode->crtc_htotal - 1) << 16));
8286         I915_WRITE(HBLANK(cpu_transcoder),
8287                    (adjusted_mode->crtc_hblank_start - 1) |
8288                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8289         I915_WRITE(HSYNC(cpu_transcoder),
8290                    (adjusted_mode->crtc_hsync_start - 1) |
8291                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8292
8293         I915_WRITE(VTOTAL(cpu_transcoder),
8294                    (adjusted_mode->crtc_vdisplay - 1) |
8295                    ((crtc_vtotal - 1) << 16));
8296         I915_WRITE(VBLANK(cpu_transcoder),
8297                    (adjusted_mode->crtc_vblank_start - 1) |
8298                    ((crtc_vblank_end - 1) << 16));
8299         I915_WRITE(VSYNC(cpu_transcoder),
8300                    (adjusted_mode->crtc_vsync_start - 1) |
8301                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8302
8303         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8304          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8305          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8306          * bits. */
8307         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8308             (pipe == PIPE_B || pipe == PIPE_C))
8309                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8310
8311 }
8312
8313 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8314 {
8315         struct drm_device *dev = intel_crtc->base.dev;
8316         struct drm_i915_private *dev_priv = to_i915(dev);
8317         enum pipe pipe = intel_crtc->pipe;
8318
8319         /* pipesrc controls the size that is scaled from, which should
8320          * always be the user's requested size.
8321          */
8322         I915_WRITE(PIPESRC(pipe),
8323                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8324                    (intel_crtc->config->pipe_src_h - 1));
8325 }
8326
8327 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8328                                    struct intel_crtc_state *pipe_config)
8329 {
8330         struct drm_device *dev = crtc->base.dev;
8331         struct drm_i915_private *dev_priv = to_i915(dev);
8332         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8333         uint32_t tmp;
8334
8335         tmp = I915_READ(HTOTAL(cpu_transcoder));
8336         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8337         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8338         tmp = I915_READ(HBLANK(cpu_transcoder));
8339         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8340         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8341         tmp = I915_READ(HSYNC(cpu_transcoder));
8342         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8343         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8344
8345         tmp = I915_READ(VTOTAL(cpu_transcoder));
8346         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8347         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8348         tmp = I915_READ(VBLANK(cpu_transcoder));
8349         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8350         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8351         tmp = I915_READ(VSYNC(cpu_transcoder));
8352         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8353         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8354
8355         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8356                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8357                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8358                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8359         }
8360 }
8361
8362 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8363                                     struct intel_crtc_state *pipe_config)
8364 {
8365         struct drm_device *dev = crtc->base.dev;
8366         struct drm_i915_private *dev_priv = to_i915(dev);
8367         u32 tmp;
8368
8369         tmp = I915_READ(PIPESRC(crtc->pipe));
8370         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8371         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8372
8373         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8374         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8375 }
8376
8377 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8378                                  struct intel_crtc_state *pipe_config)
8379 {
8380         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8381         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8382         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8383         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8384
8385         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8386         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8387         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8388         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8389
8390         mode->flags = pipe_config->base.adjusted_mode.flags;
8391         mode->type = DRM_MODE_TYPE_DRIVER;
8392
8393         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8394         mode->flags |= pipe_config->base.adjusted_mode.flags;
8395
8396         mode->hsync = drm_mode_hsync(mode);
8397         mode->vrefresh = drm_mode_vrefresh(mode);
8398         drm_mode_set_name(mode);
8399 }
8400
8401 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8402 {
8403         struct drm_device *dev = intel_crtc->base.dev;
8404         struct drm_i915_private *dev_priv = to_i915(dev);
8405         uint32_t pipeconf;
8406
8407         pipeconf = 0;
8408
8409         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8410             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8411                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8412
8413         if (intel_crtc->config->double_wide)
8414                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8415
8416         /* only g4x and later have fancy bpc/dither controls */
8417         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8418             IS_CHERRYVIEW(dev_priv)) {
8419                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8420                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8421                         pipeconf |= PIPECONF_DITHER_EN |
8422                                     PIPECONF_DITHER_TYPE_SP;
8423
8424                 switch (intel_crtc->config->pipe_bpp) {
8425                 case 18:
8426                         pipeconf |= PIPECONF_6BPC;
8427                         break;
8428                 case 24:
8429                         pipeconf |= PIPECONF_8BPC;
8430                         break;
8431                 case 30:
8432                         pipeconf |= PIPECONF_10BPC;
8433                         break;
8434                 default:
8435                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8436                         BUG();
8437                 }
8438         }
8439
8440         if (HAS_PIPE_CXSR(dev)) {
8441                 if (intel_crtc->lowfreq_avail) {
8442                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8443                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8444                 } else {
8445                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8446                 }
8447         }
8448
8449         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8450                 if (INTEL_INFO(dev)->gen < 4 ||
8451                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8452                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8453                 else
8454                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8455         } else
8456                 pipeconf |= PIPECONF_PROGRESSIVE;
8457
8458         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8459              intel_crtc->config->limited_color_range)
8460                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8461
8462         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8463         POSTING_READ(PIPECONF(intel_crtc->pipe));
8464 }
8465
8466 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8467                                    struct intel_crtc_state *crtc_state)
8468 {
8469         struct drm_device *dev = crtc->base.dev;
8470         struct drm_i915_private *dev_priv = to_i915(dev);
8471         const struct intel_limit *limit;
8472         int refclk = 48000;
8473
8474         memset(&crtc_state->dpll_hw_state, 0,
8475                sizeof(crtc_state->dpll_hw_state));
8476
8477         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8478                 if (intel_panel_use_ssc(dev_priv)) {
8479                         refclk = dev_priv->vbt.lvds_ssc_freq;
8480                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8481                 }
8482
8483                 limit = &intel_limits_i8xx_lvds;
8484         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8485                 limit = &intel_limits_i8xx_dvo;
8486         } else {
8487                 limit = &intel_limits_i8xx_dac;
8488         }
8489
8490         if (!crtc_state->clock_set &&
8491             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8492                                  refclk, NULL, &crtc_state->dpll)) {
8493                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8494                 return -EINVAL;
8495         }
8496
8497         i8xx_compute_dpll(crtc, crtc_state, NULL);
8498
8499         return 0;
8500 }
8501
8502 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8503                                   struct intel_crtc_state *crtc_state)
8504 {
8505         struct drm_device *dev = crtc->base.dev;
8506         struct drm_i915_private *dev_priv = to_i915(dev);
8507         const struct intel_limit *limit;
8508         int refclk = 96000;
8509
8510         memset(&crtc_state->dpll_hw_state, 0,
8511                sizeof(crtc_state->dpll_hw_state));
8512
8513         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8514                 if (intel_panel_use_ssc(dev_priv)) {
8515                         refclk = dev_priv->vbt.lvds_ssc_freq;
8516                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8517                 }
8518
8519                 if (intel_is_dual_link_lvds(dev))
8520                         limit = &intel_limits_g4x_dual_channel_lvds;
8521                 else
8522                         limit = &intel_limits_g4x_single_channel_lvds;
8523         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8524                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8525                 limit = &intel_limits_g4x_hdmi;
8526         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8527                 limit = &intel_limits_g4x_sdvo;
8528         } else {
8529                 /* The option is for other outputs */
8530                 limit = &intel_limits_i9xx_sdvo;
8531         }
8532
8533         if (!crtc_state->clock_set &&
8534             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8535                                 refclk, NULL, &crtc_state->dpll)) {
8536                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8537                 return -EINVAL;
8538         }
8539
8540         i9xx_compute_dpll(crtc, crtc_state, NULL);
8541
8542         return 0;
8543 }
8544
8545 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8546                                   struct intel_crtc_state *crtc_state)
8547 {
8548         struct drm_device *dev = crtc->base.dev;
8549         struct drm_i915_private *dev_priv = to_i915(dev);
8550         const struct intel_limit *limit;
8551         int refclk = 96000;
8552
8553         memset(&crtc_state->dpll_hw_state, 0,
8554                sizeof(crtc_state->dpll_hw_state));
8555
8556         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8557                 if (intel_panel_use_ssc(dev_priv)) {
8558                         refclk = dev_priv->vbt.lvds_ssc_freq;
8559                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8560                 }
8561
8562                 limit = &intel_limits_pineview_lvds;
8563         } else {
8564                 limit = &intel_limits_pineview_sdvo;
8565         }
8566
8567         if (!crtc_state->clock_set &&
8568             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8569                                 refclk, NULL, &crtc_state->dpll)) {
8570                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8571                 return -EINVAL;
8572         }
8573
8574         i9xx_compute_dpll(crtc, crtc_state, NULL);
8575
8576         return 0;
8577 }
8578
8579 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8580                                    struct intel_crtc_state *crtc_state)
8581 {
8582         struct drm_device *dev = crtc->base.dev;
8583         struct drm_i915_private *dev_priv = to_i915(dev);
8584         const struct intel_limit *limit;
8585         int refclk = 96000;
8586
8587         memset(&crtc_state->dpll_hw_state, 0,
8588                sizeof(crtc_state->dpll_hw_state));
8589
8590         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8591                 if (intel_panel_use_ssc(dev_priv)) {
8592                         refclk = dev_priv->vbt.lvds_ssc_freq;
8593                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8594                 }
8595
8596                 limit = &intel_limits_i9xx_lvds;
8597         } else {
8598                 limit = &intel_limits_i9xx_sdvo;
8599         }
8600
8601         if (!crtc_state->clock_set &&
8602             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8603                                  refclk, NULL, &crtc_state->dpll)) {
8604                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8605                 return -EINVAL;
8606         }
8607
8608         i9xx_compute_dpll(crtc, crtc_state, NULL);
8609
8610         return 0;
8611 }
8612
8613 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8614                                   struct intel_crtc_state *crtc_state)
8615 {
8616         int refclk = 100000;
8617         const struct intel_limit *limit = &intel_limits_chv;
8618
8619         memset(&crtc_state->dpll_hw_state, 0,
8620                sizeof(crtc_state->dpll_hw_state));
8621
8622         if (!crtc_state->clock_set &&
8623             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8624                                 refclk, NULL, &crtc_state->dpll)) {
8625                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8626                 return -EINVAL;
8627         }
8628
8629         chv_compute_dpll(crtc, crtc_state);
8630
8631         return 0;
8632 }
8633
8634 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8635                                   struct intel_crtc_state *crtc_state)
8636 {
8637         int refclk = 100000;
8638         const struct intel_limit *limit = &intel_limits_vlv;
8639
8640         memset(&crtc_state->dpll_hw_state, 0,
8641                sizeof(crtc_state->dpll_hw_state));
8642
8643         if (!crtc_state->clock_set &&
8644             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8645                                 refclk, NULL, &crtc_state->dpll)) {
8646                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8647                 return -EINVAL;
8648         }
8649
8650         vlv_compute_dpll(crtc, crtc_state);
8651
8652         return 0;
8653 }
8654
8655 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8656                                  struct intel_crtc_state *pipe_config)
8657 {
8658         struct drm_device *dev = crtc->base.dev;
8659         struct drm_i915_private *dev_priv = to_i915(dev);
8660         uint32_t tmp;
8661
8662         if (INTEL_GEN(dev_priv) <= 3 &&
8663             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8664                 return;
8665
8666         tmp = I915_READ(PFIT_CONTROL);
8667         if (!(tmp & PFIT_ENABLE))
8668                 return;
8669
8670         /* Check whether the pfit is attached to our pipe. */
8671         if (INTEL_INFO(dev)->gen < 4) {
8672                 if (crtc->pipe != PIPE_B)
8673                         return;
8674         } else {
8675                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8676                         return;
8677         }
8678
8679         pipe_config->gmch_pfit.control = tmp;
8680         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8681 }
8682
8683 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8684                                struct intel_crtc_state *pipe_config)
8685 {
8686         struct drm_device *dev = crtc->base.dev;
8687         struct drm_i915_private *dev_priv = to_i915(dev);
8688         int pipe = pipe_config->cpu_transcoder;
8689         struct dpll clock;
8690         u32 mdiv;
8691         int refclk = 100000;
8692
8693         /* In case of DSI, DPLL will not be used */
8694         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8695                 return;
8696
8697         mutex_lock(&dev_priv->sb_lock);
8698         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8699         mutex_unlock(&dev_priv->sb_lock);
8700
8701         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8702         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8703         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8704         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8705         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8706
8707         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8708 }
8709
8710 static void
8711 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8712                               struct intel_initial_plane_config *plane_config)
8713 {
8714         struct drm_device *dev = crtc->base.dev;
8715         struct drm_i915_private *dev_priv = to_i915(dev);
8716         u32 val, base, offset;
8717         int pipe = crtc->pipe, plane = crtc->plane;
8718         int fourcc, pixel_format;
8719         unsigned int aligned_height;
8720         struct drm_framebuffer *fb;
8721         struct intel_framebuffer *intel_fb;
8722
8723         val = I915_READ(DSPCNTR(plane));
8724         if (!(val & DISPLAY_PLANE_ENABLE))
8725                 return;
8726
8727         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8728         if (!intel_fb) {
8729                 DRM_DEBUG_KMS("failed to alloc fb\n");
8730                 return;
8731         }
8732
8733         fb = &intel_fb->base;
8734
8735         if (INTEL_INFO(dev)->gen >= 4) {
8736                 if (val & DISPPLANE_TILED) {
8737                         plane_config->tiling = I915_TILING_X;
8738                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8739                 }
8740         }
8741
8742         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8743         fourcc = i9xx_format_to_fourcc(pixel_format);
8744         fb->pixel_format = fourcc;
8745         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8746
8747         if (INTEL_INFO(dev)->gen >= 4) {
8748                 if (plane_config->tiling)
8749                         offset = I915_READ(DSPTILEOFF(plane));
8750                 else
8751                         offset = I915_READ(DSPLINOFF(plane));
8752                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8753         } else {
8754                 base = I915_READ(DSPADDR(plane));
8755         }
8756         plane_config->base = base;
8757
8758         val = I915_READ(PIPESRC(pipe));
8759         fb->width = ((val >> 16) & 0xfff) + 1;
8760         fb->height = ((val >> 0) & 0xfff) + 1;
8761
8762         val = I915_READ(DSPSTRIDE(pipe));
8763         fb->pitches[0] = val & 0xffffffc0;
8764
8765         aligned_height = intel_fb_align_height(dev, fb->height,
8766                                                fb->pixel_format,
8767                                                fb->modifier[0]);
8768
8769         plane_config->size = fb->pitches[0] * aligned_height;
8770
8771         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8772                       pipe_name(pipe), plane, fb->width, fb->height,
8773                       fb->bits_per_pixel, base, fb->pitches[0],
8774                       plane_config->size);
8775
8776         plane_config->fb = intel_fb;
8777 }
8778
8779 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8780                                struct intel_crtc_state *pipe_config)
8781 {
8782         struct drm_device *dev = crtc->base.dev;
8783         struct drm_i915_private *dev_priv = to_i915(dev);
8784         int pipe = pipe_config->cpu_transcoder;
8785         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8786         struct dpll clock;
8787         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8788         int refclk = 100000;
8789
8790         /* In case of DSI, DPLL will not be used */
8791         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8792                 return;
8793
8794         mutex_lock(&dev_priv->sb_lock);
8795         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8796         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8797         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8798         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8799         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8800         mutex_unlock(&dev_priv->sb_lock);
8801
8802         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8803         clock.m2 = (pll_dw0 & 0xff) << 22;
8804         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8805                 clock.m2 |= pll_dw2 & 0x3fffff;
8806         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8807         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8808         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8809
8810         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8811 }
8812
8813 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8814                                  struct intel_crtc_state *pipe_config)
8815 {
8816         struct drm_device *dev = crtc->base.dev;
8817         struct drm_i915_private *dev_priv = to_i915(dev);
8818         enum intel_display_power_domain power_domain;
8819         uint32_t tmp;
8820         bool ret;
8821
8822         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8823         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8824                 return false;
8825
8826         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8827         pipe_config->shared_dpll = NULL;
8828
8829         ret = false;
8830
8831         tmp = I915_READ(PIPECONF(crtc->pipe));
8832         if (!(tmp & PIPECONF_ENABLE))
8833                 goto out;
8834
8835         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8836             IS_CHERRYVIEW(dev_priv)) {
8837                 switch (tmp & PIPECONF_BPC_MASK) {
8838                 case PIPECONF_6BPC:
8839                         pipe_config->pipe_bpp = 18;
8840                         break;
8841                 case PIPECONF_8BPC:
8842                         pipe_config->pipe_bpp = 24;
8843                         break;
8844                 case PIPECONF_10BPC:
8845                         pipe_config->pipe_bpp = 30;
8846                         break;
8847                 default:
8848                         break;
8849                 }
8850         }
8851
8852         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8853             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8854                 pipe_config->limited_color_range = true;
8855
8856         if (INTEL_INFO(dev)->gen < 4)
8857                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8858
8859         intel_get_pipe_timings(crtc, pipe_config);
8860         intel_get_pipe_src_size(crtc, pipe_config);
8861
8862         i9xx_get_pfit_config(crtc, pipe_config);
8863
8864         if (INTEL_INFO(dev)->gen >= 4) {
8865                 /* No way to read it out on pipes B and C */
8866                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8867                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8868                 else
8869                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8870                 pipe_config->pixel_multiplier =
8871                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8872                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8873                 pipe_config->dpll_hw_state.dpll_md = tmp;
8874         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8875                    IS_G33(dev_priv)) {
8876                 tmp = I915_READ(DPLL(crtc->pipe));
8877                 pipe_config->pixel_multiplier =
8878                         ((tmp & SDVO_MULTIPLIER_MASK)
8879                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8880         } else {
8881                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8882                  * port and will be fixed up in the encoder->get_config
8883                  * function. */
8884                 pipe_config->pixel_multiplier = 1;
8885         }
8886         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8887         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8888                 /*
8889                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8890                  * on 830. Filter it out here so that we don't
8891                  * report errors due to that.
8892                  */
8893                 if (IS_I830(dev_priv))
8894                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8895
8896                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8897                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8898         } else {
8899                 /* Mask out read-only status bits. */
8900                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8901                                                      DPLL_PORTC_READY_MASK |
8902                                                      DPLL_PORTB_READY_MASK);
8903         }
8904
8905         if (IS_CHERRYVIEW(dev_priv))
8906                 chv_crtc_clock_get(crtc, pipe_config);
8907         else if (IS_VALLEYVIEW(dev))
8908                 vlv_crtc_clock_get(crtc, pipe_config);
8909         else
8910                 i9xx_crtc_clock_get(crtc, pipe_config);
8911
8912         /*
8913          * Normally the dotclock is filled in by the encoder .get_config()
8914          * but in case the pipe is enabled w/o any ports we need a sane
8915          * default.
8916          */
8917         pipe_config->base.adjusted_mode.crtc_clock =
8918                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8919
8920         ret = true;
8921
8922 out:
8923         intel_display_power_put(dev_priv, power_domain);
8924
8925         return ret;
8926 }
8927
8928 static void ironlake_init_pch_refclk(struct drm_device *dev)
8929 {
8930         struct drm_i915_private *dev_priv = to_i915(dev);
8931         struct intel_encoder *encoder;
8932         int i;
8933         u32 val, final;
8934         bool has_lvds = false;
8935         bool has_cpu_edp = false;
8936         bool has_panel = false;
8937         bool has_ck505 = false;
8938         bool can_ssc = false;
8939         bool using_ssc_source = false;
8940
8941         /* We need to take the global config into account */
8942         for_each_intel_encoder(dev, encoder) {
8943                 switch (encoder->type) {
8944                 case INTEL_OUTPUT_LVDS:
8945                         has_panel = true;
8946                         has_lvds = true;
8947                         break;
8948                 case INTEL_OUTPUT_EDP:
8949                         has_panel = true;
8950                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8951                                 has_cpu_edp = true;
8952                         break;
8953                 default:
8954                         break;
8955                 }
8956         }
8957
8958         if (HAS_PCH_IBX(dev_priv)) {
8959                 has_ck505 = dev_priv->vbt.display_clock_mode;
8960                 can_ssc = has_ck505;
8961         } else {
8962                 has_ck505 = false;
8963                 can_ssc = true;
8964         }
8965
8966         /* Check if any DPLLs are using the SSC source */
8967         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8968                 u32 temp = I915_READ(PCH_DPLL(i));
8969
8970                 if (!(temp & DPLL_VCO_ENABLE))
8971                         continue;
8972
8973                 if ((temp & PLL_REF_INPUT_MASK) ==
8974                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8975                         using_ssc_source = true;
8976                         break;
8977                 }
8978         }
8979
8980         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8981                       has_panel, has_lvds, has_ck505, using_ssc_source);
8982
8983         /* Ironlake: try to setup display ref clock before DPLL
8984          * enabling. This is only under driver's control after
8985          * PCH B stepping, previous chipset stepping should be
8986          * ignoring this setting.
8987          */
8988         val = I915_READ(PCH_DREF_CONTROL);
8989
8990         /* As we must carefully and slowly disable/enable each source in turn,
8991          * compute the final state we want first and check if we need to
8992          * make any changes at all.
8993          */
8994         final = val;
8995         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8996         if (has_ck505)
8997                 final |= DREF_NONSPREAD_CK505_ENABLE;
8998         else
8999                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9000
9001         final &= ~DREF_SSC_SOURCE_MASK;
9002         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9003         final &= ~DREF_SSC1_ENABLE;
9004
9005         if (has_panel) {
9006                 final |= DREF_SSC_SOURCE_ENABLE;
9007
9008                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9009                         final |= DREF_SSC1_ENABLE;
9010
9011                 if (has_cpu_edp) {
9012                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9013                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9014                         else
9015                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9016                 } else
9017                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9018         } else if (using_ssc_source) {
9019                 final |= DREF_SSC_SOURCE_ENABLE;
9020                 final |= DREF_SSC1_ENABLE;
9021         }
9022
9023         if (final == val)
9024                 return;
9025
9026         /* Always enable nonspread source */
9027         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9028
9029         if (has_ck505)
9030                 val |= DREF_NONSPREAD_CK505_ENABLE;
9031         else
9032                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9033
9034         if (has_panel) {
9035                 val &= ~DREF_SSC_SOURCE_MASK;
9036                 val |= DREF_SSC_SOURCE_ENABLE;
9037
9038                 /* SSC must be turned on before enabling the CPU output  */
9039                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9040                         DRM_DEBUG_KMS("Using SSC on panel\n");
9041                         val |= DREF_SSC1_ENABLE;
9042                 } else
9043                         val &= ~DREF_SSC1_ENABLE;
9044
9045                 /* Get SSC going before enabling the outputs */
9046                 I915_WRITE(PCH_DREF_CONTROL, val);
9047                 POSTING_READ(PCH_DREF_CONTROL);
9048                 udelay(200);
9049
9050                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9051
9052                 /* Enable CPU source on CPU attached eDP */
9053                 if (has_cpu_edp) {
9054                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9055                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9056                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9057                         } else
9058                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9059                 } else
9060                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9061
9062                 I915_WRITE(PCH_DREF_CONTROL, val);
9063                 POSTING_READ(PCH_DREF_CONTROL);
9064                 udelay(200);
9065         } else {
9066                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9067
9068                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9069
9070                 /* Turn off CPU output */
9071                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9072
9073                 I915_WRITE(PCH_DREF_CONTROL, val);
9074                 POSTING_READ(PCH_DREF_CONTROL);
9075                 udelay(200);
9076
9077                 if (!using_ssc_source) {
9078                         DRM_DEBUG_KMS("Disabling SSC source\n");
9079
9080                         /* Turn off the SSC source */
9081                         val &= ~DREF_SSC_SOURCE_MASK;
9082                         val |= DREF_SSC_SOURCE_DISABLE;
9083
9084                         /* Turn off SSC1 */
9085                         val &= ~DREF_SSC1_ENABLE;
9086
9087                         I915_WRITE(PCH_DREF_CONTROL, val);
9088                         POSTING_READ(PCH_DREF_CONTROL);
9089                         udelay(200);
9090                 }
9091         }
9092
9093         BUG_ON(val != final);
9094 }
9095
9096 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9097 {
9098         uint32_t tmp;
9099
9100         tmp = I915_READ(SOUTH_CHICKEN2);
9101         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9102         I915_WRITE(SOUTH_CHICKEN2, tmp);
9103
9104         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9105                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9106                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9107
9108         tmp = I915_READ(SOUTH_CHICKEN2);
9109         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9110         I915_WRITE(SOUTH_CHICKEN2, tmp);
9111
9112         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9113                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9114                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9115 }
9116
9117 /* WaMPhyProgramming:hsw */
9118 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9119 {
9120         uint32_t tmp;
9121
9122         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9123         tmp &= ~(0xFF << 24);
9124         tmp |= (0x12 << 24);
9125         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9126
9127         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9128         tmp |= (1 << 11);
9129         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9130
9131         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9132         tmp |= (1 << 11);
9133         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9134
9135         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9136         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9137         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9138
9139         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9140         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9141         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9142
9143         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9144         tmp &= ~(7 << 13);
9145         tmp |= (5 << 13);
9146         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9147
9148         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9149         tmp &= ~(7 << 13);
9150         tmp |= (5 << 13);
9151         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9152
9153         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9154         tmp &= ~0xFF;
9155         tmp |= 0x1C;
9156         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9157
9158         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9159         tmp &= ~0xFF;
9160         tmp |= 0x1C;
9161         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9162
9163         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9164         tmp &= ~(0xFF << 16);
9165         tmp |= (0x1C << 16);
9166         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9167
9168         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9169         tmp &= ~(0xFF << 16);
9170         tmp |= (0x1C << 16);
9171         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9172
9173         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9174         tmp |= (1 << 27);
9175         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9176
9177         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9178         tmp |= (1 << 27);
9179         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9180
9181         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9182         tmp &= ~(0xF << 28);
9183         tmp |= (4 << 28);
9184         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9185
9186         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9187         tmp &= ~(0xF << 28);
9188         tmp |= (4 << 28);
9189         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9190 }
9191
9192 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9193  * Programming" based on the parameters passed:
9194  * - Sequence to enable CLKOUT_DP
9195  * - Sequence to enable CLKOUT_DP without spread
9196  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9197  */
9198 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9199                                  bool with_fdi)
9200 {
9201         struct drm_i915_private *dev_priv = to_i915(dev);
9202         uint32_t reg, tmp;
9203
9204         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9205                 with_spread = true;
9206         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9207             with_fdi, "LP PCH doesn't have FDI\n"))
9208                 with_fdi = false;
9209
9210         mutex_lock(&dev_priv->sb_lock);
9211
9212         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9213         tmp &= ~SBI_SSCCTL_DISABLE;
9214         tmp |= SBI_SSCCTL_PATHALT;
9215         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9216
9217         udelay(24);
9218
9219         if (with_spread) {
9220                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9221                 tmp &= ~SBI_SSCCTL_PATHALT;
9222                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9223
9224                 if (with_fdi) {
9225                         lpt_reset_fdi_mphy(dev_priv);
9226                         lpt_program_fdi_mphy(dev_priv);
9227                 }
9228         }
9229
9230         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9231         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9232         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9233         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9234
9235         mutex_unlock(&dev_priv->sb_lock);
9236 }
9237
9238 /* Sequence to disable CLKOUT_DP */
9239 static void lpt_disable_clkout_dp(struct drm_device *dev)
9240 {
9241         struct drm_i915_private *dev_priv = to_i915(dev);
9242         uint32_t reg, tmp;
9243
9244         mutex_lock(&dev_priv->sb_lock);
9245
9246         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9247         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9248         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9249         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9250
9251         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9252         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9253                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9254                         tmp |= SBI_SSCCTL_PATHALT;
9255                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9256                         udelay(32);
9257                 }
9258                 tmp |= SBI_SSCCTL_DISABLE;
9259                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9260         }
9261
9262         mutex_unlock(&dev_priv->sb_lock);
9263 }
9264
9265 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9266
9267 static const uint16_t sscdivintphase[] = {
9268         [BEND_IDX( 50)] = 0x3B23,
9269         [BEND_IDX( 45)] = 0x3B23,
9270         [BEND_IDX( 40)] = 0x3C23,
9271         [BEND_IDX( 35)] = 0x3C23,
9272         [BEND_IDX( 30)] = 0x3D23,
9273         [BEND_IDX( 25)] = 0x3D23,
9274         [BEND_IDX( 20)] = 0x3E23,
9275         [BEND_IDX( 15)] = 0x3E23,
9276         [BEND_IDX( 10)] = 0x3F23,
9277         [BEND_IDX(  5)] = 0x3F23,
9278         [BEND_IDX(  0)] = 0x0025,
9279         [BEND_IDX( -5)] = 0x0025,
9280         [BEND_IDX(-10)] = 0x0125,
9281         [BEND_IDX(-15)] = 0x0125,
9282         [BEND_IDX(-20)] = 0x0225,
9283         [BEND_IDX(-25)] = 0x0225,
9284         [BEND_IDX(-30)] = 0x0325,
9285         [BEND_IDX(-35)] = 0x0325,
9286         [BEND_IDX(-40)] = 0x0425,
9287         [BEND_IDX(-45)] = 0x0425,
9288         [BEND_IDX(-50)] = 0x0525,
9289 };
9290
9291 /*
9292  * Bend CLKOUT_DP
9293  * steps -50 to 50 inclusive, in steps of 5
9294  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9295  * change in clock period = -(steps / 10) * 5.787 ps
9296  */
9297 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9298 {
9299         uint32_t tmp;
9300         int idx = BEND_IDX(steps);
9301
9302         if (WARN_ON(steps % 5 != 0))
9303                 return;
9304
9305         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9306                 return;
9307
9308         mutex_lock(&dev_priv->sb_lock);
9309
9310         if (steps % 10 != 0)
9311                 tmp = 0xAAAAAAAB;
9312         else
9313                 tmp = 0x00000000;
9314         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9315
9316         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9317         tmp &= 0xffff0000;
9318         tmp |= sscdivintphase[idx];
9319         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9320
9321         mutex_unlock(&dev_priv->sb_lock);
9322 }
9323
9324 #undef BEND_IDX
9325
9326 static void lpt_init_pch_refclk(struct drm_device *dev)
9327 {
9328         struct intel_encoder *encoder;
9329         bool has_vga = false;
9330
9331         for_each_intel_encoder(dev, encoder) {
9332                 switch (encoder->type) {
9333                 case INTEL_OUTPUT_ANALOG:
9334                         has_vga = true;
9335                         break;
9336                 default:
9337                         break;
9338                 }
9339         }
9340
9341         if (has_vga) {
9342                 lpt_bend_clkout_dp(to_i915(dev), 0);
9343                 lpt_enable_clkout_dp(dev, true, true);
9344         } else {
9345                 lpt_disable_clkout_dp(dev);
9346         }
9347 }
9348
9349 /*
9350  * Initialize reference clocks when the driver loads
9351  */
9352 void intel_init_pch_refclk(struct drm_device *dev)
9353 {
9354         struct drm_i915_private *dev_priv = to_i915(dev);
9355
9356         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9357                 ironlake_init_pch_refclk(dev);
9358         else if (HAS_PCH_LPT(dev_priv))
9359                 lpt_init_pch_refclk(dev);
9360 }
9361
9362 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9363 {
9364         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9366         int pipe = intel_crtc->pipe;
9367         uint32_t val;
9368
9369         val = 0;
9370
9371         switch (intel_crtc->config->pipe_bpp) {
9372         case 18:
9373                 val |= PIPECONF_6BPC;
9374                 break;
9375         case 24:
9376                 val |= PIPECONF_8BPC;
9377                 break;
9378         case 30:
9379                 val |= PIPECONF_10BPC;
9380                 break;
9381         case 36:
9382                 val |= PIPECONF_12BPC;
9383                 break;
9384         default:
9385                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9386                 BUG();
9387         }
9388
9389         if (intel_crtc->config->dither)
9390                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9391
9392         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9393                 val |= PIPECONF_INTERLACED_ILK;
9394         else
9395                 val |= PIPECONF_PROGRESSIVE;
9396
9397         if (intel_crtc->config->limited_color_range)
9398                 val |= PIPECONF_COLOR_RANGE_SELECT;
9399
9400         I915_WRITE(PIPECONF(pipe), val);
9401         POSTING_READ(PIPECONF(pipe));
9402 }
9403
9404 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9405 {
9406         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9408         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9409         u32 val = 0;
9410
9411         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9412                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9413
9414         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9415                 val |= PIPECONF_INTERLACED_ILK;
9416         else
9417                 val |= PIPECONF_PROGRESSIVE;
9418
9419         I915_WRITE(PIPECONF(cpu_transcoder), val);
9420         POSTING_READ(PIPECONF(cpu_transcoder));
9421 }
9422
9423 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9424 {
9425         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9427
9428         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9429                 u32 val = 0;
9430
9431                 switch (intel_crtc->config->pipe_bpp) {
9432                 case 18:
9433                         val |= PIPEMISC_DITHER_6_BPC;
9434                         break;
9435                 case 24:
9436                         val |= PIPEMISC_DITHER_8_BPC;
9437                         break;
9438                 case 30:
9439                         val |= PIPEMISC_DITHER_10_BPC;
9440                         break;
9441                 case 36:
9442                         val |= PIPEMISC_DITHER_12_BPC;
9443                         break;
9444                 default:
9445                         /* Case prevented by pipe_config_set_bpp. */
9446                         BUG();
9447                 }
9448
9449                 if (intel_crtc->config->dither)
9450                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9451
9452                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9453         }
9454 }
9455
9456 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9457 {
9458         /*
9459          * Account for spread spectrum to avoid
9460          * oversubscribing the link. Max center spread
9461          * is 2.5%; use 5% for safety's sake.
9462          */
9463         u32 bps = target_clock * bpp * 21 / 20;
9464         return DIV_ROUND_UP(bps, link_bw * 8);
9465 }
9466
9467 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9468 {
9469         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9470 }
9471
9472 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9473                                   struct intel_crtc_state *crtc_state,
9474                                   struct dpll *reduced_clock)
9475 {
9476         struct drm_crtc *crtc = &intel_crtc->base;
9477         struct drm_device *dev = crtc->dev;
9478         struct drm_i915_private *dev_priv = to_i915(dev);
9479         u32 dpll, fp, fp2;
9480         int factor;
9481
9482         /* Enable autotuning of the PLL clock (if permissible) */
9483         factor = 21;
9484         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9485                 if ((intel_panel_use_ssc(dev_priv) &&
9486                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9487                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9488                         factor = 25;
9489         } else if (crtc_state->sdvo_tv_clock)
9490                 factor = 20;
9491
9492         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9493
9494         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9495                 fp |= FP_CB_TUNE;
9496
9497         if (reduced_clock) {
9498                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9499
9500                 if (reduced_clock->m < factor * reduced_clock->n)
9501                         fp2 |= FP_CB_TUNE;
9502         } else {
9503                 fp2 = fp;
9504         }
9505
9506         dpll = 0;
9507
9508         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9509                 dpll |= DPLLB_MODE_LVDS;
9510         else
9511                 dpll |= DPLLB_MODE_DAC_SERIAL;
9512
9513         dpll |= (crtc_state->pixel_multiplier - 1)
9514                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9515
9516         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9517             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9518                 dpll |= DPLL_SDVO_HIGH_SPEED;
9519
9520         if (intel_crtc_has_dp_encoder(crtc_state))
9521                 dpll |= DPLL_SDVO_HIGH_SPEED;
9522
9523         /*
9524          * The high speed IO clock is only really required for
9525          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9526          * possible to share the DPLL between CRT and HDMI. Enabling
9527          * the clock needlessly does no real harm, except use up a
9528          * bit of power potentially.
9529          *
9530          * We'll limit this to IVB with 3 pipes, since it has only two
9531          * DPLLs and so DPLL sharing is the only way to get three pipes
9532          * driving PCH ports at the same time. On SNB we could do this,
9533          * and potentially avoid enabling the second DPLL, but it's not
9534          * clear if it''s a win or loss power wise. No point in doing
9535          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9536          */
9537         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9538             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9539                 dpll |= DPLL_SDVO_HIGH_SPEED;
9540
9541         /* compute bitmask from p1 value */
9542         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9543         /* also FPA1 */
9544         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9545
9546         switch (crtc_state->dpll.p2) {
9547         case 5:
9548                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9549                 break;
9550         case 7:
9551                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9552                 break;
9553         case 10:
9554                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9555                 break;
9556         case 14:
9557                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9558                 break;
9559         }
9560
9561         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9562             intel_panel_use_ssc(dev_priv))
9563                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9564         else
9565                 dpll |= PLL_REF_INPUT_DREFCLK;
9566
9567         dpll |= DPLL_VCO_ENABLE;
9568
9569         crtc_state->dpll_hw_state.dpll = dpll;
9570         crtc_state->dpll_hw_state.fp0 = fp;
9571         crtc_state->dpll_hw_state.fp1 = fp2;
9572 }
9573
9574 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9575                                        struct intel_crtc_state *crtc_state)
9576 {
9577         struct drm_device *dev = crtc->base.dev;
9578         struct drm_i915_private *dev_priv = to_i915(dev);
9579         struct dpll reduced_clock;
9580         bool has_reduced_clock = false;
9581         struct intel_shared_dpll *pll;
9582         const struct intel_limit *limit;
9583         int refclk = 120000;
9584
9585         memset(&crtc_state->dpll_hw_state, 0,
9586                sizeof(crtc_state->dpll_hw_state));
9587
9588         crtc->lowfreq_avail = false;
9589
9590         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9591         if (!crtc_state->has_pch_encoder)
9592                 return 0;
9593
9594         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9595                 if (intel_panel_use_ssc(dev_priv)) {
9596                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9597                                       dev_priv->vbt.lvds_ssc_freq);
9598                         refclk = dev_priv->vbt.lvds_ssc_freq;
9599                 }
9600
9601                 if (intel_is_dual_link_lvds(dev)) {
9602                         if (refclk == 100000)
9603                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9604                         else
9605                                 limit = &intel_limits_ironlake_dual_lvds;
9606                 } else {
9607                         if (refclk == 100000)
9608                                 limit = &intel_limits_ironlake_single_lvds_100m;
9609                         else
9610                                 limit = &intel_limits_ironlake_single_lvds;
9611                 }
9612         } else {
9613                 limit = &intel_limits_ironlake_dac;
9614         }
9615
9616         if (!crtc_state->clock_set &&
9617             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9618                                 refclk, NULL, &crtc_state->dpll)) {
9619                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9620                 return -EINVAL;
9621         }
9622
9623         ironlake_compute_dpll(crtc, crtc_state,
9624                               has_reduced_clock ? &reduced_clock : NULL);
9625
9626         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9627         if (pll == NULL) {
9628                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9629                                  pipe_name(crtc->pipe));
9630                 return -EINVAL;
9631         }
9632
9633         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9634             has_reduced_clock)
9635                 crtc->lowfreq_avail = true;
9636
9637         return 0;
9638 }
9639
9640 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9641                                          struct intel_link_m_n *m_n)
9642 {
9643         struct drm_device *dev = crtc->base.dev;
9644         struct drm_i915_private *dev_priv = to_i915(dev);
9645         enum pipe pipe = crtc->pipe;
9646
9647         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9648         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9649         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9650                 & ~TU_SIZE_MASK;
9651         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9652         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9653                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9654 }
9655
9656 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9657                                          enum transcoder transcoder,
9658                                          struct intel_link_m_n *m_n,
9659                                          struct intel_link_m_n *m2_n2)
9660 {
9661         struct drm_device *dev = crtc->base.dev;
9662         struct drm_i915_private *dev_priv = to_i915(dev);
9663         enum pipe pipe = crtc->pipe;
9664
9665         if (INTEL_INFO(dev)->gen >= 5) {
9666                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9667                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9668                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9669                         & ~TU_SIZE_MASK;
9670                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9671                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9672                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9673                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9674                  * gen < 8) and if DRRS is supported (to make sure the
9675                  * registers are not unnecessarily read).
9676                  */
9677                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9678                         crtc->config->has_drrs) {
9679                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9680                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9681                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9682                                         & ~TU_SIZE_MASK;
9683                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9684                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9685                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9686                 }
9687         } else {
9688                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9689                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9690                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9691                         & ~TU_SIZE_MASK;
9692                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9693                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9694                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9695         }
9696 }
9697
9698 void intel_dp_get_m_n(struct intel_crtc *crtc,
9699                       struct intel_crtc_state *pipe_config)
9700 {
9701         if (pipe_config->has_pch_encoder)
9702                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9703         else
9704                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9705                                              &pipe_config->dp_m_n,
9706                                              &pipe_config->dp_m2_n2);
9707 }
9708
9709 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9710                                         struct intel_crtc_state *pipe_config)
9711 {
9712         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9713                                      &pipe_config->fdi_m_n, NULL);
9714 }
9715
9716 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9717                                     struct intel_crtc_state *pipe_config)
9718 {
9719         struct drm_device *dev = crtc->base.dev;
9720         struct drm_i915_private *dev_priv = to_i915(dev);
9721         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9722         uint32_t ps_ctrl = 0;
9723         int id = -1;
9724         int i;
9725
9726         /* find scaler attached to this pipe */
9727         for (i = 0; i < crtc->num_scalers; i++) {
9728                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9729                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9730                         id = i;
9731                         pipe_config->pch_pfit.enabled = true;
9732                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9733                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9734                         break;
9735                 }
9736         }
9737
9738         scaler_state->scaler_id = id;
9739         if (id >= 0) {
9740                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9741         } else {
9742                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9743         }
9744 }
9745
9746 static void
9747 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9748                                  struct intel_initial_plane_config *plane_config)
9749 {
9750         struct drm_device *dev = crtc->base.dev;
9751         struct drm_i915_private *dev_priv = to_i915(dev);
9752         u32 val, base, offset, stride_mult, tiling;
9753         int pipe = crtc->pipe;
9754         int fourcc, pixel_format;
9755         unsigned int aligned_height;
9756         struct drm_framebuffer *fb;
9757         struct intel_framebuffer *intel_fb;
9758
9759         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9760         if (!intel_fb) {
9761                 DRM_DEBUG_KMS("failed to alloc fb\n");
9762                 return;
9763         }
9764
9765         fb = &intel_fb->base;
9766
9767         val = I915_READ(PLANE_CTL(pipe, 0));
9768         if (!(val & PLANE_CTL_ENABLE))
9769                 goto error;
9770
9771         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9772         fourcc = skl_format_to_fourcc(pixel_format,
9773                                       val & PLANE_CTL_ORDER_RGBX,
9774                                       val & PLANE_CTL_ALPHA_MASK);
9775         fb->pixel_format = fourcc;
9776         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9777
9778         tiling = val & PLANE_CTL_TILED_MASK;
9779         switch (tiling) {
9780         case PLANE_CTL_TILED_LINEAR:
9781                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9782                 break;
9783         case PLANE_CTL_TILED_X:
9784                 plane_config->tiling = I915_TILING_X;
9785                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9786                 break;
9787         case PLANE_CTL_TILED_Y:
9788                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9789                 break;
9790         case PLANE_CTL_TILED_YF:
9791                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9792                 break;
9793         default:
9794                 MISSING_CASE(tiling);
9795                 goto error;
9796         }
9797
9798         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9799         plane_config->base = base;
9800
9801         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9802
9803         val = I915_READ(PLANE_SIZE(pipe, 0));
9804         fb->height = ((val >> 16) & 0xfff) + 1;
9805         fb->width = ((val >> 0) & 0x1fff) + 1;
9806
9807         val = I915_READ(PLANE_STRIDE(pipe, 0));
9808         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9809                                                 fb->pixel_format);
9810         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9811
9812         aligned_height = intel_fb_align_height(dev, fb->height,
9813                                                fb->pixel_format,
9814                                                fb->modifier[0]);
9815
9816         plane_config->size = fb->pitches[0] * aligned_height;
9817
9818         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9819                       pipe_name(pipe), fb->width, fb->height,
9820                       fb->bits_per_pixel, base, fb->pitches[0],
9821                       plane_config->size);
9822
9823         plane_config->fb = intel_fb;
9824         return;
9825
9826 error:
9827         kfree(intel_fb);
9828 }
9829
9830 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9831                                      struct intel_crtc_state *pipe_config)
9832 {
9833         struct drm_device *dev = crtc->base.dev;
9834         struct drm_i915_private *dev_priv = to_i915(dev);
9835         uint32_t tmp;
9836
9837         tmp = I915_READ(PF_CTL(crtc->pipe));
9838
9839         if (tmp & PF_ENABLE) {
9840                 pipe_config->pch_pfit.enabled = true;
9841                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9842                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9843
9844                 /* We currently do not free assignements of panel fitters on
9845                  * ivb/hsw (since we don't use the higher upscaling modes which
9846                  * differentiates them) so just WARN about this case for now. */
9847                 if (IS_GEN7(dev)) {
9848                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9849                                 PF_PIPE_SEL_IVB(crtc->pipe));
9850                 }
9851         }
9852 }
9853
9854 static void
9855 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9856                                   struct intel_initial_plane_config *plane_config)
9857 {
9858         struct drm_device *dev = crtc->base.dev;
9859         struct drm_i915_private *dev_priv = to_i915(dev);
9860         u32 val, base, offset;
9861         int pipe = crtc->pipe;
9862         int fourcc, pixel_format;
9863         unsigned int aligned_height;
9864         struct drm_framebuffer *fb;
9865         struct intel_framebuffer *intel_fb;
9866
9867         val = I915_READ(DSPCNTR(pipe));
9868         if (!(val & DISPLAY_PLANE_ENABLE))
9869                 return;
9870
9871         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9872         if (!intel_fb) {
9873                 DRM_DEBUG_KMS("failed to alloc fb\n");
9874                 return;
9875         }
9876
9877         fb = &intel_fb->base;
9878
9879         if (INTEL_INFO(dev)->gen >= 4) {
9880                 if (val & DISPPLANE_TILED) {
9881                         plane_config->tiling = I915_TILING_X;
9882                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9883                 }
9884         }
9885
9886         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9887         fourcc = i9xx_format_to_fourcc(pixel_format);
9888         fb->pixel_format = fourcc;
9889         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9890
9891         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9892         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9893                 offset = I915_READ(DSPOFFSET(pipe));
9894         } else {
9895                 if (plane_config->tiling)
9896                         offset = I915_READ(DSPTILEOFF(pipe));
9897                 else
9898                         offset = I915_READ(DSPLINOFF(pipe));
9899         }
9900         plane_config->base = base;
9901
9902         val = I915_READ(PIPESRC(pipe));
9903         fb->width = ((val >> 16) & 0xfff) + 1;
9904         fb->height = ((val >> 0) & 0xfff) + 1;
9905
9906         val = I915_READ(DSPSTRIDE(pipe));
9907         fb->pitches[0] = val & 0xffffffc0;
9908
9909         aligned_height = intel_fb_align_height(dev, fb->height,
9910                                                fb->pixel_format,
9911                                                fb->modifier[0]);
9912
9913         plane_config->size = fb->pitches[0] * aligned_height;
9914
9915         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9916                       pipe_name(pipe), fb->width, fb->height,
9917                       fb->bits_per_pixel, base, fb->pitches[0],
9918                       plane_config->size);
9919
9920         plane_config->fb = intel_fb;
9921 }
9922
9923 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9924                                      struct intel_crtc_state *pipe_config)
9925 {
9926         struct drm_device *dev = crtc->base.dev;
9927         struct drm_i915_private *dev_priv = to_i915(dev);
9928         enum intel_display_power_domain power_domain;
9929         uint32_t tmp;
9930         bool ret;
9931
9932         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9933         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9934                 return false;
9935
9936         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9937         pipe_config->shared_dpll = NULL;
9938
9939         ret = false;
9940         tmp = I915_READ(PIPECONF(crtc->pipe));
9941         if (!(tmp & PIPECONF_ENABLE))
9942                 goto out;
9943
9944         switch (tmp & PIPECONF_BPC_MASK) {
9945         case PIPECONF_6BPC:
9946                 pipe_config->pipe_bpp = 18;
9947                 break;
9948         case PIPECONF_8BPC:
9949                 pipe_config->pipe_bpp = 24;
9950                 break;
9951         case PIPECONF_10BPC:
9952                 pipe_config->pipe_bpp = 30;
9953                 break;
9954         case PIPECONF_12BPC:
9955                 pipe_config->pipe_bpp = 36;
9956                 break;
9957         default:
9958                 break;
9959         }
9960
9961         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9962                 pipe_config->limited_color_range = true;
9963
9964         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9965                 struct intel_shared_dpll *pll;
9966                 enum intel_dpll_id pll_id;
9967
9968                 pipe_config->has_pch_encoder = true;
9969
9970                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9971                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9972                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9973
9974                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9975
9976                 if (HAS_PCH_IBX(dev_priv)) {
9977                         /*
9978                          * The pipe->pch transcoder and pch transcoder->pll
9979                          * mapping is fixed.
9980                          */
9981                         pll_id = (enum intel_dpll_id) crtc->pipe;
9982                 } else {
9983                         tmp = I915_READ(PCH_DPLL_SEL);
9984                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9985                                 pll_id = DPLL_ID_PCH_PLL_B;
9986                         else
9987                                 pll_id= DPLL_ID_PCH_PLL_A;
9988                 }
9989
9990                 pipe_config->shared_dpll =
9991                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9992                 pll = pipe_config->shared_dpll;
9993
9994                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9995                                                  &pipe_config->dpll_hw_state));
9996
9997                 tmp = pipe_config->dpll_hw_state.dpll;
9998                 pipe_config->pixel_multiplier =
9999                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10000                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10001
10002                 ironlake_pch_clock_get(crtc, pipe_config);
10003         } else {
10004                 pipe_config->pixel_multiplier = 1;
10005         }
10006
10007         intel_get_pipe_timings(crtc, pipe_config);
10008         intel_get_pipe_src_size(crtc, pipe_config);
10009
10010         ironlake_get_pfit_config(crtc, pipe_config);
10011
10012         ret = true;
10013
10014 out:
10015         intel_display_power_put(dev_priv, power_domain);
10016
10017         return ret;
10018 }
10019
10020 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10021 {
10022         struct drm_device *dev = &dev_priv->drm;
10023         struct intel_crtc *crtc;
10024
10025         for_each_intel_crtc(dev, crtc)
10026                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10027                      pipe_name(crtc->pipe));
10028
10029         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10030         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10031         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10032         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10033         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10034         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10035              "CPU PWM1 enabled\n");
10036         if (IS_HASWELL(dev_priv))
10037                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10038                      "CPU PWM2 enabled\n");
10039         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10040              "PCH PWM1 enabled\n");
10041         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10042              "Utility pin enabled\n");
10043         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10044
10045         /*
10046          * In theory we can still leave IRQs enabled, as long as only the HPD
10047          * interrupts remain enabled. We used to check for that, but since it's
10048          * gen-specific and since we only disable LCPLL after we fully disable
10049          * the interrupts, the check below should be enough.
10050          */
10051         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10052 }
10053
10054 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10055 {
10056         if (IS_HASWELL(dev_priv))
10057                 return I915_READ(D_COMP_HSW);
10058         else
10059                 return I915_READ(D_COMP_BDW);
10060 }
10061
10062 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10063 {
10064         if (IS_HASWELL(dev_priv)) {
10065                 mutex_lock(&dev_priv->rps.hw_lock);
10066                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10067                                             val))
10068                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10069                 mutex_unlock(&dev_priv->rps.hw_lock);
10070         } else {
10071                 I915_WRITE(D_COMP_BDW, val);
10072                 POSTING_READ(D_COMP_BDW);
10073         }
10074 }
10075
10076 /*
10077  * This function implements pieces of two sequences from BSpec:
10078  * - Sequence for display software to disable LCPLL
10079  * - Sequence for display software to allow package C8+
10080  * The steps implemented here are just the steps that actually touch the LCPLL
10081  * register. Callers should take care of disabling all the display engine
10082  * functions, doing the mode unset, fixing interrupts, etc.
10083  */
10084 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10085                               bool switch_to_fclk, bool allow_power_down)
10086 {
10087         uint32_t val;
10088
10089         assert_can_disable_lcpll(dev_priv);
10090
10091         val = I915_READ(LCPLL_CTL);
10092
10093         if (switch_to_fclk) {
10094                 val |= LCPLL_CD_SOURCE_FCLK;
10095                 I915_WRITE(LCPLL_CTL, val);
10096
10097                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10098                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10099                         DRM_ERROR("Switching to FCLK failed\n");
10100
10101                 val = I915_READ(LCPLL_CTL);
10102         }
10103
10104         val |= LCPLL_PLL_DISABLE;
10105         I915_WRITE(LCPLL_CTL, val);
10106         POSTING_READ(LCPLL_CTL);
10107
10108         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10109                 DRM_ERROR("LCPLL still locked\n");
10110
10111         val = hsw_read_dcomp(dev_priv);
10112         val |= D_COMP_COMP_DISABLE;
10113         hsw_write_dcomp(dev_priv, val);
10114         ndelay(100);
10115
10116         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10117                      1))
10118                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10119
10120         if (allow_power_down) {
10121                 val = I915_READ(LCPLL_CTL);
10122                 val |= LCPLL_POWER_DOWN_ALLOW;
10123                 I915_WRITE(LCPLL_CTL, val);
10124                 POSTING_READ(LCPLL_CTL);
10125         }
10126 }
10127
10128 /*
10129  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10130  * source.
10131  */
10132 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10133 {
10134         uint32_t val;
10135
10136         val = I915_READ(LCPLL_CTL);
10137
10138         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10139                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10140                 return;
10141
10142         /*
10143          * Make sure we're not on PC8 state before disabling PC8, otherwise
10144          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10145          */
10146         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10147
10148         if (val & LCPLL_POWER_DOWN_ALLOW) {
10149                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10150                 I915_WRITE(LCPLL_CTL, val);
10151                 POSTING_READ(LCPLL_CTL);
10152         }
10153
10154         val = hsw_read_dcomp(dev_priv);
10155         val |= D_COMP_COMP_FORCE;
10156         val &= ~D_COMP_COMP_DISABLE;
10157         hsw_write_dcomp(dev_priv, val);
10158
10159         val = I915_READ(LCPLL_CTL);
10160         val &= ~LCPLL_PLL_DISABLE;
10161         I915_WRITE(LCPLL_CTL, val);
10162
10163         if (intel_wait_for_register(dev_priv,
10164                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10165                                     5))
10166                 DRM_ERROR("LCPLL not locked yet\n");
10167
10168         if (val & LCPLL_CD_SOURCE_FCLK) {
10169                 val = I915_READ(LCPLL_CTL);
10170                 val &= ~LCPLL_CD_SOURCE_FCLK;
10171                 I915_WRITE(LCPLL_CTL, val);
10172
10173                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10174                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10175                         DRM_ERROR("Switching back to LCPLL failed\n");
10176         }
10177
10178         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10179         intel_update_cdclk(&dev_priv->drm);
10180 }
10181
10182 /*
10183  * Package states C8 and deeper are really deep PC states that can only be
10184  * reached when all the devices on the system allow it, so even if the graphics
10185  * device allows PC8+, it doesn't mean the system will actually get to these
10186  * states. Our driver only allows PC8+ when going into runtime PM.
10187  *
10188  * The requirements for PC8+ are that all the outputs are disabled, the power
10189  * well is disabled and most interrupts are disabled, and these are also
10190  * requirements for runtime PM. When these conditions are met, we manually do
10191  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10192  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10193  * hang the machine.
10194  *
10195  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10196  * the state of some registers, so when we come back from PC8+ we need to
10197  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10198  * need to take care of the registers kept by RC6. Notice that this happens even
10199  * if we don't put the device in PCI D3 state (which is what currently happens
10200  * because of the runtime PM support).
10201  *
10202  * For more, read "Display Sequences for Package C8" on the hardware
10203  * documentation.
10204  */
10205 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10206 {
10207         struct drm_device *dev = &dev_priv->drm;
10208         uint32_t val;
10209
10210         DRM_DEBUG_KMS("Enabling package C8+\n");
10211
10212         if (HAS_PCH_LPT_LP(dev_priv)) {
10213                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10214                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10215                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10216         }
10217
10218         lpt_disable_clkout_dp(dev);
10219         hsw_disable_lcpll(dev_priv, true, true);
10220 }
10221
10222 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10223 {
10224         struct drm_device *dev = &dev_priv->drm;
10225         uint32_t val;
10226
10227         DRM_DEBUG_KMS("Disabling package C8+\n");
10228
10229         hsw_restore_lcpll(dev_priv);
10230         lpt_init_pch_refclk(dev);
10231
10232         if (HAS_PCH_LPT_LP(dev_priv)) {
10233                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10234                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10235                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10236         }
10237 }
10238
10239 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10240 {
10241         struct drm_device *dev = old_state->dev;
10242         struct intel_atomic_state *old_intel_state =
10243                 to_intel_atomic_state(old_state);
10244         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10245
10246         bxt_set_cdclk(to_i915(dev), req_cdclk);
10247 }
10248
10249 /* compute the max rate for new configuration */
10250 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10251 {
10252         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10253         struct drm_i915_private *dev_priv = to_i915(state->dev);
10254         struct drm_crtc *crtc;
10255         struct drm_crtc_state *cstate;
10256         struct intel_crtc_state *crtc_state;
10257         unsigned max_pixel_rate = 0, i;
10258         enum pipe pipe;
10259
10260         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10261                sizeof(intel_state->min_pixclk));
10262
10263         for_each_crtc_in_state(state, crtc, cstate, i) {
10264                 int pixel_rate;
10265
10266                 crtc_state = to_intel_crtc_state(cstate);
10267                 if (!crtc_state->base.enable) {
10268                         intel_state->min_pixclk[i] = 0;
10269                         continue;
10270                 }
10271
10272                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10273
10274                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10275                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10276                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10277
10278                 intel_state->min_pixclk[i] = pixel_rate;
10279         }
10280
10281         for_each_pipe(dev_priv, pipe)
10282                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10283
10284         return max_pixel_rate;
10285 }
10286
10287 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10288 {
10289         struct drm_i915_private *dev_priv = to_i915(dev);
10290         uint32_t val, data;
10291         int ret;
10292
10293         if (WARN((I915_READ(LCPLL_CTL) &
10294                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10295                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10296                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10297                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10298                  "trying to change cdclk frequency with cdclk not enabled\n"))
10299                 return;
10300
10301         mutex_lock(&dev_priv->rps.hw_lock);
10302         ret = sandybridge_pcode_write(dev_priv,
10303                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10304         mutex_unlock(&dev_priv->rps.hw_lock);
10305         if (ret) {
10306                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10307                 return;
10308         }
10309
10310         val = I915_READ(LCPLL_CTL);
10311         val |= LCPLL_CD_SOURCE_FCLK;
10312         I915_WRITE(LCPLL_CTL, val);
10313
10314         if (wait_for_us(I915_READ(LCPLL_CTL) &
10315                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10316                 DRM_ERROR("Switching to FCLK failed\n");
10317
10318         val = I915_READ(LCPLL_CTL);
10319         val &= ~LCPLL_CLK_FREQ_MASK;
10320
10321         switch (cdclk) {
10322         case 450000:
10323                 val |= LCPLL_CLK_FREQ_450;
10324                 data = 0;
10325                 break;
10326         case 540000:
10327                 val |= LCPLL_CLK_FREQ_54O_BDW;
10328                 data = 1;
10329                 break;
10330         case 337500:
10331                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10332                 data = 2;
10333                 break;
10334         case 675000:
10335                 val |= LCPLL_CLK_FREQ_675_BDW;
10336                 data = 3;
10337                 break;
10338         default:
10339                 WARN(1, "invalid cdclk frequency\n");
10340                 return;
10341         }
10342
10343         I915_WRITE(LCPLL_CTL, val);
10344
10345         val = I915_READ(LCPLL_CTL);
10346         val &= ~LCPLL_CD_SOURCE_FCLK;
10347         I915_WRITE(LCPLL_CTL, val);
10348
10349         if (wait_for_us((I915_READ(LCPLL_CTL) &
10350                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10351                 DRM_ERROR("Switching back to LCPLL failed\n");
10352
10353         mutex_lock(&dev_priv->rps.hw_lock);
10354         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10355         mutex_unlock(&dev_priv->rps.hw_lock);
10356
10357         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10358
10359         intel_update_cdclk(dev);
10360
10361         WARN(cdclk != dev_priv->cdclk_freq,
10362              "cdclk requested %d kHz but got %d kHz\n",
10363              cdclk, dev_priv->cdclk_freq);
10364 }
10365
10366 static int broadwell_calc_cdclk(int max_pixclk)
10367 {
10368         if (max_pixclk > 540000)
10369                 return 675000;
10370         else if (max_pixclk > 450000)
10371                 return 540000;
10372         else if (max_pixclk > 337500)
10373                 return 450000;
10374         else
10375                 return 337500;
10376 }
10377
10378 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10379 {
10380         struct drm_i915_private *dev_priv = to_i915(state->dev);
10381         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10382         int max_pixclk = ilk_max_pixel_rate(state);
10383         int cdclk;
10384
10385         /*
10386          * FIXME should also account for plane ratio
10387          * once 64bpp pixel formats are supported.
10388          */
10389         cdclk = broadwell_calc_cdclk(max_pixclk);
10390
10391         if (cdclk > dev_priv->max_cdclk_freq) {
10392                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10393                               cdclk, dev_priv->max_cdclk_freq);
10394                 return -EINVAL;
10395         }
10396
10397         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10398         if (!intel_state->active_crtcs)
10399                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10400
10401         return 0;
10402 }
10403
10404 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10405 {
10406         struct drm_device *dev = old_state->dev;
10407         struct intel_atomic_state *old_intel_state =
10408                 to_intel_atomic_state(old_state);
10409         unsigned req_cdclk = old_intel_state->dev_cdclk;
10410
10411         broadwell_set_cdclk(dev, req_cdclk);
10412 }
10413
10414 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10415 {
10416         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10417         struct drm_i915_private *dev_priv = to_i915(state->dev);
10418         const int max_pixclk = ilk_max_pixel_rate(state);
10419         int vco = intel_state->cdclk_pll_vco;
10420         int cdclk;
10421
10422         /*
10423          * FIXME should also account for plane ratio
10424          * once 64bpp pixel formats are supported.
10425          */
10426         cdclk = skl_calc_cdclk(max_pixclk, vco);
10427
10428         /*
10429          * FIXME move the cdclk caclulation to
10430          * compute_config() so we can fail gracegully.
10431          */
10432         if (cdclk > dev_priv->max_cdclk_freq) {
10433                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10434                           cdclk, dev_priv->max_cdclk_freq);
10435                 cdclk = dev_priv->max_cdclk_freq;
10436         }
10437
10438         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10439         if (!intel_state->active_crtcs)
10440                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10441
10442         return 0;
10443 }
10444
10445 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10446 {
10447         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10448         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10449         unsigned int req_cdclk = intel_state->dev_cdclk;
10450         unsigned int req_vco = intel_state->cdclk_pll_vco;
10451
10452         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10453 }
10454
10455 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10456                                       struct intel_crtc_state *crtc_state)
10457 {
10458         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10459                 if (!intel_ddi_pll_select(crtc, crtc_state))
10460                         return -EINVAL;
10461         }
10462
10463         crtc->lowfreq_avail = false;
10464
10465         return 0;
10466 }
10467
10468 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10469                                 enum port port,
10470                                 struct intel_crtc_state *pipe_config)
10471 {
10472         enum intel_dpll_id id;
10473
10474         switch (port) {
10475         case PORT_A:
10476                 id = DPLL_ID_SKL_DPLL0;
10477                 break;
10478         case PORT_B:
10479                 id = DPLL_ID_SKL_DPLL1;
10480                 break;
10481         case PORT_C:
10482                 id = DPLL_ID_SKL_DPLL2;
10483                 break;
10484         default:
10485                 DRM_ERROR("Incorrect port type\n");
10486                 return;
10487         }
10488
10489         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10490 }
10491
10492 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10493                                 enum port port,
10494                                 struct intel_crtc_state *pipe_config)
10495 {
10496         enum intel_dpll_id id;
10497         u32 temp;
10498
10499         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10500         id = temp >> (port * 3 + 1);
10501
10502         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10503                 return;
10504
10505         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10506 }
10507
10508 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10509                                 enum port port,
10510                                 struct intel_crtc_state *pipe_config)
10511 {
10512         enum intel_dpll_id id;
10513         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10514
10515         switch (ddi_pll_sel) {
10516         case PORT_CLK_SEL_WRPLL1:
10517                 id = DPLL_ID_WRPLL1;
10518                 break;
10519         case PORT_CLK_SEL_WRPLL2:
10520                 id = DPLL_ID_WRPLL2;
10521                 break;
10522         case PORT_CLK_SEL_SPLL:
10523                 id = DPLL_ID_SPLL;
10524                 break;
10525         case PORT_CLK_SEL_LCPLL_810:
10526                 id = DPLL_ID_LCPLL_810;
10527                 break;
10528         case PORT_CLK_SEL_LCPLL_1350:
10529                 id = DPLL_ID_LCPLL_1350;
10530                 break;
10531         case PORT_CLK_SEL_LCPLL_2700:
10532                 id = DPLL_ID_LCPLL_2700;
10533                 break;
10534         default:
10535                 MISSING_CASE(ddi_pll_sel);
10536                 /* fall through */
10537         case PORT_CLK_SEL_NONE:
10538                 return;
10539         }
10540
10541         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10542 }
10543
10544 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10545                                      struct intel_crtc_state *pipe_config,
10546                                      unsigned long *power_domain_mask)
10547 {
10548         struct drm_device *dev = crtc->base.dev;
10549         struct drm_i915_private *dev_priv = to_i915(dev);
10550         enum intel_display_power_domain power_domain;
10551         u32 tmp;
10552
10553         /*
10554          * The pipe->transcoder mapping is fixed with the exception of the eDP
10555          * transcoder handled below.
10556          */
10557         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10558
10559         /*
10560          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10561          * consistency and less surprising code; it's in always on power).
10562          */
10563         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10564         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10565                 enum pipe trans_edp_pipe;
10566                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10567                 default:
10568                         WARN(1, "unknown pipe linked to edp transcoder\n");
10569                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10570                 case TRANS_DDI_EDP_INPUT_A_ON:
10571                         trans_edp_pipe = PIPE_A;
10572                         break;
10573                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10574                         trans_edp_pipe = PIPE_B;
10575                         break;
10576                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10577                         trans_edp_pipe = PIPE_C;
10578                         break;
10579                 }
10580
10581                 if (trans_edp_pipe == crtc->pipe)
10582                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10583         }
10584
10585         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10586         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10587                 return false;
10588         *power_domain_mask |= BIT(power_domain);
10589
10590         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10591
10592         return tmp & PIPECONF_ENABLE;
10593 }
10594
10595 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10596                                          struct intel_crtc_state *pipe_config,
10597                                          unsigned long *power_domain_mask)
10598 {
10599         struct drm_device *dev = crtc->base.dev;
10600         struct drm_i915_private *dev_priv = to_i915(dev);
10601         enum intel_display_power_domain power_domain;
10602         enum port port;
10603         enum transcoder cpu_transcoder;
10604         u32 tmp;
10605
10606         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10607                 if (port == PORT_A)
10608                         cpu_transcoder = TRANSCODER_DSI_A;
10609                 else
10610                         cpu_transcoder = TRANSCODER_DSI_C;
10611
10612                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10613                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10614                         continue;
10615                 *power_domain_mask |= BIT(power_domain);
10616
10617                 /*
10618                  * The PLL needs to be enabled with a valid divider
10619                  * configuration, otherwise accessing DSI registers will hang
10620                  * the machine. See BSpec North Display Engine
10621                  * registers/MIPI[BXT]. We can break out here early, since we
10622                  * need the same DSI PLL to be enabled for both DSI ports.
10623                  */
10624                 if (!intel_dsi_pll_is_enabled(dev_priv))
10625                         break;
10626
10627                 /* XXX: this works for video mode only */
10628                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10629                 if (!(tmp & DPI_ENABLE))
10630                         continue;
10631
10632                 tmp = I915_READ(MIPI_CTRL(port));
10633                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10634                         continue;
10635
10636                 pipe_config->cpu_transcoder = cpu_transcoder;
10637                 break;
10638         }
10639
10640         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10641 }
10642
10643 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10644                                        struct intel_crtc_state *pipe_config)
10645 {
10646         struct drm_device *dev = crtc->base.dev;
10647         struct drm_i915_private *dev_priv = to_i915(dev);
10648         struct intel_shared_dpll *pll;
10649         enum port port;
10650         uint32_t tmp;
10651
10652         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10653
10654         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10655
10656         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10657                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10658         else if (IS_BROXTON(dev_priv))
10659                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10660         else
10661                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10662
10663         pll = pipe_config->shared_dpll;
10664         if (pll) {
10665                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10666                                                  &pipe_config->dpll_hw_state));
10667         }
10668
10669         /*
10670          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10671          * DDI E. So just check whether this pipe is wired to DDI E and whether
10672          * the PCH transcoder is on.
10673          */
10674         if (INTEL_INFO(dev)->gen < 9 &&
10675             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10676                 pipe_config->has_pch_encoder = true;
10677
10678                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10679                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10680                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10681
10682                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10683         }
10684 }
10685
10686 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10687                                     struct intel_crtc_state *pipe_config)
10688 {
10689         struct drm_device *dev = crtc->base.dev;
10690         struct drm_i915_private *dev_priv = to_i915(dev);
10691         enum intel_display_power_domain power_domain;
10692         unsigned long power_domain_mask;
10693         bool active;
10694
10695         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10696         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10697                 return false;
10698         power_domain_mask = BIT(power_domain);
10699
10700         pipe_config->shared_dpll = NULL;
10701
10702         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10703
10704         if (IS_BROXTON(dev_priv) &&
10705             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10706                 WARN_ON(active);
10707                 active = true;
10708         }
10709
10710         if (!active)
10711                 goto out;
10712
10713         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10714                 haswell_get_ddi_port_state(crtc, pipe_config);
10715                 intel_get_pipe_timings(crtc, pipe_config);
10716         }
10717
10718         intel_get_pipe_src_size(crtc, pipe_config);
10719
10720         pipe_config->gamma_mode =
10721                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10722
10723         if (INTEL_INFO(dev)->gen >= 9) {
10724                 skl_init_scalers(dev, crtc, pipe_config);
10725         }
10726
10727         if (INTEL_INFO(dev)->gen >= 9) {
10728                 pipe_config->scaler_state.scaler_id = -1;
10729                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10730         }
10731
10732         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10733         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10734                 power_domain_mask |= BIT(power_domain);
10735                 if (INTEL_INFO(dev)->gen >= 9)
10736                         skylake_get_pfit_config(crtc, pipe_config);
10737                 else
10738                         ironlake_get_pfit_config(crtc, pipe_config);
10739         }
10740
10741         if (IS_HASWELL(dev_priv))
10742                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10743                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10744
10745         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10746             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10747                 pipe_config->pixel_multiplier =
10748                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10749         } else {
10750                 pipe_config->pixel_multiplier = 1;
10751         }
10752
10753 out:
10754         for_each_power_domain(power_domain, power_domain_mask)
10755                 intel_display_power_put(dev_priv, power_domain);
10756
10757         return active;
10758 }
10759
10760 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10761                                const struct intel_plane_state *plane_state)
10762 {
10763         struct drm_device *dev = crtc->dev;
10764         struct drm_i915_private *dev_priv = to_i915(dev);
10765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10766         uint32_t cntl = 0, size = 0;
10767
10768         if (plane_state && plane_state->base.visible) {
10769                 unsigned int width = plane_state->base.crtc_w;
10770                 unsigned int height = plane_state->base.crtc_h;
10771                 unsigned int stride = roundup_pow_of_two(width) * 4;
10772
10773                 switch (stride) {
10774                 default:
10775                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10776                                   width, stride);
10777                         stride = 256;
10778                         /* fallthrough */
10779                 case 256:
10780                 case 512:
10781                 case 1024:
10782                 case 2048:
10783                         break;
10784                 }
10785
10786                 cntl |= CURSOR_ENABLE |
10787                         CURSOR_GAMMA_ENABLE |
10788                         CURSOR_FORMAT_ARGB |
10789                         CURSOR_STRIDE(stride);
10790
10791                 size = (height << 12) | width;
10792         }
10793
10794         if (intel_crtc->cursor_cntl != 0 &&
10795             (intel_crtc->cursor_base != base ||
10796              intel_crtc->cursor_size != size ||
10797              intel_crtc->cursor_cntl != cntl)) {
10798                 /* On these chipsets we can only modify the base/size/stride
10799                  * whilst the cursor is disabled.
10800                  */
10801                 I915_WRITE(CURCNTR(PIPE_A), 0);
10802                 POSTING_READ(CURCNTR(PIPE_A));
10803                 intel_crtc->cursor_cntl = 0;
10804         }
10805
10806         if (intel_crtc->cursor_base != base) {
10807                 I915_WRITE(CURBASE(PIPE_A), base);
10808                 intel_crtc->cursor_base = base;
10809         }
10810
10811         if (intel_crtc->cursor_size != size) {
10812                 I915_WRITE(CURSIZE, size);
10813                 intel_crtc->cursor_size = size;
10814         }
10815
10816         if (intel_crtc->cursor_cntl != cntl) {
10817                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10818                 POSTING_READ(CURCNTR(PIPE_A));
10819                 intel_crtc->cursor_cntl = cntl;
10820         }
10821 }
10822
10823 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10824                                const struct intel_plane_state *plane_state)
10825 {
10826         struct drm_device *dev = crtc->dev;
10827         struct drm_i915_private *dev_priv = to_i915(dev);
10828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10829         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10830         int pipe = intel_crtc->pipe;
10831         uint32_t cntl = 0;
10832
10833         if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10834                 skl_write_cursor_wm(intel_crtc, wm);
10835
10836         if (plane_state && plane_state->base.visible) {
10837                 cntl = MCURSOR_GAMMA_ENABLE;
10838                 switch (plane_state->base.crtc_w) {
10839                         case 64:
10840                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10841                                 break;
10842                         case 128:
10843                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10844                                 break;
10845                         case 256:
10846                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10847                                 break;
10848                         default:
10849                                 MISSING_CASE(plane_state->base.crtc_w);
10850                                 return;
10851                 }
10852                 cntl |= pipe << 28; /* Connect to correct pipe */
10853
10854                 if (HAS_DDI(dev_priv))
10855                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10856
10857                 if (plane_state->base.rotation == DRM_ROTATE_180)
10858                         cntl |= CURSOR_ROTATE_180;
10859         }
10860
10861         if (intel_crtc->cursor_cntl != cntl) {
10862                 I915_WRITE(CURCNTR(pipe), cntl);
10863                 POSTING_READ(CURCNTR(pipe));
10864                 intel_crtc->cursor_cntl = cntl;
10865         }
10866
10867         /* and commit changes on next vblank */
10868         I915_WRITE(CURBASE(pipe), base);
10869         POSTING_READ(CURBASE(pipe));
10870
10871         intel_crtc->cursor_base = base;
10872 }
10873
10874 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10875 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10876                                      const struct intel_plane_state *plane_state)
10877 {
10878         struct drm_device *dev = crtc->dev;
10879         struct drm_i915_private *dev_priv = to_i915(dev);
10880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10881         int pipe = intel_crtc->pipe;
10882         u32 base = intel_crtc->cursor_addr;
10883         u32 pos = 0;
10884
10885         if (plane_state) {
10886                 int x = plane_state->base.crtc_x;
10887                 int y = plane_state->base.crtc_y;
10888
10889                 if (x < 0) {
10890                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10891                         x = -x;
10892                 }
10893                 pos |= x << CURSOR_X_SHIFT;
10894
10895                 if (y < 0) {
10896                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10897                         y = -y;
10898                 }
10899                 pos |= y << CURSOR_Y_SHIFT;
10900
10901                 /* ILK+ do this automagically */
10902                 if (HAS_GMCH_DISPLAY(dev_priv) &&
10903                     plane_state->base.rotation == DRM_ROTATE_180) {
10904                         base += (plane_state->base.crtc_h *
10905                                  plane_state->base.crtc_w - 1) * 4;
10906                 }
10907         }
10908
10909         I915_WRITE(CURPOS(pipe), pos);
10910
10911         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
10912                 i845_update_cursor(crtc, base, plane_state);
10913         else
10914                 i9xx_update_cursor(crtc, base, plane_state);
10915 }
10916
10917 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10918                            uint32_t width, uint32_t height)
10919 {
10920         if (width == 0 || height == 0)
10921                 return false;
10922
10923         /*
10924          * 845g/865g are special in that they are only limited by
10925          * the width of their cursors, the height is arbitrary up to
10926          * the precision of the register. Everything else requires
10927          * square cursors, limited to a few power-of-two sizes.
10928          */
10929         if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
10930                 if ((width & 63) != 0)
10931                         return false;
10932
10933                 if (width > (IS_845G(dev_priv) ? 64 : 512))
10934                         return false;
10935
10936                 if (height > 1023)
10937                         return false;
10938         } else {
10939                 switch (width | height) {
10940                 case 256:
10941                 case 128:
10942                         if (IS_GEN2(dev_priv))
10943                                 return false;
10944                 case 64:
10945                         break;
10946                 default:
10947                         return false;
10948                 }
10949         }
10950
10951         return true;
10952 }
10953
10954 /* VESA 640x480x72Hz mode to set on the pipe */
10955 static struct drm_display_mode load_detect_mode = {
10956         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10957                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10958 };
10959
10960 struct drm_framebuffer *
10961 __intel_framebuffer_create(struct drm_device *dev,
10962                            struct drm_mode_fb_cmd2 *mode_cmd,
10963                            struct drm_i915_gem_object *obj)
10964 {
10965         struct intel_framebuffer *intel_fb;
10966         int ret;
10967
10968         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10969         if (!intel_fb)
10970                 return ERR_PTR(-ENOMEM);
10971
10972         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10973         if (ret)
10974                 goto err;
10975
10976         return &intel_fb->base;
10977
10978 err:
10979         kfree(intel_fb);
10980         return ERR_PTR(ret);
10981 }
10982
10983 static struct drm_framebuffer *
10984 intel_framebuffer_create(struct drm_device *dev,
10985                          struct drm_mode_fb_cmd2 *mode_cmd,
10986                          struct drm_i915_gem_object *obj)
10987 {
10988         struct drm_framebuffer *fb;
10989         int ret;
10990
10991         ret = i915_mutex_lock_interruptible(dev);
10992         if (ret)
10993                 return ERR_PTR(ret);
10994         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10995         mutex_unlock(&dev->struct_mutex);
10996
10997         return fb;
10998 }
10999
11000 static u32
11001 intel_framebuffer_pitch_for_width(int width, int bpp)
11002 {
11003         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11004         return ALIGN(pitch, 64);
11005 }
11006
11007 static u32
11008 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11009 {
11010         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11011         return PAGE_ALIGN(pitch * mode->vdisplay);
11012 }
11013
11014 static struct drm_framebuffer *
11015 intel_framebuffer_create_for_mode(struct drm_device *dev,
11016                                   struct drm_display_mode *mode,
11017                                   int depth, int bpp)
11018 {
11019         struct drm_framebuffer *fb;
11020         struct drm_i915_gem_object *obj;
11021         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11022
11023         obj = i915_gem_object_create(dev,
11024                                     intel_framebuffer_size_for_mode(mode, bpp));
11025         if (IS_ERR(obj))
11026                 return ERR_CAST(obj);
11027
11028         mode_cmd.width = mode->hdisplay;
11029         mode_cmd.height = mode->vdisplay;
11030         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11031                                                                 bpp);
11032         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11033
11034         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11035         if (IS_ERR(fb))
11036                 i915_gem_object_put_unlocked(obj);
11037
11038         return fb;
11039 }
11040
11041 static struct drm_framebuffer *
11042 mode_fits_in_fbdev(struct drm_device *dev,
11043                    struct drm_display_mode *mode)
11044 {
11045 #ifdef CONFIG_DRM_FBDEV_EMULATION
11046         struct drm_i915_private *dev_priv = to_i915(dev);
11047         struct drm_i915_gem_object *obj;
11048         struct drm_framebuffer *fb;
11049
11050         if (!dev_priv->fbdev)
11051                 return NULL;
11052
11053         if (!dev_priv->fbdev->fb)
11054                 return NULL;
11055
11056         obj = dev_priv->fbdev->fb->obj;
11057         BUG_ON(!obj);
11058
11059         fb = &dev_priv->fbdev->fb->base;
11060         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11061                                                                fb->bits_per_pixel))
11062                 return NULL;
11063
11064         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11065                 return NULL;
11066
11067         drm_framebuffer_reference(fb);
11068         return fb;
11069 #else
11070         return NULL;
11071 #endif
11072 }
11073
11074 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11075                                            struct drm_crtc *crtc,
11076                                            struct drm_display_mode *mode,
11077                                            struct drm_framebuffer *fb,
11078                                            int x, int y)
11079 {
11080         struct drm_plane_state *plane_state;
11081         int hdisplay, vdisplay;
11082         int ret;
11083
11084         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11085         if (IS_ERR(plane_state))
11086                 return PTR_ERR(plane_state);
11087
11088         if (mode)
11089                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11090         else
11091                 hdisplay = vdisplay = 0;
11092
11093         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11094         if (ret)
11095                 return ret;
11096         drm_atomic_set_fb_for_plane(plane_state, fb);
11097         plane_state->crtc_x = 0;
11098         plane_state->crtc_y = 0;
11099         plane_state->crtc_w = hdisplay;
11100         plane_state->crtc_h = vdisplay;
11101         plane_state->src_x = x << 16;
11102         plane_state->src_y = y << 16;
11103         plane_state->src_w = hdisplay << 16;
11104         plane_state->src_h = vdisplay << 16;
11105
11106         return 0;
11107 }
11108
11109 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11110                                 struct drm_display_mode *mode,
11111                                 struct intel_load_detect_pipe *old,
11112                                 struct drm_modeset_acquire_ctx *ctx)
11113 {
11114         struct intel_crtc *intel_crtc;
11115         struct intel_encoder *intel_encoder =
11116                 intel_attached_encoder(connector);
11117         struct drm_crtc *possible_crtc;
11118         struct drm_encoder *encoder = &intel_encoder->base;
11119         struct drm_crtc *crtc = NULL;
11120         struct drm_device *dev = encoder->dev;
11121         struct drm_framebuffer *fb;
11122         struct drm_mode_config *config = &dev->mode_config;
11123         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11124         struct drm_connector_state *connector_state;
11125         struct intel_crtc_state *crtc_state;
11126         int ret, i = -1;
11127
11128         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11129                       connector->base.id, connector->name,
11130                       encoder->base.id, encoder->name);
11131
11132         old->restore_state = NULL;
11133
11134 retry:
11135         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11136         if (ret)
11137                 goto fail;
11138
11139         /*
11140          * Algorithm gets a little messy:
11141          *
11142          *   - if the connector already has an assigned crtc, use it (but make
11143          *     sure it's on first)
11144          *
11145          *   - try to find the first unused crtc that can drive this connector,
11146          *     and use that if we find one
11147          */
11148
11149         /* See if we already have a CRTC for this connector */
11150         if (connector->state->crtc) {
11151                 crtc = connector->state->crtc;
11152
11153                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11154                 if (ret)
11155                         goto fail;
11156
11157                 /* Make sure the crtc and connector are running */
11158                 goto found;
11159         }
11160
11161         /* Find an unused one (if possible) */
11162         for_each_crtc(dev, possible_crtc) {
11163                 i++;
11164                 if (!(encoder->possible_crtcs & (1 << i)))
11165                         continue;
11166
11167                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11168                 if (ret)
11169                         goto fail;
11170
11171                 if (possible_crtc->state->enable) {
11172                         drm_modeset_unlock(&possible_crtc->mutex);
11173                         continue;
11174                 }
11175
11176                 crtc = possible_crtc;
11177                 break;
11178         }
11179
11180         /*
11181          * If we didn't find an unused CRTC, don't use any.
11182          */
11183         if (!crtc) {
11184                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11185                 goto fail;
11186         }
11187
11188 found:
11189         intel_crtc = to_intel_crtc(crtc);
11190
11191         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11192         if (ret)
11193                 goto fail;
11194
11195         state = drm_atomic_state_alloc(dev);
11196         restore_state = drm_atomic_state_alloc(dev);
11197         if (!state || !restore_state) {
11198                 ret = -ENOMEM;
11199                 goto fail;
11200         }
11201
11202         state->acquire_ctx = ctx;
11203         restore_state->acquire_ctx = ctx;
11204
11205         connector_state = drm_atomic_get_connector_state(state, connector);
11206         if (IS_ERR(connector_state)) {
11207                 ret = PTR_ERR(connector_state);
11208                 goto fail;
11209         }
11210
11211         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11212         if (ret)
11213                 goto fail;
11214
11215         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11216         if (IS_ERR(crtc_state)) {
11217                 ret = PTR_ERR(crtc_state);
11218                 goto fail;
11219         }
11220
11221         crtc_state->base.active = crtc_state->base.enable = true;
11222
11223         if (!mode)
11224                 mode = &load_detect_mode;
11225
11226         /* We need a framebuffer large enough to accommodate all accesses
11227          * that the plane may generate whilst we perform load detection.
11228          * We can not rely on the fbcon either being present (we get called
11229          * during its initialisation to detect all boot displays, or it may
11230          * not even exist) or that it is large enough to satisfy the
11231          * requested mode.
11232          */
11233         fb = mode_fits_in_fbdev(dev, mode);
11234         if (fb == NULL) {
11235                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11236                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11237         } else
11238                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11239         if (IS_ERR(fb)) {
11240                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11241                 goto fail;
11242         }
11243
11244         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11245         if (ret)
11246                 goto fail;
11247
11248         drm_framebuffer_unreference(fb);
11249
11250         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11251         if (ret)
11252                 goto fail;
11253
11254         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11255         if (!ret)
11256                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11257         if (!ret)
11258                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11259         if (ret) {
11260                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11261                 goto fail;
11262         }
11263
11264         ret = drm_atomic_commit(state);
11265         if (ret) {
11266                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11267                 goto fail;
11268         }
11269
11270         old->restore_state = restore_state;
11271
11272         /* let the connector get through one full cycle before testing */
11273         intel_wait_for_vblank(dev, intel_crtc->pipe);
11274         return true;
11275
11276 fail:
11277         drm_atomic_state_free(state);
11278         drm_atomic_state_free(restore_state);
11279         restore_state = state = NULL;
11280
11281         if (ret == -EDEADLK) {
11282                 drm_modeset_backoff(ctx);
11283                 goto retry;
11284         }
11285
11286         return false;
11287 }
11288
11289 void intel_release_load_detect_pipe(struct drm_connector *connector,
11290                                     struct intel_load_detect_pipe *old,
11291                                     struct drm_modeset_acquire_ctx *ctx)
11292 {
11293         struct intel_encoder *intel_encoder =
11294                 intel_attached_encoder(connector);
11295         struct drm_encoder *encoder = &intel_encoder->base;
11296         struct drm_atomic_state *state = old->restore_state;
11297         int ret;
11298
11299         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11300                       connector->base.id, connector->name,
11301                       encoder->base.id, encoder->name);
11302
11303         if (!state)
11304                 return;
11305
11306         ret = drm_atomic_commit(state);
11307         if (ret) {
11308                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11309                 drm_atomic_state_free(state);
11310         }
11311 }
11312
11313 static int i9xx_pll_refclk(struct drm_device *dev,
11314                            const struct intel_crtc_state *pipe_config)
11315 {
11316         struct drm_i915_private *dev_priv = to_i915(dev);
11317         u32 dpll = pipe_config->dpll_hw_state.dpll;
11318
11319         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11320                 return dev_priv->vbt.lvds_ssc_freq;
11321         else if (HAS_PCH_SPLIT(dev_priv))
11322                 return 120000;
11323         else if (!IS_GEN2(dev))
11324                 return 96000;
11325         else
11326                 return 48000;
11327 }
11328
11329 /* Returns the clock of the currently programmed mode of the given pipe. */
11330 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11331                                 struct intel_crtc_state *pipe_config)
11332 {
11333         struct drm_device *dev = crtc->base.dev;
11334         struct drm_i915_private *dev_priv = to_i915(dev);
11335         int pipe = pipe_config->cpu_transcoder;
11336         u32 dpll = pipe_config->dpll_hw_state.dpll;
11337         u32 fp;
11338         struct dpll clock;
11339         int port_clock;
11340         int refclk = i9xx_pll_refclk(dev, pipe_config);
11341
11342         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11343                 fp = pipe_config->dpll_hw_state.fp0;
11344         else
11345                 fp = pipe_config->dpll_hw_state.fp1;
11346
11347         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11348         if (IS_PINEVIEW(dev)) {
11349                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11350                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11351         } else {
11352                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11353                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11354         }
11355
11356         if (!IS_GEN2(dev)) {
11357                 if (IS_PINEVIEW(dev))
11358                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11359                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11360                 else
11361                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11362                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11363
11364                 switch (dpll & DPLL_MODE_MASK) {
11365                 case DPLLB_MODE_DAC_SERIAL:
11366                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11367                                 5 : 10;
11368                         break;
11369                 case DPLLB_MODE_LVDS:
11370                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11371                                 7 : 14;
11372                         break;
11373                 default:
11374                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11375                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11376                         return;
11377                 }
11378
11379                 if (IS_PINEVIEW(dev))
11380                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11381                 else
11382                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11383         } else {
11384                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11385                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11386
11387                 if (is_lvds) {
11388                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11389                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11390
11391                         if (lvds & LVDS_CLKB_POWER_UP)
11392                                 clock.p2 = 7;
11393                         else
11394                                 clock.p2 = 14;
11395                 } else {
11396                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11397                                 clock.p1 = 2;
11398                         else {
11399                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11400                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11401                         }
11402                         if (dpll & PLL_P2_DIVIDE_BY_4)
11403                                 clock.p2 = 4;
11404                         else
11405                                 clock.p2 = 2;
11406                 }
11407
11408                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11409         }
11410
11411         /*
11412          * This value includes pixel_multiplier. We will use
11413          * port_clock to compute adjusted_mode.crtc_clock in the
11414          * encoder's get_config() function.
11415          */
11416         pipe_config->port_clock = port_clock;
11417 }
11418
11419 int intel_dotclock_calculate(int link_freq,
11420                              const struct intel_link_m_n *m_n)
11421 {
11422         /*
11423          * The calculation for the data clock is:
11424          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11425          * But we want to avoid losing precison if possible, so:
11426          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11427          *
11428          * and the link clock is simpler:
11429          * link_clock = (m * link_clock) / n
11430          */
11431
11432         if (!m_n->link_n)
11433                 return 0;
11434
11435         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11436 }
11437
11438 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11439                                    struct intel_crtc_state *pipe_config)
11440 {
11441         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11442
11443         /* read out port_clock from the DPLL */
11444         i9xx_crtc_clock_get(crtc, pipe_config);
11445
11446         /*
11447          * In case there is an active pipe without active ports,
11448          * we may need some idea for the dotclock anyway.
11449          * Calculate one based on the FDI configuration.
11450          */
11451         pipe_config->base.adjusted_mode.crtc_clock =
11452                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11453                                          &pipe_config->fdi_m_n);
11454 }
11455
11456 /** Returns the currently programmed mode of the given pipe. */
11457 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11458                                              struct drm_crtc *crtc)
11459 {
11460         struct drm_i915_private *dev_priv = to_i915(dev);
11461         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11462         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11463         struct drm_display_mode *mode;
11464         struct intel_crtc_state *pipe_config;
11465         int htot = I915_READ(HTOTAL(cpu_transcoder));
11466         int hsync = I915_READ(HSYNC(cpu_transcoder));
11467         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11468         int vsync = I915_READ(VSYNC(cpu_transcoder));
11469         enum pipe pipe = intel_crtc->pipe;
11470
11471         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11472         if (!mode)
11473                 return NULL;
11474
11475         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11476         if (!pipe_config) {
11477                 kfree(mode);
11478                 return NULL;
11479         }
11480
11481         /*
11482          * Construct a pipe_config sufficient for getting the clock info
11483          * back out of crtc_clock_get.
11484          *
11485          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11486          * to use a real value here instead.
11487          */
11488         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11489         pipe_config->pixel_multiplier = 1;
11490         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11491         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11492         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11493         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11494
11495         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11496         mode->hdisplay = (htot & 0xffff) + 1;
11497         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11498         mode->hsync_start = (hsync & 0xffff) + 1;
11499         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11500         mode->vdisplay = (vtot & 0xffff) + 1;
11501         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11502         mode->vsync_start = (vsync & 0xffff) + 1;
11503         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11504
11505         drm_mode_set_name(mode);
11506
11507         kfree(pipe_config);
11508
11509         return mode;
11510 }
11511
11512 static void intel_crtc_destroy(struct drm_crtc *crtc)
11513 {
11514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11515         struct drm_device *dev = crtc->dev;
11516         struct intel_flip_work *work;
11517
11518         spin_lock_irq(&dev->event_lock);
11519         work = intel_crtc->flip_work;
11520         intel_crtc->flip_work = NULL;
11521         spin_unlock_irq(&dev->event_lock);
11522
11523         if (work) {
11524                 cancel_work_sync(&work->mmio_work);
11525                 cancel_work_sync(&work->unpin_work);
11526                 kfree(work);
11527         }
11528
11529         drm_crtc_cleanup(crtc);
11530
11531         kfree(intel_crtc);
11532 }
11533
11534 static void intel_unpin_work_fn(struct work_struct *__work)
11535 {
11536         struct intel_flip_work *work =
11537                 container_of(__work, struct intel_flip_work, unpin_work);
11538         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11539         struct drm_device *dev = crtc->base.dev;
11540         struct drm_plane *primary = crtc->base.primary;
11541
11542         if (is_mmio_work(work))
11543                 flush_work(&work->mmio_work);
11544
11545         mutex_lock(&dev->struct_mutex);
11546         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11547         i915_gem_object_put(work->pending_flip_obj);
11548         mutex_unlock(&dev->struct_mutex);
11549
11550         i915_gem_request_put(work->flip_queued_req);
11551
11552         intel_frontbuffer_flip_complete(to_i915(dev),
11553                                         to_intel_plane(primary)->frontbuffer_bit);
11554         intel_fbc_post_update(crtc);
11555         drm_framebuffer_unreference(work->old_fb);
11556
11557         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11558         atomic_dec(&crtc->unpin_work_count);
11559
11560         kfree(work);
11561 }
11562
11563 /* Is 'a' after or equal to 'b'? */
11564 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11565 {
11566         return !((a - b) & 0x80000000);
11567 }
11568
11569 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11570                                    struct intel_flip_work *work)
11571 {
11572         struct drm_device *dev = crtc->base.dev;
11573         struct drm_i915_private *dev_priv = to_i915(dev);
11574
11575         if (abort_flip_on_reset(crtc))
11576                 return true;
11577
11578         /*
11579          * The relevant registers doen't exist on pre-ctg.
11580          * As the flip done interrupt doesn't trigger for mmio
11581          * flips on gmch platforms, a flip count check isn't
11582          * really needed there. But since ctg has the registers,
11583          * include it in the check anyway.
11584          */
11585         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11586                 return true;
11587
11588         /*
11589          * BDW signals flip done immediately if the plane
11590          * is disabled, even if the plane enable is already
11591          * armed to occur at the next vblank :(
11592          */
11593
11594         /*
11595          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11596          * used the same base address. In that case the mmio flip might
11597          * have completed, but the CS hasn't even executed the flip yet.
11598          *
11599          * A flip count check isn't enough as the CS might have updated
11600          * the base address just after start of vblank, but before we
11601          * managed to process the interrupt. This means we'd complete the
11602          * CS flip too soon.
11603          *
11604          * Combining both checks should get us a good enough result. It may
11605          * still happen that the CS flip has been executed, but has not
11606          * yet actually completed. But in case the base address is the same
11607          * anyway, we don't really care.
11608          */
11609         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11610                 crtc->flip_work->gtt_offset &&
11611                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11612                                     crtc->flip_work->flip_count);
11613 }
11614
11615 static bool
11616 __pageflip_finished_mmio(struct intel_crtc *crtc,
11617                                struct intel_flip_work *work)
11618 {
11619         /*
11620          * MMIO work completes when vblank is different from
11621          * flip_queued_vblank.
11622          *
11623          * Reset counter value doesn't matter, this is handled by
11624          * i915_wait_request finishing early, so no need to handle
11625          * reset here.
11626          */
11627         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11628 }
11629
11630
11631 static bool pageflip_finished(struct intel_crtc *crtc,
11632                               struct intel_flip_work *work)
11633 {
11634         if (!atomic_read(&work->pending))
11635                 return false;
11636
11637         smp_rmb();
11638
11639         if (is_mmio_work(work))
11640                 return __pageflip_finished_mmio(crtc, work);
11641         else
11642                 return __pageflip_finished_cs(crtc, work);
11643 }
11644
11645 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11646 {
11647         struct drm_device *dev = &dev_priv->drm;
11648         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11650         struct intel_flip_work *work;
11651         unsigned long flags;
11652
11653         /* Ignore early vblank irqs */
11654         if (!crtc)
11655                 return;
11656
11657         /*
11658          * This is called both by irq handlers and the reset code (to complete
11659          * lost pageflips) so needs the full irqsave spinlocks.
11660          */
11661         spin_lock_irqsave(&dev->event_lock, flags);
11662         work = intel_crtc->flip_work;
11663
11664         if (work != NULL &&
11665             !is_mmio_work(work) &&
11666             pageflip_finished(intel_crtc, work))
11667                 page_flip_completed(intel_crtc);
11668
11669         spin_unlock_irqrestore(&dev->event_lock, flags);
11670 }
11671
11672 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11673 {
11674         struct drm_device *dev = &dev_priv->drm;
11675         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11677         struct intel_flip_work *work;
11678         unsigned long flags;
11679
11680         /* Ignore early vblank irqs */
11681         if (!crtc)
11682                 return;
11683
11684         /*
11685          * This is called both by irq handlers and the reset code (to complete
11686          * lost pageflips) so needs the full irqsave spinlocks.
11687          */
11688         spin_lock_irqsave(&dev->event_lock, flags);
11689         work = intel_crtc->flip_work;
11690
11691         if (work != NULL &&
11692             is_mmio_work(work) &&
11693             pageflip_finished(intel_crtc, work))
11694                 page_flip_completed(intel_crtc);
11695
11696         spin_unlock_irqrestore(&dev->event_lock, flags);
11697 }
11698
11699 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11700                                                struct intel_flip_work *work)
11701 {
11702         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11703
11704         /* Ensure that the work item is consistent when activating it ... */
11705         smp_mb__before_atomic();
11706         atomic_set(&work->pending, 1);
11707 }
11708
11709 static int intel_gen2_queue_flip(struct drm_device *dev,
11710                                  struct drm_crtc *crtc,
11711                                  struct drm_framebuffer *fb,
11712                                  struct drm_i915_gem_object *obj,
11713                                  struct drm_i915_gem_request *req,
11714                                  uint32_t flags)
11715 {
11716         struct intel_ring *ring = req->ring;
11717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11718         u32 flip_mask;
11719         int ret;
11720
11721         ret = intel_ring_begin(req, 6);
11722         if (ret)
11723                 return ret;
11724
11725         /* Can't queue multiple flips, so wait for the previous
11726          * one to finish before executing the next.
11727          */
11728         if (intel_crtc->plane)
11729                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11730         else
11731                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11732         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11733         intel_ring_emit(ring, MI_NOOP);
11734         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11735                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11736         intel_ring_emit(ring, fb->pitches[0]);
11737         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11738         intel_ring_emit(ring, 0); /* aux display base address, unused */
11739
11740         return 0;
11741 }
11742
11743 static int intel_gen3_queue_flip(struct drm_device *dev,
11744                                  struct drm_crtc *crtc,
11745                                  struct drm_framebuffer *fb,
11746                                  struct drm_i915_gem_object *obj,
11747                                  struct drm_i915_gem_request *req,
11748                                  uint32_t flags)
11749 {
11750         struct intel_ring *ring = req->ring;
11751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11752         u32 flip_mask;
11753         int ret;
11754
11755         ret = intel_ring_begin(req, 6);
11756         if (ret)
11757                 return ret;
11758
11759         if (intel_crtc->plane)
11760                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11761         else
11762                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11763         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11764         intel_ring_emit(ring, MI_NOOP);
11765         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11766                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11767         intel_ring_emit(ring, fb->pitches[0]);
11768         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11769         intel_ring_emit(ring, MI_NOOP);
11770
11771         return 0;
11772 }
11773
11774 static int intel_gen4_queue_flip(struct drm_device *dev,
11775                                  struct drm_crtc *crtc,
11776                                  struct drm_framebuffer *fb,
11777                                  struct drm_i915_gem_object *obj,
11778                                  struct drm_i915_gem_request *req,
11779                                  uint32_t flags)
11780 {
11781         struct intel_ring *ring = req->ring;
11782         struct drm_i915_private *dev_priv = to_i915(dev);
11783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11784         uint32_t pf, pipesrc;
11785         int ret;
11786
11787         ret = intel_ring_begin(req, 4);
11788         if (ret)
11789                 return ret;
11790
11791         /* i965+ uses the linear or tiled offsets from the
11792          * Display Registers (which do not change across a page-flip)
11793          * so we need only reprogram the base address.
11794          */
11795         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11796                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11797         intel_ring_emit(ring, fb->pitches[0]);
11798         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11799                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11800
11801         /* XXX Enabling the panel-fitter across page-flip is so far
11802          * untested on non-native modes, so ignore it for now.
11803          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11804          */
11805         pf = 0;
11806         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11807         intel_ring_emit(ring, pf | pipesrc);
11808
11809         return 0;
11810 }
11811
11812 static int intel_gen6_queue_flip(struct drm_device *dev,
11813                                  struct drm_crtc *crtc,
11814                                  struct drm_framebuffer *fb,
11815                                  struct drm_i915_gem_object *obj,
11816                                  struct drm_i915_gem_request *req,
11817                                  uint32_t flags)
11818 {
11819         struct intel_ring *ring = req->ring;
11820         struct drm_i915_private *dev_priv = to_i915(dev);
11821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11822         uint32_t pf, pipesrc;
11823         int ret;
11824
11825         ret = intel_ring_begin(req, 4);
11826         if (ret)
11827                 return ret;
11828
11829         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11830                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11831         intel_ring_emit(ring, fb->pitches[0] |
11832                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11833         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11834
11835         /* Contrary to the suggestions in the documentation,
11836          * "Enable Panel Fitter" does not seem to be required when page
11837          * flipping with a non-native mode, and worse causes a normal
11838          * modeset to fail.
11839          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11840          */
11841         pf = 0;
11842         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11843         intel_ring_emit(ring, pf | pipesrc);
11844
11845         return 0;
11846 }
11847
11848 static int intel_gen7_queue_flip(struct drm_device *dev,
11849                                  struct drm_crtc *crtc,
11850                                  struct drm_framebuffer *fb,
11851                                  struct drm_i915_gem_object *obj,
11852                                  struct drm_i915_gem_request *req,
11853                                  uint32_t flags)
11854 {
11855         struct intel_ring *ring = req->ring;
11856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11857         uint32_t plane_bit = 0;
11858         int len, ret;
11859
11860         switch (intel_crtc->plane) {
11861         case PLANE_A:
11862                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11863                 break;
11864         case PLANE_B:
11865                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11866                 break;
11867         case PLANE_C:
11868                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11869                 break;
11870         default:
11871                 WARN_ONCE(1, "unknown plane in flip command\n");
11872                 return -ENODEV;
11873         }
11874
11875         len = 4;
11876         if (req->engine->id == RCS) {
11877                 len += 6;
11878                 /*
11879                  * On Gen 8, SRM is now taking an extra dword to accommodate
11880                  * 48bits addresses, and we need a NOOP for the batch size to
11881                  * stay even.
11882                  */
11883                 if (IS_GEN8(dev))
11884                         len += 2;
11885         }
11886
11887         /*
11888          * BSpec MI_DISPLAY_FLIP for IVB:
11889          * "The full packet must be contained within the same cache line."
11890          *
11891          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11892          * cacheline, if we ever start emitting more commands before
11893          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11894          * then do the cacheline alignment, and finally emit the
11895          * MI_DISPLAY_FLIP.
11896          */
11897         ret = intel_ring_cacheline_align(req);
11898         if (ret)
11899                 return ret;
11900
11901         ret = intel_ring_begin(req, len);
11902         if (ret)
11903                 return ret;
11904
11905         /* Unmask the flip-done completion message. Note that the bspec says that
11906          * we should do this for both the BCS and RCS, and that we must not unmask
11907          * more than one flip event at any time (or ensure that one flip message
11908          * can be sent by waiting for flip-done prior to queueing new flips).
11909          * Experimentation says that BCS works despite DERRMR masking all
11910          * flip-done completion events and that unmasking all planes at once
11911          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11912          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11913          */
11914         if (req->engine->id == RCS) {
11915                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11916                 intel_ring_emit_reg(ring, DERRMR);
11917                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11918                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11919                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11920                 if (IS_GEN8(dev))
11921                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11922                                               MI_SRM_LRM_GLOBAL_GTT);
11923                 else
11924                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11925                                               MI_SRM_LRM_GLOBAL_GTT);
11926                 intel_ring_emit_reg(ring, DERRMR);
11927                 intel_ring_emit(ring,
11928                                 i915_ggtt_offset(req->engine->scratch) + 256);
11929                 if (IS_GEN8(dev)) {
11930                         intel_ring_emit(ring, 0);
11931                         intel_ring_emit(ring, MI_NOOP);
11932                 }
11933         }
11934
11935         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11936         intel_ring_emit(ring, fb->pitches[0] |
11937                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11938         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11939         intel_ring_emit(ring, (MI_NOOP));
11940
11941         return 0;
11942 }
11943
11944 static bool use_mmio_flip(struct intel_engine_cs *engine,
11945                           struct drm_i915_gem_object *obj)
11946 {
11947         struct reservation_object *resv;
11948
11949         /*
11950          * This is not being used for older platforms, because
11951          * non-availability of flip done interrupt forces us to use
11952          * CS flips. Older platforms derive flip done using some clever
11953          * tricks involving the flip_pending status bits and vblank irqs.
11954          * So using MMIO flips there would disrupt this mechanism.
11955          */
11956
11957         if (engine == NULL)
11958                 return true;
11959
11960         if (INTEL_GEN(engine->i915) < 5)
11961                 return false;
11962
11963         if (i915.use_mmio_flip < 0)
11964                 return false;
11965         else if (i915.use_mmio_flip > 0)
11966                 return true;
11967         else if (i915.enable_execlists)
11968                 return true;
11969
11970         resv = i915_gem_object_get_dmabuf_resv(obj);
11971         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11972                 return true;
11973
11974         return engine != i915_gem_active_get_engine(&obj->last_write,
11975                                                     &obj->base.dev->struct_mutex);
11976 }
11977
11978 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11979                              unsigned int rotation,
11980                              struct intel_flip_work *work)
11981 {
11982         struct drm_device *dev = intel_crtc->base.dev;
11983         struct drm_i915_private *dev_priv = to_i915(dev);
11984         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11985         const enum pipe pipe = intel_crtc->pipe;
11986         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11987
11988         ctl = I915_READ(PLANE_CTL(pipe, 0));
11989         ctl &= ~PLANE_CTL_TILED_MASK;
11990         switch (fb->modifier[0]) {
11991         case DRM_FORMAT_MOD_NONE:
11992                 break;
11993         case I915_FORMAT_MOD_X_TILED:
11994                 ctl |= PLANE_CTL_TILED_X;
11995                 break;
11996         case I915_FORMAT_MOD_Y_TILED:
11997                 ctl |= PLANE_CTL_TILED_Y;
11998                 break;
11999         case I915_FORMAT_MOD_Yf_TILED:
12000                 ctl |= PLANE_CTL_TILED_YF;
12001                 break;
12002         default:
12003                 MISSING_CASE(fb->modifier[0]);
12004         }
12005
12006         /*
12007          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12008          * PLANE_SURF updates, the update is then guaranteed to be atomic.
12009          */
12010         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12011         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12012
12013         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12014         POSTING_READ(PLANE_SURF(pipe, 0));
12015 }
12016
12017 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12018                              struct intel_flip_work *work)
12019 {
12020         struct drm_device *dev = intel_crtc->base.dev;
12021         struct drm_i915_private *dev_priv = to_i915(dev);
12022         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12023         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12024         u32 dspcntr;
12025
12026         dspcntr = I915_READ(reg);
12027
12028         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12029                 dspcntr |= DISPPLANE_TILED;
12030         else
12031                 dspcntr &= ~DISPPLANE_TILED;
12032
12033         I915_WRITE(reg, dspcntr);
12034
12035         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12036         POSTING_READ(DSPSURF(intel_crtc->plane));
12037 }
12038
12039 static void intel_mmio_flip_work_func(struct work_struct *w)
12040 {
12041         struct intel_flip_work *work =
12042                 container_of(w, struct intel_flip_work, mmio_work);
12043         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12044         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12045         struct intel_framebuffer *intel_fb =
12046                 to_intel_framebuffer(crtc->base.primary->fb);
12047         struct drm_i915_gem_object *obj = intel_fb->obj;
12048         struct reservation_object *resv;
12049
12050         if (work->flip_queued_req)
12051                 WARN_ON(i915_wait_request(work->flip_queued_req,
12052                                           0, NULL, NO_WAITBOOST));
12053
12054         /* For framebuffer backed by dmabuf, wait for fence */
12055         resv = i915_gem_object_get_dmabuf_resv(obj);
12056         if (resv)
12057                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12058                                                             MAX_SCHEDULE_TIMEOUT) < 0);
12059
12060         intel_pipe_update_start(crtc);
12061
12062         if (INTEL_GEN(dev_priv) >= 9)
12063                 skl_do_mmio_flip(crtc, work->rotation, work);
12064         else
12065                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12066                 ilk_do_mmio_flip(crtc, work);
12067
12068         intel_pipe_update_end(crtc, work);
12069 }
12070
12071 static int intel_default_queue_flip(struct drm_device *dev,
12072                                     struct drm_crtc *crtc,
12073                                     struct drm_framebuffer *fb,
12074                                     struct drm_i915_gem_object *obj,
12075                                     struct drm_i915_gem_request *req,
12076                                     uint32_t flags)
12077 {
12078         return -ENODEV;
12079 }
12080
12081 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12082                                       struct intel_crtc *intel_crtc,
12083                                       struct intel_flip_work *work)
12084 {
12085         u32 addr, vblank;
12086
12087         if (!atomic_read(&work->pending))
12088                 return false;
12089
12090         smp_rmb();
12091
12092         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12093         if (work->flip_ready_vblank == 0) {
12094                 if (work->flip_queued_req &&
12095                     !i915_gem_request_completed(work->flip_queued_req))
12096                         return false;
12097
12098                 work->flip_ready_vblank = vblank;
12099         }
12100
12101         if (vblank - work->flip_ready_vblank < 3)
12102                 return false;
12103
12104         /* Potential stall - if we see that the flip has happened,
12105          * assume a missed interrupt. */
12106         if (INTEL_GEN(dev_priv) >= 4)
12107                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12108         else
12109                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12110
12111         /* There is a potential issue here with a false positive after a flip
12112          * to the same address. We could address this by checking for a
12113          * non-incrementing frame counter.
12114          */
12115         return addr == work->gtt_offset;
12116 }
12117
12118 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12119 {
12120         struct drm_device *dev = &dev_priv->drm;
12121         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12123         struct intel_flip_work *work;
12124
12125         WARN_ON(!in_interrupt());
12126
12127         if (crtc == NULL)
12128                 return;
12129
12130         spin_lock(&dev->event_lock);
12131         work = intel_crtc->flip_work;
12132
12133         if (work != NULL && !is_mmio_work(work) &&
12134             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12135                 WARN_ONCE(1,
12136                           "Kicking stuck page flip: queued at %d, now %d\n",
12137                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12138                 page_flip_completed(intel_crtc);
12139                 work = NULL;
12140         }
12141
12142         if (work != NULL && !is_mmio_work(work) &&
12143             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12144                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12145         spin_unlock(&dev->event_lock);
12146 }
12147
12148 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12149                                 struct drm_framebuffer *fb,
12150                                 struct drm_pending_vblank_event *event,
12151                                 uint32_t page_flip_flags)
12152 {
12153         struct drm_device *dev = crtc->dev;
12154         struct drm_i915_private *dev_priv = to_i915(dev);
12155         struct drm_framebuffer *old_fb = crtc->primary->fb;
12156         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12158         struct drm_plane *primary = crtc->primary;
12159         enum pipe pipe = intel_crtc->pipe;
12160         struct intel_flip_work *work;
12161         struct intel_engine_cs *engine;
12162         bool mmio_flip;
12163         struct drm_i915_gem_request *request;
12164         struct i915_vma *vma;
12165         int ret;
12166
12167         /*
12168          * drm_mode_page_flip_ioctl() should already catch this, but double
12169          * check to be safe.  In the future we may enable pageflipping from
12170          * a disabled primary plane.
12171          */
12172         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12173                 return -EBUSY;
12174
12175         /* Can't change pixel format via MI display flips. */
12176         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12177                 return -EINVAL;
12178
12179         /*
12180          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12181          * Note that pitch changes could also affect these register.
12182          */
12183         if (INTEL_INFO(dev)->gen > 3 &&
12184             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12185              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12186                 return -EINVAL;
12187
12188         if (i915_terminally_wedged(&dev_priv->gpu_error))
12189                 goto out_hang;
12190
12191         work = kzalloc(sizeof(*work), GFP_KERNEL);
12192         if (work == NULL)
12193                 return -ENOMEM;
12194
12195         work->event = event;
12196         work->crtc = crtc;
12197         work->old_fb = old_fb;
12198         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12199
12200         ret = drm_crtc_vblank_get(crtc);
12201         if (ret)
12202                 goto free_work;
12203
12204         /* We borrow the event spin lock for protecting flip_work */
12205         spin_lock_irq(&dev->event_lock);
12206         if (intel_crtc->flip_work) {
12207                 /* Before declaring the flip queue wedged, check if
12208                  * the hardware completed the operation behind our backs.
12209                  */
12210                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12211                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12212                         page_flip_completed(intel_crtc);
12213                 } else {
12214                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12215                         spin_unlock_irq(&dev->event_lock);
12216
12217                         drm_crtc_vblank_put(crtc);
12218                         kfree(work);
12219                         return -EBUSY;
12220                 }
12221         }
12222         intel_crtc->flip_work = work;
12223         spin_unlock_irq(&dev->event_lock);
12224
12225         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12226                 flush_workqueue(dev_priv->wq);
12227
12228         /* Reference the objects for the scheduled work. */
12229         drm_framebuffer_reference(work->old_fb);
12230
12231         crtc->primary->fb = fb;
12232         update_state_fb(crtc->primary);
12233
12234         work->pending_flip_obj = i915_gem_object_get(obj);
12235
12236         ret = i915_mutex_lock_interruptible(dev);
12237         if (ret)
12238                 goto cleanup;
12239
12240         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12241         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12242                 ret = -EIO;
12243                 goto cleanup;
12244         }
12245
12246         atomic_inc(&intel_crtc->unpin_work_count);
12247
12248         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12249                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12250
12251         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12252                 engine = dev_priv->engine[BCS];
12253                 if (fb->modifier[0] != old_fb->modifier[0])
12254                         /* vlv: DISPLAY_FLIP fails to change tiling */
12255                         engine = NULL;
12256         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12257                 engine = dev_priv->engine[BCS];
12258         } else if (INTEL_INFO(dev)->gen >= 7) {
12259                 engine = i915_gem_active_get_engine(&obj->last_write,
12260                                                     &obj->base.dev->struct_mutex);
12261                 if (engine == NULL || engine->id != RCS)
12262                         engine = dev_priv->engine[BCS];
12263         } else {
12264                 engine = dev_priv->engine[RCS];
12265         }
12266
12267         mmio_flip = use_mmio_flip(engine, obj);
12268
12269         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12270         if (IS_ERR(vma)) {
12271                 ret = PTR_ERR(vma);
12272                 goto cleanup_pending;
12273         }
12274
12275         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12276         work->gtt_offset += intel_crtc->dspaddr_offset;
12277         work->rotation = crtc->primary->state->rotation;
12278
12279         /*
12280          * There's the potential that the next frame will not be compatible with
12281          * FBC, so we want to call pre_update() before the actual page flip.
12282          * The problem is that pre_update() caches some information about the fb
12283          * object, so we want to do this only after the object is pinned. Let's
12284          * be on the safe side and do this immediately before scheduling the
12285          * flip.
12286          */
12287         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12288                              to_intel_plane_state(primary->state));
12289
12290         if (mmio_flip) {
12291                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12292
12293                 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12294                                                             &obj->base.dev->struct_mutex);
12295                 queue_work(system_unbound_wq, &work->mmio_work);
12296         } else {
12297                 request = i915_gem_request_alloc(engine, engine->last_context);
12298                 if (IS_ERR(request)) {
12299                         ret = PTR_ERR(request);
12300                         goto cleanup_unpin;
12301                 }
12302
12303                 ret = i915_gem_request_await_object(request, obj, false);
12304                 if (ret)
12305                         goto cleanup_request;
12306
12307                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12308                                                    page_flip_flags);
12309                 if (ret)
12310                         goto cleanup_request;
12311
12312                 intel_mark_page_flip_active(intel_crtc, work);
12313
12314                 work->flip_queued_req = i915_gem_request_get(request);
12315                 i915_add_request_no_flush(request);
12316         }
12317
12318         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12319                           to_intel_plane(primary)->frontbuffer_bit);
12320         mutex_unlock(&dev->struct_mutex);
12321
12322         intel_frontbuffer_flip_prepare(to_i915(dev),
12323                                        to_intel_plane(primary)->frontbuffer_bit);
12324
12325         trace_i915_flip_request(intel_crtc->plane, obj);
12326
12327         return 0;
12328
12329 cleanup_request:
12330         i915_add_request_no_flush(request);
12331 cleanup_unpin:
12332         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12333 cleanup_pending:
12334         atomic_dec(&intel_crtc->unpin_work_count);
12335         mutex_unlock(&dev->struct_mutex);
12336 cleanup:
12337         crtc->primary->fb = old_fb;
12338         update_state_fb(crtc->primary);
12339
12340         i915_gem_object_put_unlocked(obj);
12341         drm_framebuffer_unreference(work->old_fb);
12342
12343         spin_lock_irq(&dev->event_lock);
12344         intel_crtc->flip_work = NULL;
12345         spin_unlock_irq(&dev->event_lock);
12346
12347         drm_crtc_vblank_put(crtc);
12348 free_work:
12349         kfree(work);
12350
12351         if (ret == -EIO) {
12352                 struct drm_atomic_state *state;
12353                 struct drm_plane_state *plane_state;
12354
12355 out_hang:
12356                 state = drm_atomic_state_alloc(dev);
12357                 if (!state)
12358                         return -ENOMEM;
12359                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12360
12361 retry:
12362                 plane_state = drm_atomic_get_plane_state(state, primary);
12363                 ret = PTR_ERR_OR_ZERO(plane_state);
12364                 if (!ret) {
12365                         drm_atomic_set_fb_for_plane(plane_state, fb);
12366
12367                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12368                         if (!ret)
12369                                 ret = drm_atomic_commit(state);
12370                 }
12371
12372                 if (ret == -EDEADLK) {
12373                         drm_modeset_backoff(state->acquire_ctx);
12374                         drm_atomic_state_clear(state);
12375                         goto retry;
12376                 }
12377
12378                 if (ret)
12379                         drm_atomic_state_free(state);
12380
12381                 if (ret == 0 && event) {
12382                         spin_lock_irq(&dev->event_lock);
12383                         drm_crtc_send_vblank_event(crtc, event);
12384                         spin_unlock_irq(&dev->event_lock);
12385                 }
12386         }
12387         return ret;
12388 }
12389
12390
12391 /**
12392  * intel_wm_need_update - Check whether watermarks need updating
12393  * @plane: drm plane
12394  * @state: new plane state
12395  *
12396  * Check current plane state versus the new one to determine whether
12397  * watermarks need to be recalculated.
12398  *
12399  * Returns true or false.
12400  */
12401 static bool intel_wm_need_update(struct drm_plane *plane,
12402                                  struct drm_plane_state *state)
12403 {
12404         struct intel_plane_state *new = to_intel_plane_state(state);
12405         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12406
12407         /* Update watermarks on tiling or size changes. */
12408         if (new->base.visible != cur->base.visible)
12409                 return true;
12410
12411         if (!cur->base.fb || !new->base.fb)
12412                 return false;
12413
12414         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12415             cur->base.rotation != new->base.rotation ||
12416             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12417             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12418             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12419             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12420                 return true;
12421
12422         return false;
12423 }
12424
12425 static bool needs_scaling(struct intel_plane_state *state)
12426 {
12427         int src_w = drm_rect_width(&state->base.src) >> 16;
12428         int src_h = drm_rect_height(&state->base.src) >> 16;
12429         int dst_w = drm_rect_width(&state->base.dst);
12430         int dst_h = drm_rect_height(&state->base.dst);
12431
12432         return (src_w != dst_w || src_h != dst_h);
12433 }
12434
12435 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12436                                     struct drm_plane_state *plane_state)
12437 {
12438         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12439         struct drm_crtc *crtc = crtc_state->crtc;
12440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12441         struct drm_plane *plane = plane_state->plane;
12442         struct drm_device *dev = crtc->dev;
12443         struct drm_i915_private *dev_priv = to_i915(dev);
12444         struct intel_plane_state *old_plane_state =
12445                 to_intel_plane_state(plane->state);
12446         bool mode_changed = needs_modeset(crtc_state);
12447         bool was_crtc_enabled = crtc->state->active;
12448         bool is_crtc_enabled = crtc_state->active;
12449         bool turn_off, turn_on, visible, was_visible;
12450         struct drm_framebuffer *fb = plane_state->fb;
12451         int ret;
12452
12453         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12454                 ret = skl_update_scaler_plane(
12455                         to_intel_crtc_state(crtc_state),
12456                         to_intel_plane_state(plane_state));
12457                 if (ret)
12458                         return ret;
12459         }
12460
12461         was_visible = old_plane_state->base.visible;
12462         visible = to_intel_plane_state(plane_state)->base.visible;
12463
12464         if (!was_crtc_enabled && WARN_ON(was_visible))
12465                 was_visible = false;
12466
12467         /*
12468          * Visibility is calculated as if the crtc was on, but
12469          * after scaler setup everything depends on it being off
12470          * when the crtc isn't active.
12471          *
12472          * FIXME this is wrong for watermarks. Watermarks should also
12473          * be computed as if the pipe would be active. Perhaps move
12474          * per-plane wm computation to the .check_plane() hook, and
12475          * only combine the results from all planes in the current place?
12476          */
12477         if (!is_crtc_enabled)
12478                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12479
12480         if (!was_visible && !visible)
12481                 return 0;
12482
12483         if (fb != old_plane_state->base.fb)
12484                 pipe_config->fb_changed = true;
12485
12486         turn_off = was_visible && (!visible || mode_changed);
12487         turn_on = visible && (!was_visible || mode_changed);
12488
12489         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12490                          intel_crtc->base.base.id,
12491                          intel_crtc->base.name,
12492                          plane->base.id, plane->name,
12493                          fb ? fb->base.id : -1);
12494
12495         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12496                          plane->base.id, plane->name,
12497                          was_visible, visible,
12498                          turn_off, turn_on, mode_changed);
12499
12500         if (turn_on) {
12501                 pipe_config->update_wm_pre = true;
12502
12503                 /* must disable cxsr around plane enable/disable */
12504                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12505                         pipe_config->disable_cxsr = true;
12506         } else if (turn_off) {
12507                 pipe_config->update_wm_post = true;
12508
12509                 /* must disable cxsr around plane enable/disable */
12510                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12511                         pipe_config->disable_cxsr = true;
12512         } else if (intel_wm_need_update(plane, plane_state)) {
12513                 /* FIXME bollocks */
12514                 pipe_config->update_wm_pre = true;
12515                 pipe_config->update_wm_post = true;
12516         }
12517
12518         /* Pre-gen9 platforms need two-step watermark updates */
12519         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12520             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12521                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12522
12523         if (visible || was_visible)
12524                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12525
12526         /*
12527          * WaCxSRDisabledForSpriteScaling:ivb
12528          *
12529          * cstate->update_wm was already set above, so this flag will
12530          * take effect when we commit and program watermarks.
12531          */
12532         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12533             needs_scaling(to_intel_plane_state(plane_state)) &&
12534             !needs_scaling(old_plane_state))
12535                 pipe_config->disable_lp_wm = true;
12536
12537         return 0;
12538 }
12539
12540 static bool encoders_cloneable(const struct intel_encoder *a,
12541                                const struct intel_encoder *b)
12542 {
12543         /* masks could be asymmetric, so check both ways */
12544         return a == b || (a->cloneable & (1 << b->type) &&
12545                           b->cloneable & (1 << a->type));
12546 }
12547
12548 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12549                                          struct intel_crtc *crtc,
12550                                          struct intel_encoder *encoder)
12551 {
12552         struct intel_encoder *source_encoder;
12553         struct drm_connector *connector;
12554         struct drm_connector_state *connector_state;
12555         int i;
12556
12557         for_each_connector_in_state(state, connector, connector_state, i) {
12558                 if (connector_state->crtc != &crtc->base)
12559                         continue;
12560
12561                 source_encoder =
12562                         to_intel_encoder(connector_state->best_encoder);
12563                 if (!encoders_cloneable(encoder, source_encoder))
12564                         return false;
12565         }
12566
12567         return true;
12568 }
12569
12570 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12571                                    struct drm_crtc_state *crtc_state)
12572 {
12573         struct drm_device *dev = crtc->dev;
12574         struct drm_i915_private *dev_priv = to_i915(dev);
12575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12576         struct intel_crtc_state *pipe_config =
12577                 to_intel_crtc_state(crtc_state);
12578         struct drm_atomic_state *state = crtc_state->state;
12579         int ret;
12580         bool mode_changed = needs_modeset(crtc_state);
12581
12582         if (mode_changed && !crtc_state->active)
12583                 pipe_config->update_wm_post = true;
12584
12585         if (mode_changed && crtc_state->enable &&
12586             dev_priv->display.crtc_compute_clock &&
12587             !WARN_ON(pipe_config->shared_dpll)) {
12588                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12589                                                            pipe_config);
12590                 if (ret)
12591                         return ret;
12592         }
12593
12594         if (crtc_state->color_mgmt_changed) {
12595                 ret = intel_color_check(crtc, crtc_state);
12596                 if (ret)
12597                         return ret;
12598
12599                 /*
12600                  * Changing color management on Intel hardware is
12601                  * handled as part of planes update.
12602                  */
12603                 crtc_state->planes_changed = true;
12604         }
12605
12606         ret = 0;
12607         if (dev_priv->display.compute_pipe_wm) {
12608                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12609                 if (ret) {
12610                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12611                         return ret;
12612                 }
12613         }
12614
12615         if (dev_priv->display.compute_intermediate_wm &&
12616             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12617                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12618                         return 0;
12619
12620                 /*
12621                  * Calculate 'intermediate' watermarks that satisfy both the
12622                  * old state and the new state.  We can program these
12623                  * immediately.
12624                  */
12625                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12626                                                                 intel_crtc,
12627                                                                 pipe_config);
12628                 if (ret) {
12629                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12630                         return ret;
12631                 }
12632         } else if (dev_priv->display.compute_intermediate_wm) {
12633                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12634                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12635         }
12636
12637         if (INTEL_INFO(dev)->gen >= 9) {
12638                 if (mode_changed)
12639                         ret = skl_update_scaler_crtc(pipe_config);
12640
12641                 if (!ret)
12642                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12643                                                          pipe_config);
12644         }
12645
12646         return ret;
12647 }
12648
12649 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12650         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12651         .atomic_begin = intel_begin_crtc_commit,
12652         .atomic_flush = intel_finish_crtc_commit,
12653         .atomic_check = intel_crtc_atomic_check,
12654 };
12655
12656 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12657 {
12658         struct intel_connector *connector;
12659
12660         for_each_intel_connector(dev, connector) {
12661                 if (connector->base.state->crtc)
12662                         drm_connector_unreference(&connector->base);
12663
12664                 if (connector->base.encoder) {
12665                         connector->base.state->best_encoder =
12666                                 connector->base.encoder;
12667                         connector->base.state->crtc =
12668                                 connector->base.encoder->crtc;
12669
12670                         drm_connector_reference(&connector->base);
12671                 } else {
12672                         connector->base.state->best_encoder = NULL;
12673                         connector->base.state->crtc = NULL;
12674                 }
12675         }
12676 }
12677
12678 static void
12679 connected_sink_compute_bpp(struct intel_connector *connector,
12680                            struct intel_crtc_state *pipe_config)
12681 {
12682         const struct drm_display_info *info = &connector->base.display_info;
12683         int bpp = pipe_config->pipe_bpp;
12684
12685         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12686                       connector->base.base.id,
12687                       connector->base.name);
12688
12689         /* Don't use an invalid EDID bpc value */
12690         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12691                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12692                               bpp, info->bpc * 3);
12693                 pipe_config->pipe_bpp = info->bpc * 3;
12694         }
12695
12696         /* Clamp bpp to 8 on screens without EDID 1.4 */
12697         if (info->bpc == 0 && bpp > 24) {
12698                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12699                               bpp);
12700                 pipe_config->pipe_bpp = 24;
12701         }
12702 }
12703
12704 static int
12705 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12706                           struct intel_crtc_state *pipe_config)
12707 {
12708         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12709         struct drm_atomic_state *state;
12710         struct drm_connector *connector;
12711         struct drm_connector_state *connector_state;
12712         int bpp, i;
12713
12714         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12715             IS_CHERRYVIEW(dev_priv)))
12716                 bpp = 10*3;
12717         else if (INTEL_GEN(dev_priv) >= 5)
12718                 bpp = 12*3;
12719         else
12720                 bpp = 8*3;
12721
12722
12723         pipe_config->pipe_bpp = bpp;
12724
12725         state = pipe_config->base.state;
12726
12727         /* Clamp display bpp to EDID value */
12728         for_each_connector_in_state(state, connector, connector_state, i) {
12729                 if (connector_state->crtc != &crtc->base)
12730                         continue;
12731
12732                 connected_sink_compute_bpp(to_intel_connector(connector),
12733                                            pipe_config);
12734         }
12735
12736         return bpp;
12737 }
12738
12739 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12740 {
12741         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12742                         "type: 0x%x flags: 0x%x\n",
12743                 mode->crtc_clock,
12744                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12745                 mode->crtc_hsync_end, mode->crtc_htotal,
12746                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12747                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12748 }
12749
12750 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12751                                    struct intel_crtc_state *pipe_config,
12752                                    const char *context)
12753 {
12754         struct drm_device *dev = crtc->base.dev;
12755         struct drm_i915_private *dev_priv = to_i915(dev);
12756         struct drm_plane *plane;
12757         struct intel_plane *intel_plane;
12758         struct intel_plane_state *state;
12759         struct drm_framebuffer *fb;
12760
12761         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12762                       crtc->base.base.id, crtc->base.name,
12763                       context, pipe_config, pipe_name(crtc->pipe));
12764
12765         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12766         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12767                       pipe_config->pipe_bpp, pipe_config->dither);
12768         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12769                       pipe_config->has_pch_encoder,
12770                       pipe_config->fdi_lanes,
12771                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12772                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12773                       pipe_config->fdi_m_n.tu);
12774         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12775                       intel_crtc_has_dp_encoder(pipe_config),
12776                       pipe_config->lane_count,
12777                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12778                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12779                       pipe_config->dp_m_n.tu);
12780
12781         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12782                       intel_crtc_has_dp_encoder(pipe_config),
12783                       pipe_config->lane_count,
12784                       pipe_config->dp_m2_n2.gmch_m,
12785                       pipe_config->dp_m2_n2.gmch_n,
12786                       pipe_config->dp_m2_n2.link_m,
12787                       pipe_config->dp_m2_n2.link_n,
12788                       pipe_config->dp_m2_n2.tu);
12789
12790         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12791                       pipe_config->has_audio,
12792                       pipe_config->has_infoframe);
12793
12794         DRM_DEBUG_KMS("requested mode:\n");
12795         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12796         DRM_DEBUG_KMS("adjusted mode:\n");
12797         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12798         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12799         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12800         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12801                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12802         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12803                       crtc->num_scalers,
12804                       pipe_config->scaler_state.scaler_users,
12805                       pipe_config->scaler_state.scaler_id);
12806         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12807                       pipe_config->gmch_pfit.control,
12808                       pipe_config->gmch_pfit.pgm_ratios,
12809                       pipe_config->gmch_pfit.lvds_border_bits);
12810         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12811                       pipe_config->pch_pfit.pos,
12812                       pipe_config->pch_pfit.size,
12813                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12814         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12815         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12816
12817         if (IS_BROXTON(dev_priv)) {
12818                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12819                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12820                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12821                               pipe_config->dpll_hw_state.ebb0,
12822                               pipe_config->dpll_hw_state.ebb4,
12823                               pipe_config->dpll_hw_state.pll0,
12824                               pipe_config->dpll_hw_state.pll1,
12825                               pipe_config->dpll_hw_state.pll2,
12826                               pipe_config->dpll_hw_state.pll3,
12827                               pipe_config->dpll_hw_state.pll6,
12828                               pipe_config->dpll_hw_state.pll8,
12829                               pipe_config->dpll_hw_state.pll9,
12830                               pipe_config->dpll_hw_state.pll10,
12831                               pipe_config->dpll_hw_state.pcsdw12);
12832         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12833                 DRM_DEBUG_KMS("dpll_hw_state: "
12834                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12835                               pipe_config->dpll_hw_state.ctrl1,
12836                               pipe_config->dpll_hw_state.cfgcr1,
12837                               pipe_config->dpll_hw_state.cfgcr2);
12838         } else if (HAS_DDI(dev_priv)) {
12839                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12840                               pipe_config->dpll_hw_state.wrpll,
12841                               pipe_config->dpll_hw_state.spll);
12842         } else {
12843                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12844                               "fp0: 0x%x, fp1: 0x%x\n",
12845                               pipe_config->dpll_hw_state.dpll,
12846                               pipe_config->dpll_hw_state.dpll_md,
12847                               pipe_config->dpll_hw_state.fp0,
12848                               pipe_config->dpll_hw_state.fp1);
12849         }
12850
12851         DRM_DEBUG_KMS("planes on this crtc\n");
12852         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12853                 char *format_name;
12854                 intel_plane = to_intel_plane(plane);
12855                 if (intel_plane->pipe != crtc->pipe)
12856                         continue;
12857
12858                 state = to_intel_plane_state(plane->state);
12859                 fb = state->base.fb;
12860                 if (!fb) {
12861                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12862                                       plane->base.id, plane->name, state->scaler_id);
12863                         continue;
12864                 }
12865
12866                 format_name = drm_get_format_name(fb->pixel_format);
12867
12868                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12869                               plane->base.id, plane->name);
12870                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12871                               fb->base.id, fb->width, fb->height, format_name);
12872                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12873                               state->scaler_id,
12874                               state->base.src.x1 >> 16,
12875                               state->base.src.y1 >> 16,
12876                               drm_rect_width(&state->base.src) >> 16,
12877                               drm_rect_height(&state->base.src) >> 16,
12878                               state->base.dst.x1, state->base.dst.y1,
12879                               drm_rect_width(&state->base.dst),
12880                               drm_rect_height(&state->base.dst));
12881
12882                 kfree(format_name);
12883         }
12884 }
12885
12886 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12887 {
12888         struct drm_device *dev = state->dev;
12889         struct drm_connector *connector;
12890         unsigned int used_ports = 0;
12891         unsigned int used_mst_ports = 0;
12892
12893         /*
12894          * Walk the connector list instead of the encoder
12895          * list to detect the problem on ddi platforms
12896          * where there's just one encoder per digital port.
12897          */
12898         drm_for_each_connector(connector, dev) {
12899                 struct drm_connector_state *connector_state;
12900                 struct intel_encoder *encoder;
12901
12902                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12903                 if (!connector_state)
12904                         connector_state = connector->state;
12905
12906                 if (!connector_state->best_encoder)
12907                         continue;
12908
12909                 encoder = to_intel_encoder(connector_state->best_encoder);
12910
12911                 WARN_ON(!connector_state->crtc);
12912
12913                 switch (encoder->type) {
12914                         unsigned int port_mask;
12915                 case INTEL_OUTPUT_UNKNOWN:
12916                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12917                                 break;
12918                 case INTEL_OUTPUT_DP:
12919                 case INTEL_OUTPUT_HDMI:
12920                 case INTEL_OUTPUT_EDP:
12921                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12922
12923                         /* the same port mustn't appear more than once */
12924                         if (used_ports & port_mask)
12925                                 return false;
12926
12927                         used_ports |= port_mask;
12928                         break;
12929                 case INTEL_OUTPUT_DP_MST:
12930                         used_mst_ports |=
12931                                 1 << enc_to_mst(&encoder->base)->primary->port;
12932                         break;
12933                 default:
12934                         break;
12935                 }
12936         }
12937
12938         /* can't mix MST and SST/HDMI on the same port */
12939         if (used_ports & used_mst_ports)
12940                 return false;
12941
12942         return true;
12943 }
12944
12945 static void
12946 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12947 {
12948         struct drm_crtc_state tmp_state;
12949         struct intel_crtc_scaler_state scaler_state;
12950         struct intel_dpll_hw_state dpll_hw_state;
12951         struct intel_shared_dpll *shared_dpll;
12952         bool force_thru;
12953
12954         /* FIXME: before the switch to atomic started, a new pipe_config was
12955          * kzalloc'd. Code that depends on any field being zero should be
12956          * fixed, so that the crtc_state can be safely duplicated. For now,
12957          * only fields that are know to not cause problems are preserved. */
12958
12959         tmp_state = crtc_state->base;
12960         scaler_state = crtc_state->scaler_state;
12961         shared_dpll = crtc_state->shared_dpll;
12962         dpll_hw_state = crtc_state->dpll_hw_state;
12963         force_thru = crtc_state->pch_pfit.force_thru;
12964
12965         memset(crtc_state, 0, sizeof *crtc_state);
12966
12967         crtc_state->base = tmp_state;
12968         crtc_state->scaler_state = scaler_state;
12969         crtc_state->shared_dpll = shared_dpll;
12970         crtc_state->dpll_hw_state = dpll_hw_state;
12971         crtc_state->pch_pfit.force_thru = force_thru;
12972 }
12973
12974 static int
12975 intel_modeset_pipe_config(struct drm_crtc *crtc,
12976                           struct intel_crtc_state *pipe_config)
12977 {
12978         struct drm_atomic_state *state = pipe_config->base.state;
12979         struct intel_encoder *encoder;
12980         struct drm_connector *connector;
12981         struct drm_connector_state *connector_state;
12982         int base_bpp, ret = -EINVAL;
12983         int i;
12984         bool retry = true;
12985
12986         clear_intel_crtc_state(pipe_config);
12987
12988         pipe_config->cpu_transcoder =
12989                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12990
12991         /*
12992          * Sanitize sync polarity flags based on requested ones. If neither
12993          * positive or negative polarity is requested, treat this as meaning
12994          * negative polarity.
12995          */
12996         if (!(pipe_config->base.adjusted_mode.flags &
12997               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12998                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12999
13000         if (!(pipe_config->base.adjusted_mode.flags &
13001               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13002                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13003
13004         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13005                                              pipe_config);
13006         if (base_bpp < 0)
13007                 goto fail;
13008
13009         /*
13010          * Determine the real pipe dimensions. Note that stereo modes can
13011          * increase the actual pipe size due to the frame doubling and
13012          * insertion of additional space for blanks between the frame. This
13013          * is stored in the crtc timings. We use the requested mode to do this
13014          * computation to clearly distinguish it from the adjusted mode, which
13015          * can be changed by the connectors in the below retry loop.
13016          */
13017         drm_crtc_get_hv_timing(&pipe_config->base.mode,
13018                                &pipe_config->pipe_src_w,
13019                                &pipe_config->pipe_src_h);
13020
13021         for_each_connector_in_state(state, connector, connector_state, i) {
13022                 if (connector_state->crtc != crtc)
13023                         continue;
13024
13025                 encoder = to_intel_encoder(connector_state->best_encoder);
13026
13027                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13028                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13029                         goto fail;
13030                 }
13031
13032                 /*
13033                  * Determine output_types before calling the .compute_config()
13034                  * hooks so that the hooks can use this information safely.
13035                  */
13036                 pipe_config->output_types |= 1 << encoder->type;
13037         }
13038
13039 encoder_retry:
13040         /* Ensure the port clock defaults are reset when retrying. */
13041         pipe_config->port_clock = 0;
13042         pipe_config->pixel_multiplier = 1;
13043
13044         /* Fill in default crtc timings, allow encoders to overwrite them. */
13045         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13046                               CRTC_STEREO_DOUBLE);
13047
13048         /* Pass our mode to the connectors and the CRTC to give them a chance to
13049          * adjust it according to limitations or connector properties, and also
13050          * a chance to reject the mode entirely.
13051          */
13052         for_each_connector_in_state(state, connector, connector_state, i) {
13053                 if (connector_state->crtc != crtc)
13054                         continue;
13055
13056                 encoder = to_intel_encoder(connector_state->best_encoder);
13057
13058                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13059                         DRM_DEBUG_KMS("Encoder config failure\n");
13060                         goto fail;
13061                 }
13062         }
13063
13064         /* Set default port clock if not overwritten by the encoder. Needs to be
13065          * done afterwards in case the encoder adjusts the mode. */
13066         if (!pipe_config->port_clock)
13067                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13068                         * pipe_config->pixel_multiplier;
13069
13070         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13071         if (ret < 0) {
13072                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13073                 goto fail;
13074         }
13075
13076         if (ret == RETRY) {
13077                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13078                         ret = -EINVAL;
13079                         goto fail;
13080                 }
13081
13082                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13083                 retry = false;
13084                 goto encoder_retry;
13085         }
13086
13087         /* Dithering seems to not pass-through bits correctly when it should, so
13088          * only enable it on 6bpc panels. */
13089         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13090         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13091                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13092
13093 fail:
13094         return ret;
13095 }
13096
13097 static void
13098 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13099 {
13100         struct drm_crtc *crtc;
13101         struct drm_crtc_state *crtc_state;
13102         int i;
13103
13104         /* Double check state. */
13105         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13106                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13107
13108                 /* Update hwmode for vblank functions */
13109                 if (crtc->state->active)
13110                         crtc->hwmode = crtc->state->adjusted_mode;
13111                 else
13112                         crtc->hwmode.crtc_clock = 0;
13113
13114                 /*
13115                  * Update legacy state to satisfy fbc code. This can
13116                  * be removed when fbc uses the atomic state.
13117                  */
13118                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13119                         struct drm_plane_state *plane_state = crtc->primary->state;
13120
13121                         crtc->primary->fb = plane_state->fb;
13122                         crtc->x = plane_state->src_x >> 16;
13123                         crtc->y = plane_state->src_y >> 16;
13124                 }
13125         }
13126 }
13127
13128 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13129 {
13130         int diff;
13131
13132         if (clock1 == clock2)
13133                 return true;
13134
13135         if (!clock1 || !clock2)
13136                 return false;
13137
13138         diff = abs(clock1 - clock2);
13139
13140         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13141                 return true;
13142
13143         return false;
13144 }
13145
13146 static bool
13147 intel_compare_m_n(unsigned int m, unsigned int n,
13148                   unsigned int m2, unsigned int n2,
13149                   bool exact)
13150 {
13151         if (m == m2 && n == n2)
13152                 return true;
13153
13154         if (exact || !m || !n || !m2 || !n2)
13155                 return false;
13156
13157         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13158
13159         if (n > n2) {
13160                 while (n > n2) {
13161                         m2 <<= 1;
13162                         n2 <<= 1;
13163                 }
13164         } else if (n < n2) {
13165                 while (n < n2) {
13166                         m <<= 1;
13167                         n <<= 1;
13168                 }
13169         }
13170
13171         if (n != n2)
13172                 return false;
13173
13174         return intel_fuzzy_clock_check(m, m2);
13175 }
13176
13177 static bool
13178 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13179                        struct intel_link_m_n *m2_n2,
13180                        bool adjust)
13181 {
13182         if (m_n->tu == m2_n2->tu &&
13183             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13184                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13185             intel_compare_m_n(m_n->link_m, m_n->link_n,
13186                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13187                 if (adjust)
13188                         *m2_n2 = *m_n;
13189
13190                 return true;
13191         }
13192
13193         return false;
13194 }
13195
13196 static bool
13197 intel_pipe_config_compare(struct drm_device *dev,
13198                           struct intel_crtc_state *current_config,
13199                           struct intel_crtc_state *pipe_config,
13200                           bool adjust)
13201 {
13202         struct drm_i915_private *dev_priv = to_i915(dev);
13203         bool ret = true;
13204
13205 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13206         do { \
13207                 if (!adjust) \
13208                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13209                 else \
13210                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13211         } while (0)
13212
13213 #define PIPE_CONF_CHECK_X(name) \
13214         if (current_config->name != pipe_config->name) { \
13215                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13216                           "(expected 0x%08x, found 0x%08x)\n", \
13217                           current_config->name, \
13218                           pipe_config->name); \
13219                 ret = false; \
13220         }
13221
13222 #define PIPE_CONF_CHECK_I(name) \
13223         if (current_config->name != pipe_config->name) { \
13224                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13225                           "(expected %i, found %i)\n", \
13226                           current_config->name, \
13227                           pipe_config->name); \
13228                 ret = false; \
13229         }
13230
13231 #define PIPE_CONF_CHECK_P(name) \
13232         if (current_config->name != pipe_config->name) { \
13233                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13234                           "(expected %p, found %p)\n", \
13235                           current_config->name, \
13236                           pipe_config->name); \
13237                 ret = false; \
13238         }
13239
13240 #define PIPE_CONF_CHECK_M_N(name) \
13241         if (!intel_compare_link_m_n(&current_config->name, \
13242                                     &pipe_config->name,\
13243                                     adjust)) { \
13244                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13245                           "(expected tu %i gmch %i/%i link %i/%i, " \
13246                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13247                           current_config->name.tu, \
13248                           current_config->name.gmch_m, \
13249                           current_config->name.gmch_n, \
13250                           current_config->name.link_m, \
13251                           current_config->name.link_n, \
13252                           pipe_config->name.tu, \
13253                           pipe_config->name.gmch_m, \
13254                           pipe_config->name.gmch_n, \
13255                           pipe_config->name.link_m, \
13256                           pipe_config->name.link_n); \
13257                 ret = false; \
13258         }
13259
13260 /* This is required for BDW+ where there is only one set of registers for
13261  * switching between high and low RR.
13262  * This macro can be used whenever a comparison has to be made between one
13263  * hw state and multiple sw state variables.
13264  */
13265 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13266         if (!intel_compare_link_m_n(&current_config->name, \
13267                                     &pipe_config->name, adjust) && \
13268             !intel_compare_link_m_n(&current_config->alt_name, \
13269                                     &pipe_config->name, adjust)) { \
13270                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13271                           "(expected tu %i gmch %i/%i link %i/%i, " \
13272                           "or tu %i gmch %i/%i link %i/%i, " \
13273                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13274                           current_config->name.tu, \
13275                           current_config->name.gmch_m, \
13276                           current_config->name.gmch_n, \
13277                           current_config->name.link_m, \
13278                           current_config->name.link_n, \
13279                           current_config->alt_name.tu, \
13280                           current_config->alt_name.gmch_m, \
13281                           current_config->alt_name.gmch_n, \
13282                           current_config->alt_name.link_m, \
13283                           current_config->alt_name.link_n, \
13284                           pipe_config->name.tu, \
13285                           pipe_config->name.gmch_m, \
13286                           pipe_config->name.gmch_n, \
13287                           pipe_config->name.link_m, \
13288                           pipe_config->name.link_n); \
13289                 ret = false; \
13290         }
13291
13292 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13293         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13294                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13295                           "(expected %i, found %i)\n", \
13296                           current_config->name & (mask), \
13297                           pipe_config->name & (mask)); \
13298                 ret = false; \
13299         }
13300
13301 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13302         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13303                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13304                           "(expected %i, found %i)\n", \
13305                           current_config->name, \
13306                           pipe_config->name); \
13307                 ret = false; \
13308         }
13309
13310 #define PIPE_CONF_QUIRK(quirk)  \
13311         ((current_config->quirks | pipe_config->quirks) & (quirk))
13312
13313         PIPE_CONF_CHECK_I(cpu_transcoder);
13314
13315         PIPE_CONF_CHECK_I(has_pch_encoder);
13316         PIPE_CONF_CHECK_I(fdi_lanes);
13317         PIPE_CONF_CHECK_M_N(fdi_m_n);
13318
13319         PIPE_CONF_CHECK_I(lane_count);
13320         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13321
13322         if (INTEL_INFO(dev)->gen < 8) {
13323                 PIPE_CONF_CHECK_M_N(dp_m_n);
13324
13325                 if (current_config->has_drrs)
13326                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13327         } else
13328                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13329
13330         PIPE_CONF_CHECK_X(output_types);
13331
13332         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13333         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13334         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13335         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13336         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13337         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13338
13339         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13340         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13341         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13342         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13343         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13344         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13345
13346         PIPE_CONF_CHECK_I(pixel_multiplier);
13347         PIPE_CONF_CHECK_I(has_hdmi_sink);
13348         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13349             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13350                 PIPE_CONF_CHECK_I(limited_color_range);
13351         PIPE_CONF_CHECK_I(has_infoframe);
13352
13353         PIPE_CONF_CHECK_I(has_audio);
13354
13355         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13356                               DRM_MODE_FLAG_INTERLACE);
13357
13358         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13359                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13360                                       DRM_MODE_FLAG_PHSYNC);
13361                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13362                                       DRM_MODE_FLAG_NHSYNC);
13363                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13364                                       DRM_MODE_FLAG_PVSYNC);
13365                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13366                                       DRM_MODE_FLAG_NVSYNC);
13367         }
13368
13369         PIPE_CONF_CHECK_X(gmch_pfit.control);
13370         /* pfit ratios are autocomputed by the hw on gen4+ */
13371         if (INTEL_INFO(dev)->gen < 4)
13372                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13373         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13374
13375         if (!adjust) {
13376                 PIPE_CONF_CHECK_I(pipe_src_w);
13377                 PIPE_CONF_CHECK_I(pipe_src_h);
13378
13379                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13380                 if (current_config->pch_pfit.enabled) {
13381                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13382                         PIPE_CONF_CHECK_X(pch_pfit.size);
13383                 }
13384
13385                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13386         }
13387
13388         /* BDW+ don't expose a synchronous way to read the state */
13389         if (IS_HASWELL(dev_priv))
13390                 PIPE_CONF_CHECK_I(ips_enabled);
13391
13392         PIPE_CONF_CHECK_I(double_wide);
13393
13394         PIPE_CONF_CHECK_P(shared_dpll);
13395         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13396         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13397         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13398         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13399         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13400         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13401         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13402         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13403         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13404
13405         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13406         PIPE_CONF_CHECK_X(dsi_pll.div);
13407
13408         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13409                 PIPE_CONF_CHECK_I(pipe_bpp);
13410
13411         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13412         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13413
13414 #undef PIPE_CONF_CHECK_X
13415 #undef PIPE_CONF_CHECK_I
13416 #undef PIPE_CONF_CHECK_P
13417 #undef PIPE_CONF_CHECK_FLAGS
13418 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13419 #undef PIPE_CONF_QUIRK
13420 #undef INTEL_ERR_OR_DBG_KMS
13421
13422         return ret;
13423 }
13424
13425 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13426                                            const struct intel_crtc_state *pipe_config)
13427 {
13428         if (pipe_config->has_pch_encoder) {
13429                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13430                                                             &pipe_config->fdi_m_n);
13431                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13432
13433                 /*
13434                  * FDI already provided one idea for the dotclock.
13435                  * Yell if the encoder disagrees.
13436                  */
13437                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13438                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13439                      fdi_dotclock, dotclock);
13440         }
13441 }
13442
13443 static void verify_wm_state(struct drm_crtc *crtc,
13444                             struct drm_crtc_state *new_state)
13445 {
13446         struct drm_device *dev = crtc->dev;
13447         struct drm_i915_private *dev_priv = to_i915(dev);
13448         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13449         struct skl_ddb_entry *hw_entry, *sw_entry;
13450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13451         const enum pipe pipe = intel_crtc->pipe;
13452         int plane;
13453
13454         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13455                 return;
13456
13457         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13458         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13459
13460         /* planes */
13461         for_each_plane(dev_priv, pipe, plane) {
13462                 hw_entry = &hw_ddb.plane[pipe][plane];
13463                 sw_entry = &sw_ddb->plane[pipe][plane];
13464
13465                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13466                         continue;
13467
13468                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13469                           "(expected (%u,%u), found (%u,%u))\n",
13470                           pipe_name(pipe), plane + 1,
13471                           sw_entry->start, sw_entry->end,
13472                           hw_entry->start, hw_entry->end);
13473         }
13474
13475         /*
13476          * cursor
13477          * If the cursor plane isn't active, we may not have updated it's ddb
13478          * allocation. In that case since the ddb allocation will be updated
13479          * once the plane becomes visible, we can skip this check
13480          */
13481         if (intel_crtc->cursor_addr) {
13482                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13483                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13484
13485                 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13486                         DRM_ERROR("mismatch in DDB state pipe %c cursor "
13487                                   "(expected (%u,%u), found (%u,%u))\n",
13488                                   pipe_name(pipe),
13489                                   sw_entry->start, sw_entry->end,
13490                                   hw_entry->start, hw_entry->end);
13491                 }
13492         }
13493 }
13494
13495 static void
13496 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13497 {
13498         struct drm_connector *connector;
13499
13500         drm_for_each_connector(connector, dev) {
13501                 struct drm_encoder *encoder = connector->encoder;
13502                 struct drm_connector_state *state = connector->state;
13503
13504                 if (state->crtc != crtc)
13505                         continue;
13506
13507                 intel_connector_verify_state(to_intel_connector(connector));
13508
13509                 I915_STATE_WARN(state->best_encoder != encoder,
13510                      "connector's atomic encoder doesn't match legacy encoder\n");
13511         }
13512 }
13513
13514 static void
13515 verify_encoder_state(struct drm_device *dev)
13516 {
13517         struct intel_encoder *encoder;
13518         struct intel_connector *connector;
13519
13520         for_each_intel_encoder(dev, encoder) {
13521                 bool enabled = false;
13522                 enum pipe pipe;
13523
13524                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13525                               encoder->base.base.id,
13526                               encoder->base.name);
13527
13528                 for_each_intel_connector(dev, connector) {
13529                         if (connector->base.state->best_encoder != &encoder->base)
13530                                 continue;
13531                         enabled = true;
13532
13533                         I915_STATE_WARN(connector->base.state->crtc !=
13534                                         encoder->base.crtc,
13535                              "connector's crtc doesn't match encoder crtc\n");
13536                 }
13537
13538                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13539                      "encoder's enabled state mismatch "
13540                      "(expected %i, found %i)\n",
13541                      !!encoder->base.crtc, enabled);
13542
13543                 if (!encoder->base.crtc) {
13544                         bool active;
13545
13546                         active = encoder->get_hw_state(encoder, &pipe);
13547                         I915_STATE_WARN(active,
13548                              "encoder detached but still enabled on pipe %c.\n",
13549                              pipe_name(pipe));
13550                 }
13551         }
13552 }
13553
13554 static void
13555 verify_crtc_state(struct drm_crtc *crtc,
13556                   struct drm_crtc_state *old_crtc_state,
13557                   struct drm_crtc_state *new_crtc_state)
13558 {
13559         struct drm_device *dev = crtc->dev;
13560         struct drm_i915_private *dev_priv = to_i915(dev);
13561         struct intel_encoder *encoder;
13562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13563         struct intel_crtc_state *pipe_config, *sw_config;
13564         struct drm_atomic_state *old_state;
13565         bool active;
13566
13567         old_state = old_crtc_state->state;
13568         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13569         pipe_config = to_intel_crtc_state(old_crtc_state);
13570         memset(pipe_config, 0, sizeof(*pipe_config));
13571         pipe_config->base.crtc = crtc;
13572         pipe_config->base.state = old_state;
13573
13574         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13575
13576         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13577
13578         /* hw state is inconsistent with the pipe quirk */
13579         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13580             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13581                 active = new_crtc_state->active;
13582
13583         I915_STATE_WARN(new_crtc_state->active != active,
13584              "crtc active state doesn't match with hw state "
13585              "(expected %i, found %i)\n", new_crtc_state->active, active);
13586
13587         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13588              "transitional active state does not match atomic hw state "
13589              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13590
13591         for_each_encoder_on_crtc(dev, crtc, encoder) {
13592                 enum pipe pipe;
13593
13594                 active = encoder->get_hw_state(encoder, &pipe);
13595                 I915_STATE_WARN(active != new_crtc_state->active,
13596                         "[ENCODER:%i] active %i with crtc active %i\n",
13597                         encoder->base.base.id, active, new_crtc_state->active);
13598
13599                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13600                                 "Encoder connected to wrong pipe %c\n",
13601                                 pipe_name(pipe));
13602
13603                 if (active) {
13604                         pipe_config->output_types |= 1 << encoder->type;
13605                         encoder->get_config(encoder, pipe_config);
13606                 }
13607         }
13608
13609         if (!new_crtc_state->active)
13610                 return;
13611
13612         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13613
13614         sw_config = to_intel_crtc_state(crtc->state);
13615         if (!intel_pipe_config_compare(dev, sw_config,
13616                                        pipe_config, false)) {
13617                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13618                 intel_dump_pipe_config(intel_crtc, pipe_config,
13619                                        "[hw state]");
13620                 intel_dump_pipe_config(intel_crtc, sw_config,
13621                                        "[sw state]");
13622         }
13623 }
13624
13625 static void
13626 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13627                          struct intel_shared_dpll *pll,
13628                          struct drm_crtc *crtc,
13629                          struct drm_crtc_state *new_state)
13630 {
13631         struct intel_dpll_hw_state dpll_hw_state;
13632         unsigned crtc_mask;
13633         bool active;
13634
13635         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13636
13637         DRM_DEBUG_KMS("%s\n", pll->name);
13638
13639         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13640
13641         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13642                 I915_STATE_WARN(!pll->on && pll->active_mask,
13643                      "pll in active use but not on in sw tracking\n");
13644                 I915_STATE_WARN(pll->on && !pll->active_mask,
13645                      "pll is on but not used by any active crtc\n");
13646                 I915_STATE_WARN(pll->on != active,
13647                      "pll on state mismatch (expected %i, found %i)\n",
13648                      pll->on, active);
13649         }
13650
13651         if (!crtc) {
13652                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13653                                 "more active pll users than references: %x vs %x\n",
13654                                 pll->active_mask, pll->config.crtc_mask);
13655
13656                 return;
13657         }
13658
13659         crtc_mask = 1 << drm_crtc_index(crtc);
13660
13661         if (new_state->active)
13662                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13663                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13664                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13665         else
13666                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13667                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13668                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13669
13670         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13671                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13672                         crtc_mask, pll->config.crtc_mask);
13673
13674         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13675                                           &dpll_hw_state,
13676                                           sizeof(dpll_hw_state)),
13677                         "pll hw state mismatch\n");
13678 }
13679
13680 static void
13681 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13682                          struct drm_crtc_state *old_crtc_state,
13683                          struct drm_crtc_state *new_crtc_state)
13684 {
13685         struct drm_i915_private *dev_priv = to_i915(dev);
13686         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13687         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13688
13689         if (new_state->shared_dpll)
13690                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13691
13692         if (old_state->shared_dpll &&
13693             old_state->shared_dpll != new_state->shared_dpll) {
13694                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13695                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13696
13697                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13698                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13699                                 pipe_name(drm_crtc_index(crtc)));
13700                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13701                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13702                                 pipe_name(drm_crtc_index(crtc)));
13703         }
13704 }
13705
13706 static void
13707 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13708                          struct drm_crtc_state *old_state,
13709                          struct drm_crtc_state *new_state)
13710 {
13711         if (!needs_modeset(new_state) &&
13712             !to_intel_crtc_state(new_state)->update_pipe)
13713                 return;
13714
13715         verify_wm_state(crtc, new_state);
13716         verify_connector_state(crtc->dev, crtc);
13717         verify_crtc_state(crtc, old_state, new_state);
13718         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13719 }
13720
13721 static void
13722 verify_disabled_dpll_state(struct drm_device *dev)
13723 {
13724         struct drm_i915_private *dev_priv = to_i915(dev);
13725         int i;
13726
13727         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13728                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13729 }
13730
13731 static void
13732 intel_modeset_verify_disabled(struct drm_device *dev)
13733 {
13734         verify_encoder_state(dev);
13735         verify_connector_state(dev, NULL);
13736         verify_disabled_dpll_state(dev);
13737 }
13738
13739 static void update_scanline_offset(struct intel_crtc *crtc)
13740 {
13741         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13742
13743         /*
13744          * The scanline counter increments at the leading edge of hsync.
13745          *
13746          * On most platforms it starts counting from vtotal-1 on the
13747          * first active line. That means the scanline counter value is
13748          * always one less than what we would expect. Ie. just after
13749          * start of vblank, which also occurs at start of hsync (on the
13750          * last active line), the scanline counter will read vblank_start-1.
13751          *
13752          * On gen2 the scanline counter starts counting from 1 instead
13753          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13754          * to keep the value positive), instead of adding one.
13755          *
13756          * On HSW+ the behaviour of the scanline counter depends on the output
13757          * type. For DP ports it behaves like most other platforms, but on HDMI
13758          * there's an extra 1 line difference. So we need to add two instead of
13759          * one to the value.
13760          */
13761         if (IS_GEN2(dev_priv)) {
13762                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13763                 int vtotal;
13764
13765                 vtotal = adjusted_mode->crtc_vtotal;
13766                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13767                         vtotal /= 2;
13768
13769                 crtc->scanline_offset = vtotal - 1;
13770         } else if (HAS_DDI(dev_priv) &&
13771                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13772                 crtc->scanline_offset = 2;
13773         } else
13774                 crtc->scanline_offset = 1;
13775 }
13776
13777 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13778 {
13779         struct drm_device *dev = state->dev;
13780         struct drm_i915_private *dev_priv = to_i915(dev);
13781         struct intel_shared_dpll_config *shared_dpll = NULL;
13782         struct drm_crtc *crtc;
13783         struct drm_crtc_state *crtc_state;
13784         int i;
13785
13786         if (!dev_priv->display.crtc_compute_clock)
13787                 return;
13788
13789         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13790                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13791                 struct intel_shared_dpll *old_dpll =
13792                         to_intel_crtc_state(crtc->state)->shared_dpll;
13793
13794                 if (!needs_modeset(crtc_state))
13795                         continue;
13796
13797                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13798
13799                 if (!old_dpll)
13800                         continue;
13801
13802                 if (!shared_dpll)
13803                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13804
13805                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13806         }
13807 }
13808
13809 /*
13810  * This implements the workaround described in the "notes" section of the mode
13811  * set sequence documentation. When going from no pipes or single pipe to
13812  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13813  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13814  */
13815 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13816 {
13817         struct drm_crtc_state *crtc_state;
13818         struct intel_crtc *intel_crtc;
13819         struct drm_crtc *crtc;
13820         struct intel_crtc_state *first_crtc_state = NULL;
13821         struct intel_crtc_state *other_crtc_state = NULL;
13822         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13823         int i;
13824
13825         /* look at all crtc's that are going to be enabled in during modeset */
13826         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13827                 intel_crtc = to_intel_crtc(crtc);
13828
13829                 if (!crtc_state->active || !needs_modeset(crtc_state))
13830                         continue;
13831
13832                 if (first_crtc_state) {
13833                         other_crtc_state = to_intel_crtc_state(crtc_state);
13834                         break;
13835                 } else {
13836                         first_crtc_state = to_intel_crtc_state(crtc_state);
13837                         first_pipe = intel_crtc->pipe;
13838                 }
13839         }
13840
13841         /* No workaround needed? */
13842         if (!first_crtc_state)
13843                 return 0;
13844
13845         /* w/a possibly needed, check how many crtc's are already enabled. */
13846         for_each_intel_crtc(state->dev, intel_crtc) {
13847                 struct intel_crtc_state *pipe_config;
13848
13849                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13850                 if (IS_ERR(pipe_config))
13851                         return PTR_ERR(pipe_config);
13852
13853                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13854
13855                 if (!pipe_config->base.active ||
13856                     needs_modeset(&pipe_config->base))
13857                         continue;
13858
13859                 /* 2 or more enabled crtcs means no need for w/a */
13860                 if (enabled_pipe != INVALID_PIPE)
13861                         return 0;
13862
13863                 enabled_pipe = intel_crtc->pipe;
13864         }
13865
13866         if (enabled_pipe != INVALID_PIPE)
13867                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13868         else if (other_crtc_state)
13869                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13870
13871         return 0;
13872 }
13873
13874 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13875 {
13876         struct drm_crtc *crtc;
13877         struct drm_crtc_state *crtc_state;
13878         int ret = 0;
13879
13880         /* add all active pipes to the state */
13881         for_each_crtc(state->dev, crtc) {
13882                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13883                 if (IS_ERR(crtc_state))
13884                         return PTR_ERR(crtc_state);
13885
13886                 if (!crtc_state->active || needs_modeset(crtc_state))
13887                         continue;
13888
13889                 crtc_state->mode_changed = true;
13890
13891                 ret = drm_atomic_add_affected_connectors(state, crtc);
13892                 if (ret)
13893                         break;
13894
13895                 ret = drm_atomic_add_affected_planes(state, crtc);
13896                 if (ret)
13897                         break;
13898         }
13899
13900         return ret;
13901 }
13902
13903 static int intel_modeset_checks(struct drm_atomic_state *state)
13904 {
13905         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13906         struct drm_i915_private *dev_priv = to_i915(state->dev);
13907         struct drm_crtc *crtc;
13908         struct drm_crtc_state *crtc_state;
13909         int ret = 0, i;
13910
13911         if (!check_digital_port_conflicts(state)) {
13912                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13913                 return -EINVAL;
13914         }
13915
13916         intel_state->modeset = true;
13917         intel_state->active_crtcs = dev_priv->active_crtcs;
13918
13919         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13920                 if (crtc_state->active)
13921                         intel_state->active_crtcs |= 1 << i;
13922                 else
13923                         intel_state->active_crtcs &= ~(1 << i);
13924
13925                 if (crtc_state->active != crtc->state->active)
13926                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13927         }
13928
13929         /*
13930          * See if the config requires any additional preparation, e.g.
13931          * to adjust global state with pipes off.  We need to do this
13932          * here so we can get the modeset_pipe updated config for the new
13933          * mode set on this crtc.  For other crtcs we need to use the
13934          * adjusted_mode bits in the crtc directly.
13935          */
13936         if (dev_priv->display.modeset_calc_cdclk) {
13937                 if (!intel_state->cdclk_pll_vco)
13938                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13939                 if (!intel_state->cdclk_pll_vco)
13940                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13941
13942                 ret = dev_priv->display.modeset_calc_cdclk(state);
13943                 if (ret < 0)
13944                         return ret;
13945
13946                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13947                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13948                         ret = intel_modeset_all_pipes(state);
13949
13950                 if (ret < 0)
13951                         return ret;
13952
13953                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13954                               intel_state->cdclk, intel_state->dev_cdclk);
13955         } else
13956                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13957
13958         intel_modeset_clear_plls(state);
13959
13960         if (IS_HASWELL(dev_priv))
13961                 return haswell_mode_set_planes_workaround(state);
13962
13963         return 0;
13964 }
13965
13966 /*
13967  * Handle calculation of various watermark data at the end of the atomic check
13968  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13969  * handlers to ensure that all derived state has been updated.
13970  */
13971 static int calc_watermark_data(struct drm_atomic_state *state)
13972 {
13973         struct drm_device *dev = state->dev;
13974         struct drm_i915_private *dev_priv = to_i915(dev);
13975
13976         /* Is there platform-specific watermark information to calculate? */
13977         if (dev_priv->display.compute_global_watermarks)
13978                 return dev_priv->display.compute_global_watermarks(state);
13979
13980         return 0;
13981 }
13982
13983 /**
13984  * intel_atomic_check - validate state object
13985  * @dev: drm device
13986  * @state: state to validate
13987  */
13988 static int intel_atomic_check(struct drm_device *dev,
13989                               struct drm_atomic_state *state)
13990 {
13991         struct drm_i915_private *dev_priv = to_i915(dev);
13992         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13993         struct drm_crtc *crtc;
13994         struct drm_crtc_state *crtc_state;
13995         int ret, i;
13996         bool any_ms = false;
13997
13998         ret = drm_atomic_helper_check_modeset(dev, state);
13999         if (ret)
14000                 return ret;
14001
14002         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14003                 struct intel_crtc_state *pipe_config =
14004                         to_intel_crtc_state(crtc_state);
14005
14006                 /* Catch I915_MODE_FLAG_INHERITED */
14007                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14008                         crtc_state->mode_changed = true;
14009
14010                 if (!needs_modeset(crtc_state))
14011                         continue;
14012
14013                 if (!crtc_state->enable) {
14014                         any_ms = true;
14015                         continue;
14016                 }
14017
14018                 /* FIXME: For only active_changed we shouldn't need to do any
14019                  * state recomputation at all. */
14020
14021                 ret = drm_atomic_add_affected_connectors(state, crtc);
14022                 if (ret)
14023                         return ret;
14024
14025                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14026                 if (ret) {
14027                         intel_dump_pipe_config(to_intel_crtc(crtc),
14028                                                pipe_config, "[failed]");
14029                         return ret;
14030                 }
14031
14032                 if (i915.fastboot &&
14033                     intel_pipe_config_compare(dev,
14034                                         to_intel_crtc_state(crtc->state),
14035                                         pipe_config, true)) {
14036                         crtc_state->mode_changed = false;
14037                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14038                 }
14039
14040                 if (needs_modeset(crtc_state))
14041                         any_ms = true;
14042
14043                 ret = drm_atomic_add_affected_planes(state, crtc);
14044                 if (ret)
14045                         return ret;
14046
14047                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14048                                        needs_modeset(crtc_state) ?
14049                                        "[modeset]" : "[fastset]");
14050         }
14051
14052         if (any_ms) {
14053                 ret = intel_modeset_checks(state);
14054
14055                 if (ret)
14056                         return ret;
14057         } else
14058                 intel_state->cdclk = dev_priv->cdclk_freq;
14059
14060         ret = drm_atomic_helper_check_planes(dev, state);
14061         if (ret)
14062                 return ret;
14063
14064         intel_fbc_choose_crtc(dev_priv, state);
14065         return calc_watermark_data(state);
14066 }
14067
14068 static int intel_atomic_prepare_commit(struct drm_device *dev,
14069                                        struct drm_atomic_state *state,
14070                                        bool nonblock)
14071 {
14072         struct drm_i915_private *dev_priv = to_i915(dev);
14073         struct drm_plane_state *plane_state;
14074         struct drm_crtc_state *crtc_state;
14075         struct drm_plane *plane;
14076         struct drm_crtc *crtc;
14077         int i, ret;
14078
14079         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14080                 if (state->legacy_cursor_update)
14081                         continue;
14082
14083                 ret = intel_crtc_wait_for_pending_flips(crtc);
14084                 if (ret)
14085                         return ret;
14086
14087                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14088                         flush_workqueue(dev_priv->wq);
14089         }
14090
14091         ret = mutex_lock_interruptible(&dev->struct_mutex);
14092         if (ret)
14093                 return ret;
14094
14095         ret = drm_atomic_helper_prepare_planes(dev, state);
14096         mutex_unlock(&dev->struct_mutex);
14097
14098         if (!ret && !nonblock) {
14099                 for_each_plane_in_state(state, plane, plane_state, i) {
14100                         struct intel_plane_state *intel_plane_state =
14101                                 to_intel_plane_state(plane_state);
14102
14103                         if (!intel_plane_state->wait_req)
14104                                 continue;
14105
14106                         ret = i915_wait_request(intel_plane_state->wait_req,
14107                                                 I915_WAIT_INTERRUPTIBLE,
14108                                                 NULL, NULL);
14109                         if (ret) {
14110                                 /* Any hang should be swallowed by the wait */
14111                                 WARN_ON(ret == -EIO);
14112                                 mutex_lock(&dev->struct_mutex);
14113                                 drm_atomic_helper_cleanup_planes(dev, state);
14114                                 mutex_unlock(&dev->struct_mutex);
14115                                 break;
14116                         }
14117                 }
14118         }
14119
14120         return ret;
14121 }
14122
14123 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14124 {
14125         struct drm_device *dev = crtc->base.dev;
14126
14127         if (!dev->max_vblank_count)
14128                 return drm_accurate_vblank_count(&crtc->base);
14129
14130         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14131 }
14132
14133 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14134                                           struct drm_i915_private *dev_priv,
14135                                           unsigned crtc_mask)
14136 {
14137         unsigned last_vblank_count[I915_MAX_PIPES];
14138         enum pipe pipe;
14139         int ret;
14140
14141         if (!crtc_mask)
14142                 return;
14143
14144         for_each_pipe(dev_priv, pipe) {
14145                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14146
14147                 if (!((1 << pipe) & crtc_mask))
14148                         continue;
14149
14150                 ret = drm_crtc_vblank_get(crtc);
14151                 if (WARN_ON(ret != 0)) {
14152                         crtc_mask &= ~(1 << pipe);
14153                         continue;
14154                 }
14155
14156                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14157         }
14158
14159         for_each_pipe(dev_priv, pipe) {
14160                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14161                 long lret;
14162
14163                 if (!((1 << pipe) & crtc_mask))
14164                         continue;
14165
14166                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14167                                 last_vblank_count[pipe] !=
14168                                         drm_crtc_vblank_count(crtc),
14169                                 msecs_to_jiffies(50));
14170
14171                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14172
14173                 drm_crtc_vblank_put(crtc);
14174         }
14175 }
14176
14177 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14178 {
14179         /* fb updated, need to unpin old fb */
14180         if (crtc_state->fb_changed)
14181                 return true;
14182
14183         /* wm changes, need vblank before final wm's */
14184         if (crtc_state->update_wm_post)
14185                 return true;
14186
14187         /*
14188          * cxsr is re-enabled after vblank.
14189          * This is already handled by crtc_state->update_wm_post,
14190          * but added for clarity.
14191          */
14192         if (crtc_state->disable_cxsr)
14193                 return true;
14194
14195         return false;
14196 }
14197
14198 static void intel_update_crtc(struct drm_crtc *crtc,
14199                               struct drm_atomic_state *state,
14200                               struct drm_crtc_state *old_crtc_state,
14201                               unsigned int *crtc_vblank_mask)
14202 {
14203         struct drm_device *dev = crtc->dev;
14204         struct drm_i915_private *dev_priv = to_i915(dev);
14205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14206         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14207         bool modeset = needs_modeset(crtc->state);
14208
14209         if (modeset) {
14210                 update_scanline_offset(intel_crtc);
14211                 dev_priv->display.crtc_enable(pipe_config, state);
14212         } else {
14213                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14214         }
14215
14216         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14217                 intel_fbc_enable(
14218                     intel_crtc, pipe_config,
14219                     to_intel_plane_state(crtc->primary->state));
14220         }
14221
14222         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14223
14224         if (needs_vblank_wait(pipe_config))
14225                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14226 }
14227
14228 static void intel_update_crtcs(struct drm_atomic_state *state,
14229                                unsigned int *crtc_vblank_mask)
14230 {
14231         struct drm_crtc *crtc;
14232         struct drm_crtc_state *old_crtc_state;
14233         int i;
14234
14235         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14236                 if (!crtc->state->active)
14237                         continue;
14238
14239                 intel_update_crtc(crtc, state, old_crtc_state,
14240                                   crtc_vblank_mask);
14241         }
14242 }
14243
14244 static void skl_update_crtcs(struct drm_atomic_state *state,
14245                              unsigned int *crtc_vblank_mask)
14246 {
14247         struct drm_device *dev = state->dev;
14248         struct drm_i915_private *dev_priv = to_i915(dev);
14249         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14250         struct drm_crtc *crtc;
14251         struct drm_crtc_state *old_crtc_state;
14252         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14253         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14254         unsigned int updated = 0;
14255         bool progress;
14256         enum pipe pipe;
14257
14258         /*
14259          * Whenever the number of active pipes changes, we need to make sure we
14260          * update the pipes in the right order so that their ddb allocations
14261          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14262          * cause pipe underruns and other bad stuff.
14263          */
14264         do {
14265                 int i;
14266                 progress = false;
14267
14268                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14269                         bool vbl_wait = false;
14270                         unsigned int cmask = drm_crtc_mask(crtc);
14271                         pipe = to_intel_crtc(crtc)->pipe;
14272
14273                         if (updated & cmask || !crtc->state->active)
14274                                 continue;
14275                         if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14276                                                         pipe))
14277                                 continue;
14278
14279                         updated |= cmask;
14280
14281                         /*
14282                          * If this is an already active pipe, it's DDB changed,
14283                          * and this isn't the last pipe that needs updating
14284                          * then we need to wait for a vblank to pass for the
14285                          * new ddb allocation to take effect.
14286                          */
14287                         if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14288                             !crtc->state->active_changed &&
14289                             intel_state->wm_results.dirty_pipes != updated)
14290                                 vbl_wait = true;
14291
14292                         intel_update_crtc(crtc, state, old_crtc_state,
14293                                           crtc_vblank_mask);
14294
14295                         if (vbl_wait)
14296                                 intel_wait_for_vblank(dev, pipe);
14297
14298                         progress = true;
14299                 }
14300         } while (progress);
14301 }
14302
14303 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14304 {
14305         struct drm_device *dev = state->dev;
14306         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14307         struct drm_i915_private *dev_priv = to_i915(dev);
14308         struct drm_crtc_state *old_crtc_state;
14309         struct drm_crtc *crtc;
14310         struct intel_crtc_state *intel_cstate;
14311         struct drm_plane *plane;
14312         struct drm_plane_state *plane_state;
14313         bool hw_check = intel_state->modeset;
14314         unsigned long put_domains[I915_MAX_PIPES] = {};
14315         unsigned crtc_vblank_mask = 0;
14316         int i, ret;
14317
14318         for_each_plane_in_state(state, plane, plane_state, i) {
14319                 struct intel_plane_state *intel_plane_state =
14320                         to_intel_plane_state(plane_state);
14321
14322                 if (!intel_plane_state->wait_req)
14323                         continue;
14324
14325                 ret = i915_wait_request(intel_plane_state->wait_req,
14326                                         0, NULL, NULL);
14327                 /* EIO should be eaten, and we can't get interrupted in the
14328                  * worker, and blocking commits have waited already. */
14329                 WARN_ON(ret);
14330         }
14331
14332         drm_atomic_helper_wait_for_dependencies(state);
14333
14334         if (intel_state->modeset) {
14335                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14336                        sizeof(intel_state->min_pixclk));
14337                 dev_priv->active_crtcs = intel_state->active_crtcs;
14338                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14339
14340                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14341         }
14342
14343         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14344                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14345
14346                 if (needs_modeset(crtc->state) ||
14347                     to_intel_crtc_state(crtc->state)->update_pipe) {
14348                         hw_check = true;
14349
14350                         put_domains[to_intel_crtc(crtc)->pipe] =
14351                                 modeset_get_crtc_power_domains(crtc,
14352                                         to_intel_crtc_state(crtc->state));
14353                 }
14354
14355                 if (!needs_modeset(crtc->state))
14356                         continue;
14357
14358                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14359
14360                 if (old_crtc_state->active) {
14361                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14362                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14363                         intel_crtc->active = false;
14364                         intel_fbc_disable(intel_crtc);
14365                         intel_disable_shared_dpll(intel_crtc);
14366
14367                         /*
14368                          * Underruns don't always raise
14369                          * interrupts, so check manually.
14370                          */
14371                         intel_check_cpu_fifo_underruns(dev_priv);
14372                         intel_check_pch_fifo_underruns(dev_priv);
14373
14374                         if (!crtc->state->active)
14375                                 intel_update_watermarks(crtc);
14376                 }
14377         }
14378
14379         /* Only after disabling all output pipelines that will be changed can we
14380          * update the the output configuration. */
14381         intel_modeset_update_crtc_state(state);
14382
14383         if (intel_state->modeset) {
14384                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14385
14386                 if (dev_priv->display.modeset_commit_cdclk &&
14387                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14388                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14389                         dev_priv->display.modeset_commit_cdclk(state);
14390
14391                 /*
14392                  * SKL workaround: bspec recommends we disable the SAGV when we
14393                  * have more then one pipe enabled
14394                  */
14395                 if (!intel_can_enable_sagv(state))
14396                         intel_disable_sagv(dev_priv);
14397
14398                 intel_modeset_verify_disabled(dev);
14399         }
14400
14401         /* Complete the events for pipes that have now been disabled */
14402         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14403                 bool modeset = needs_modeset(crtc->state);
14404
14405                 /* Complete events for now disable pipes here. */
14406                 if (modeset && !crtc->state->active && crtc->state->event) {
14407                         spin_lock_irq(&dev->event_lock);
14408                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14409                         spin_unlock_irq(&dev->event_lock);
14410
14411                         crtc->state->event = NULL;
14412                 }
14413         }
14414
14415         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14416         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14417
14418         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14419          * already, but still need the state for the delayed optimization. To
14420          * fix this:
14421          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14422          * - schedule that vblank worker _before_ calling hw_done
14423          * - at the start of commit_tail, cancel it _synchrously
14424          * - switch over to the vblank wait helper in the core after that since
14425          *   we don't need out special handling any more.
14426          */
14427         if (!state->legacy_cursor_update)
14428                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14429
14430         /*
14431          * Now that the vblank has passed, we can go ahead and program the
14432          * optimal watermarks on platforms that need two-step watermark
14433          * programming.
14434          *
14435          * TODO: Move this (and other cleanup) to an async worker eventually.
14436          */
14437         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14438                 intel_cstate = to_intel_crtc_state(crtc->state);
14439
14440                 if (dev_priv->display.optimize_watermarks)
14441                         dev_priv->display.optimize_watermarks(intel_cstate);
14442         }
14443
14444         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14445                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14446
14447                 if (put_domains[i])
14448                         modeset_put_power_domains(dev_priv, put_domains[i]);
14449
14450                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14451         }
14452
14453         if (intel_state->modeset && intel_can_enable_sagv(state))
14454                 intel_enable_sagv(dev_priv);
14455
14456         drm_atomic_helper_commit_hw_done(state);
14457
14458         if (intel_state->modeset)
14459                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14460
14461         mutex_lock(&dev->struct_mutex);
14462         drm_atomic_helper_cleanup_planes(dev, state);
14463         mutex_unlock(&dev->struct_mutex);
14464
14465         drm_atomic_helper_commit_cleanup_done(state);
14466
14467         drm_atomic_state_free(state);
14468
14469         /* As one of the primary mmio accessors, KMS has a high likelihood
14470          * of triggering bugs in unclaimed access. After we finish
14471          * modesetting, see if an error has been flagged, and if so
14472          * enable debugging for the next modeset - and hope we catch
14473          * the culprit.
14474          *
14475          * XXX note that we assume display power is on at this point.
14476          * This might hold true now but we need to add pm helper to check
14477          * unclaimed only when the hardware is on, as atomic commits
14478          * can happen also when the device is completely off.
14479          */
14480         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14481 }
14482
14483 static void intel_atomic_commit_work(struct work_struct *work)
14484 {
14485         struct drm_atomic_state *state = container_of(work,
14486                                                       struct drm_atomic_state,
14487                                                       commit_work);
14488         intel_atomic_commit_tail(state);
14489 }
14490
14491 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14492 {
14493         struct drm_plane_state *old_plane_state;
14494         struct drm_plane *plane;
14495         int i;
14496
14497         for_each_plane_in_state(state, plane, old_plane_state, i)
14498                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14499                                   intel_fb_obj(plane->state->fb),
14500                                   to_intel_plane(plane)->frontbuffer_bit);
14501 }
14502
14503 /**
14504  * intel_atomic_commit - commit validated state object
14505  * @dev: DRM device
14506  * @state: the top-level driver state object
14507  * @nonblock: nonblocking commit
14508  *
14509  * This function commits a top-level state object that has been validated
14510  * with drm_atomic_helper_check().
14511  *
14512  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
14513  * nonblocking commits are only safe for pure plane updates. Everything else
14514  * should work though.
14515  *
14516  * RETURNS
14517  * Zero for success or -errno.
14518  */
14519 static int intel_atomic_commit(struct drm_device *dev,
14520                                struct drm_atomic_state *state,
14521                                bool nonblock)
14522 {
14523         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14524         struct drm_i915_private *dev_priv = to_i915(dev);
14525         int ret = 0;
14526
14527         if (intel_state->modeset && nonblock) {
14528                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14529                 return -EINVAL;
14530         }
14531
14532         ret = drm_atomic_helper_setup_commit(state, nonblock);
14533         if (ret)
14534                 return ret;
14535
14536         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14537
14538         ret = intel_atomic_prepare_commit(dev, state, nonblock);
14539         if (ret) {
14540                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14541                 return ret;
14542         }
14543
14544         drm_atomic_helper_swap_state(state, true);
14545         dev_priv->wm.distrust_bios_wm = false;
14546         dev_priv->wm.skl_results = intel_state->wm_results;
14547         intel_shared_dpll_commit(state);
14548         intel_atomic_track_fbs(state);
14549
14550         if (nonblock)
14551                 queue_work(system_unbound_wq, &state->commit_work);
14552         else
14553                 intel_atomic_commit_tail(state);
14554
14555         return 0;
14556 }
14557
14558 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14559 {
14560         struct drm_device *dev = crtc->dev;
14561         struct drm_atomic_state *state;
14562         struct drm_crtc_state *crtc_state;
14563         int ret;
14564
14565         state = drm_atomic_state_alloc(dev);
14566         if (!state) {
14567                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14568                               crtc->base.id, crtc->name);
14569                 return;
14570         }
14571
14572         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14573
14574 retry:
14575         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14576         ret = PTR_ERR_OR_ZERO(crtc_state);
14577         if (!ret) {
14578                 if (!crtc_state->active)
14579                         goto out;
14580
14581                 crtc_state->mode_changed = true;
14582                 ret = drm_atomic_commit(state);
14583         }
14584
14585         if (ret == -EDEADLK) {
14586                 drm_atomic_state_clear(state);
14587                 drm_modeset_backoff(state->acquire_ctx);
14588                 goto retry;
14589         }
14590
14591         if (ret)
14592 out:
14593                 drm_atomic_state_free(state);
14594 }
14595
14596 /*
14597  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14598  *        drm_atomic_helper_legacy_gamma_set() directly.
14599  */
14600 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14601                                          u16 *red, u16 *green, u16 *blue,
14602                                          uint32_t size)
14603 {
14604         struct drm_device *dev = crtc->dev;
14605         struct drm_mode_config *config = &dev->mode_config;
14606         struct drm_crtc_state *state;
14607         int ret;
14608
14609         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14610         if (ret)
14611                 return ret;
14612
14613         /*
14614          * Make sure we update the legacy properties so this works when
14615          * atomic is not enabled.
14616          */
14617
14618         state = crtc->state;
14619
14620         drm_object_property_set_value(&crtc->base,
14621                                       config->degamma_lut_property,
14622                                       (state->degamma_lut) ?
14623                                       state->degamma_lut->base.id : 0);
14624
14625         drm_object_property_set_value(&crtc->base,
14626                                       config->ctm_property,
14627                                       (state->ctm) ?
14628                                       state->ctm->base.id : 0);
14629
14630         drm_object_property_set_value(&crtc->base,
14631                                       config->gamma_lut_property,
14632                                       (state->gamma_lut) ?
14633                                       state->gamma_lut->base.id : 0);
14634
14635         return 0;
14636 }
14637
14638 static const struct drm_crtc_funcs intel_crtc_funcs = {
14639         .gamma_set = intel_atomic_legacy_gamma_set,
14640         .set_config = drm_atomic_helper_set_config,
14641         .set_property = drm_atomic_helper_crtc_set_property,
14642         .destroy = intel_crtc_destroy,
14643         .page_flip = intel_crtc_page_flip,
14644         .atomic_duplicate_state = intel_crtc_duplicate_state,
14645         .atomic_destroy_state = intel_crtc_destroy_state,
14646 };
14647
14648 /**
14649  * intel_prepare_plane_fb - Prepare fb for usage on plane
14650  * @plane: drm plane to prepare for
14651  * @fb: framebuffer to prepare for presentation
14652  *
14653  * Prepares a framebuffer for usage on a display plane.  Generally this
14654  * involves pinning the underlying object and updating the frontbuffer tracking
14655  * bits.  Some older platforms need special physical address handling for
14656  * cursor planes.
14657  *
14658  * Must be called with struct_mutex held.
14659  *
14660  * Returns 0 on success, negative error code on failure.
14661  */
14662 int
14663 intel_prepare_plane_fb(struct drm_plane *plane,
14664                        struct drm_plane_state *new_state)
14665 {
14666         struct drm_device *dev = plane->dev;
14667         struct drm_i915_private *dev_priv = to_i915(dev);
14668         struct drm_framebuffer *fb = new_state->fb;
14669         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14670         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14671         struct reservation_object *resv;
14672         int ret = 0;
14673
14674         if (!obj && !old_obj)
14675                 return 0;
14676
14677         if (old_obj) {
14678                 struct drm_crtc_state *crtc_state =
14679                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14680
14681                 /* Big Hammer, we also need to ensure that any pending
14682                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14683                  * current scanout is retired before unpinning the old
14684                  * framebuffer. Note that we rely on userspace rendering
14685                  * into the buffer attached to the pipe they are waiting
14686                  * on. If not, userspace generates a GPU hang with IPEHR
14687                  * point to the MI_WAIT_FOR_EVENT.
14688                  *
14689                  * This should only fail upon a hung GPU, in which case we
14690                  * can safely continue.
14691                  */
14692                 if (needs_modeset(crtc_state))
14693                         ret = i915_gem_object_wait_rendering(old_obj, true);
14694                 if (ret) {
14695                         /* GPU hangs should have been swallowed by the wait */
14696                         WARN_ON(ret == -EIO);
14697                         return ret;
14698                 }
14699         }
14700
14701         if (!obj)
14702                 return 0;
14703
14704         /* For framebuffer backed by dmabuf, wait for fence */
14705         resv = i915_gem_object_get_dmabuf_resv(obj);
14706         if (resv) {
14707                 long lret;
14708
14709                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14710                                                            MAX_SCHEDULE_TIMEOUT);
14711                 if (lret == -ERESTARTSYS)
14712                         return lret;
14713
14714                 WARN(lret < 0, "waiting returns %li\n", lret);
14715         }
14716
14717         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14718             INTEL_INFO(dev)->cursor_needs_physical) {
14719                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14720                 ret = i915_gem_object_attach_phys(obj, align);
14721                 if (ret)
14722                         DRM_DEBUG_KMS("failed to attach phys object\n");
14723         } else {
14724                 struct i915_vma *vma;
14725
14726                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14727                 if (IS_ERR(vma))
14728                         ret = PTR_ERR(vma);
14729         }
14730
14731         if (ret == 0) {
14732                 to_intel_plane_state(new_state)->wait_req =
14733                         i915_gem_active_get(&obj->last_write,
14734                                             &obj->base.dev->struct_mutex);
14735         }
14736
14737         return ret;
14738 }
14739
14740 /**
14741  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14742  * @plane: drm plane to clean up for
14743  * @fb: old framebuffer that was on plane
14744  *
14745  * Cleans up a framebuffer that has just been removed from a plane.
14746  *
14747  * Must be called with struct_mutex held.
14748  */
14749 void
14750 intel_cleanup_plane_fb(struct drm_plane *plane,
14751                        struct drm_plane_state *old_state)
14752 {
14753         struct drm_device *dev = plane->dev;
14754         struct intel_plane_state *old_intel_state;
14755         struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14756         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14757         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14758
14759         old_intel_state = to_intel_plane_state(old_state);
14760
14761         if (!obj && !old_obj)
14762                 return;
14763
14764         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14765             !INTEL_INFO(dev)->cursor_needs_physical))
14766                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14767
14768         i915_gem_request_assign(&intel_state->wait_req, NULL);
14769         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14770 }
14771
14772 int
14773 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14774 {
14775         int max_scale;
14776         int crtc_clock, cdclk;
14777
14778         if (!intel_crtc || !crtc_state->base.enable)
14779                 return DRM_PLANE_HELPER_NO_SCALING;
14780
14781         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14782         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14783
14784         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14785                 return DRM_PLANE_HELPER_NO_SCALING;
14786
14787         /*
14788          * skl max scale is lower of:
14789          *    close to 3 but not 3, -1 is for that purpose
14790          *            or
14791          *    cdclk/crtc_clock
14792          */
14793         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14794
14795         return max_scale;
14796 }
14797
14798 static int
14799 intel_check_primary_plane(struct drm_plane *plane,
14800                           struct intel_crtc_state *crtc_state,
14801                           struct intel_plane_state *state)
14802 {
14803         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14804         struct drm_crtc *crtc = state->base.crtc;
14805         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14806         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14807         bool can_position = false;
14808         int ret;
14809
14810         if (INTEL_GEN(dev_priv) >= 9) {
14811                 /* use scaler when colorkey is not required */
14812                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14813                         min_scale = 1;
14814                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14815                 }
14816                 can_position = true;
14817         }
14818
14819         ret = drm_plane_helper_check_state(&state->base,
14820                                            &state->clip,
14821                                            min_scale, max_scale,
14822                                            can_position, true);
14823         if (ret)
14824                 return ret;
14825
14826         if (!state->base.fb)
14827                 return 0;
14828
14829         if (INTEL_GEN(dev_priv) >= 9) {
14830                 ret = skl_check_plane_surface(state);
14831                 if (ret)
14832                         return ret;
14833         }
14834
14835         return 0;
14836 }
14837
14838 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14839                                     struct drm_crtc_state *old_crtc_state)
14840 {
14841         struct drm_device *dev = crtc->dev;
14842         struct drm_i915_private *dev_priv = to_i915(dev);
14843         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14844         struct intel_crtc_state *old_intel_state =
14845                 to_intel_crtc_state(old_crtc_state);
14846         bool modeset = needs_modeset(crtc->state);
14847         enum pipe pipe = intel_crtc->pipe;
14848
14849         /* Perform vblank evasion around commit operation */
14850         intel_pipe_update_start(intel_crtc);
14851
14852         if (modeset)
14853                 return;
14854
14855         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14856                 intel_color_set_csc(crtc->state);
14857                 intel_color_load_luts(crtc->state);
14858         }
14859
14860         if (to_intel_crtc_state(crtc->state)->update_pipe)
14861                 intel_update_pipe_config(intel_crtc, old_intel_state);
14862         else if (INTEL_GEN(dev_priv) >= 9) {
14863                 skl_detach_scalers(intel_crtc);
14864
14865                 I915_WRITE(PIPE_WM_LINETIME(pipe),
14866                            dev_priv->wm.skl_hw.wm_linetime[pipe]);
14867         }
14868 }
14869
14870 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14871                                      struct drm_crtc_state *old_crtc_state)
14872 {
14873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14874
14875         intel_pipe_update_end(intel_crtc, NULL);
14876 }
14877
14878 /**
14879  * intel_plane_destroy - destroy a plane
14880  * @plane: plane to destroy
14881  *
14882  * Common destruction function for all types of planes (primary, cursor,
14883  * sprite).
14884  */
14885 void intel_plane_destroy(struct drm_plane *plane)
14886 {
14887         if (!plane)
14888                 return;
14889
14890         drm_plane_cleanup(plane);
14891         kfree(to_intel_plane(plane));
14892 }
14893
14894 const struct drm_plane_funcs intel_plane_funcs = {
14895         .update_plane = drm_atomic_helper_update_plane,
14896         .disable_plane = drm_atomic_helper_disable_plane,
14897         .destroy = intel_plane_destroy,
14898         .set_property = drm_atomic_helper_plane_set_property,
14899         .atomic_get_property = intel_plane_atomic_get_property,
14900         .atomic_set_property = intel_plane_atomic_set_property,
14901         .atomic_duplicate_state = intel_plane_duplicate_state,
14902         .atomic_destroy_state = intel_plane_destroy_state,
14903
14904 };
14905
14906 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14907                                                     int pipe)
14908 {
14909         struct drm_i915_private *dev_priv = to_i915(dev);
14910         struct intel_plane *primary = NULL;
14911         struct intel_plane_state *state = NULL;
14912         const uint32_t *intel_primary_formats;
14913         unsigned int num_formats;
14914         int ret;
14915
14916         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14917         if (!primary)
14918                 goto fail;
14919
14920         state = intel_create_plane_state(&primary->base);
14921         if (!state)
14922                 goto fail;
14923         primary->base.state = &state->base;
14924
14925         primary->can_scale = false;
14926         primary->max_downscale = 1;
14927         if (INTEL_INFO(dev)->gen >= 9) {
14928                 primary->can_scale = true;
14929                 state->scaler_id = -1;
14930         }
14931         primary->pipe = pipe;
14932         primary->plane = pipe;
14933         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14934         primary->check_plane = intel_check_primary_plane;
14935         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14936                 primary->plane = !pipe;
14937
14938         if (INTEL_INFO(dev)->gen >= 9) {
14939                 intel_primary_formats = skl_primary_formats;
14940                 num_formats = ARRAY_SIZE(skl_primary_formats);
14941
14942                 primary->update_plane = skylake_update_primary_plane;
14943                 primary->disable_plane = skylake_disable_primary_plane;
14944         } else if (HAS_PCH_SPLIT(dev_priv)) {
14945                 intel_primary_formats = i965_primary_formats;
14946                 num_formats = ARRAY_SIZE(i965_primary_formats);
14947
14948                 primary->update_plane = ironlake_update_primary_plane;
14949                 primary->disable_plane = i9xx_disable_primary_plane;
14950         } else if (INTEL_INFO(dev)->gen >= 4) {
14951                 intel_primary_formats = i965_primary_formats;
14952                 num_formats = ARRAY_SIZE(i965_primary_formats);
14953
14954                 primary->update_plane = i9xx_update_primary_plane;
14955                 primary->disable_plane = i9xx_disable_primary_plane;
14956         } else {
14957                 intel_primary_formats = i8xx_primary_formats;
14958                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14959
14960                 primary->update_plane = i9xx_update_primary_plane;
14961                 primary->disable_plane = i9xx_disable_primary_plane;
14962         }
14963
14964         if (INTEL_INFO(dev)->gen >= 9)
14965                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14966                                                &intel_plane_funcs,
14967                                                intel_primary_formats, num_formats,
14968                                                DRM_PLANE_TYPE_PRIMARY,
14969                                                "plane 1%c", pipe_name(pipe));
14970         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
14971                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14972                                                &intel_plane_funcs,
14973                                                intel_primary_formats, num_formats,
14974                                                DRM_PLANE_TYPE_PRIMARY,
14975                                                "primary %c", pipe_name(pipe));
14976         else
14977                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14978                                                &intel_plane_funcs,
14979                                                intel_primary_formats, num_formats,
14980                                                DRM_PLANE_TYPE_PRIMARY,
14981                                                "plane %c", plane_name(primary->plane));
14982         if (ret)
14983                 goto fail;
14984
14985         if (INTEL_INFO(dev)->gen >= 4)
14986                 intel_create_rotation_property(dev, primary);
14987
14988         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14989
14990         return &primary->base;
14991
14992 fail:
14993         kfree(state);
14994         kfree(primary);
14995
14996         return NULL;
14997 }
14998
14999 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
15000 {
15001         if (!dev->mode_config.rotation_property) {
15002                 unsigned long flags = DRM_ROTATE_0 |
15003                         DRM_ROTATE_180;
15004
15005                 if (INTEL_INFO(dev)->gen >= 9)
15006                         flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
15007
15008                 dev->mode_config.rotation_property =
15009                         drm_mode_create_rotation_property(dev, flags);
15010         }
15011         if (dev->mode_config.rotation_property)
15012                 drm_object_attach_property(&plane->base.base,
15013                                 dev->mode_config.rotation_property,
15014                                 plane->base.state->rotation);
15015 }
15016
15017 static int
15018 intel_check_cursor_plane(struct drm_plane *plane,
15019                          struct intel_crtc_state *crtc_state,
15020                          struct intel_plane_state *state)
15021 {
15022         struct drm_framebuffer *fb = state->base.fb;
15023         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15024         enum pipe pipe = to_intel_plane(plane)->pipe;
15025         unsigned stride;
15026         int ret;
15027
15028         ret = drm_plane_helper_check_state(&state->base,
15029                                            &state->clip,
15030                                            DRM_PLANE_HELPER_NO_SCALING,
15031                                            DRM_PLANE_HELPER_NO_SCALING,
15032                                            true, true);
15033         if (ret)
15034                 return ret;
15035
15036         /* if we want to turn off the cursor ignore width and height */
15037         if (!obj)
15038                 return 0;
15039
15040         /* Check for which cursor types we support */
15041         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15042                             state->base.crtc_h)) {
15043                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15044                           state->base.crtc_w, state->base.crtc_h);
15045                 return -EINVAL;
15046         }
15047
15048         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15049         if (obj->base.size < stride * state->base.crtc_h) {
15050                 DRM_DEBUG_KMS("buffer is too small\n");
15051                 return -ENOMEM;
15052         }
15053
15054         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15055                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15056                 return -EINVAL;
15057         }
15058
15059         /*
15060          * There's something wrong with the cursor on CHV pipe C.
15061          * If it straddles the left edge of the screen then
15062          * moving it away from the edge or disabling it often
15063          * results in a pipe underrun, and often that can lead to
15064          * dead pipe (constant underrun reported, and it scans
15065          * out just a solid color). To recover from that, the
15066          * display power well must be turned off and on again.
15067          * Refuse the put the cursor into that compromised position.
15068          */
15069         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15070             state->base.visible && state->base.crtc_x < 0) {
15071                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15072                 return -EINVAL;
15073         }
15074
15075         return 0;
15076 }
15077
15078 static void
15079 intel_disable_cursor_plane(struct drm_plane *plane,
15080                            struct drm_crtc *crtc)
15081 {
15082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15083
15084         intel_crtc->cursor_addr = 0;
15085         intel_crtc_update_cursor(crtc, NULL);
15086 }
15087
15088 static void
15089 intel_update_cursor_plane(struct drm_plane *plane,
15090                           const struct intel_crtc_state *crtc_state,
15091                           const struct intel_plane_state *state)
15092 {
15093         struct drm_crtc *crtc = crtc_state->base.crtc;
15094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15095         struct drm_device *dev = plane->dev;
15096         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15097         uint32_t addr;
15098
15099         if (!obj)
15100                 addr = 0;
15101         else if (!INTEL_INFO(dev)->cursor_needs_physical)
15102                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15103         else
15104                 addr = obj->phys_handle->busaddr;
15105
15106         intel_crtc->cursor_addr = addr;
15107         intel_crtc_update_cursor(crtc, state);
15108 }
15109
15110 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15111                                                    int pipe)
15112 {
15113         struct intel_plane *cursor = NULL;
15114         struct intel_plane_state *state = NULL;
15115         int ret;
15116
15117         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15118         if (!cursor)
15119                 goto fail;
15120
15121         state = intel_create_plane_state(&cursor->base);
15122         if (!state)
15123                 goto fail;
15124         cursor->base.state = &state->base;
15125
15126         cursor->can_scale = false;
15127         cursor->max_downscale = 1;
15128         cursor->pipe = pipe;
15129         cursor->plane = pipe;
15130         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15131         cursor->check_plane = intel_check_cursor_plane;
15132         cursor->update_plane = intel_update_cursor_plane;
15133         cursor->disable_plane = intel_disable_cursor_plane;
15134
15135         ret = drm_universal_plane_init(dev, &cursor->base, 0,
15136                                        &intel_plane_funcs,
15137                                        intel_cursor_formats,
15138                                        ARRAY_SIZE(intel_cursor_formats),
15139                                        DRM_PLANE_TYPE_CURSOR,
15140                                        "cursor %c", pipe_name(pipe));
15141         if (ret)
15142                 goto fail;
15143
15144         if (INTEL_INFO(dev)->gen >= 4) {
15145                 if (!dev->mode_config.rotation_property)
15146                         dev->mode_config.rotation_property =
15147                                 drm_mode_create_rotation_property(dev,
15148                                                         DRM_ROTATE_0 |
15149                                                         DRM_ROTATE_180);
15150                 if (dev->mode_config.rotation_property)
15151                         drm_object_attach_property(&cursor->base.base,
15152                                 dev->mode_config.rotation_property,
15153                                 state->base.rotation);
15154         }
15155
15156         if (INTEL_INFO(dev)->gen >=9)
15157                 state->scaler_id = -1;
15158
15159         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15160
15161         return &cursor->base;
15162
15163 fail:
15164         kfree(state);
15165         kfree(cursor);
15166
15167         return NULL;
15168 }
15169
15170 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15171         struct intel_crtc_state *crtc_state)
15172 {
15173         int i;
15174         struct intel_scaler *intel_scaler;
15175         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15176
15177         for (i = 0; i < intel_crtc->num_scalers; i++) {
15178                 intel_scaler = &scaler_state->scalers[i];
15179                 intel_scaler->in_use = 0;
15180                 intel_scaler->mode = PS_SCALER_MODE_DYN;
15181         }
15182
15183         scaler_state->scaler_id = -1;
15184 }
15185
15186 static void intel_crtc_init(struct drm_device *dev, int pipe)
15187 {
15188         struct drm_i915_private *dev_priv = to_i915(dev);
15189         struct intel_crtc *intel_crtc;
15190         struct intel_crtc_state *crtc_state = NULL;
15191         struct drm_plane *primary = NULL;
15192         struct drm_plane *cursor = NULL;
15193         int ret;
15194
15195         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15196         if (intel_crtc == NULL)
15197                 return;
15198
15199         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15200         if (!crtc_state)
15201                 goto fail;
15202         intel_crtc->config = crtc_state;
15203         intel_crtc->base.state = &crtc_state->base;
15204         crtc_state->base.crtc = &intel_crtc->base;
15205
15206         /* initialize shared scalers */
15207         if (INTEL_INFO(dev)->gen >= 9) {
15208                 if (pipe == PIPE_C)
15209                         intel_crtc->num_scalers = 1;
15210                 else
15211                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15212
15213                 skl_init_scalers(dev, intel_crtc, crtc_state);
15214         }
15215
15216         primary = intel_primary_plane_create(dev, pipe);
15217         if (!primary)
15218                 goto fail;
15219
15220         cursor = intel_cursor_plane_create(dev, pipe);
15221         if (!cursor)
15222                 goto fail;
15223
15224         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15225                                         cursor, &intel_crtc_funcs,
15226                                         "pipe %c", pipe_name(pipe));
15227         if (ret)
15228                 goto fail;
15229
15230         /*
15231          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15232          * is hooked to pipe B. Hence we want plane A feeding pipe B.
15233          */
15234         intel_crtc->pipe = pipe;
15235         intel_crtc->plane = pipe;
15236         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15237                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15238                 intel_crtc->plane = !pipe;
15239         }
15240
15241         intel_crtc->cursor_base = ~0;
15242         intel_crtc->cursor_cntl = ~0;
15243         intel_crtc->cursor_size = ~0;
15244
15245         intel_crtc->wm.cxsr_allowed = true;
15246
15247         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15248                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15249         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15250         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15251
15252         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15253
15254         intel_color_init(&intel_crtc->base);
15255
15256         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15257         return;
15258
15259 fail:
15260         intel_plane_destroy(primary);
15261         intel_plane_destroy(cursor);
15262         kfree(crtc_state);
15263         kfree(intel_crtc);
15264 }
15265
15266 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15267 {
15268         struct drm_encoder *encoder = connector->base.encoder;
15269         struct drm_device *dev = connector->base.dev;
15270
15271         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15272
15273         if (!encoder || WARN_ON(!encoder->crtc))
15274                 return INVALID_PIPE;
15275
15276         return to_intel_crtc(encoder->crtc)->pipe;
15277 }
15278
15279 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15280                                 struct drm_file *file)
15281 {
15282         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15283         struct drm_crtc *drmmode_crtc;
15284         struct intel_crtc *crtc;
15285
15286         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15287         if (!drmmode_crtc)
15288                 return -ENOENT;
15289
15290         crtc = to_intel_crtc(drmmode_crtc);
15291         pipe_from_crtc_id->pipe = crtc->pipe;
15292
15293         return 0;
15294 }
15295
15296 static int intel_encoder_clones(struct intel_encoder *encoder)
15297 {
15298         struct drm_device *dev = encoder->base.dev;
15299         struct intel_encoder *source_encoder;
15300         int index_mask = 0;
15301         int entry = 0;
15302
15303         for_each_intel_encoder(dev, source_encoder) {
15304                 if (encoders_cloneable(encoder, source_encoder))
15305                         index_mask |= (1 << entry);
15306
15307                 entry++;
15308         }
15309
15310         return index_mask;
15311 }
15312
15313 static bool has_edp_a(struct drm_device *dev)
15314 {
15315         struct drm_i915_private *dev_priv = to_i915(dev);
15316
15317         if (!IS_MOBILE(dev))
15318                 return false;
15319
15320         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15321                 return false;
15322
15323         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15324                 return false;
15325
15326         return true;
15327 }
15328
15329 static bool intel_crt_present(struct drm_device *dev)
15330 {
15331         struct drm_i915_private *dev_priv = to_i915(dev);
15332
15333         if (INTEL_INFO(dev)->gen >= 9)
15334                 return false;
15335
15336         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15337                 return false;
15338
15339         if (IS_CHERRYVIEW(dev_priv))
15340                 return false;
15341
15342         if (HAS_PCH_LPT_H(dev_priv) &&
15343             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15344                 return false;
15345
15346         /* DDI E can't be used if DDI A requires 4 lanes */
15347         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15348                 return false;
15349
15350         if (!dev_priv->vbt.int_crt_support)
15351                 return false;
15352
15353         return true;
15354 }
15355
15356 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15357 {
15358         int pps_num;
15359         int pps_idx;
15360
15361         if (HAS_DDI(dev_priv))
15362                 return;
15363         /*
15364          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15365          * everywhere where registers can be write protected.
15366          */
15367         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15368                 pps_num = 2;
15369         else
15370                 pps_num = 1;
15371
15372         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15373                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15374
15375                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15376                 I915_WRITE(PP_CONTROL(pps_idx), val);
15377         }
15378 }
15379
15380 static void intel_pps_init(struct drm_i915_private *dev_priv)
15381 {
15382         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15383                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15384         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15385                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15386         else
15387                 dev_priv->pps_mmio_base = PPS_BASE;
15388
15389         intel_pps_unlock_regs_wa(dev_priv);
15390 }
15391
15392 static void intel_setup_outputs(struct drm_device *dev)
15393 {
15394         struct drm_i915_private *dev_priv = to_i915(dev);
15395         struct intel_encoder *encoder;
15396         bool dpd_is_edp = false;
15397
15398         intel_pps_init(dev_priv);
15399
15400         /*
15401          * intel_edp_init_connector() depends on this completing first, to
15402          * prevent the registeration of both eDP and LVDS and the incorrect
15403          * sharing of the PPS.
15404          */
15405         intel_lvds_init(dev);
15406
15407         if (intel_crt_present(dev))
15408                 intel_crt_init(dev);
15409
15410         if (IS_BROXTON(dev_priv)) {
15411                 /*
15412                  * FIXME: Broxton doesn't support port detection via the
15413                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15414                  * detect the ports.
15415                  */
15416                 intel_ddi_init(dev, PORT_A);
15417                 intel_ddi_init(dev, PORT_B);
15418                 intel_ddi_init(dev, PORT_C);
15419
15420                 intel_dsi_init(dev);
15421         } else if (HAS_DDI(dev_priv)) {
15422                 int found;
15423
15424                 /*
15425                  * Haswell uses DDI functions to detect digital outputs.
15426                  * On SKL pre-D0 the strap isn't connected, so we assume
15427                  * it's there.
15428                  */
15429                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15430                 /* WaIgnoreDDIAStrap: skl */
15431                 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15432                         intel_ddi_init(dev, PORT_A);
15433
15434                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15435                  * register */
15436                 found = I915_READ(SFUSE_STRAP);
15437
15438                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15439                         intel_ddi_init(dev, PORT_B);
15440                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15441                         intel_ddi_init(dev, PORT_C);
15442                 if (found & SFUSE_STRAP_DDID_DETECTED)
15443                         intel_ddi_init(dev, PORT_D);
15444                 /*
15445                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15446                  */
15447                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15448                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15449                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15450                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15451                         intel_ddi_init(dev, PORT_E);
15452
15453         } else if (HAS_PCH_SPLIT(dev_priv)) {
15454                 int found;
15455                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15456
15457                 if (has_edp_a(dev))
15458                         intel_dp_init(dev, DP_A, PORT_A);
15459
15460                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15461                         /* PCH SDVOB multiplex with HDMIB */
15462                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15463                         if (!found)
15464                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15465                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15466                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15467                 }
15468
15469                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15470                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15471
15472                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15473                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15474
15475                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15476                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15477
15478                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15479                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15480         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15481                 bool has_edp, has_port;
15482
15483                 /*
15484                  * The DP_DETECTED bit is the latched state of the DDC
15485                  * SDA pin at boot. However since eDP doesn't require DDC
15486                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15487                  * eDP ports may have been muxed to an alternate function.
15488                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15489                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15490                  * detect eDP ports.
15491                  *
15492                  * Sadly the straps seem to be missing sometimes even for HDMI
15493                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15494                  * and VBT for the presence of the port. Additionally we can't
15495                  * trust the port type the VBT declares as we've seen at least
15496                  * HDMI ports that the VBT claim are DP or eDP.
15497                  */
15498                 has_edp = intel_dp_is_edp(dev, PORT_B);
15499                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15500                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15501                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15502                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15503                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15504
15505                 has_edp = intel_dp_is_edp(dev, PORT_C);
15506                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15507                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15508                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15509                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15510                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15511
15512                 if (IS_CHERRYVIEW(dev_priv)) {
15513                         /*
15514                          * eDP not supported on port D,
15515                          * so no need to worry about it
15516                          */
15517                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15518                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15519                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15520                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15521                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15522                 }
15523
15524                 intel_dsi_init(dev);
15525         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15526                 bool found = false;
15527
15528                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15529                         DRM_DEBUG_KMS("probing SDVOB\n");
15530                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15531                         if (!found && IS_G4X(dev_priv)) {
15532                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15533                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15534                         }
15535
15536                         if (!found && IS_G4X(dev_priv))
15537                                 intel_dp_init(dev, DP_B, PORT_B);
15538                 }
15539
15540                 /* Before G4X SDVOC doesn't have its own detect register */
15541
15542                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15543                         DRM_DEBUG_KMS("probing SDVOC\n");
15544                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15545                 }
15546
15547                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15548
15549                         if (IS_G4X(dev_priv)) {
15550                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15551                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15552                         }
15553                         if (IS_G4X(dev_priv))
15554                                 intel_dp_init(dev, DP_C, PORT_C);
15555                 }
15556
15557                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15558                         intel_dp_init(dev, DP_D, PORT_D);
15559         } else if (IS_GEN2(dev))
15560                 intel_dvo_init(dev);
15561
15562         if (SUPPORTS_TV(dev))
15563                 intel_tv_init(dev);
15564
15565         intel_psr_init(dev);
15566
15567         for_each_intel_encoder(dev, encoder) {
15568                 encoder->base.possible_crtcs = encoder->crtc_mask;
15569                 encoder->base.possible_clones =
15570                         intel_encoder_clones(encoder);
15571         }
15572
15573         intel_init_pch_refclk(dev);
15574
15575         drm_helper_move_panel_connectors_to_head(dev);
15576 }
15577
15578 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15579 {
15580         struct drm_device *dev = fb->dev;
15581         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15582
15583         drm_framebuffer_cleanup(fb);
15584         mutex_lock(&dev->struct_mutex);
15585         WARN_ON(!intel_fb->obj->framebuffer_references--);
15586         i915_gem_object_put(intel_fb->obj);
15587         mutex_unlock(&dev->struct_mutex);
15588         kfree(intel_fb);
15589 }
15590
15591 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15592                                                 struct drm_file *file,
15593                                                 unsigned int *handle)
15594 {
15595         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15596         struct drm_i915_gem_object *obj = intel_fb->obj;
15597
15598         if (obj->userptr.mm) {
15599                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15600                 return -EINVAL;
15601         }
15602
15603         return drm_gem_handle_create(file, &obj->base, handle);
15604 }
15605
15606 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15607                                         struct drm_file *file,
15608                                         unsigned flags, unsigned color,
15609                                         struct drm_clip_rect *clips,
15610                                         unsigned num_clips)
15611 {
15612         struct drm_device *dev = fb->dev;
15613         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15614         struct drm_i915_gem_object *obj = intel_fb->obj;
15615
15616         mutex_lock(&dev->struct_mutex);
15617         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15618         mutex_unlock(&dev->struct_mutex);
15619
15620         return 0;
15621 }
15622
15623 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15624         .destroy = intel_user_framebuffer_destroy,
15625         .create_handle = intel_user_framebuffer_create_handle,
15626         .dirty = intel_user_framebuffer_dirty,
15627 };
15628
15629 static
15630 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15631                          uint64_t fb_modifier, uint32_t pixel_format)
15632 {
15633         u32 gen = INTEL_INFO(dev_priv)->gen;
15634
15635         if (gen >= 9) {
15636                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15637
15638                 /* "The stride in bytes must not exceed the of the size of 8K
15639                  *  pixels and 32K bytes."
15640                  */
15641                 return min(8192 * cpp, 32768);
15642         } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15643                    !IS_CHERRYVIEW(dev_priv)) {
15644                 return 32*1024;
15645         } else if (gen >= 4) {
15646                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15647                         return 16*1024;
15648                 else
15649                         return 32*1024;
15650         } else if (gen >= 3) {
15651                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15652                         return 8*1024;
15653                 else
15654                         return 16*1024;
15655         } else {
15656                 /* XXX DSPC is limited to 4k tiled */
15657                 return 8*1024;
15658         }
15659 }
15660
15661 static int intel_framebuffer_init(struct drm_device *dev,
15662                                   struct intel_framebuffer *intel_fb,
15663                                   struct drm_mode_fb_cmd2 *mode_cmd,
15664                                   struct drm_i915_gem_object *obj)
15665 {
15666         struct drm_i915_private *dev_priv = to_i915(dev);
15667         unsigned int tiling = i915_gem_object_get_tiling(obj);
15668         int ret;
15669         u32 pitch_limit, stride_alignment;
15670         char *format_name;
15671
15672         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15673
15674         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15675                 /*
15676                  * If there's a fence, enforce that
15677                  * the fb modifier and tiling mode match.
15678                  */
15679                 if (tiling != I915_TILING_NONE &&
15680                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15681                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15682                         return -EINVAL;
15683                 }
15684         } else {
15685                 if (tiling == I915_TILING_X) {
15686                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15687                 } else if (tiling == I915_TILING_Y) {
15688                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15689                         return -EINVAL;
15690                 }
15691         }
15692
15693         /* Passed in modifier sanity checking. */
15694         switch (mode_cmd->modifier[0]) {
15695         case I915_FORMAT_MOD_Y_TILED:
15696         case I915_FORMAT_MOD_Yf_TILED:
15697                 if (INTEL_INFO(dev)->gen < 9) {
15698                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15699                                   mode_cmd->modifier[0]);
15700                         return -EINVAL;
15701                 }
15702         case DRM_FORMAT_MOD_NONE:
15703         case I915_FORMAT_MOD_X_TILED:
15704                 break;
15705         default:
15706                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15707                           mode_cmd->modifier[0]);
15708                 return -EINVAL;
15709         }
15710
15711         /*
15712          * gen2/3 display engine uses the fence if present,
15713          * so the tiling mode must match the fb modifier exactly.
15714          */
15715         if (INTEL_INFO(dev_priv)->gen < 4 &&
15716             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15717                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15718                 return -EINVAL;
15719         }
15720
15721         stride_alignment = intel_fb_stride_alignment(dev_priv,
15722                                                      mode_cmd->modifier[0],
15723                                                      mode_cmd->pixel_format);
15724         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15725                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15726                           mode_cmd->pitches[0], stride_alignment);
15727                 return -EINVAL;
15728         }
15729
15730         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15731                                            mode_cmd->pixel_format);
15732         if (mode_cmd->pitches[0] > pitch_limit) {
15733                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15734                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15735                           "tiled" : "linear",
15736                           mode_cmd->pitches[0], pitch_limit);
15737                 return -EINVAL;
15738         }
15739
15740         /*
15741          * If there's a fence, enforce that
15742          * the fb pitch and fence stride match.
15743          */
15744         if (tiling != I915_TILING_NONE &&
15745             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15746                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15747                           mode_cmd->pitches[0],
15748                           i915_gem_object_get_stride(obj));
15749                 return -EINVAL;
15750         }
15751
15752         /* Reject formats not supported by any plane early. */
15753         switch (mode_cmd->pixel_format) {
15754         case DRM_FORMAT_C8:
15755         case DRM_FORMAT_RGB565:
15756         case DRM_FORMAT_XRGB8888:
15757         case DRM_FORMAT_ARGB8888:
15758                 break;
15759         case DRM_FORMAT_XRGB1555:
15760                 if (INTEL_INFO(dev)->gen > 3) {
15761                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15762                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15763                         kfree(format_name);
15764                         return -EINVAL;
15765                 }
15766                 break;
15767         case DRM_FORMAT_ABGR8888:
15768                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15769                     INTEL_INFO(dev)->gen < 9) {
15770                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15771                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15772                         kfree(format_name);
15773                         return -EINVAL;
15774                 }
15775                 break;
15776         case DRM_FORMAT_XBGR8888:
15777         case DRM_FORMAT_XRGB2101010:
15778         case DRM_FORMAT_XBGR2101010:
15779                 if (INTEL_INFO(dev)->gen < 4) {
15780                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15781                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15782                         kfree(format_name);
15783                         return -EINVAL;
15784                 }
15785                 break;
15786         case DRM_FORMAT_ABGR2101010:
15787                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15788                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15789                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15790                         kfree(format_name);
15791                         return -EINVAL;
15792                 }
15793                 break;
15794         case DRM_FORMAT_YUYV:
15795         case DRM_FORMAT_UYVY:
15796         case DRM_FORMAT_YVYU:
15797         case DRM_FORMAT_VYUY:
15798                 if (INTEL_INFO(dev)->gen < 5) {
15799                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15800                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15801                         kfree(format_name);
15802                         return -EINVAL;
15803                 }
15804                 break;
15805         default:
15806                 format_name = drm_get_format_name(mode_cmd->pixel_format);
15807                 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15808                 kfree(format_name);
15809                 return -EINVAL;
15810         }
15811
15812         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15813         if (mode_cmd->offsets[0] != 0)
15814                 return -EINVAL;
15815
15816         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15817         intel_fb->obj = obj;
15818
15819         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15820         if (ret)
15821                 return ret;
15822
15823         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15824         if (ret) {
15825                 DRM_ERROR("framebuffer init failed %d\n", ret);
15826                 return ret;
15827         }
15828
15829         intel_fb->obj->framebuffer_references++;
15830
15831         return 0;
15832 }
15833
15834 static struct drm_framebuffer *
15835 intel_user_framebuffer_create(struct drm_device *dev,
15836                               struct drm_file *filp,
15837                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15838 {
15839         struct drm_framebuffer *fb;
15840         struct drm_i915_gem_object *obj;
15841         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15842
15843         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15844         if (!obj)
15845                 return ERR_PTR(-ENOENT);
15846
15847         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15848         if (IS_ERR(fb))
15849                 i915_gem_object_put_unlocked(obj);
15850
15851         return fb;
15852 }
15853
15854 static const struct drm_mode_config_funcs intel_mode_funcs = {
15855         .fb_create = intel_user_framebuffer_create,
15856         .output_poll_changed = intel_fbdev_output_poll_changed,
15857         .atomic_check = intel_atomic_check,
15858         .atomic_commit = intel_atomic_commit,
15859         .atomic_state_alloc = intel_atomic_state_alloc,
15860         .atomic_state_clear = intel_atomic_state_clear,
15861 };
15862
15863 /**
15864  * intel_init_display_hooks - initialize the display modesetting hooks
15865  * @dev_priv: device private
15866  */
15867 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15868 {
15869         if (INTEL_INFO(dev_priv)->gen >= 9) {
15870                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15871                 dev_priv->display.get_initial_plane_config =
15872                         skylake_get_initial_plane_config;
15873                 dev_priv->display.crtc_compute_clock =
15874                         haswell_crtc_compute_clock;
15875                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15876                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15877         } else if (HAS_DDI(dev_priv)) {
15878                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15879                 dev_priv->display.get_initial_plane_config =
15880                         ironlake_get_initial_plane_config;
15881                 dev_priv->display.crtc_compute_clock =
15882                         haswell_crtc_compute_clock;
15883                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15884                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15885         } else if (HAS_PCH_SPLIT(dev_priv)) {
15886                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15887                 dev_priv->display.get_initial_plane_config =
15888                         ironlake_get_initial_plane_config;
15889                 dev_priv->display.crtc_compute_clock =
15890                         ironlake_crtc_compute_clock;
15891                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15892                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15893         } else if (IS_CHERRYVIEW(dev_priv)) {
15894                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15895                 dev_priv->display.get_initial_plane_config =
15896                         i9xx_get_initial_plane_config;
15897                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15898                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15899                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15900         } else if (IS_VALLEYVIEW(dev_priv)) {
15901                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15902                 dev_priv->display.get_initial_plane_config =
15903                         i9xx_get_initial_plane_config;
15904                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15905                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15906                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15907         } else if (IS_G4X(dev_priv)) {
15908                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15909                 dev_priv->display.get_initial_plane_config =
15910                         i9xx_get_initial_plane_config;
15911                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15912                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15913                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15914         } else if (IS_PINEVIEW(dev_priv)) {
15915                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15916                 dev_priv->display.get_initial_plane_config =
15917                         i9xx_get_initial_plane_config;
15918                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15919                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15920                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15921         } else if (!IS_GEN2(dev_priv)) {
15922                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15923                 dev_priv->display.get_initial_plane_config =
15924                         i9xx_get_initial_plane_config;
15925                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15926                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15927                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15928         } else {
15929                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15930                 dev_priv->display.get_initial_plane_config =
15931                         i9xx_get_initial_plane_config;
15932                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15933                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15934                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15935         }
15936
15937         /* Returns the core display clock speed */
15938         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15939                 dev_priv->display.get_display_clock_speed =
15940                         skylake_get_display_clock_speed;
15941         else if (IS_BROXTON(dev_priv))
15942                 dev_priv->display.get_display_clock_speed =
15943                         broxton_get_display_clock_speed;
15944         else if (IS_BROADWELL(dev_priv))
15945                 dev_priv->display.get_display_clock_speed =
15946                         broadwell_get_display_clock_speed;
15947         else if (IS_HASWELL(dev_priv))
15948                 dev_priv->display.get_display_clock_speed =
15949                         haswell_get_display_clock_speed;
15950         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15951                 dev_priv->display.get_display_clock_speed =
15952                         valleyview_get_display_clock_speed;
15953         else if (IS_GEN5(dev_priv))
15954                 dev_priv->display.get_display_clock_speed =
15955                         ilk_get_display_clock_speed;
15956         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15957                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15958                 dev_priv->display.get_display_clock_speed =
15959                         i945_get_display_clock_speed;
15960         else if (IS_GM45(dev_priv))
15961                 dev_priv->display.get_display_clock_speed =
15962                         gm45_get_display_clock_speed;
15963         else if (IS_CRESTLINE(dev_priv))
15964                 dev_priv->display.get_display_clock_speed =
15965                         i965gm_get_display_clock_speed;
15966         else if (IS_PINEVIEW(dev_priv))
15967                 dev_priv->display.get_display_clock_speed =
15968                         pnv_get_display_clock_speed;
15969         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15970                 dev_priv->display.get_display_clock_speed =
15971                         g33_get_display_clock_speed;
15972         else if (IS_I915G(dev_priv))
15973                 dev_priv->display.get_display_clock_speed =
15974                         i915_get_display_clock_speed;
15975         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15976                 dev_priv->display.get_display_clock_speed =
15977                         i9xx_misc_get_display_clock_speed;
15978         else if (IS_I915GM(dev_priv))
15979                 dev_priv->display.get_display_clock_speed =
15980                         i915gm_get_display_clock_speed;
15981         else if (IS_I865G(dev_priv))
15982                 dev_priv->display.get_display_clock_speed =
15983                         i865_get_display_clock_speed;
15984         else if (IS_I85X(dev_priv))
15985                 dev_priv->display.get_display_clock_speed =
15986                         i85x_get_display_clock_speed;
15987         else { /* 830 */
15988                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15989                 dev_priv->display.get_display_clock_speed =
15990                         i830_get_display_clock_speed;
15991         }
15992
15993         if (IS_GEN5(dev_priv)) {
15994                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15995         } else if (IS_GEN6(dev_priv)) {
15996                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15997         } else if (IS_IVYBRIDGE(dev_priv)) {
15998                 /* FIXME: detect B0+ stepping and use auto training */
15999                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16000         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16001                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16002         }
16003
16004         if (IS_BROADWELL(dev_priv)) {
16005                 dev_priv->display.modeset_commit_cdclk =
16006                         broadwell_modeset_commit_cdclk;
16007                 dev_priv->display.modeset_calc_cdclk =
16008                         broadwell_modeset_calc_cdclk;
16009         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16010                 dev_priv->display.modeset_commit_cdclk =
16011                         valleyview_modeset_commit_cdclk;
16012                 dev_priv->display.modeset_calc_cdclk =
16013                         valleyview_modeset_calc_cdclk;
16014         } else if (IS_BROXTON(dev_priv)) {
16015                 dev_priv->display.modeset_commit_cdclk =
16016                         bxt_modeset_commit_cdclk;
16017                 dev_priv->display.modeset_calc_cdclk =
16018                         bxt_modeset_calc_cdclk;
16019         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16020                 dev_priv->display.modeset_commit_cdclk =
16021                         skl_modeset_commit_cdclk;
16022                 dev_priv->display.modeset_calc_cdclk =
16023                         skl_modeset_calc_cdclk;
16024         }
16025
16026         if (dev_priv->info.gen >= 9)
16027                 dev_priv->display.update_crtcs = skl_update_crtcs;
16028         else
16029                 dev_priv->display.update_crtcs = intel_update_crtcs;
16030
16031         switch (INTEL_INFO(dev_priv)->gen) {
16032         case 2:
16033                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16034                 break;
16035
16036         case 3:
16037                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16038                 break;
16039
16040         case 4:
16041         case 5:
16042                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16043                 break;
16044
16045         case 6:
16046                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16047                 break;
16048         case 7:
16049         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16050                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16051                 break;
16052         case 9:
16053                 /* Drop through - unsupported since execlist only. */
16054         default:
16055                 /* Default just returns -ENODEV to indicate unsupported */
16056                 dev_priv->display.queue_flip = intel_default_queue_flip;
16057         }
16058 }
16059
16060 /*
16061  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16062  * resume, or other times.  This quirk makes sure that's the case for
16063  * affected systems.
16064  */
16065 static void quirk_pipea_force(struct drm_device *dev)
16066 {
16067         struct drm_i915_private *dev_priv = to_i915(dev);
16068
16069         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16070         DRM_INFO("applying pipe a force quirk\n");
16071 }
16072
16073 static void quirk_pipeb_force(struct drm_device *dev)
16074 {
16075         struct drm_i915_private *dev_priv = to_i915(dev);
16076
16077         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16078         DRM_INFO("applying pipe b force quirk\n");
16079 }
16080
16081 /*
16082  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16083  */
16084 static void quirk_ssc_force_disable(struct drm_device *dev)
16085 {
16086         struct drm_i915_private *dev_priv = to_i915(dev);
16087         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16088         DRM_INFO("applying lvds SSC disable quirk\n");
16089 }
16090
16091 /*
16092  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16093  * brightness value
16094  */
16095 static void quirk_invert_brightness(struct drm_device *dev)
16096 {
16097         struct drm_i915_private *dev_priv = to_i915(dev);
16098         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16099         DRM_INFO("applying inverted panel brightness quirk\n");
16100 }
16101
16102 /* Some VBT's incorrectly indicate no backlight is present */
16103 static void quirk_backlight_present(struct drm_device *dev)
16104 {
16105         struct drm_i915_private *dev_priv = to_i915(dev);
16106         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16107         DRM_INFO("applying backlight present quirk\n");
16108 }
16109
16110 struct intel_quirk {
16111         int device;
16112         int subsystem_vendor;
16113         int subsystem_device;
16114         void (*hook)(struct drm_device *dev);
16115 };
16116
16117 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16118 struct intel_dmi_quirk {
16119         void (*hook)(struct drm_device *dev);
16120         const struct dmi_system_id (*dmi_id_list)[];
16121 };
16122
16123 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16124 {
16125         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16126         return 1;
16127 }
16128
16129 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16130         {
16131                 .dmi_id_list = &(const struct dmi_system_id[]) {
16132                         {
16133                                 .callback = intel_dmi_reverse_brightness,
16134                                 .ident = "NCR Corporation",
16135                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16136                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16137                                 },
16138                         },
16139                         { }  /* terminating entry */
16140                 },
16141                 .hook = quirk_invert_brightness,
16142         },
16143 };
16144
16145 static struct intel_quirk intel_quirks[] = {
16146         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16147         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16148
16149         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16150         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16151
16152         /* 830 needs to leave pipe A & dpll A up */
16153         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16154
16155         /* 830 needs to leave pipe B & dpll B up */
16156         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16157
16158         /* Lenovo U160 cannot use SSC on LVDS */
16159         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16160
16161         /* Sony Vaio Y cannot use SSC on LVDS */
16162         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16163
16164         /* Acer Aspire 5734Z must invert backlight brightness */
16165         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16166
16167         /* Acer/eMachines G725 */
16168         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16169
16170         /* Acer/eMachines e725 */
16171         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16172
16173         /* Acer/Packard Bell NCL20 */
16174         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16175
16176         /* Acer Aspire 4736Z */
16177         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16178
16179         /* Acer Aspire 5336 */
16180         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16181
16182         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16183         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16184
16185         /* Acer C720 Chromebook (Core i3 4005U) */
16186         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16187
16188         /* Apple Macbook 2,1 (Core 2 T7400) */
16189         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16190
16191         /* Apple Macbook 4,1 */
16192         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16193
16194         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16195         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16196
16197         /* HP Chromebook 14 (Celeron 2955U) */
16198         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16199
16200         /* Dell Chromebook 11 */
16201         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16202
16203         /* Dell Chromebook 11 (2015 version) */
16204         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16205 };
16206
16207 static void intel_init_quirks(struct drm_device *dev)
16208 {
16209         struct pci_dev *d = dev->pdev;
16210         int i;
16211
16212         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16213                 struct intel_quirk *q = &intel_quirks[i];
16214
16215                 if (d->device == q->device &&
16216                     (d->subsystem_vendor == q->subsystem_vendor ||
16217                      q->subsystem_vendor == PCI_ANY_ID) &&
16218                     (d->subsystem_device == q->subsystem_device ||
16219                      q->subsystem_device == PCI_ANY_ID))
16220                         q->hook(dev);
16221         }
16222         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16223                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16224                         intel_dmi_quirks[i].hook(dev);
16225         }
16226 }
16227
16228 /* Disable the VGA plane that we never use */
16229 static void i915_disable_vga(struct drm_device *dev)
16230 {
16231         struct drm_i915_private *dev_priv = to_i915(dev);
16232         struct pci_dev *pdev = dev_priv->drm.pdev;
16233         u8 sr1;
16234         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16235
16236         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16237         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16238         outb(SR01, VGA_SR_INDEX);
16239         sr1 = inb(VGA_SR_DATA);
16240         outb(sr1 | 1<<5, VGA_SR_DATA);
16241         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16242         udelay(300);
16243
16244         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16245         POSTING_READ(vga_reg);
16246 }
16247
16248 void intel_modeset_init_hw(struct drm_device *dev)
16249 {
16250         struct drm_i915_private *dev_priv = to_i915(dev);
16251
16252         intel_update_cdclk(dev);
16253
16254         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16255
16256         intel_init_clock_gating(dev);
16257 }
16258
16259 /*
16260  * Calculate what we think the watermarks should be for the state we've read
16261  * out of the hardware and then immediately program those watermarks so that
16262  * we ensure the hardware settings match our internal state.
16263  *
16264  * We can calculate what we think WM's should be by creating a duplicate of the
16265  * current state (which was constructed during hardware readout) and running it
16266  * through the atomic check code to calculate new watermark values in the
16267  * state object.
16268  */
16269 static void sanitize_watermarks(struct drm_device *dev)
16270 {
16271         struct drm_i915_private *dev_priv = to_i915(dev);
16272         struct drm_atomic_state *state;
16273         struct drm_crtc *crtc;
16274         struct drm_crtc_state *cstate;
16275         struct drm_modeset_acquire_ctx ctx;
16276         int ret;
16277         int i;
16278
16279         /* Only supported on platforms that use atomic watermark design */
16280         if (!dev_priv->display.optimize_watermarks)
16281                 return;
16282
16283         /*
16284          * We need to hold connection_mutex before calling duplicate_state so
16285          * that the connector loop is protected.
16286          */
16287         drm_modeset_acquire_init(&ctx, 0);
16288 retry:
16289         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16290         if (ret == -EDEADLK) {
16291                 drm_modeset_backoff(&ctx);
16292                 goto retry;
16293         } else if (WARN_ON(ret)) {
16294                 goto fail;
16295         }
16296
16297         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16298         if (WARN_ON(IS_ERR(state)))
16299                 goto fail;
16300
16301         /*
16302          * Hardware readout is the only time we don't want to calculate
16303          * intermediate watermarks (since we don't trust the current
16304          * watermarks).
16305          */
16306         to_intel_atomic_state(state)->skip_intermediate_wm = true;
16307
16308         ret = intel_atomic_check(dev, state);
16309         if (ret) {
16310                 /*
16311                  * If we fail here, it means that the hardware appears to be
16312                  * programmed in a way that shouldn't be possible, given our
16313                  * understanding of watermark requirements.  This might mean a
16314                  * mistake in the hardware readout code or a mistake in the
16315                  * watermark calculations for a given platform.  Raise a WARN
16316                  * so that this is noticeable.
16317                  *
16318                  * If this actually happens, we'll have to just leave the
16319                  * BIOS-programmed watermarks untouched and hope for the best.
16320                  */
16321                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16322                 goto fail;
16323         }
16324
16325         /* Write calculated watermark values back */
16326         for_each_crtc_in_state(state, crtc, cstate, i) {
16327                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16328
16329                 cs->wm.need_postvbl_update = true;
16330                 dev_priv->display.optimize_watermarks(cs);
16331         }
16332
16333         drm_atomic_state_free(state);
16334 fail:
16335         drm_modeset_drop_locks(&ctx);
16336         drm_modeset_acquire_fini(&ctx);
16337 }
16338
16339 void intel_modeset_init(struct drm_device *dev)
16340 {
16341         struct drm_i915_private *dev_priv = to_i915(dev);
16342         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16343         int sprite, ret;
16344         enum pipe pipe;
16345         struct intel_crtc *crtc;
16346
16347         drm_mode_config_init(dev);
16348
16349         dev->mode_config.min_width = 0;
16350         dev->mode_config.min_height = 0;
16351
16352         dev->mode_config.preferred_depth = 24;
16353         dev->mode_config.prefer_shadow = 1;
16354
16355         dev->mode_config.allow_fb_modifiers = true;
16356
16357         dev->mode_config.funcs = &intel_mode_funcs;
16358
16359         intel_init_quirks(dev);
16360
16361         intel_init_pm(dev);
16362
16363         if (INTEL_INFO(dev)->num_pipes == 0)
16364                 return;
16365
16366         /*
16367          * There may be no VBT; and if the BIOS enabled SSC we can
16368          * just keep using it to avoid unnecessary flicker.  Whereas if the
16369          * BIOS isn't using it, don't assume it will work even if the VBT
16370          * indicates as much.
16371          */
16372         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16373                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16374                                             DREF_SSC1_ENABLE);
16375
16376                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16377                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16378                                      bios_lvds_use_ssc ? "en" : "dis",
16379                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16380                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16381                 }
16382         }
16383
16384         if (IS_GEN2(dev)) {
16385                 dev->mode_config.max_width = 2048;
16386                 dev->mode_config.max_height = 2048;
16387         } else if (IS_GEN3(dev)) {
16388                 dev->mode_config.max_width = 4096;
16389                 dev->mode_config.max_height = 4096;
16390         } else {
16391                 dev->mode_config.max_width = 8192;
16392                 dev->mode_config.max_height = 8192;
16393         }
16394
16395         if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
16396                 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
16397                 dev->mode_config.cursor_height = 1023;
16398         } else if (IS_GEN2(dev)) {
16399                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16400                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16401         } else {
16402                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16403                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16404         }
16405
16406         dev->mode_config.fb_base = ggtt->mappable_base;
16407
16408         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16409                       INTEL_INFO(dev)->num_pipes,
16410                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16411
16412         for_each_pipe(dev_priv, pipe) {
16413                 intel_crtc_init(dev, pipe);
16414                 for_each_sprite(dev_priv, pipe, sprite) {
16415                         ret = intel_plane_init(dev, pipe, sprite);
16416                         if (ret)
16417                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16418                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
16419                 }
16420         }
16421
16422         intel_update_czclk(dev_priv);
16423         intel_update_cdclk(dev);
16424
16425         intel_shared_dpll_init(dev);
16426
16427         if (dev_priv->max_cdclk_freq == 0)
16428                 intel_update_max_cdclk(dev);
16429
16430         /* Just disable it once at startup */
16431         i915_disable_vga(dev);
16432         intel_setup_outputs(dev);
16433
16434         drm_modeset_lock_all(dev);
16435         intel_modeset_setup_hw_state(dev);
16436         drm_modeset_unlock_all(dev);
16437
16438         for_each_intel_crtc(dev, crtc) {
16439                 struct intel_initial_plane_config plane_config = {};
16440
16441                 if (!crtc->active)
16442                         continue;
16443
16444                 /*
16445                  * Note that reserving the BIOS fb up front prevents us
16446                  * from stuffing other stolen allocations like the ring
16447                  * on top.  This prevents some ugliness at boot time, and
16448                  * can even allow for smooth boot transitions if the BIOS
16449                  * fb is large enough for the active pipe configuration.
16450                  */
16451                 dev_priv->display.get_initial_plane_config(crtc,
16452                                                            &plane_config);
16453
16454                 /*
16455                  * If the fb is shared between multiple heads, we'll
16456                  * just get the first one.
16457                  */
16458                 intel_find_initial_plane_obj(crtc, &plane_config);
16459         }
16460
16461         /*
16462          * Make sure hardware watermarks really match the state we read out.
16463          * Note that we need to do this after reconstructing the BIOS fb's
16464          * since the watermark calculation done here will use pstate->fb.
16465          */
16466         sanitize_watermarks(dev);
16467 }
16468
16469 static void intel_enable_pipe_a(struct drm_device *dev)
16470 {
16471         struct intel_connector *connector;
16472         struct drm_connector *crt = NULL;
16473         struct intel_load_detect_pipe load_detect_temp;
16474         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16475
16476         /* We can't just switch on the pipe A, we need to set things up with a
16477          * proper mode and output configuration. As a gross hack, enable pipe A
16478          * by enabling the load detect pipe once. */
16479         for_each_intel_connector(dev, connector) {
16480                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16481                         crt = &connector->base;
16482                         break;
16483                 }
16484         }
16485
16486         if (!crt)
16487                 return;
16488
16489         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16490                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16491 }
16492
16493 static bool
16494 intel_check_plane_mapping(struct intel_crtc *crtc)
16495 {
16496         struct drm_device *dev = crtc->base.dev;
16497         struct drm_i915_private *dev_priv = to_i915(dev);
16498         u32 val;
16499
16500         if (INTEL_INFO(dev)->num_pipes == 1)
16501                 return true;
16502
16503         val = I915_READ(DSPCNTR(!crtc->plane));
16504
16505         if ((val & DISPLAY_PLANE_ENABLE) &&
16506             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16507                 return false;
16508
16509         return true;
16510 }
16511
16512 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16513 {
16514         struct drm_device *dev = crtc->base.dev;
16515         struct intel_encoder *encoder;
16516
16517         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16518                 return true;
16519
16520         return false;
16521 }
16522
16523 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16524 {
16525         struct drm_device *dev = encoder->base.dev;
16526         struct intel_connector *connector;
16527
16528         for_each_connector_on_encoder(dev, &encoder->base, connector)
16529                 return connector;
16530
16531         return NULL;
16532 }
16533
16534 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16535                               enum transcoder pch_transcoder)
16536 {
16537         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16538                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16539 }
16540
16541 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16542 {
16543         struct drm_device *dev = crtc->base.dev;
16544         struct drm_i915_private *dev_priv = to_i915(dev);
16545         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16546
16547         /* Clear any frame start delays used for debugging left by the BIOS */
16548         if (!transcoder_is_dsi(cpu_transcoder)) {
16549                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16550
16551                 I915_WRITE(reg,
16552                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16553         }
16554
16555         /* restore vblank interrupts to correct state */
16556         drm_crtc_vblank_reset(&crtc->base);
16557         if (crtc->active) {
16558                 struct intel_plane *plane;
16559
16560                 drm_crtc_vblank_on(&crtc->base);
16561
16562                 /* Disable everything but the primary plane */
16563                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16564                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16565                                 continue;
16566
16567                         plane->disable_plane(&plane->base, &crtc->base);
16568                 }
16569         }
16570
16571         /* We need to sanitize the plane -> pipe mapping first because this will
16572          * disable the crtc (and hence change the state) if it is wrong. Note
16573          * that gen4+ has a fixed plane -> pipe mapping.  */
16574         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16575                 bool plane;
16576
16577                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16578                               crtc->base.base.id, crtc->base.name);
16579
16580                 /* Pipe has the wrong plane attached and the plane is active.
16581                  * Temporarily change the plane mapping and disable everything
16582                  * ...  */
16583                 plane = crtc->plane;
16584                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16585                 crtc->plane = !plane;
16586                 intel_crtc_disable_noatomic(&crtc->base);
16587                 crtc->plane = plane;
16588         }
16589
16590         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16591             crtc->pipe == PIPE_A && !crtc->active) {
16592                 /* BIOS forgot to enable pipe A, this mostly happens after
16593                  * resume. Force-enable the pipe to fix this, the update_dpms
16594                  * call below we restore the pipe to the right state, but leave
16595                  * the required bits on. */
16596                 intel_enable_pipe_a(dev);
16597         }
16598
16599         /* Adjust the state of the output pipe according to whether we
16600          * have active connectors/encoders. */
16601         if (crtc->active && !intel_crtc_has_encoders(crtc))
16602                 intel_crtc_disable_noatomic(&crtc->base);
16603
16604         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16605                 /*
16606                  * We start out with underrun reporting disabled to avoid races.
16607                  * For correct bookkeeping mark this on active crtcs.
16608                  *
16609                  * Also on gmch platforms we dont have any hardware bits to
16610                  * disable the underrun reporting. Which means we need to start
16611                  * out with underrun reporting disabled also on inactive pipes,
16612                  * since otherwise we'll complain about the garbage we read when
16613                  * e.g. coming up after runtime pm.
16614                  *
16615                  * No protection against concurrent access is required - at
16616                  * worst a fifo underrun happens which also sets this to false.
16617                  */
16618                 crtc->cpu_fifo_underrun_disabled = true;
16619                 /*
16620                  * We track the PCH trancoder underrun reporting state
16621                  * within the crtc. With crtc for pipe A housing the underrun
16622                  * reporting state for PCH transcoder A, crtc for pipe B housing
16623                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16624                  * and marking underrun reporting as disabled for the non-existing
16625                  * PCH transcoders B and C would prevent enabling the south
16626                  * error interrupt (see cpt_can_enable_serr_int()).
16627                  */
16628                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16629                         crtc->pch_fifo_underrun_disabled = true;
16630         }
16631 }
16632
16633 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16634 {
16635         struct intel_connector *connector;
16636
16637         /* We need to check both for a crtc link (meaning that the
16638          * encoder is active and trying to read from a pipe) and the
16639          * pipe itself being active. */
16640         bool has_active_crtc = encoder->base.crtc &&
16641                 to_intel_crtc(encoder->base.crtc)->active;
16642
16643         connector = intel_encoder_find_connector(encoder);
16644         if (connector && !has_active_crtc) {
16645                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16646                               encoder->base.base.id,
16647                               encoder->base.name);
16648
16649                 /* Connector is active, but has no active pipe. This is
16650                  * fallout from our resume register restoring. Disable
16651                  * the encoder manually again. */
16652                 if (encoder->base.crtc) {
16653                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16654
16655                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16656                                       encoder->base.base.id,
16657                                       encoder->base.name);
16658                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16659                         if (encoder->post_disable)
16660                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16661                 }
16662                 encoder->base.crtc = NULL;
16663
16664                 /* Inconsistent output/port/pipe state happens presumably due to
16665                  * a bug in one of the get_hw_state functions. Or someplace else
16666                  * in our code, like the register restore mess on resume. Clamp
16667                  * things to off as a safer default. */
16668
16669                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16670                 connector->base.encoder = NULL;
16671         }
16672         /* Enabled encoders without active connectors will be fixed in
16673          * the crtc fixup. */
16674 }
16675
16676 void i915_redisable_vga_power_on(struct drm_device *dev)
16677 {
16678         struct drm_i915_private *dev_priv = to_i915(dev);
16679         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16680
16681         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16682                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16683                 i915_disable_vga(dev);
16684         }
16685 }
16686
16687 void i915_redisable_vga(struct drm_device *dev)
16688 {
16689         struct drm_i915_private *dev_priv = to_i915(dev);
16690
16691         /* This function can be called both from intel_modeset_setup_hw_state or
16692          * at a very early point in our resume sequence, where the power well
16693          * structures are not yet restored. Since this function is at a very
16694          * paranoid "someone might have enabled VGA while we were not looking"
16695          * level, just check if the power well is enabled instead of trying to
16696          * follow the "don't touch the power well if we don't need it" policy
16697          * the rest of the driver uses. */
16698         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16699                 return;
16700
16701         i915_redisable_vga_power_on(dev);
16702
16703         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16704 }
16705
16706 static bool primary_get_hw_state(struct intel_plane *plane)
16707 {
16708         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16709
16710         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16711 }
16712
16713 /* FIXME read out full plane state for all planes */
16714 static void readout_plane_state(struct intel_crtc *crtc)
16715 {
16716         struct drm_plane *primary = crtc->base.primary;
16717         struct intel_plane_state *plane_state =
16718                 to_intel_plane_state(primary->state);
16719
16720         plane_state->base.visible = crtc->active &&
16721                 primary_get_hw_state(to_intel_plane(primary));
16722
16723         if (plane_state->base.visible)
16724                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16725 }
16726
16727 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16728 {
16729         struct drm_i915_private *dev_priv = to_i915(dev);
16730         enum pipe pipe;
16731         struct intel_crtc *crtc;
16732         struct intel_encoder *encoder;
16733         struct intel_connector *connector;
16734         int i;
16735
16736         dev_priv->active_crtcs = 0;
16737
16738         for_each_intel_crtc(dev, crtc) {
16739                 struct intel_crtc_state *crtc_state = crtc->config;
16740                 int pixclk = 0;
16741
16742                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16743                 memset(crtc_state, 0, sizeof(*crtc_state));
16744                 crtc_state->base.crtc = &crtc->base;
16745
16746                 crtc_state->base.active = crtc_state->base.enable =
16747                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16748
16749                 crtc->base.enabled = crtc_state->base.enable;
16750                 crtc->active = crtc_state->base.active;
16751
16752                 if (crtc_state->base.active) {
16753                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16754
16755                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16756                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16757                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16758                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16759                         else
16760                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16761
16762                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16763                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16764                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16765                 }
16766
16767                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16768
16769                 readout_plane_state(crtc);
16770
16771                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16772                               crtc->base.base.id, crtc->base.name,
16773                               crtc->active ? "enabled" : "disabled");
16774         }
16775
16776         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16777                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16778
16779                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16780                                                   &pll->config.hw_state);
16781                 pll->config.crtc_mask = 0;
16782                 for_each_intel_crtc(dev, crtc) {
16783                         if (crtc->active && crtc->config->shared_dpll == pll)
16784                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16785                 }
16786                 pll->active_mask = pll->config.crtc_mask;
16787
16788                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16789                               pll->name, pll->config.crtc_mask, pll->on);
16790         }
16791
16792         for_each_intel_encoder(dev, encoder) {
16793                 pipe = 0;
16794
16795                 if (encoder->get_hw_state(encoder, &pipe)) {
16796                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16797                         encoder->base.crtc = &crtc->base;
16798                         crtc->config->output_types |= 1 << encoder->type;
16799                         encoder->get_config(encoder, crtc->config);
16800                 } else {
16801                         encoder->base.crtc = NULL;
16802                 }
16803
16804                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16805                               encoder->base.base.id,
16806                               encoder->base.name,
16807                               encoder->base.crtc ? "enabled" : "disabled",
16808                               pipe_name(pipe));
16809         }
16810
16811         for_each_intel_connector(dev, connector) {
16812                 if (connector->get_hw_state(connector)) {
16813                         connector->base.dpms = DRM_MODE_DPMS_ON;
16814
16815                         encoder = connector->encoder;
16816                         connector->base.encoder = &encoder->base;
16817
16818                         if (encoder->base.crtc &&
16819                             encoder->base.crtc->state->active) {
16820                                 /*
16821                                  * This has to be done during hardware readout
16822                                  * because anything calling .crtc_disable may
16823                                  * rely on the connector_mask being accurate.
16824                                  */
16825                                 encoder->base.crtc->state->connector_mask |=
16826                                         1 << drm_connector_index(&connector->base);
16827                                 encoder->base.crtc->state->encoder_mask |=
16828                                         1 << drm_encoder_index(&encoder->base);
16829                         }
16830
16831                 } else {
16832                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16833                         connector->base.encoder = NULL;
16834                 }
16835                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16836                               connector->base.base.id,
16837                               connector->base.name,
16838                               connector->base.encoder ? "enabled" : "disabled");
16839         }
16840
16841         for_each_intel_crtc(dev, crtc) {
16842                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16843
16844                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16845                 if (crtc->base.state->active) {
16846                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16847                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16848                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16849
16850                         /*
16851                          * The initial mode needs to be set in order to keep
16852                          * the atomic core happy. It wants a valid mode if the
16853                          * crtc's enabled, so we do the above call.
16854                          *
16855                          * At this point some state updated by the connectors
16856                          * in their ->detect() callback has not run yet, so
16857                          * no recalculation can be done yet.
16858                          *
16859                          * Even if we could do a recalculation and modeset
16860                          * right now it would cause a double modeset if
16861                          * fbdev or userspace chooses a different initial mode.
16862                          *
16863                          * If that happens, someone indicated they wanted a
16864                          * mode change, which means it's safe to do a full
16865                          * recalculation.
16866                          */
16867                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16868
16869                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16870                         update_scanline_offset(crtc);
16871                 }
16872
16873                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16874         }
16875 }
16876
16877 /* Scan out the current hw modeset state,
16878  * and sanitizes it to the current state
16879  */
16880 static void
16881 intel_modeset_setup_hw_state(struct drm_device *dev)
16882 {
16883         struct drm_i915_private *dev_priv = to_i915(dev);
16884         enum pipe pipe;
16885         struct intel_crtc *crtc;
16886         struct intel_encoder *encoder;
16887         int i;
16888
16889         intel_modeset_readout_hw_state(dev);
16890
16891         /* HW state is read out, now we need to sanitize this mess. */
16892         for_each_intel_encoder(dev, encoder) {
16893                 intel_sanitize_encoder(encoder);
16894         }
16895
16896         for_each_pipe(dev_priv, pipe) {
16897                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16898                 intel_sanitize_crtc(crtc);
16899                 intel_dump_pipe_config(crtc, crtc->config,
16900                                        "[setup_hw_state]");
16901         }
16902
16903         intel_modeset_update_connector_atomic_state(dev);
16904
16905         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16906                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16907
16908                 if (!pll->on || pll->active_mask)
16909                         continue;
16910
16911                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16912
16913                 pll->funcs.disable(dev_priv, pll);
16914                 pll->on = false;
16915         }
16916
16917         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16918                 vlv_wm_get_hw_state(dev);
16919         else if (IS_GEN9(dev))
16920                 skl_wm_get_hw_state(dev);
16921         else if (HAS_PCH_SPLIT(dev_priv))
16922                 ilk_wm_get_hw_state(dev);
16923
16924         for_each_intel_crtc(dev, crtc) {
16925                 unsigned long put_domains;
16926
16927                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16928                 if (WARN_ON(put_domains))
16929                         modeset_put_power_domains(dev_priv, put_domains);
16930         }
16931         intel_display_set_init_power(dev_priv, false);
16932
16933         intel_fbc_init_pipe_state(dev_priv);
16934 }
16935
16936 void intel_display_resume(struct drm_device *dev)
16937 {
16938         struct drm_i915_private *dev_priv = to_i915(dev);
16939         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16940         struct drm_modeset_acquire_ctx ctx;
16941         int ret;
16942
16943         dev_priv->modeset_restore_state = NULL;
16944         if (state)
16945                 state->acquire_ctx = &ctx;
16946
16947         /*
16948          * This is a cludge because with real atomic modeset mode_config.mutex
16949          * won't be taken. Unfortunately some probed state like
16950          * audio_codec_enable is still protected by mode_config.mutex, so lock
16951          * it here for now.
16952          */
16953         mutex_lock(&dev->mode_config.mutex);
16954         drm_modeset_acquire_init(&ctx, 0);
16955
16956         while (1) {
16957                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16958                 if (ret != -EDEADLK)
16959                         break;
16960
16961                 drm_modeset_backoff(&ctx);
16962         }
16963
16964         if (!ret)
16965                 ret = __intel_display_resume(dev, state);
16966
16967         drm_modeset_drop_locks(&ctx);
16968         drm_modeset_acquire_fini(&ctx);
16969         mutex_unlock(&dev->mode_config.mutex);
16970
16971         if (ret) {
16972                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16973                 drm_atomic_state_free(state);
16974         }
16975 }
16976
16977 void intel_modeset_gem_init(struct drm_device *dev)
16978 {
16979         struct drm_i915_private *dev_priv = to_i915(dev);
16980         struct drm_crtc *c;
16981         struct drm_i915_gem_object *obj;
16982
16983         intel_init_gt_powersave(dev_priv);
16984
16985         intel_modeset_init_hw(dev);
16986
16987         intel_setup_overlay(dev_priv);
16988
16989         /*
16990          * Make sure any fbs we allocated at startup are properly
16991          * pinned & fenced.  When we do the allocation it's too early
16992          * for this.
16993          */
16994         for_each_crtc(dev, c) {
16995                 struct i915_vma *vma;
16996
16997                 obj = intel_fb_obj(c->primary->fb);
16998                 if (obj == NULL)
16999                         continue;
17000
17001                 mutex_lock(&dev->struct_mutex);
17002                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17003                                                  c->primary->state->rotation);
17004                 mutex_unlock(&dev->struct_mutex);
17005                 if (IS_ERR(vma)) {
17006                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
17007                                   to_intel_crtc(c)->pipe);
17008                         drm_framebuffer_unreference(c->primary->fb);
17009                         c->primary->fb = NULL;
17010                         c->primary->crtc = c->primary->state->crtc = NULL;
17011                         update_state_fb(c->primary);
17012                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17013                 }
17014         }
17015 }
17016
17017 int intel_connector_register(struct drm_connector *connector)
17018 {
17019         struct intel_connector *intel_connector = to_intel_connector(connector);
17020         int ret;
17021
17022         ret = intel_backlight_device_register(intel_connector);
17023         if (ret)
17024                 goto err;
17025
17026         return 0;
17027
17028 err:
17029         return ret;
17030 }
17031
17032 void intel_connector_unregister(struct drm_connector *connector)
17033 {
17034         struct intel_connector *intel_connector = to_intel_connector(connector);
17035
17036         intel_backlight_device_unregister(intel_connector);
17037         intel_panel_destroy_backlight(connector);
17038 }
17039
17040 void intel_modeset_cleanup(struct drm_device *dev)
17041 {
17042         struct drm_i915_private *dev_priv = to_i915(dev);
17043
17044         intel_disable_gt_powersave(dev_priv);
17045
17046         /*
17047          * Interrupts and polling as the first thing to avoid creating havoc.
17048          * Too much stuff here (turning of connectors, ...) would
17049          * experience fancy races otherwise.
17050          */
17051         intel_irq_uninstall(dev_priv);
17052
17053         /*
17054          * Due to the hpd irq storm handling the hotplug work can re-arm the
17055          * poll handlers. Hence disable polling after hpd handling is shut down.
17056          */
17057         drm_kms_helper_poll_fini(dev);
17058
17059         intel_unregister_dsm_handler();
17060
17061         intel_fbc_global_disable(dev_priv);
17062
17063         /* flush any delayed tasks or pending work */
17064         flush_scheduled_work();
17065
17066         drm_mode_config_cleanup(dev);
17067
17068         intel_cleanup_overlay(dev_priv);
17069
17070         intel_cleanup_gt_powersave(dev_priv);
17071
17072         intel_teardown_gmbus(dev);
17073 }
17074
17075 void intel_connector_attach_encoder(struct intel_connector *connector,
17076                                     struct intel_encoder *encoder)
17077 {
17078         connector->encoder = encoder;
17079         drm_mode_connector_attach_encoder(&connector->base,
17080                                           &encoder->base);
17081 }
17082
17083 /*
17084  * set vga decode state - true == enable VGA decode
17085  */
17086 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17087 {
17088         struct drm_i915_private *dev_priv = to_i915(dev);
17089         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17090         u16 gmch_ctrl;
17091
17092         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17093                 DRM_ERROR("failed to read control word\n");
17094                 return -EIO;
17095         }
17096
17097         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17098                 return 0;
17099
17100         if (state)
17101                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17102         else
17103                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17104
17105         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17106                 DRM_ERROR("failed to write control word\n");
17107                 return -EIO;
17108         }
17109
17110         return 0;
17111 }
17112
17113 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17114
17115 struct intel_display_error_state {
17116
17117         u32 power_well_driver;
17118
17119         int num_transcoders;
17120
17121         struct intel_cursor_error_state {
17122                 u32 control;
17123                 u32 position;
17124                 u32 base;
17125                 u32 size;
17126         } cursor[I915_MAX_PIPES];
17127
17128         struct intel_pipe_error_state {
17129                 bool power_domain_on;
17130                 u32 source;
17131                 u32 stat;
17132         } pipe[I915_MAX_PIPES];
17133
17134         struct intel_plane_error_state {
17135                 u32 control;
17136                 u32 stride;
17137                 u32 size;
17138                 u32 pos;
17139                 u32 addr;
17140                 u32 surface;
17141                 u32 tile_offset;
17142         } plane[I915_MAX_PIPES];
17143
17144         struct intel_transcoder_error_state {
17145                 bool power_domain_on;
17146                 enum transcoder cpu_transcoder;
17147
17148                 u32 conf;
17149
17150                 u32 htotal;
17151                 u32 hblank;
17152                 u32 hsync;
17153                 u32 vtotal;
17154                 u32 vblank;
17155                 u32 vsync;
17156         } transcoder[4];
17157 };
17158
17159 struct intel_display_error_state *
17160 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17161 {
17162         struct intel_display_error_state *error;
17163         int transcoders[] = {
17164                 TRANSCODER_A,
17165                 TRANSCODER_B,
17166                 TRANSCODER_C,
17167                 TRANSCODER_EDP,
17168         };
17169         int i;
17170
17171         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17172                 return NULL;
17173
17174         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17175         if (error == NULL)
17176                 return NULL;
17177
17178         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17179                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17180
17181         for_each_pipe(dev_priv, i) {
17182                 error->pipe[i].power_domain_on =
17183                         __intel_display_power_is_enabled(dev_priv,
17184                                                          POWER_DOMAIN_PIPE(i));
17185                 if (!error->pipe[i].power_domain_on)
17186                         continue;
17187
17188                 error->cursor[i].control = I915_READ(CURCNTR(i));
17189                 error->cursor[i].position = I915_READ(CURPOS(i));
17190                 error->cursor[i].base = I915_READ(CURBASE(i));
17191
17192                 error->plane[i].control = I915_READ(DSPCNTR(i));
17193                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17194                 if (INTEL_GEN(dev_priv) <= 3) {
17195                         error->plane[i].size = I915_READ(DSPSIZE(i));
17196                         error->plane[i].pos = I915_READ(DSPPOS(i));
17197                 }
17198                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17199                         error->plane[i].addr = I915_READ(DSPADDR(i));
17200                 if (INTEL_GEN(dev_priv) >= 4) {
17201                         error->plane[i].surface = I915_READ(DSPSURF(i));
17202                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17203                 }
17204
17205                 error->pipe[i].source = I915_READ(PIPESRC(i));
17206
17207                 if (HAS_GMCH_DISPLAY(dev_priv))
17208                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17209         }
17210
17211         /* Note: this does not include DSI transcoders. */
17212         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17213         if (HAS_DDI(dev_priv))
17214                 error->num_transcoders++; /* Account for eDP. */
17215
17216         for (i = 0; i < error->num_transcoders; i++) {
17217                 enum transcoder cpu_transcoder = transcoders[i];
17218
17219                 error->transcoder[i].power_domain_on =
17220                         __intel_display_power_is_enabled(dev_priv,
17221                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17222                 if (!error->transcoder[i].power_domain_on)
17223                         continue;
17224
17225                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17226
17227                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17228                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17229                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17230                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17231                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17232                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17233                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17234         }
17235
17236         return error;
17237 }
17238
17239 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17240
17241 void
17242 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17243                                 struct drm_device *dev,
17244                                 struct intel_display_error_state *error)
17245 {
17246         struct drm_i915_private *dev_priv = to_i915(dev);
17247         int i;
17248
17249         if (!error)
17250                 return;
17251
17252         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17253         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17254                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17255                            error->power_well_driver);
17256         for_each_pipe(dev_priv, i) {
17257                 err_printf(m, "Pipe [%d]:\n", i);
17258                 err_printf(m, "  Power: %s\n",
17259                            onoff(error->pipe[i].power_domain_on));
17260                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17261                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17262
17263                 err_printf(m, "Plane [%d]:\n", i);
17264                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17265                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17266                 if (INTEL_INFO(dev)->gen <= 3) {
17267                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17268                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17269                 }
17270                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17271                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17272                 if (INTEL_INFO(dev)->gen >= 4) {
17273                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17274                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17275                 }
17276
17277                 err_printf(m, "Cursor [%d]:\n", i);
17278                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17279                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17280                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17281         }
17282
17283         for (i = 0; i < error->num_transcoders; i++) {
17284                 err_printf(m, "CPU transcoder: %s\n",
17285                            transcoder_name(error->transcoder[i].cpu_transcoder));
17286                 err_printf(m, "  Power: %s\n",
17287                            onoff(error->transcoder[i].power_domain_on));
17288                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17289                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17290                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17291                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17292                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17293                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17294                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17295         }
17296 }
17297
17298 #endif