2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
76 static const uint32_t skl_primary_formats[] = {
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
91 static const uint32_t skl_pri_planar_formats[] = {
98 DRM_FORMAT_XRGB2101010,
99 DRM_FORMAT_XBGR2101010,
107 static const uint64_t skl_format_modifiers_noccs[] = {
108 I915_FORMAT_MOD_Yf_TILED,
109 I915_FORMAT_MOD_Y_TILED,
110 I915_FORMAT_MOD_X_TILED,
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_INVALID
115 static const uint64_t skl_format_modifiers_ccs[] = {
116 I915_FORMAT_MOD_Yf_TILED_CCS,
117 I915_FORMAT_MOD_Y_TILED_CCS,
118 I915_FORMAT_MOD_Yf_TILED,
119 I915_FORMAT_MOD_Y_TILED,
120 I915_FORMAT_MOD_X_TILED,
121 DRM_FORMAT_MOD_LINEAR,
122 DRM_FORMAT_MOD_INVALID
126 static const uint32_t intel_cursor_formats[] = {
130 static const uint64_t cursor_format_modifiers[] = {
131 DRM_FORMAT_MOD_LINEAR,
132 DRM_FORMAT_MOD_INVALID
135 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
136 struct intel_crtc_state *pipe_config);
137 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
138 struct intel_crtc_state *pipe_config);
140 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
141 struct drm_i915_gem_object *obj,
142 struct drm_mode_fb_cmd2 *mode_cmd);
143 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
144 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
145 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
147 struct intel_link_m_n *m_n,
148 struct intel_link_m_n *m2_n2);
149 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
150 static void haswell_set_pipeconf(struct drm_crtc *crtc);
151 static void haswell_set_pipemisc(struct drm_crtc *crtc);
152 static void vlv_prepare_pll(struct intel_crtc *crtc,
153 const struct intel_crtc_state *pipe_config);
154 static void chv_prepare_pll(struct intel_crtc *crtc,
155 const struct intel_crtc_state *pipe_config);
156 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
157 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
158 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
159 struct intel_crtc_state *crtc_state);
160 static void skylake_pfit_enable(struct intel_crtc *crtc);
161 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
162 static void ironlake_pfit_enable(struct intel_crtc *crtc);
163 static void intel_modeset_setup_hw_state(struct drm_device *dev,
164 struct drm_modeset_acquire_ctx *ctx);
165 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
170 } dot, vco, n, m, m1, m2, p, p1;
174 int p2_slow, p2_fast;
178 /* returns HPLL frequency in kHz */
179 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
181 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
183 /* Obtain SKU information */
184 mutex_lock(&dev_priv->sb_lock);
185 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
186 CCK_FUSE_HPLL_FREQ_MASK;
187 mutex_unlock(&dev_priv->sb_lock);
189 return vco_freq[hpll_freq] * 1000;
192 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
193 const char *name, u32 reg, int ref_freq)
198 mutex_lock(&dev_priv->sb_lock);
199 val = vlv_cck_read(dev_priv, reg);
200 mutex_unlock(&dev_priv->sb_lock);
202 divider = val & CCK_FREQUENCY_VALUES;
204 WARN((val & CCK_FREQUENCY_STATUS) !=
205 (divider << CCK_FREQUENCY_STATUS_SHIFT),
206 "%s change in progress\n", name);
208 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
211 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
212 const char *name, u32 reg)
214 if (dev_priv->hpll_freq == 0)
215 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
217 return vlv_get_cck_clock(dev_priv, name, reg,
218 dev_priv->hpll_freq);
221 static void intel_update_czclk(struct drm_i915_private *dev_priv)
223 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
226 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
227 CCK_CZ_CLOCK_CONTROL);
229 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
232 static inline u32 /* units of 100MHz */
233 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
234 const struct intel_crtc_state *pipe_config)
236 if (HAS_DDI(dev_priv))
237 return pipe_config->port_clock; /* SPLL */
239 return dev_priv->fdi_pll_freq;
242 static const struct intel_limit intel_limits_i8xx_dac = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 908000, .max = 1512000 },
245 .n = { .min = 2, .max = 16 },
246 .m = { .min = 96, .max = 140 },
247 .m1 = { .min = 18, .max = 26 },
248 .m2 = { .min = 6, .max = 16 },
249 .p = { .min = 4, .max = 128 },
250 .p1 = { .min = 2, .max = 33 },
251 .p2 = { .dot_limit = 165000,
252 .p2_slow = 4, .p2_fast = 2 },
255 static const struct intel_limit intel_limits_i8xx_dvo = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 908000, .max = 1512000 },
258 .n = { .min = 2, .max = 16 },
259 .m = { .min = 96, .max = 140 },
260 .m1 = { .min = 18, .max = 26 },
261 .m2 = { .min = 6, .max = 16 },
262 .p = { .min = 4, .max = 128 },
263 .p1 = { .min = 2, .max = 33 },
264 .p2 = { .dot_limit = 165000,
265 .p2_slow = 4, .p2_fast = 4 },
268 static const struct intel_limit intel_limits_i8xx_lvds = {
269 .dot = { .min = 25000, .max = 350000 },
270 .vco = { .min = 908000, .max = 1512000 },
271 .n = { .min = 2, .max = 16 },
272 .m = { .min = 96, .max = 140 },
273 .m1 = { .min = 18, .max = 26 },
274 .m2 = { .min = 6, .max = 16 },
275 .p = { .min = 4, .max = 128 },
276 .p1 = { .min = 1, .max = 6 },
277 .p2 = { .dot_limit = 165000,
278 .p2_slow = 14, .p2_fast = 7 },
281 static const struct intel_limit intel_limits_i9xx_sdvo = {
282 .dot = { .min = 20000, .max = 400000 },
283 .vco = { .min = 1400000, .max = 2800000 },
284 .n = { .min = 1, .max = 6 },
285 .m = { .min = 70, .max = 120 },
286 .m1 = { .min = 8, .max = 18 },
287 .m2 = { .min = 3, .max = 7 },
288 .p = { .min = 5, .max = 80 },
289 .p1 = { .min = 1, .max = 8 },
290 .p2 = { .dot_limit = 200000,
291 .p2_slow = 10, .p2_fast = 5 },
294 static const struct intel_limit intel_limits_i9xx_lvds = {
295 .dot = { .min = 20000, .max = 400000 },
296 .vco = { .min = 1400000, .max = 2800000 },
297 .n = { .min = 1, .max = 6 },
298 .m = { .min = 70, .max = 120 },
299 .m1 = { .min = 8, .max = 18 },
300 .m2 = { .min = 3, .max = 7 },
301 .p = { .min = 7, .max = 98 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 112000,
304 .p2_slow = 14, .p2_fast = 7 },
308 static const struct intel_limit intel_limits_g4x_sdvo = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 1750000, .max = 3500000},
311 .n = { .min = 1, .max = 4 },
312 .m = { .min = 104, .max = 138 },
313 .m1 = { .min = 17, .max = 23 },
314 .m2 = { .min = 5, .max = 11 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 1, .max = 3},
317 .p2 = { .dot_limit = 270000,
323 static const struct intel_limit intel_limits_g4x_hdmi = {
324 .dot = { .min = 22000, .max = 400000 },
325 .vco = { .min = 1750000, .max = 3500000},
326 .n = { .min = 1, .max = 4 },
327 .m = { .min = 104, .max = 138 },
328 .m1 = { .min = 16, .max = 23 },
329 .m2 = { .min = 5, .max = 11 },
330 .p = { .min = 5, .max = 80 },
331 .p1 = { .min = 1, .max = 8},
332 .p2 = { .dot_limit = 165000,
333 .p2_slow = 10, .p2_fast = 5 },
336 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
337 .dot = { .min = 20000, .max = 115000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 28, .max = 112 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 14, .p2_fast = 14
350 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
351 .dot = { .min = 80000, .max = 224000 },
352 .vco = { .min = 1750000, .max = 3500000 },
353 .n = { .min = 1, .max = 3 },
354 .m = { .min = 104, .max = 138 },
355 .m1 = { .min = 17, .max = 23 },
356 .m2 = { .min = 5, .max = 11 },
357 .p = { .min = 14, .max = 42 },
358 .p1 = { .min = 2, .max = 6 },
359 .p2 = { .dot_limit = 0,
360 .p2_slow = 7, .p2_fast = 7
364 static const struct intel_limit intel_limits_pineview_sdvo = {
365 .dot = { .min = 20000, .max = 400000},
366 .vco = { .min = 1700000, .max = 3500000 },
367 /* Pineview's Ncounter is a ring counter */
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 /* Pineview only has one combined m divider, which we treat as m2. */
371 .m1 = { .min = 0, .max = 0 },
372 .m2 = { .min = 0, .max = 254 },
373 .p = { .min = 5, .max = 80 },
374 .p1 = { .min = 1, .max = 8 },
375 .p2 = { .dot_limit = 200000,
376 .p2_slow = 10, .p2_fast = 5 },
379 static const struct intel_limit intel_limits_pineview_lvds = {
380 .dot = { .min = 20000, .max = 400000 },
381 .vco = { .min = 1700000, .max = 3500000 },
382 .n = { .min = 3, .max = 6 },
383 .m = { .min = 2, .max = 256 },
384 .m1 = { .min = 0, .max = 0 },
385 .m2 = { .min = 0, .max = 254 },
386 .p = { .min = 7, .max = 112 },
387 .p1 = { .min = 1, .max = 8 },
388 .p2 = { .dot_limit = 112000,
389 .p2_slow = 14, .p2_fast = 14 },
392 /* Ironlake / Sandybridge
394 * We calculate clock using (register_value + 2) for N/M1/M2, so here
395 * the range value for them is (actual_value - 2).
397 static const struct intel_limit intel_limits_ironlake_dac = {
398 .dot = { .min = 25000, .max = 350000 },
399 .vco = { .min = 1760000, .max = 3510000 },
400 .n = { .min = 1, .max = 5 },
401 .m = { .min = 79, .max = 127 },
402 .m1 = { .min = 12, .max = 22 },
403 .m2 = { .min = 5, .max = 9 },
404 .p = { .min = 5, .max = 80 },
405 .p1 = { .min = 1, .max = 8 },
406 .p2 = { .dot_limit = 225000,
407 .p2_slow = 10, .p2_fast = 5 },
410 static const struct intel_limit intel_limits_ironlake_single_lvds = {
411 .dot = { .min = 25000, .max = 350000 },
412 .vco = { .min = 1760000, .max = 3510000 },
413 .n = { .min = 1, .max = 3 },
414 .m = { .min = 79, .max = 118 },
415 .m1 = { .min = 12, .max = 22 },
416 .m2 = { .min = 5, .max = 9 },
417 .p = { .min = 28, .max = 112 },
418 .p1 = { .min = 2, .max = 8 },
419 .p2 = { .dot_limit = 225000,
420 .p2_slow = 14, .p2_fast = 14 },
423 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 3 },
427 .m = { .min = 79, .max = 127 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 14, .max = 56 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 7, .p2_fast = 7 },
436 /* LVDS 100mhz refclk limits. */
437 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
438 .dot = { .min = 25000, .max = 350000 },
439 .vco = { .min = 1760000, .max = 3510000 },
440 .n = { .min = 1, .max = 2 },
441 .m = { .min = 79, .max = 126 },
442 .m1 = { .min = 12, .max = 22 },
443 .m2 = { .min = 5, .max = 9 },
444 .p = { .min = 28, .max = 112 },
445 .p1 = { .min = 2, .max = 8 },
446 .p2 = { .dot_limit = 225000,
447 .p2_slow = 14, .p2_fast = 14 },
450 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
451 .dot = { .min = 25000, .max = 350000 },
452 .vco = { .min = 1760000, .max = 3510000 },
453 .n = { .min = 1, .max = 3 },
454 .m = { .min = 79, .max = 126 },
455 .m1 = { .min = 12, .max = 22 },
456 .m2 = { .min = 5, .max = 9 },
457 .p = { .min = 14, .max = 42 },
458 .p1 = { .min = 2, .max = 6 },
459 .p2 = { .dot_limit = 225000,
460 .p2_slow = 7, .p2_fast = 7 },
463 static const struct intel_limit intel_limits_vlv = {
465 * These are the data rate limits (measured in fast clocks)
466 * since those are the strictest limits we have. The fast
467 * clock and actual rate limits are more relaxed, so checking
468 * them would make no difference.
470 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
471 .vco = { .min = 4000000, .max = 6000000 },
472 .n = { .min = 1, .max = 7 },
473 .m1 = { .min = 2, .max = 3 },
474 .m2 = { .min = 11, .max = 156 },
475 .p1 = { .min = 2, .max = 3 },
476 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
479 static const struct intel_limit intel_limits_chv = {
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
486 .dot = { .min = 25000 * 5, .max = 540000 * 5},
487 .vco = { .min = 4800000, .max = 6480000 },
488 .n = { .min = 1, .max = 1 },
489 .m1 = { .min = 2, .max = 2 },
490 .m2 = { .min = 24 << 22, .max = 175 << 22 },
491 .p1 = { .min = 2, .max = 4 },
492 .p2 = { .p2_slow = 1, .p2_fast = 14 },
495 static const struct intel_limit intel_limits_bxt = {
496 /* FIXME: find real dot limits */
497 .dot = { .min = 0, .max = INT_MAX },
498 .vco = { .min = 4800000, .max = 6700000 },
499 .n = { .min = 1, .max = 1 },
500 .m1 = { .min = 2, .max = 2 },
501 /* FIXME: find real m2 limits */
502 .m2 = { .min = 2 << 22, .max = 255 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 20 },
508 skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
510 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
514 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
516 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
520 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
522 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
526 I915_WRITE(CLKGATE_DIS_PSL(pipe),
527 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
529 I915_WRITE(CLKGATE_DIS_PSL(pipe),
530 I915_READ(CLKGATE_DIS_PSL(pipe)) &
531 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
535 needs_modeset(const struct drm_crtc_state *state)
537 return drm_atomic_crtc_needs_modeset(state);
541 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
542 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
543 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
544 * The helpers' return value is the rate of the clock that is fed to the
545 * display engine's pipe which can be the above fast dot clock rate or a
546 * divided-down version of it.
548 /* m1 is reserved as 0 in Pineview, n is a ring counter */
549 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
551 clock->m = clock->m2 + 2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
561 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
563 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
566 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
568 clock->m = i9xx_dpll_compute_m(clock);
569 clock->p = clock->p1 * clock->p2;
570 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
572 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
573 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m1 * clock->m2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587 return clock->dot / 5;
590 int chv_calc_dpll_params(int refclk, struct dpll *clock)
592 clock->m = clock->m1 * clock->m2;
593 clock->p = clock->p1 * clock->p2;
594 if (WARN_ON(clock->n == 0 || clock->p == 0))
596 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
598 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
600 return clock->dot / 5;
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
606 * Returns whether the given set of divisors are valid for a given refclk with
607 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
610 const struct intel_limit *limit,
611 const struct dpll *clock)
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
616 INTELPllInvalid("p1 out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
622 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
623 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
624 if (clock->m1 <= clock->m2)
625 INTELPllInvalid("m1 <= m2\n");
627 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
628 !IS_GEN9_LP(dev_priv)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
647 i9xx_select_p2_div(const struct intel_limit *limit,
648 const struct intel_crtc_state *crtc_state,
651 struct drm_device *dev = crtc_state->base.crtc->dev;
653 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev))
660 return limit->p2.p2_fast;
662 return limit->p2.p2_slow;
664 if (target < limit->p2.dot_limit)
665 return limit->p2.p2_slow;
667 return limit->p2.p2_fast;
672 * Returns a set of divisors for the desired target clock with the given
673 * refclk, or FALSE. The returned values represent the clock equation:
674 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
676 * Target and reference clocks are specified in kHz.
678 * If match_clock is provided, then best_clock P divider must match the P
679 * divider from @match_clock used for LVDS downclocking.
682 i9xx_find_best_dpll(const struct intel_limit *limit,
683 struct intel_crtc_state *crtc_state,
684 int target, int refclk, struct dpll *match_clock,
685 struct dpll *best_clock)
687 struct drm_device *dev = crtc_state->base.crtc->dev;
691 memset(best_clock, 0, sizeof(*best_clock));
693 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
695 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
697 for (clock.m2 = limit->m2.min;
698 clock.m2 <= limit->m2.max; clock.m2++) {
699 if (clock.m2 >= clock.m1)
701 for (clock.n = limit->n.min;
702 clock.n <= limit->n.max; clock.n++) {
703 for (clock.p1 = limit->p1.min;
704 clock.p1 <= limit->p1.max; clock.p1++) {
707 i9xx_calc_dpll_params(refclk, &clock);
708 if (!intel_PLL_is_valid(to_i915(dev),
713 clock.p != match_clock->p)
716 this_err = abs(clock.dot - target);
717 if (this_err < err) {
726 return (err != target);
730 * Returns a set of divisors for the desired target clock with the given
731 * refclk, or FALSE. The returned values represent the clock equation:
732 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
734 * Target and reference clocks are specified in kHz.
736 * If match_clock is provided, then best_clock P divider must match the P
737 * divider from @match_clock used for LVDS downclocking.
740 pnv_find_best_dpll(const struct intel_limit *limit,
741 struct intel_crtc_state *crtc_state,
742 int target, int refclk, struct dpll *match_clock,
743 struct dpll *best_clock)
745 struct drm_device *dev = crtc_state->base.crtc->dev;
749 memset(best_clock, 0, sizeof(*best_clock));
751 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
755 for (clock.m2 = limit->m2.min;
756 clock.m2 <= limit->m2.max; clock.m2++) {
757 for (clock.n = limit->n.min;
758 clock.n <= limit->n.max; clock.n++) {
759 for (clock.p1 = limit->p1.min;
760 clock.p1 <= limit->p1.max; clock.p1++) {
763 pnv_calc_dpll_params(refclk, &clock);
764 if (!intel_PLL_is_valid(to_i915(dev),
769 clock.p != match_clock->p)
772 this_err = abs(clock.dot - target);
773 if (this_err < err) {
782 return (err != target);
786 * Returns a set of divisors for the desired target clock with the given
787 * refclk, or FALSE. The returned values represent the clock equation:
788 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
790 * Target and reference clocks are specified in kHz.
792 * If match_clock is provided, then best_clock P divider must match the P
793 * divider from @match_clock used for LVDS downclocking.
796 g4x_find_best_dpll(const struct intel_limit *limit,
797 struct intel_crtc_state *crtc_state,
798 int target, int refclk, struct dpll *match_clock,
799 struct dpll *best_clock)
801 struct drm_device *dev = crtc_state->base.crtc->dev;
805 /* approximately equals target * 0.00585 */
806 int err_most = (target >> 8) + (target >> 9);
808 memset(best_clock, 0, sizeof(*best_clock));
810 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
812 max_n = limit->n.max;
813 /* based on hardware requirement, prefer smaller n to precision */
814 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
815 /* based on hardware requirement, prefere larger m1,m2 */
816 for (clock.m1 = limit->m1.max;
817 clock.m1 >= limit->m1.min; clock.m1--) {
818 for (clock.m2 = limit->m2.max;
819 clock.m2 >= limit->m2.min; clock.m2--) {
820 for (clock.p1 = limit->p1.max;
821 clock.p1 >= limit->p1.min; clock.p1--) {
824 i9xx_calc_dpll_params(refclk, &clock);
825 if (!intel_PLL_is_valid(to_i915(dev),
830 this_err = abs(clock.dot - target);
831 if (this_err < err_most) {
845 * Check if the calculated PLL configuration is more optimal compared to the
846 * best configuration and error found so far. Return the calculated error.
848 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
849 const struct dpll *calculated_clock,
850 const struct dpll *best_clock,
851 unsigned int best_error_ppm,
852 unsigned int *error_ppm)
855 * For CHV ignore the error and consider only the P value.
856 * Prefer a bigger P value based on HW requirements.
858 if (IS_CHERRYVIEW(to_i915(dev))) {
861 return calculated_clock->p > best_clock->p;
864 if (WARN_ON_ONCE(!target_freq))
867 *error_ppm = div_u64(1000000ULL *
868 abs(target_freq - calculated_clock->dot),
871 * Prefer a better P value over a better (smaller) error if the error
872 * is small. Ensure this preference for future configurations too by
873 * setting the error to 0.
875 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
881 return *error_ppm + 10 < best_error_ppm;
885 * Returns a set of divisors for the desired target clock with the given
886 * refclk, or FALSE. The returned values represent the clock equation:
887 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
890 vlv_find_best_dpll(const struct intel_limit *limit,
891 struct intel_crtc_state *crtc_state,
892 int target, int refclk, struct dpll *match_clock,
893 struct dpll *best_clock)
895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
896 struct drm_device *dev = crtc->base.dev;
898 unsigned int bestppm = 1000000;
899 /* min update 19.2 MHz */
900 int max_n = min(limit->n.max, refclk / 19200);
903 target *= 5; /* fast clock */
905 memset(best_clock, 0, sizeof(*best_clock));
907 /* based on hardware requirement, prefer smaller n to precision */
908 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
909 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
910 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 clock.p = clock.p1 * clock.p2;
913 /* based on hardware requirement, prefer bigger m1,m2 values */
914 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
917 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
920 vlv_calc_dpll_params(refclk, &clock);
922 if (!intel_PLL_is_valid(to_i915(dev),
927 if (!vlv_PLL_is_optimal(dev, target,
945 * Returns a set of divisors for the desired target clock with the given
946 * refclk, or FALSE. The returned values represent the clock equation:
947 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
950 chv_find_best_dpll(const struct intel_limit *limit,
951 struct intel_crtc_state *crtc_state,
952 int target, int refclk, struct dpll *match_clock,
953 struct dpll *best_clock)
955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
956 struct drm_device *dev = crtc->base.dev;
957 unsigned int best_error_ppm;
962 memset(best_clock, 0, sizeof(*best_clock));
963 best_error_ppm = 1000000;
966 * Based on hardware doc, the n always set to 1, and m1 always
967 * set to 2. If requires to support 200Mhz refclk, we need to
968 * revisit this because n may not 1 anymore.
970 clock.n = 1, clock.m1 = 2;
971 target *= 5; /* fast clock */
973 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
974 for (clock.p2 = limit->p2.p2_fast;
975 clock.p2 >= limit->p2.p2_slow;
976 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
977 unsigned int error_ppm;
979 clock.p = clock.p1 * clock.p2;
981 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
982 clock.n) << 22, refclk * clock.m1);
984 if (m2 > INT_MAX/clock.m1)
989 chv_calc_dpll_params(refclk, &clock);
991 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
994 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
995 best_error_ppm, &error_ppm))
999 best_error_ppm = error_ppm;
1007 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1008 struct dpll *best_clock)
1010 int refclk = 100000;
1011 const struct intel_limit *limit = &intel_limits_bxt;
1013 return chv_find_best_dpll(limit, crtc_state,
1014 target_clock, refclk, NULL, best_clock);
1017 bool intel_crtc_active(struct intel_crtc *crtc)
1019 /* Be paranoid as we can arrive here with only partial
1020 * state retrieved from the hardware during setup.
1022 * We can ditch the adjusted_mode.crtc_clock check as soon
1023 * as Haswell has gained clock readout/fastboot support.
1025 * We can ditch the crtc->primary->fb check as soon as we can
1026 * properly reconstruct framebuffers.
1028 * FIXME: The intel_crtc->active here should be switched to
1029 * crtc->state->active once we have proper CRTC states wired up
1032 return crtc->active && crtc->base.primary->state->fb &&
1033 crtc->config->base.adjusted_mode.crtc_clock;
1036 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1039 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1041 return crtc->config->cpu_transcoder;
1044 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1047 i915_reg_t reg = PIPEDSL(pipe);
1051 if (IS_GEN2(dev_priv))
1052 line_mask = DSL_LINEMASK_GEN2;
1054 line_mask = DSL_LINEMASK_GEN3;
1056 line1 = I915_READ(reg) & line_mask;
1058 line2 = I915_READ(reg) & line_mask;
1060 return line1 != line2;
1063 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1066 enum pipe pipe = crtc->pipe;
1068 /* Wait for the display line to settle/start moving */
1069 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1070 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1071 pipe_name(pipe), onoff(state));
1074 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1076 wait_for_pipe_scanline_moving(crtc, false);
1079 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1081 wait_for_pipe_scanline_moving(crtc, true);
1085 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1087 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1090 if (INTEL_GEN(dev_priv) >= 4) {
1091 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1092 i915_reg_t reg = PIPECONF(cpu_transcoder);
1094 /* Wait for the Pipe State to go off */
1095 if (intel_wait_for_register(dev_priv,
1096 reg, I965_PIPECONF_ACTIVE, 0,
1098 WARN(1, "pipe_off wait timed out\n");
1100 intel_wait_for_pipe_scanline_stopped(crtc);
1104 /* Only for pre-ILK configs */
1105 void assert_pll(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1111 val = I915_READ(DPLL(pipe));
1112 cur_state = !!(val & DPLL_VCO_ENABLE);
1113 I915_STATE_WARN(cur_state != state,
1114 "PLL state assertion failure (expected %s, current %s)\n",
1115 onoff(state), onoff(cur_state));
1118 /* XXX: the dsi pll is shared between MIPI DSI ports */
1119 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124 mutex_lock(&dev_priv->sb_lock);
1125 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1126 mutex_unlock(&dev_priv->sb_lock);
1128 cur_state = val & DSI_PLL_VCO_EN;
1129 I915_STATE_WARN(cur_state != state,
1130 "DSI PLL state assertion failure (expected %s, current %s)\n",
1131 onoff(state), onoff(cur_state));
1134 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1138 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1141 if (HAS_DDI(dev_priv)) {
1142 /* DDI does not have a specific FDI_TX register */
1143 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1144 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1146 u32 val = I915_READ(FDI_TX_CTL(pipe));
1147 cur_state = !!(val & FDI_TX_ENABLE);
1149 I915_STATE_WARN(cur_state != state,
1150 "FDI TX state assertion failure (expected %s, current %s)\n",
1151 onoff(state), onoff(cur_state));
1153 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1154 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1156 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1157 enum pipe pipe, bool state)
1162 val = I915_READ(FDI_RX_CTL(pipe));
1163 cur_state = !!(val & FDI_RX_ENABLE);
1164 I915_STATE_WARN(cur_state != state,
1165 "FDI RX state assertion failure (expected %s, current %s)\n",
1166 onoff(state), onoff(cur_state));
1168 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1169 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1171 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1176 /* ILK FDI PLL is always enabled */
1177 if (IS_GEN5(dev_priv))
1180 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181 if (HAS_DDI(dev_priv))
1184 val = I915_READ(FDI_TX_CTL(pipe));
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1194 val = I915_READ(FDI_RX_CTL(pipe));
1195 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1198 onoff(state), onoff(cur_state));
1201 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1205 enum pipe panel_pipe = INVALID_PIPE;
1208 if (WARN_ON(HAS_DDI(dev_priv)))
1211 if (HAS_PCH_SPLIT(dev_priv)) {
1214 pp_reg = PP_CONTROL(0);
1215 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1218 case PANEL_PORT_SELECT_LVDS:
1219 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1221 case PANEL_PORT_SELECT_DPA:
1222 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1224 case PANEL_PORT_SELECT_DPC:
1225 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1227 case PANEL_PORT_SELECT_DPD:
1228 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1231 MISSING_CASE(port_sel);
1234 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1235 /* presumably write lock depends on pipe, not port select */
1236 pp_reg = PP_CONTROL(pipe);
1241 pp_reg = PP_CONTROL(0);
1242 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1244 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1245 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1248 val = I915_READ(pp_reg);
1249 if (!(val & PANEL_POWER_ON) ||
1250 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1253 I915_STATE_WARN(panel_pipe == pipe && locked,
1254 "panel assertion failure, pipe %c regs locked\n",
1258 void assert_pipe(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, bool state)
1262 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1264 enum intel_display_power_domain power_domain;
1266 /* we keep both pipes enabled on 830 */
1267 if (IS_I830(dev_priv))
1270 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1271 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1272 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1273 cur_state = !!(val & PIPECONF_ENABLE);
1275 intel_display_power_put(dev_priv, power_domain);
1280 I915_STATE_WARN(cur_state != state,
1281 "pipe %c assertion failure (expected %s, current %s)\n",
1282 pipe_name(pipe), onoff(state), onoff(cur_state));
1285 static void assert_plane(struct intel_plane *plane, bool state)
1290 cur_state = plane->get_hw_state(plane, &pipe);
1292 I915_STATE_WARN(cur_state != state,
1293 "%s assertion failure (expected %s, current %s)\n",
1294 plane->base.name, onoff(state), onoff(cur_state));
1297 #define assert_plane_enabled(p) assert_plane(p, true)
1298 #define assert_plane_disabled(p) assert_plane(p, false)
1300 static void assert_planes_disabled(struct intel_crtc *crtc)
1302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1303 struct intel_plane *plane;
1305 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1306 assert_plane_disabled(plane);
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312 drm_crtc_vblank_put(crtc);
1315 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1321 val = I915_READ(PCH_TRANSCONF(pipe));
1322 enabled = !!(val & TRANS_ENABLE);
1323 I915_STATE_WARN(enabled,
1324 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1329 enum pipe pipe, enum port port,
1332 enum pipe port_pipe;
1335 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1337 I915_STATE_WARN(state && port_pipe == pipe,
1338 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1339 port_name(port), pipe_name(pipe));
1341 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1342 "IBX PCH DP %c still using transcoder B\n",
1346 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, enum port port,
1348 i915_reg_t hdmi_reg)
1350 enum pipe port_pipe;
1353 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1355 I915_STATE_WARN(state && port_pipe == pipe,
1356 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1357 port_name(port), pipe_name(pipe));
1359 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1360 "IBX PCH HDMI %c still using transcoder B\n",
1364 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1367 enum pipe port_pipe;
1369 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1370 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1371 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1373 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1375 "PCH VGA enabled on transcoder %c, should be disabled\n",
1378 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1380 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1383 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1384 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1385 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1388 static void _vlv_enable_pll(struct intel_crtc *crtc,
1389 const struct intel_crtc_state *pipe_config)
1391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1392 enum pipe pipe = crtc->pipe;
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1395 POSTING_READ(DPLL(pipe));
1398 if (intel_wait_for_register(dev_priv,
1403 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1406 static void vlv_enable_pll(struct intel_crtc *crtc,
1407 const struct intel_crtc_state *pipe_config)
1409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1410 enum pipe pipe = crtc->pipe;
1412 assert_pipe_disabled(dev_priv, pipe);
1414 /* PLL is protected by panel, make sure we can write it */
1415 assert_panel_unlocked(dev_priv, pipe);
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1418 _vlv_enable_pll(crtc, pipe_config);
1420 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1421 POSTING_READ(DPLL_MD(pipe));
1425 static void _chv_enable_pll(struct intel_crtc *crtc,
1426 const struct intel_crtc_state *pipe_config)
1428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1429 enum pipe pipe = crtc->pipe;
1430 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1433 mutex_lock(&dev_priv->sb_lock);
1435 /* Enable back the 10bit clock to display controller */
1436 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1437 tmp |= DPIO_DCLKP_EN;
1438 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1440 mutex_unlock(&dev_priv->sb_lock);
1443 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1448 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1450 /* Check PLL is locked */
1451 if (intel_wait_for_register(dev_priv,
1452 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1454 DRM_ERROR("PLL %d failed to lock\n", pipe);
1457 static void chv_enable_pll(struct intel_crtc *crtc,
1458 const struct intel_crtc_state *pipe_config)
1460 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1461 enum pipe pipe = crtc->pipe;
1463 assert_pipe_disabled(dev_priv, pipe);
1465 /* PLL is protected by panel, make sure we can write it */
1466 assert_panel_unlocked(dev_priv, pipe);
1468 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1469 _chv_enable_pll(crtc, pipe_config);
1471 if (pipe != PIPE_A) {
1473 * WaPixelRepeatModeFixForC0:chv
1475 * DPLLCMD is AWOL. Use chicken bits to propagate
1476 * the value from DPLLBMD to either pipe B or C.
1478 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1479 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1480 I915_WRITE(CBR4_VLV, 0);
1481 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1484 * DPLLB VGA mode also seems to cause problems.
1485 * We should always have it disabled.
1487 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1489 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1490 POSTING_READ(DPLL_MD(pipe));
1494 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1496 struct intel_crtc *crtc;
1499 for_each_intel_crtc(&dev_priv->drm, crtc) {
1500 count += crtc->base.state->active &&
1501 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1507 static void i9xx_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_state *crtc_state)
1510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1511 i915_reg_t reg = DPLL(crtc->pipe);
1512 u32 dpll = crtc_state->dpll_hw_state.dpll;
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1517 /* PLL is protected by panel, make sure we can write it */
1518 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1519 assert_panel_unlocked(dev_priv, crtc->pipe);
1521 /* Enable DVO 2x clock on both PLLs if necessary */
1522 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1524 * It appears to be important that we don't enable this
1525 * for the current pipe before otherwise configuring the
1526 * PLL. No idea how this should be handled if multiple
1527 * DVO outputs are enabled simultaneosly.
1529 dpll |= DPLL_DVO_2X_MODE;
1530 I915_WRITE(DPLL(!crtc->pipe),
1531 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1535 * Apparently we need to have VGA mode enabled prior to changing
1536 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1537 * dividers, even though the register value does change.
1541 I915_WRITE(reg, dpll);
1543 /* Wait for the clocks to stabilize. */
1547 if (INTEL_GEN(dev_priv) >= 4) {
1548 I915_WRITE(DPLL_MD(crtc->pipe),
1549 crtc_state->dpll_hw_state.dpll_md);
1551 /* The pixel multiplier can only be updated once the
1552 * DPLL is enabled and the clocks are stable.
1554 * So write it again.
1556 I915_WRITE(reg, dpll);
1559 /* We do this three times for luck */
1560 for (i = 0; i < 3; i++) {
1561 I915_WRITE(reg, dpll);
1563 udelay(150); /* wait for warmup */
1567 static void i9xx_disable_pll(struct intel_crtc *crtc)
1569 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1570 enum pipe pipe = crtc->pipe;
1572 /* Disable DVO 2x clock on both PLLs if necessary */
1573 if (IS_I830(dev_priv) &&
1574 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1575 !intel_num_dvo_pipes(dev_priv)) {
1576 I915_WRITE(DPLL(PIPE_B),
1577 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1578 I915_WRITE(DPLL(PIPE_A),
1579 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1582 /* Don't disable pipe or pipe PLLs if needed */
1583 if (IS_I830(dev_priv))
1586 /* Make sure the pipe isn't still relying on us */
1587 assert_pipe_disabled(dev_priv, pipe);
1589 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1590 POSTING_READ(DPLL(pipe));
1593 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1597 /* Make sure the pipe isn't still relying on us */
1598 assert_pipe_disabled(dev_priv, pipe);
1600 val = DPLL_INTEGRATED_REF_CLK_VLV |
1601 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1603 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1605 I915_WRITE(DPLL(pipe), val);
1606 POSTING_READ(DPLL(pipe));
1609 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1611 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1614 /* Make sure the pipe isn't still relying on us */
1615 assert_pipe_disabled(dev_priv, pipe);
1617 val = DPLL_SSC_REF_CLK_CHV |
1618 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1620 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1622 I915_WRITE(DPLL(pipe), val);
1623 POSTING_READ(DPLL(pipe));
1625 mutex_lock(&dev_priv->sb_lock);
1627 /* Disable 10bit clock to display controller */
1628 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1629 val &= ~DPIO_DCLKP_EN;
1630 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1632 mutex_unlock(&dev_priv->sb_lock);
1635 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1636 struct intel_digital_port *dport,
1637 unsigned int expected_mask)
1640 i915_reg_t dpll_reg;
1642 switch (dport->base.port) {
1644 port_mask = DPLL_PORTB_READY_MASK;
1648 port_mask = DPLL_PORTC_READY_MASK;
1650 expected_mask <<= 4;
1653 port_mask = DPLL_PORTD_READY_MASK;
1654 dpll_reg = DPIO_PHY_STATUS;
1660 if (intel_wait_for_register(dev_priv,
1661 dpll_reg, port_mask, expected_mask,
1663 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1664 port_name(dport->base.port),
1665 I915_READ(dpll_reg) & port_mask, expected_mask);
1668 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1671 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1674 uint32_t val, pipeconf_val;
1676 /* Make sure PCH DPLL is enabled */
1677 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1679 /* FDI must be feeding us bits for PCH ports */
1680 assert_fdi_tx_enabled(dev_priv, pipe);
1681 assert_fdi_rx_enabled(dev_priv, pipe);
1683 if (HAS_PCH_CPT(dev_priv)) {
1684 /* Workaround: Set the timing override bit before enabling the
1685 * pch transcoder. */
1686 reg = TRANS_CHICKEN2(pipe);
1687 val = I915_READ(reg);
1688 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1689 I915_WRITE(reg, val);
1692 reg = PCH_TRANSCONF(pipe);
1693 val = I915_READ(reg);
1694 pipeconf_val = I915_READ(PIPECONF(pipe));
1696 if (HAS_PCH_IBX(dev_priv)) {
1698 * Make the BPC in transcoder be consistent with
1699 * that in pipeconf reg. For HDMI we must use 8bpc
1700 * here for both 8bpc and 12bpc.
1702 val &= ~PIPECONF_BPC_MASK;
1703 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1704 val |= PIPECONF_8BPC;
1706 val |= pipeconf_val & PIPECONF_BPC_MASK;
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711 if (HAS_PCH_IBX(dev_priv) &&
1712 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1715 val |= TRANS_INTERLACED;
1717 val |= TRANS_PROGRESSIVE;
1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (intel_wait_for_register(dev_priv,
1721 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1723 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1726 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1727 enum transcoder cpu_transcoder)
1729 u32 val, pipeconf_val;
1731 /* FDI must be feeding us bits for PCH ports */
1732 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1733 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1735 /* Workaround: set timing override bit. */
1736 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1737 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1738 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1741 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1743 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1744 PIPECONF_INTERLACED_ILK)
1745 val |= TRANS_INTERLACED;
1747 val |= TRANS_PROGRESSIVE;
1749 I915_WRITE(LPT_TRANSCONF, val);
1750 if (intel_wait_for_register(dev_priv,
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1771 reg = PCH_TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (intel_wait_for_register(dev_priv,
1777 reg, TRANS_STATE_ENABLE, 0,
1779 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1781 if (HAS_PCH_CPT(dev_priv)) {
1782 /* Workaround: Clear the timing override chicken bit again. */
1783 reg = TRANS_CHICKEN2(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1786 I915_WRITE(reg, val);
1790 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1794 val = I915_READ(LPT_TRANSCONF);
1795 val &= ~TRANS_ENABLE;
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 /* wait for PCH transcoder off, transcoder state */
1798 if (intel_wait_for_register(dev_priv,
1799 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1801 DRM_ERROR("Failed to disable PCH transcoder\n");
1803 /* Workaround: clear timing override bit. */
1804 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1805 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1806 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1809 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1811 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1813 if (HAS_PCH_LPT(dev_priv))
1819 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1821 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1824 enum pipe pipe = crtc->pipe;
1828 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1830 assert_planes_disabled(crtc);
1833 * A pipe without a PLL won't actually be able to drive bits from
1834 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1837 if (HAS_GMCH_DISPLAY(dev_priv)) {
1838 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1839 assert_dsi_pll_enabled(dev_priv);
1841 assert_pll_enabled(dev_priv, pipe);
1843 if (new_crtc_state->has_pch_encoder) {
1844 /* if driving the PCH, we need FDI enabled */
1845 assert_fdi_rx_pll_enabled(dev_priv,
1846 intel_crtc_pch_transcoder(crtc));
1847 assert_fdi_tx_pll_enabled(dev_priv,
1848 (enum pipe) cpu_transcoder);
1850 /* FIXME: assert CPU port conditions for SNB+ */
1853 reg = PIPECONF(cpu_transcoder);
1854 val = I915_READ(reg);
1855 if (val & PIPECONF_ENABLE) {
1856 /* we keep both pipes enabled on 830 */
1857 WARN_ON(!IS_I830(dev_priv));
1861 I915_WRITE(reg, val | PIPECONF_ENABLE);
1865 * Until the pipe starts PIPEDSL reads will return a stale value,
1866 * which causes an apparent vblank timestamp jump when PIPEDSL
1867 * resets to its proper value. That also messes up the frame count
1868 * when it's derived from the timestamps. So let's wait for the
1869 * pipe to start properly before we call drm_crtc_vblank_on()
1871 if (dev_priv->drm.max_vblank_count == 0)
1872 intel_wait_for_pipe_scanline_moving(crtc);
1875 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1877 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1879 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1880 enum pipe pipe = crtc->pipe;
1884 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1887 * Make sure planes won't keep trying to pump pixels to us,
1888 * or we might hang the display.
1890 assert_planes_disabled(crtc);
1892 reg = PIPECONF(cpu_transcoder);
1893 val = I915_READ(reg);
1894 if ((val & PIPECONF_ENABLE) == 0)
1898 * Double wide has implications for planes
1899 * so best keep it disabled when not needed.
1901 if (old_crtc_state->double_wide)
1902 val &= ~PIPECONF_DOUBLE_WIDE;
1904 /* Don't disable pipe or pipe PLLs if needed */
1905 if (!IS_I830(dev_priv))
1906 val &= ~PIPECONF_ENABLE;
1908 I915_WRITE(reg, val);
1909 if ((val & PIPECONF_ENABLE) == 0)
1910 intel_wait_for_pipe_off(old_crtc_state);
1913 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1915 return IS_GEN2(dev_priv) ? 2048 : 4096;
1919 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1921 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1922 unsigned int cpp = fb->format->cpp[plane];
1924 switch (fb->modifier) {
1925 case DRM_FORMAT_MOD_LINEAR:
1927 case I915_FORMAT_MOD_X_TILED:
1928 if (IS_GEN2(dev_priv))
1932 case I915_FORMAT_MOD_Y_TILED_CCS:
1936 case I915_FORMAT_MOD_Y_TILED:
1937 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1941 case I915_FORMAT_MOD_Yf_TILED_CCS:
1945 case I915_FORMAT_MOD_Yf_TILED:
1961 MISSING_CASE(fb->modifier);
1967 intel_tile_height(const struct drm_framebuffer *fb, int plane)
1969 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1972 return intel_tile_size(to_i915(fb->dev)) /
1973 intel_tile_width_bytes(fb, plane);
1976 /* Return the tile dimensions in pixel units */
1977 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
1978 unsigned int *tile_width,
1979 unsigned int *tile_height)
1981 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
1982 unsigned int cpp = fb->format->cpp[plane];
1984 *tile_width = tile_width_bytes / cpp;
1985 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1989 intel_fb_align_height(const struct drm_framebuffer *fb,
1990 int plane, unsigned int height)
1992 unsigned int tile_height = intel_tile_height(fb, plane);
1994 return ALIGN(height, tile_height);
1997 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1999 unsigned int size = 0;
2002 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2003 size += rot_info->plane[i].width * rot_info->plane[i].height;
2009 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2010 const struct drm_framebuffer *fb,
2011 unsigned int rotation)
2013 view->type = I915_GGTT_VIEW_NORMAL;
2014 if (drm_rotation_90_or_270(rotation)) {
2015 view->type = I915_GGTT_VIEW_ROTATED;
2016 view->rotated = to_intel_framebuffer(fb)->rot_info;
2020 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2022 if (IS_I830(dev_priv))
2024 else if (IS_I85X(dev_priv))
2026 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2032 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2034 if (INTEL_GEN(dev_priv) >= 9)
2036 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2037 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2039 else if (INTEL_GEN(dev_priv) >= 4)
2045 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2048 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2050 /* AUX_DIST needs only 4K alignment */
2054 switch (fb->modifier) {
2055 case DRM_FORMAT_MOD_LINEAR:
2056 return intel_linear_alignment(dev_priv);
2057 case I915_FORMAT_MOD_X_TILED:
2058 if (INTEL_GEN(dev_priv) >= 9)
2061 case I915_FORMAT_MOD_Y_TILED_CCS:
2062 case I915_FORMAT_MOD_Yf_TILED_CCS:
2063 case I915_FORMAT_MOD_Y_TILED:
2064 case I915_FORMAT_MOD_Yf_TILED:
2065 return 1 * 1024 * 1024;
2067 MISSING_CASE(fb->modifier);
2072 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2074 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2075 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2077 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2081 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2082 unsigned int rotation,
2084 unsigned long *out_flags)
2086 struct drm_device *dev = fb->dev;
2087 struct drm_i915_private *dev_priv = to_i915(dev);
2088 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2089 struct i915_ggtt_view view;
2090 struct i915_vma *vma;
2091 unsigned int pinctl;
2094 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2096 alignment = intel_surf_alignment(fb, 0);
2098 intel_fill_fb_ggtt_view(&view, fb, rotation);
2100 /* Note that the w/a also requires 64 PTE of padding following the
2101 * bo. We currently fill all unused PTE with the shadow page and so
2102 * we should always have valid PTE following the scanout preventing
2105 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2106 alignment = 256 * 1024;
2109 * Global gtt pte registers are special registers which actually forward
2110 * writes to a chunk of system memory. Which means that there is no risk
2111 * that the register values disappear as soon as we call
2112 * intel_runtime_pm_put(), so it is correct to wrap only the
2113 * pin/unpin/fence and not more.
2115 intel_runtime_pm_get(dev_priv);
2117 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2121 /* Valleyview is definitely limited to scanning out the first
2122 * 512MiB. Lets presume this behaviour was inherited from the
2123 * g4x display engine and that all earlier gen are similarly
2124 * limited. Testing suggests that it is a little more
2125 * complicated than this. For example, Cherryview appears quite
2126 * happy to scanout from anywhere within its global aperture.
2128 if (HAS_GMCH_DISPLAY(dev_priv))
2129 pinctl |= PIN_MAPPABLE;
2131 vma = i915_gem_object_pin_to_display_plane(obj,
2132 alignment, &view, pinctl);
2136 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2139 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2140 * fence, whereas 965+ only requires a fence if using
2141 * framebuffer compression. For simplicity, we always, when
2142 * possible, install a fence as the cost is not that onerous.
2144 * If we fail to fence the tiled scanout, then either the
2145 * modeset will reject the change (which is highly unlikely as
2146 * the affected systems, all but one, do not have unmappable
2147 * space) or we will not be able to enable full powersaving
2148 * techniques (also likely not to apply due to various limits
2149 * FBC and the like impose on the size of the buffer, which
2150 * presumably we violated anyway with this unmappable buffer).
2151 * Anyway, it is presumably better to stumble onwards with
2152 * something and try to run the system in a "less than optimal"
2153 * mode that matches the user configuration.
2155 ret = i915_vma_pin_fence(vma);
2156 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2157 i915_gem_object_unpin_from_display_plane(vma);
2162 if (ret == 0 && vma->fence)
2163 *out_flags |= PLANE_HAS_FENCE;
2168 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2170 intel_runtime_pm_put(dev_priv);
2174 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2176 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2178 if (flags & PLANE_HAS_FENCE)
2179 i915_vma_unpin_fence(vma);
2180 i915_gem_object_unpin_from_display_plane(vma);
2184 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2185 unsigned int rotation)
2187 if (drm_rotation_90_or_270(rotation))
2188 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2190 return fb->pitches[plane];
2194 * Convert the x/y offsets into a linear offset.
2195 * Only valid with 0/180 degree rotation, which is fine since linear
2196 * offset is only used with linear buffers on pre-hsw and tiled buffers
2197 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2199 u32 intel_fb_xy_to_linear(int x, int y,
2200 const struct intel_plane_state *state,
2203 const struct drm_framebuffer *fb = state->base.fb;
2204 unsigned int cpp = fb->format->cpp[plane];
2205 unsigned int pitch = fb->pitches[plane];
2207 return y * pitch + x * cpp;
2211 * Add the x/y offsets derived from fb->offsets[] to the user
2212 * specified plane src x/y offsets. The resulting x/y offsets
2213 * specify the start of scanout from the beginning of the gtt mapping.
2215 void intel_add_fb_offsets(int *x, int *y,
2216 const struct intel_plane_state *state,
2220 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2221 unsigned int rotation = state->base.rotation;
2223 if (drm_rotation_90_or_270(rotation)) {
2224 *x += intel_fb->rotated[plane].x;
2225 *y += intel_fb->rotated[plane].y;
2227 *x += intel_fb->normal[plane].x;
2228 *y += intel_fb->normal[plane].y;
2232 static u32 __intel_adjust_tile_offset(int *x, int *y,
2233 unsigned int tile_width,
2234 unsigned int tile_height,
2235 unsigned int tile_size,
2236 unsigned int pitch_tiles,
2240 unsigned int pitch_pixels = pitch_tiles * tile_width;
2243 WARN_ON(old_offset & (tile_size - 1));
2244 WARN_ON(new_offset & (tile_size - 1));
2245 WARN_ON(new_offset > old_offset);
2247 tiles = (old_offset - new_offset) / tile_size;
2249 *y += tiles / pitch_tiles * tile_height;
2250 *x += tiles % pitch_tiles * tile_width;
2252 /* minimize x in case it got needlessly big */
2253 *y += *x / pitch_pixels * tile_height;
2259 static u32 _intel_adjust_tile_offset(int *x, int *y,
2260 const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation,
2262 u32 old_offset, u32 new_offset)
2264 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2265 unsigned int cpp = fb->format->cpp[plane];
2266 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2268 WARN_ON(new_offset > old_offset);
2270 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2271 unsigned int tile_size, tile_width, tile_height;
2272 unsigned int pitch_tiles;
2274 tile_size = intel_tile_size(dev_priv);
2275 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2277 if (drm_rotation_90_or_270(rotation)) {
2278 pitch_tiles = pitch / tile_height;
2279 swap(tile_width, tile_height);
2281 pitch_tiles = pitch / (tile_width * cpp);
2284 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2285 tile_size, pitch_tiles,
2286 old_offset, new_offset);
2288 old_offset += *y * pitch + *x * cpp;
2290 *y = (old_offset - new_offset) / pitch;
2291 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2298 * Adjust the tile offset by moving the difference into
2301 static u32 intel_adjust_tile_offset(int *x, int *y,
2302 const struct intel_plane_state *state, int plane,
2303 u32 old_offset, u32 new_offset)
2305 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2306 state->base.rotation,
2307 old_offset, new_offset);
2311 * Computes the linear offset to the base tile and adjusts
2312 * x, y. bytes per pixel is assumed to be a power-of-two.
2314 * In the 90/270 rotated case, x and y are assumed
2315 * to be already rotated to match the rotated GTT view, and
2316 * pitch is the tile_height aligned framebuffer height.
2318 * This function is used when computing the derived information
2319 * under intel_framebuffer, so using any of that information
2320 * here is not allowed. Anything under drm_framebuffer can be
2321 * used. This is why the user has to pass in the pitch since it
2322 * is specified in the rotated orientation.
2324 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2326 const struct drm_framebuffer *fb, int plane,
2328 unsigned int rotation,
2331 uint64_t fb_modifier = fb->modifier;
2332 unsigned int cpp = fb->format->cpp[plane];
2333 u32 offset, offset_aligned;
2338 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2339 unsigned int tile_size, tile_width, tile_height;
2340 unsigned int tile_rows, tiles, pitch_tiles;
2342 tile_size = intel_tile_size(dev_priv);
2343 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2345 if (drm_rotation_90_or_270(rotation)) {
2346 pitch_tiles = pitch / tile_height;
2347 swap(tile_width, tile_height);
2349 pitch_tiles = pitch / (tile_width * cpp);
2352 tile_rows = *y / tile_height;
2355 tiles = *x / tile_width;
2358 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2359 offset_aligned = offset & ~alignment;
2361 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2362 tile_size, pitch_tiles,
2363 offset, offset_aligned);
2365 offset = *y * pitch + *x * cpp;
2366 offset_aligned = offset & ~alignment;
2368 *y = (offset & alignment) / pitch;
2369 *x = ((offset & alignment) - *y * pitch) / cpp;
2372 return offset_aligned;
2375 u32 intel_compute_tile_offset(int *x, int *y,
2376 const struct intel_plane_state *state,
2379 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2380 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2381 const struct drm_framebuffer *fb = state->base.fb;
2382 unsigned int rotation = state->base.rotation;
2383 int pitch = intel_fb_pitch(fb, plane, rotation);
2386 if (intel_plane->id == PLANE_CURSOR)
2387 alignment = intel_cursor_alignment(dev_priv);
2389 alignment = intel_surf_alignment(fb, plane);
2391 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2392 rotation, alignment);
2395 /* Convert the fb->offset[] into x/y offsets */
2396 static int intel_fb_offset_to_xy(int *x, int *y,
2397 const struct drm_framebuffer *fb, int plane)
2399 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2401 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2402 fb->offsets[plane] % intel_tile_size(dev_priv))
2408 _intel_adjust_tile_offset(x, y,
2409 fb, plane, DRM_MODE_ROTATE_0,
2410 fb->offsets[plane], 0);
2415 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2417 switch (fb_modifier) {
2418 case I915_FORMAT_MOD_X_TILED:
2419 return I915_TILING_X;
2420 case I915_FORMAT_MOD_Y_TILED:
2421 case I915_FORMAT_MOD_Y_TILED_CCS:
2422 return I915_TILING_Y;
2424 return I915_TILING_NONE;
2429 * From the Sky Lake PRM:
2430 * "The Color Control Surface (CCS) contains the compression status of
2431 * the cache-line pairs. The compression state of the cache-line pair
2432 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2433 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2434 * cache-line-pairs. CCS is always Y tiled."
2436 * Since cache line pairs refers to horizontally adjacent cache lines,
2437 * each cache line in the CCS corresponds to an area of 32x16 cache
2438 * lines on the main surface. Since each pixel is 4 bytes, this gives
2439 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2442 static const struct drm_format_info ccs_formats[] = {
2443 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2444 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2445 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2446 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2449 static const struct drm_format_info *
2450 lookup_format_info(const struct drm_format_info formats[],
2451 int num_formats, u32 format)
2455 for (i = 0; i < num_formats; i++) {
2456 if (formats[i].format == format)
2463 static const struct drm_format_info *
2464 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2466 switch (cmd->modifier[0]) {
2467 case I915_FORMAT_MOD_Y_TILED_CCS:
2468 case I915_FORMAT_MOD_Yf_TILED_CCS:
2469 return lookup_format_info(ccs_formats,
2470 ARRAY_SIZE(ccs_formats),
2478 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2479 struct drm_framebuffer *fb)
2481 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2482 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2483 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2484 u32 gtt_offset_rotated = 0;
2485 unsigned int max_size = 0;
2486 int i, num_planes = fb->format->num_planes;
2487 unsigned int tile_size = intel_tile_size(dev_priv);
2489 for (i = 0; i < num_planes; i++) {
2490 unsigned int width, height;
2491 unsigned int cpp, size;
2496 cpp = fb->format->cpp[i];
2497 width = drm_framebuffer_plane_width(fb->width, fb, i);
2498 height = drm_framebuffer_plane_height(fb->height, fb, i);
2500 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2502 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2507 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2508 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2509 int hsub = fb->format->hsub;
2510 int vsub = fb->format->vsub;
2511 int tile_width, tile_height;
2515 intel_tile_dims(fb, i, &tile_width, &tile_height);
2517 tile_height *= vsub;
2519 ccs_x = (x * hsub) % tile_width;
2520 ccs_y = (y * vsub) % tile_height;
2521 main_x = intel_fb->normal[0].x % tile_width;
2522 main_y = intel_fb->normal[0].y % tile_height;
2525 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2526 * x/y offsets must match between CCS and the main surface.
2528 if (main_x != ccs_x || main_y != ccs_y) {
2529 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2532 intel_fb->normal[0].x,
2533 intel_fb->normal[0].y,
2540 * The fence (if used) is aligned to the start of the object
2541 * so having the framebuffer wrap around across the edge of the
2542 * fenced region doesn't really work. We have no API to configure
2543 * the fence start offset within the object (nor could we probably
2544 * on gen2/3). So it's just easier if we just require that the
2545 * fb layout agrees with the fence layout. We already check that the
2546 * fb stride matches the fence stride elsewhere.
2548 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2549 (x + width) * cpp > fb->pitches[i]) {
2550 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2556 * First pixel of the framebuffer from
2557 * the start of the normal gtt mapping.
2559 intel_fb->normal[i].x = x;
2560 intel_fb->normal[i].y = y;
2562 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2563 fb, i, fb->pitches[i],
2564 DRM_MODE_ROTATE_0, tile_size);
2565 offset /= tile_size;
2567 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2568 unsigned int tile_width, tile_height;
2569 unsigned int pitch_tiles;
2572 intel_tile_dims(fb, i, &tile_width, &tile_height);
2574 rot_info->plane[i].offset = offset;
2575 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2576 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2577 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2579 intel_fb->rotated[i].pitch =
2580 rot_info->plane[i].height * tile_height;
2582 /* how many tiles does this plane need */
2583 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2585 * If the plane isn't horizontally tile aligned,
2586 * we need one more tile.
2591 /* rotate the x/y offsets to match the GTT view */
2597 rot_info->plane[i].width * tile_width,
2598 rot_info->plane[i].height * tile_height,
2599 DRM_MODE_ROTATE_270);
2603 /* rotate the tile dimensions to match the GTT view */
2604 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2605 swap(tile_width, tile_height);
2608 * We only keep the x/y offsets, so push all of the
2609 * gtt offset into the x/y offsets.
2611 __intel_adjust_tile_offset(&x, &y,
2612 tile_width, tile_height,
2613 tile_size, pitch_tiles,
2614 gtt_offset_rotated * tile_size, 0);
2616 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2619 * First pixel of the framebuffer from
2620 * the start of the rotated gtt mapping.
2622 intel_fb->rotated[i].x = x;
2623 intel_fb->rotated[i].y = y;
2625 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2626 x * cpp, tile_size);
2629 /* how many tiles in total needed in the bo */
2630 max_size = max(max_size, offset + size);
2633 if (max_size * tile_size > obj->base.size) {
2634 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2635 max_size * tile_size, obj->base.size);
2642 static int i9xx_format_to_fourcc(int format)
2645 case DISPPLANE_8BPP:
2646 return DRM_FORMAT_C8;
2647 case DISPPLANE_BGRX555:
2648 return DRM_FORMAT_XRGB1555;
2649 case DISPPLANE_BGRX565:
2650 return DRM_FORMAT_RGB565;
2652 case DISPPLANE_BGRX888:
2653 return DRM_FORMAT_XRGB8888;
2654 case DISPPLANE_RGBX888:
2655 return DRM_FORMAT_XBGR8888;
2656 case DISPPLANE_BGRX101010:
2657 return DRM_FORMAT_XRGB2101010;
2658 case DISPPLANE_RGBX101010:
2659 return DRM_FORMAT_XBGR2101010;
2663 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2666 case PLANE_CTL_FORMAT_RGB_565:
2667 return DRM_FORMAT_RGB565;
2668 case PLANE_CTL_FORMAT_NV12:
2669 return DRM_FORMAT_NV12;
2671 case PLANE_CTL_FORMAT_XRGB_8888:
2674 return DRM_FORMAT_ABGR8888;
2676 return DRM_FORMAT_XBGR8888;
2679 return DRM_FORMAT_ARGB8888;
2681 return DRM_FORMAT_XRGB8888;
2683 case PLANE_CTL_FORMAT_XRGB_2101010:
2685 return DRM_FORMAT_XBGR2101010;
2687 return DRM_FORMAT_XRGB2101010;
2692 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2693 struct intel_initial_plane_config *plane_config)
2695 struct drm_device *dev = crtc->base.dev;
2696 struct drm_i915_private *dev_priv = to_i915(dev);
2697 struct drm_i915_gem_object *obj = NULL;
2698 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2699 struct drm_framebuffer *fb = &plane_config->fb->base;
2700 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2701 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2704 size_aligned -= base_aligned;
2706 if (plane_config->size == 0)
2709 /* If the FB is too big, just don't use it since fbdev is not very
2710 * important and we should probably use that space with FBC or other
2712 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2715 mutex_lock(&dev->struct_mutex);
2716 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2720 mutex_unlock(&dev->struct_mutex);
2724 if (plane_config->tiling == I915_TILING_X)
2725 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2727 mode_cmd.pixel_format = fb->format->format;
2728 mode_cmd.width = fb->width;
2729 mode_cmd.height = fb->height;
2730 mode_cmd.pitches[0] = fb->pitches[0];
2731 mode_cmd.modifier[0] = fb->modifier;
2732 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2734 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2735 DRM_DEBUG_KMS("intel fb init failed\n");
2740 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2744 i915_gem_object_put(obj);
2749 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2750 struct intel_plane_state *plane_state,
2753 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2755 plane_state->base.visible = visible;
2757 /* FIXME pre-g4x don't work like this */
2759 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2760 crtc_state->active_planes |= BIT(plane->id);
2762 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2763 crtc_state->active_planes &= ~BIT(plane->id);
2766 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2767 crtc_state->base.crtc->name,
2768 crtc_state->active_planes);
2771 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2772 struct intel_plane *plane)
2774 struct intel_crtc_state *crtc_state =
2775 to_intel_crtc_state(crtc->base.state);
2776 struct intel_plane_state *plane_state =
2777 to_intel_plane_state(plane->base.state);
2779 intel_set_plane_visible(crtc_state, plane_state, false);
2781 if (plane->id == PLANE_PRIMARY)
2782 intel_pre_disable_primary_noatomic(&crtc->base);
2784 trace_intel_disable_plane(&plane->base, crtc);
2785 plane->disable_plane(plane, crtc);
2789 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2790 struct intel_initial_plane_config *plane_config)
2792 struct drm_device *dev = intel_crtc->base.dev;
2793 struct drm_i915_private *dev_priv = to_i915(dev);
2795 struct drm_i915_gem_object *obj;
2796 struct drm_plane *primary = intel_crtc->base.primary;
2797 struct drm_plane_state *plane_state = primary->state;
2798 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2799 struct intel_plane *intel_plane = to_intel_plane(primary);
2800 struct intel_plane_state *intel_state =
2801 to_intel_plane_state(plane_state);
2802 struct drm_framebuffer *fb;
2804 if (!plane_config->fb)
2807 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2808 fb = &plane_config->fb->base;
2812 kfree(plane_config->fb);
2815 * Failed to alloc the obj, check to see if we should share
2816 * an fb with another CRTC instead
2818 for_each_crtc(dev, c) {
2819 struct intel_plane_state *state;
2821 if (c == &intel_crtc->base)
2824 if (!to_intel_crtc(c)->active)
2827 state = to_intel_plane_state(c->primary->state);
2831 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2832 fb = state->base.fb;
2833 drm_framebuffer_get(fb);
2839 * We've failed to reconstruct the BIOS FB. Current display state
2840 * indicates that the primary plane is visible, but has a NULL FB,
2841 * which will lead to problems later if we don't fix it up. The
2842 * simplest solution is to just disable the primary plane now and
2843 * pretend the BIOS never had it enabled.
2845 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2850 mutex_lock(&dev->struct_mutex);
2852 intel_pin_and_fence_fb_obj(fb,
2853 primary->state->rotation,
2854 intel_plane_uses_fence(intel_state),
2855 &intel_state->flags);
2856 mutex_unlock(&dev->struct_mutex);
2857 if (IS_ERR(intel_state->vma)) {
2858 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2859 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2861 intel_state->vma = NULL;
2862 drm_framebuffer_put(fb);
2866 obj = intel_fb_obj(fb);
2867 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2869 plane_state->src_x = 0;
2870 plane_state->src_y = 0;
2871 plane_state->src_w = fb->width << 16;
2872 plane_state->src_h = fb->height << 16;
2874 plane_state->crtc_x = 0;
2875 plane_state->crtc_y = 0;
2876 plane_state->crtc_w = fb->width;
2877 plane_state->crtc_h = fb->height;
2879 intel_state->base.src = drm_plane_state_src(plane_state);
2880 intel_state->base.dst = drm_plane_state_dest(plane_state);
2882 if (i915_gem_object_is_tiled(obj))
2883 dev_priv->preserve_bios_swizzle = true;
2885 drm_framebuffer_get(fb);
2886 primary->fb = primary->state->fb = fb;
2887 primary->crtc = primary->state->crtc = &intel_crtc->base;
2889 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2890 to_intel_plane_state(plane_state),
2893 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2894 &obj->frontbuffer_bits);
2897 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2898 unsigned int rotation)
2900 int cpp = fb->format->cpp[plane];
2902 switch (fb->modifier) {
2903 case DRM_FORMAT_MOD_LINEAR:
2904 case I915_FORMAT_MOD_X_TILED:
2917 case I915_FORMAT_MOD_Y_TILED_CCS:
2918 case I915_FORMAT_MOD_Yf_TILED_CCS:
2919 /* FIXME AUX plane? */
2920 case I915_FORMAT_MOD_Y_TILED:
2921 case I915_FORMAT_MOD_Yf_TILED:
2936 MISSING_CASE(fb->modifier);
2942 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2943 int main_x, int main_y, u32 main_offset)
2945 const struct drm_framebuffer *fb = plane_state->base.fb;
2946 int hsub = fb->format->hsub;
2947 int vsub = fb->format->vsub;
2948 int aux_x = plane_state->aux.x;
2949 int aux_y = plane_state->aux.y;
2950 u32 aux_offset = plane_state->aux.offset;
2951 u32 alignment = intel_surf_alignment(fb, 1);
2953 while (aux_offset >= main_offset && aux_y <= main_y) {
2956 if (aux_x == main_x && aux_y == main_y)
2959 if (aux_offset == 0)
2964 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2965 aux_offset, aux_offset - alignment);
2966 aux_x = x * hsub + aux_x % hsub;
2967 aux_y = y * vsub + aux_y % vsub;
2970 if (aux_x != main_x || aux_y != main_y)
2973 plane_state->aux.offset = aux_offset;
2974 plane_state->aux.x = aux_x;
2975 plane_state->aux.y = aux_y;
2980 static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
2981 struct intel_plane_state *plane_state)
2983 struct drm_i915_private *dev_priv =
2984 to_i915(plane_state->base.plane->dev);
2985 const struct drm_framebuffer *fb = plane_state->base.fb;
2986 unsigned int rotation = plane_state->base.rotation;
2987 int x = plane_state->base.src.x1 >> 16;
2988 int y = plane_state->base.src.y1 >> 16;
2989 int w = drm_rect_width(&plane_state->base.src) >> 16;
2990 int h = drm_rect_height(&plane_state->base.src) >> 16;
2991 int dst_x = plane_state->base.dst.x1;
2992 int pipe_src_w = crtc_state->pipe_src_w;
2993 int max_width = skl_max_plane_width(fb, 0, rotation);
2994 int max_height = 4096;
2995 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2997 if (w > max_width || h > max_height) {
2998 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2999 w, h, max_width, max_height);
3004 * Display WA #1175: cnl,glk
3005 * Planes other than the cursor may cause FIFO underflow and display
3006 * corruption if starting less than 4 pixels from the right edge of
3008 * Besides the above WA fix the similar problem, where planes other
3009 * than the cursor ending less than 4 pixels from the left edge of the
3010 * screen may cause FIFO underflow and display corruption.
3012 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3013 (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
3014 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
3015 dst_x + w < 4 ? "end" : "start",
3016 dst_x + w < 4 ? dst_x + w : dst_x,
3021 intel_add_fb_offsets(&x, &y, plane_state, 0);
3022 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3023 alignment = intel_surf_alignment(fb, 0);
3026 * AUX surface offset is specified as the distance from the
3027 * main surface offset, and it must be non-negative. Make
3028 * sure that is what we will get.
3030 if (offset > aux_offset)
3031 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3032 offset, aux_offset & ~(alignment - 1));
3035 * When using an X-tiled surface, the plane blows up
3036 * if the x offset + width exceed the stride.
3038 * TODO: linear and Y-tiled seem fine, Yf untested,
3040 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3041 int cpp = fb->format->cpp[0];
3043 while ((x + w) * cpp > fb->pitches[0]) {
3045 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3049 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3050 offset, offset - alignment);
3055 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3056 * they match with the main surface x/y offsets.
3058 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3059 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3060 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3064 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3065 offset, offset - alignment);
3068 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3069 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3074 plane_state->main.offset = offset;
3075 plane_state->main.x = x;
3076 plane_state->main.y = y;
3082 skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
3083 struct intel_plane_state *plane_state)
3085 /* Display WA #1106 */
3086 if (plane_state->base.rotation !=
3087 (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90) &&
3088 plane_state->base.rotation != DRM_MODE_ROTATE_270)
3092 * src coordinates are rotated here.
3093 * We check height but report it as width
3095 if (((drm_rect_height(&plane_state->base.src) >> 16) % 4) != 0) {
3096 DRM_DEBUG_KMS("src width must be multiple "
3097 "of 4 for rotated NV12\n");
3104 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3106 const struct drm_framebuffer *fb = plane_state->base.fb;
3107 unsigned int rotation = plane_state->base.rotation;
3108 int max_width = skl_max_plane_width(fb, 1, rotation);
3109 int max_height = 4096;
3110 int x = plane_state->base.src.x1 >> 17;
3111 int y = plane_state->base.src.y1 >> 17;
3112 int w = drm_rect_width(&plane_state->base.src) >> 17;
3113 int h = drm_rect_height(&plane_state->base.src) >> 17;
3116 intel_add_fb_offsets(&x, &y, plane_state, 1);
3117 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3119 /* FIXME not quite sure how/if these apply to the chroma plane */
3120 if (w > max_width || h > max_height) {
3121 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3122 w, h, max_width, max_height);
3126 plane_state->aux.offset = offset;
3127 plane_state->aux.x = x;
3128 plane_state->aux.y = y;
3133 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3135 const struct drm_framebuffer *fb = plane_state->base.fb;
3136 int src_x = plane_state->base.src.x1 >> 16;
3137 int src_y = plane_state->base.src.y1 >> 16;
3138 int hsub = fb->format->hsub;
3139 int vsub = fb->format->vsub;
3140 int x = src_x / hsub;
3141 int y = src_y / vsub;
3144 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3145 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3146 plane_state->base.rotation);
3150 intel_add_fb_offsets(&x, &y, plane_state, 1);
3151 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3153 plane_state->aux.offset = offset;
3154 plane_state->aux.x = x * hsub + src_x % hsub;
3155 plane_state->aux.y = y * vsub + src_y % vsub;
3160 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
3161 struct intel_plane_state *plane_state)
3163 const struct drm_framebuffer *fb = plane_state->base.fb;
3164 unsigned int rotation = plane_state->base.rotation;
3167 if (rotation & DRM_MODE_REFLECT_X &&
3168 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
3169 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
3173 if (!plane_state->base.visible)
3176 /* Rotate src coordinates to match rotated GTT view */
3177 if (drm_rotation_90_or_270(rotation))
3178 drm_rect_rotate(&plane_state->base.src,
3179 fb->width << 16, fb->height << 16,
3180 DRM_MODE_ROTATE_270);
3183 * Handle the AUX surface first since
3184 * the main surface setup depends on it.
3186 if (fb->format->format == DRM_FORMAT_NV12) {
3187 ret = skl_check_nv12_surface(crtc_state, plane_state);
3190 ret = skl_check_nv12_aux_surface(plane_state);
3193 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3194 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3195 ret = skl_check_ccs_aux_surface(plane_state);
3199 plane_state->aux.offset = ~0xfff;
3200 plane_state->aux.x = 0;
3201 plane_state->aux.y = 0;
3204 ret = skl_check_main_surface(crtc_state, plane_state);
3211 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3212 const struct intel_plane_state *plane_state)
3214 struct drm_i915_private *dev_priv =
3215 to_i915(plane_state->base.plane->dev);
3216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3217 const struct drm_framebuffer *fb = plane_state->base.fb;
3218 unsigned int rotation = plane_state->base.rotation;
3221 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3223 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3224 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3225 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3227 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3228 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3230 if (INTEL_GEN(dev_priv) < 5)
3231 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3233 switch (fb->format->format) {
3235 dspcntr |= DISPPLANE_8BPP;
3237 case DRM_FORMAT_XRGB1555:
3238 dspcntr |= DISPPLANE_BGRX555;
3240 case DRM_FORMAT_RGB565:
3241 dspcntr |= DISPPLANE_BGRX565;
3243 case DRM_FORMAT_XRGB8888:
3244 dspcntr |= DISPPLANE_BGRX888;
3246 case DRM_FORMAT_XBGR8888:
3247 dspcntr |= DISPPLANE_RGBX888;
3249 case DRM_FORMAT_XRGB2101010:
3250 dspcntr |= DISPPLANE_BGRX101010;
3252 case DRM_FORMAT_XBGR2101010:
3253 dspcntr |= DISPPLANE_RGBX101010;
3256 MISSING_CASE(fb->format->format);
3260 if (INTEL_GEN(dev_priv) >= 4 &&
3261 fb->modifier == I915_FORMAT_MOD_X_TILED)
3262 dspcntr |= DISPPLANE_TILED;
3264 if (rotation & DRM_MODE_ROTATE_180)
3265 dspcntr |= DISPPLANE_ROTATE_180;
3267 if (rotation & DRM_MODE_REFLECT_X)
3268 dspcntr |= DISPPLANE_MIRROR;
3273 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3275 struct drm_i915_private *dev_priv =
3276 to_i915(plane_state->base.plane->dev);
3277 int src_x = plane_state->base.src.x1 >> 16;
3278 int src_y = plane_state->base.src.y1 >> 16;
3281 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3283 if (INTEL_GEN(dev_priv) >= 4)
3284 offset = intel_compute_tile_offset(&src_x, &src_y,
3289 /* HSW/BDW do this automagically in hardware */
3290 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3291 unsigned int rotation = plane_state->base.rotation;
3292 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3293 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3295 if (rotation & DRM_MODE_ROTATE_180) {
3298 } else if (rotation & DRM_MODE_REFLECT_X) {
3303 plane_state->main.offset = offset;
3304 plane_state->main.x = src_x;
3305 plane_state->main.y = src_y;
3310 static void i9xx_update_plane(struct intel_plane *plane,
3311 const struct intel_crtc_state *crtc_state,
3312 const struct intel_plane_state *plane_state)
3314 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3315 const struct drm_framebuffer *fb = plane_state->base.fb;
3316 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3318 u32 dspcntr = plane_state->ctl;
3319 i915_reg_t reg = DSPCNTR(i9xx_plane);
3320 int x = plane_state->main.x;
3321 int y = plane_state->main.y;
3322 unsigned long irqflags;
3325 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3327 if (INTEL_GEN(dev_priv) >= 4)
3328 dspaddr_offset = plane_state->main.offset;
3330 dspaddr_offset = linear_offset;
3332 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3334 if (INTEL_GEN(dev_priv) < 4) {
3335 /* pipesrc and dspsize control the size that is scaled from,
3336 * which should always be the user's requested size.
3338 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3339 ((crtc_state->pipe_src_h - 1) << 16) |
3340 (crtc_state->pipe_src_w - 1));
3341 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3342 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3343 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3344 ((crtc_state->pipe_src_h - 1) << 16) |
3345 (crtc_state->pipe_src_w - 1));
3346 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3347 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3350 I915_WRITE_FW(reg, dspcntr);
3352 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
3353 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3354 I915_WRITE_FW(DSPSURF(i9xx_plane),
3355 intel_plane_ggtt_offset(plane_state) +
3357 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3358 } else if (INTEL_GEN(dev_priv) >= 4) {
3359 I915_WRITE_FW(DSPSURF(i9xx_plane),
3360 intel_plane_ggtt_offset(plane_state) +
3362 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3363 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3365 I915_WRITE_FW(DSPADDR(i9xx_plane),
3366 intel_plane_ggtt_offset(plane_state) +
3369 POSTING_READ_FW(reg);
3371 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3374 static void i9xx_disable_plane(struct intel_plane *plane,
3375 struct intel_crtc *crtc)
3377 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3378 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3379 unsigned long irqflags;
3381 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3383 I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3384 if (INTEL_GEN(dev_priv) >= 4)
3385 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3387 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3388 POSTING_READ_FW(DSPCNTR(i9xx_plane));
3390 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3393 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3396 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3397 enum intel_display_power_domain power_domain;
3398 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3403 * Not 100% correct for planes that can move between pipes,
3404 * but that's only the case for gen2-4 which don't have any
3405 * display power wells.
3407 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3408 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3411 val = I915_READ(DSPCNTR(i9xx_plane));
3413 ret = val & DISPLAY_PLANE_ENABLE;
3415 if (INTEL_GEN(dev_priv) >= 5)
3416 *pipe = plane->pipe;
3418 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3419 DISPPLANE_SEL_PIPE_SHIFT;
3421 intel_display_power_put(dev_priv, power_domain);
3427 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3429 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3432 return intel_tile_width_bytes(fb, plane);
3435 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3437 struct drm_device *dev = intel_crtc->base.dev;
3438 struct drm_i915_private *dev_priv = to_i915(dev);
3440 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3441 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3442 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3446 * This function detaches (aka. unbinds) unused scalers in hardware
3448 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3450 struct intel_crtc_scaler_state *scaler_state;
3453 scaler_state = &intel_crtc->config->scaler_state;
3455 /* loop through and disable scalers that aren't in use */
3456 for (i = 0; i < intel_crtc->num_scalers; i++) {
3457 if (!scaler_state->scalers[i].in_use)
3458 skl_detach_scaler(intel_crtc, i);
3462 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3463 unsigned int rotation)
3467 if (plane >= fb->format->num_planes)
3470 stride = intel_fb_pitch(fb, plane, rotation);
3473 * The stride is either expressed as a multiple of 64 bytes chunks for
3474 * linear buffers or in number of tiles for tiled buffers.
3476 if (drm_rotation_90_or_270(rotation))
3477 stride /= intel_tile_height(fb, plane);
3479 stride /= intel_fb_stride_alignment(fb, plane);
3484 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3486 switch (pixel_format) {
3488 return PLANE_CTL_FORMAT_INDEXED;
3489 case DRM_FORMAT_RGB565:
3490 return PLANE_CTL_FORMAT_RGB_565;
3491 case DRM_FORMAT_XBGR8888:
3492 case DRM_FORMAT_ABGR8888:
3493 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3494 case DRM_FORMAT_XRGB8888:
3495 case DRM_FORMAT_ARGB8888:
3496 return PLANE_CTL_FORMAT_XRGB_8888;
3497 case DRM_FORMAT_XRGB2101010:
3498 return PLANE_CTL_FORMAT_XRGB_2101010;
3499 case DRM_FORMAT_XBGR2101010:
3500 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3501 case DRM_FORMAT_YUYV:
3502 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3503 case DRM_FORMAT_YVYU:
3504 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3505 case DRM_FORMAT_UYVY:
3506 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3507 case DRM_FORMAT_VYUY:
3508 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3509 case DRM_FORMAT_NV12:
3510 return PLANE_CTL_FORMAT_NV12;
3512 MISSING_CASE(pixel_format);
3519 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3520 * to be already pre-multiplied. We need to add a knob (or a different
3521 * DRM_FORMAT) for user-space to configure that.
3523 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3525 switch (pixel_format) {
3526 case DRM_FORMAT_ABGR8888:
3527 case DRM_FORMAT_ARGB8888:
3528 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3530 return PLANE_CTL_ALPHA_DISABLE;
3534 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3536 switch (pixel_format) {
3537 case DRM_FORMAT_ABGR8888:
3538 case DRM_FORMAT_ARGB8888:
3539 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3541 return PLANE_COLOR_ALPHA_DISABLE;
3545 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3547 switch (fb_modifier) {
3548 case DRM_FORMAT_MOD_LINEAR:
3550 case I915_FORMAT_MOD_X_TILED:
3551 return PLANE_CTL_TILED_X;
3552 case I915_FORMAT_MOD_Y_TILED:
3553 return PLANE_CTL_TILED_Y;
3554 case I915_FORMAT_MOD_Y_TILED_CCS:
3555 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3556 case I915_FORMAT_MOD_Yf_TILED:
3557 return PLANE_CTL_TILED_YF;
3558 case I915_FORMAT_MOD_Yf_TILED_CCS:
3559 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3561 MISSING_CASE(fb_modifier);
3567 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3570 case DRM_MODE_ROTATE_0:
3573 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3574 * while i915 HW rotation is clockwise, thats why this swapping.
3576 case DRM_MODE_ROTATE_90:
3577 return PLANE_CTL_ROTATE_270;
3578 case DRM_MODE_ROTATE_180:
3579 return PLANE_CTL_ROTATE_180;
3580 case DRM_MODE_ROTATE_270:
3581 return PLANE_CTL_ROTATE_90;
3583 MISSING_CASE(rotate);
3589 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3594 case DRM_MODE_REFLECT_X:
3595 return PLANE_CTL_FLIP_HORIZONTAL;
3596 case DRM_MODE_REFLECT_Y:
3598 MISSING_CASE(reflect);
3604 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3605 const struct intel_plane_state *plane_state)
3607 struct drm_i915_private *dev_priv =
3608 to_i915(plane_state->base.plane->dev);
3609 const struct drm_framebuffer *fb = plane_state->base.fb;
3610 unsigned int rotation = plane_state->base.rotation;
3611 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3614 plane_ctl = PLANE_CTL_ENABLE;
3616 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3617 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3619 PLANE_CTL_PIPE_GAMMA_ENABLE |
3620 PLANE_CTL_PIPE_CSC_ENABLE |
3621 PLANE_CTL_PLANE_GAMMA_DISABLE;
3623 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3624 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3626 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3627 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3630 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3631 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3632 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3634 if (INTEL_GEN(dev_priv) >= 10)
3635 plane_ctl |= cnl_plane_ctl_flip(rotation &
3636 DRM_MODE_REFLECT_MASK);
3638 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3639 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3640 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3641 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3646 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3647 const struct intel_plane_state *plane_state)
3649 struct drm_i915_private *dev_priv =
3650 to_i915(plane_state->base.plane->dev);
3651 const struct drm_framebuffer *fb = plane_state->base.fb;
3652 u32 plane_color_ctl = 0;
3654 if (INTEL_GEN(dev_priv) < 11) {
3655 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3656 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3658 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3659 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3661 if (intel_format_is_yuv(fb->format->format)) {
3662 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3663 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3665 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3667 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3668 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3671 return plane_color_ctl;
3675 __intel_display_resume(struct drm_device *dev,
3676 struct drm_atomic_state *state,
3677 struct drm_modeset_acquire_ctx *ctx)
3679 struct drm_crtc_state *crtc_state;
3680 struct drm_crtc *crtc;
3683 intel_modeset_setup_hw_state(dev, ctx);
3684 i915_redisable_vga(to_i915(dev));
3690 * We've duplicated the state, pointers to the old state are invalid.
3692 * Don't attempt to use the old state until we commit the duplicated state.
3694 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3696 * Force recalculation even if we restore
3697 * current state. With fast modeset this may not result
3698 * in a modeset when the state is compatible.
3700 crtc_state->mode_changed = true;
3703 /* ignore any reset values/BIOS leftovers in the WM registers */
3704 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3705 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3707 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3709 WARN_ON(ret == -EDEADLK);
3713 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3715 return intel_has_gpu_reset(dev_priv) &&
3716 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3719 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3721 struct drm_device *dev = &dev_priv->drm;
3722 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3723 struct drm_atomic_state *state;
3726 /* reset doesn't touch the display */
3727 if (!i915_modparams.force_reset_modeset_test &&
3728 !gpu_reset_clobbers_display(dev_priv))
3731 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3732 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3733 wake_up_all(&dev_priv->gpu_error.wait_queue);
3735 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3736 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3737 i915_gem_set_wedged(dev_priv);
3741 * Need mode_config.mutex so that we don't
3742 * trample ongoing ->detect() and whatnot.
3744 mutex_lock(&dev->mode_config.mutex);
3745 drm_modeset_acquire_init(ctx, 0);
3747 ret = drm_modeset_lock_all_ctx(dev, ctx);
3748 if (ret != -EDEADLK)
3751 drm_modeset_backoff(ctx);
3754 * Disabling the crtcs gracefully seems nicer. Also the
3755 * g33 docs say we should at least disable all the planes.
3757 state = drm_atomic_helper_duplicate_state(dev, ctx);
3758 if (IS_ERR(state)) {
3759 ret = PTR_ERR(state);
3760 DRM_ERROR("Duplicating state failed with %i\n", ret);
3764 ret = drm_atomic_helper_disable_all(dev, ctx);
3766 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3767 drm_atomic_state_put(state);
3771 dev_priv->modeset_restore_state = state;
3772 state->acquire_ctx = ctx;
3775 void intel_finish_reset(struct drm_i915_private *dev_priv)
3777 struct drm_device *dev = &dev_priv->drm;
3778 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3779 struct drm_atomic_state *state;
3782 /* reset doesn't touch the display */
3783 if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3786 state = fetch_and_zero(&dev_priv->modeset_restore_state);
3790 /* reset doesn't touch the display */
3791 if (!gpu_reset_clobbers_display(dev_priv)) {
3792 /* for testing only restore the display */
3793 ret = __intel_display_resume(dev, state, ctx);
3795 DRM_ERROR("Restoring old state failed with %i\n", ret);
3798 * The display has been reset as well,
3799 * so need a full re-initialization.
3801 intel_runtime_pm_disable_interrupts(dev_priv);
3802 intel_runtime_pm_enable_interrupts(dev_priv);
3804 intel_pps_unlock_regs_wa(dev_priv);
3805 intel_modeset_init_hw(dev);
3806 intel_init_clock_gating(dev_priv);
3808 spin_lock_irq(&dev_priv->irq_lock);
3809 if (dev_priv->display.hpd_irq_setup)
3810 dev_priv->display.hpd_irq_setup(dev_priv);
3811 spin_unlock_irq(&dev_priv->irq_lock);
3813 ret = __intel_display_resume(dev, state, ctx);
3815 DRM_ERROR("Restoring old state failed with %i\n", ret);
3817 intel_hpd_init(dev_priv);
3820 drm_atomic_state_put(state);
3822 drm_modeset_drop_locks(ctx);
3823 drm_modeset_acquire_fini(ctx);
3824 mutex_unlock(&dev->mode_config.mutex);
3826 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3829 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3830 const struct intel_crtc_state *new_crtc_state)
3832 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3833 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3835 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3836 crtc->base.mode = new_crtc_state->base.mode;
3839 * Update pipe size and adjust fitter if needed: the reason for this is
3840 * that in compute_mode_changes we check the native mode (not the pfit
3841 * mode) to see if we can flip rather than do a full mode set. In the
3842 * fastboot case, we'll flip, but if we don't update the pipesrc and
3843 * pfit state, we'll end up with a big fb scanned out into the wrong
3847 I915_WRITE(PIPESRC(crtc->pipe),
3848 ((new_crtc_state->pipe_src_w - 1) << 16) |
3849 (new_crtc_state->pipe_src_h - 1));
3851 /* on skylake this is done by detaching scalers */
3852 if (INTEL_GEN(dev_priv) >= 9) {
3853 skl_detach_scalers(crtc);
3855 if (new_crtc_state->pch_pfit.enabled)
3856 skylake_pfit_enable(crtc);
3857 } else if (HAS_PCH_SPLIT(dev_priv)) {
3858 if (new_crtc_state->pch_pfit.enabled)
3859 ironlake_pfit_enable(crtc);
3860 else if (old_crtc_state->pch_pfit.enabled)
3861 ironlake_pfit_disable(crtc, true);
3865 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3867 struct drm_device *dev = crtc->base.dev;
3868 struct drm_i915_private *dev_priv = to_i915(dev);
3869 int pipe = crtc->pipe;
3873 /* enable normal train */
3874 reg = FDI_TX_CTL(pipe);
3875 temp = I915_READ(reg);
3876 if (IS_IVYBRIDGE(dev_priv)) {
3877 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3878 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3880 temp &= ~FDI_LINK_TRAIN_NONE;
3881 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3883 I915_WRITE(reg, temp);
3885 reg = FDI_RX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 if (HAS_PCH_CPT(dev_priv)) {
3888 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3889 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3891 temp &= ~FDI_LINK_TRAIN_NONE;
3892 temp |= FDI_LINK_TRAIN_NONE;
3894 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3896 /* wait one idle pattern time */
3900 /* IVB wants error correction enabled */
3901 if (IS_IVYBRIDGE(dev_priv))
3902 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3903 FDI_FE_ERRC_ENABLE);
3906 /* The FDI link training functions for ILK/Ibexpeak. */
3907 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3908 const struct intel_crtc_state *crtc_state)
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = to_i915(dev);
3912 int pipe = crtc->pipe;
3916 /* FDI needs bits from pipe first */
3917 assert_pipe_enabled(dev_priv, pipe);
3919 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3921 reg = FDI_RX_IMR(pipe);
3922 temp = I915_READ(reg);
3923 temp &= ~FDI_RX_SYMBOL_LOCK;
3924 temp &= ~FDI_RX_BIT_LOCK;
3925 I915_WRITE(reg, temp);
3929 /* enable CPU FDI TX and PCH FDI RX */
3930 reg = FDI_TX_CTL(pipe);
3931 temp = I915_READ(reg);
3932 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3933 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3934 temp &= ~FDI_LINK_TRAIN_NONE;
3935 temp |= FDI_LINK_TRAIN_PATTERN_1;
3936 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3938 reg = FDI_RX_CTL(pipe);
3939 temp = I915_READ(reg);
3940 temp &= ~FDI_LINK_TRAIN_NONE;
3941 temp |= FDI_LINK_TRAIN_PATTERN_1;
3942 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3947 /* Ironlake workaround, enable clock pointer after FDI enable*/
3948 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3949 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3950 FDI_RX_PHASE_SYNC_POINTER_EN);
3952 reg = FDI_RX_IIR(pipe);
3953 for (tries = 0; tries < 5; tries++) {
3954 temp = I915_READ(reg);
3955 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3957 if ((temp & FDI_RX_BIT_LOCK)) {
3958 DRM_DEBUG_KMS("FDI train 1 done.\n");
3959 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3964 DRM_ERROR("FDI train 1 fail!\n");
3967 reg = FDI_TX_CTL(pipe);
3968 temp = I915_READ(reg);
3969 temp &= ~FDI_LINK_TRAIN_NONE;
3970 temp |= FDI_LINK_TRAIN_PATTERN_2;
3971 I915_WRITE(reg, temp);
3973 reg = FDI_RX_CTL(pipe);
3974 temp = I915_READ(reg);
3975 temp &= ~FDI_LINK_TRAIN_NONE;
3976 temp |= FDI_LINK_TRAIN_PATTERN_2;
3977 I915_WRITE(reg, temp);
3982 reg = FDI_RX_IIR(pipe);
3983 for (tries = 0; tries < 5; tries++) {
3984 temp = I915_READ(reg);
3985 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3987 if (temp & FDI_RX_SYMBOL_LOCK) {
3988 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3989 DRM_DEBUG_KMS("FDI train 2 done.\n");
3994 DRM_ERROR("FDI train 2 fail!\n");
3996 DRM_DEBUG_KMS("FDI train done\n");
4000 static const int snb_b_fdi_train_param[] = {
4001 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4002 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4003 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4004 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4007 /* The FDI link training functions for SNB/Cougarpoint. */
4008 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4009 const struct intel_crtc_state *crtc_state)
4011 struct drm_device *dev = crtc->base.dev;
4012 struct drm_i915_private *dev_priv = to_i915(dev);
4013 int pipe = crtc->pipe;
4017 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4019 reg = FDI_RX_IMR(pipe);
4020 temp = I915_READ(reg);
4021 temp &= ~FDI_RX_SYMBOL_LOCK;
4022 temp &= ~FDI_RX_BIT_LOCK;
4023 I915_WRITE(reg, temp);
4028 /* enable CPU FDI TX and PCH FDI RX */
4029 reg = FDI_TX_CTL(pipe);
4030 temp = I915_READ(reg);
4031 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4032 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4033 temp &= ~FDI_LINK_TRAIN_NONE;
4034 temp |= FDI_LINK_TRAIN_PATTERN_1;
4035 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4037 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4038 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4040 I915_WRITE(FDI_RX_MISC(pipe),
4041 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4043 reg = FDI_RX_CTL(pipe);
4044 temp = I915_READ(reg);
4045 if (HAS_PCH_CPT(dev_priv)) {
4046 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4047 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4049 temp &= ~FDI_LINK_TRAIN_NONE;
4050 temp |= FDI_LINK_TRAIN_PATTERN_1;
4052 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4057 for (i = 0; i < 4; i++) {
4058 reg = FDI_TX_CTL(pipe);
4059 temp = I915_READ(reg);
4060 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4061 temp |= snb_b_fdi_train_param[i];
4062 I915_WRITE(reg, temp);
4067 for (retry = 0; retry < 5; retry++) {
4068 reg = FDI_RX_IIR(pipe);
4069 temp = I915_READ(reg);
4070 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4071 if (temp & FDI_RX_BIT_LOCK) {
4072 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4073 DRM_DEBUG_KMS("FDI train 1 done.\n");
4082 DRM_ERROR("FDI train 1 fail!\n");
4085 reg = FDI_TX_CTL(pipe);
4086 temp = I915_READ(reg);
4087 temp &= ~FDI_LINK_TRAIN_NONE;
4088 temp |= FDI_LINK_TRAIN_PATTERN_2;
4089 if (IS_GEN6(dev_priv)) {
4090 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4092 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4094 I915_WRITE(reg, temp);
4096 reg = FDI_RX_CTL(pipe);
4097 temp = I915_READ(reg);
4098 if (HAS_PCH_CPT(dev_priv)) {
4099 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4100 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4102 temp &= ~FDI_LINK_TRAIN_NONE;
4103 temp |= FDI_LINK_TRAIN_PATTERN_2;
4105 I915_WRITE(reg, temp);
4110 for (i = 0; i < 4; i++) {
4111 reg = FDI_TX_CTL(pipe);
4112 temp = I915_READ(reg);
4113 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4114 temp |= snb_b_fdi_train_param[i];
4115 I915_WRITE(reg, temp);
4120 for (retry = 0; retry < 5; retry++) {
4121 reg = FDI_RX_IIR(pipe);
4122 temp = I915_READ(reg);
4123 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4124 if (temp & FDI_RX_SYMBOL_LOCK) {
4125 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4126 DRM_DEBUG_KMS("FDI train 2 done.\n");
4135 DRM_ERROR("FDI train 2 fail!\n");
4137 DRM_DEBUG_KMS("FDI train done.\n");
4140 /* Manual link training for Ivy Bridge A0 parts */
4141 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4142 const struct intel_crtc_state *crtc_state)
4144 struct drm_device *dev = crtc->base.dev;
4145 struct drm_i915_private *dev_priv = to_i915(dev);
4146 int pipe = crtc->pipe;
4150 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4152 reg = FDI_RX_IMR(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~FDI_RX_SYMBOL_LOCK;
4155 temp &= ~FDI_RX_BIT_LOCK;
4156 I915_WRITE(reg, temp);
4161 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4162 I915_READ(FDI_RX_IIR(pipe)));
4164 /* Try each vswing and preemphasis setting twice before moving on */
4165 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4166 /* disable first in case we need to retry */
4167 reg = FDI_TX_CTL(pipe);
4168 temp = I915_READ(reg);
4169 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4170 temp &= ~FDI_TX_ENABLE;
4171 I915_WRITE(reg, temp);
4173 reg = FDI_RX_CTL(pipe);
4174 temp = I915_READ(reg);
4175 temp &= ~FDI_LINK_TRAIN_AUTO;
4176 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4177 temp &= ~FDI_RX_ENABLE;
4178 I915_WRITE(reg, temp);
4180 /* enable CPU FDI TX and PCH FDI RX */
4181 reg = FDI_TX_CTL(pipe);
4182 temp = I915_READ(reg);
4183 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4184 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4185 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4186 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4187 temp |= snb_b_fdi_train_param[j/2];
4188 temp |= FDI_COMPOSITE_SYNC;
4189 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4191 I915_WRITE(FDI_RX_MISC(pipe),
4192 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4194 reg = FDI_RX_CTL(pipe);
4195 temp = I915_READ(reg);
4196 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4197 temp |= FDI_COMPOSITE_SYNC;
4198 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4201 udelay(1); /* should be 0.5us */
4203 for (i = 0; i < 4; i++) {
4204 reg = FDI_RX_IIR(pipe);
4205 temp = I915_READ(reg);
4206 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4208 if (temp & FDI_RX_BIT_LOCK ||
4209 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4210 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4211 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4215 udelay(1); /* should be 0.5us */
4218 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4223 reg = FDI_TX_CTL(pipe);
4224 temp = I915_READ(reg);
4225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4226 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4227 I915_WRITE(reg, temp);
4229 reg = FDI_RX_CTL(pipe);
4230 temp = I915_READ(reg);
4231 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4232 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4233 I915_WRITE(reg, temp);
4236 udelay(2); /* should be 1.5us */
4238 for (i = 0; i < 4; i++) {
4239 reg = FDI_RX_IIR(pipe);
4240 temp = I915_READ(reg);
4241 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4243 if (temp & FDI_RX_SYMBOL_LOCK ||
4244 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4245 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4246 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4250 udelay(2); /* should be 1.5us */
4253 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4257 DRM_DEBUG_KMS("FDI train done.\n");
4260 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4262 struct drm_device *dev = intel_crtc->base.dev;
4263 struct drm_i915_private *dev_priv = to_i915(dev);
4264 int pipe = intel_crtc->pipe;
4268 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4269 reg = FDI_RX_CTL(pipe);
4270 temp = I915_READ(reg);
4271 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4272 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4273 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4274 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4279 /* Switch from Rawclk to PCDclk */
4280 temp = I915_READ(reg);
4281 I915_WRITE(reg, temp | FDI_PCDCLK);
4286 /* Enable CPU FDI TX PLL, always on for Ironlake */
4287 reg = FDI_TX_CTL(pipe);
4288 temp = I915_READ(reg);
4289 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4290 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4297 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4299 struct drm_device *dev = intel_crtc->base.dev;
4300 struct drm_i915_private *dev_priv = to_i915(dev);
4301 int pipe = intel_crtc->pipe;
4305 /* Switch from PCDclk to Rawclk */
4306 reg = FDI_RX_CTL(pipe);
4307 temp = I915_READ(reg);
4308 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4310 /* Disable CPU FDI TX PLL */
4311 reg = FDI_TX_CTL(pipe);
4312 temp = I915_READ(reg);
4313 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4318 reg = FDI_RX_CTL(pipe);
4319 temp = I915_READ(reg);
4320 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4322 /* Wait for the clocks to turn off. */
4327 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4329 struct drm_device *dev = crtc->dev;
4330 struct drm_i915_private *dev_priv = to_i915(dev);
4331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4332 int pipe = intel_crtc->pipe;
4336 /* disable CPU FDI tx and PCH FDI rx */
4337 reg = FDI_TX_CTL(pipe);
4338 temp = I915_READ(reg);
4339 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4342 reg = FDI_RX_CTL(pipe);
4343 temp = I915_READ(reg);
4344 temp &= ~(0x7 << 16);
4345 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4346 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4351 /* Ironlake workaround, disable clock pointer after downing FDI */
4352 if (HAS_PCH_IBX(dev_priv))
4353 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4355 /* still set train pattern 1 */
4356 reg = FDI_TX_CTL(pipe);
4357 temp = I915_READ(reg);
4358 temp &= ~FDI_LINK_TRAIN_NONE;
4359 temp |= FDI_LINK_TRAIN_PATTERN_1;
4360 I915_WRITE(reg, temp);
4362 reg = FDI_RX_CTL(pipe);
4363 temp = I915_READ(reg);
4364 if (HAS_PCH_CPT(dev_priv)) {
4365 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4366 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4368 temp &= ~FDI_LINK_TRAIN_NONE;
4369 temp |= FDI_LINK_TRAIN_PATTERN_1;
4371 /* BPC in FDI rx is consistent with that in PIPECONF */
4372 temp &= ~(0x07 << 16);
4373 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4374 I915_WRITE(reg, temp);
4380 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4382 struct drm_crtc *crtc;
4385 drm_for_each_crtc(crtc, &dev_priv->drm) {
4386 struct drm_crtc_commit *commit;
4387 spin_lock(&crtc->commit_lock);
4388 commit = list_first_entry_or_null(&crtc->commit_list,
4389 struct drm_crtc_commit, commit_entry);
4390 cleanup_done = commit ?
4391 try_wait_for_completion(&commit->cleanup_done) : true;
4392 spin_unlock(&crtc->commit_lock);
4397 drm_crtc_wait_one_vblank(crtc);
4405 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4409 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4411 mutex_lock(&dev_priv->sb_lock);
4413 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4414 temp |= SBI_SSCCTL_DISABLE;
4415 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4417 mutex_unlock(&dev_priv->sb_lock);
4420 /* Program iCLKIP clock to the desired frequency */
4421 static void lpt_program_iclkip(struct intel_crtc *crtc)
4423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4424 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4425 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4428 lpt_disable_iclkip(dev_priv);
4430 /* The iCLK virtual clock root frequency is in MHz,
4431 * but the adjusted_mode->crtc_clock in in KHz. To get the
4432 * divisors, it is necessary to divide one by another, so we
4433 * convert the virtual clock precision to KHz here for higher
4436 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4437 u32 iclk_virtual_root_freq = 172800 * 1000;
4438 u32 iclk_pi_range = 64;
4439 u32 desired_divisor;
4441 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4443 divsel = (desired_divisor / iclk_pi_range) - 2;
4444 phaseinc = desired_divisor % iclk_pi_range;
4447 * Near 20MHz is a corner case which is
4448 * out of range for the 7-bit divisor
4454 /* This should not happen with any sane values */
4455 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4456 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4457 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4458 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4460 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4467 mutex_lock(&dev_priv->sb_lock);
4469 /* Program SSCDIVINTPHASE6 */
4470 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4471 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4472 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4473 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4474 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4475 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4476 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4477 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4479 /* Program SSCAUXDIV */
4480 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4481 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4482 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4483 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4485 /* Enable modulator and associated divider */
4486 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4487 temp &= ~SBI_SSCCTL_DISABLE;
4488 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4490 mutex_unlock(&dev_priv->sb_lock);
4492 /* Wait for initialization time */
4495 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4498 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4500 u32 divsel, phaseinc, auxdiv;
4501 u32 iclk_virtual_root_freq = 172800 * 1000;
4502 u32 iclk_pi_range = 64;
4503 u32 desired_divisor;
4506 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4509 mutex_lock(&dev_priv->sb_lock);
4511 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4512 if (temp & SBI_SSCCTL_DISABLE) {
4513 mutex_unlock(&dev_priv->sb_lock);
4517 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4518 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4519 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4520 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4521 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4523 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4524 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4525 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4527 mutex_unlock(&dev_priv->sb_lock);
4529 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4531 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4532 desired_divisor << auxdiv);
4535 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4536 enum pipe pch_transcoder)
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = to_i915(dev);
4540 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4542 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4543 I915_READ(HTOTAL(cpu_transcoder)));
4544 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4545 I915_READ(HBLANK(cpu_transcoder)));
4546 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4547 I915_READ(HSYNC(cpu_transcoder)));
4549 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4550 I915_READ(VTOTAL(cpu_transcoder)));
4551 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4552 I915_READ(VBLANK(cpu_transcoder)));
4553 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4554 I915_READ(VSYNC(cpu_transcoder)));
4555 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4556 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4559 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4561 struct drm_i915_private *dev_priv = to_i915(dev);
4564 temp = I915_READ(SOUTH_CHICKEN1);
4565 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4568 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4571 temp &= ~FDI_BC_BIFURCATION_SELECT;
4573 temp |= FDI_BC_BIFURCATION_SELECT;
4575 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4576 I915_WRITE(SOUTH_CHICKEN1, temp);
4577 POSTING_READ(SOUTH_CHICKEN1);
4580 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4582 struct drm_device *dev = intel_crtc->base.dev;
4584 switch (intel_crtc->pipe) {
4588 if (intel_crtc->config->fdi_lanes > 2)
4589 cpt_set_fdi_bc_bifurcation(dev, false);
4591 cpt_set_fdi_bc_bifurcation(dev, true);
4595 cpt_set_fdi_bc_bifurcation(dev, true);
4604 * Finds the encoder associated with the given CRTC. This can only be
4605 * used when we know that the CRTC isn't feeding multiple encoders!
4607 static struct intel_encoder *
4608 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4609 const struct intel_crtc_state *crtc_state)
4611 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4612 const struct drm_connector_state *connector_state;
4613 const struct drm_connector *connector;
4614 struct intel_encoder *encoder = NULL;
4615 int num_encoders = 0;
4618 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4619 if (connector_state->crtc != &crtc->base)
4622 encoder = to_intel_encoder(connector_state->best_encoder);
4626 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4627 num_encoders, pipe_name(crtc->pipe));
4633 * Enable PCH resources required for PCH ports:
4635 * - FDI training & RX/TX
4636 * - update transcoder timings
4637 * - DP transcoding bits
4640 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4641 const struct intel_crtc_state *crtc_state)
4643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4644 struct drm_device *dev = crtc->base.dev;
4645 struct drm_i915_private *dev_priv = to_i915(dev);
4646 int pipe = crtc->pipe;
4649 assert_pch_transcoder_disabled(dev_priv, pipe);
4651 if (IS_IVYBRIDGE(dev_priv))
4652 ivybridge_update_fdi_bc_bifurcation(crtc);
4654 /* Write the TU size bits before fdi link training, so that error
4655 * detection works. */
4656 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4657 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4659 /* For PCH output, training FDI link */
4660 dev_priv->display.fdi_link_train(crtc, crtc_state);
4662 /* We need to program the right clock selection before writing the pixel
4663 * mutliplier into the DPLL. */
4664 if (HAS_PCH_CPT(dev_priv)) {
4667 temp = I915_READ(PCH_DPLL_SEL);
4668 temp |= TRANS_DPLL_ENABLE(pipe);
4669 sel = TRANS_DPLLB_SEL(pipe);
4670 if (crtc_state->shared_dpll ==
4671 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4675 I915_WRITE(PCH_DPLL_SEL, temp);
4678 /* XXX: pch pll's can be enabled any time before we enable the PCH
4679 * transcoder, and we actually should do this to not upset any PCH
4680 * transcoder that already use the clock when we share it.
4682 * Note that enable_shared_dpll tries to do the right thing, but
4683 * get_shared_dpll unconditionally resets the pll - we need that to have
4684 * the right LVDS enable sequence. */
4685 intel_enable_shared_dpll(crtc);
4687 /* set transcoder timing, panel must allow it */
4688 assert_panel_unlocked(dev_priv, pipe);
4689 ironlake_pch_transcoder_set_timings(crtc, pipe);
4691 intel_fdi_normal_train(crtc);
4693 /* For PCH DP, enable TRANS_DP_CTL */
4694 if (HAS_PCH_CPT(dev_priv) &&
4695 intel_crtc_has_dp_encoder(crtc_state)) {
4696 const struct drm_display_mode *adjusted_mode =
4697 &crtc_state->base.adjusted_mode;
4698 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4699 i915_reg_t reg = TRANS_DP_CTL(pipe);
4702 temp = I915_READ(reg);
4703 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4704 TRANS_DP_SYNC_MASK |
4706 temp |= TRANS_DP_OUTPUT_ENABLE;
4707 temp |= bpc << 9; /* same format but at 11:9 */
4709 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4710 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4711 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4712 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4714 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4715 WARN_ON(port < PORT_B || port > PORT_D);
4716 temp |= TRANS_DP_PORT_SEL(port);
4718 I915_WRITE(reg, temp);
4721 ironlake_enable_pch_transcoder(dev_priv, pipe);
4724 static void lpt_pch_enable(const struct intel_atomic_state *state,
4725 const struct intel_crtc_state *crtc_state)
4727 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4728 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4729 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4731 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4733 lpt_program_iclkip(crtc);
4735 /* Set transcoder timing. */
4736 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4738 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4741 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4743 struct drm_i915_private *dev_priv = to_i915(dev);
4744 i915_reg_t dslreg = PIPEDSL(pipe);
4747 temp = I915_READ(dslreg);
4749 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4750 if (wait_for(I915_READ(dslreg) != temp, 5))
4751 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4756 * The hardware phase 0.0 refers to the center of the pixel.
4757 * We want to start from the top/left edge which is phase
4758 * -0.5. That matches how the hardware calculates the scaling
4759 * factors (from top-left of the first pixel to bottom-right
4760 * of the last pixel, as opposed to the pixel centers).
4762 * For 4:2:0 subsampled chroma planes we obviously have to
4763 * adjust that so that the chroma sample position lands in
4766 * Note that for packed YCbCr 4:2:2 formats there is no way to
4767 * control chroma siting. The hardware simply replicates the
4768 * chroma samples for both of the luma samples, and thus we don't
4769 * actually get the expected MPEG2 chroma siting convention :(
4770 * The same behaviour is observed on pre-SKL platforms as well.
4772 u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
4774 int phase = -0x8000;
4778 phase += (sub - 1) * 0x8000 / sub;
4781 phase = 0x10000 + phase;
4783 trip = PS_PHASE_TRIP;
4785 return ((phase >> 2) & PS_PHASE_MASK) | trip;
4789 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4790 unsigned int scaler_user, int *scaler_id,
4791 int src_w, int src_h, int dst_w, int dst_h,
4792 bool plane_scaler_check,
4793 uint32_t pixel_format)
4795 struct intel_crtc_scaler_state *scaler_state =
4796 &crtc_state->scaler_state;
4797 struct intel_crtc *intel_crtc =
4798 to_intel_crtc(crtc_state->base.crtc);
4799 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4800 const struct drm_display_mode *adjusted_mode =
4801 &crtc_state->base.adjusted_mode;
4805 * Src coordinates are already rotated by 270 degrees for
4806 * the 90/270 degree plane rotation cases (to match the
4807 * GTT mapping), hence no need to account for rotation here.
4809 need_scaling = src_w != dst_w || src_h != dst_h;
4811 if (plane_scaler_check)
4812 if (pixel_format == DRM_FORMAT_NV12)
4813 need_scaling = true;
4815 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4816 need_scaling = true;
4819 * Scaling/fitting not supported in IF-ID mode in GEN9+
4820 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4821 * Once NV12 is enabled, handle it here while allocating scaler
4824 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4825 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4826 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4831 * if plane is being disabled or scaler is no more required or force detach
4832 * - free scaler binded to this plane/crtc
4833 * - in order to do this, update crtc->scaler_usage
4835 * Here scaler state in crtc_state is set free so that
4836 * scaler can be assigned to other user. Actual register
4837 * update to free the scaler is done in plane/panel-fit programming.
4838 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4840 if (force_detach || !need_scaling) {
4841 if (*scaler_id >= 0) {
4842 scaler_state->scaler_users &= ~(1 << scaler_user);
4843 scaler_state->scalers[*scaler_id].in_use = 0;
4845 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4846 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4847 intel_crtc->pipe, scaler_user, *scaler_id,
4848 scaler_state->scaler_users);
4854 if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4855 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4856 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4861 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4862 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4863 (IS_GEN11(dev_priv) &&
4864 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4865 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4866 (!IS_GEN11(dev_priv) &&
4867 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4868 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4869 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4870 "size is out of scaler range\n",
4871 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4875 /* mark this plane as a scaler user in crtc_state */
4876 scaler_state->scaler_users |= (1 << scaler_user);
4877 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4878 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4879 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4880 scaler_state->scaler_users);
4886 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4888 * @state: crtc's scaler state
4891 * 0 - scaler_usage updated successfully
4892 * error - requested scaling cannot be supported or other error condition
4894 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4896 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4898 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4899 &state->scaler_state.scaler_id,
4900 state->pipe_src_w, state->pipe_src_h,
4901 adjusted_mode->crtc_hdisplay,
4902 adjusted_mode->crtc_vdisplay, false, 0);
4906 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4907 * @crtc_state: crtc's scaler state
4908 * @plane_state: atomic plane state to update
4911 * 0 - scaler_usage updated successfully
4912 * error - requested scaling cannot be supported or other error condition
4914 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4915 struct intel_plane_state *plane_state)
4918 struct intel_plane *intel_plane =
4919 to_intel_plane(plane_state->base.plane);
4920 struct drm_framebuffer *fb = plane_state->base.fb;
4923 bool force_detach = !fb || !plane_state->base.visible;
4925 ret = skl_update_scaler(crtc_state, force_detach,
4926 drm_plane_index(&intel_plane->base),
4927 &plane_state->scaler_id,
4928 drm_rect_width(&plane_state->base.src) >> 16,
4929 drm_rect_height(&plane_state->base.src) >> 16,
4930 drm_rect_width(&plane_state->base.dst),
4931 drm_rect_height(&plane_state->base.dst),
4932 fb ? true : false, fb ? fb->format->format : 0);
4934 if (ret || plane_state->scaler_id < 0)
4937 /* check colorkey */
4938 if (plane_state->ckey.flags) {
4939 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4940 intel_plane->base.base.id,
4941 intel_plane->base.name);
4945 /* Check src format */
4946 switch (fb->format->format) {
4947 case DRM_FORMAT_RGB565:
4948 case DRM_FORMAT_XBGR8888:
4949 case DRM_FORMAT_XRGB8888:
4950 case DRM_FORMAT_ABGR8888:
4951 case DRM_FORMAT_ARGB8888:
4952 case DRM_FORMAT_XRGB2101010:
4953 case DRM_FORMAT_XBGR2101010:
4954 case DRM_FORMAT_YUYV:
4955 case DRM_FORMAT_YVYU:
4956 case DRM_FORMAT_UYVY:
4957 case DRM_FORMAT_VYUY:
4958 case DRM_FORMAT_NV12:
4961 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4962 intel_plane->base.base.id, intel_plane->base.name,
4963 fb->base.id, fb->format->format);
4970 static void skylake_scaler_disable(struct intel_crtc *crtc)
4974 for (i = 0; i < crtc->num_scalers; i++)
4975 skl_detach_scaler(crtc, i);
4978 static void skylake_pfit_enable(struct intel_crtc *crtc)
4980 struct drm_device *dev = crtc->base.dev;
4981 struct drm_i915_private *dev_priv = to_i915(dev);
4982 int pipe = crtc->pipe;
4983 struct intel_crtc_scaler_state *scaler_state =
4984 &crtc->config->scaler_state;
4986 if (crtc->config->pch_pfit.enabled) {
4987 u16 uv_rgb_hphase, uv_rgb_vphase;
4990 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4993 uv_rgb_hphase = skl_scaler_calc_phase(1, false);
4994 uv_rgb_vphase = skl_scaler_calc_phase(1, false);
4996 id = scaler_state->scaler_id;
4997 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4998 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4999 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5000 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5001 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5002 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5003 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
5004 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
5008 static void ironlake_pfit_enable(struct intel_crtc *crtc)
5010 struct drm_device *dev = crtc->base.dev;
5011 struct drm_i915_private *dev_priv = to_i915(dev);
5012 int pipe = crtc->pipe;
5014 if (crtc->config->pch_pfit.enabled) {
5015 /* Force use of hard-coded filter coefficients
5016 * as some pre-programmed values are broken,
5019 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5020 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5021 PF_PIPE_SEL_IVB(pipe));
5023 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5024 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
5025 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
5029 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5031 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5032 struct drm_device *dev = crtc->base.dev;
5033 struct drm_i915_private *dev_priv = to_i915(dev);
5035 if (!crtc_state->ips_enabled)
5039 * We can only enable IPS after we enable a plane and wait for a vblank
5040 * This function is called from post_plane_update, which is run after
5043 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5045 if (IS_BROADWELL(dev_priv)) {
5046 mutex_lock(&dev_priv->pcu_lock);
5047 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5048 IPS_ENABLE | IPS_PCODE_CONTROL));
5049 mutex_unlock(&dev_priv->pcu_lock);
5050 /* Quoting Art Runyan: "its not safe to expect any particular
5051 * value in IPS_CTL bit 31 after enabling IPS through the
5052 * mailbox." Moreover, the mailbox may return a bogus state,
5053 * so we need to just enable it and continue on.
5056 I915_WRITE(IPS_CTL, IPS_ENABLE);
5057 /* The bit only becomes 1 in the next vblank, so this wait here
5058 * is essentially intel_wait_for_vblank. If we don't have this
5059 * and don't wait for vblanks until the end of crtc_enable, then
5060 * the HW state readout code will complain that the expected
5061 * IPS_CTL value is not the one we read. */
5062 if (intel_wait_for_register(dev_priv,
5063 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5065 DRM_ERROR("Timed out waiting for IPS enable\n");
5069 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5071 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5072 struct drm_device *dev = crtc->base.dev;
5073 struct drm_i915_private *dev_priv = to_i915(dev);
5075 if (!crtc_state->ips_enabled)
5078 if (IS_BROADWELL(dev_priv)) {
5079 mutex_lock(&dev_priv->pcu_lock);
5080 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5081 mutex_unlock(&dev_priv->pcu_lock);
5082 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
5083 if (intel_wait_for_register(dev_priv,
5084 IPS_CTL, IPS_ENABLE, 0,
5086 DRM_ERROR("Timed out waiting for IPS disable\n");
5088 I915_WRITE(IPS_CTL, 0);
5089 POSTING_READ(IPS_CTL);
5092 /* We need to wait for a vblank before we can disable the plane. */
5093 intel_wait_for_vblank(dev_priv, crtc->pipe);
5096 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5098 if (intel_crtc->overlay) {
5099 struct drm_device *dev = intel_crtc->base.dev;
5101 mutex_lock(&dev->struct_mutex);
5102 (void) intel_overlay_switch_off(intel_crtc->overlay);
5103 mutex_unlock(&dev->struct_mutex);
5106 /* Let userspace switch the overlay on again. In most cases userspace
5107 * has to recompute where to put it anyway.
5112 * intel_post_enable_primary - Perform operations after enabling primary plane
5113 * @crtc: the CRTC whose primary plane was just enabled
5114 * @new_crtc_state: the enabling state
5116 * Performs potentially sleeping operations that must be done after the primary
5117 * plane is enabled, such as updating FBC and IPS. Note that this may be
5118 * called due to an explicit primary plane update, or due to an implicit
5119 * re-enable that is caused when a sprite plane is updated to no longer
5120 * completely hide the primary plane.
5123 intel_post_enable_primary(struct drm_crtc *crtc,
5124 const struct intel_crtc_state *new_crtc_state)
5126 struct drm_device *dev = crtc->dev;
5127 struct drm_i915_private *dev_priv = to_i915(dev);
5128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5129 int pipe = intel_crtc->pipe;
5132 * Gen2 reports pipe underruns whenever all planes are disabled.
5133 * So don't enable underrun reporting before at least some planes
5135 * FIXME: Need to fix the logic to work when we turn off all planes
5136 * but leave the pipe running.
5138 if (IS_GEN2(dev_priv))
5139 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5141 /* Underruns don't always raise interrupts, so check manually. */
5142 intel_check_cpu_fifo_underruns(dev_priv);
5143 intel_check_pch_fifo_underruns(dev_priv);
5146 /* FIXME get rid of this and use pre_plane_update */
5148 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5150 struct drm_device *dev = crtc->dev;
5151 struct drm_i915_private *dev_priv = to_i915(dev);
5152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153 int pipe = intel_crtc->pipe;
5156 * Gen2 reports pipe underruns whenever all planes are disabled.
5157 * So disable underrun reporting before all the planes get disabled.
5159 if (IS_GEN2(dev_priv))
5160 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5162 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5165 * Vblank time updates from the shadow to live plane control register
5166 * are blocked if the memory self-refresh mode is active at that
5167 * moment. So to make sure the plane gets truly disabled, disable
5168 * first the self-refresh mode. The self-refresh enable bit in turn
5169 * will be checked/applied by the HW only at the next frame start
5170 * event which is after the vblank start event, so we need to have a
5171 * wait-for-vblank between disabling the plane and the pipe.
5173 if (HAS_GMCH_DISPLAY(dev_priv) &&
5174 intel_set_memory_cxsr(dev_priv, false))
5175 intel_wait_for_vblank(dev_priv, pipe);
5178 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5179 const struct intel_crtc_state *new_crtc_state)
5181 if (!old_crtc_state->ips_enabled)
5184 if (needs_modeset(&new_crtc_state->base))
5187 return !new_crtc_state->ips_enabled;
5190 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5191 const struct intel_crtc_state *new_crtc_state)
5193 if (!new_crtc_state->ips_enabled)
5196 if (needs_modeset(&new_crtc_state->base))
5200 * We can't read out IPS on broadwell, assume the worst and
5201 * forcibly enable IPS on the first fastset.
5203 if (new_crtc_state->update_pipe &&
5204 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5207 return !old_crtc_state->ips_enabled;
5210 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5211 const struct intel_crtc_state *crtc_state)
5213 if (!crtc_state->nv12_planes)
5216 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
5219 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5220 IS_CANNONLAKE(dev_priv))
5226 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5228 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5229 struct drm_device *dev = crtc->base.dev;
5230 struct drm_i915_private *dev_priv = to_i915(dev);
5231 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5232 struct intel_crtc_state *pipe_config =
5233 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5235 struct drm_plane *primary = crtc->base.primary;
5236 struct drm_plane_state *old_primary_state =
5237 drm_atomic_get_old_plane_state(old_state, primary);
5239 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5241 if (pipe_config->update_wm_post && pipe_config->base.active)
5242 intel_update_watermarks(crtc);
5244 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5245 hsw_enable_ips(pipe_config);
5247 if (old_primary_state) {
5248 struct drm_plane_state *new_primary_state =
5249 drm_atomic_get_new_plane_state(old_state, primary);
5251 intel_fbc_post_update(crtc);
5253 if (new_primary_state->visible &&
5254 (needs_modeset(&pipe_config->base) ||
5255 !old_primary_state->visible))
5256 intel_post_enable_primary(&crtc->base, pipe_config);
5259 /* Display WA 827 */
5260 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5261 !needs_nv12_wa(dev_priv, pipe_config)) {
5262 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5263 skl_wa_528(dev_priv, crtc->pipe, false);
5267 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5268 struct intel_crtc_state *pipe_config)
5270 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5271 struct drm_device *dev = crtc->base.dev;
5272 struct drm_i915_private *dev_priv = to_i915(dev);
5273 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5274 struct drm_plane *primary = crtc->base.primary;
5275 struct drm_plane_state *old_primary_state =
5276 drm_atomic_get_old_plane_state(old_state, primary);
5277 bool modeset = needs_modeset(&pipe_config->base);
5278 struct intel_atomic_state *old_intel_state =
5279 to_intel_atomic_state(old_state);
5281 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5282 hsw_disable_ips(old_crtc_state);
5284 if (old_primary_state) {
5285 struct intel_plane_state *new_primary_state =
5286 intel_atomic_get_new_plane_state(old_intel_state,
5287 to_intel_plane(primary));
5289 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5291 * Gen2 reports pipe underruns whenever all planes are disabled.
5292 * So disable underrun reporting before all the planes get disabled.
5294 if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5295 (modeset || !new_primary_state->base.visible))
5296 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5299 /* Display WA 827 */
5300 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5301 needs_nv12_wa(dev_priv, pipe_config)) {
5302 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5303 skl_wa_528(dev_priv, crtc->pipe, true);
5307 * Vblank time updates from the shadow to live plane control register
5308 * are blocked if the memory self-refresh mode is active at that
5309 * moment. So to make sure the plane gets truly disabled, disable
5310 * first the self-refresh mode. The self-refresh enable bit in turn
5311 * will be checked/applied by the HW only at the next frame start
5312 * event which is after the vblank start event, so we need to have a
5313 * wait-for-vblank between disabling the plane and the pipe.
5315 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5316 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5317 intel_wait_for_vblank(dev_priv, crtc->pipe);
5320 * IVB workaround: must disable low power watermarks for at least
5321 * one frame before enabling scaling. LP watermarks can be re-enabled
5322 * when scaling is disabled.
5324 * WaCxSRDisabledForSpriteScaling:ivb
5326 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5327 intel_wait_for_vblank(dev_priv, crtc->pipe);
5330 * If we're doing a modeset, we're done. No need to do any pre-vblank
5331 * watermark programming here.
5333 if (needs_modeset(&pipe_config->base))
5337 * For platforms that support atomic watermarks, program the
5338 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5339 * will be the intermediate values that are safe for both pre- and
5340 * post- vblank; when vblank happens, the 'active' values will be set
5341 * to the final 'target' values and we'll do this again to get the
5342 * optimal watermarks. For gen9+ platforms, the values we program here
5343 * will be the final target values which will get automatically latched
5344 * at vblank time; no further programming will be necessary.
5346 * If a platform hasn't been transitioned to atomic watermarks yet,
5347 * we'll continue to update watermarks the old way, if flags tell
5350 if (dev_priv->display.initial_watermarks != NULL)
5351 dev_priv->display.initial_watermarks(old_intel_state,
5353 else if (pipe_config->update_wm_pre)
5354 intel_update_watermarks(crtc);
5357 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5359 struct drm_device *dev = crtc->dev;
5360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5361 struct drm_plane *p;
5362 int pipe = intel_crtc->pipe;
5364 intel_crtc_dpms_overlay_disable(intel_crtc);
5366 drm_for_each_plane_mask(p, dev, plane_mask)
5367 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5370 * FIXME: Once we grow proper nuclear flip support out of this we need
5371 * to compute the mask of flip planes precisely. For the time being
5372 * consider this a flip to a NULL plane.
5374 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5377 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5378 struct intel_crtc_state *crtc_state,
5379 struct drm_atomic_state *old_state)
5381 struct drm_connector_state *conn_state;
5382 struct drm_connector *conn;
5385 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5386 struct intel_encoder *encoder =
5387 to_intel_encoder(conn_state->best_encoder);
5389 if (conn_state->crtc != crtc)
5392 if (encoder->pre_pll_enable)
5393 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5397 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5398 struct intel_crtc_state *crtc_state,
5399 struct drm_atomic_state *old_state)
5401 struct drm_connector_state *conn_state;
5402 struct drm_connector *conn;
5405 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5406 struct intel_encoder *encoder =
5407 to_intel_encoder(conn_state->best_encoder);
5409 if (conn_state->crtc != crtc)
5412 if (encoder->pre_enable)
5413 encoder->pre_enable(encoder, crtc_state, conn_state);
5417 static void intel_encoders_enable(struct drm_crtc *crtc,
5418 struct intel_crtc_state *crtc_state,
5419 struct drm_atomic_state *old_state)
5421 struct drm_connector_state *conn_state;
5422 struct drm_connector *conn;
5425 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5426 struct intel_encoder *encoder =
5427 to_intel_encoder(conn_state->best_encoder);
5429 if (conn_state->crtc != crtc)
5432 encoder->enable(encoder, crtc_state, conn_state);
5433 intel_opregion_notify_encoder(encoder, true);
5437 static void intel_encoders_disable(struct drm_crtc *crtc,
5438 struct intel_crtc_state *old_crtc_state,
5439 struct drm_atomic_state *old_state)
5441 struct drm_connector_state *old_conn_state;
5442 struct drm_connector *conn;
5445 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5446 struct intel_encoder *encoder =
5447 to_intel_encoder(old_conn_state->best_encoder);
5449 if (old_conn_state->crtc != crtc)
5452 intel_opregion_notify_encoder(encoder, false);
5453 encoder->disable(encoder, old_crtc_state, old_conn_state);
5457 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5458 struct intel_crtc_state *old_crtc_state,
5459 struct drm_atomic_state *old_state)
5461 struct drm_connector_state *old_conn_state;
5462 struct drm_connector *conn;
5465 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5466 struct intel_encoder *encoder =
5467 to_intel_encoder(old_conn_state->best_encoder);
5469 if (old_conn_state->crtc != crtc)
5472 if (encoder->post_disable)
5473 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5477 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5478 struct intel_crtc_state *old_crtc_state,
5479 struct drm_atomic_state *old_state)
5481 struct drm_connector_state *old_conn_state;
5482 struct drm_connector *conn;
5485 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5486 struct intel_encoder *encoder =
5487 to_intel_encoder(old_conn_state->best_encoder);
5489 if (old_conn_state->crtc != crtc)
5492 if (encoder->post_pll_disable)
5493 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5497 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5498 struct drm_atomic_state *old_state)
5500 struct drm_crtc *crtc = pipe_config->base.crtc;
5501 struct drm_device *dev = crtc->dev;
5502 struct drm_i915_private *dev_priv = to_i915(dev);
5503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5504 int pipe = intel_crtc->pipe;
5505 struct intel_atomic_state *old_intel_state =
5506 to_intel_atomic_state(old_state);
5508 if (WARN_ON(intel_crtc->active))
5512 * Sometimes spurious CPU pipe underruns happen during FDI
5513 * training, at least with VGA+HDMI cloning. Suppress them.
5515 * On ILK we get an occasional spurious CPU pipe underruns
5516 * between eDP port A enable and vdd enable. Also PCH port
5517 * enable seems to result in the occasional CPU pipe underrun.
5519 * Spurious PCH underruns also occur during PCH enabling.
5521 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5522 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5524 if (intel_crtc->config->has_pch_encoder)
5525 intel_prepare_shared_dpll(intel_crtc);
5527 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5528 intel_dp_set_m_n(intel_crtc, M1_N1);
5530 intel_set_pipe_timings(intel_crtc);
5531 intel_set_pipe_src_size(intel_crtc);
5533 if (intel_crtc->config->has_pch_encoder) {
5534 intel_cpu_transcoder_set_m_n(intel_crtc,
5535 &intel_crtc->config->fdi_m_n, NULL);
5538 ironlake_set_pipeconf(crtc);
5540 intel_crtc->active = true;
5542 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5544 if (intel_crtc->config->has_pch_encoder) {
5545 /* Note: FDI PLL enabling _must_ be done before we enable the
5546 * cpu pipes, hence this is separate from all the other fdi/pch
5548 ironlake_fdi_pll_enable(intel_crtc);
5550 assert_fdi_tx_disabled(dev_priv, pipe);
5551 assert_fdi_rx_disabled(dev_priv, pipe);
5554 ironlake_pfit_enable(intel_crtc);
5557 * On ILK+ LUT must be loaded before the pipe is running but with
5560 intel_color_load_luts(&pipe_config->base);
5562 if (dev_priv->display.initial_watermarks != NULL)
5563 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5564 intel_enable_pipe(pipe_config);
5566 if (intel_crtc->config->has_pch_encoder)
5567 ironlake_pch_enable(old_intel_state, pipe_config);
5569 assert_vblank_disabled(crtc);
5570 drm_crtc_vblank_on(crtc);
5572 intel_encoders_enable(crtc, pipe_config, old_state);
5574 if (HAS_PCH_CPT(dev_priv))
5575 cpt_verify_modeset(dev, intel_crtc->pipe);
5578 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5579 * And a second vblank wait is needed at least on ILK with
5580 * some interlaced HDMI modes. Let's do the double wait always
5581 * in case there are more corner cases we don't know about.
5583 if (intel_crtc->config->has_pch_encoder) {
5584 intel_wait_for_vblank(dev_priv, pipe);
5585 intel_wait_for_vblank(dev_priv, pipe);
5587 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5588 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5591 /* IPS only exists on ULT machines and is tied to pipe A. */
5592 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5594 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5597 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5598 enum pipe pipe, bool apply)
5600 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5601 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5608 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5611 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5614 enum pipe pipe = crtc->pipe;
5617 val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5619 /* Program B credit equally to all pipes */
5620 val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5622 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5625 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5626 struct drm_atomic_state *old_state)
5628 struct drm_crtc *crtc = pipe_config->base.crtc;
5629 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5631 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5632 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5633 struct intel_atomic_state *old_intel_state =
5634 to_intel_atomic_state(old_state);
5635 bool psl_clkgate_wa;
5638 if (WARN_ON(intel_crtc->active))
5641 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5643 if (intel_crtc->config->shared_dpll)
5644 intel_enable_shared_dpll(intel_crtc);
5646 if (INTEL_GEN(dev_priv) >= 11)
5647 icl_map_plls_to_ports(crtc, pipe_config, old_state);
5649 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5651 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5652 intel_dp_set_m_n(intel_crtc, M1_N1);
5654 if (!transcoder_is_dsi(cpu_transcoder))
5655 intel_set_pipe_timings(intel_crtc);
5657 intel_set_pipe_src_size(intel_crtc);
5659 if (cpu_transcoder != TRANSCODER_EDP &&
5660 !transcoder_is_dsi(cpu_transcoder)) {
5661 I915_WRITE(PIPE_MULT(cpu_transcoder),
5662 intel_crtc->config->pixel_multiplier - 1);
5665 if (intel_crtc->config->has_pch_encoder) {
5666 intel_cpu_transcoder_set_m_n(intel_crtc,
5667 &intel_crtc->config->fdi_m_n, NULL);
5670 if (!transcoder_is_dsi(cpu_transcoder))
5671 haswell_set_pipeconf(crtc);
5673 haswell_set_pipemisc(crtc);
5675 intel_color_set_csc(&pipe_config->base);
5677 intel_crtc->active = true;
5679 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5680 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5681 intel_crtc->config->pch_pfit.enabled;
5683 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5685 if (INTEL_GEN(dev_priv) >= 9)
5686 skylake_pfit_enable(intel_crtc);
5688 ironlake_pfit_enable(intel_crtc);
5691 * On ILK+ LUT must be loaded before the pipe is running but with
5694 intel_color_load_luts(&pipe_config->base);
5697 * Display WA #1153: enable hardware to bypass the alpha math
5698 * and rounding for per-pixel values 00 and 0xff
5700 if (INTEL_GEN(dev_priv) >= 11) {
5701 pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
5702 if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
5703 I915_WRITE_FW(PIPE_CHICKEN(pipe),
5704 pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
5707 intel_ddi_set_pipe_settings(pipe_config);
5708 if (!transcoder_is_dsi(cpu_transcoder))
5709 intel_ddi_enable_transcoder_func(pipe_config);
5711 if (dev_priv->display.initial_watermarks != NULL)
5712 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5714 if (INTEL_GEN(dev_priv) >= 11)
5715 icl_pipe_mbus_enable(intel_crtc);
5717 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5718 if (!transcoder_is_dsi(cpu_transcoder))
5719 intel_enable_pipe(pipe_config);
5721 if (intel_crtc->config->has_pch_encoder)
5722 lpt_pch_enable(old_intel_state, pipe_config);
5724 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5725 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5727 assert_vblank_disabled(crtc);
5728 drm_crtc_vblank_on(crtc);
5730 intel_encoders_enable(crtc, pipe_config, old_state);
5732 if (psl_clkgate_wa) {
5733 intel_wait_for_vblank(dev_priv, pipe);
5734 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5737 /* If we change the relative order between pipe/planes enabling, we need
5738 * to change the workaround. */
5739 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5740 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5741 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5742 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5746 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5748 struct drm_device *dev = crtc->base.dev;
5749 struct drm_i915_private *dev_priv = to_i915(dev);
5750 int pipe = crtc->pipe;
5752 /* To avoid upsetting the power well on haswell only disable the pfit if
5753 * it's in use. The hw state code will make sure we get this right. */
5754 if (force || crtc->config->pch_pfit.enabled) {
5755 I915_WRITE(PF_CTL(pipe), 0);
5756 I915_WRITE(PF_WIN_POS(pipe), 0);
5757 I915_WRITE(PF_WIN_SZ(pipe), 0);
5761 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5762 struct drm_atomic_state *old_state)
5764 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5765 struct drm_device *dev = crtc->dev;
5766 struct drm_i915_private *dev_priv = to_i915(dev);
5767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5768 int pipe = intel_crtc->pipe;
5771 * Sometimes spurious CPU pipe underruns happen when the
5772 * pipe is already disabled, but FDI RX/TX is still enabled.
5773 * Happens at least with VGA+HDMI cloning. Suppress them.
5775 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5776 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5778 intel_encoders_disable(crtc, old_crtc_state, old_state);
5780 drm_crtc_vblank_off(crtc);
5781 assert_vblank_disabled(crtc);
5783 intel_disable_pipe(old_crtc_state);
5785 ironlake_pfit_disable(intel_crtc, false);
5787 if (intel_crtc->config->has_pch_encoder)
5788 ironlake_fdi_disable(crtc);
5790 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5792 if (intel_crtc->config->has_pch_encoder) {
5793 ironlake_disable_pch_transcoder(dev_priv, pipe);
5795 if (HAS_PCH_CPT(dev_priv)) {
5799 /* disable TRANS_DP_CTL */
5800 reg = TRANS_DP_CTL(pipe);
5801 temp = I915_READ(reg);
5802 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5803 TRANS_DP_PORT_SEL_MASK);
5804 temp |= TRANS_DP_PORT_SEL_NONE;
5805 I915_WRITE(reg, temp);
5807 /* disable DPLL_SEL */
5808 temp = I915_READ(PCH_DPLL_SEL);
5809 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5810 I915_WRITE(PCH_DPLL_SEL, temp);
5813 ironlake_fdi_pll_disable(intel_crtc);
5816 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5817 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5820 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5821 struct drm_atomic_state *old_state)
5823 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5824 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5826 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
5828 intel_encoders_disable(crtc, old_crtc_state, old_state);
5830 drm_crtc_vblank_off(crtc);
5831 assert_vblank_disabled(crtc);
5833 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5834 if (!transcoder_is_dsi(cpu_transcoder))
5835 intel_disable_pipe(old_crtc_state);
5837 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
5838 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
5840 if (!transcoder_is_dsi(cpu_transcoder))
5841 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5843 if (INTEL_GEN(dev_priv) >= 9)
5844 skylake_scaler_disable(intel_crtc);
5846 ironlake_pfit_disable(intel_crtc, false);
5848 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5850 if (INTEL_GEN(dev_priv) >= 11)
5851 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
5854 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5856 struct drm_device *dev = crtc->base.dev;
5857 struct drm_i915_private *dev_priv = to_i915(dev);
5858 struct intel_crtc_state *pipe_config = crtc->config;
5860 if (!pipe_config->gmch_pfit.control)
5864 * The panel fitter should only be adjusted whilst the pipe is disabled,
5865 * according to register description and PRM.
5867 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5868 assert_pipe_disabled(dev_priv, crtc->pipe);
5870 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5871 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5873 /* Border color in case we don't scale up to the full screen. Black by
5874 * default, change to something else for debugging. */
5875 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5878 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
5880 if (IS_ICELAKE(dev_priv))
5881 return port >= PORT_C && port <= PORT_F;
5886 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
5888 if (!intel_port_is_tc(dev_priv, port))
5889 return PORT_TC_NONE;
5891 return port - PORT_C;
5894 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5898 return POWER_DOMAIN_PORT_DDI_A_LANES;
5900 return POWER_DOMAIN_PORT_DDI_B_LANES;
5902 return POWER_DOMAIN_PORT_DDI_C_LANES;
5904 return POWER_DOMAIN_PORT_DDI_D_LANES;
5906 return POWER_DOMAIN_PORT_DDI_E_LANES;
5908 return POWER_DOMAIN_PORT_DDI_F_LANES;
5911 return POWER_DOMAIN_PORT_OTHER;
5915 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5916 struct intel_crtc_state *crtc_state)
5918 struct drm_device *dev = crtc->dev;
5919 struct drm_i915_private *dev_priv = to_i915(dev);
5920 struct drm_encoder *encoder;
5921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5922 enum pipe pipe = intel_crtc->pipe;
5924 enum transcoder transcoder = crtc_state->cpu_transcoder;
5926 if (!crtc_state->base.active)
5929 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5930 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5931 if (crtc_state->pch_pfit.enabled ||
5932 crtc_state->pch_pfit.force_thru)
5933 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5935 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5936 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5938 mask |= BIT_ULL(intel_encoder->power_domain);
5941 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5942 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5944 if (crtc_state->shared_dpll)
5945 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5951 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5952 struct intel_crtc_state *crtc_state)
5954 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5956 enum intel_display_power_domain domain;
5957 u64 domains, new_domains, old_domains;
5959 old_domains = intel_crtc->enabled_power_domains;
5960 intel_crtc->enabled_power_domains = new_domains =
5961 get_crtc_power_domains(crtc, crtc_state);
5963 domains = new_domains & ~old_domains;
5965 for_each_power_domain(domain, domains)
5966 intel_display_power_get(dev_priv, domain);
5968 return old_domains & ~new_domains;
5971 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5974 enum intel_display_power_domain domain;
5976 for_each_power_domain(domain, domains)
5977 intel_display_power_put(dev_priv, domain);
5980 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5981 struct drm_atomic_state *old_state)
5983 struct intel_atomic_state *old_intel_state =
5984 to_intel_atomic_state(old_state);
5985 struct drm_crtc *crtc = pipe_config->base.crtc;
5986 struct drm_device *dev = crtc->dev;
5987 struct drm_i915_private *dev_priv = to_i915(dev);
5988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5989 int pipe = intel_crtc->pipe;
5991 if (WARN_ON(intel_crtc->active))
5994 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5995 intel_dp_set_m_n(intel_crtc, M1_N1);
5997 intel_set_pipe_timings(intel_crtc);
5998 intel_set_pipe_src_size(intel_crtc);
6000 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6001 struct drm_i915_private *dev_priv = to_i915(dev);
6003 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6004 I915_WRITE(CHV_CANVAS(pipe), 0);
6007 i9xx_set_pipeconf(intel_crtc);
6009 intel_crtc->active = true;
6011 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6013 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6015 if (IS_CHERRYVIEW(dev_priv)) {
6016 chv_prepare_pll(intel_crtc, intel_crtc->config);
6017 chv_enable_pll(intel_crtc, intel_crtc->config);
6019 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6020 vlv_enable_pll(intel_crtc, intel_crtc->config);
6023 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6025 i9xx_pfit_enable(intel_crtc);
6027 intel_color_load_luts(&pipe_config->base);
6029 dev_priv->display.initial_watermarks(old_intel_state,
6031 intel_enable_pipe(pipe_config);
6033 assert_vblank_disabled(crtc);
6034 drm_crtc_vblank_on(crtc);
6036 intel_encoders_enable(crtc, pipe_config, old_state);
6039 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6041 struct drm_device *dev = crtc->base.dev;
6042 struct drm_i915_private *dev_priv = to_i915(dev);
6044 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6045 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6048 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6049 struct drm_atomic_state *old_state)
6051 struct intel_atomic_state *old_intel_state =
6052 to_intel_atomic_state(old_state);
6053 struct drm_crtc *crtc = pipe_config->base.crtc;
6054 struct drm_device *dev = crtc->dev;
6055 struct drm_i915_private *dev_priv = to_i915(dev);
6056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6057 enum pipe pipe = intel_crtc->pipe;
6059 if (WARN_ON(intel_crtc->active))
6062 i9xx_set_pll_dividers(intel_crtc);
6064 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6065 intel_dp_set_m_n(intel_crtc, M1_N1);
6067 intel_set_pipe_timings(intel_crtc);
6068 intel_set_pipe_src_size(intel_crtc);
6070 i9xx_set_pipeconf(intel_crtc);
6072 intel_crtc->active = true;
6074 if (!IS_GEN2(dev_priv))
6075 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6077 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6079 i9xx_enable_pll(intel_crtc, pipe_config);
6081 i9xx_pfit_enable(intel_crtc);
6083 intel_color_load_luts(&pipe_config->base);
6085 if (dev_priv->display.initial_watermarks != NULL)
6086 dev_priv->display.initial_watermarks(old_intel_state,
6087 intel_crtc->config);
6089 intel_update_watermarks(intel_crtc);
6090 intel_enable_pipe(pipe_config);
6092 assert_vblank_disabled(crtc);
6093 drm_crtc_vblank_on(crtc);
6095 intel_encoders_enable(crtc, pipe_config, old_state);
6098 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6100 struct drm_device *dev = crtc->base.dev;
6101 struct drm_i915_private *dev_priv = to_i915(dev);
6103 if (!crtc->config->gmch_pfit.control)
6106 assert_pipe_disabled(dev_priv, crtc->pipe);
6108 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6109 I915_READ(PFIT_CONTROL));
6110 I915_WRITE(PFIT_CONTROL, 0);
6113 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6114 struct drm_atomic_state *old_state)
6116 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6117 struct drm_device *dev = crtc->dev;
6118 struct drm_i915_private *dev_priv = to_i915(dev);
6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120 int pipe = intel_crtc->pipe;
6123 * On gen2 planes are double buffered but the pipe isn't, so we must
6124 * wait for planes to fully turn off before disabling the pipe.
6126 if (IS_GEN2(dev_priv))
6127 intel_wait_for_vblank(dev_priv, pipe);
6129 intel_encoders_disable(crtc, old_crtc_state, old_state);
6131 drm_crtc_vblank_off(crtc);
6132 assert_vblank_disabled(crtc);
6134 intel_disable_pipe(old_crtc_state);
6136 i9xx_pfit_disable(intel_crtc);
6138 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6140 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6141 if (IS_CHERRYVIEW(dev_priv))
6142 chv_disable_pll(dev_priv, pipe);
6143 else if (IS_VALLEYVIEW(dev_priv))
6144 vlv_disable_pll(dev_priv, pipe);
6146 i9xx_disable_pll(intel_crtc);
6149 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6151 if (!IS_GEN2(dev_priv))
6152 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6154 if (!dev_priv->display.initial_watermarks)
6155 intel_update_watermarks(intel_crtc);
6157 /* clock the pipe down to 640x480@60 to potentially save power */
6158 if (IS_I830(dev_priv))
6159 i830_enable_pipe(dev_priv, pipe);
6162 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6163 struct drm_modeset_acquire_ctx *ctx)
6165 struct intel_encoder *encoder;
6166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6168 enum intel_display_power_domain domain;
6169 struct intel_plane *plane;
6171 struct drm_atomic_state *state;
6172 struct intel_crtc_state *crtc_state;
6175 if (!intel_crtc->active)
6178 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6179 const struct intel_plane_state *plane_state =
6180 to_intel_plane_state(plane->base.state);
6182 if (plane_state->base.visible)
6183 intel_plane_disable_noatomic(intel_crtc, plane);
6186 state = drm_atomic_state_alloc(crtc->dev);
6188 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6189 crtc->base.id, crtc->name);
6193 state->acquire_ctx = ctx;
6195 /* Everything's already locked, -EDEADLK can't happen. */
6196 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6197 ret = drm_atomic_add_affected_connectors(state, crtc);
6199 WARN_ON(IS_ERR(crtc_state) || ret);
6201 dev_priv->display.crtc_disable(crtc_state, state);
6203 drm_atomic_state_put(state);
6205 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6206 crtc->base.id, crtc->name);
6208 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6209 crtc->state->active = false;
6210 intel_crtc->active = false;
6211 crtc->enabled = false;
6212 crtc->state->connector_mask = 0;
6213 crtc->state->encoder_mask = 0;
6215 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6216 encoder->base.crtc = NULL;
6218 intel_fbc_disable(intel_crtc);
6219 intel_update_watermarks(intel_crtc);
6220 intel_disable_shared_dpll(intel_crtc);
6222 domains = intel_crtc->enabled_power_domains;
6223 for_each_power_domain(domain, domains)
6224 intel_display_power_put(dev_priv, domain);
6225 intel_crtc->enabled_power_domains = 0;
6227 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6228 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6229 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6233 * turn all crtc's off, but do not adjust state
6234 * This has to be paired with a call to intel_modeset_setup_hw_state.
6236 int intel_display_suspend(struct drm_device *dev)
6238 struct drm_i915_private *dev_priv = to_i915(dev);
6239 struct drm_atomic_state *state;
6242 state = drm_atomic_helper_suspend(dev);
6243 ret = PTR_ERR_OR_ZERO(state);
6245 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6247 dev_priv->modeset_restore_state = state;
6251 void intel_encoder_destroy(struct drm_encoder *encoder)
6253 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6255 drm_encoder_cleanup(encoder);
6256 kfree(intel_encoder);
6259 /* Cross check the actual hw state with our own modeset state tracking (and it's
6260 * internal consistency). */
6261 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6262 struct drm_connector_state *conn_state)
6264 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6266 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6267 connector->base.base.id,
6268 connector->base.name);
6270 if (connector->get_hw_state(connector)) {
6271 struct intel_encoder *encoder = connector->encoder;
6273 I915_STATE_WARN(!crtc_state,
6274 "connector enabled without attached crtc\n");
6279 I915_STATE_WARN(!crtc_state->active,
6280 "connector is active, but attached crtc isn't\n");
6282 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6285 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6286 "atomic encoder doesn't match attached encoder\n");
6288 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6289 "attached encoder crtc differs from connector crtc\n");
6291 I915_STATE_WARN(crtc_state && crtc_state->active,
6292 "attached crtc is active, but connector isn't\n");
6293 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6294 "best encoder set without crtc!\n");
6298 int intel_connector_init(struct intel_connector *connector)
6300 struct intel_digital_connector_state *conn_state;
6303 * Allocate enough memory to hold intel_digital_connector_state,
6304 * This might be a few bytes too many, but for connectors that don't
6305 * need it we'll free the state and allocate a smaller one on the first
6306 * succesful commit anyway.
6308 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6312 __drm_atomic_helper_connector_reset(&connector->base,
6318 struct intel_connector *intel_connector_alloc(void)
6320 struct intel_connector *connector;
6322 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6326 if (intel_connector_init(connector) < 0) {
6335 * Free the bits allocated by intel_connector_alloc.
6336 * This should only be used after intel_connector_alloc has returned
6337 * successfully, and before drm_connector_init returns successfully.
6338 * Otherwise the destroy callbacks for the connector and the state should
6339 * take care of proper cleanup/free
6341 void intel_connector_free(struct intel_connector *connector)
6343 kfree(to_intel_digital_connector_state(connector->base.state));
6347 /* Simple connector->get_hw_state implementation for encoders that support only
6348 * one connector and no cloning and hence the encoder state determines the state
6349 * of the connector. */
6350 bool intel_connector_get_hw_state(struct intel_connector *connector)
6353 struct intel_encoder *encoder = connector->encoder;
6355 return encoder->get_hw_state(encoder, &pipe);
6358 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6360 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6361 return crtc_state->fdi_lanes;
6366 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6367 struct intel_crtc_state *pipe_config)
6369 struct drm_i915_private *dev_priv = to_i915(dev);
6370 struct drm_atomic_state *state = pipe_config->base.state;
6371 struct intel_crtc *other_crtc;
6372 struct intel_crtc_state *other_crtc_state;
6374 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6375 pipe_name(pipe), pipe_config->fdi_lanes);
6376 if (pipe_config->fdi_lanes > 4) {
6377 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6378 pipe_name(pipe), pipe_config->fdi_lanes);
6382 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6383 if (pipe_config->fdi_lanes > 2) {
6384 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6385 pipe_config->fdi_lanes);
6392 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6395 /* Ivybridge 3 pipe is really complicated */
6400 if (pipe_config->fdi_lanes <= 2)
6403 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6405 intel_atomic_get_crtc_state(state, other_crtc);
6406 if (IS_ERR(other_crtc_state))
6407 return PTR_ERR(other_crtc_state);
6409 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6410 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6411 pipe_name(pipe), pipe_config->fdi_lanes);
6416 if (pipe_config->fdi_lanes > 2) {
6417 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6418 pipe_name(pipe), pipe_config->fdi_lanes);
6422 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6424 intel_atomic_get_crtc_state(state, other_crtc);
6425 if (IS_ERR(other_crtc_state))
6426 return PTR_ERR(other_crtc_state);
6428 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6429 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6439 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6440 struct intel_crtc_state *pipe_config)
6442 struct drm_device *dev = intel_crtc->base.dev;
6443 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6444 int lane, link_bw, fdi_dotclock, ret;
6445 bool needs_recompute = false;
6448 /* FDI is a binary signal running at ~2.7GHz, encoding
6449 * each output octet as 10 bits. The actual frequency
6450 * is stored as a divider into a 100MHz clock, and the
6451 * mode pixel clock is stored in units of 1KHz.
6452 * Hence the bw of each lane in terms of the mode signal
6455 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6457 fdi_dotclock = adjusted_mode->crtc_clock;
6459 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6460 pipe_config->pipe_bpp);
6462 pipe_config->fdi_lanes = lane;
6464 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6465 link_bw, &pipe_config->fdi_m_n, false);
6467 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6468 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6469 pipe_config->pipe_bpp -= 2*3;
6470 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6471 pipe_config->pipe_bpp);
6472 needs_recompute = true;
6473 pipe_config->bw_constrained = true;
6478 if (needs_recompute)
6484 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6486 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6489 /* IPS only exists on ULT machines and is tied to pipe A. */
6490 if (!hsw_crtc_supports_ips(crtc))
6493 if (!i915_modparams.enable_ips)
6496 if (crtc_state->pipe_bpp > 24)
6500 * We compare against max which means we must take
6501 * the increased cdclk requirement into account when
6502 * calculating the new cdclk.
6504 * Should measure whether using a lower cdclk w/o IPS
6506 if (IS_BROADWELL(dev_priv) &&
6507 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6513 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6515 struct drm_i915_private *dev_priv =
6516 to_i915(crtc_state->base.crtc->dev);
6517 struct intel_atomic_state *intel_state =
6518 to_intel_atomic_state(crtc_state->base.state);
6520 if (!hsw_crtc_state_ips_capable(crtc_state))
6523 if (crtc_state->ips_force_disable)
6526 /* IPS should be fine as long as at least one plane is enabled. */
6527 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6530 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6531 if (IS_BROADWELL(dev_priv) &&
6532 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6538 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6540 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6542 /* GDG double wide on either pipe, otherwise pipe A only */
6543 return INTEL_GEN(dev_priv) < 4 &&
6544 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6547 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6549 uint32_t pixel_rate;
6551 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6554 * We only use IF-ID interlacing. If we ever use
6555 * PF-ID we'll need to adjust the pixel_rate here.
6558 if (pipe_config->pch_pfit.enabled) {
6559 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6560 uint32_t pfit_size = pipe_config->pch_pfit.size;
6562 pipe_w = pipe_config->pipe_src_w;
6563 pipe_h = pipe_config->pipe_src_h;
6565 pfit_w = (pfit_size >> 16) & 0xFFFF;
6566 pfit_h = pfit_size & 0xFFFF;
6567 if (pipe_w < pfit_w)
6569 if (pipe_h < pfit_h)
6572 if (WARN_ON(!pfit_w || !pfit_h))
6575 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6582 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6584 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6586 if (HAS_GMCH_DISPLAY(dev_priv))
6587 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6588 crtc_state->pixel_rate =
6589 crtc_state->base.adjusted_mode.crtc_clock;
6591 crtc_state->pixel_rate =
6592 ilk_pipe_pixel_rate(crtc_state);
6595 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6596 struct intel_crtc_state *pipe_config)
6598 struct drm_device *dev = crtc->base.dev;
6599 struct drm_i915_private *dev_priv = to_i915(dev);
6600 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6601 int clock_limit = dev_priv->max_dotclk_freq;
6603 if (INTEL_GEN(dev_priv) < 4) {
6604 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6607 * Enable double wide mode when the dot clock
6608 * is > 90% of the (display) core speed.
6610 if (intel_crtc_supports_double_wide(crtc) &&
6611 adjusted_mode->crtc_clock > clock_limit) {
6612 clock_limit = dev_priv->max_dotclk_freq;
6613 pipe_config->double_wide = true;
6617 if (adjusted_mode->crtc_clock > clock_limit) {
6618 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6619 adjusted_mode->crtc_clock, clock_limit,
6620 yesno(pipe_config->double_wide));
6624 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6626 * There is only one pipe CSC unit per pipe, and we need that
6627 * for output conversion from RGB->YCBCR. So if CTM is already
6628 * applied we can't support YCBCR420 output.
6630 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6635 * Pipe horizontal size must be even in:
6637 * - LVDS dual channel mode
6638 * - Double wide pipe
6640 if (pipe_config->pipe_src_w & 1) {
6641 if (pipe_config->double_wide) {
6642 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6646 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6647 intel_is_dual_link_lvds(dev)) {
6648 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6653 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6654 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6656 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6657 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6660 intel_crtc_compute_pixel_rate(pipe_config);
6662 if (pipe_config->has_pch_encoder)
6663 return ironlake_fdi_compute_config(crtc, pipe_config);
6669 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6671 while (*num > DATA_LINK_M_N_MASK ||
6672 *den > DATA_LINK_M_N_MASK) {
6678 static void compute_m_n(unsigned int m, unsigned int n,
6679 uint32_t *ret_m, uint32_t *ret_n,
6683 * Reduce M/N as much as possible without loss in precision. Several DP
6684 * dongles in particular seem to be fussy about too large *link* M/N
6685 * values. The passed in values are more likely to have the least
6686 * significant bits zero than M after rounding below, so do this first.
6689 while ((m & 1) == 0 && (n & 1) == 0) {
6695 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6696 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6697 intel_reduce_m_n_ratio(ret_m, ret_n);
6701 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6702 int pixel_clock, int link_clock,
6703 struct intel_link_m_n *m_n,
6708 compute_m_n(bits_per_pixel * pixel_clock,
6709 link_clock * nlanes * 8,
6710 &m_n->gmch_m, &m_n->gmch_n,
6713 compute_m_n(pixel_clock, link_clock,
6714 &m_n->link_m, &m_n->link_n,
6718 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6720 if (i915_modparams.panel_use_ssc >= 0)
6721 return i915_modparams.panel_use_ssc != 0;
6722 return dev_priv->vbt.lvds_use_ssc
6723 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6726 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6728 return (1 << dpll->n) << 16 | dpll->m2;
6731 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6733 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6736 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6737 struct intel_crtc_state *crtc_state,
6738 struct dpll *reduced_clock)
6740 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6743 if (IS_PINEVIEW(dev_priv)) {
6744 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6746 fp2 = pnv_dpll_compute_fp(reduced_clock);
6748 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6750 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6753 crtc_state->dpll_hw_state.fp0 = fp;
6755 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6757 crtc_state->dpll_hw_state.fp1 = fp2;
6759 crtc_state->dpll_hw_state.fp1 = fp;
6763 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6769 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6770 * and set it to a reasonable value instead.
6772 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6773 reg_val &= 0xffffff00;
6774 reg_val |= 0x00000030;
6775 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6777 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6778 reg_val &= 0x00ffffff;
6779 reg_val |= 0x8c000000;
6780 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6782 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6783 reg_val &= 0xffffff00;
6784 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6786 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6787 reg_val &= 0x00ffffff;
6788 reg_val |= 0xb0000000;
6789 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6792 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6793 struct intel_link_m_n *m_n)
6795 struct drm_device *dev = crtc->base.dev;
6796 struct drm_i915_private *dev_priv = to_i915(dev);
6797 int pipe = crtc->pipe;
6799 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6800 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6801 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6802 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6805 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6806 struct intel_link_m_n *m_n,
6807 struct intel_link_m_n *m2_n2)
6809 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6810 int pipe = crtc->pipe;
6811 enum transcoder transcoder = crtc->config->cpu_transcoder;
6813 if (INTEL_GEN(dev_priv) >= 5) {
6814 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6815 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6816 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6817 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6818 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6819 * for gen < 8) and if DRRS is supported (to make sure the
6820 * registers are not unnecessarily accessed).
6822 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6823 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6824 I915_WRITE(PIPE_DATA_M2(transcoder),
6825 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6826 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6827 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6828 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6831 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6832 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6833 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6834 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6838 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6840 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6843 dp_m_n = &crtc->config->dp_m_n;
6844 dp_m2_n2 = &crtc->config->dp_m2_n2;
6845 } else if (m_n == M2_N2) {
6848 * M2_N2 registers are not supported. Hence m2_n2 divider value
6849 * needs to be programmed into M1_N1.
6851 dp_m_n = &crtc->config->dp_m2_n2;
6853 DRM_ERROR("Unsupported divider value\n");
6857 if (crtc->config->has_pch_encoder)
6858 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6860 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6863 static void vlv_compute_dpll(struct intel_crtc *crtc,
6864 struct intel_crtc_state *pipe_config)
6866 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6867 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6868 if (crtc->pipe != PIPE_A)
6869 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6871 /* DPLL not used with DSI, but still need the rest set up */
6872 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6873 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6874 DPLL_EXT_BUFFER_ENABLE_VLV;
6876 pipe_config->dpll_hw_state.dpll_md =
6877 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6880 static void chv_compute_dpll(struct intel_crtc *crtc,
6881 struct intel_crtc_state *pipe_config)
6883 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6884 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6885 if (crtc->pipe != PIPE_A)
6886 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6888 /* DPLL not used with DSI, but still need the rest set up */
6889 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6890 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6892 pipe_config->dpll_hw_state.dpll_md =
6893 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6896 static void vlv_prepare_pll(struct intel_crtc *crtc,
6897 const struct intel_crtc_state *pipe_config)
6899 struct drm_device *dev = crtc->base.dev;
6900 struct drm_i915_private *dev_priv = to_i915(dev);
6901 enum pipe pipe = crtc->pipe;
6903 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6904 u32 coreclk, reg_val;
6907 I915_WRITE(DPLL(pipe),
6908 pipe_config->dpll_hw_state.dpll &
6909 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6911 /* No need to actually set up the DPLL with DSI */
6912 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6915 mutex_lock(&dev_priv->sb_lock);
6917 bestn = pipe_config->dpll.n;
6918 bestm1 = pipe_config->dpll.m1;
6919 bestm2 = pipe_config->dpll.m2;
6920 bestp1 = pipe_config->dpll.p1;
6921 bestp2 = pipe_config->dpll.p2;
6923 /* See eDP HDMI DPIO driver vbios notes doc */
6925 /* PLL B needs special handling */
6927 vlv_pllb_recal_opamp(dev_priv, pipe);
6929 /* Set up Tx target for periodic Rcomp update */
6930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6932 /* Disable target IRef on PLL */
6933 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6934 reg_val &= 0x00ffffff;
6935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6937 /* Disable fast lock */
6938 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6940 /* Set idtafcrecal before PLL is enabled */
6941 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6942 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6943 mdiv |= ((bestn << DPIO_N_SHIFT));
6944 mdiv |= (1 << DPIO_K_SHIFT);
6947 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6948 * but we don't support that).
6949 * Note: don't use the DAC post divider as it seems unstable.
6951 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6954 mdiv |= DPIO_ENABLE_CALIBRATION;
6955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6957 /* Set HBR and RBR LPF coefficients */
6958 if (pipe_config->port_clock == 162000 ||
6959 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6960 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6961 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6964 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6967 if (intel_crtc_has_dp_encoder(pipe_config)) {
6968 /* Use SSC source */
6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6975 } else { /* HDMI or VGA */
6976 /* Use bend source */
6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6981 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6985 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6986 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6987 if (intel_crtc_has_dp_encoder(crtc->config))
6988 coreclk |= 0x01000000;
6989 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6991 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6992 mutex_unlock(&dev_priv->sb_lock);
6995 static void chv_prepare_pll(struct intel_crtc *crtc,
6996 const struct intel_crtc_state *pipe_config)
6998 struct drm_device *dev = crtc->base.dev;
6999 struct drm_i915_private *dev_priv = to_i915(dev);
7000 enum pipe pipe = crtc->pipe;
7001 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7002 u32 loopfilter, tribuf_calcntr;
7003 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7007 /* Enable Refclk and SSC */
7008 I915_WRITE(DPLL(pipe),
7009 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7011 /* No need to actually set up the DPLL with DSI */
7012 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7015 bestn = pipe_config->dpll.n;
7016 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7017 bestm1 = pipe_config->dpll.m1;
7018 bestm2 = pipe_config->dpll.m2 >> 22;
7019 bestp1 = pipe_config->dpll.p1;
7020 bestp2 = pipe_config->dpll.p2;
7021 vco = pipe_config->dpll.vco;
7025 mutex_lock(&dev_priv->sb_lock);
7027 /* p1 and p2 divider */
7028 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7029 5 << DPIO_CHV_S1_DIV_SHIFT |
7030 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7031 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7032 1 << DPIO_CHV_K_DIV_SHIFT);
7034 /* Feedback post-divider - m2 */
7035 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7037 /* Feedback refclk divider - n and m1 */
7038 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7039 DPIO_CHV_M1_DIV_BY_2 |
7040 1 << DPIO_CHV_N_DIV_SHIFT);
7042 /* M2 fraction division */
7043 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7045 /* M2 fraction division enable */
7046 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7047 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7048 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7050 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7051 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7053 /* Program digital lock detect threshold */
7054 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7055 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7056 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7057 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7059 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7060 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7063 if (vco == 5400000) {
7064 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7065 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7066 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7067 tribuf_calcntr = 0x9;
7068 } else if (vco <= 6200000) {
7069 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7070 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7071 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7072 tribuf_calcntr = 0x9;
7073 } else if (vco <= 6480000) {
7074 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7075 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7076 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7077 tribuf_calcntr = 0x8;
7079 /* Not supported. Apply the same limits as in the max case */
7080 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7081 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7082 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7085 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7087 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7088 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7089 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7090 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7093 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7094 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7097 mutex_unlock(&dev_priv->sb_lock);
7101 * vlv_force_pll_on - forcibly enable just the PLL
7102 * @dev_priv: i915 private structure
7103 * @pipe: pipe PLL to enable
7104 * @dpll: PLL configuration
7106 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7107 * in cases where we need the PLL enabled even when @pipe is not going to
7110 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7111 const struct dpll *dpll)
7113 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7114 struct intel_crtc_state *pipe_config;
7116 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7120 pipe_config->base.crtc = &crtc->base;
7121 pipe_config->pixel_multiplier = 1;
7122 pipe_config->dpll = *dpll;
7124 if (IS_CHERRYVIEW(dev_priv)) {
7125 chv_compute_dpll(crtc, pipe_config);
7126 chv_prepare_pll(crtc, pipe_config);
7127 chv_enable_pll(crtc, pipe_config);
7129 vlv_compute_dpll(crtc, pipe_config);
7130 vlv_prepare_pll(crtc, pipe_config);
7131 vlv_enable_pll(crtc, pipe_config);
7140 * vlv_force_pll_off - forcibly disable just the PLL
7141 * @dev_priv: i915 private structure
7142 * @pipe: pipe PLL to disable
7144 * Disable the PLL for @pipe. To be used in cases where we need
7145 * the PLL enabled even when @pipe is not going to be enabled.
7147 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7149 if (IS_CHERRYVIEW(dev_priv))
7150 chv_disable_pll(dev_priv, pipe);
7152 vlv_disable_pll(dev_priv, pipe);
7155 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7156 struct intel_crtc_state *crtc_state,
7157 struct dpll *reduced_clock)
7159 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7161 struct dpll *clock = &crtc_state->dpll;
7163 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7165 dpll = DPLL_VGA_MODE_DIS;
7167 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7168 dpll |= DPLLB_MODE_LVDS;
7170 dpll |= DPLLB_MODE_DAC_SERIAL;
7172 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7173 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7174 dpll |= (crtc_state->pixel_multiplier - 1)
7175 << SDVO_MULTIPLIER_SHIFT_HIRES;
7178 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7179 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7180 dpll |= DPLL_SDVO_HIGH_SPEED;
7182 if (intel_crtc_has_dp_encoder(crtc_state))
7183 dpll |= DPLL_SDVO_HIGH_SPEED;
7185 /* compute bitmask from p1 value */
7186 if (IS_PINEVIEW(dev_priv))
7187 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7189 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7190 if (IS_G4X(dev_priv) && reduced_clock)
7191 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7193 switch (clock->p2) {
7195 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7198 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7201 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7204 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7207 if (INTEL_GEN(dev_priv) >= 4)
7208 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7210 if (crtc_state->sdvo_tv_clock)
7211 dpll |= PLL_REF_INPUT_TVCLKINBC;
7212 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7213 intel_panel_use_ssc(dev_priv))
7214 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7216 dpll |= PLL_REF_INPUT_DREFCLK;
7218 dpll |= DPLL_VCO_ENABLE;
7219 crtc_state->dpll_hw_state.dpll = dpll;
7221 if (INTEL_GEN(dev_priv) >= 4) {
7222 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7223 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7224 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7228 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7229 struct intel_crtc_state *crtc_state,
7230 struct dpll *reduced_clock)
7232 struct drm_device *dev = crtc->base.dev;
7233 struct drm_i915_private *dev_priv = to_i915(dev);
7235 struct dpll *clock = &crtc_state->dpll;
7237 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7239 dpll = DPLL_VGA_MODE_DIS;
7241 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7242 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7245 dpll |= PLL_P1_DIVIDE_BY_TWO;
7247 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7249 dpll |= PLL_P2_DIVIDE_BY_4;
7252 if (!IS_I830(dev_priv) &&
7253 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7254 dpll |= DPLL_DVO_2X_MODE;
7256 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7257 intel_panel_use_ssc(dev_priv))
7258 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7260 dpll |= PLL_REF_INPUT_DREFCLK;
7262 dpll |= DPLL_VCO_ENABLE;
7263 crtc_state->dpll_hw_state.dpll = dpll;
7266 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7268 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7269 enum pipe pipe = intel_crtc->pipe;
7270 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7271 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7272 uint32_t crtc_vtotal, crtc_vblank_end;
7275 /* We need to be careful not to changed the adjusted mode, for otherwise
7276 * the hw state checker will get angry at the mismatch. */
7277 crtc_vtotal = adjusted_mode->crtc_vtotal;
7278 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7280 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7281 /* the chip adds 2 halflines automatically */
7283 crtc_vblank_end -= 1;
7285 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7286 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7288 vsyncshift = adjusted_mode->crtc_hsync_start -
7289 adjusted_mode->crtc_htotal / 2;
7291 vsyncshift += adjusted_mode->crtc_htotal;
7294 if (INTEL_GEN(dev_priv) > 3)
7295 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7297 I915_WRITE(HTOTAL(cpu_transcoder),
7298 (adjusted_mode->crtc_hdisplay - 1) |
7299 ((adjusted_mode->crtc_htotal - 1) << 16));
7300 I915_WRITE(HBLANK(cpu_transcoder),
7301 (adjusted_mode->crtc_hblank_start - 1) |
7302 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7303 I915_WRITE(HSYNC(cpu_transcoder),
7304 (adjusted_mode->crtc_hsync_start - 1) |
7305 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7307 I915_WRITE(VTOTAL(cpu_transcoder),
7308 (adjusted_mode->crtc_vdisplay - 1) |
7309 ((crtc_vtotal - 1) << 16));
7310 I915_WRITE(VBLANK(cpu_transcoder),
7311 (adjusted_mode->crtc_vblank_start - 1) |
7312 ((crtc_vblank_end - 1) << 16));
7313 I915_WRITE(VSYNC(cpu_transcoder),
7314 (adjusted_mode->crtc_vsync_start - 1) |
7315 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7317 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7318 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7319 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7321 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7322 (pipe == PIPE_B || pipe == PIPE_C))
7323 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7327 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7329 struct drm_device *dev = intel_crtc->base.dev;
7330 struct drm_i915_private *dev_priv = to_i915(dev);
7331 enum pipe pipe = intel_crtc->pipe;
7333 /* pipesrc controls the size that is scaled from, which should
7334 * always be the user's requested size.
7336 I915_WRITE(PIPESRC(pipe),
7337 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7338 (intel_crtc->config->pipe_src_h - 1));
7341 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7342 struct intel_crtc_state *pipe_config)
7344 struct drm_device *dev = crtc->base.dev;
7345 struct drm_i915_private *dev_priv = to_i915(dev);
7346 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7349 tmp = I915_READ(HTOTAL(cpu_transcoder));
7350 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7351 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7352 tmp = I915_READ(HBLANK(cpu_transcoder));
7353 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7354 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7355 tmp = I915_READ(HSYNC(cpu_transcoder));
7356 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7357 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7359 tmp = I915_READ(VTOTAL(cpu_transcoder));
7360 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7361 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7362 tmp = I915_READ(VBLANK(cpu_transcoder));
7363 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7364 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7365 tmp = I915_READ(VSYNC(cpu_transcoder));
7366 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7367 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7369 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7370 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7371 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7372 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7376 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7377 struct intel_crtc_state *pipe_config)
7379 struct drm_device *dev = crtc->base.dev;
7380 struct drm_i915_private *dev_priv = to_i915(dev);
7383 tmp = I915_READ(PIPESRC(crtc->pipe));
7384 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7385 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7387 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7388 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7391 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7392 struct intel_crtc_state *pipe_config)
7394 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7395 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7396 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7397 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7399 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7400 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7401 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7402 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7404 mode->flags = pipe_config->base.adjusted_mode.flags;
7405 mode->type = DRM_MODE_TYPE_DRIVER;
7407 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7409 mode->hsync = drm_mode_hsync(mode);
7410 mode->vrefresh = drm_mode_vrefresh(mode);
7411 drm_mode_set_name(mode);
7414 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7416 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7421 /* we keep both pipes enabled on 830 */
7422 if (IS_I830(dev_priv))
7423 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7425 if (intel_crtc->config->double_wide)
7426 pipeconf |= PIPECONF_DOUBLE_WIDE;
7428 /* only g4x and later have fancy bpc/dither controls */
7429 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7430 IS_CHERRYVIEW(dev_priv)) {
7431 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7432 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7433 pipeconf |= PIPECONF_DITHER_EN |
7434 PIPECONF_DITHER_TYPE_SP;
7436 switch (intel_crtc->config->pipe_bpp) {
7438 pipeconf |= PIPECONF_6BPC;
7441 pipeconf |= PIPECONF_8BPC;
7444 pipeconf |= PIPECONF_10BPC;
7447 /* Case prevented by intel_choose_pipe_bpp_dither. */
7452 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7453 if (INTEL_GEN(dev_priv) < 4 ||
7454 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7455 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7457 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7459 pipeconf |= PIPECONF_PROGRESSIVE;
7461 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7462 intel_crtc->config->limited_color_range)
7463 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7465 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7466 POSTING_READ(PIPECONF(intel_crtc->pipe));
7469 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7470 struct intel_crtc_state *crtc_state)
7472 struct drm_device *dev = crtc->base.dev;
7473 struct drm_i915_private *dev_priv = to_i915(dev);
7474 const struct intel_limit *limit;
7477 memset(&crtc_state->dpll_hw_state, 0,
7478 sizeof(crtc_state->dpll_hw_state));
7480 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7481 if (intel_panel_use_ssc(dev_priv)) {
7482 refclk = dev_priv->vbt.lvds_ssc_freq;
7483 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7486 limit = &intel_limits_i8xx_lvds;
7487 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7488 limit = &intel_limits_i8xx_dvo;
7490 limit = &intel_limits_i8xx_dac;
7493 if (!crtc_state->clock_set &&
7494 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7495 refclk, NULL, &crtc_state->dpll)) {
7496 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7500 i8xx_compute_dpll(crtc, crtc_state, NULL);
7505 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7506 struct intel_crtc_state *crtc_state)
7508 struct drm_device *dev = crtc->base.dev;
7509 struct drm_i915_private *dev_priv = to_i915(dev);
7510 const struct intel_limit *limit;
7513 memset(&crtc_state->dpll_hw_state, 0,
7514 sizeof(crtc_state->dpll_hw_state));
7516 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7517 if (intel_panel_use_ssc(dev_priv)) {
7518 refclk = dev_priv->vbt.lvds_ssc_freq;
7519 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7522 if (intel_is_dual_link_lvds(dev))
7523 limit = &intel_limits_g4x_dual_channel_lvds;
7525 limit = &intel_limits_g4x_single_channel_lvds;
7526 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7527 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7528 limit = &intel_limits_g4x_hdmi;
7529 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7530 limit = &intel_limits_g4x_sdvo;
7532 /* The option is for other outputs */
7533 limit = &intel_limits_i9xx_sdvo;
7536 if (!crtc_state->clock_set &&
7537 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7538 refclk, NULL, &crtc_state->dpll)) {
7539 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7543 i9xx_compute_dpll(crtc, crtc_state, NULL);
7548 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7549 struct intel_crtc_state *crtc_state)
7551 struct drm_device *dev = crtc->base.dev;
7552 struct drm_i915_private *dev_priv = to_i915(dev);
7553 const struct intel_limit *limit;
7556 memset(&crtc_state->dpll_hw_state, 0,
7557 sizeof(crtc_state->dpll_hw_state));
7559 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7560 if (intel_panel_use_ssc(dev_priv)) {
7561 refclk = dev_priv->vbt.lvds_ssc_freq;
7562 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7565 limit = &intel_limits_pineview_lvds;
7567 limit = &intel_limits_pineview_sdvo;
7570 if (!crtc_state->clock_set &&
7571 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7572 refclk, NULL, &crtc_state->dpll)) {
7573 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7577 i9xx_compute_dpll(crtc, crtc_state, NULL);
7582 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7583 struct intel_crtc_state *crtc_state)
7585 struct drm_device *dev = crtc->base.dev;
7586 struct drm_i915_private *dev_priv = to_i915(dev);
7587 const struct intel_limit *limit;
7590 memset(&crtc_state->dpll_hw_state, 0,
7591 sizeof(crtc_state->dpll_hw_state));
7593 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7594 if (intel_panel_use_ssc(dev_priv)) {
7595 refclk = dev_priv->vbt.lvds_ssc_freq;
7596 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7599 limit = &intel_limits_i9xx_lvds;
7601 limit = &intel_limits_i9xx_sdvo;
7604 if (!crtc_state->clock_set &&
7605 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7606 refclk, NULL, &crtc_state->dpll)) {
7607 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7611 i9xx_compute_dpll(crtc, crtc_state, NULL);
7616 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7617 struct intel_crtc_state *crtc_state)
7619 int refclk = 100000;
7620 const struct intel_limit *limit = &intel_limits_chv;
7622 memset(&crtc_state->dpll_hw_state, 0,
7623 sizeof(crtc_state->dpll_hw_state));
7625 if (!crtc_state->clock_set &&
7626 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7627 refclk, NULL, &crtc_state->dpll)) {
7628 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7632 chv_compute_dpll(crtc, crtc_state);
7637 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7638 struct intel_crtc_state *crtc_state)
7640 int refclk = 100000;
7641 const struct intel_limit *limit = &intel_limits_vlv;
7643 memset(&crtc_state->dpll_hw_state, 0,
7644 sizeof(crtc_state->dpll_hw_state));
7646 if (!crtc_state->clock_set &&
7647 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7648 refclk, NULL, &crtc_state->dpll)) {
7649 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7653 vlv_compute_dpll(crtc, crtc_state);
7658 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7659 struct intel_crtc_state *pipe_config)
7661 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7664 if (INTEL_GEN(dev_priv) <= 3 &&
7665 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7668 tmp = I915_READ(PFIT_CONTROL);
7669 if (!(tmp & PFIT_ENABLE))
7672 /* Check whether the pfit is attached to our pipe. */
7673 if (INTEL_GEN(dev_priv) < 4) {
7674 if (crtc->pipe != PIPE_B)
7677 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7681 pipe_config->gmch_pfit.control = tmp;
7682 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7685 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7686 struct intel_crtc_state *pipe_config)
7688 struct drm_device *dev = crtc->base.dev;
7689 struct drm_i915_private *dev_priv = to_i915(dev);
7690 int pipe = pipe_config->cpu_transcoder;
7693 int refclk = 100000;
7695 /* In case of DSI, DPLL will not be used */
7696 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7699 mutex_lock(&dev_priv->sb_lock);
7700 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7701 mutex_unlock(&dev_priv->sb_lock);
7703 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7704 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7705 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7706 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7707 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7709 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7713 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7714 struct intel_initial_plane_config *plane_config)
7716 struct drm_device *dev = crtc->base.dev;
7717 struct drm_i915_private *dev_priv = to_i915(dev);
7718 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7719 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7721 u32 val, base, offset;
7722 int fourcc, pixel_format;
7723 unsigned int aligned_height;
7724 struct drm_framebuffer *fb;
7725 struct intel_framebuffer *intel_fb;
7727 if (!plane->get_hw_state(plane, &pipe))
7730 WARN_ON(pipe != crtc->pipe);
7732 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7734 DRM_DEBUG_KMS("failed to alloc fb\n");
7738 fb = &intel_fb->base;
7742 val = I915_READ(DSPCNTR(i9xx_plane));
7744 if (INTEL_GEN(dev_priv) >= 4) {
7745 if (val & DISPPLANE_TILED) {
7746 plane_config->tiling = I915_TILING_X;
7747 fb->modifier = I915_FORMAT_MOD_X_TILED;
7751 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7752 fourcc = i9xx_format_to_fourcc(pixel_format);
7753 fb->format = drm_format_info(fourcc);
7755 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7756 offset = I915_READ(DSPOFFSET(i9xx_plane));
7757 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7758 } else if (INTEL_GEN(dev_priv) >= 4) {
7759 if (plane_config->tiling)
7760 offset = I915_READ(DSPTILEOFF(i9xx_plane));
7762 offset = I915_READ(DSPLINOFF(i9xx_plane));
7763 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7765 base = I915_READ(DSPADDR(i9xx_plane));
7767 plane_config->base = base;
7769 val = I915_READ(PIPESRC(pipe));
7770 fb->width = ((val >> 16) & 0xfff) + 1;
7771 fb->height = ((val >> 0) & 0xfff) + 1;
7773 val = I915_READ(DSPSTRIDE(i9xx_plane));
7774 fb->pitches[0] = val & 0xffffffc0;
7776 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7778 plane_config->size = fb->pitches[0] * aligned_height;
7780 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7781 crtc->base.name, plane->base.name, fb->width, fb->height,
7782 fb->format->cpp[0] * 8, base, fb->pitches[0],
7783 plane_config->size);
7785 plane_config->fb = intel_fb;
7788 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7789 struct intel_crtc_state *pipe_config)
7791 struct drm_device *dev = crtc->base.dev;
7792 struct drm_i915_private *dev_priv = to_i915(dev);
7793 int pipe = pipe_config->cpu_transcoder;
7794 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7796 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7797 int refclk = 100000;
7799 /* In case of DSI, DPLL will not be used */
7800 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7803 mutex_lock(&dev_priv->sb_lock);
7804 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7805 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7806 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7807 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7808 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7809 mutex_unlock(&dev_priv->sb_lock);
7811 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7812 clock.m2 = (pll_dw0 & 0xff) << 22;
7813 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7814 clock.m2 |= pll_dw2 & 0x3fffff;
7815 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7816 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7817 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7819 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7822 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7823 struct intel_crtc_state *pipe_config)
7825 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7826 enum intel_display_power_domain power_domain;
7830 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7831 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7834 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7835 pipe_config->shared_dpll = NULL;
7839 tmp = I915_READ(PIPECONF(crtc->pipe));
7840 if (!(tmp & PIPECONF_ENABLE))
7843 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7844 IS_CHERRYVIEW(dev_priv)) {
7845 switch (tmp & PIPECONF_BPC_MASK) {
7847 pipe_config->pipe_bpp = 18;
7850 pipe_config->pipe_bpp = 24;
7852 case PIPECONF_10BPC:
7853 pipe_config->pipe_bpp = 30;
7860 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7861 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7862 pipe_config->limited_color_range = true;
7864 if (INTEL_GEN(dev_priv) < 4)
7865 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7867 intel_get_pipe_timings(crtc, pipe_config);
7868 intel_get_pipe_src_size(crtc, pipe_config);
7870 i9xx_get_pfit_config(crtc, pipe_config);
7872 if (INTEL_GEN(dev_priv) >= 4) {
7873 /* No way to read it out on pipes B and C */
7874 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7875 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7877 tmp = I915_READ(DPLL_MD(crtc->pipe));
7878 pipe_config->pixel_multiplier =
7879 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7880 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7881 pipe_config->dpll_hw_state.dpll_md = tmp;
7882 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7883 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7884 tmp = I915_READ(DPLL(crtc->pipe));
7885 pipe_config->pixel_multiplier =
7886 ((tmp & SDVO_MULTIPLIER_MASK)
7887 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7889 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7890 * port and will be fixed up in the encoder->get_config
7892 pipe_config->pixel_multiplier = 1;
7894 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7895 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7897 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7898 * on 830. Filter it out here so that we don't
7899 * report errors due to that.
7901 if (IS_I830(dev_priv))
7902 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7904 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7905 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7907 /* Mask out read-only status bits. */
7908 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7909 DPLL_PORTC_READY_MASK |
7910 DPLL_PORTB_READY_MASK);
7913 if (IS_CHERRYVIEW(dev_priv))
7914 chv_crtc_clock_get(crtc, pipe_config);
7915 else if (IS_VALLEYVIEW(dev_priv))
7916 vlv_crtc_clock_get(crtc, pipe_config);
7918 i9xx_crtc_clock_get(crtc, pipe_config);
7921 * Normally the dotclock is filled in by the encoder .get_config()
7922 * but in case the pipe is enabled w/o any ports we need a sane
7925 pipe_config->base.adjusted_mode.crtc_clock =
7926 pipe_config->port_clock / pipe_config->pixel_multiplier;
7931 intel_display_power_put(dev_priv, power_domain);
7936 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7938 struct intel_encoder *encoder;
7941 bool has_lvds = false;
7942 bool has_cpu_edp = false;
7943 bool has_panel = false;
7944 bool has_ck505 = false;
7945 bool can_ssc = false;
7946 bool using_ssc_source = false;
7948 /* We need to take the global config into account */
7949 for_each_intel_encoder(&dev_priv->drm, encoder) {
7950 switch (encoder->type) {
7951 case INTEL_OUTPUT_LVDS:
7955 case INTEL_OUTPUT_EDP:
7957 if (encoder->port == PORT_A)
7965 if (HAS_PCH_IBX(dev_priv)) {
7966 has_ck505 = dev_priv->vbt.display_clock_mode;
7967 can_ssc = has_ck505;
7973 /* Check if any DPLLs are using the SSC source */
7974 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7975 u32 temp = I915_READ(PCH_DPLL(i));
7977 if (!(temp & DPLL_VCO_ENABLE))
7980 if ((temp & PLL_REF_INPUT_MASK) ==
7981 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7982 using_ssc_source = true;
7987 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7988 has_panel, has_lvds, has_ck505, using_ssc_source);
7990 /* Ironlake: try to setup display ref clock before DPLL
7991 * enabling. This is only under driver's control after
7992 * PCH B stepping, previous chipset stepping should be
7993 * ignoring this setting.
7995 val = I915_READ(PCH_DREF_CONTROL);
7997 /* As we must carefully and slowly disable/enable each source in turn,
7998 * compute the final state we want first and check if we need to
7999 * make any changes at all.
8002 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8004 final |= DREF_NONSPREAD_CK505_ENABLE;
8006 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8008 final &= ~DREF_SSC_SOURCE_MASK;
8009 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8010 final &= ~DREF_SSC1_ENABLE;
8013 final |= DREF_SSC_SOURCE_ENABLE;
8015 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8016 final |= DREF_SSC1_ENABLE;
8019 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8020 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8022 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8024 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8025 } else if (using_ssc_source) {
8026 final |= DREF_SSC_SOURCE_ENABLE;
8027 final |= DREF_SSC1_ENABLE;
8033 /* Always enable nonspread source */
8034 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8037 val |= DREF_NONSPREAD_CK505_ENABLE;
8039 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8042 val &= ~DREF_SSC_SOURCE_MASK;
8043 val |= DREF_SSC_SOURCE_ENABLE;
8045 /* SSC must be turned on before enabling the CPU output */
8046 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8047 DRM_DEBUG_KMS("Using SSC on panel\n");
8048 val |= DREF_SSC1_ENABLE;
8050 val &= ~DREF_SSC1_ENABLE;
8052 /* Get SSC going before enabling the outputs */
8053 I915_WRITE(PCH_DREF_CONTROL, val);
8054 POSTING_READ(PCH_DREF_CONTROL);
8057 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8059 /* Enable CPU source on CPU attached eDP */
8061 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8062 DRM_DEBUG_KMS("Using SSC on eDP\n");
8063 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8065 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8067 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8069 I915_WRITE(PCH_DREF_CONTROL, val);
8070 POSTING_READ(PCH_DREF_CONTROL);
8073 DRM_DEBUG_KMS("Disabling CPU source output\n");
8075 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8077 /* Turn off CPU output */
8078 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8080 I915_WRITE(PCH_DREF_CONTROL, val);
8081 POSTING_READ(PCH_DREF_CONTROL);
8084 if (!using_ssc_source) {
8085 DRM_DEBUG_KMS("Disabling SSC source\n");
8087 /* Turn off the SSC source */
8088 val &= ~DREF_SSC_SOURCE_MASK;
8089 val |= DREF_SSC_SOURCE_DISABLE;
8092 val &= ~DREF_SSC1_ENABLE;
8094 I915_WRITE(PCH_DREF_CONTROL, val);
8095 POSTING_READ(PCH_DREF_CONTROL);
8100 BUG_ON(val != final);
8103 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8107 tmp = I915_READ(SOUTH_CHICKEN2);
8108 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8109 I915_WRITE(SOUTH_CHICKEN2, tmp);
8111 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8112 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8113 DRM_ERROR("FDI mPHY reset assert timeout\n");
8115 tmp = I915_READ(SOUTH_CHICKEN2);
8116 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8117 I915_WRITE(SOUTH_CHICKEN2, tmp);
8119 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8120 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8121 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8124 /* WaMPhyProgramming:hsw */
8125 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8129 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8130 tmp &= ~(0xFF << 24);
8131 tmp |= (0x12 << 24);
8132 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8134 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8136 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8138 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8140 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8142 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8143 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8144 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8146 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8147 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8148 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8150 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8153 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8155 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8158 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8160 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8163 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8165 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8168 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8170 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8171 tmp &= ~(0xFF << 16);
8172 tmp |= (0x1C << 16);
8173 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8175 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8176 tmp &= ~(0xFF << 16);
8177 tmp |= (0x1C << 16);
8178 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8180 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8182 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8184 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8186 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8188 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8189 tmp &= ~(0xF << 28);
8191 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8193 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8194 tmp &= ~(0xF << 28);
8196 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8199 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8200 * Programming" based on the parameters passed:
8201 * - Sequence to enable CLKOUT_DP
8202 * - Sequence to enable CLKOUT_DP without spread
8203 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8205 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8206 bool with_spread, bool with_fdi)
8210 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8212 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8213 with_fdi, "LP PCH doesn't have FDI\n"))
8216 mutex_lock(&dev_priv->sb_lock);
8218 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8219 tmp &= ~SBI_SSCCTL_DISABLE;
8220 tmp |= SBI_SSCCTL_PATHALT;
8221 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8226 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8227 tmp &= ~SBI_SSCCTL_PATHALT;
8228 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8231 lpt_reset_fdi_mphy(dev_priv);
8232 lpt_program_fdi_mphy(dev_priv);
8236 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8237 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8238 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8239 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8241 mutex_unlock(&dev_priv->sb_lock);
8244 /* Sequence to disable CLKOUT_DP */
8245 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8249 mutex_lock(&dev_priv->sb_lock);
8251 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8252 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8253 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8254 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8256 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8257 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8258 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8259 tmp |= SBI_SSCCTL_PATHALT;
8260 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8263 tmp |= SBI_SSCCTL_DISABLE;
8264 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8267 mutex_unlock(&dev_priv->sb_lock);
8270 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8272 static const uint16_t sscdivintphase[] = {
8273 [BEND_IDX( 50)] = 0x3B23,
8274 [BEND_IDX( 45)] = 0x3B23,
8275 [BEND_IDX( 40)] = 0x3C23,
8276 [BEND_IDX( 35)] = 0x3C23,
8277 [BEND_IDX( 30)] = 0x3D23,
8278 [BEND_IDX( 25)] = 0x3D23,
8279 [BEND_IDX( 20)] = 0x3E23,
8280 [BEND_IDX( 15)] = 0x3E23,
8281 [BEND_IDX( 10)] = 0x3F23,
8282 [BEND_IDX( 5)] = 0x3F23,
8283 [BEND_IDX( 0)] = 0x0025,
8284 [BEND_IDX( -5)] = 0x0025,
8285 [BEND_IDX(-10)] = 0x0125,
8286 [BEND_IDX(-15)] = 0x0125,
8287 [BEND_IDX(-20)] = 0x0225,
8288 [BEND_IDX(-25)] = 0x0225,
8289 [BEND_IDX(-30)] = 0x0325,
8290 [BEND_IDX(-35)] = 0x0325,
8291 [BEND_IDX(-40)] = 0x0425,
8292 [BEND_IDX(-45)] = 0x0425,
8293 [BEND_IDX(-50)] = 0x0525,
8298 * steps -50 to 50 inclusive, in steps of 5
8299 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8300 * change in clock period = -(steps / 10) * 5.787 ps
8302 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8305 int idx = BEND_IDX(steps);
8307 if (WARN_ON(steps % 5 != 0))
8310 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8313 mutex_lock(&dev_priv->sb_lock);
8315 if (steps % 10 != 0)
8319 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8321 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8323 tmp |= sscdivintphase[idx];
8324 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8326 mutex_unlock(&dev_priv->sb_lock);
8331 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8333 struct intel_encoder *encoder;
8334 bool has_vga = false;
8336 for_each_intel_encoder(&dev_priv->drm, encoder) {
8337 switch (encoder->type) {
8338 case INTEL_OUTPUT_ANALOG:
8347 lpt_bend_clkout_dp(dev_priv, 0);
8348 lpt_enable_clkout_dp(dev_priv, true, true);
8350 lpt_disable_clkout_dp(dev_priv);
8355 * Initialize reference clocks when the driver loads
8357 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8359 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8360 ironlake_init_pch_refclk(dev_priv);
8361 else if (HAS_PCH_LPT(dev_priv))
8362 lpt_init_pch_refclk(dev_priv);
8365 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8367 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8369 int pipe = intel_crtc->pipe;
8374 switch (intel_crtc->config->pipe_bpp) {
8376 val |= PIPECONF_6BPC;
8379 val |= PIPECONF_8BPC;
8382 val |= PIPECONF_10BPC;
8385 val |= PIPECONF_12BPC;
8388 /* Case prevented by intel_choose_pipe_bpp_dither. */
8392 if (intel_crtc->config->dither)
8393 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8395 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8396 val |= PIPECONF_INTERLACED_ILK;
8398 val |= PIPECONF_PROGRESSIVE;
8400 if (intel_crtc->config->limited_color_range)
8401 val |= PIPECONF_COLOR_RANGE_SELECT;
8403 I915_WRITE(PIPECONF(pipe), val);
8404 POSTING_READ(PIPECONF(pipe));
8407 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8409 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8411 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8414 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8415 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8417 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8418 val |= PIPECONF_INTERLACED_ILK;
8420 val |= PIPECONF_PROGRESSIVE;
8422 I915_WRITE(PIPECONF(cpu_transcoder), val);
8423 POSTING_READ(PIPECONF(cpu_transcoder));
8426 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8428 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8430 struct intel_crtc_state *config = intel_crtc->config;
8432 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8435 switch (intel_crtc->config->pipe_bpp) {
8437 val |= PIPEMISC_DITHER_6_BPC;
8440 val |= PIPEMISC_DITHER_8_BPC;
8443 val |= PIPEMISC_DITHER_10_BPC;
8446 val |= PIPEMISC_DITHER_12_BPC;
8449 /* Case prevented by pipe_config_set_bpp. */
8453 if (intel_crtc->config->dither)
8454 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8456 if (config->ycbcr420) {
8457 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8458 PIPEMISC_YUV420_ENABLE |
8459 PIPEMISC_YUV420_MODE_FULL_BLEND;
8462 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8466 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8469 * Account for spread spectrum to avoid
8470 * oversubscribing the link. Max center spread
8471 * is 2.5%; use 5% for safety's sake.
8473 u32 bps = target_clock * bpp * 21 / 20;
8474 return DIV_ROUND_UP(bps, link_bw * 8);
8477 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8479 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8482 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8483 struct intel_crtc_state *crtc_state,
8484 struct dpll *reduced_clock)
8486 struct drm_crtc *crtc = &intel_crtc->base;
8487 struct drm_device *dev = crtc->dev;
8488 struct drm_i915_private *dev_priv = to_i915(dev);
8492 /* Enable autotuning of the PLL clock (if permissible) */
8494 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8495 if ((intel_panel_use_ssc(dev_priv) &&
8496 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8497 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8499 } else if (crtc_state->sdvo_tv_clock)
8502 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8504 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8507 if (reduced_clock) {
8508 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8510 if (reduced_clock->m < factor * reduced_clock->n)
8518 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8519 dpll |= DPLLB_MODE_LVDS;
8521 dpll |= DPLLB_MODE_DAC_SERIAL;
8523 dpll |= (crtc_state->pixel_multiplier - 1)
8524 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8526 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8527 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8528 dpll |= DPLL_SDVO_HIGH_SPEED;
8530 if (intel_crtc_has_dp_encoder(crtc_state))
8531 dpll |= DPLL_SDVO_HIGH_SPEED;
8534 * The high speed IO clock is only really required for
8535 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8536 * possible to share the DPLL between CRT and HDMI. Enabling
8537 * the clock needlessly does no real harm, except use up a
8538 * bit of power potentially.
8540 * We'll limit this to IVB with 3 pipes, since it has only two
8541 * DPLLs and so DPLL sharing is the only way to get three pipes
8542 * driving PCH ports at the same time. On SNB we could do this,
8543 * and potentially avoid enabling the second DPLL, but it's not
8544 * clear if it''s a win or loss power wise. No point in doing
8545 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8547 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8548 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8549 dpll |= DPLL_SDVO_HIGH_SPEED;
8551 /* compute bitmask from p1 value */
8552 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8554 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8556 switch (crtc_state->dpll.p2) {
8558 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8561 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8564 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8567 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8571 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8572 intel_panel_use_ssc(dev_priv))
8573 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8575 dpll |= PLL_REF_INPUT_DREFCLK;
8577 dpll |= DPLL_VCO_ENABLE;
8579 crtc_state->dpll_hw_state.dpll = dpll;
8580 crtc_state->dpll_hw_state.fp0 = fp;
8581 crtc_state->dpll_hw_state.fp1 = fp2;
8584 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8585 struct intel_crtc_state *crtc_state)
8587 struct drm_device *dev = crtc->base.dev;
8588 struct drm_i915_private *dev_priv = to_i915(dev);
8589 const struct intel_limit *limit;
8590 int refclk = 120000;
8592 memset(&crtc_state->dpll_hw_state, 0,
8593 sizeof(crtc_state->dpll_hw_state));
8595 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8596 if (!crtc_state->has_pch_encoder)
8599 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8600 if (intel_panel_use_ssc(dev_priv)) {
8601 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8602 dev_priv->vbt.lvds_ssc_freq);
8603 refclk = dev_priv->vbt.lvds_ssc_freq;
8606 if (intel_is_dual_link_lvds(dev)) {
8607 if (refclk == 100000)
8608 limit = &intel_limits_ironlake_dual_lvds_100m;
8610 limit = &intel_limits_ironlake_dual_lvds;
8612 if (refclk == 100000)
8613 limit = &intel_limits_ironlake_single_lvds_100m;
8615 limit = &intel_limits_ironlake_single_lvds;
8618 limit = &intel_limits_ironlake_dac;
8621 if (!crtc_state->clock_set &&
8622 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8623 refclk, NULL, &crtc_state->dpll)) {
8624 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8628 ironlake_compute_dpll(crtc, crtc_state, NULL);
8630 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8631 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8632 pipe_name(crtc->pipe));
8639 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8640 struct intel_link_m_n *m_n)
8642 struct drm_device *dev = crtc->base.dev;
8643 struct drm_i915_private *dev_priv = to_i915(dev);
8644 enum pipe pipe = crtc->pipe;
8646 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8647 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8648 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8650 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8651 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8652 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8655 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8656 enum transcoder transcoder,
8657 struct intel_link_m_n *m_n,
8658 struct intel_link_m_n *m2_n2)
8660 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8661 enum pipe pipe = crtc->pipe;
8663 if (INTEL_GEN(dev_priv) >= 5) {
8664 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8665 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8666 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8668 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8669 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8670 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8671 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8672 * gen < 8) and if DRRS is supported (to make sure the
8673 * registers are not unnecessarily read).
8675 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8676 crtc->config->has_drrs) {
8677 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8678 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8679 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8681 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8682 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8683 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8686 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8687 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8688 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8690 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8691 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8692 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8696 void intel_dp_get_m_n(struct intel_crtc *crtc,
8697 struct intel_crtc_state *pipe_config)
8699 if (pipe_config->has_pch_encoder)
8700 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8702 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8703 &pipe_config->dp_m_n,
8704 &pipe_config->dp_m2_n2);
8707 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8708 struct intel_crtc_state *pipe_config)
8710 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8711 &pipe_config->fdi_m_n, NULL);
8714 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8715 struct intel_crtc_state *pipe_config)
8717 struct drm_device *dev = crtc->base.dev;
8718 struct drm_i915_private *dev_priv = to_i915(dev);
8719 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8720 uint32_t ps_ctrl = 0;
8724 /* find scaler attached to this pipe */
8725 for (i = 0; i < crtc->num_scalers; i++) {
8726 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8727 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8729 pipe_config->pch_pfit.enabled = true;
8730 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8731 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8736 scaler_state->scaler_id = id;
8738 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8740 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8745 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8746 struct intel_initial_plane_config *plane_config)
8748 struct drm_device *dev = crtc->base.dev;
8749 struct drm_i915_private *dev_priv = to_i915(dev);
8750 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8751 enum plane_id plane_id = plane->id;
8753 u32 val, base, offset, stride_mult, tiling, alpha;
8754 int fourcc, pixel_format;
8755 unsigned int aligned_height;
8756 struct drm_framebuffer *fb;
8757 struct intel_framebuffer *intel_fb;
8759 if (!plane->get_hw_state(plane, &pipe))
8762 WARN_ON(pipe != crtc->pipe);
8764 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8766 DRM_DEBUG_KMS("failed to alloc fb\n");
8770 fb = &intel_fb->base;
8774 val = I915_READ(PLANE_CTL(pipe, plane_id));
8776 if (INTEL_GEN(dev_priv) >= 11)
8777 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8779 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8781 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8782 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8783 alpha &= PLANE_COLOR_ALPHA_MASK;
8785 alpha = val & PLANE_CTL_ALPHA_MASK;
8788 fourcc = skl_format_to_fourcc(pixel_format,
8789 val & PLANE_CTL_ORDER_RGBX, alpha);
8790 fb->format = drm_format_info(fourcc);
8792 tiling = val & PLANE_CTL_TILED_MASK;
8794 case PLANE_CTL_TILED_LINEAR:
8795 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8797 case PLANE_CTL_TILED_X:
8798 plane_config->tiling = I915_TILING_X;
8799 fb->modifier = I915_FORMAT_MOD_X_TILED;
8801 case PLANE_CTL_TILED_Y:
8802 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8803 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8805 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8807 case PLANE_CTL_TILED_YF:
8808 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8809 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8811 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8814 MISSING_CASE(tiling);
8818 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8819 plane_config->base = base;
8821 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8823 val = I915_READ(PLANE_SIZE(pipe, plane_id));
8824 fb->height = ((val >> 16) & 0xfff) + 1;
8825 fb->width = ((val >> 0) & 0x1fff) + 1;
8827 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8828 stride_mult = intel_fb_stride_alignment(fb, 0);
8829 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8831 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8833 plane_config->size = fb->pitches[0] * aligned_height;
8835 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8836 crtc->base.name, plane->base.name, fb->width, fb->height,
8837 fb->format->cpp[0] * 8, base, fb->pitches[0],
8838 plane_config->size);
8840 plane_config->fb = intel_fb;
8847 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8848 struct intel_crtc_state *pipe_config)
8850 struct drm_device *dev = crtc->base.dev;
8851 struct drm_i915_private *dev_priv = to_i915(dev);
8854 tmp = I915_READ(PF_CTL(crtc->pipe));
8856 if (tmp & PF_ENABLE) {
8857 pipe_config->pch_pfit.enabled = true;
8858 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8859 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8861 /* We currently do not free assignements of panel fitters on
8862 * ivb/hsw (since we don't use the higher upscaling modes which
8863 * differentiates them) so just WARN about this case for now. */
8864 if (IS_GEN7(dev_priv)) {
8865 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8866 PF_PIPE_SEL_IVB(crtc->pipe));
8871 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8872 struct intel_crtc_state *pipe_config)
8874 struct drm_device *dev = crtc->base.dev;
8875 struct drm_i915_private *dev_priv = to_i915(dev);
8876 enum intel_display_power_domain power_domain;
8880 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8881 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8884 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8885 pipe_config->shared_dpll = NULL;
8888 tmp = I915_READ(PIPECONF(crtc->pipe));
8889 if (!(tmp & PIPECONF_ENABLE))
8892 switch (tmp & PIPECONF_BPC_MASK) {
8894 pipe_config->pipe_bpp = 18;
8897 pipe_config->pipe_bpp = 24;
8899 case PIPECONF_10BPC:
8900 pipe_config->pipe_bpp = 30;
8902 case PIPECONF_12BPC:
8903 pipe_config->pipe_bpp = 36;
8909 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8910 pipe_config->limited_color_range = true;
8912 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8913 struct intel_shared_dpll *pll;
8914 enum intel_dpll_id pll_id;
8916 pipe_config->has_pch_encoder = true;
8918 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8919 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8920 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8922 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8924 if (HAS_PCH_IBX(dev_priv)) {
8926 * The pipe->pch transcoder and pch transcoder->pll
8929 pll_id = (enum intel_dpll_id) crtc->pipe;
8931 tmp = I915_READ(PCH_DPLL_SEL);
8932 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8933 pll_id = DPLL_ID_PCH_PLL_B;
8935 pll_id= DPLL_ID_PCH_PLL_A;
8938 pipe_config->shared_dpll =
8939 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8940 pll = pipe_config->shared_dpll;
8942 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
8943 &pipe_config->dpll_hw_state));
8945 tmp = pipe_config->dpll_hw_state.dpll;
8946 pipe_config->pixel_multiplier =
8947 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8948 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8950 ironlake_pch_clock_get(crtc, pipe_config);
8952 pipe_config->pixel_multiplier = 1;
8955 intel_get_pipe_timings(crtc, pipe_config);
8956 intel_get_pipe_src_size(crtc, pipe_config);
8958 ironlake_get_pfit_config(crtc, pipe_config);
8963 intel_display_power_put(dev_priv, power_domain);
8968 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8970 struct drm_device *dev = &dev_priv->drm;
8971 struct intel_crtc *crtc;
8973 for_each_intel_crtc(dev, crtc)
8974 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8975 pipe_name(crtc->pipe));
8977 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8978 "Display power well on\n");
8979 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8980 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8981 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8982 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8983 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8984 "CPU PWM1 enabled\n");
8985 if (IS_HASWELL(dev_priv))
8986 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8987 "CPU PWM2 enabled\n");
8988 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8989 "PCH PWM1 enabled\n");
8990 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8991 "Utility pin enabled\n");
8992 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8995 * In theory we can still leave IRQs enabled, as long as only the HPD
8996 * interrupts remain enabled. We used to check for that, but since it's
8997 * gen-specific and since we only disable LCPLL after we fully disable
8998 * the interrupts, the check below should be enough.
9000 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9003 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9005 if (IS_HASWELL(dev_priv))
9006 return I915_READ(D_COMP_HSW);
9008 return I915_READ(D_COMP_BDW);
9011 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9013 if (IS_HASWELL(dev_priv)) {
9014 mutex_lock(&dev_priv->pcu_lock);
9015 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9017 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9018 mutex_unlock(&dev_priv->pcu_lock);
9020 I915_WRITE(D_COMP_BDW, val);
9021 POSTING_READ(D_COMP_BDW);
9026 * This function implements pieces of two sequences from BSpec:
9027 * - Sequence for display software to disable LCPLL
9028 * - Sequence for display software to allow package C8+
9029 * The steps implemented here are just the steps that actually touch the LCPLL
9030 * register. Callers should take care of disabling all the display engine
9031 * functions, doing the mode unset, fixing interrupts, etc.
9033 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9034 bool switch_to_fclk, bool allow_power_down)
9038 assert_can_disable_lcpll(dev_priv);
9040 val = I915_READ(LCPLL_CTL);
9042 if (switch_to_fclk) {
9043 val |= LCPLL_CD_SOURCE_FCLK;
9044 I915_WRITE(LCPLL_CTL, val);
9046 if (wait_for_us(I915_READ(LCPLL_CTL) &
9047 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9048 DRM_ERROR("Switching to FCLK failed\n");
9050 val = I915_READ(LCPLL_CTL);
9053 val |= LCPLL_PLL_DISABLE;
9054 I915_WRITE(LCPLL_CTL, val);
9055 POSTING_READ(LCPLL_CTL);
9057 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9058 DRM_ERROR("LCPLL still locked\n");
9060 val = hsw_read_dcomp(dev_priv);
9061 val |= D_COMP_COMP_DISABLE;
9062 hsw_write_dcomp(dev_priv, val);
9065 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9067 DRM_ERROR("D_COMP RCOMP still in progress\n");
9069 if (allow_power_down) {
9070 val = I915_READ(LCPLL_CTL);
9071 val |= LCPLL_POWER_DOWN_ALLOW;
9072 I915_WRITE(LCPLL_CTL, val);
9073 POSTING_READ(LCPLL_CTL);
9078 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9081 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9085 val = I915_READ(LCPLL_CTL);
9087 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9088 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9092 * Make sure we're not on PC8 state before disabling PC8, otherwise
9093 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9095 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9097 if (val & LCPLL_POWER_DOWN_ALLOW) {
9098 val &= ~LCPLL_POWER_DOWN_ALLOW;
9099 I915_WRITE(LCPLL_CTL, val);
9100 POSTING_READ(LCPLL_CTL);
9103 val = hsw_read_dcomp(dev_priv);
9104 val |= D_COMP_COMP_FORCE;
9105 val &= ~D_COMP_COMP_DISABLE;
9106 hsw_write_dcomp(dev_priv, val);
9108 val = I915_READ(LCPLL_CTL);
9109 val &= ~LCPLL_PLL_DISABLE;
9110 I915_WRITE(LCPLL_CTL, val);
9112 if (intel_wait_for_register(dev_priv,
9113 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9115 DRM_ERROR("LCPLL not locked yet\n");
9117 if (val & LCPLL_CD_SOURCE_FCLK) {
9118 val = I915_READ(LCPLL_CTL);
9119 val &= ~LCPLL_CD_SOURCE_FCLK;
9120 I915_WRITE(LCPLL_CTL, val);
9122 if (wait_for_us((I915_READ(LCPLL_CTL) &
9123 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9124 DRM_ERROR("Switching back to LCPLL failed\n");
9127 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9129 intel_update_cdclk(dev_priv);
9130 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9134 * Package states C8 and deeper are really deep PC states that can only be
9135 * reached when all the devices on the system allow it, so even if the graphics
9136 * device allows PC8+, it doesn't mean the system will actually get to these
9137 * states. Our driver only allows PC8+ when going into runtime PM.
9139 * The requirements for PC8+ are that all the outputs are disabled, the power
9140 * well is disabled and most interrupts are disabled, and these are also
9141 * requirements for runtime PM. When these conditions are met, we manually do
9142 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9143 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9146 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9147 * the state of some registers, so when we come back from PC8+ we need to
9148 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9149 * need to take care of the registers kept by RC6. Notice that this happens even
9150 * if we don't put the device in PCI D3 state (which is what currently happens
9151 * because of the runtime PM support).
9153 * For more, read "Display Sequences for Package C8" on the hardware
9156 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9160 DRM_DEBUG_KMS("Enabling package C8+\n");
9162 if (HAS_PCH_LPT_LP(dev_priv)) {
9163 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9164 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9165 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9168 lpt_disable_clkout_dp(dev_priv);
9169 hsw_disable_lcpll(dev_priv, true, true);
9172 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9176 DRM_DEBUG_KMS("Disabling package C8+\n");
9178 hsw_restore_lcpll(dev_priv);
9179 lpt_init_pch_refclk(dev_priv);
9181 if (HAS_PCH_LPT_LP(dev_priv)) {
9182 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9183 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9184 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9188 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9189 struct intel_crtc_state *crtc_state)
9191 struct intel_atomic_state *state =
9192 to_intel_atomic_state(crtc_state->base.state);
9194 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9195 struct intel_encoder *encoder =
9196 intel_get_crtc_new_encoder(state, crtc_state);
9198 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9199 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9200 pipe_name(crtc->pipe));
9208 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9210 struct intel_crtc_state *pipe_config)
9212 enum intel_dpll_id id;
9215 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9216 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9218 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9221 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9224 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9226 struct intel_crtc_state *pipe_config)
9228 enum intel_dpll_id id;
9231 /* TODO: TBT pll not implemented. */
9235 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9236 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9237 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9239 if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
9243 id = DPLL_ID_ICL_MGPLL1;
9246 id = DPLL_ID_ICL_MGPLL2;
9249 id = DPLL_ID_ICL_MGPLL3;
9252 id = DPLL_ID_ICL_MGPLL4;
9259 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9262 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9264 struct intel_crtc_state *pipe_config)
9266 enum intel_dpll_id id;
9270 id = DPLL_ID_SKL_DPLL0;
9273 id = DPLL_ID_SKL_DPLL1;
9276 id = DPLL_ID_SKL_DPLL2;
9279 DRM_ERROR("Incorrect port type\n");
9283 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9286 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9288 struct intel_crtc_state *pipe_config)
9290 enum intel_dpll_id id;
9293 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9294 id = temp >> (port * 3 + 1);
9296 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9299 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9302 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9304 struct intel_crtc_state *pipe_config)
9306 enum intel_dpll_id id;
9307 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9309 switch (ddi_pll_sel) {
9310 case PORT_CLK_SEL_WRPLL1:
9311 id = DPLL_ID_WRPLL1;
9313 case PORT_CLK_SEL_WRPLL2:
9314 id = DPLL_ID_WRPLL2;
9316 case PORT_CLK_SEL_SPLL:
9319 case PORT_CLK_SEL_LCPLL_810:
9320 id = DPLL_ID_LCPLL_810;
9322 case PORT_CLK_SEL_LCPLL_1350:
9323 id = DPLL_ID_LCPLL_1350;
9325 case PORT_CLK_SEL_LCPLL_2700:
9326 id = DPLL_ID_LCPLL_2700;
9329 MISSING_CASE(ddi_pll_sel);
9331 case PORT_CLK_SEL_NONE:
9335 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9338 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9339 struct intel_crtc_state *pipe_config,
9340 u64 *power_domain_mask)
9342 struct drm_device *dev = crtc->base.dev;
9343 struct drm_i915_private *dev_priv = to_i915(dev);
9344 enum intel_display_power_domain power_domain;
9348 * The pipe->transcoder mapping is fixed with the exception of the eDP
9349 * transcoder handled below.
9351 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9354 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9355 * consistency and less surprising code; it's in always on power).
9357 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9358 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9359 enum pipe trans_edp_pipe;
9360 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9362 WARN(1, "unknown pipe linked to edp transcoder\n");
9364 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9365 case TRANS_DDI_EDP_INPUT_A_ON:
9366 trans_edp_pipe = PIPE_A;
9368 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9369 trans_edp_pipe = PIPE_B;
9371 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9372 trans_edp_pipe = PIPE_C;
9376 if (trans_edp_pipe == crtc->pipe)
9377 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9380 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9381 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9383 *power_domain_mask |= BIT_ULL(power_domain);
9385 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9387 return tmp & PIPECONF_ENABLE;
9390 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9391 struct intel_crtc_state *pipe_config,
9392 u64 *power_domain_mask)
9394 struct drm_device *dev = crtc->base.dev;
9395 struct drm_i915_private *dev_priv = to_i915(dev);
9396 enum intel_display_power_domain power_domain;
9398 enum transcoder cpu_transcoder;
9401 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9403 cpu_transcoder = TRANSCODER_DSI_A;
9405 cpu_transcoder = TRANSCODER_DSI_C;
9407 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9408 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9410 *power_domain_mask |= BIT_ULL(power_domain);
9413 * The PLL needs to be enabled with a valid divider
9414 * configuration, otherwise accessing DSI registers will hang
9415 * the machine. See BSpec North Display Engine
9416 * registers/MIPI[BXT]. We can break out here early, since we
9417 * need the same DSI PLL to be enabled for both DSI ports.
9419 if (!bxt_dsi_pll_is_enabled(dev_priv))
9422 /* XXX: this works for video mode only */
9423 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9424 if (!(tmp & DPI_ENABLE))
9427 tmp = I915_READ(MIPI_CTRL(port));
9428 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9431 pipe_config->cpu_transcoder = cpu_transcoder;
9435 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9438 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9439 struct intel_crtc_state *pipe_config)
9441 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9442 struct intel_shared_dpll *pll;
9446 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9448 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9450 if (IS_ICELAKE(dev_priv))
9451 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9452 else if (IS_CANNONLAKE(dev_priv))
9453 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9454 else if (IS_GEN9_BC(dev_priv))
9455 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9456 else if (IS_GEN9_LP(dev_priv))
9457 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9459 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9461 pll = pipe_config->shared_dpll;
9463 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9464 &pipe_config->dpll_hw_state));
9468 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9469 * DDI E. So just check whether this pipe is wired to DDI E and whether
9470 * the PCH transcoder is on.
9472 if (INTEL_GEN(dev_priv) < 9 &&
9473 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9474 pipe_config->has_pch_encoder = true;
9476 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9477 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9478 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9480 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9484 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9485 struct intel_crtc_state *pipe_config)
9487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9488 enum intel_display_power_domain power_domain;
9489 u64 power_domain_mask;
9492 intel_crtc_init_scalers(crtc, pipe_config);
9494 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9495 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9497 power_domain_mask = BIT_ULL(power_domain);
9499 pipe_config->shared_dpll = NULL;
9501 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9503 if (IS_GEN9_LP(dev_priv) &&
9504 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9512 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9513 haswell_get_ddi_port_state(crtc, pipe_config);
9514 intel_get_pipe_timings(crtc, pipe_config);
9517 intel_get_pipe_src_size(crtc, pipe_config);
9519 pipe_config->gamma_mode =
9520 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9522 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9523 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9524 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9526 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9527 bool blend_mode_420 = tmp &
9528 PIPEMISC_YUV420_MODE_FULL_BLEND;
9530 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9531 if (pipe_config->ycbcr420 != clrspace_yuv ||
9532 pipe_config->ycbcr420 != blend_mode_420)
9533 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9534 } else if (clrspace_yuv) {
9535 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9539 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9540 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9541 power_domain_mask |= BIT_ULL(power_domain);
9542 if (INTEL_GEN(dev_priv) >= 9)
9543 skylake_get_pfit_config(crtc, pipe_config);
9545 ironlake_get_pfit_config(crtc, pipe_config);
9548 if (hsw_crtc_supports_ips(crtc)) {
9549 if (IS_HASWELL(dev_priv))
9550 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9553 * We cannot readout IPS state on broadwell, set to
9554 * true so we can set it to a defined state on first
9557 pipe_config->ips_enabled = true;
9561 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9562 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9563 pipe_config->pixel_multiplier =
9564 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9566 pipe_config->pixel_multiplier = 1;
9570 for_each_power_domain(power_domain, power_domain_mask)
9571 intel_display_power_put(dev_priv, power_domain);
9576 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9578 struct drm_i915_private *dev_priv =
9579 to_i915(plane_state->base.plane->dev);
9580 const struct drm_framebuffer *fb = plane_state->base.fb;
9581 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9584 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9585 base = obj->phys_handle->busaddr;
9587 base = intel_plane_ggtt_offset(plane_state);
9589 base += plane_state->main.offset;
9591 /* ILK+ do this automagically */
9592 if (HAS_GMCH_DISPLAY(dev_priv) &&
9593 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9594 base += (plane_state->base.crtc_h *
9595 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9600 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9602 int x = plane_state->base.crtc_x;
9603 int y = plane_state->base.crtc_y;
9607 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9610 pos |= x << CURSOR_X_SHIFT;
9613 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9616 pos |= y << CURSOR_Y_SHIFT;
9621 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9623 const struct drm_mode_config *config =
9624 &plane_state->base.plane->dev->mode_config;
9625 int width = plane_state->base.crtc_w;
9626 int height = plane_state->base.crtc_h;
9628 return width > 0 && width <= config->cursor_width &&
9629 height > 0 && height <= config->cursor_height;
9632 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9633 struct intel_plane_state *plane_state)
9635 const struct drm_framebuffer *fb = plane_state->base.fb;
9640 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9642 DRM_PLANE_HELPER_NO_SCALING,
9643 DRM_PLANE_HELPER_NO_SCALING,
9651 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9652 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9656 src_x = plane_state->base.src_x >> 16;
9657 src_y = plane_state->base.src_y >> 16;
9659 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9660 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9662 if (src_x != 0 || src_y != 0) {
9663 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9667 plane_state->main.offset = offset;
9672 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9673 const struct intel_plane_state *plane_state)
9675 const struct drm_framebuffer *fb = plane_state->base.fb;
9677 return CURSOR_ENABLE |
9678 CURSOR_GAMMA_ENABLE |
9679 CURSOR_FORMAT_ARGB |
9680 CURSOR_STRIDE(fb->pitches[0]);
9683 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9685 int width = plane_state->base.crtc_w;
9688 * 845g/865g are only limited by the width of their cursors,
9689 * the height is arbitrary up to the precision of the register.
9691 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9694 static int i845_check_cursor(struct intel_plane *plane,
9695 struct intel_crtc_state *crtc_state,
9696 struct intel_plane_state *plane_state)
9698 const struct drm_framebuffer *fb = plane_state->base.fb;
9701 ret = intel_check_cursor(crtc_state, plane_state);
9705 /* if we want to turn off the cursor ignore width and height */
9709 /* Check for which cursor types we support */
9710 if (!i845_cursor_size_ok(plane_state)) {
9711 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9712 plane_state->base.crtc_w,
9713 plane_state->base.crtc_h);
9717 switch (fb->pitches[0]) {
9724 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9729 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9734 static void i845_update_cursor(struct intel_plane *plane,
9735 const struct intel_crtc_state *crtc_state,
9736 const struct intel_plane_state *plane_state)
9738 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9739 u32 cntl = 0, base = 0, pos = 0, size = 0;
9740 unsigned long irqflags;
9742 if (plane_state && plane_state->base.visible) {
9743 unsigned int width = plane_state->base.crtc_w;
9744 unsigned int height = plane_state->base.crtc_h;
9746 cntl = plane_state->ctl;
9747 size = (height << 12) | width;
9749 base = intel_cursor_base(plane_state);
9750 pos = intel_cursor_position(plane_state);
9753 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9755 /* On these chipsets we can only modify the base/size/stride
9756 * whilst the cursor is disabled.
9758 if (plane->cursor.base != base ||
9759 plane->cursor.size != size ||
9760 plane->cursor.cntl != cntl) {
9761 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9762 I915_WRITE_FW(CURBASE(PIPE_A), base);
9763 I915_WRITE_FW(CURSIZE, size);
9764 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9765 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9767 plane->cursor.base = base;
9768 plane->cursor.size = size;
9769 plane->cursor.cntl = cntl;
9771 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9774 POSTING_READ_FW(CURCNTR(PIPE_A));
9776 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9779 static void i845_disable_cursor(struct intel_plane *plane,
9780 struct intel_crtc *crtc)
9782 i845_update_cursor(plane, NULL, NULL);
9785 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
9788 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9789 enum intel_display_power_domain power_domain;
9792 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9793 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9796 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9800 intel_display_power_put(dev_priv, power_domain);
9805 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9806 const struct intel_plane_state *plane_state)
9808 struct drm_i915_private *dev_priv =
9809 to_i915(plane_state->base.plane->dev);
9810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9813 if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
9814 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
9816 if (INTEL_GEN(dev_priv) <= 10) {
9817 cntl |= MCURSOR_GAMMA_ENABLE;
9819 if (HAS_DDI(dev_priv))
9820 cntl |= MCURSOR_PIPE_CSC_ENABLE;
9823 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9824 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9826 switch (plane_state->base.crtc_w) {
9828 cntl |= MCURSOR_MODE_64_ARGB_AX;
9831 cntl |= MCURSOR_MODE_128_ARGB_AX;
9834 cntl |= MCURSOR_MODE_256_ARGB_AX;
9837 MISSING_CASE(plane_state->base.crtc_w);
9841 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9842 cntl |= MCURSOR_ROTATE_180;
9847 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9849 struct drm_i915_private *dev_priv =
9850 to_i915(plane_state->base.plane->dev);
9851 int width = plane_state->base.crtc_w;
9852 int height = plane_state->base.crtc_h;
9854 if (!intel_cursor_size_ok(plane_state))
9857 /* Cursor width is limited to a few power-of-two sizes */
9868 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9869 * height from 8 lines up to the cursor width, when the
9870 * cursor is not rotated. Everything else requires square
9873 if (HAS_CUR_FBC(dev_priv) &&
9874 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9875 if (height < 8 || height > width)
9878 if (height != width)
9885 static int i9xx_check_cursor(struct intel_plane *plane,
9886 struct intel_crtc_state *crtc_state,
9887 struct intel_plane_state *plane_state)
9889 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9890 const struct drm_framebuffer *fb = plane_state->base.fb;
9891 enum pipe pipe = plane->pipe;
9894 ret = intel_check_cursor(crtc_state, plane_state);
9898 /* if we want to turn off the cursor ignore width and height */
9902 /* Check for which cursor types we support */
9903 if (!i9xx_cursor_size_ok(plane_state)) {
9904 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9905 plane_state->base.crtc_w,
9906 plane_state->base.crtc_h);
9910 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9911 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9912 fb->pitches[0], plane_state->base.crtc_w);
9917 * There's something wrong with the cursor on CHV pipe C.
9918 * If it straddles the left edge of the screen then
9919 * moving it away from the edge or disabling it often
9920 * results in a pipe underrun, and often that can lead to
9921 * dead pipe (constant underrun reported, and it scans
9922 * out just a solid color). To recover from that, the
9923 * display power well must be turned off and on again.
9924 * Refuse the put the cursor into that compromised position.
9926 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9927 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9928 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9932 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9937 static void i9xx_update_cursor(struct intel_plane *plane,
9938 const struct intel_crtc_state *crtc_state,
9939 const struct intel_plane_state *plane_state)
9941 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9942 enum pipe pipe = plane->pipe;
9943 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9944 unsigned long irqflags;
9946 if (plane_state && plane_state->base.visible) {
9947 cntl = plane_state->ctl;
9949 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9950 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9952 base = intel_cursor_base(plane_state);
9953 pos = intel_cursor_position(plane_state);
9956 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9959 * On some platforms writing CURCNTR first will also
9960 * cause CURPOS to be armed by the CURBASE write.
9961 * Without the CURCNTR write the CURPOS write would
9962 * arm itself. Thus we always start the full update
9963 * with a CURCNTR write.
9965 * On other platforms CURPOS always requires the
9966 * CURBASE write to arm the update. Additonally
9967 * a write to any of the cursor register will cancel
9968 * an already armed cursor update. Thus leaving out
9969 * the CURBASE write after CURPOS could lead to a
9970 * cursor that doesn't appear to move, or even change
9971 * shape. Thus we always write CURBASE.
9973 * CURCNTR and CUR_FBC_CTL are always
9974 * armed by the CURBASE write only.
9976 if (plane->cursor.base != base ||
9977 plane->cursor.size != fbc_ctl ||
9978 plane->cursor.cntl != cntl) {
9979 I915_WRITE_FW(CURCNTR(pipe), cntl);
9980 if (HAS_CUR_FBC(dev_priv))
9981 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9982 I915_WRITE_FW(CURPOS(pipe), pos);
9983 I915_WRITE_FW(CURBASE(pipe), base);
9985 plane->cursor.base = base;
9986 plane->cursor.size = fbc_ctl;
9987 plane->cursor.cntl = cntl;
9989 I915_WRITE_FW(CURPOS(pipe), pos);
9990 I915_WRITE_FW(CURBASE(pipe), base);
9993 POSTING_READ_FW(CURBASE(pipe));
9995 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9998 static void i9xx_disable_cursor(struct intel_plane *plane,
9999 struct intel_crtc *crtc)
10001 i9xx_update_cursor(plane, NULL, NULL);
10004 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10007 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10008 enum intel_display_power_domain power_domain;
10013 * Not 100% correct for planes that can move between pipes,
10014 * but that's only the case for gen2-3 which don't have any
10015 * display power wells.
10017 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10018 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10021 val = I915_READ(CURCNTR(plane->pipe));
10023 ret = val & MCURSOR_MODE;
10025 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10026 *pipe = plane->pipe;
10028 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10029 MCURSOR_PIPE_SELECT_SHIFT;
10031 intel_display_power_put(dev_priv, power_domain);
10036 /* VESA 640x480x72Hz mode to set on the pipe */
10037 static const struct drm_display_mode load_detect_mode = {
10038 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10039 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10042 struct drm_framebuffer *
10043 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10044 struct drm_mode_fb_cmd2 *mode_cmd)
10046 struct intel_framebuffer *intel_fb;
10049 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10051 return ERR_PTR(-ENOMEM);
10053 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10057 return &intel_fb->base;
10061 return ERR_PTR(ret);
10064 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10065 struct drm_crtc *crtc)
10067 struct drm_plane *plane;
10068 struct drm_plane_state *plane_state;
10071 ret = drm_atomic_add_affected_planes(state, crtc);
10075 for_each_new_plane_in_state(state, plane, plane_state, i) {
10076 if (plane_state->crtc != crtc)
10079 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10083 drm_atomic_set_fb_for_plane(plane_state, NULL);
10089 int intel_get_load_detect_pipe(struct drm_connector *connector,
10090 const struct drm_display_mode *mode,
10091 struct intel_load_detect_pipe *old,
10092 struct drm_modeset_acquire_ctx *ctx)
10094 struct intel_crtc *intel_crtc;
10095 struct intel_encoder *intel_encoder =
10096 intel_attached_encoder(connector);
10097 struct drm_crtc *possible_crtc;
10098 struct drm_encoder *encoder = &intel_encoder->base;
10099 struct drm_crtc *crtc = NULL;
10100 struct drm_device *dev = encoder->dev;
10101 struct drm_i915_private *dev_priv = to_i915(dev);
10102 struct drm_mode_config *config = &dev->mode_config;
10103 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10104 struct drm_connector_state *connector_state;
10105 struct intel_crtc_state *crtc_state;
10108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10109 connector->base.id, connector->name,
10110 encoder->base.id, encoder->name);
10112 old->restore_state = NULL;
10114 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10117 * Algorithm gets a little messy:
10119 * - if the connector already has an assigned crtc, use it (but make
10120 * sure it's on first)
10122 * - try to find the first unused crtc that can drive this connector,
10123 * and use that if we find one
10126 /* See if we already have a CRTC for this connector */
10127 if (connector->state->crtc) {
10128 crtc = connector->state->crtc;
10130 ret = drm_modeset_lock(&crtc->mutex, ctx);
10134 /* Make sure the crtc and connector are running */
10138 /* Find an unused one (if possible) */
10139 for_each_crtc(dev, possible_crtc) {
10141 if (!(encoder->possible_crtcs & (1 << i)))
10144 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10148 if (possible_crtc->state->enable) {
10149 drm_modeset_unlock(&possible_crtc->mutex);
10153 crtc = possible_crtc;
10158 * If we didn't find an unused CRTC, don't use any.
10161 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10167 intel_crtc = to_intel_crtc(crtc);
10169 state = drm_atomic_state_alloc(dev);
10170 restore_state = drm_atomic_state_alloc(dev);
10171 if (!state || !restore_state) {
10176 state->acquire_ctx = ctx;
10177 restore_state->acquire_ctx = ctx;
10179 connector_state = drm_atomic_get_connector_state(state, connector);
10180 if (IS_ERR(connector_state)) {
10181 ret = PTR_ERR(connector_state);
10185 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10189 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10190 if (IS_ERR(crtc_state)) {
10191 ret = PTR_ERR(crtc_state);
10195 crtc_state->base.active = crtc_state->base.enable = true;
10198 mode = &load_detect_mode;
10200 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10204 ret = intel_modeset_disable_planes(state, crtc);
10208 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10210 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10212 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10214 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10218 ret = drm_atomic_commit(state);
10220 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10224 old->restore_state = restore_state;
10225 drm_atomic_state_put(state);
10227 /* let the connector get through one full cycle before testing */
10228 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10233 drm_atomic_state_put(state);
10236 if (restore_state) {
10237 drm_atomic_state_put(restore_state);
10238 restore_state = NULL;
10241 if (ret == -EDEADLK)
10247 void intel_release_load_detect_pipe(struct drm_connector *connector,
10248 struct intel_load_detect_pipe *old,
10249 struct drm_modeset_acquire_ctx *ctx)
10251 struct intel_encoder *intel_encoder =
10252 intel_attached_encoder(connector);
10253 struct drm_encoder *encoder = &intel_encoder->base;
10254 struct drm_atomic_state *state = old->restore_state;
10257 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10258 connector->base.id, connector->name,
10259 encoder->base.id, encoder->name);
10264 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10266 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10267 drm_atomic_state_put(state);
10270 static int i9xx_pll_refclk(struct drm_device *dev,
10271 const struct intel_crtc_state *pipe_config)
10273 struct drm_i915_private *dev_priv = to_i915(dev);
10274 u32 dpll = pipe_config->dpll_hw_state.dpll;
10276 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10277 return dev_priv->vbt.lvds_ssc_freq;
10278 else if (HAS_PCH_SPLIT(dev_priv))
10280 else if (!IS_GEN2(dev_priv))
10286 /* Returns the clock of the currently programmed mode of the given pipe. */
10287 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10288 struct intel_crtc_state *pipe_config)
10290 struct drm_device *dev = crtc->base.dev;
10291 struct drm_i915_private *dev_priv = to_i915(dev);
10292 int pipe = pipe_config->cpu_transcoder;
10293 u32 dpll = pipe_config->dpll_hw_state.dpll;
10297 int refclk = i9xx_pll_refclk(dev, pipe_config);
10299 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10300 fp = pipe_config->dpll_hw_state.fp0;
10302 fp = pipe_config->dpll_hw_state.fp1;
10304 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10305 if (IS_PINEVIEW(dev_priv)) {
10306 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10307 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10309 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10310 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10313 if (!IS_GEN2(dev_priv)) {
10314 if (IS_PINEVIEW(dev_priv))
10315 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10316 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10318 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10319 DPLL_FPA01_P1_POST_DIV_SHIFT);
10321 switch (dpll & DPLL_MODE_MASK) {
10322 case DPLLB_MODE_DAC_SERIAL:
10323 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10326 case DPLLB_MODE_LVDS:
10327 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10331 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10332 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10336 if (IS_PINEVIEW(dev_priv))
10337 port_clock = pnv_calc_dpll_params(refclk, &clock);
10339 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10341 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10342 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10345 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10346 DPLL_FPA01_P1_POST_DIV_SHIFT);
10348 if (lvds & LVDS_CLKB_POWER_UP)
10353 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10356 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10357 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10359 if (dpll & PLL_P2_DIVIDE_BY_4)
10365 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10369 * This value includes pixel_multiplier. We will use
10370 * port_clock to compute adjusted_mode.crtc_clock in the
10371 * encoder's get_config() function.
10373 pipe_config->port_clock = port_clock;
10376 int intel_dotclock_calculate(int link_freq,
10377 const struct intel_link_m_n *m_n)
10380 * The calculation for the data clock is:
10381 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10382 * But we want to avoid losing precison if possible, so:
10383 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10385 * and the link clock is simpler:
10386 * link_clock = (m * link_clock) / n
10392 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10395 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10396 struct intel_crtc_state *pipe_config)
10398 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10400 /* read out port_clock from the DPLL */
10401 i9xx_crtc_clock_get(crtc, pipe_config);
10404 * In case there is an active pipe without active ports,
10405 * we may need some idea for the dotclock anyway.
10406 * Calculate one based on the FDI configuration.
10408 pipe_config->base.adjusted_mode.crtc_clock =
10409 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10410 &pipe_config->fdi_m_n);
10413 /* Returns the currently programmed mode of the given encoder. */
10414 struct drm_display_mode *
10415 intel_encoder_current_mode(struct intel_encoder *encoder)
10417 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10418 struct intel_crtc_state *crtc_state;
10419 struct drm_display_mode *mode;
10420 struct intel_crtc *crtc;
10423 if (!encoder->get_hw_state(encoder, &pipe))
10426 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10428 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10432 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10438 crtc_state->base.crtc = &crtc->base;
10440 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10446 encoder->get_config(encoder, crtc_state);
10448 intel_mode_from_pipe_config(mode, crtc_state);
10455 static void intel_crtc_destroy(struct drm_crtc *crtc)
10457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10459 drm_crtc_cleanup(crtc);
10464 * intel_wm_need_update - Check whether watermarks need updating
10465 * @plane: drm plane
10466 * @state: new plane state
10468 * Check current plane state versus the new one to determine whether
10469 * watermarks need to be recalculated.
10471 * Returns true or false.
10473 static bool intel_wm_need_update(struct drm_plane *plane,
10474 struct drm_plane_state *state)
10476 struct intel_plane_state *new = to_intel_plane_state(state);
10477 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10479 /* Update watermarks on tiling or size changes. */
10480 if (new->base.visible != cur->base.visible)
10483 if (!cur->base.fb || !new->base.fb)
10486 if (cur->base.fb->modifier != new->base.fb->modifier ||
10487 cur->base.rotation != new->base.rotation ||
10488 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10489 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10490 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10491 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10497 static bool needs_scaling(const struct intel_plane_state *state)
10499 int src_w = drm_rect_width(&state->base.src) >> 16;
10500 int src_h = drm_rect_height(&state->base.src) >> 16;
10501 int dst_w = drm_rect_width(&state->base.dst);
10502 int dst_h = drm_rect_height(&state->base.dst);
10504 return (src_w != dst_w || src_h != dst_h);
10507 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10508 struct drm_crtc_state *crtc_state,
10509 const struct intel_plane_state *old_plane_state,
10510 struct drm_plane_state *plane_state)
10512 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10513 struct drm_crtc *crtc = crtc_state->crtc;
10514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10515 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10516 struct drm_device *dev = crtc->dev;
10517 struct drm_i915_private *dev_priv = to_i915(dev);
10518 bool mode_changed = needs_modeset(crtc_state);
10519 bool was_crtc_enabled = old_crtc_state->base.active;
10520 bool is_crtc_enabled = crtc_state->active;
10521 bool turn_off, turn_on, visible, was_visible;
10522 struct drm_framebuffer *fb = plane_state->fb;
10525 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10526 ret = skl_update_scaler_plane(
10527 to_intel_crtc_state(crtc_state),
10528 to_intel_plane_state(plane_state));
10533 was_visible = old_plane_state->base.visible;
10534 visible = plane_state->visible;
10536 if (!was_crtc_enabled && WARN_ON(was_visible))
10537 was_visible = false;
10540 * Visibility is calculated as if the crtc was on, but
10541 * after scaler setup everything depends on it being off
10542 * when the crtc isn't active.
10544 * FIXME this is wrong for watermarks. Watermarks should also
10545 * be computed as if the pipe would be active. Perhaps move
10546 * per-plane wm computation to the .check_plane() hook, and
10547 * only combine the results from all planes in the current place?
10549 if (!is_crtc_enabled) {
10550 plane_state->visible = visible = false;
10551 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10554 if (!was_visible && !visible)
10557 if (fb != old_plane_state->base.fb)
10558 pipe_config->fb_changed = true;
10560 turn_off = was_visible && (!visible || mode_changed);
10561 turn_on = visible && (!was_visible || mode_changed);
10563 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10564 intel_crtc->base.base.id, intel_crtc->base.name,
10565 plane->base.base.id, plane->base.name,
10566 fb ? fb->base.id : -1);
10568 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10569 plane->base.base.id, plane->base.name,
10570 was_visible, visible,
10571 turn_off, turn_on, mode_changed);
10574 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10575 pipe_config->update_wm_pre = true;
10577 /* must disable cxsr around plane enable/disable */
10578 if (plane->id != PLANE_CURSOR)
10579 pipe_config->disable_cxsr = true;
10580 } else if (turn_off) {
10581 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10582 pipe_config->update_wm_post = true;
10584 /* must disable cxsr around plane enable/disable */
10585 if (plane->id != PLANE_CURSOR)
10586 pipe_config->disable_cxsr = true;
10587 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10588 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10589 /* FIXME bollocks */
10590 pipe_config->update_wm_pre = true;
10591 pipe_config->update_wm_post = true;
10595 if (visible || was_visible)
10596 pipe_config->fb_bits |= plane->frontbuffer_bit;
10599 * WaCxSRDisabledForSpriteScaling:ivb
10601 * cstate->update_wm was already set above, so this flag will
10602 * take effect when we commit and program watermarks.
10604 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10605 needs_scaling(to_intel_plane_state(plane_state)) &&
10606 !needs_scaling(old_plane_state))
10607 pipe_config->disable_lp_wm = true;
10612 static bool encoders_cloneable(const struct intel_encoder *a,
10613 const struct intel_encoder *b)
10615 /* masks could be asymmetric, so check both ways */
10616 return a == b || (a->cloneable & (1 << b->type) &&
10617 b->cloneable & (1 << a->type));
10620 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10621 struct intel_crtc *crtc,
10622 struct intel_encoder *encoder)
10624 struct intel_encoder *source_encoder;
10625 struct drm_connector *connector;
10626 struct drm_connector_state *connector_state;
10629 for_each_new_connector_in_state(state, connector, connector_state, i) {
10630 if (connector_state->crtc != &crtc->base)
10634 to_intel_encoder(connector_state->best_encoder);
10635 if (!encoders_cloneable(encoder, source_encoder))
10642 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10643 struct drm_crtc_state *crtc_state)
10645 struct drm_device *dev = crtc->dev;
10646 struct drm_i915_private *dev_priv = to_i915(dev);
10647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10648 struct intel_crtc_state *pipe_config =
10649 to_intel_crtc_state(crtc_state);
10650 struct drm_atomic_state *state = crtc_state->state;
10652 bool mode_changed = needs_modeset(crtc_state);
10654 if (mode_changed && !crtc_state->active)
10655 pipe_config->update_wm_post = true;
10657 if (mode_changed && crtc_state->enable &&
10658 dev_priv->display.crtc_compute_clock &&
10659 !WARN_ON(pipe_config->shared_dpll)) {
10660 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10666 if (crtc_state->color_mgmt_changed) {
10667 ret = intel_color_check(crtc, crtc_state);
10672 * Changing color management on Intel hardware is
10673 * handled as part of planes update.
10675 crtc_state->planes_changed = true;
10679 if (dev_priv->display.compute_pipe_wm) {
10680 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10682 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10687 if (dev_priv->display.compute_intermediate_wm &&
10688 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10689 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10693 * Calculate 'intermediate' watermarks that satisfy both the
10694 * old state and the new state. We can program these
10697 ret = dev_priv->display.compute_intermediate_wm(dev,
10701 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10704 } else if (dev_priv->display.compute_intermediate_wm) {
10705 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10706 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10709 if (INTEL_GEN(dev_priv) >= 9) {
10711 ret = skl_update_scaler_crtc(pipe_config);
10714 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10717 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10721 if (HAS_IPS(dev_priv))
10722 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10727 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10728 .atomic_begin = intel_begin_crtc_commit,
10729 .atomic_flush = intel_finish_crtc_commit,
10730 .atomic_check = intel_crtc_atomic_check,
10733 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10735 struct intel_connector *connector;
10736 struct drm_connector_list_iter conn_iter;
10738 drm_connector_list_iter_begin(dev, &conn_iter);
10739 for_each_intel_connector_iter(connector, &conn_iter) {
10740 if (connector->base.state->crtc)
10741 drm_connector_put(&connector->base);
10743 if (connector->base.encoder) {
10744 connector->base.state->best_encoder =
10745 connector->base.encoder;
10746 connector->base.state->crtc =
10747 connector->base.encoder->crtc;
10749 drm_connector_get(&connector->base);
10751 connector->base.state->best_encoder = NULL;
10752 connector->base.state->crtc = NULL;
10755 drm_connector_list_iter_end(&conn_iter);
10759 connected_sink_compute_bpp(struct intel_connector *connector,
10760 struct intel_crtc_state *pipe_config)
10762 const struct drm_display_info *info = &connector->base.display_info;
10763 int bpp = pipe_config->pipe_bpp;
10765 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10766 connector->base.base.id,
10767 connector->base.name);
10769 /* Don't use an invalid EDID bpc value */
10770 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10771 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10772 bpp, info->bpc * 3);
10773 pipe_config->pipe_bpp = info->bpc * 3;
10776 /* Clamp bpp to 8 on screens without EDID 1.4 */
10777 if (info->bpc == 0 && bpp > 24) {
10778 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10780 pipe_config->pipe_bpp = 24;
10785 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10786 struct intel_crtc_state *pipe_config)
10788 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10789 struct drm_atomic_state *state;
10790 struct drm_connector *connector;
10791 struct drm_connector_state *connector_state;
10794 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10795 IS_CHERRYVIEW(dev_priv)))
10797 else if (INTEL_GEN(dev_priv) >= 5)
10803 pipe_config->pipe_bpp = bpp;
10805 state = pipe_config->base.state;
10807 /* Clamp display bpp to EDID value */
10808 for_each_new_connector_in_state(state, connector, connector_state, i) {
10809 if (connector_state->crtc != &crtc->base)
10812 connected_sink_compute_bpp(to_intel_connector(connector),
10819 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10821 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10822 "type: 0x%x flags: 0x%x\n",
10824 mode->crtc_hdisplay, mode->crtc_hsync_start,
10825 mode->crtc_hsync_end, mode->crtc_htotal,
10826 mode->crtc_vdisplay, mode->crtc_vsync_start,
10827 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10831 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10832 unsigned int lane_count, struct intel_link_m_n *m_n)
10834 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10836 m_n->gmch_m, m_n->gmch_n,
10837 m_n->link_m, m_n->link_n, m_n->tu);
10840 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10842 static const char * const output_type_str[] = {
10843 OUTPUT_TYPE(UNUSED),
10844 OUTPUT_TYPE(ANALOG),
10848 OUTPUT_TYPE(TVOUT),
10854 OUTPUT_TYPE(DP_MST),
10859 static void snprintf_output_types(char *buf, size_t len,
10860 unsigned int output_types)
10867 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10870 if ((output_types & BIT(i)) == 0)
10873 r = snprintf(str, len, "%s%s",
10874 str != buf ? "," : "", output_type_str[i]);
10880 output_types &= ~BIT(i);
10883 WARN_ON_ONCE(output_types != 0);
10886 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10887 struct intel_crtc_state *pipe_config,
10888 const char *context)
10890 struct drm_device *dev = crtc->base.dev;
10891 struct drm_i915_private *dev_priv = to_i915(dev);
10892 struct drm_plane *plane;
10893 struct intel_plane *intel_plane;
10894 struct intel_plane_state *state;
10895 struct drm_framebuffer *fb;
10898 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10899 crtc->base.base.id, crtc->base.name, context);
10901 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10902 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10903 buf, pipe_config->output_types);
10905 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10906 transcoder_name(pipe_config->cpu_transcoder),
10907 pipe_config->pipe_bpp, pipe_config->dither);
10909 if (pipe_config->has_pch_encoder)
10910 intel_dump_m_n_config(pipe_config, "fdi",
10911 pipe_config->fdi_lanes,
10912 &pipe_config->fdi_m_n);
10914 if (pipe_config->ycbcr420)
10915 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10917 if (intel_crtc_has_dp_encoder(pipe_config)) {
10918 intel_dump_m_n_config(pipe_config, "dp m_n",
10919 pipe_config->lane_count, &pipe_config->dp_m_n);
10920 if (pipe_config->has_drrs)
10921 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10922 pipe_config->lane_count,
10923 &pipe_config->dp_m2_n2);
10926 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10927 pipe_config->has_audio, pipe_config->has_infoframe);
10929 DRM_DEBUG_KMS("requested mode:\n");
10930 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10931 DRM_DEBUG_KMS("adjusted mode:\n");
10932 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10933 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10934 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10935 pipe_config->port_clock,
10936 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10937 pipe_config->pixel_rate);
10939 if (INTEL_GEN(dev_priv) >= 9)
10940 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10942 pipe_config->scaler_state.scaler_users,
10943 pipe_config->scaler_state.scaler_id);
10945 if (HAS_GMCH_DISPLAY(dev_priv))
10946 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10947 pipe_config->gmch_pfit.control,
10948 pipe_config->gmch_pfit.pgm_ratios,
10949 pipe_config->gmch_pfit.lvds_border_bits);
10951 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10952 pipe_config->pch_pfit.pos,
10953 pipe_config->pch_pfit.size,
10954 enableddisabled(pipe_config->pch_pfit.enabled));
10956 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10957 pipe_config->ips_enabled, pipe_config->double_wide);
10959 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10961 DRM_DEBUG_KMS("planes on this crtc\n");
10962 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10963 struct drm_format_name_buf format_name;
10964 intel_plane = to_intel_plane(plane);
10965 if (intel_plane->pipe != crtc->pipe)
10968 state = to_intel_plane_state(plane->state);
10969 fb = state->base.fb;
10971 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10972 plane->base.id, plane->name, state->scaler_id);
10976 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10977 plane->base.id, plane->name,
10978 fb->base.id, fb->width, fb->height,
10979 drm_get_format_name(fb->format->format, &format_name));
10980 if (INTEL_GEN(dev_priv) >= 9)
10981 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10983 state->base.src.x1 >> 16,
10984 state->base.src.y1 >> 16,
10985 drm_rect_width(&state->base.src) >> 16,
10986 drm_rect_height(&state->base.src) >> 16,
10987 state->base.dst.x1, state->base.dst.y1,
10988 drm_rect_width(&state->base.dst),
10989 drm_rect_height(&state->base.dst));
10993 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10995 struct drm_device *dev = state->dev;
10996 struct drm_connector *connector;
10997 struct drm_connector_list_iter conn_iter;
10998 unsigned int used_ports = 0;
10999 unsigned int used_mst_ports = 0;
11003 * Walk the connector list instead of the encoder
11004 * list to detect the problem on ddi platforms
11005 * where there's just one encoder per digital port.
11007 drm_connector_list_iter_begin(dev, &conn_iter);
11008 drm_for_each_connector_iter(connector, &conn_iter) {
11009 struct drm_connector_state *connector_state;
11010 struct intel_encoder *encoder;
11012 connector_state = drm_atomic_get_new_connector_state(state, connector);
11013 if (!connector_state)
11014 connector_state = connector->state;
11016 if (!connector_state->best_encoder)
11019 encoder = to_intel_encoder(connector_state->best_encoder);
11021 WARN_ON(!connector_state->crtc);
11023 switch (encoder->type) {
11024 unsigned int port_mask;
11025 case INTEL_OUTPUT_DDI:
11026 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11028 /* else: fall through */
11029 case INTEL_OUTPUT_DP:
11030 case INTEL_OUTPUT_HDMI:
11031 case INTEL_OUTPUT_EDP:
11032 port_mask = 1 << encoder->port;
11034 /* the same port mustn't appear more than once */
11035 if (used_ports & port_mask)
11038 used_ports |= port_mask;
11040 case INTEL_OUTPUT_DP_MST:
11042 1 << encoder->port;
11048 drm_connector_list_iter_end(&conn_iter);
11050 /* can't mix MST and SST/HDMI on the same port */
11051 if (used_ports & used_mst_ports)
11058 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11060 struct drm_i915_private *dev_priv =
11061 to_i915(crtc_state->base.crtc->dev);
11062 struct intel_crtc_scaler_state scaler_state;
11063 struct intel_dpll_hw_state dpll_hw_state;
11064 struct intel_shared_dpll *shared_dpll;
11065 struct intel_crtc_wm_state wm_state;
11066 bool force_thru, ips_force_disable;
11068 /* FIXME: before the switch to atomic started, a new pipe_config was
11069 * kzalloc'd. Code that depends on any field being zero should be
11070 * fixed, so that the crtc_state can be safely duplicated. For now,
11071 * only fields that are know to not cause problems are preserved. */
11073 scaler_state = crtc_state->scaler_state;
11074 shared_dpll = crtc_state->shared_dpll;
11075 dpll_hw_state = crtc_state->dpll_hw_state;
11076 force_thru = crtc_state->pch_pfit.force_thru;
11077 ips_force_disable = crtc_state->ips_force_disable;
11078 if (IS_G4X(dev_priv) ||
11079 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11080 wm_state = crtc_state->wm;
11082 /* Keep base drm_crtc_state intact, only clear our extended struct */
11083 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11084 memset(&crtc_state->base + 1, 0,
11085 sizeof(*crtc_state) - sizeof(crtc_state->base));
11087 crtc_state->scaler_state = scaler_state;
11088 crtc_state->shared_dpll = shared_dpll;
11089 crtc_state->dpll_hw_state = dpll_hw_state;
11090 crtc_state->pch_pfit.force_thru = force_thru;
11091 crtc_state->ips_force_disable = ips_force_disable;
11092 if (IS_G4X(dev_priv) ||
11093 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11094 crtc_state->wm = wm_state;
11098 intel_modeset_pipe_config(struct drm_crtc *crtc,
11099 struct intel_crtc_state *pipe_config)
11101 struct drm_atomic_state *state = pipe_config->base.state;
11102 struct intel_encoder *encoder;
11103 struct drm_connector *connector;
11104 struct drm_connector_state *connector_state;
11105 int base_bpp, ret = -EINVAL;
11109 clear_intel_crtc_state(pipe_config);
11111 pipe_config->cpu_transcoder =
11112 (enum transcoder) to_intel_crtc(crtc)->pipe;
11115 * Sanitize sync polarity flags based on requested ones. If neither
11116 * positive or negative polarity is requested, treat this as meaning
11117 * negative polarity.
11119 if (!(pipe_config->base.adjusted_mode.flags &
11120 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11121 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11123 if (!(pipe_config->base.adjusted_mode.flags &
11124 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11125 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11127 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11133 * Determine the real pipe dimensions. Note that stereo modes can
11134 * increase the actual pipe size due to the frame doubling and
11135 * insertion of additional space for blanks between the frame. This
11136 * is stored in the crtc timings. We use the requested mode to do this
11137 * computation to clearly distinguish it from the adjusted mode, which
11138 * can be changed by the connectors in the below retry loop.
11140 drm_mode_get_hv_timing(&pipe_config->base.mode,
11141 &pipe_config->pipe_src_w,
11142 &pipe_config->pipe_src_h);
11144 for_each_new_connector_in_state(state, connector, connector_state, i) {
11145 if (connector_state->crtc != crtc)
11148 encoder = to_intel_encoder(connector_state->best_encoder);
11150 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11151 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11156 * Determine output_types before calling the .compute_config()
11157 * hooks so that the hooks can use this information safely.
11159 if (encoder->compute_output_type)
11160 pipe_config->output_types |=
11161 BIT(encoder->compute_output_type(encoder, pipe_config,
11164 pipe_config->output_types |= BIT(encoder->type);
11168 /* Ensure the port clock defaults are reset when retrying. */
11169 pipe_config->port_clock = 0;
11170 pipe_config->pixel_multiplier = 1;
11172 /* Fill in default crtc timings, allow encoders to overwrite them. */
11173 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11174 CRTC_STEREO_DOUBLE);
11176 /* Pass our mode to the connectors and the CRTC to give them a chance to
11177 * adjust it according to limitations or connector properties, and also
11178 * a chance to reject the mode entirely.
11180 for_each_new_connector_in_state(state, connector, connector_state, i) {
11181 if (connector_state->crtc != crtc)
11184 encoder = to_intel_encoder(connector_state->best_encoder);
11186 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11187 DRM_DEBUG_KMS("Encoder config failure\n");
11192 /* Set default port clock if not overwritten by the encoder. Needs to be
11193 * done afterwards in case the encoder adjusts the mode. */
11194 if (!pipe_config->port_clock)
11195 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11196 * pipe_config->pixel_multiplier;
11198 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11200 DRM_DEBUG_KMS("CRTC fixup failed\n");
11204 if (ret == RETRY) {
11205 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11210 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11212 goto encoder_retry;
11215 /* Dithering seems to not pass-through bits correctly when it should, so
11216 * only enable it on 6bpc panels and when its not a compliance
11217 * test requesting 6bpc video pattern.
11219 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11220 !pipe_config->dither_force_disable;
11221 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11222 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11228 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11232 if (clock1 == clock2)
11235 if (!clock1 || !clock2)
11238 diff = abs(clock1 - clock2);
11240 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11247 intel_compare_m_n(unsigned int m, unsigned int n,
11248 unsigned int m2, unsigned int n2,
11251 if (m == m2 && n == n2)
11254 if (exact || !m || !n || !m2 || !n2)
11257 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11264 } else if (n < n2) {
11274 return intel_fuzzy_clock_check(m, m2);
11278 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11279 struct intel_link_m_n *m2_n2,
11282 if (m_n->tu == m2_n2->tu &&
11283 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11284 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11285 intel_compare_m_n(m_n->link_m, m_n->link_n,
11286 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11296 static void __printf(3, 4)
11297 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11299 struct va_format vaf;
11302 va_start(args, format);
11307 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11309 drm_err("mismatch in %s %pV", name, &vaf);
11315 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11316 struct intel_crtc_state *current_config,
11317 struct intel_crtc_state *pipe_config,
11321 bool fixup_inherited = adjust &&
11322 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11323 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11325 #define PIPE_CONF_CHECK_X(name) do { \
11326 if (current_config->name != pipe_config->name) { \
11327 pipe_config_err(adjust, __stringify(name), \
11328 "(expected 0x%08x, found 0x%08x)\n", \
11329 current_config->name, \
11330 pipe_config->name); \
11335 #define PIPE_CONF_CHECK_I(name) do { \
11336 if (current_config->name != pipe_config->name) { \
11337 pipe_config_err(adjust, __stringify(name), \
11338 "(expected %i, found %i)\n", \
11339 current_config->name, \
11340 pipe_config->name); \
11345 #define PIPE_CONF_CHECK_BOOL(name) do { \
11346 if (current_config->name != pipe_config->name) { \
11347 pipe_config_err(adjust, __stringify(name), \
11348 "(expected %s, found %s)\n", \
11349 yesno(current_config->name), \
11350 yesno(pipe_config->name)); \
11356 * Checks state where we only read out the enabling, but not the entire
11357 * state itself (like full infoframes or ELD for audio). These states
11358 * require a full modeset on bootup to fix up.
11360 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11361 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11362 PIPE_CONF_CHECK_BOOL(name); \
11364 pipe_config_err(adjust, __stringify(name), \
11365 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11366 yesno(current_config->name), \
11367 yesno(pipe_config->name)); \
11372 #define PIPE_CONF_CHECK_P(name) do { \
11373 if (current_config->name != pipe_config->name) { \
11374 pipe_config_err(adjust, __stringify(name), \
11375 "(expected %p, found %p)\n", \
11376 current_config->name, \
11377 pipe_config->name); \
11382 #define PIPE_CONF_CHECK_M_N(name) do { \
11383 if (!intel_compare_link_m_n(¤t_config->name, \
11384 &pipe_config->name,\
11386 pipe_config_err(adjust, __stringify(name), \
11387 "(expected tu %i gmch %i/%i link %i/%i, " \
11388 "found tu %i, gmch %i/%i link %i/%i)\n", \
11389 current_config->name.tu, \
11390 current_config->name.gmch_m, \
11391 current_config->name.gmch_n, \
11392 current_config->name.link_m, \
11393 current_config->name.link_n, \
11394 pipe_config->name.tu, \
11395 pipe_config->name.gmch_m, \
11396 pipe_config->name.gmch_n, \
11397 pipe_config->name.link_m, \
11398 pipe_config->name.link_n); \
11403 /* This is required for BDW+ where there is only one set of registers for
11404 * switching between high and low RR.
11405 * This macro can be used whenever a comparison has to be made between one
11406 * hw state and multiple sw state variables.
11408 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11409 if (!intel_compare_link_m_n(¤t_config->name, \
11410 &pipe_config->name, adjust) && \
11411 !intel_compare_link_m_n(¤t_config->alt_name, \
11412 &pipe_config->name, adjust)) { \
11413 pipe_config_err(adjust, __stringify(name), \
11414 "(expected tu %i gmch %i/%i link %i/%i, " \
11415 "or tu %i gmch %i/%i link %i/%i, " \
11416 "found tu %i, gmch %i/%i link %i/%i)\n", \
11417 current_config->name.tu, \
11418 current_config->name.gmch_m, \
11419 current_config->name.gmch_n, \
11420 current_config->name.link_m, \
11421 current_config->name.link_n, \
11422 current_config->alt_name.tu, \
11423 current_config->alt_name.gmch_m, \
11424 current_config->alt_name.gmch_n, \
11425 current_config->alt_name.link_m, \
11426 current_config->alt_name.link_n, \
11427 pipe_config->name.tu, \
11428 pipe_config->name.gmch_m, \
11429 pipe_config->name.gmch_n, \
11430 pipe_config->name.link_m, \
11431 pipe_config->name.link_n); \
11436 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11437 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11438 pipe_config_err(adjust, __stringify(name), \
11439 "(%x) (expected %i, found %i)\n", \
11441 current_config->name & (mask), \
11442 pipe_config->name & (mask)); \
11447 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11448 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11449 pipe_config_err(adjust, __stringify(name), \
11450 "(expected %i, found %i)\n", \
11451 current_config->name, \
11452 pipe_config->name); \
11457 #define PIPE_CONF_QUIRK(quirk) \
11458 ((current_config->quirks | pipe_config->quirks) & (quirk))
11460 PIPE_CONF_CHECK_I(cpu_transcoder);
11462 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11463 PIPE_CONF_CHECK_I(fdi_lanes);
11464 PIPE_CONF_CHECK_M_N(fdi_m_n);
11466 PIPE_CONF_CHECK_I(lane_count);
11467 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11469 if (INTEL_GEN(dev_priv) < 8) {
11470 PIPE_CONF_CHECK_M_N(dp_m_n);
11472 if (current_config->has_drrs)
11473 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11475 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11477 PIPE_CONF_CHECK_X(output_types);
11479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11491 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11493 PIPE_CONF_CHECK_I(pixel_multiplier);
11494 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11495 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11496 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11497 PIPE_CONF_CHECK_BOOL(limited_color_range);
11499 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11500 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11501 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11502 PIPE_CONF_CHECK_BOOL(ycbcr420);
11504 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11506 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11507 DRM_MODE_FLAG_INTERLACE);
11509 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11510 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11511 DRM_MODE_FLAG_PHSYNC);
11512 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11513 DRM_MODE_FLAG_NHSYNC);
11514 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11515 DRM_MODE_FLAG_PVSYNC);
11516 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11517 DRM_MODE_FLAG_NVSYNC);
11520 PIPE_CONF_CHECK_X(gmch_pfit.control);
11521 /* pfit ratios are autocomputed by the hw on gen4+ */
11522 if (INTEL_GEN(dev_priv) < 4)
11523 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11524 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11527 PIPE_CONF_CHECK_I(pipe_src_w);
11528 PIPE_CONF_CHECK_I(pipe_src_h);
11530 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11531 if (current_config->pch_pfit.enabled) {
11532 PIPE_CONF_CHECK_X(pch_pfit.pos);
11533 PIPE_CONF_CHECK_X(pch_pfit.size);
11536 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11537 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11540 PIPE_CONF_CHECK_BOOL(double_wide);
11542 PIPE_CONF_CHECK_P(shared_dpll);
11543 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11544 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11545 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11546 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11547 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11548 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11549 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11550 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11551 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11552 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11553 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11554 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11555 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11556 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11557 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11558 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11559 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11560 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11561 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11562 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11563 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11564 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
11565 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
11566 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
11567 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
11568 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
11569 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
11570 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
11571 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
11572 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
11573 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
11575 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11576 PIPE_CONF_CHECK_X(dsi_pll.div);
11578 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11579 PIPE_CONF_CHECK_I(pipe_bpp);
11581 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11582 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11584 PIPE_CONF_CHECK_I(min_voltage_level);
11586 #undef PIPE_CONF_CHECK_X
11587 #undef PIPE_CONF_CHECK_I
11588 #undef PIPE_CONF_CHECK_BOOL
11589 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11590 #undef PIPE_CONF_CHECK_P
11591 #undef PIPE_CONF_CHECK_FLAGS
11592 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11593 #undef PIPE_CONF_QUIRK
11598 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11599 const struct intel_crtc_state *pipe_config)
11601 if (pipe_config->has_pch_encoder) {
11602 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11603 &pipe_config->fdi_m_n);
11604 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11607 * FDI already provided one idea for the dotclock.
11608 * Yell if the encoder disagrees.
11610 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11611 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11612 fdi_dotclock, dotclock);
11616 static void verify_wm_state(struct drm_crtc *crtc,
11617 struct drm_crtc_state *new_state)
11619 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11620 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11621 struct skl_pipe_wm hw_wm, *sw_wm;
11622 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11623 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11625 const enum pipe pipe = intel_crtc->pipe;
11626 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11628 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11631 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11632 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11634 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11635 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11637 if (INTEL_GEN(dev_priv) >= 11)
11638 if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
11639 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
11640 sw_ddb->enabled_slices,
11641 hw_ddb.enabled_slices);
11643 for_each_universal_plane(dev_priv, pipe, plane) {
11644 hw_plane_wm = &hw_wm.planes[plane];
11645 sw_plane_wm = &sw_wm->planes[plane];
11648 for (level = 0; level <= max_level; level++) {
11649 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11650 &sw_plane_wm->wm[level]))
11653 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11654 pipe_name(pipe), plane + 1, level,
11655 sw_plane_wm->wm[level].plane_en,
11656 sw_plane_wm->wm[level].plane_res_b,
11657 sw_plane_wm->wm[level].plane_res_l,
11658 hw_plane_wm->wm[level].plane_en,
11659 hw_plane_wm->wm[level].plane_res_b,
11660 hw_plane_wm->wm[level].plane_res_l);
11663 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11664 &sw_plane_wm->trans_wm)) {
11665 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11666 pipe_name(pipe), plane + 1,
11667 sw_plane_wm->trans_wm.plane_en,
11668 sw_plane_wm->trans_wm.plane_res_b,
11669 sw_plane_wm->trans_wm.plane_res_l,
11670 hw_plane_wm->trans_wm.plane_en,
11671 hw_plane_wm->trans_wm.plane_res_b,
11672 hw_plane_wm->trans_wm.plane_res_l);
11676 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11677 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11679 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11680 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11681 pipe_name(pipe), plane + 1,
11682 sw_ddb_entry->start, sw_ddb_entry->end,
11683 hw_ddb_entry->start, hw_ddb_entry->end);
11689 * If the cursor plane isn't active, we may not have updated it's ddb
11690 * allocation. In that case since the ddb allocation will be updated
11691 * once the plane becomes visible, we can skip this check
11694 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11695 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11698 for (level = 0; level <= max_level; level++) {
11699 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11700 &sw_plane_wm->wm[level]))
11703 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11704 pipe_name(pipe), level,
11705 sw_plane_wm->wm[level].plane_en,
11706 sw_plane_wm->wm[level].plane_res_b,
11707 sw_plane_wm->wm[level].plane_res_l,
11708 hw_plane_wm->wm[level].plane_en,
11709 hw_plane_wm->wm[level].plane_res_b,
11710 hw_plane_wm->wm[level].plane_res_l);
11713 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11714 &sw_plane_wm->trans_wm)) {
11715 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11717 sw_plane_wm->trans_wm.plane_en,
11718 sw_plane_wm->trans_wm.plane_res_b,
11719 sw_plane_wm->trans_wm.plane_res_l,
11720 hw_plane_wm->trans_wm.plane_en,
11721 hw_plane_wm->trans_wm.plane_res_b,
11722 hw_plane_wm->trans_wm.plane_res_l);
11726 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11727 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11729 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11730 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11732 sw_ddb_entry->start, sw_ddb_entry->end,
11733 hw_ddb_entry->start, hw_ddb_entry->end);
11739 verify_connector_state(struct drm_device *dev,
11740 struct drm_atomic_state *state,
11741 struct drm_crtc *crtc)
11743 struct drm_connector *connector;
11744 struct drm_connector_state *new_conn_state;
11747 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11748 struct drm_encoder *encoder = connector->encoder;
11749 struct drm_crtc_state *crtc_state = NULL;
11751 if (new_conn_state->crtc != crtc)
11755 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11757 intel_connector_verify_state(crtc_state, new_conn_state);
11759 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11760 "connector's atomic encoder doesn't match legacy encoder\n");
11765 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11767 struct intel_encoder *encoder;
11768 struct drm_connector *connector;
11769 struct drm_connector_state *old_conn_state, *new_conn_state;
11772 for_each_intel_encoder(dev, encoder) {
11773 bool enabled = false, found = false;
11776 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11777 encoder->base.base.id,
11778 encoder->base.name);
11780 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11781 new_conn_state, i) {
11782 if (old_conn_state->best_encoder == &encoder->base)
11785 if (new_conn_state->best_encoder != &encoder->base)
11787 found = enabled = true;
11789 I915_STATE_WARN(new_conn_state->crtc !=
11790 encoder->base.crtc,
11791 "connector's crtc doesn't match encoder crtc\n");
11797 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11798 "encoder's enabled state mismatch "
11799 "(expected %i, found %i)\n",
11800 !!encoder->base.crtc, enabled);
11802 if (!encoder->base.crtc) {
11805 active = encoder->get_hw_state(encoder, &pipe);
11806 I915_STATE_WARN(active,
11807 "encoder detached but still enabled on pipe %c.\n",
11814 verify_crtc_state(struct drm_crtc *crtc,
11815 struct drm_crtc_state *old_crtc_state,
11816 struct drm_crtc_state *new_crtc_state)
11818 struct drm_device *dev = crtc->dev;
11819 struct drm_i915_private *dev_priv = to_i915(dev);
11820 struct intel_encoder *encoder;
11821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11822 struct intel_crtc_state *pipe_config, *sw_config;
11823 struct drm_atomic_state *old_state;
11826 old_state = old_crtc_state->state;
11827 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11828 pipe_config = to_intel_crtc_state(old_crtc_state);
11829 memset(pipe_config, 0, sizeof(*pipe_config));
11830 pipe_config->base.crtc = crtc;
11831 pipe_config->base.state = old_state;
11833 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11835 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11837 /* we keep both pipes enabled on 830 */
11838 if (IS_I830(dev_priv))
11839 active = new_crtc_state->active;
11841 I915_STATE_WARN(new_crtc_state->active != active,
11842 "crtc active state doesn't match with hw state "
11843 "(expected %i, found %i)\n", new_crtc_state->active, active);
11845 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11846 "transitional active state does not match atomic hw state "
11847 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11849 for_each_encoder_on_crtc(dev, crtc, encoder) {
11852 active = encoder->get_hw_state(encoder, &pipe);
11853 I915_STATE_WARN(active != new_crtc_state->active,
11854 "[ENCODER:%i] active %i with crtc active %i\n",
11855 encoder->base.base.id, active, new_crtc_state->active);
11857 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11858 "Encoder connected to wrong pipe %c\n",
11862 encoder->get_config(encoder, pipe_config);
11865 intel_crtc_compute_pixel_rate(pipe_config);
11867 if (!new_crtc_state->active)
11870 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11872 sw_config = to_intel_crtc_state(new_crtc_state);
11873 if (!intel_pipe_config_compare(dev_priv, sw_config,
11874 pipe_config, false)) {
11875 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11876 intel_dump_pipe_config(intel_crtc, pipe_config,
11878 intel_dump_pipe_config(intel_crtc, sw_config,
11884 intel_verify_planes(struct intel_atomic_state *state)
11886 struct intel_plane *plane;
11887 const struct intel_plane_state *plane_state;
11890 for_each_new_intel_plane_in_state(state, plane,
11892 assert_plane(plane, plane_state->base.visible);
11896 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11897 struct intel_shared_dpll *pll,
11898 struct drm_crtc *crtc,
11899 struct drm_crtc_state *new_state)
11901 struct intel_dpll_hw_state dpll_hw_state;
11902 unsigned crtc_mask;
11905 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11907 DRM_DEBUG_KMS("%s\n", pll->info->name);
11909 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
11911 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
11912 I915_STATE_WARN(!pll->on && pll->active_mask,
11913 "pll in active use but not on in sw tracking\n");
11914 I915_STATE_WARN(pll->on && !pll->active_mask,
11915 "pll is on but not used by any active crtc\n");
11916 I915_STATE_WARN(pll->on != active,
11917 "pll on state mismatch (expected %i, found %i)\n",
11922 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11923 "more active pll users than references: %x vs %x\n",
11924 pll->active_mask, pll->state.crtc_mask);
11929 crtc_mask = 1 << drm_crtc_index(crtc);
11931 if (new_state->active)
11932 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11933 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11934 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11936 I915_STATE_WARN(pll->active_mask & crtc_mask,
11937 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11938 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11940 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11941 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11942 crtc_mask, pll->state.crtc_mask);
11944 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11946 sizeof(dpll_hw_state)),
11947 "pll hw state mismatch\n");
11951 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11952 struct drm_crtc_state *old_crtc_state,
11953 struct drm_crtc_state *new_crtc_state)
11955 struct drm_i915_private *dev_priv = to_i915(dev);
11956 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11957 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11959 if (new_state->shared_dpll)
11960 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11962 if (old_state->shared_dpll &&
11963 old_state->shared_dpll != new_state->shared_dpll) {
11964 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11965 struct intel_shared_dpll *pll = old_state->shared_dpll;
11967 I915_STATE_WARN(pll->active_mask & crtc_mask,
11968 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11969 pipe_name(drm_crtc_index(crtc)));
11970 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11971 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11972 pipe_name(drm_crtc_index(crtc)));
11977 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11978 struct drm_atomic_state *state,
11979 struct drm_crtc_state *old_state,
11980 struct drm_crtc_state *new_state)
11982 if (!needs_modeset(new_state) &&
11983 !to_intel_crtc_state(new_state)->update_pipe)
11986 verify_wm_state(crtc, new_state);
11987 verify_connector_state(crtc->dev, state, crtc);
11988 verify_crtc_state(crtc, old_state, new_state);
11989 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11993 verify_disabled_dpll_state(struct drm_device *dev)
11995 struct drm_i915_private *dev_priv = to_i915(dev);
11998 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11999 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12003 intel_modeset_verify_disabled(struct drm_device *dev,
12004 struct drm_atomic_state *state)
12006 verify_encoder_state(dev, state);
12007 verify_connector_state(dev, state, NULL);
12008 verify_disabled_dpll_state(dev);
12011 static void update_scanline_offset(struct intel_crtc *crtc)
12013 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12016 * The scanline counter increments at the leading edge of hsync.
12018 * On most platforms it starts counting from vtotal-1 on the
12019 * first active line. That means the scanline counter value is
12020 * always one less than what we would expect. Ie. just after
12021 * start of vblank, which also occurs at start of hsync (on the
12022 * last active line), the scanline counter will read vblank_start-1.
12024 * On gen2 the scanline counter starts counting from 1 instead
12025 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12026 * to keep the value positive), instead of adding one.
12028 * On HSW+ the behaviour of the scanline counter depends on the output
12029 * type. For DP ports it behaves like most other platforms, but on HDMI
12030 * there's an extra 1 line difference. So we need to add two instead of
12031 * one to the value.
12033 * On VLV/CHV DSI the scanline counter would appear to increment
12034 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12035 * that means we can't tell whether we're in vblank or not while
12036 * we're on that particular line. We must still set scanline_offset
12037 * to 1 so that the vblank timestamps come out correct when we query
12038 * the scanline counter from within the vblank interrupt handler.
12039 * However if queried just before the start of vblank we'll get an
12040 * answer that's slightly in the future.
12042 if (IS_GEN2(dev_priv)) {
12043 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12046 vtotal = adjusted_mode->crtc_vtotal;
12047 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12050 crtc->scanline_offset = vtotal - 1;
12051 } else if (HAS_DDI(dev_priv) &&
12052 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12053 crtc->scanline_offset = 2;
12055 crtc->scanline_offset = 1;
12058 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12060 struct drm_device *dev = state->dev;
12061 struct drm_i915_private *dev_priv = to_i915(dev);
12062 struct drm_crtc *crtc;
12063 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12066 if (!dev_priv->display.crtc_compute_clock)
12069 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12071 struct intel_shared_dpll *old_dpll =
12072 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12074 if (!needs_modeset(new_crtc_state))
12077 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12082 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12087 * This implements the workaround described in the "notes" section of the mode
12088 * set sequence documentation. When going from no pipes or single pipe to
12089 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12090 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12092 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12094 struct drm_crtc_state *crtc_state;
12095 struct intel_crtc *intel_crtc;
12096 struct drm_crtc *crtc;
12097 struct intel_crtc_state *first_crtc_state = NULL;
12098 struct intel_crtc_state *other_crtc_state = NULL;
12099 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12102 /* look at all crtc's that are going to be enabled in during modeset */
12103 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12104 intel_crtc = to_intel_crtc(crtc);
12106 if (!crtc_state->active || !needs_modeset(crtc_state))
12109 if (first_crtc_state) {
12110 other_crtc_state = to_intel_crtc_state(crtc_state);
12113 first_crtc_state = to_intel_crtc_state(crtc_state);
12114 first_pipe = intel_crtc->pipe;
12118 /* No workaround needed? */
12119 if (!first_crtc_state)
12122 /* w/a possibly needed, check how many crtc's are already enabled. */
12123 for_each_intel_crtc(state->dev, intel_crtc) {
12124 struct intel_crtc_state *pipe_config;
12126 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12127 if (IS_ERR(pipe_config))
12128 return PTR_ERR(pipe_config);
12130 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12132 if (!pipe_config->base.active ||
12133 needs_modeset(&pipe_config->base))
12136 /* 2 or more enabled crtcs means no need for w/a */
12137 if (enabled_pipe != INVALID_PIPE)
12140 enabled_pipe = intel_crtc->pipe;
12143 if (enabled_pipe != INVALID_PIPE)
12144 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12145 else if (other_crtc_state)
12146 other_crtc_state->hsw_workaround_pipe = first_pipe;
12151 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12153 struct drm_crtc *crtc;
12155 /* Add all pipes to the state */
12156 for_each_crtc(state->dev, crtc) {
12157 struct drm_crtc_state *crtc_state;
12159 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12160 if (IS_ERR(crtc_state))
12161 return PTR_ERR(crtc_state);
12167 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12169 struct drm_crtc *crtc;
12172 * Add all pipes to the state, and force
12173 * a modeset on all the active ones.
12175 for_each_crtc(state->dev, crtc) {
12176 struct drm_crtc_state *crtc_state;
12179 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12180 if (IS_ERR(crtc_state))
12181 return PTR_ERR(crtc_state);
12183 if (!crtc_state->active || needs_modeset(crtc_state))
12186 crtc_state->mode_changed = true;
12188 ret = drm_atomic_add_affected_connectors(state, crtc);
12192 ret = drm_atomic_add_affected_planes(state, crtc);
12200 static int intel_modeset_checks(struct drm_atomic_state *state)
12202 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12203 struct drm_i915_private *dev_priv = to_i915(state->dev);
12204 struct drm_crtc *crtc;
12205 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12208 if (!check_digital_port_conflicts(state)) {
12209 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12213 intel_state->modeset = true;
12214 intel_state->active_crtcs = dev_priv->active_crtcs;
12215 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12216 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12218 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12219 if (new_crtc_state->active)
12220 intel_state->active_crtcs |= 1 << i;
12222 intel_state->active_crtcs &= ~(1 << i);
12224 if (old_crtc_state->active != new_crtc_state->active)
12225 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12229 * See if the config requires any additional preparation, e.g.
12230 * to adjust global state with pipes off. We need to do this
12231 * here so we can get the modeset_pipe updated config for the new
12232 * mode set on this crtc. For other crtcs we need to use the
12233 * adjusted_mode bits in the crtc directly.
12235 if (dev_priv->display.modeset_calc_cdclk) {
12236 ret = dev_priv->display.modeset_calc_cdclk(state);
12241 * Writes to dev_priv->cdclk.logical must protected by
12242 * holding all the crtc locks, even if we don't end up
12243 * touching the hardware
12245 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12246 &intel_state->cdclk.logical)) {
12247 ret = intel_lock_all_pipes(state);
12252 /* All pipes must be switched off while we change the cdclk. */
12253 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12254 &intel_state->cdclk.actual)) {
12255 ret = intel_modeset_all_pipes(state);
12260 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12261 intel_state->cdclk.logical.cdclk,
12262 intel_state->cdclk.actual.cdclk);
12263 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12264 intel_state->cdclk.logical.voltage_level,
12265 intel_state->cdclk.actual.voltage_level);
12267 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12270 intel_modeset_clear_plls(state);
12272 if (IS_HASWELL(dev_priv))
12273 return haswell_mode_set_planes_workaround(state);
12279 * Handle calculation of various watermark data at the end of the atomic check
12280 * phase. The code here should be run after the per-crtc and per-plane 'check'
12281 * handlers to ensure that all derived state has been updated.
12283 static int calc_watermark_data(struct drm_atomic_state *state)
12285 struct drm_device *dev = state->dev;
12286 struct drm_i915_private *dev_priv = to_i915(dev);
12288 /* Is there platform-specific watermark information to calculate? */
12289 if (dev_priv->display.compute_global_watermarks)
12290 return dev_priv->display.compute_global_watermarks(state);
12296 * intel_atomic_check - validate state object
12298 * @state: state to validate
12300 static int intel_atomic_check(struct drm_device *dev,
12301 struct drm_atomic_state *state)
12303 struct drm_i915_private *dev_priv = to_i915(dev);
12304 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12305 struct drm_crtc *crtc;
12306 struct drm_crtc_state *old_crtc_state, *crtc_state;
12308 bool any_ms = false;
12310 /* Catch I915_MODE_FLAG_INHERITED */
12311 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12313 if (crtc_state->mode.private_flags !=
12314 old_crtc_state->mode.private_flags)
12315 crtc_state->mode_changed = true;
12318 ret = drm_atomic_helper_check_modeset(dev, state);
12322 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12323 struct intel_crtc_state *pipe_config =
12324 to_intel_crtc_state(crtc_state);
12326 if (!needs_modeset(crtc_state))
12329 if (!crtc_state->enable) {
12334 ret = intel_modeset_pipe_config(crtc, pipe_config);
12336 intel_dump_pipe_config(to_intel_crtc(crtc),
12337 pipe_config, "[failed]");
12341 if (i915_modparams.fastboot &&
12342 intel_pipe_config_compare(dev_priv,
12343 to_intel_crtc_state(old_crtc_state),
12344 pipe_config, true)) {
12345 crtc_state->mode_changed = false;
12346 pipe_config->update_pipe = true;
12349 if (needs_modeset(crtc_state))
12352 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12353 needs_modeset(crtc_state) ?
12354 "[modeset]" : "[fastset]");
12358 ret = intel_modeset_checks(state);
12363 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12366 ret = drm_atomic_helper_check_planes(dev, state);
12370 intel_fbc_choose_crtc(dev_priv, intel_state);
12371 return calc_watermark_data(state);
12374 static int intel_atomic_prepare_commit(struct drm_device *dev,
12375 struct drm_atomic_state *state)
12377 return drm_atomic_helper_prepare_planes(dev, state);
12380 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12382 struct drm_device *dev = crtc->base.dev;
12384 if (!dev->max_vblank_count)
12385 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12387 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12390 static void intel_update_crtc(struct drm_crtc *crtc,
12391 struct drm_atomic_state *state,
12392 struct drm_crtc_state *old_crtc_state,
12393 struct drm_crtc_state *new_crtc_state)
12395 struct drm_device *dev = crtc->dev;
12396 struct drm_i915_private *dev_priv = to_i915(dev);
12397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12398 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12399 bool modeset = needs_modeset(new_crtc_state);
12400 struct intel_plane_state *new_plane_state =
12401 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12402 to_intel_plane(crtc->primary));
12405 update_scanline_offset(intel_crtc);
12406 dev_priv->display.crtc_enable(pipe_config, state);
12408 /* vblanks work again, re-enable pipe CRC. */
12409 intel_crtc_enable_pipe_crc(intel_crtc);
12411 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12415 if (new_plane_state)
12416 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12418 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12421 static void intel_update_crtcs(struct drm_atomic_state *state)
12423 struct drm_crtc *crtc;
12424 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12427 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12428 if (!new_crtc_state->active)
12431 intel_update_crtc(crtc, state, old_crtc_state,
12436 static void skl_update_crtcs(struct drm_atomic_state *state)
12438 struct drm_i915_private *dev_priv = to_i915(state->dev);
12439 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12440 struct drm_crtc *crtc;
12441 struct intel_crtc *intel_crtc;
12442 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12443 struct intel_crtc_state *cstate;
12444 unsigned int updated = 0;
12448 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12449 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12451 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12453 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12454 /* ignore allocations for crtc's that have been turned off. */
12455 if (new_crtc_state->active)
12456 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12458 /* If 2nd DBuf slice required, enable it here */
12459 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
12460 icl_dbuf_slices_update(dev_priv, required_slices);
12463 * Whenever the number of active pipes changes, we need to make sure we
12464 * update the pipes in the right order so that their ddb allocations
12465 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12466 * cause pipe underruns and other bad stuff.
12471 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12472 bool vbl_wait = false;
12473 unsigned int cmask = drm_crtc_mask(crtc);
12475 intel_crtc = to_intel_crtc(crtc);
12476 cstate = to_intel_crtc_state(new_crtc_state);
12477 pipe = intel_crtc->pipe;
12479 if (updated & cmask || !cstate->base.active)
12482 if (skl_ddb_allocation_overlaps(dev_priv,
12484 &cstate->wm.skl.ddb,
12489 entries[i] = &cstate->wm.skl.ddb;
12492 * If this is an already active pipe, it's DDB changed,
12493 * and this isn't the last pipe that needs updating
12494 * then we need to wait for a vblank to pass for the
12495 * new ddb allocation to take effect.
12497 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12498 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12499 !new_crtc_state->active_changed &&
12500 intel_state->wm_results.dirty_pipes != updated)
12503 intel_update_crtc(crtc, state, old_crtc_state,
12507 intel_wait_for_vblank(dev_priv, pipe);
12511 } while (progress);
12513 /* If 2nd DBuf slice is no more required disable it */
12514 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
12515 icl_dbuf_slices_update(dev_priv, required_slices);
12518 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12520 struct intel_atomic_state *state, *next;
12521 struct llist_node *freed;
12523 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12524 llist_for_each_entry_safe(state, next, freed, freed)
12525 drm_atomic_state_put(&state->base);
12528 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12530 struct drm_i915_private *dev_priv =
12531 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12533 intel_atomic_helper_free_state(dev_priv);
12536 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12538 struct wait_queue_entry wait_fence, wait_reset;
12539 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12541 init_wait_entry(&wait_fence, 0);
12542 init_wait_entry(&wait_reset, 0);
12544 prepare_to_wait(&intel_state->commit_ready.wait,
12545 &wait_fence, TASK_UNINTERRUPTIBLE);
12546 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12547 &wait_reset, TASK_UNINTERRUPTIBLE);
12550 if (i915_sw_fence_done(&intel_state->commit_ready)
12551 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12556 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12557 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12560 static void intel_atomic_cleanup_work(struct work_struct *work)
12562 struct drm_atomic_state *state =
12563 container_of(work, struct drm_atomic_state, commit_work);
12564 struct drm_i915_private *i915 = to_i915(state->dev);
12566 drm_atomic_helper_cleanup_planes(&i915->drm, state);
12567 drm_atomic_helper_commit_cleanup_done(state);
12568 drm_atomic_state_put(state);
12570 intel_atomic_helper_free_state(i915);
12573 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12575 struct drm_device *dev = state->dev;
12576 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12577 struct drm_i915_private *dev_priv = to_i915(dev);
12578 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12579 struct drm_crtc *crtc;
12580 struct intel_crtc_state *intel_cstate;
12581 u64 put_domains[I915_MAX_PIPES] = {};
12584 intel_atomic_commit_fence_wait(intel_state);
12586 drm_atomic_helper_wait_for_dependencies(state);
12588 if (intel_state->modeset)
12589 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12591 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12594 if (needs_modeset(new_crtc_state) ||
12595 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12597 put_domains[to_intel_crtc(crtc)->pipe] =
12598 modeset_get_crtc_power_domains(crtc,
12599 to_intel_crtc_state(new_crtc_state));
12602 if (!needs_modeset(new_crtc_state))
12605 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12606 to_intel_crtc_state(new_crtc_state));
12608 if (old_crtc_state->active) {
12609 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12612 * We need to disable pipe CRC before disabling the pipe,
12613 * or we race against vblank off.
12615 intel_crtc_disable_pipe_crc(intel_crtc);
12617 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12618 intel_crtc->active = false;
12619 intel_fbc_disable(intel_crtc);
12620 intel_disable_shared_dpll(intel_crtc);
12623 * Underruns don't always raise
12624 * interrupts, so check manually.
12626 intel_check_cpu_fifo_underruns(dev_priv);
12627 intel_check_pch_fifo_underruns(dev_priv);
12629 if (!new_crtc_state->active) {
12631 * Make sure we don't call initial_watermarks
12632 * for ILK-style watermark updates.
12634 * No clue what this is supposed to achieve.
12636 if (INTEL_GEN(dev_priv) >= 9)
12637 dev_priv->display.initial_watermarks(intel_state,
12638 to_intel_crtc_state(new_crtc_state));
12643 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12644 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12645 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12647 if (intel_state->modeset) {
12648 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12650 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12653 * SKL workaround: bspec recommends we disable the SAGV when we
12654 * have more then one pipe enabled
12656 if (!intel_can_enable_sagv(state))
12657 intel_disable_sagv(dev_priv);
12659 intel_modeset_verify_disabled(dev, state);
12662 /* Complete the events for pipes that have now been disabled */
12663 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12664 bool modeset = needs_modeset(new_crtc_state);
12666 /* Complete events for now disable pipes here. */
12667 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12668 spin_lock_irq(&dev->event_lock);
12669 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12670 spin_unlock_irq(&dev->event_lock);
12672 new_crtc_state->event = NULL;
12676 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12677 dev_priv->display.update_crtcs(state);
12679 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12680 * already, but still need the state for the delayed optimization. To
12682 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12683 * - schedule that vblank worker _before_ calling hw_done
12684 * - at the start of commit_tail, cancel it _synchrously
12685 * - switch over to the vblank wait helper in the core after that since
12686 * we don't need out special handling any more.
12688 drm_atomic_helper_wait_for_flip_done(dev, state);
12691 * Now that the vblank has passed, we can go ahead and program the
12692 * optimal watermarks on platforms that need two-step watermark
12695 * TODO: Move this (and other cleanup) to an async worker eventually.
12697 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12698 intel_cstate = to_intel_crtc_state(new_crtc_state);
12700 if (dev_priv->display.optimize_watermarks)
12701 dev_priv->display.optimize_watermarks(intel_state,
12705 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12706 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12708 if (put_domains[i])
12709 modeset_put_power_domains(dev_priv, put_domains[i]);
12711 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12714 if (intel_state->modeset)
12715 intel_verify_planes(intel_state);
12717 if (intel_state->modeset && intel_can_enable_sagv(state))
12718 intel_enable_sagv(dev_priv);
12720 drm_atomic_helper_commit_hw_done(state);
12722 if (intel_state->modeset) {
12723 /* As one of the primary mmio accessors, KMS has a high
12724 * likelihood of triggering bugs in unclaimed access. After we
12725 * finish modesetting, see if an error has been flagged, and if
12726 * so enable debugging for the next modeset - and hope we catch
12729 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12730 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12734 * Defer the cleanup of the old state to a separate worker to not
12735 * impede the current task (userspace for blocking modesets) that
12736 * are executed inline. For out-of-line asynchronous modesets/flips,
12737 * deferring to a new worker seems overkill, but we would place a
12738 * schedule point (cond_resched()) here anyway to keep latencies
12741 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
12742 schedule_work(&state->commit_work);
12745 static void intel_atomic_commit_work(struct work_struct *work)
12747 struct drm_atomic_state *state =
12748 container_of(work, struct drm_atomic_state, commit_work);
12750 intel_atomic_commit_tail(state);
12753 static int __i915_sw_fence_call
12754 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12755 enum i915_sw_fence_notify notify)
12757 struct intel_atomic_state *state =
12758 container_of(fence, struct intel_atomic_state, commit_ready);
12761 case FENCE_COMPLETE:
12762 /* we do blocking waits in the worker, nothing to do here */
12766 struct intel_atomic_helper *helper =
12767 &to_i915(state->base.dev)->atomic_helper;
12769 if (llist_add(&state->freed, &helper->free_list))
12770 schedule_work(&helper->free_work);
12775 return NOTIFY_DONE;
12778 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12780 struct drm_plane_state *old_plane_state, *new_plane_state;
12781 struct drm_plane *plane;
12784 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12785 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12786 intel_fb_obj(new_plane_state->fb),
12787 to_intel_plane(plane)->frontbuffer_bit);
12791 * intel_atomic_commit - commit validated state object
12793 * @state: the top-level driver state object
12794 * @nonblock: nonblocking commit
12796 * This function commits a top-level state object that has been validated
12797 * with drm_atomic_helper_check().
12800 * Zero for success or -errno.
12802 static int intel_atomic_commit(struct drm_device *dev,
12803 struct drm_atomic_state *state,
12806 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12807 struct drm_i915_private *dev_priv = to_i915(dev);
12810 drm_atomic_state_get(state);
12811 i915_sw_fence_init(&intel_state->commit_ready,
12812 intel_atomic_commit_ready);
12815 * The intel_legacy_cursor_update() fast path takes care
12816 * of avoiding the vblank waits for simple cursor
12817 * movement and flips. For cursor on/off and size changes,
12818 * we want to perform the vblank waits so that watermark
12819 * updates happen during the correct frames. Gen9+ have
12820 * double buffered watermarks and so shouldn't need this.
12822 * Unset state->legacy_cursor_update before the call to
12823 * drm_atomic_helper_setup_commit() because otherwise
12824 * drm_atomic_helper_wait_for_flip_done() is a noop and
12825 * we get FIFO underruns because we didn't wait
12828 * FIXME doing watermarks and fb cleanup from a vblank worker
12829 * (assuming we had any) would solve these problems.
12831 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12832 struct intel_crtc_state *new_crtc_state;
12833 struct intel_crtc *crtc;
12836 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12837 if (new_crtc_state->wm.need_postvbl_update ||
12838 new_crtc_state->update_wm_post)
12839 state->legacy_cursor_update = false;
12842 ret = intel_atomic_prepare_commit(dev, state);
12844 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12845 i915_sw_fence_commit(&intel_state->commit_ready);
12849 ret = drm_atomic_helper_setup_commit(state, nonblock);
12851 ret = drm_atomic_helper_swap_state(state, true);
12854 i915_sw_fence_commit(&intel_state->commit_ready);
12856 drm_atomic_helper_cleanup_planes(dev, state);
12859 dev_priv->wm.distrust_bios_wm = false;
12860 intel_shared_dpll_swap_state(state);
12861 intel_atomic_track_fbs(state);
12863 if (intel_state->modeset) {
12864 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12865 sizeof(intel_state->min_cdclk));
12866 memcpy(dev_priv->min_voltage_level,
12867 intel_state->min_voltage_level,
12868 sizeof(intel_state->min_voltage_level));
12869 dev_priv->active_crtcs = intel_state->active_crtcs;
12870 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12871 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12874 drm_atomic_state_get(state);
12875 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12877 i915_sw_fence_commit(&intel_state->commit_ready);
12878 if (nonblock && intel_state->modeset) {
12879 queue_work(dev_priv->modeset_wq, &state->commit_work);
12880 } else if (nonblock) {
12881 queue_work(system_unbound_wq, &state->commit_work);
12883 if (intel_state->modeset)
12884 flush_workqueue(dev_priv->modeset_wq);
12885 intel_atomic_commit_tail(state);
12891 static const struct drm_crtc_funcs intel_crtc_funcs = {
12892 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12893 .set_config = drm_atomic_helper_set_config,
12894 .destroy = intel_crtc_destroy,
12895 .page_flip = drm_atomic_helper_page_flip,
12896 .atomic_duplicate_state = intel_crtc_duplicate_state,
12897 .atomic_destroy_state = intel_crtc_destroy_state,
12898 .set_crc_source = intel_crtc_set_crc_source,
12901 struct wait_rps_boost {
12902 struct wait_queue_entry wait;
12904 struct drm_crtc *crtc;
12905 struct i915_request *request;
12908 static int do_rps_boost(struct wait_queue_entry *_wait,
12909 unsigned mode, int sync, void *key)
12911 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12912 struct i915_request *rq = wait->request;
12915 * If we missed the vblank, but the request is already running it
12916 * is reasonable to assume that it will complete before the next
12917 * vblank without our intervention, so leave RPS alone.
12919 if (!i915_request_started(rq))
12920 gen6_rps_boost(rq, NULL);
12921 i915_request_put(rq);
12923 drm_crtc_vblank_put(wait->crtc);
12925 list_del(&wait->wait.entry);
12930 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12931 struct dma_fence *fence)
12933 struct wait_rps_boost *wait;
12935 if (!dma_fence_is_i915(fence))
12938 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12941 if (drm_crtc_vblank_get(crtc))
12944 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12946 drm_crtc_vblank_put(crtc);
12950 wait->request = to_request(dma_fence_get(fence));
12953 wait->wait.func = do_rps_boost;
12954 wait->wait.flags = 0;
12956 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12959 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
12961 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12963 struct drm_framebuffer *fb = plane_state->base.fb;
12964 struct i915_vma *vma;
12966 if (plane->id == PLANE_CURSOR &&
12967 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12968 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12969 const int align = intel_cursor_alignment(dev_priv);
12971 return i915_gem_object_attach_phys(obj, align);
12974 vma = intel_pin_and_fence_fb_obj(fb,
12975 plane_state->base.rotation,
12976 intel_plane_uses_fence(plane_state),
12977 &plane_state->flags);
12979 return PTR_ERR(vma);
12981 plane_state->vma = vma;
12986 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
12988 struct i915_vma *vma;
12990 vma = fetch_and_zero(&old_plane_state->vma);
12992 intel_unpin_fb_vma(vma, old_plane_state->flags);
12995 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
12997 struct i915_sched_attr attr = {
12998 .priority = I915_PRIORITY_DISPLAY,
13001 i915_gem_object_wait_priority(obj, 0, &attr);
13005 * intel_prepare_plane_fb - Prepare fb for usage on plane
13006 * @plane: drm plane to prepare for
13007 * @new_state: the plane state being prepared
13009 * Prepares a framebuffer for usage on a display plane. Generally this
13010 * involves pinning the underlying object and updating the frontbuffer tracking
13011 * bits. Some older platforms need special physical address handling for
13014 * Must be called with struct_mutex held.
13016 * Returns 0 on success, negative error code on failure.
13019 intel_prepare_plane_fb(struct drm_plane *plane,
13020 struct drm_plane_state *new_state)
13022 struct intel_atomic_state *intel_state =
13023 to_intel_atomic_state(new_state->state);
13024 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13025 struct drm_framebuffer *fb = new_state->fb;
13026 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13027 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13031 struct drm_crtc_state *crtc_state =
13032 drm_atomic_get_new_crtc_state(new_state->state,
13033 plane->state->crtc);
13035 /* Big Hammer, we also need to ensure that any pending
13036 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13037 * current scanout is retired before unpinning the old
13038 * framebuffer. Note that we rely on userspace rendering
13039 * into the buffer attached to the pipe they are waiting
13040 * on. If not, userspace generates a GPU hang with IPEHR
13041 * point to the MI_WAIT_FOR_EVENT.
13043 * This should only fail upon a hung GPU, in which case we
13044 * can safely continue.
13046 if (needs_modeset(crtc_state)) {
13047 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13048 old_obj->resv, NULL,
13056 if (new_state->fence) { /* explicit fencing */
13057 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13059 I915_FENCE_TIMEOUT,
13068 ret = i915_gem_object_pin_pages(obj);
13072 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13074 i915_gem_object_unpin_pages(obj);
13078 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13080 fb_obj_bump_render_priority(obj);
13082 mutex_unlock(&dev_priv->drm.struct_mutex);
13083 i915_gem_object_unpin_pages(obj);
13087 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13089 if (!new_state->fence) { /* implicit fencing */
13090 struct dma_fence *fence;
13092 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13094 false, I915_FENCE_TIMEOUT,
13099 fence = reservation_object_get_excl_rcu(obj->resv);
13101 add_rps_boost_after_vblank(new_state->crtc, fence);
13102 dma_fence_put(fence);
13105 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13112 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13113 * @plane: drm plane to clean up for
13114 * @old_state: the state from the previous modeset
13116 * Cleans up a framebuffer that has just been removed from a plane.
13118 * Must be called with struct_mutex held.
13121 intel_cleanup_plane_fb(struct drm_plane *plane,
13122 struct drm_plane_state *old_state)
13124 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13126 /* Should only be called after a successful intel_prepare_plane_fb()! */
13127 mutex_lock(&dev_priv->drm.struct_mutex);
13128 intel_plane_unpin_fb(to_intel_plane_state(old_state));
13129 mutex_unlock(&dev_priv->drm.struct_mutex);
13133 skl_max_scale(struct intel_crtc *intel_crtc,
13134 struct intel_crtc_state *crtc_state,
13135 uint32_t pixel_format)
13137 struct drm_i915_private *dev_priv;
13138 int max_scale, mult;
13139 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13141 if (!intel_crtc || !crtc_state->base.enable)
13142 return DRM_PLANE_HELPER_NO_SCALING;
13144 dev_priv = to_i915(intel_crtc->base.dev);
13146 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13147 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13149 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13152 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13153 return DRM_PLANE_HELPER_NO_SCALING;
13156 * skl max scale is lower of:
13157 * close to 3 but not 3, -1 is for that purpose
13161 mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
13162 tmpclk1 = (1 << 16) * mult - 1;
13163 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13164 max_scale = min(tmpclk1, tmpclk2);
13170 intel_check_primary_plane(struct intel_plane *plane,
13171 struct intel_crtc_state *crtc_state,
13172 struct intel_plane_state *state)
13174 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13175 struct drm_crtc *crtc = state->base.crtc;
13176 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13177 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13178 bool can_position = false;
13180 uint32_t pixel_format = 0;
13182 if (INTEL_GEN(dev_priv) >= 9) {
13183 /* use scaler when colorkey is not required */
13184 if (!state->ckey.flags) {
13186 if (state->base.fb)
13187 pixel_format = state->base.fb->format->format;
13188 max_scale = skl_max_scale(to_intel_crtc(crtc),
13189 crtc_state, pixel_format);
13191 can_position = true;
13194 ret = drm_atomic_helper_check_plane_state(&state->base,
13196 min_scale, max_scale,
13197 can_position, true);
13201 if (!state->base.fb)
13204 if (INTEL_GEN(dev_priv) >= 9) {
13205 ret = skl_check_plane_surface(crtc_state, state);
13209 state->ctl = skl_plane_ctl(crtc_state, state);
13211 ret = i9xx_check_plane_surface(state);
13215 state->ctl = i9xx_plane_ctl(crtc_state, state);
13218 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
13219 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
13224 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13225 struct drm_crtc_state *old_crtc_state)
13227 struct drm_device *dev = crtc->dev;
13228 struct drm_i915_private *dev_priv = to_i915(dev);
13229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13230 struct intel_crtc_state *old_intel_cstate =
13231 to_intel_crtc_state(old_crtc_state);
13232 struct intel_atomic_state *old_intel_state =
13233 to_intel_atomic_state(old_crtc_state->state);
13234 struct intel_crtc_state *intel_cstate =
13235 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13236 bool modeset = needs_modeset(&intel_cstate->base);
13239 (intel_cstate->base.color_mgmt_changed ||
13240 intel_cstate->update_pipe)) {
13241 intel_color_set_csc(&intel_cstate->base);
13242 intel_color_load_luts(&intel_cstate->base);
13245 /* Perform vblank evasion around commit operation */
13246 intel_pipe_update_start(intel_cstate);
13251 if (intel_cstate->update_pipe)
13252 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13253 else if (INTEL_GEN(dev_priv) >= 9)
13254 skl_detach_scalers(intel_crtc);
13257 if (dev_priv->display.atomic_update_watermarks)
13258 dev_priv->display.atomic_update_watermarks(old_intel_state,
13262 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13263 struct intel_crtc_state *crtc_state)
13265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13267 if (!IS_GEN2(dev_priv))
13268 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13270 if (crtc_state->has_pch_encoder) {
13271 enum pipe pch_transcoder =
13272 intel_crtc_pch_transcoder(crtc);
13274 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13278 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13279 struct drm_crtc_state *old_crtc_state)
13281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13282 struct intel_atomic_state *old_intel_state =
13283 to_intel_atomic_state(old_crtc_state->state);
13284 struct intel_crtc_state *new_crtc_state =
13285 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13287 intel_pipe_update_end(new_crtc_state);
13289 if (new_crtc_state->update_pipe &&
13290 !needs_modeset(&new_crtc_state->base) &&
13291 old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13292 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
13296 * intel_plane_destroy - destroy a plane
13297 * @plane: plane to destroy
13299 * Common destruction function for all types of planes (primary, cursor,
13302 void intel_plane_destroy(struct drm_plane *plane)
13304 drm_plane_cleanup(plane);
13305 kfree(to_intel_plane(plane));
13308 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
13311 case DRM_FORMAT_C8:
13312 case DRM_FORMAT_RGB565:
13313 case DRM_FORMAT_XRGB1555:
13314 case DRM_FORMAT_XRGB8888:
13315 return modifier == DRM_FORMAT_MOD_LINEAR ||
13316 modifier == I915_FORMAT_MOD_X_TILED;
13322 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
13325 case DRM_FORMAT_C8:
13326 case DRM_FORMAT_RGB565:
13327 case DRM_FORMAT_XRGB8888:
13328 case DRM_FORMAT_XBGR8888:
13329 case DRM_FORMAT_XRGB2101010:
13330 case DRM_FORMAT_XBGR2101010:
13331 return modifier == DRM_FORMAT_MOD_LINEAR ||
13332 modifier == I915_FORMAT_MOD_X_TILED;
13338 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13341 case DRM_FORMAT_XRGB8888:
13342 case DRM_FORMAT_XBGR8888:
13343 case DRM_FORMAT_ARGB8888:
13344 case DRM_FORMAT_ABGR8888:
13345 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13346 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13349 case DRM_FORMAT_RGB565:
13350 case DRM_FORMAT_XRGB2101010:
13351 case DRM_FORMAT_XBGR2101010:
13352 case DRM_FORMAT_YUYV:
13353 case DRM_FORMAT_YVYU:
13354 case DRM_FORMAT_UYVY:
13355 case DRM_FORMAT_VYUY:
13356 case DRM_FORMAT_NV12:
13357 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13360 case DRM_FORMAT_C8:
13361 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13362 modifier == I915_FORMAT_MOD_X_TILED ||
13363 modifier == I915_FORMAT_MOD_Y_TILED)
13371 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13375 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13377 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13380 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13381 modifier != DRM_FORMAT_MOD_LINEAR)
13384 if (INTEL_GEN(dev_priv) >= 9)
13385 return skl_mod_supported(format, modifier);
13386 else if (INTEL_GEN(dev_priv) >= 4)
13387 return i965_mod_supported(format, modifier);
13389 return i8xx_mod_supported(format, modifier);
13392 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13396 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13399 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13402 static struct drm_plane_funcs intel_plane_funcs = {
13403 .update_plane = drm_atomic_helper_update_plane,
13404 .disable_plane = drm_atomic_helper_disable_plane,
13405 .destroy = intel_plane_destroy,
13406 .atomic_get_property = intel_plane_atomic_get_property,
13407 .atomic_set_property = intel_plane_atomic_set_property,
13408 .atomic_duplicate_state = intel_plane_duplicate_state,
13409 .atomic_destroy_state = intel_plane_destroy_state,
13410 .format_mod_supported = intel_primary_plane_format_mod_supported,
13414 intel_legacy_cursor_update(struct drm_plane *plane,
13415 struct drm_crtc *crtc,
13416 struct drm_framebuffer *fb,
13417 int crtc_x, int crtc_y,
13418 unsigned int crtc_w, unsigned int crtc_h,
13419 uint32_t src_x, uint32_t src_y,
13420 uint32_t src_w, uint32_t src_h,
13421 struct drm_modeset_acquire_ctx *ctx)
13423 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13425 struct drm_plane_state *old_plane_state, *new_plane_state;
13426 struct intel_plane *intel_plane = to_intel_plane(plane);
13427 struct drm_framebuffer *old_fb;
13428 struct drm_crtc_state *crtc_state = crtc->state;
13431 * When crtc is inactive or there is a modeset pending,
13432 * wait for it to complete in the slowpath
13434 if (!crtc_state->active || needs_modeset(crtc_state) ||
13435 to_intel_crtc_state(crtc_state)->update_pipe)
13438 old_plane_state = plane->state;
13440 * Don't do an async update if there is an outstanding commit modifying
13441 * the plane. This prevents our async update's changes from getting
13442 * overridden by a previous synchronous update's state.
13444 if (old_plane_state->commit &&
13445 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13449 * If any parameters change that may affect watermarks,
13450 * take the slowpath. Only changing fb or position should be
13453 if (old_plane_state->crtc != crtc ||
13454 old_plane_state->src_w != src_w ||
13455 old_plane_state->src_h != src_h ||
13456 old_plane_state->crtc_w != crtc_w ||
13457 old_plane_state->crtc_h != crtc_h ||
13458 !old_plane_state->fb != !fb)
13461 new_plane_state = intel_plane_duplicate_state(plane);
13462 if (!new_plane_state)
13465 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13467 new_plane_state->src_x = src_x;
13468 new_plane_state->src_y = src_y;
13469 new_plane_state->src_w = src_w;
13470 new_plane_state->src_h = src_h;
13471 new_plane_state->crtc_x = crtc_x;
13472 new_plane_state->crtc_y = crtc_y;
13473 new_plane_state->crtc_w = crtc_w;
13474 new_plane_state->crtc_h = crtc_h;
13476 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13477 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13478 to_intel_plane_state(plane->state),
13479 to_intel_plane_state(new_plane_state));
13483 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13487 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13491 intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
13493 old_fb = old_plane_state->fb;
13494 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13495 intel_plane->frontbuffer_bit);
13497 /* Swap plane state */
13498 plane->state = new_plane_state;
13500 if (plane->state->visible) {
13501 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13502 intel_plane->update_plane(intel_plane,
13503 to_intel_crtc_state(crtc->state),
13504 to_intel_plane_state(plane->state));
13506 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13507 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13510 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13513 mutex_unlock(&dev_priv->drm.struct_mutex);
13516 intel_plane_destroy_state(plane, new_plane_state);
13518 intel_plane_destroy_state(plane, old_plane_state);
13522 return drm_atomic_helper_update_plane(plane, crtc, fb,
13523 crtc_x, crtc_y, crtc_w, crtc_h,
13524 src_x, src_y, src_w, src_h, ctx);
13527 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13528 .update_plane = intel_legacy_cursor_update,
13529 .disable_plane = drm_atomic_helper_disable_plane,
13530 .destroy = intel_plane_destroy,
13531 .atomic_get_property = intel_plane_atomic_get_property,
13532 .atomic_set_property = intel_plane_atomic_set_property,
13533 .atomic_duplicate_state = intel_plane_duplicate_state,
13534 .atomic_destroy_state = intel_plane_destroy_state,
13535 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13538 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13539 enum i9xx_plane_id i9xx_plane)
13541 if (!HAS_FBC(dev_priv))
13544 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13545 return i9xx_plane == PLANE_A; /* tied to pipe A */
13546 else if (IS_IVYBRIDGE(dev_priv))
13547 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13548 i9xx_plane == PLANE_C;
13549 else if (INTEL_GEN(dev_priv) >= 4)
13550 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13552 return i9xx_plane == PLANE_A;
13555 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13556 enum pipe pipe, enum plane_id plane_id)
13558 if (!HAS_FBC(dev_priv))
13561 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13564 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
13565 enum pipe pipe, enum plane_id plane_id)
13567 if (plane_id == PLANE_PRIMARY) {
13568 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13570 else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
13571 !IS_GEMINILAKE(dev_priv))
13573 } else if (plane_id >= PLANE_SPRITE0) {
13574 if (plane_id == PLANE_CURSOR)
13576 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
13577 if (plane_id != PLANE_SPRITE0)
13580 if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
13581 IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13588 static struct intel_plane *
13589 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13591 struct intel_plane *primary = NULL;
13592 struct intel_plane_state *state = NULL;
13593 const uint32_t *intel_primary_formats;
13594 unsigned int supported_rotations;
13595 unsigned int num_formats;
13596 const uint64_t *modifiers;
13599 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13605 state = intel_create_plane_state(&primary->base);
13611 primary->base.state = &state->base;
13613 primary->can_scale = false;
13614 primary->max_downscale = 1;
13615 if (INTEL_GEN(dev_priv) >= 9) {
13616 primary->can_scale = true;
13617 state->scaler_id = -1;
13619 primary->pipe = pipe;
13621 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13622 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13624 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13625 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13627 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13628 primary->id = PLANE_PRIMARY;
13629 primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13631 if (INTEL_GEN(dev_priv) >= 9)
13632 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13636 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13637 primary->i9xx_plane);
13639 if (primary->has_fbc) {
13640 struct intel_fbc *fbc = &dev_priv->fbc;
13642 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13645 primary->check_plane = intel_check_primary_plane;
13647 if (INTEL_GEN(dev_priv) >= 9) {
13648 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13649 intel_primary_formats = skl_pri_planar_formats;
13650 num_formats = ARRAY_SIZE(skl_pri_planar_formats);
13652 intel_primary_formats = skl_primary_formats;
13653 num_formats = ARRAY_SIZE(skl_primary_formats);
13656 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
13657 modifiers = skl_format_modifiers_ccs;
13659 modifiers = skl_format_modifiers_noccs;
13661 primary->update_plane = skl_update_plane;
13662 primary->disable_plane = skl_disable_plane;
13663 primary->get_hw_state = skl_plane_get_hw_state;
13664 } else if (INTEL_GEN(dev_priv) >= 4) {
13665 intel_primary_formats = i965_primary_formats;
13666 num_formats = ARRAY_SIZE(i965_primary_formats);
13667 modifiers = i9xx_format_modifiers;
13669 primary->update_plane = i9xx_update_plane;
13670 primary->disable_plane = i9xx_disable_plane;
13671 primary->get_hw_state = i9xx_plane_get_hw_state;
13673 intel_primary_formats = i8xx_primary_formats;
13674 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13675 modifiers = i9xx_format_modifiers;
13677 primary->update_plane = i9xx_update_plane;
13678 primary->disable_plane = i9xx_disable_plane;
13679 primary->get_hw_state = i9xx_plane_get_hw_state;
13682 if (INTEL_GEN(dev_priv) >= 9)
13683 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13684 0, &intel_plane_funcs,
13685 intel_primary_formats, num_formats,
13687 DRM_PLANE_TYPE_PRIMARY,
13688 "plane 1%c", pipe_name(pipe));
13689 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13690 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13691 0, &intel_plane_funcs,
13692 intel_primary_formats, num_formats,
13694 DRM_PLANE_TYPE_PRIMARY,
13695 "primary %c", pipe_name(pipe));
13697 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13698 0, &intel_plane_funcs,
13699 intel_primary_formats, num_formats,
13701 DRM_PLANE_TYPE_PRIMARY,
13703 plane_name(primary->i9xx_plane));
13707 if (INTEL_GEN(dev_priv) >= 10) {
13708 supported_rotations =
13709 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13710 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13711 DRM_MODE_REFLECT_X;
13712 } else if (INTEL_GEN(dev_priv) >= 9) {
13713 supported_rotations =
13714 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13715 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13716 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13717 supported_rotations =
13718 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13719 DRM_MODE_REFLECT_X;
13720 } else if (INTEL_GEN(dev_priv) >= 4) {
13721 supported_rotations =
13722 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13724 supported_rotations = DRM_MODE_ROTATE_0;
13727 if (INTEL_GEN(dev_priv) >= 4)
13728 drm_plane_create_rotation_property(&primary->base,
13730 supported_rotations);
13732 if (INTEL_GEN(dev_priv) >= 9)
13733 drm_plane_create_color_properties(&primary->base,
13734 BIT(DRM_COLOR_YCBCR_BT601) |
13735 BIT(DRM_COLOR_YCBCR_BT709),
13736 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13737 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13738 DRM_COLOR_YCBCR_BT709,
13739 DRM_COLOR_YCBCR_LIMITED_RANGE);
13741 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13749 return ERR_PTR(ret);
13752 static struct intel_plane *
13753 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13756 struct intel_plane *cursor = NULL;
13757 struct intel_plane_state *state = NULL;
13760 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13766 state = intel_create_plane_state(&cursor->base);
13772 cursor->base.state = &state->base;
13774 cursor->can_scale = false;
13775 cursor->max_downscale = 1;
13776 cursor->pipe = pipe;
13777 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13778 cursor->id = PLANE_CURSOR;
13779 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13781 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13782 cursor->update_plane = i845_update_cursor;
13783 cursor->disable_plane = i845_disable_cursor;
13784 cursor->get_hw_state = i845_cursor_get_hw_state;
13785 cursor->check_plane = i845_check_cursor;
13787 cursor->update_plane = i9xx_update_cursor;
13788 cursor->disable_plane = i9xx_disable_cursor;
13789 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13790 cursor->check_plane = i9xx_check_cursor;
13793 cursor->cursor.base = ~0;
13794 cursor->cursor.cntl = ~0;
13796 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13797 cursor->cursor.size = ~0;
13799 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13800 0, &intel_cursor_plane_funcs,
13801 intel_cursor_formats,
13802 ARRAY_SIZE(intel_cursor_formats),
13803 cursor_format_modifiers,
13804 DRM_PLANE_TYPE_CURSOR,
13805 "cursor %c", pipe_name(pipe));
13809 if (INTEL_GEN(dev_priv) >= 4)
13810 drm_plane_create_rotation_property(&cursor->base,
13812 DRM_MODE_ROTATE_0 |
13813 DRM_MODE_ROTATE_180);
13815 if (INTEL_GEN(dev_priv) >= 9)
13816 state->scaler_id = -1;
13818 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13826 return ERR_PTR(ret);
13829 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13830 struct intel_crtc_state *crtc_state)
13832 struct intel_crtc_scaler_state *scaler_state =
13833 &crtc_state->scaler_state;
13834 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13837 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13838 if (!crtc->num_scalers)
13841 for (i = 0; i < crtc->num_scalers; i++) {
13842 struct intel_scaler *scaler = &scaler_state->scalers[i];
13844 scaler->in_use = 0;
13845 scaler->mode = PS_SCALER_MODE_DYN;
13848 scaler_state->scaler_id = -1;
13851 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13853 struct intel_crtc *intel_crtc;
13854 struct intel_crtc_state *crtc_state = NULL;
13855 struct intel_plane *primary = NULL;
13856 struct intel_plane *cursor = NULL;
13859 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13863 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13868 intel_crtc->config = crtc_state;
13869 intel_crtc->base.state = &crtc_state->base;
13870 crtc_state->base.crtc = &intel_crtc->base;
13872 primary = intel_primary_plane_create(dev_priv, pipe);
13873 if (IS_ERR(primary)) {
13874 ret = PTR_ERR(primary);
13877 intel_crtc->plane_ids_mask |= BIT(primary->id);
13879 for_each_sprite(dev_priv, pipe, sprite) {
13880 struct intel_plane *plane;
13882 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13883 if (IS_ERR(plane)) {
13884 ret = PTR_ERR(plane);
13887 intel_crtc->plane_ids_mask |= BIT(plane->id);
13890 cursor = intel_cursor_plane_create(dev_priv, pipe);
13891 if (IS_ERR(cursor)) {
13892 ret = PTR_ERR(cursor);
13895 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13897 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13898 &primary->base, &cursor->base,
13900 "pipe %c", pipe_name(pipe));
13904 intel_crtc->pipe = pipe;
13906 /* initialize shared scalers */
13907 intel_crtc_init_scalers(intel_crtc, crtc_state);
13909 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
13910 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
13911 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
13913 if (INTEL_GEN(dev_priv) < 9) {
13914 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
13916 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13917 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
13918 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
13921 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13923 intel_color_init(&intel_crtc->base);
13925 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13931 * drm_mode_config_cleanup() will free up any
13932 * crtcs/planes already initialized.
13940 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13942 struct drm_device *dev = connector->base.dev;
13944 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13946 if (!connector->base.state->crtc)
13947 return INVALID_PIPE;
13949 return to_intel_crtc(connector->base.state->crtc)->pipe;
13952 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
13953 struct drm_file *file)
13955 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13956 struct drm_crtc *drmmode_crtc;
13957 struct intel_crtc *crtc;
13959 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13963 crtc = to_intel_crtc(drmmode_crtc);
13964 pipe_from_crtc_id->pipe = crtc->pipe;
13969 static int intel_encoder_clones(struct intel_encoder *encoder)
13971 struct drm_device *dev = encoder->base.dev;
13972 struct intel_encoder *source_encoder;
13973 int index_mask = 0;
13976 for_each_intel_encoder(dev, source_encoder) {
13977 if (encoders_cloneable(encoder, source_encoder))
13978 index_mask |= (1 << entry);
13986 static bool has_edp_a(struct drm_i915_private *dev_priv)
13988 if (!IS_MOBILE(dev_priv))
13991 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13994 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14000 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14002 if (INTEL_GEN(dev_priv) >= 9)
14005 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14008 if (IS_CHERRYVIEW(dev_priv))
14011 if (HAS_PCH_LPT_H(dev_priv) &&
14012 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14015 /* DDI E can't be used if DDI A requires 4 lanes */
14016 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14019 if (!dev_priv->vbt.int_crt_support)
14025 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14030 if (HAS_DDI(dev_priv))
14033 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14034 * everywhere where registers can be write protected.
14036 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14041 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14042 u32 val = I915_READ(PP_CONTROL(pps_idx));
14044 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14045 I915_WRITE(PP_CONTROL(pps_idx), val);
14049 static void intel_pps_init(struct drm_i915_private *dev_priv)
14051 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14052 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14053 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14054 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14056 dev_priv->pps_mmio_base = PPS_BASE;
14058 intel_pps_unlock_regs_wa(dev_priv);
14061 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14063 struct intel_encoder *encoder;
14064 bool dpd_is_edp = false;
14066 intel_pps_init(dev_priv);
14069 * intel_edp_init_connector() depends on this completing first, to
14070 * prevent the registeration of both eDP and LVDS and the incorrect
14071 * sharing of the PPS.
14073 intel_lvds_init(dev_priv);
14075 if (intel_crt_present(dev_priv))
14076 intel_crt_init(dev_priv);
14078 if (IS_ICELAKE(dev_priv)) {
14079 intel_ddi_init(dev_priv, PORT_A);
14080 intel_ddi_init(dev_priv, PORT_B);
14081 intel_ddi_init(dev_priv, PORT_C);
14082 intel_ddi_init(dev_priv, PORT_D);
14083 intel_ddi_init(dev_priv, PORT_E);
14084 intel_ddi_init(dev_priv, PORT_F);
14085 } else if (IS_GEN9_LP(dev_priv)) {
14087 * FIXME: Broxton doesn't support port detection via the
14088 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14089 * detect the ports.
14091 intel_ddi_init(dev_priv, PORT_A);
14092 intel_ddi_init(dev_priv, PORT_B);
14093 intel_ddi_init(dev_priv, PORT_C);
14095 vlv_dsi_init(dev_priv);
14096 } else if (HAS_DDI(dev_priv)) {
14100 * Haswell uses DDI functions to detect digital outputs.
14101 * On SKL pre-D0 the strap isn't connected, so we assume
14104 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14105 /* WaIgnoreDDIAStrap: skl */
14106 if (found || IS_GEN9_BC(dev_priv))
14107 intel_ddi_init(dev_priv, PORT_A);
14109 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14111 found = I915_READ(SFUSE_STRAP);
14113 if (found & SFUSE_STRAP_DDIB_DETECTED)
14114 intel_ddi_init(dev_priv, PORT_B);
14115 if (found & SFUSE_STRAP_DDIC_DETECTED)
14116 intel_ddi_init(dev_priv, PORT_C);
14117 if (found & SFUSE_STRAP_DDID_DETECTED)
14118 intel_ddi_init(dev_priv, PORT_D);
14119 if (found & SFUSE_STRAP_DDIF_DETECTED)
14120 intel_ddi_init(dev_priv, PORT_F);
14122 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14124 if (IS_GEN9_BC(dev_priv) &&
14125 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14126 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14127 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14128 intel_ddi_init(dev_priv, PORT_E);
14130 } else if (HAS_PCH_SPLIT(dev_priv)) {
14132 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14134 if (has_edp_a(dev_priv))
14135 intel_dp_init(dev_priv, DP_A, PORT_A);
14137 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14138 /* PCH SDVOB multiplex with HDMIB */
14139 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14141 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14142 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14143 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14146 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14147 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14149 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14150 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14152 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14153 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14155 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14156 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14157 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14158 bool has_edp, has_port;
14161 * The DP_DETECTED bit is the latched state of the DDC
14162 * SDA pin at boot. However since eDP doesn't require DDC
14163 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14164 * eDP ports may have been muxed to an alternate function.
14165 * Thus we can't rely on the DP_DETECTED bit alone to detect
14166 * eDP ports. Consult the VBT as well as DP_DETECTED to
14167 * detect eDP ports.
14169 * Sadly the straps seem to be missing sometimes even for HDMI
14170 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14171 * and VBT for the presence of the port. Additionally we can't
14172 * trust the port type the VBT declares as we've seen at least
14173 * HDMI ports that the VBT claim are DP or eDP.
14175 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14176 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14177 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14178 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14179 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14180 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14182 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14183 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14184 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14185 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14186 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14187 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14189 if (IS_CHERRYVIEW(dev_priv)) {
14191 * eDP not supported on port D,
14192 * so no need to worry about it
14194 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14195 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14196 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14197 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14198 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14201 vlv_dsi_init(dev_priv);
14202 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14203 bool found = false;
14205 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14206 DRM_DEBUG_KMS("probing SDVOB\n");
14207 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14208 if (!found && IS_G4X(dev_priv)) {
14209 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14210 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14213 if (!found && IS_G4X(dev_priv))
14214 intel_dp_init(dev_priv, DP_B, PORT_B);
14217 /* Before G4X SDVOC doesn't have its own detect register */
14219 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14220 DRM_DEBUG_KMS("probing SDVOC\n");
14221 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14224 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14226 if (IS_G4X(dev_priv)) {
14227 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14228 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14230 if (IS_G4X(dev_priv))
14231 intel_dp_init(dev_priv, DP_C, PORT_C);
14234 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14235 intel_dp_init(dev_priv, DP_D, PORT_D);
14236 } else if (IS_GEN2(dev_priv))
14237 intel_dvo_init(dev_priv);
14239 if (SUPPORTS_TV(dev_priv))
14240 intel_tv_init(dev_priv);
14242 intel_psr_init(dev_priv);
14244 for_each_intel_encoder(&dev_priv->drm, encoder) {
14245 encoder->base.possible_crtcs = encoder->crtc_mask;
14246 encoder->base.possible_clones =
14247 intel_encoder_clones(encoder);
14250 intel_init_pch_refclk(dev_priv);
14252 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14255 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14257 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14258 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14260 drm_framebuffer_cleanup(fb);
14262 i915_gem_object_lock(obj);
14263 WARN_ON(!obj->framebuffer_references--);
14264 i915_gem_object_unlock(obj);
14266 i915_gem_object_put(obj);
14271 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14272 struct drm_file *file,
14273 unsigned int *handle)
14275 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14277 if (obj->userptr.mm) {
14278 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14282 return drm_gem_handle_create(file, &obj->base, handle);
14285 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14286 struct drm_file *file,
14287 unsigned flags, unsigned color,
14288 struct drm_clip_rect *clips,
14289 unsigned num_clips)
14291 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14293 i915_gem_object_flush_if_display(obj);
14294 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14299 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14300 .destroy = intel_user_framebuffer_destroy,
14301 .create_handle = intel_user_framebuffer_create_handle,
14302 .dirty = intel_user_framebuffer_dirty,
14306 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14307 uint64_t fb_modifier, uint32_t pixel_format)
14309 u32 gen = INTEL_GEN(dev_priv);
14312 int cpp = drm_format_plane_cpp(pixel_format, 0);
14314 /* "The stride in bytes must not exceed the of the size of 8K
14315 * pixels and 32K bytes."
14317 return min(8192 * cpp, 32768);
14318 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14320 } else if (gen >= 4) {
14321 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14325 } else if (gen >= 3) {
14326 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14331 /* XXX DSPC is limited to 4k tiled */
14336 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14337 struct drm_i915_gem_object *obj,
14338 struct drm_mode_fb_cmd2 *mode_cmd)
14340 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14341 struct drm_framebuffer *fb = &intel_fb->base;
14342 struct drm_format_name_buf format_name;
14344 unsigned int tiling, stride;
14348 i915_gem_object_lock(obj);
14349 obj->framebuffer_references++;
14350 tiling = i915_gem_object_get_tiling(obj);
14351 stride = i915_gem_object_get_stride(obj);
14352 i915_gem_object_unlock(obj);
14354 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14356 * If there's a fence, enforce that
14357 * the fb modifier and tiling mode match.
14359 if (tiling != I915_TILING_NONE &&
14360 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14361 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14365 if (tiling == I915_TILING_X) {
14366 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14367 } else if (tiling == I915_TILING_Y) {
14368 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14373 /* Passed in modifier sanity checking. */
14374 switch (mode_cmd->modifier[0]) {
14375 case I915_FORMAT_MOD_Y_TILED_CCS:
14376 case I915_FORMAT_MOD_Yf_TILED_CCS:
14377 switch (mode_cmd->pixel_format) {
14378 case DRM_FORMAT_XBGR8888:
14379 case DRM_FORMAT_ABGR8888:
14380 case DRM_FORMAT_XRGB8888:
14381 case DRM_FORMAT_ARGB8888:
14384 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14388 case I915_FORMAT_MOD_Y_TILED:
14389 case I915_FORMAT_MOD_Yf_TILED:
14390 if (INTEL_GEN(dev_priv) < 9) {
14391 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14392 mode_cmd->modifier[0]);
14395 case DRM_FORMAT_MOD_LINEAR:
14396 case I915_FORMAT_MOD_X_TILED:
14399 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14400 mode_cmd->modifier[0]);
14405 * gen2/3 display engine uses the fence if present,
14406 * so the tiling mode must match the fb modifier exactly.
14408 if (INTEL_GEN(dev_priv) < 4 &&
14409 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14410 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14414 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14415 mode_cmd->pixel_format);
14416 if (mode_cmd->pitches[0] > pitch_limit) {
14417 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14418 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14419 "tiled" : "linear",
14420 mode_cmd->pitches[0], pitch_limit);
14425 * If there's a fence, enforce that
14426 * the fb pitch and fence stride match.
14428 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14429 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14430 mode_cmd->pitches[0], stride);
14434 /* Reject formats not supported by any plane early. */
14435 switch (mode_cmd->pixel_format) {
14436 case DRM_FORMAT_C8:
14437 case DRM_FORMAT_RGB565:
14438 case DRM_FORMAT_XRGB8888:
14439 case DRM_FORMAT_ARGB8888:
14441 case DRM_FORMAT_XRGB1555:
14442 if (INTEL_GEN(dev_priv) > 3) {
14443 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14444 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14448 case DRM_FORMAT_ABGR8888:
14449 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14450 INTEL_GEN(dev_priv) < 9) {
14451 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14452 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14456 case DRM_FORMAT_XBGR8888:
14457 case DRM_FORMAT_XRGB2101010:
14458 case DRM_FORMAT_XBGR2101010:
14459 if (INTEL_GEN(dev_priv) < 4) {
14460 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14461 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14465 case DRM_FORMAT_ABGR2101010:
14466 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14467 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14468 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14472 case DRM_FORMAT_YUYV:
14473 case DRM_FORMAT_UYVY:
14474 case DRM_FORMAT_YVYU:
14475 case DRM_FORMAT_VYUY:
14476 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14477 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14478 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14482 case DRM_FORMAT_NV12:
14483 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14484 IS_BROXTON(dev_priv)) {
14485 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14486 drm_get_format_name(mode_cmd->pixel_format,
14492 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14493 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14497 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14498 if (mode_cmd->offsets[0] != 0)
14501 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14503 if (fb->format->format == DRM_FORMAT_NV12 &&
14504 (fb->width < SKL_MIN_YUV_420_SRC_W ||
14505 fb->height < SKL_MIN_YUV_420_SRC_H ||
14506 (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14507 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14511 for (i = 0; i < fb->format->num_planes; i++) {
14512 u32 stride_alignment;
14514 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14515 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14519 stride_alignment = intel_fb_stride_alignment(fb, i);
14522 * Display WA #0531: skl,bxt,kbl,glk
14524 * Render decompression and plane width > 3840
14525 * combined with horizontal panning requires the
14526 * plane stride to be a multiple of 4. We'll just
14527 * require the entire fb to accommodate that to avoid
14528 * potential runtime errors at plane configuration time.
14530 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14531 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14532 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14533 stride_alignment *= 4;
14535 if (fb->pitches[i] & (stride_alignment - 1)) {
14536 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14537 i, fb->pitches[i], stride_alignment);
14541 fb->obj[i] = &obj->base;
14544 ret = intel_fill_fb_info(dev_priv, fb);
14548 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14550 DRM_ERROR("framebuffer init failed %d\n", ret);
14557 i915_gem_object_lock(obj);
14558 obj->framebuffer_references--;
14559 i915_gem_object_unlock(obj);
14563 static struct drm_framebuffer *
14564 intel_user_framebuffer_create(struct drm_device *dev,
14565 struct drm_file *filp,
14566 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14568 struct drm_framebuffer *fb;
14569 struct drm_i915_gem_object *obj;
14570 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14572 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14574 return ERR_PTR(-ENOENT);
14576 fb = intel_framebuffer_create(obj, &mode_cmd);
14578 i915_gem_object_put(obj);
14583 static void intel_atomic_state_free(struct drm_atomic_state *state)
14585 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14587 drm_atomic_state_default_release(state);
14589 i915_sw_fence_fini(&intel_state->commit_ready);
14594 static enum drm_mode_status
14595 intel_mode_valid(struct drm_device *dev,
14596 const struct drm_display_mode *mode)
14598 struct drm_i915_private *dev_priv = to_i915(dev);
14599 int hdisplay_max, htotal_max;
14600 int vdisplay_max, vtotal_max;
14603 * Can't reject DBLSCAN here because Xorg ddxen can add piles
14604 * of DBLSCAN modes to the output's mode list when they detect
14605 * the scaling mode property on the connector. And they don't
14606 * ask the kernel to validate those modes in any way until
14607 * modeset time at which point the client gets a protocol error.
14608 * So in order to not upset those clients we silently ignore the
14609 * DBLSCAN flag on such connectors. For other connectors we will
14610 * reject modes with the DBLSCAN flag in encoder->compute_config().
14611 * And we always reject DBLSCAN modes in connector->mode_valid()
14612 * as we never want such modes on the connector's mode list.
14615 if (mode->vscan > 1)
14616 return MODE_NO_VSCAN;
14618 if (mode->flags & DRM_MODE_FLAG_HSKEW)
14619 return MODE_H_ILLEGAL;
14621 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14622 DRM_MODE_FLAG_NCSYNC |
14623 DRM_MODE_FLAG_PCSYNC))
14626 if (mode->flags & (DRM_MODE_FLAG_BCAST |
14627 DRM_MODE_FLAG_PIXMUX |
14628 DRM_MODE_FLAG_CLKDIV2))
14631 if (INTEL_GEN(dev_priv) >= 9 ||
14632 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
14633 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
14634 vdisplay_max = 4096;
14637 } else if (INTEL_GEN(dev_priv) >= 3) {
14638 hdisplay_max = 4096;
14639 vdisplay_max = 4096;
14643 hdisplay_max = 2048;
14644 vdisplay_max = 2048;
14649 if (mode->hdisplay > hdisplay_max ||
14650 mode->hsync_start > htotal_max ||
14651 mode->hsync_end > htotal_max ||
14652 mode->htotal > htotal_max)
14653 return MODE_H_ILLEGAL;
14655 if (mode->vdisplay > vdisplay_max ||
14656 mode->vsync_start > vtotal_max ||
14657 mode->vsync_end > vtotal_max ||
14658 mode->vtotal > vtotal_max)
14659 return MODE_V_ILLEGAL;
14664 static const struct drm_mode_config_funcs intel_mode_funcs = {
14665 .fb_create = intel_user_framebuffer_create,
14666 .get_format_info = intel_get_format_info,
14667 .output_poll_changed = intel_fbdev_output_poll_changed,
14668 .mode_valid = intel_mode_valid,
14669 .atomic_check = intel_atomic_check,
14670 .atomic_commit = intel_atomic_commit,
14671 .atomic_state_alloc = intel_atomic_state_alloc,
14672 .atomic_state_clear = intel_atomic_state_clear,
14673 .atomic_state_free = intel_atomic_state_free,
14677 * intel_init_display_hooks - initialize the display modesetting hooks
14678 * @dev_priv: device private
14680 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14682 intel_init_cdclk_hooks(dev_priv);
14684 if (INTEL_GEN(dev_priv) >= 9) {
14685 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14686 dev_priv->display.get_initial_plane_config =
14687 skylake_get_initial_plane_config;
14688 dev_priv->display.crtc_compute_clock =
14689 haswell_crtc_compute_clock;
14690 dev_priv->display.crtc_enable = haswell_crtc_enable;
14691 dev_priv->display.crtc_disable = haswell_crtc_disable;
14692 } else if (HAS_DDI(dev_priv)) {
14693 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14694 dev_priv->display.get_initial_plane_config =
14695 i9xx_get_initial_plane_config;
14696 dev_priv->display.crtc_compute_clock =
14697 haswell_crtc_compute_clock;
14698 dev_priv->display.crtc_enable = haswell_crtc_enable;
14699 dev_priv->display.crtc_disable = haswell_crtc_disable;
14700 } else if (HAS_PCH_SPLIT(dev_priv)) {
14701 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14702 dev_priv->display.get_initial_plane_config =
14703 i9xx_get_initial_plane_config;
14704 dev_priv->display.crtc_compute_clock =
14705 ironlake_crtc_compute_clock;
14706 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14707 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14708 } else if (IS_CHERRYVIEW(dev_priv)) {
14709 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14710 dev_priv->display.get_initial_plane_config =
14711 i9xx_get_initial_plane_config;
14712 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14713 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14714 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14715 } else if (IS_VALLEYVIEW(dev_priv)) {
14716 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14717 dev_priv->display.get_initial_plane_config =
14718 i9xx_get_initial_plane_config;
14719 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14720 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14721 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14722 } else if (IS_G4X(dev_priv)) {
14723 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14724 dev_priv->display.get_initial_plane_config =
14725 i9xx_get_initial_plane_config;
14726 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14727 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14728 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14729 } else if (IS_PINEVIEW(dev_priv)) {
14730 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14731 dev_priv->display.get_initial_plane_config =
14732 i9xx_get_initial_plane_config;
14733 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14734 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14735 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14736 } else if (!IS_GEN2(dev_priv)) {
14737 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14738 dev_priv->display.get_initial_plane_config =
14739 i9xx_get_initial_plane_config;
14740 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14741 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14742 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14744 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14745 dev_priv->display.get_initial_plane_config =
14746 i9xx_get_initial_plane_config;
14747 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14748 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14749 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14752 if (IS_GEN5(dev_priv)) {
14753 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14754 } else if (IS_GEN6(dev_priv)) {
14755 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14756 } else if (IS_IVYBRIDGE(dev_priv)) {
14757 /* FIXME: detect B0+ stepping and use auto training */
14758 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14759 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14760 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14763 if (INTEL_GEN(dev_priv) >= 9)
14764 dev_priv->display.update_crtcs = skl_update_crtcs;
14766 dev_priv->display.update_crtcs = intel_update_crtcs;
14770 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14772 static void quirk_ssc_force_disable(struct drm_device *dev)
14774 struct drm_i915_private *dev_priv = to_i915(dev);
14775 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14776 DRM_INFO("applying lvds SSC disable quirk\n");
14780 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14783 static void quirk_invert_brightness(struct drm_device *dev)
14785 struct drm_i915_private *dev_priv = to_i915(dev);
14786 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14787 DRM_INFO("applying inverted panel brightness quirk\n");
14790 /* Some VBT's incorrectly indicate no backlight is present */
14791 static void quirk_backlight_present(struct drm_device *dev)
14793 struct drm_i915_private *dev_priv = to_i915(dev);
14794 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14795 DRM_INFO("applying backlight present quirk\n");
14798 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14799 * which is 300 ms greater than eDP spec T12 min.
14801 static void quirk_increase_t12_delay(struct drm_device *dev)
14803 struct drm_i915_private *dev_priv = to_i915(dev);
14805 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14806 DRM_INFO("Applying T12 delay quirk\n");
14809 struct intel_quirk {
14811 int subsystem_vendor;
14812 int subsystem_device;
14813 void (*hook)(struct drm_device *dev);
14816 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14817 struct intel_dmi_quirk {
14818 void (*hook)(struct drm_device *dev);
14819 const struct dmi_system_id (*dmi_id_list)[];
14822 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14824 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14828 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14830 .dmi_id_list = &(const struct dmi_system_id[]) {
14832 .callback = intel_dmi_reverse_brightness,
14833 .ident = "NCR Corporation",
14834 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14835 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14838 { } /* terminating entry */
14840 .hook = quirk_invert_brightness,
14844 static struct intel_quirk intel_quirks[] = {
14845 /* Lenovo U160 cannot use SSC on LVDS */
14846 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14848 /* Sony Vaio Y cannot use SSC on LVDS */
14849 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14851 /* Acer Aspire 5734Z must invert backlight brightness */
14852 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14854 /* Acer/eMachines G725 */
14855 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14857 /* Acer/eMachines e725 */
14858 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14860 /* Acer/Packard Bell NCL20 */
14861 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14863 /* Acer Aspire 4736Z */
14864 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14866 /* Acer Aspire 5336 */
14867 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14869 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14870 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14872 /* Acer C720 Chromebook (Core i3 4005U) */
14873 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14875 /* Apple Macbook 2,1 (Core 2 T7400) */
14876 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14878 /* Apple Macbook 4,1 */
14879 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14881 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14882 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14884 /* HP Chromebook 14 (Celeron 2955U) */
14885 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14887 /* Dell Chromebook 11 */
14888 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14890 /* Dell Chromebook 11 (2015 version) */
14891 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14893 /* Toshiba Satellite P50-C-18C */
14894 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14897 static void intel_init_quirks(struct drm_device *dev)
14899 struct pci_dev *d = dev->pdev;
14902 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14903 struct intel_quirk *q = &intel_quirks[i];
14905 if (d->device == q->device &&
14906 (d->subsystem_vendor == q->subsystem_vendor ||
14907 q->subsystem_vendor == PCI_ANY_ID) &&
14908 (d->subsystem_device == q->subsystem_device ||
14909 q->subsystem_device == PCI_ANY_ID))
14912 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14913 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14914 intel_dmi_quirks[i].hook(dev);
14918 /* Disable the VGA plane that we never use */
14919 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14921 struct pci_dev *pdev = dev_priv->drm.pdev;
14923 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14925 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14926 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14927 outb(SR01, VGA_SR_INDEX);
14928 sr1 = inb(VGA_SR_DATA);
14929 outb(sr1 | 1<<5, VGA_SR_DATA);
14930 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14933 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14934 POSTING_READ(vga_reg);
14937 void intel_modeset_init_hw(struct drm_device *dev)
14939 struct drm_i915_private *dev_priv = to_i915(dev);
14941 intel_update_cdclk(dev_priv);
14942 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14943 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14947 * Calculate what we think the watermarks should be for the state we've read
14948 * out of the hardware and then immediately program those watermarks so that
14949 * we ensure the hardware settings match our internal state.
14951 * We can calculate what we think WM's should be by creating a duplicate of the
14952 * current state (which was constructed during hardware readout) and running it
14953 * through the atomic check code to calculate new watermark values in the
14956 static void sanitize_watermarks(struct drm_device *dev)
14958 struct drm_i915_private *dev_priv = to_i915(dev);
14959 struct drm_atomic_state *state;
14960 struct intel_atomic_state *intel_state;
14961 struct drm_crtc *crtc;
14962 struct drm_crtc_state *cstate;
14963 struct drm_modeset_acquire_ctx ctx;
14967 /* Only supported on platforms that use atomic watermark design */
14968 if (!dev_priv->display.optimize_watermarks)
14972 * We need to hold connection_mutex before calling duplicate_state so
14973 * that the connector loop is protected.
14975 drm_modeset_acquire_init(&ctx, 0);
14977 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14978 if (ret == -EDEADLK) {
14979 drm_modeset_backoff(&ctx);
14981 } else if (WARN_ON(ret)) {
14985 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14986 if (WARN_ON(IS_ERR(state)))
14989 intel_state = to_intel_atomic_state(state);
14992 * Hardware readout is the only time we don't want to calculate
14993 * intermediate watermarks (since we don't trust the current
14996 if (!HAS_GMCH_DISPLAY(dev_priv))
14997 intel_state->skip_intermediate_wm = true;
14999 ret = intel_atomic_check(dev, state);
15002 * If we fail here, it means that the hardware appears to be
15003 * programmed in a way that shouldn't be possible, given our
15004 * understanding of watermark requirements. This might mean a
15005 * mistake in the hardware readout code or a mistake in the
15006 * watermark calculations for a given platform. Raise a WARN
15007 * so that this is noticeable.
15009 * If this actually happens, we'll have to just leave the
15010 * BIOS-programmed watermarks untouched and hope for the best.
15012 WARN(true, "Could not determine valid watermarks for inherited state\n");
15016 /* Write calculated watermark values back */
15017 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15018 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15020 cs->wm.need_postvbl_update = true;
15021 dev_priv->display.optimize_watermarks(intel_state, cs);
15023 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15027 drm_atomic_state_put(state);
15029 drm_modeset_drop_locks(&ctx);
15030 drm_modeset_acquire_fini(&ctx);
15033 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15035 if (IS_GEN5(dev_priv)) {
15037 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15039 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15040 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
15041 dev_priv->fdi_pll_freq = 270000;
15046 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15049 int intel_modeset_init(struct drm_device *dev)
15051 struct drm_i915_private *dev_priv = to_i915(dev);
15052 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15054 struct intel_crtc *crtc;
15056 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15058 drm_mode_config_init(dev);
15060 dev->mode_config.min_width = 0;
15061 dev->mode_config.min_height = 0;
15063 dev->mode_config.preferred_depth = 24;
15064 dev->mode_config.prefer_shadow = 1;
15066 dev->mode_config.allow_fb_modifiers = true;
15068 dev->mode_config.funcs = &intel_mode_funcs;
15070 init_llist_head(&dev_priv->atomic_helper.free_list);
15071 INIT_WORK(&dev_priv->atomic_helper.free_work,
15072 intel_atomic_helper_free_state_worker);
15074 intel_init_quirks(dev);
15076 intel_init_pm(dev_priv);
15078 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15082 * There may be no VBT; and if the BIOS enabled SSC we can
15083 * just keep using it to avoid unnecessary flicker. Whereas if the
15084 * BIOS isn't using it, don't assume it will work even if the VBT
15085 * indicates as much.
15087 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15088 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15091 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15092 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15093 bios_lvds_use_ssc ? "en" : "dis",
15094 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15095 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15099 /* maximum framebuffer dimensions */
15100 if (IS_GEN2(dev_priv)) {
15101 dev->mode_config.max_width = 2048;
15102 dev->mode_config.max_height = 2048;
15103 } else if (IS_GEN3(dev_priv)) {
15104 dev->mode_config.max_width = 4096;
15105 dev->mode_config.max_height = 4096;
15107 dev->mode_config.max_width = 8192;
15108 dev->mode_config.max_height = 8192;
15111 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15112 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15113 dev->mode_config.cursor_height = 1023;
15114 } else if (IS_GEN2(dev_priv)) {
15115 dev->mode_config.cursor_width = 64;
15116 dev->mode_config.cursor_height = 64;
15118 dev->mode_config.cursor_width = 256;
15119 dev->mode_config.cursor_height = 256;
15122 dev->mode_config.fb_base = ggtt->gmadr.start;
15124 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15125 INTEL_INFO(dev_priv)->num_pipes,
15126 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15128 for_each_pipe(dev_priv, pipe) {
15131 ret = intel_crtc_init(dev_priv, pipe);
15133 drm_mode_config_cleanup(dev);
15138 intel_shared_dpll_init(dev);
15139 intel_update_fdi_pll_freq(dev_priv);
15141 intel_update_czclk(dev_priv);
15142 intel_modeset_init_hw(dev);
15144 if (dev_priv->max_cdclk_freq == 0)
15145 intel_update_max_cdclk(dev_priv);
15147 /* Just disable it once at startup */
15148 i915_disable_vga(dev_priv);
15149 intel_setup_outputs(dev_priv);
15151 drm_modeset_lock_all(dev);
15152 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15153 drm_modeset_unlock_all(dev);
15155 for_each_intel_crtc(dev, crtc) {
15156 struct intel_initial_plane_config plane_config = {};
15162 * Note that reserving the BIOS fb up front prevents us
15163 * from stuffing other stolen allocations like the ring
15164 * on top. This prevents some ugliness at boot time, and
15165 * can even allow for smooth boot transitions if the BIOS
15166 * fb is large enough for the active pipe configuration.
15168 dev_priv->display.get_initial_plane_config(crtc,
15172 * If the fb is shared between multiple heads, we'll
15173 * just get the first one.
15175 intel_find_initial_plane_obj(crtc, &plane_config);
15179 * Make sure hardware watermarks really match the state we read out.
15180 * Note that we need to do this after reconstructing the BIOS fb's
15181 * since the watermark calculation done here will use pstate->fb.
15183 if (!HAS_GMCH_DISPLAY(dev_priv))
15184 sanitize_watermarks(dev);
15189 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15191 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15192 /* 640x480@60Hz, ~25175 kHz */
15193 struct dpll clock = {
15203 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15205 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15206 pipe_name(pipe), clock.vco, clock.dot);
15208 fp = i9xx_dpll_compute_fp(&clock);
15209 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15210 DPLL_VGA_MODE_DIS |
15211 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15212 PLL_P2_DIVIDE_BY_4 |
15213 PLL_REF_INPUT_DREFCLK |
15216 I915_WRITE(FP0(pipe), fp);
15217 I915_WRITE(FP1(pipe), fp);
15219 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15220 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15221 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15222 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15223 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15224 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15225 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15228 * Apparently we need to have VGA mode enabled prior to changing
15229 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15230 * dividers, even though the register value does change.
15232 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15233 I915_WRITE(DPLL(pipe), dpll);
15235 /* Wait for the clocks to stabilize. */
15236 POSTING_READ(DPLL(pipe));
15239 /* The pixel multiplier can only be updated once the
15240 * DPLL is enabled and the clocks are stable.
15242 * So write it again.
15244 I915_WRITE(DPLL(pipe), dpll);
15246 /* We do this three times for luck */
15247 for (i = 0; i < 3 ; i++) {
15248 I915_WRITE(DPLL(pipe), dpll);
15249 POSTING_READ(DPLL(pipe));
15250 udelay(150); /* wait for warmup */
15253 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15254 POSTING_READ(PIPECONF(pipe));
15256 intel_wait_for_pipe_scanline_moving(crtc);
15259 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15261 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15263 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15266 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15267 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15268 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15269 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15270 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15272 I915_WRITE(PIPECONF(pipe), 0);
15273 POSTING_READ(PIPECONF(pipe));
15275 intel_wait_for_pipe_scanline_stopped(crtc);
15277 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15278 POSTING_READ(DPLL(pipe));
15281 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
15282 struct intel_plane *plane)
15286 if (!plane->get_hw_state(plane, &pipe))
15289 return pipe == crtc->pipe;
15293 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15295 struct intel_crtc *crtc;
15297 if (INTEL_GEN(dev_priv) >= 4)
15300 for_each_intel_crtc(&dev_priv->drm, crtc) {
15301 struct intel_plane *plane =
15302 to_intel_plane(crtc->base.primary);
15304 if (intel_plane_mapping_ok(crtc, plane))
15307 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15309 intel_plane_disable_noatomic(crtc, plane);
15313 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15315 struct drm_device *dev = crtc->base.dev;
15316 struct intel_encoder *encoder;
15318 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15324 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15326 struct drm_device *dev = encoder->base.dev;
15327 struct intel_connector *connector;
15329 for_each_connector_on_encoder(dev, &encoder->base, connector)
15335 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15336 enum pipe pch_transcoder)
15338 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15339 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15342 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15343 struct drm_modeset_acquire_ctx *ctx)
15345 struct drm_device *dev = crtc->base.dev;
15346 struct drm_i915_private *dev_priv = to_i915(dev);
15347 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15349 /* Clear any frame start delays used for debugging left by the BIOS */
15350 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15351 i915_reg_t reg = PIPECONF(cpu_transcoder);
15354 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15357 /* restore vblank interrupts to correct state */
15358 drm_crtc_vblank_reset(&crtc->base);
15359 if (crtc->active) {
15360 struct intel_plane *plane;
15362 drm_crtc_vblank_on(&crtc->base);
15364 /* Disable everything but the primary plane */
15365 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15366 const struct intel_plane_state *plane_state =
15367 to_intel_plane_state(plane->base.state);
15369 if (plane_state->base.visible &&
15370 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15371 intel_plane_disable_noatomic(crtc, plane);
15375 /* Adjust the state of the output pipe according to whether we
15376 * have active connectors/encoders. */
15377 if (crtc->active && !intel_crtc_has_encoders(crtc))
15378 intel_crtc_disable_noatomic(&crtc->base, ctx);
15380 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15382 * We start out with underrun reporting disabled to avoid races.
15383 * For correct bookkeeping mark this on active crtcs.
15385 * Also on gmch platforms we dont have any hardware bits to
15386 * disable the underrun reporting. Which means we need to start
15387 * out with underrun reporting disabled also on inactive pipes,
15388 * since otherwise we'll complain about the garbage we read when
15389 * e.g. coming up after runtime pm.
15391 * No protection against concurrent access is required - at
15392 * worst a fifo underrun happens which also sets this to false.
15394 crtc->cpu_fifo_underrun_disabled = true;
15396 * We track the PCH trancoder underrun reporting state
15397 * within the crtc. With crtc for pipe A housing the underrun
15398 * reporting state for PCH transcoder A, crtc for pipe B housing
15399 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15400 * and marking underrun reporting as disabled for the non-existing
15401 * PCH transcoders B and C would prevent enabling the south
15402 * error interrupt (see cpt_can_enable_serr_int()).
15404 if (has_pch_trancoder(dev_priv, crtc->pipe))
15405 crtc->pch_fifo_underrun_disabled = true;
15409 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15411 struct intel_connector *connector;
15413 /* We need to check both for a crtc link (meaning that the
15414 * encoder is active and trying to read from a pipe) and the
15415 * pipe itself being active. */
15416 bool has_active_crtc = encoder->base.crtc &&
15417 to_intel_crtc(encoder->base.crtc)->active;
15419 connector = intel_encoder_find_connector(encoder);
15420 if (connector && !has_active_crtc) {
15421 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15422 encoder->base.base.id,
15423 encoder->base.name);
15425 /* Connector is active, but has no active pipe. This is
15426 * fallout from our resume register restoring. Disable
15427 * the encoder manually again. */
15428 if (encoder->base.crtc) {
15429 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15431 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15432 encoder->base.base.id,
15433 encoder->base.name);
15434 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15435 if (encoder->post_disable)
15436 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15438 encoder->base.crtc = NULL;
15440 /* Inconsistent output/port/pipe state happens presumably due to
15441 * a bug in one of the get_hw_state functions. Or someplace else
15442 * in our code, like the register restore mess on resume. Clamp
15443 * things to off as a safer default. */
15445 connector->base.dpms = DRM_MODE_DPMS_OFF;
15446 connector->base.encoder = NULL;
15449 /* notify opregion of the sanitized encoder state */
15450 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15453 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15455 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15457 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15458 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15459 i915_disable_vga(dev_priv);
15463 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15465 /* This function can be called both from intel_modeset_setup_hw_state or
15466 * at a very early point in our resume sequence, where the power well
15467 * structures are not yet restored. Since this function is at a very
15468 * paranoid "someone might have enabled VGA while we were not looking"
15469 * level, just check if the power well is enabled instead of trying to
15470 * follow the "don't touch the power well if we don't need it" policy
15471 * the rest of the driver uses. */
15472 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15475 i915_redisable_vga_power_on(dev_priv);
15477 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15480 /* FIXME read out full plane state for all planes */
15481 static void readout_plane_state(struct intel_crtc *crtc)
15483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15484 struct intel_crtc_state *crtc_state =
15485 to_intel_crtc_state(crtc->base.state);
15486 struct intel_plane *plane;
15488 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15489 struct intel_plane_state *plane_state =
15490 to_intel_plane_state(plane->base.state);
15494 visible = plane->get_hw_state(plane, &pipe);
15496 intel_set_plane_visible(crtc_state, plane_state, visible);
15500 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15502 struct drm_i915_private *dev_priv = to_i915(dev);
15504 struct intel_crtc *crtc;
15505 struct intel_encoder *encoder;
15506 struct intel_connector *connector;
15507 struct drm_connector_list_iter conn_iter;
15510 dev_priv->active_crtcs = 0;
15512 for_each_intel_crtc(dev, crtc) {
15513 struct intel_crtc_state *crtc_state =
15514 to_intel_crtc_state(crtc->base.state);
15516 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15517 memset(crtc_state, 0, sizeof(*crtc_state));
15518 crtc_state->base.crtc = &crtc->base;
15520 crtc_state->base.active = crtc_state->base.enable =
15521 dev_priv->display.get_pipe_config(crtc, crtc_state);
15523 crtc->base.enabled = crtc_state->base.enable;
15524 crtc->active = crtc_state->base.active;
15526 if (crtc_state->base.active)
15527 dev_priv->active_crtcs |= 1 << crtc->pipe;
15529 readout_plane_state(crtc);
15531 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15532 crtc->base.base.id, crtc->base.name,
15533 enableddisabled(crtc_state->base.active));
15536 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15537 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15539 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15540 &pll->state.hw_state);
15541 pll->state.crtc_mask = 0;
15542 for_each_intel_crtc(dev, crtc) {
15543 struct intel_crtc_state *crtc_state =
15544 to_intel_crtc_state(crtc->base.state);
15546 if (crtc_state->base.active &&
15547 crtc_state->shared_dpll == pll)
15548 pll->state.crtc_mask |= 1 << crtc->pipe;
15550 pll->active_mask = pll->state.crtc_mask;
15552 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15553 pll->info->name, pll->state.crtc_mask, pll->on);
15556 for_each_intel_encoder(dev, encoder) {
15559 if (encoder->get_hw_state(encoder, &pipe)) {
15560 struct intel_crtc_state *crtc_state;
15562 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15563 crtc_state = to_intel_crtc_state(crtc->base.state);
15565 encoder->base.crtc = &crtc->base;
15566 encoder->get_config(encoder, crtc_state);
15568 encoder->base.crtc = NULL;
15571 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15572 encoder->base.base.id, encoder->base.name,
15573 enableddisabled(encoder->base.crtc),
15577 drm_connector_list_iter_begin(dev, &conn_iter);
15578 for_each_intel_connector_iter(connector, &conn_iter) {
15579 if (connector->get_hw_state(connector)) {
15580 connector->base.dpms = DRM_MODE_DPMS_ON;
15582 encoder = connector->encoder;
15583 connector->base.encoder = &encoder->base;
15585 if (encoder->base.crtc &&
15586 encoder->base.crtc->state->active) {
15588 * This has to be done during hardware readout
15589 * because anything calling .crtc_disable may
15590 * rely on the connector_mask being accurate.
15592 encoder->base.crtc->state->connector_mask |=
15593 1 << drm_connector_index(&connector->base);
15594 encoder->base.crtc->state->encoder_mask |=
15595 1 << drm_encoder_index(&encoder->base);
15599 connector->base.dpms = DRM_MODE_DPMS_OFF;
15600 connector->base.encoder = NULL;
15602 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15603 connector->base.base.id, connector->base.name,
15604 enableddisabled(connector->base.encoder));
15606 drm_connector_list_iter_end(&conn_iter);
15608 for_each_intel_crtc(dev, crtc) {
15609 struct intel_crtc_state *crtc_state =
15610 to_intel_crtc_state(crtc->base.state);
15613 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15614 if (crtc_state->base.active) {
15615 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15616 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15617 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15618 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15619 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15622 * The initial mode needs to be set in order to keep
15623 * the atomic core happy. It wants a valid mode if the
15624 * crtc's enabled, so we do the above call.
15626 * But we don't set all the derived state fully, hence
15627 * set a flag to indicate that a full recalculation is
15628 * needed on the next commit.
15630 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15632 intel_crtc_compute_pixel_rate(crtc_state);
15634 if (dev_priv->display.modeset_calc_cdclk) {
15635 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15636 if (WARN_ON(min_cdclk < 0))
15640 drm_calc_timestamping_constants(&crtc->base,
15641 &crtc_state->base.adjusted_mode);
15642 update_scanline_offset(crtc);
15645 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15646 dev_priv->min_voltage_level[crtc->pipe] =
15647 crtc_state->min_voltage_level;
15649 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15654 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15656 struct intel_encoder *encoder;
15658 for_each_intel_encoder(&dev_priv->drm, encoder) {
15660 enum intel_display_power_domain domain;
15661 struct intel_crtc_state *crtc_state;
15663 if (!encoder->get_power_domains)
15667 * MST-primary and inactive encoders don't have a crtc state
15668 * and neither of these require any power domain references.
15670 if (!encoder->base.crtc)
15673 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
15674 get_domains = encoder->get_power_domains(encoder, crtc_state);
15675 for_each_power_domain(domain, get_domains)
15676 intel_display_power_get(dev_priv, domain);
15680 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15682 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15683 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15684 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15687 if (IS_HASWELL(dev_priv)) {
15689 * WaRsPkgCStateDisplayPMReq:hsw
15690 * System hang if this isn't done before disabling all planes!
15692 I915_WRITE(CHICKEN_PAR1_1,
15693 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15697 /* Scan out the current hw modeset state,
15698 * and sanitizes it to the current state
15701 intel_modeset_setup_hw_state(struct drm_device *dev,
15702 struct drm_modeset_acquire_ctx *ctx)
15704 struct drm_i915_private *dev_priv = to_i915(dev);
15706 struct intel_crtc *crtc;
15707 struct intel_encoder *encoder;
15710 intel_early_display_was(dev_priv);
15711 intel_modeset_readout_hw_state(dev);
15713 /* HW state is read out, now we need to sanitize this mess. */
15714 get_encoder_power_domains(dev_priv);
15716 intel_sanitize_plane_mapping(dev_priv);
15718 for_each_intel_encoder(dev, encoder) {
15719 intel_sanitize_encoder(encoder);
15722 for_each_pipe(dev_priv, pipe) {
15723 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15725 intel_sanitize_crtc(crtc, ctx);
15726 intel_dump_pipe_config(crtc, crtc->config,
15727 "[setup_hw_state]");
15730 intel_modeset_update_connector_atomic_state(dev);
15732 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15733 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15735 if (!pll->on || pll->active_mask)
15738 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
15741 pll->info->funcs->disable(dev_priv, pll);
15745 if (IS_G4X(dev_priv)) {
15746 g4x_wm_get_hw_state(dev);
15747 g4x_wm_sanitize(dev_priv);
15748 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15749 vlv_wm_get_hw_state(dev);
15750 vlv_wm_sanitize(dev_priv);
15751 } else if (INTEL_GEN(dev_priv) >= 9) {
15752 skl_wm_get_hw_state(dev);
15753 } else if (HAS_PCH_SPLIT(dev_priv)) {
15754 ilk_wm_get_hw_state(dev);
15757 for_each_intel_crtc(dev, crtc) {
15760 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15761 if (WARN_ON(put_domains))
15762 modeset_put_power_domains(dev_priv, put_domains);
15764 intel_display_set_init_power(dev_priv, false);
15766 intel_power_domains_verify_state(dev_priv);
15768 intel_fbc_init_pipe_state(dev_priv);
15771 void intel_display_resume(struct drm_device *dev)
15773 struct drm_i915_private *dev_priv = to_i915(dev);
15774 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15775 struct drm_modeset_acquire_ctx ctx;
15778 dev_priv->modeset_restore_state = NULL;
15780 state->acquire_ctx = &ctx;
15782 drm_modeset_acquire_init(&ctx, 0);
15785 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15786 if (ret != -EDEADLK)
15789 drm_modeset_backoff(&ctx);
15793 ret = __intel_display_resume(dev, state, &ctx);
15795 intel_enable_ipc(dev_priv);
15796 drm_modeset_drop_locks(&ctx);
15797 drm_modeset_acquire_fini(&ctx);
15800 DRM_ERROR("Restoring old state failed with %i\n", ret);
15802 drm_atomic_state_put(state);
15805 int intel_connector_register(struct drm_connector *connector)
15807 struct intel_connector *intel_connector = to_intel_connector(connector);
15810 ret = intel_backlight_device_register(intel_connector);
15820 void intel_connector_unregister(struct drm_connector *connector)
15822 struct intel_connector *intel_connector = to_intel_connector(connector);
15824 intel_backlight_device_unregister(intel_connector);
15825 intel_panel_destroy_backlight(connector);
15828 static void intel_hpd_poll_fini(struct drm_device *dev)
15830 struct intel_connector *connector;
15831 struct drm_connector_list_iter conn_iter;
15833 /* Kill all the work that may have been queued by hpd. */
15834 drm_connector_list_iter_begin(dev, &conn_iter);
15835 for_each_intel_connector_iter(connector, &conn_iter) {
15836 if (connector->modeset_retry_work.func)
15837 cancel_work_sync(&connector->modeset_retry_work);
15838 if (connector->hdcp_shim) {
15839 cancel_delayed_work_sync(&connector->hdcp_check_work);
15840 cancel_work_sync(&connector->hdcp_prop_work);
15843 drm_connector_list_iter_end(&conn_iter);
15846 void intel_modeset_cleanup(struct drm_device *dev)
15848 struct drm_i915_private *dev_priv = to_i915(dev);
15850 flush_workqueue(dev_priv->modeset_wq);
15852 flush_work(&dev_priv->atomic_helper.free_work);
15853 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15855 intel_disable_gt_powersave(dev_priv);
15858 * Interrupts and polling as the first thing to avoid creating havoc.
15859 * Too much stuff here (turning of connectors, ...) would
15860 * experience fancy races otherwise.
15862 intel_irq_uninstall(dev_priv);
15865 * Due to the hpd irq storm handling the hotplug work can re-arm the
15866 * poll handlers. Hence disable polling after hpd handling is shut down.
15868 intel_hpd_poll_fini(dev);
15870 /* poll work can call into fbdev, hence clean that up afterwards */
15871 intel_fbdev_fini(dev_priv);
15873 intel_unregister_dsm_handler();
15875 intel_fbc_global_disable(dev_priv);
15877 /* flush any delayed tasks or pending work */
15878 flush_scheduled_work();
15880 drm_mode_config_cleanup(dev);
15882 intel_cleanup_overlay(dev_priv);
15884 intel_cleanup_gt_powersave(dev_priv);
15886 intel_teardown_gmbus(dev_priv);
15888 destroy_workqueue(dev_priv->modeset_wq);
15891 void intel_connector_attach_encoder(struct intel_connector *connector,
15892 struct intel_encoder *encoder)
15894 connector->encoder = encoder;
15895 drm_mode_connector_attach_encoder(&connector->base,
15900 * set vga decode state - true == enable VGA decode
15902 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15904 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15907 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15908 DRM_ERROR("failed to read control word\n");
15912 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15916 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15918 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15920 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15921 DRM_ERROR("failed to write control word\n");
15928 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15930 struct intel_display_error_state {
15932 u32 power_well_driver;
15934 int num_transcoders;
15936 struct intel_cursor_error_state {
15941 } cursor[I915_MAX_PIPES];
15943 struct intel_pipe_error_state {
15944 bool power_domain_on;
15947 } pipe[I915_MAX_PIPES];
15949 struct intel_plane_error_state {
15957 } plane[I915_MAX_PIPES];
15959 struct intel_transcoder_error_state {
15960 bool power_domain_on;
15961 enum transcoder cpu_transcoder;
15974 struct intel_display_error_state *
15975 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15977 struct intel_display_error_state *error;
15978 int transcoders[] = {
15986 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15989 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15993 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15994 error->power_well_driver =
15995 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15997 for_each_pipe(dev_priv, i) {
15998 error->pipe[i].power_domain_on =
15999 __intel_display_power_is_enabled(dev_priv,
16000 POWER_DOMAIN_PIPE(i));
16001 if (!error->pipe[i].power_domain_on)
16004 error->cursor[i].control = I915_READ(CURCNTR(i));
16005 error->cursor[i].position = I915_READ(CURPOS(i));
16006 error->cursor[i].base = I915_READ(CURBASE(i));
16008 error->plane[i].control = I915_READ(DSPCNTR(i));
16009 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16010 if (INTEL_GEN(dev_priv) <= 3) {
16011 error->plane[i].size = I915_READ(DSPSIZE(i));
16012 error->plane[i].pos = I915_READ(DSPPOS(i));
16014 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16015 error->plane[i].addr = I915_READ(DSPADDR(i));
16016 if (INTEL_GEN(dev_priv) >= 4) {
16017 error->plane[i].surface = I915_READ(DSPSURF(i));
16018 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16021 error->pipe[i].source = I915_READ(PIPESRC(i));
16023 if (HAS_GMCH_DISPLAY(dev_priv))
16024 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16027 /* Note: this does not include DSI transcoders. */
16028 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16029 if (HAS_DDI(dev_priv))
16030 error->num_transcoders++; /* Account for eDP. */
16032 for (i = 0; i < error->num_transcoders; i++) {
16033 enum transcoder cpu_transcoder = transcoders[i];
16035 error->transcoder[i].power_domain_on =
16036 __intel_display_power_is_enabled(dev_priv,
16037 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16038 if (!error->transcoder[i].power_domain_on)
16041 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16043 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16044 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16045 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16046 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16047 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16048 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16049 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16055 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16058 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16059 struct intel_display_error_state *error)
16061 struct drm_i915_private *dev_priv = m->i915;
16067 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16068 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16069 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16070 error->power_well_driver);
16071 for_each_pipe(dev_priv, i) {
16072 err_printf(m, "Pipe [%d]:\n", i);
16073 err_printf(m, " Power: %s\n",
16074 onoff(error->pipe[i].power_domain_on));
16075 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16076 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16078 err_printf(m, "Plane [%d]:\n", i);
16079 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16080 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16081 if (INTEL_GEN(dev_priv) <= 3) {
16082 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16083 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16085 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16086 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16087 if (INTEL_GEN(dev_priv) >= 4) {
16088 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16089 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16092 err_printf(m, "Cursor [%d]:\n", i);
16093 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16094 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16095 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16098 for (i = 0; i < error->num_transcoders; i++) {
16099 err_printf(m, "CPU transcoder: %s\n",
16100 transcoder_name(error->transcoder[i].cpu_transcoder));
16101 err_printf(m, " Power: %s\n",
16102 onoff(error->transcoder[i].power_domain_on));
16103 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16104 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16105 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16106 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16107 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16108 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16109 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);