2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
76 static const uint32_t skl_primary_formats[] = {
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
91 static const uint64_t skl_format_modifiers_noccs[] = {
92 I915_FORMAT_MOD_Yf_TILED,
93 I915_FORMAT_MOD_Y_TILED,
94 I915_FORMAT_MOD_X_TILED,
95 DRM_FORMAT_MOD_LINEAR,
96 DRM_FORMAT_MOD_INVALID
99 static const uint64_t skl_format_modifiers_ccs[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS,
101 I915_FORMAT_MOD_Y_TILED_CCS,
102 I915_FORMAT_MOD_Yf_TILED,
103 I915_FORMAT_MOD_Y_TILED,
104 I915_FORMAT_MOD_X_TILED,
105 DRM_FORMAT_MOD_LINEAR,
106 DRM_FORMAT_MOD_INVALID
110 static const uint32_t intel_cursor_formats[] = {
114 static const uint64_t cursor_format_modifiers[] = {
115 DRM_FORMAT_MOD_LINEAR,
116 DRM_FORMAT_MOD_INVALID
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122 struct intel_crtc_state *pipe_config);
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125 struct drm_i915_gem_object *obj,
126 struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131 struct intel_link_m_n *m_n,
132 struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139 const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143 struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148 struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
154 } dot, vco, n, m, m1, m2, p, p1;
158 int p2_slow, p2_fast;
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
165 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv->sb_lock);
169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170 CCK_FUSE_HPLL_FREQ_MASK;
171 mutex_unlock(&dev_priv->sb_lock);
173 return vco_freq[hpll_freq] * 1000;
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177 const char *name, u32 reg, int ref_freq)
182 mutex_lock(&dev_priv->sb_lock);
183 val = vlv_cck_read(dev_priv, reg);
184 mutex_unlock(&dev_priv->sb_lock);
186 divider = val & CCK_FREQUENCY_VALUES;
188 WARN((val & CCK_FREQUENCY_STATUS) !=
189 (divider << CCK_FREQUENCY_STATUS_SHIFT),
190 "%s change in progress\n", name);
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196 const char *name, u32 reg)
198 if (dev_priv->hpll_freq == 0)
199 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
201 return vlv_get_cck_clock(dev_priv, name, reg,
202 dev_priv->hpll_freq);
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
223 return dev_priv->fdi_pll_freq;
226 static const struct intel_limit intel_limits_i8xx_dac = {
227 .dot = { .min = 25000, .max = 350000 },
228 .vco = { .min = 908000, .max = 1512000 },
229 .n = { .min = 2, .max = 16 },
230 .m = { .min = 96, .max = 140 },
231 .m1 = { .min = 18, .max = 26 },
232 .m2 = { .min = 6, .max = 16 },
233 .p = { .min = 4, .max = 128 },
234 .p1 = { .min = 2, .max = 33 },
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 4, .p2_fast = 2 },
239 static const struct intel_limit intel_limits_i8xx_dvo = {
240 .dot = { .min = 25000, .max = 350000 },
241 .vco = { .min = 908000, .max = 1512000 },
242 .n = { .min = 2, .max = 16 },
243 .m = { .min = 96, .max = 140 },
244 .m1 = { .min = 18, .max = 26 },
245 .m2 = { .min = 6, .max = 16 },
246 .p = { .min = 4, .max = 128 },
247 .p1 = { .min = 2, .max = 33 },
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 4, .p2_fast = 4 },
252 static const struct intel_limit intel_limits_i8xx_lvds = {
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 908000, .max = 1512000 },
255 .n = { .min = 2, .max = 16 },
256 .m = { .min = 96, .max = 140 },
257 .m1 = { .min = 18, .max = 26 },
258 .m2 = { .min = 6, .max = 16 },
259 .p = { .min = 4, .max = 128 },
260 .p1 = { .min = 1, .max = 6 },
261 .p2 = { .dot_limit = 165000,
262 .p2_slow = 14, .p2_fast = 7 },
265 static const struct intel_limit intel_limits_i9xx_sdvo = {
266 .dot = { .min = 20000, .max = 400000 },
267 .vco = { .min = 1400000, .max = 2800000 },
268 .n = { .min = 1, .max = 6 },
269 .m = { .min = 70, .max = 120 },
270 .m1 = { .min = 8, .max = 18 },
271 .m2 = { .min = 3, .max = 7 },
272 .p = { .min = 5, .max = 80 },
273 .p1 = { .min = 1, .max = 8 },
274 .p2 = { .dot_limit = 200000,
275 .p2_slow = 10, .p2_fast = 5 },
278 static const struct intel_limit intel_limits_i9xx_lvds = {
279 .dot = { .min = 20000, .max = 400000 },
280 .vco = { .min = 1400000, .max = 2800000 },
281 .n = { .min = 1, .max = 6 },
282 .m = { .min = 70, .max = 120 },
283 .m1 = { .min = 8, .max = 18 },
284 .m2 = { .min = 3, .max = 7 },
285 .p = { .min = 7, .max = 98 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 112000,
288 .p2_slow = 14, .p2_fast = 7 },
292 static const struct intel_limit intel_limits_g4x_sdvo = {
293 .dot = { .min = 25000, .max = 270000 },
294 .vco = { .min = 1750000, .max = 3500000},
295 .n = { .min = 1, .max = 4 },
296 .m = { .min = 104, .max = 138 },
297 .m1 = { .min = 17, .max = 23 },
298 .m2 = { .min = 5, .max = 11 },
299 .p = { .min = 10, .max = 30 },
300 .p1 = { .min = 1, .max = 3},
301 .p2 = { .dot_limit = 270000,
307 static const struct intel_limit intel_limits_g4x_hdmi = {
308 .dot = { .min = 22000, .max = 400000 },
309 .vco = { .min = 1750000, .max = 3500000},
310 .n = { .min = 1, .max = 4 },
311 .m = { .min = 104, .max = 138 },
312 .m1 = { .min = 16, .max = 23 },
313 .m2 = { .min = 5, .max = 11 },
314 .p = { .min = 5, .max = 80 },
315 .p1 = { .min = 1, .max = 8},
316 .p2 = { .dot_limit = 165000,
317 .p2_slow = 10, .p2_fast = 5 },
320 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
321 .dot = { .min = 20000, .max = 115000 },
322 .vco = { .min = 1750000, .max = 3500000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 0,
330 .p2_slow = 14, .p2_fast = 14
334 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
335 .dot = { .min = 80000, .max = 224000 },
336 .vco = { .min = 1750000, .max = 3500000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 104, .max = 138 },
339 .m1 = { .min = 17, .max = 23 },
340 .m2 = { .min = 5, .max = 11 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 0,
344 .p2_slow = 7, .p2_fast = 7
348 static const struct intel_limit intel_limits_pineview_sdvo = {
349 .dot = { .min = 20000, .max = 400000},
350 .vco = { .min = 1700000, .max = 3500000 },
351 /* Pineview's Ncounter is a ring counter */
352 .n = { .min = 3, .max = 6 },
353 .m = { .min = 2, .max = 256 },
354 /* Pineview only has one combined m divider, which we treat as m2. */
355 .m1 = { .min = 0, .max = 0 },
356 .m2 = { .min = 0, .max = 254 },
357 .p = { .min = 5, .max = 80 },
358 .p1 = { .min = 1, .max = 8 },
359 .p2 = { .dot_limit = 200000,
360 .p2_slow = 10, .p2_fast = 5 },
363 static const struct intel_limit intel_limits_pineview_lvds = {
364 .dot = { .min = 20000, .max = 400000 },
365 .vco = { .min = 1700000, .max = 3500000 },
366 .n = { .min = 3, .max = 6 },
367 .m = { .min = 2, .max = 256 },
368 .m1 = { .min = 0, .max = 0 },
369 .m2 = { .min = 0, .max = 254 },
370 .p = { .min = 7, .max = 112 },
371 .p1 = { .min = 1, .max = 8 },
372 .p2 = { .dot_limit = 112000,
373 .p2_slow = 14, .p2_fast = 14 },
376 /* Ironlake / Sandybridge
378 * We calculate clock using (register_value + 2) for N/M1/M2, so here
379 * the range value for them is (actual_value - 2).
381 static const struct intel_limit intel_limits_ironlake_dac = {
382 .dot = { .min = 25000, .max = 350000 },
383 .vco = { .min = 1760000, .max = 3510000 },
384 .n = { .min = 1, .max = 5 },
385 .m = { .min = 79, .max = 127 },
386 .m1 = { .min = 12, .max = 22 },
387 .m2 = { .min = 5, .max = 9 },
388 .p = { .min = 5, .max = 80 },
389 .p1 = { .min = 1, .max = 8 },
390 .p2 = { .dot_limit = 225000,
391 .p2_slow = 10, .p2_fast = 5 },
394 static const struct intel_limit intel_limits_ironlake_single_lvds = {
395 .dot = { .min = 25000, .max = 350000 },
396 .vco = { .min = 1760000, .max = 3510000 },
397 .n = { .min = 1, .max = 3 },
398 .m = { .min = 79, .max = 118 },
399 .m1 = { .min = 12, .max = 22 },
400 .m2 = { .min = 5, .max = 9 },
401 .p = { .min = 28, .max = 112 },
402 .p1 = { .min = 2, .max = 8 },
403 .p2 = { .dot_limit = 225000,
404 .p2_slow = 14, .p2_fast = 14 },
407 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
408 .dot = { .min = 25000, .max = 350000 },
409 .vco = { .min = 1760000, .max = 3510000 },
410 .n = { .min = 1, .max = 3 },
411 .m = { .min = 79, .max = 127 },
412 .m1 = { .min = 12, .max = 22 },
413 .m2 = { .min = 5, .max = 9 },
414 .p = { .min = 14, .max = 56 },
415 .p1 = { .min = 2, .max = 8 },
416 .p2 = { .dot_limit = 225000,
417 .p2_slow = 7, .p2_fast = 7 },
420 /* LVDS 100mhz refclk limits. */
421 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
422 .dot = { .min = 25000, .max = 350000 },
423 .vco = { .min = 1760000, .max = 3510000 },
424 .n = { .min = 1, .max = 2 },
425 .m = { .min = 79, .max = 126 },
426 .m1 = { .min = 12, .max = 22 },
427 .m2 = { .min = 5, .max = 9 },
428 .p = { .min = 28, .max = 112 },
429 .p1 = { .min = 2, .max = 8 },
430 .p2 = { .dot_limit = 225000,
431 .p2_slow = 14, .p2_fast = 14 },
434 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
435 .dot = { .min = 25000, .max = 350000 },
436 .vco = { .min = 1760000, .max = 3510000 },
437 .n = { .min = 1, .max = 3 },
438 .m = { .min = 79, .max = 126 },
439 .m1 = { .min = 12, .max = 22 },
440 .m2 = { .min = 5, .max = 9 },
441 .p = { .min = 14, .max = 42 },
442 .p1 = { .min = 2, .max = 6 },
443 .p2 = { .dot_limit = 225000,
444 .p2_slow = 7, .p2_fast = 7 },
447 static const struct intel_limit intel_limits_vlv = {
449 * These are the data rate limits (measured in fast clocks)
450 * since those are the strictest limits we have. The fast
451 * clock and actual rate limits are more relaxed, so checking
452 * them would make no difference.
454 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
455 .vco = { .min = 4000000, .max = 6000000 },
456 .n = { .min = 1, .max = 7 },
457 .m1 = { .min = 2, .max = 3 },
458 .m2 = { .min = 11, .max = 156 },
459 .p1 = { .min = 2, .max = 3 },
460 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 static const struct intel_limit intel_limits_chv = {
465 * These are the data rate limits (measured in fast clocks)
466 * since those are the strictest limits we have. The fast
467 * clock and actual rate limits are more relaxed, so checking
468 * them would make no difference.
470 .dot = { .min = 25000 * 5, .max = 540000 * 5},
471 .vco = { .min = 4800000, .max = 6480000 },
472 .n = { .min = 1, .max = 1 },
473 .m1 = { .min = 2, .max = 2 },
474 .m2 = { .min = 24 << 22, .max = 175 << 22 },
475 .p1 = { .min = 2, .max = 4 },
476 .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 static const struct intel_limit intel_limits_bxt = {
480 /* FIXME: find real dot limits */
481 .dot = { .min = 0, .max = INT_MAX },
482 .vco = { .min = 4800000, .max = 6700000 },
483 .n = { .min = 1, .max = 1 },
484 .m1 = { .min = 2, .max = 2 },
485 /* FIXME: find real m2 limits */
486 .m2 = { .min = 2 << 22, .max = 255 << 22 },
487 .p1 = { .min = 2, .max = 4 },
488 .p2 = { .p2_slow = 1, .p2_fast = 20 },
492 needs_modeset(const struct drm_crtc_state *state)
494 return drm_atomic_crtc_needs_modeset(state);
498 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
499 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
500 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
501 * The helpers' return value is the rate of the clock that is fed to the
502 * display engine's pipe which can be the above fast dot clock rate or a
503 * divided-down version of it.
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
518 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
520 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
523 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
525 clock->m = i9xx_dpll_compute_m(clock);
526 clock->p = clock->p1 * clock->p2;
527 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
529 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
535 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
537 clock->m = clock->m1 * clock->m2;
538 clock->p = clock->p1 * clock->p2;
539 if (WARN_ON(clock->n == 0 || clock->p == 0))
541 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
542 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
544 return clock->dot / 5;
547 int chv_calc_dpll_params(int refclk, struct dpll *clock)
549 clock->m = clock->m1 * clock->m2;
550 clock->p = clock->p1 * clock->p2;
551 if (WARN_ON(clock->n == 0 || clock->p == 0))
553 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
555 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
557 return clock->dot / 5;
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
566 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
567 const struct intel_limit *limit,
568 const struct dpll *clock)
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
579 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
580 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
584 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
585 !IS_GEN9_LP(dev_priv)) {
586 if (clock->p < limit->p.min || limit->p.max < clock->p)
587 INTELPllInvalid("p out of range\n");
588 if (clock->m < limit->m.min || limit->m.max < clock->m)
589 INTELPllInvalid("m out of range\n");
592 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
593 INTELPllInvalid("vco out of range\n");
594 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
595 * connector, etc., rather than just a single range.
597 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
598 INTELPllInvalid("dot out of range\n");
604 i9xx_select_p2_div(const struct intel_limit *limit,
605 const struct intel_crtc_state *crtc_state,
608 struct drm_device *dev = crtc_state->base.crtc->dev;
610 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
616 if (intel_is_dual_link_lvds(dev))
617 return limit->p2.p2_fast;
619 return limit->p2.p2_slow;
621 if (target < limit->p2.dot_limit)
622 return limit->p2.p2_slow;
624 return limit->p2.p2_fast;
629 * Returns a set of divisors for the desired target clock with the given
630 * refclk, or FALSE. The returned values represent the clock equation:
631 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
633 * Target and reference clocks are specified in kHz.
635 * If match_clock is provided, then best_clock P divider must match the P
636 * divider from @match_clock used for LVDS downclocking.
639 i9xx_find_best_dpll(const struct intel_limit *limit,
640 struct intel_crtc_state *crtc_state,
641 int target, int refclk, struct dpll *match_clock,
642 struct dpll *best_clock)
644 struct drm_device *dev = crtc_state->base.crtc->dev;
648 memset(best_clock, 0, sizeof(*best_clock));
650 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
652 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
654 for (clock.m2 = limit->m2.min;
655 clock.m2 <= limit->m2.max; clock.m2++) {
656 if (clock.m2 >= clock.m1)
658 for (clock.n = limit->n.min;
659 clock.n <= limit->n.max; clock.n++) {
660 for (clock.p1 = limit->p1.min;
661 clock.p1 <= limit->p1.max; clock.p1++) {
664 i9xx_calc_dpll_params(refclk, &clock);
665 if (!intel_PLL_is_valid(to_i915(dev),
670 clock.p != match_clock->p)
673 this_err = abs(clock.dot - target);
674 if (this_err < err) {
683 return (err != target);
687 * Returns a set of divisors for the desired target clock with the given
688 * refclk, or FALSE. The returned values represent the clock equation:
689 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
691 * Target and reference clocks are specified in kHz.
693 * If match_clock is provided, then best_clock P divider must match the P
694 * divider from @match_clock used for LVDS downclocking.
697 pnv_find_best_dpll(const struct intel_limit *limit,
698 struct intel_crtc_state *crtc_state,
699 int target, int refclk, struct dpll *match_clock,
700 struct dpll *best_clock)
702 struct drm_device *dev = crtc_state->base.crtc->dev;
706 memset(best_clock, 0, sizeof(*best_clock));
708 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
712 for (clock.m2 = limit->m2.min;
713 clock.m2 <= limit->m2.max; clock.m2++) {
714 for (clock.n = limit->n.min;
715 clock.n <= limit->n.max; clock.n++) {
716 for (clock.p1 = limit->p1.min;
717 clock.p1 <= limit->p1.max; clock.p1++) {
720 pnv_calc_dpll_params(refclk, &clock);
721 if (!intel_PLL_is_valid(to_i915(dev),
726 clock.p != match_clock->p)
729 this_err = abs(clock.dot - target);
730 if (this_err < err) {
739 return (err != target);
743 * Returns a set of divisors for the desired target clock with the given
744 * refclk, or FALSE. The returned values represent the clock equation:
745 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
747 * Target and reference clocks are specified in kHz.
749 * If match_clock is provided, then best_clock P divider must match the P
750 * divider from @match_clock used for LVDS downclocking.
753 g4x_find_best_dpll(const struct intel_limit *limit,
754 struct intel_crtc_state *crtc_state,
755 int target, int refclk, struct dpll *match_clock,
756 struct dpll *best_clock)
758 struct drm_device *dev = crtc_state->base.crtc->dev;
762 /* approximately equals target * 0.00585 */
763 int err_most = (target >> 8) + (target >> 9);
765 memset(best_clock, 0, sizeof(*best_clock));
767 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
769 max_n = limit->n.max;
770 /* based on hardware requirement, prefer smaller n to precision */
771 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
772 /* based on hardware requirement, prefere larger m1,m2 */
773 for (clock.m1 = limit->m1.max;
774 clock.m1 >= limit->m1.min; clock.m1--) {
775 for (clock.m2 = limit->m2.max;
776 clock.m2 >= limit->m2.min; clock.m2--) {
777 for (clock.p1 = limit->p1.max;
778 clock.p1 >= limit->p1.min; clock.p1--) {
781 i9xx_calc_dpll_params(refclk, &clock);
782 if (!intel_PLL_is_valid(to_i915(dev),
787 this_err = abs(clock.dot - target);
788 if (this_err < err_most) {
802 * Check if the calculated PLL configuration is more optimal compared to the
803 * best configuration and error found so far. Return the calculated error.
805 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
806 const struct dpll *calculated_clock,
807 const struct dpll *best_clock,
808 unsigned int best_error_ppm,
809 unsigned int *error_ppm)
812 * For CHV ignore the error and consider only the P value.
813 * Prefer a bigger P value based on HW requirements.
815 if (IS_CHERRYVIEW(to_i915(dev))) {
818 return calculated_clock->p > best_clock->p;
821 if (WARN_ON_ONCE(!target_freq))
824 *error_ppm = div_u64(1000000ULL *
825 abs(target_freq - calculated_clock->dot),
828 * Prefer a better P value over a better (smaller) error if the error
829 * is small. Ensure this preference for future configurations too by
830 * setting the error to 0.
832 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
838 return *error_ppm + 10 < best_error_ppm;
842 * Returns a set of divisors for the desired target clock with the given
843 * refclk, or FALSE. The returned values represent the clock equation:
844 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
847 vlv_find_best_dpll(const struct intel_limit *limit,
848 struct intel_crtc_state *crtc_state,
849 int target, int refclk, struct dpll *match_clock,
850 struct dpll *best_clock)
852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
853 struct drm_device *dev = crtc->base.dev;
855 unsigned int bestppm = 1000000;
856 /* min update 19.2 MHz */
857 int max_n = min(limit->n.max, refclk / 19200);
860 target *= 5; /* fast clock */
862 memset(best_clock, 0, sizeof(*best_clock));
864 /* based on hardware requirement, prefer smaller n to precision */
865 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
866 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
867 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
868 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
869 clock.p = clock.p1 * clock.p2;
870 /* based on hardware requirement, prefer bigger m1,m2 values */
871 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
874 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
877 vlv_calc_dpll_params(refclk, &clock);
879 if (!intel_PLL_is_valid(to_i915(dev),
884 if (!vlv_PLL_is_optimal(dev, target,
902 * Returns a set of divisors for the desired target clock with the given
903 * refclk, or FALSE. The returned values represent the clock equation:
904 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
907 chv_find_best_dpll(const struct intel_limit *limit,
908 struct intel_crtc_state *crtc_state,
909 int target, int refclk, struct dpll *match_clock,
910 struct dpll *best_clock)
912 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
913 struct drm_device *dev = crtc->base.dev;
914 unsigned int best_error_ppm;
919 memset(best_clock, 0, sizeof(*best_clock));
920 best_error_ppm = 1000000;
923 * Based on hardware doc, the n always set to 1, and m1 always
924 * set to 2. If requires to support 200Mhz refclk, we need to
925 * revisit this because n may not 1 anymore.
927 clock.n = 1, clock.m1 = 2;
928 target *= 5; /* fast clock */
930 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
931 for (clock.p2 = limit->p2.p2_fast;
932 clock.p2 >= limit->p2.p2_slow;
933 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
934 unsigned int error_ppm;
936 clock.p = clock.p1 * clock.p2;
938 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
939 clock.n) << 22, refclk * clock.m1);
941 if (m2 > INT_MAX/clock.m1)
946 chv_calc_dpll_params(refclk, &clock);
948 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
951 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
952 best_error_ppm, &error_ppm))
956 best_error_ppm = error_ppm;
964 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
965 struct dpll *best_clock)
968 const struct intel_limit *limit = &intel_limits_bxt;
970 return chv_find_best_dpll(limit, crtc_state,
971 target_clock, refclk, NULL, best_clock);
974 bool intel_crtc_active(struct intel_crtc *crtc)
976 /* Be paranoid as we can arrive here with only partial
977 * state retrieved from the hardware during setup.
979 * We can ditch the adjusted_mode.crtc_clock check as soon
980 * as Haswell has gained clock readout/fastboot support.
982 * We can ditch the crtc->primary->fb check as soon as we can
983 * properly reconstruct framebuffers.
985 * FIXME: The intel_crtc->active here should be switched to
986 * crtc->state->active once we have proper CRTC states wired up
989 return crtc->active && crtc->base.primary->state->fb &&
990 crtc->config->base.adjusted_mode.crtc_clock;
993 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
996 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
998 return crtc->config->cpu_transcoder;
1001 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1004 i915_reg_t reg = PIPEDSL(pipe);
1008 if (IS_GEN2(dev_priv))
1009 line_mask = DSL_LINEMASK_GEN2;
1011 line_mask = DSL_LINEMASK_GEN3;
1013 line1 = I915_READ(reg) & line_mask;
1015 line2 = I915_READ(reg) & line_mask;
1017 return line1 != line2;
1020 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1023 enum pipe pipe = crtc->pipe;
1025 /* Wait for the display line to settle/start moving */
1026 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1027 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1028 pipe_name(pipe), onoff(state));
1031 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1033 wait_for_pipe_scanline_moving(crtc, false);
1036 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1038 wait_for_pipe_scanline_moving(crtc, true);
1042 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1044 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1045 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1047 if (INTEL_GEN(dev_priv) >= 4) {
1048 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1049 i915_reg_t reg = PIPECONF(cpu_transcoder);
1051 /* Wait for the Pipe State to go off */
1052 if (intel_wait_for_register(dev_priv,
1053 reg, I965_PIPECONF_ACTIVE, 0,
1055 WARN(1, "pipe_off wait timed out\n");
1057 intel_wait_for_pipe_scanline_stopped(crtc);
1061 /* Only for pre-ILK configs */
1062 void assert_pll(struct drm_i915_private *dev_priv,
1063 enum pipe pipe, bool state)
1068 val = I915_READ(DPLL(pipe));
1069 cur_state = !!(val & DPLL_VCO_ENABLE);
1070 I915_STATE_WARN(cur_state != state,
1071 "PLL state assertion failure (expected %s, current %s)\n",
1072 onoff(state), onoff(cur_state));
1075 /* XXX: the dsi pll is shared between MIPI DSI ports */
1076 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081 mutex_lock(&dev_priv->sb_lock);
1082 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1083 mutex_unlock(&dev_priv->sb_lock);
1085 cur_state = val & DSI_PLL_VCO_EN;
1086 I915_STATE_WARN(cur_state != state,
1087 "DSI PLL state assertion failure (expected %s, current %s)\n",
1088 onoff(state), onoff(cur_state));
1091 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1092 enum pipe pipe, bool state)
1095 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1098 if (HAS_DDI(dev_priv)) {
1099 /* DDI does not have a specific FDI_TX register */
1100 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1101 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1103 u32 val = I915_READ(FDI_TX_CTL(pipe));
1104 cur_state = !!(val & FDI_TX_ENABLE);
1106 I915_STATE_WARN(cur_state != state,
1107 "FDI TX state assertion failure (expected %s, current %s)\n",
1108 onoff(state), onoff(cur_state));
1110 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1111 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1113 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1114 enum pipe pipe, bool state)
1119 val = I915_READ(FDI_RX_CTL(pipe));
1120 cur_state = !!(val & FDI_RX_ENABLE);
1121 I915_STATE_WARN(cur_state != state,
1122 "FDI RX state assertion failure (expected %s, current %s)\n",
1123 onoff(state), onoff(cur_state));
1125 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1126 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1128 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1133 /* ILK FDI PLL is always enabled */
1134 if (IS_GEN5(dev_priv))
1137 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1138 if (HAS_DDI(dev_priv))
1141 val = I915_READ(FDI_TX_CTL(pipe));
1142 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1145 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1158 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1162 enum pipe panel_pipe = PIPE_A;
1165 if (WARN_ON(HAS_DDI(dev_priv)))
1168 if (HAS_PCH_SPLIT(dev_priv)) {
1171 pp_reg = PP_CONTROL(0);
1172 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = PP_CONTROL(pipe);
1183 pp_reg = PP_CONTROL(0);
1184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
1190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1193 I915_STATE_WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
1198 void assert_pipe(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1202 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1204 enum intel_display_power_domain power_domain;
1206 /* we keep both pipes enabled on 830 */
1207 if (IS_I830(dev_priv))
1210 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1211 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1212 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1213 cur_state = !!(val & PIPECONF_ENABLE);
1215 intel_display_power_put(dev_priv, power_domain);
1220 I915_STATE_WARN(cur_state != state,
1221 "pipe %c assertion failure (expected %s, current %s)\n",
1222 pipe_name(pipe), onoff(state), onoff(cur_state));
1225 static void assert_plane(struct intel_plane *plane, bool state)
1227 bool cur_state = plane->get_hw_state(plane);
1229 I915_STATE_WARN(cur_state != state,
1230 "%s assertion failure (expected %s, current %s)\n",
1231 plane->base.name, onoff(state), onoff(cur_state));
1234 #define assert_plane_enabled(p) assert_plane(p, true)
1235 #define assert_plane_disabled(p) assert_plane(p, false)
1237 static void assert_planes_disabled(struct intel_crtc *crtc)
1239 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1240 struct intel_plane *plane;
1242 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1243 assert_plane_disabled(plane);
1246 static void assert_vblank_disabled(struct drm_crtc *crtc)
1248 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1249 drm_crtc_vblank_put(crtc);
1252 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1258 val = I915_READ(PCH_TRANSCONF(pipe));
1259 enabled = !!(val & TRANS_ENABLE);
1260 I915_STATE_WARN(enabled,
1261 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1265 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe, u32 port_sel, u32 val)
1268 if ((val & DP_PORT_EN) == 0)
1271 if (HAS_PCH_CPT(dev_priv)) {
1272 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1273 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1275 } else if (IS_CHERRYVIEW(dev_priv)) {
1276 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1279 if ((val & DP_PIPE_MASK) != (pipe << 30))
1285 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe, u32 val)
1288 if ((val & SDVO_ENABLE) == 0)
1291 if (HAS_PCH_CPT(dev_priv)) {
1292 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1294 } else if (IS_CHERRYVIEW(dev_priv)) {
1295 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1298 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1304 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, u32 val)
1307 if ((val & LVDS_PORT_EN) == 0)
1310 if (HAS_PCH_CPT(dev_priv)) {
1311 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1314 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1320 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 val)
1323 if ((val & ADPA_DAC_ENABLE) == 0)
1325 if (HAS_PCH_CPT(dev_priv)) {
1326 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1329 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1335 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1336 enum pipe pipe, i915_reg_t reg,
1339 u32 val = I915_READ(reg);
1340 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1341 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1342 i915_mmio_reg_offset(reg), pipe_name(pipe));
1344 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1345 && (val & DP_PIPEB_SELECT),
1346 "IBX PCH dp port still using transcoder B\n");
1349 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, i915_reg_t reg)
1352 u32 val = I915_READ(reg);
1353 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1354 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1355 i915_mmio_reg_offset(reg), pipe_name(pipe));
1357 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1358 && (val & SDVO_PIPE_B_SELECT),
1359 "IBX PCH hdmi port still using transcoder B\n");
1362 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1367 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1368 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1369 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1371 val = I915_READ(PCH_ADPA);
1372 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1373 "PCH VGA enabled on transcoder %c, should be disabled\n",
1376 val = I915_READ(PCH_LVDS);
1377 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1378 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1381 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1382 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1383 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1386 static void _vlv_enable_pll(struct intel_crtc *crtc,
1387 const struct intel_crtc_state *pipe_config)
1389 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1390 enum pipe pipe = crtc->pipe;
1392 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1393 POSTING_READ(DPLL(pipe));
1396 if (intel_wait_for_register(dev_priv,
1401 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1404 static void vlv_enable_pll(struct intel_crtc *crtc,
1405 const struct intel_crtc_state *pipe_config)
1407 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1408 enum pipe pipe = crtc->pipe;
1410 assert_pipe_disabled(dev_priv, pipe);
1412 /* PLL is protected by panel, make sure we can write it */
1413 assert_panel_unlocked(dev_priv, pipe);
1415 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1416 _vlv_enable_pll(crtc, pipe_config);
1418 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1419 POSTING_READ(DPLL_MD(pipe));
1423 static void _chv_enable_pll(struct intel_crtc *crtc,
1424 const struct intel_crtc_state *pipe_config)
1426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1427 enum pipe pipe = crtc->pipe;
1428 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1431 mutex_lock(&dev_priv->sb_lock);
1433 /* Enable back the 10bit clock to display controller */
1434 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1435 tmp |= DPIO_DCLKP_EN;
1436 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1438 mutex_unlock(&dev_priv->sb_lock);
1441 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1446 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1448 /* Check PLL is locked */
1449 if (intel_wait_for_register(dev_priv,
1450 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1452 DRM_ERROR("PLL %d failed to lock\n", pipe);
1455 static void chv_enable_pll(struct intel_crtc *crtc,
1456 const struct intel_crtc_state *pipe_config)
1458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1459 enum pipe pipe = crtc->pipe;
1461 assert_pipe_disabled(dev_priv, pipe);
1463 /* PLL is protected by panel, make sure we can write it */
1464 assert_panel_unlocked(dev_priv, pipe);
1466 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1467 _chv_enable_pll(crtc, pipe_config);
1469 if (pipe != PIPE_A) {
1471 * WaPixelRepeatModeFixForC0:chv
1473 * DPLLCMD is AWOL. Use chicken bits to propagate
1474 * the value from DPLLBMD to either pipe B or C.
1476 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1477 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1478 I915_WRITE(CBR4_VLV, 0);
1479 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1482 * DPLLB VGA mode also seems to cause problems.
1483 * We should always have it disabled.
1485 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1487 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1488 POSTING_READ(DPLL_MD(pipe));
1492 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1494 struct intel_crtc *crtc;
1497 for_each_intel_crtc(&dev_priv->drm, crtc) {
1498 count += crtc->base.state->active &&
1499 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1505 static void i9xx_enable_pll(struct intel_crtc *crtc,
1506 const struct intel_crtc_state *crtc_state)
1508 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1509 i915_reg_t reg = DPLL(crtc->pipe);
1510 u32 dpll = crtc_state->dpll_hw_state.dpll;
1513 assert_pipe_disabled(dev_priv, crtc->pipe);
1515 /* PLL is protected by panel, make sure we can write it */
1516 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1517 assert_panel_unlocked(dev_priv, crtc->pipe);
1519 /* Enable DVO 2x clock on both PLLs if necessary */
1520 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1522 * It appears to be important that we don't enable this
1523 * for the current pipe before otherwise configuring the
1524 * PLL. No idea how this should be handled if multiple
1525 * DVO outputs are enabled simultaneosly.
1527 dpll |= DPLL_DVO_2X_MODE;
1528 I915_WRITE(DPLL(!crtc->pipe),
1529 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1533 * Apparently we need to have VGA mode enabled prior to changing
1534 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1535 * dividers, even though the register value does change.
1539 I915_WRITE(reg, dpll);
1541 /* Wait for the clocks to stabilize. */
1545 if (INTEL_GEN(dev_priv) >= 4) {
1546 I915_WRITE(DPLL_MD(crtc->pipe),
1547 crtc_state->dpll_hw_state.dpll_md);
1549 /* The pixel multiplier can only be updated once the
1550 * DPLL is enabled and the clocks are stable.
1552 * So write it again.
1554 I915_WRITE(reg, dpll);
1557 /* We do this three times for luck */
1558 for (i = 0; i < 3; i++) {
1559 I915_WRITE(reg, dpll);
1561 udelay(150); /* wait for warmup */
1565 static void i9xx_disable_pll(struct intel_crtc *crtc)
1567 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1568 enum pipe pipe = crtc->pipe;
1570 /* Disable DVO 2x clock on both PLLs if necessary */
1571 if (IS_I830(dev_priv) &&
1572 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1573 !intel_num_dvo_pipes(dev_priv)) {
1574 I915_WRITE(DPLL(PIPE_B),
1575 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1576 I915_WRITE(DPLL(PIPE_A),
1577 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1580 /* Don't disable pipe or pipe PLLs if needed */
1581 if (IS_I830(dev_priv))
1584 /* Make sure the pipe isn't still relying on us */
1585 assert_pipe_disabled(dev_priv, pipe);
1587 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1588 POSTING_READ(DPLL(pipe));
1591 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, pipe);
1598 val = DPLL_INTEGRATED_REF_CLK_VLV |
1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603 I915_WRITE(DPLL(pipe), val);
1604 POSTING_READ(DPLL(pipe));
1607 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1609 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1612 /* Make sure the pipe isn't still relying on us */
1613 assert_pipe_disabled(dev_priv, pipe);
1615 val = DPLL_SSC_REF_CLK_CHV |
1616 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1618 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1620 I915_WRITE(DPLL(pipe), val);
1621 POSTING_READ(DPLL(pipe));
1623 mutex_lock(&dev_priv->sb_lock);
1625 /* Disable 10bit clock to display controller */
1626 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1627 val &= ~DPIO_DCLKP_EN;
1628 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1630 mutex_unlock(&dev_priv->sb_lock);
1633 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1634 struct intel_digital_port *dport,
1635 unsigned int expected_mask)
1638 i915_reg_t dpll_reg;
1640 switch (dport->base.port) {
1642 port_mask = DPLL_PORTB_READY_MASK;
1646 port_mask = DPLL_PORTC_READY_MASK;
1648 expected_mask <<= 4;
1651 port_mask = DPLL_PORTD_READY_MASK;
1652 dpll_reg = DPIO_PHY_STATUS;
1658 if (intel_wait_for_register(dev_priv,
1659 dpll_reg, port_mask, expected_mask,
1661 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1662 port_name(dport->base.port),
1663 I915_READ(dpll_reg) & port_mask, expected_mask);
1666 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1669 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1672 uint32_t val, pipeconf_val;
1674 /* Make sure PCH DPLL is enabled */
1675 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1681 if (HAS_PCH_CPT(dev_priv)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1690 reg = PCH_TRANSCONF(pipe);
1691 val = I915_READ(reg);
1692 pipeconf_val = I915_READ(PIPECONF(pipe));
1694 if (HAS_PCH_IBX(dev_priv)) {
1696 * Make the BPC in transcoder be consistent with
1697 * that in pipeconf reg. For HDMI we must use 8bpc
1698 * here for both 8bpc and 12bpc.
1700 val &= ~PIPECONF_BPC_MASK;
1701 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1702 val |= PIPECONF_8BPC;
1704 val |= pipeconf_val & PIPECONF_BPC_MASK;
1707 val &= ~TRANS_INTERLACE_MASK;
1708 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1709 if (HAS_PCH_IBX(dev_priv) &&
1710 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1711 val |= TRANS_LEGACY_INTERLACED_ILK;
1713 val |= TRANS_INTERLACED;
1715 val |= TRANS_PROGRESSIVE;
1717 I915_WRITE(reg, val | TRANS_ENABLE);
1718 if (intel_wait_for_register(dev_priv,
1719 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1721 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1724 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1725 enum transcoder cpu_transcoder)
1727 u32 val, pipeconf_val;
1729 /* FDI must be feeding us bits for PCH ports */
1730 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1731 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1733 /* Workaround: set timing override bit. */
1734 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1735 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1739 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1741 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1742 PIPECONF_INTERLACED_ILK)
1743 val |= TRANS_INTERLACED;
1745 val |= TRANS_PROGRESSIVE;
1747 I915_WRITE(LPT_TRANSCONF, val);
1748 if (intel_wait_for_register(dev_priv,
1753 DRM_ERROR("Failed to enable PCH transcoder\n");
1756 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1762 /* FDI relies on the transcoder */
1763 assert_fdi_tx_disabled(dev_priv, pipe);
1764 assert_fdi_rx_disabled(dev_priv, pipe);
1766 /* Ports must be off as well */
1767 assert_pch_ports_disabled(dev_priv, pipe);
1769 reg = PCH_TRANSCONF(pipe);
1770 val = I915_READ(reg);
1771 val &= ~TRANS_ENABLE;
1772 I915_WRITE(reg, val);
1773 /* wait for PCH transcoder off, transcoder state */
1774 if (intel_wait_for_register(dev_priv,
1775 reg, TRANS_STATE_ENABLE, 0,
1777 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1779 if (HAS_PCH_CPT(dev_priv)) {
1780 /* Workaround: Clear the timing override chicken bit again. */
1781 reg = TRANS_CHICKEN2(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1784 I915_WRITE(reg, val);
1788 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1792 val = I915_READ(LPT_TRANSCONF);
1793 val &= ~TRANS_ENABLE;
1794 I915_WRITE(LPT_TRANSCONF, val);
1795 /* wait for PCH transcoder off, transcoder state */
1796 if (intel_wait_for_register(dev_priv,
1797 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1799 DRM_ERROR("Failed to disable PCH transcoder\n");
1801 /* Workaround: clear timing override bit. */
1802 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1803 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1804 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1807 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1809 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811 if (HAS_PCH_LPT(dev_priv))
1817 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1819 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1821 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1822 enum pipe pipe = crtc->pipe;
1826 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1828 assert_planes_disabled(crtc);
1831 * A pipe without a PLL won't actually be able to drive bits from
1832 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1835 if (HAS_GMCH_DISPLAY(dev_priv)) {
1836 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1837 assert_dsi_pll_enabled(dev_priv);
1839 assert_pll_enabled(dev_priv, pipe);
1841 if (new_crtc_state->has_pch_encoder) {
1842 /* if driving the PCH, we need FDI enabled */
1843 assert_fdi_rx_pll_enabled(dev_priv,
1844 intel_crtc_pch_transcoder(crtc));
1845 assert_fdi_tx_pll_enabled(dev_priv,
1846 (enum pipe) cpu_transcoder);
1848 /* FIXME: assert CPU port conditions for SNB+ */
1851 reg = PIPECONF(cpu_transcoder);
1852 val = I915_READ(reg);
1853 if (val & PIPECONF_ENABLE) {
1854 /* we keep both pipes enabled on 830 */
1855 WARN_ON(!IS_I830(dev_priv));
1859 I915_WRITE(reg, val | PIPECONF_ENABLE);
1863 * Until the pipe starts PIPEDSL reads will return a stale value,
1864 * which causes an apparent vblank timestamp jump when PIPEDSL
1865 * resets to its proper value. That also messes up the frame count
1866 * when it's derived from the timestamps. So let's wait for the
1867 * pipe to start properly before we call drm_crtc_vblank_on()
1869 if (dev_priv->drm.max_vblank_count == 0)
1870 intel_wait_for_pipe_scanline_moving(crtc);
1873 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1875 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1877 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1878 enum pipe pipe = crtc->pipe;
1882 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1885 * Make sure planes won't keep trying to pump pixels to us,
1886 * or we might hang the display.
1888 assert_planes_disabled(crtc);
1890 reg = PIPECONF(cpu_transcoder);
1891 val = I915_READ(reg);
1892 if ((val & PIPECONF_ENABLE) == 0)
1896 * Double wide has implications for planes
1897 * so best keep it disabled when not needed.
1899 if (old_crtc_state->double_wide)
1900 val &= ~PIPECONF_DOUBLE_WIDE;
1902 /* Don't disable pipe or pipe PLLs if needed */
1903 if (!IS_I830(dev_priv))
1904 val &= ~PIPECONF_ENABLE;
1906 I915_WRITE(reg, val);
1907 if ((val & PIPECONF_ENABLE) == 0)
1908 intel_wait_for_pipe_off(old_crtc_state);
1911 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1913 return IS_GEN2(dev_priv) ? 2048 : 4096;
1917 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1919 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1920 unsigned int cpp = fb->format->cpp[plane];
1922 switch (fb->modifier) {
1923 case DRM_FORMAT_MOD_LINEAR:
1925 case I915_FORMAT_MOD_X_TILED:
1926 if (IS_GEN2(dev_priv))
1930 case I915_FORMAT_MOD_Y_TILED_CCS:
1934 case I915_FORMAT_MOD_Y_TILED:
1935 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1939 case I915_FORMAT_MOD_Yf_TILED_CCS:
1943 case I915_FORMAT_MOD_Yf_TILED:
1959 MISSING_CASE(fb->modifier);
1965 intel_tile_height(const struct drm_framebuffer *fb, int plane)
1967 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1970 return intel_tile_size(to_i915(fb->dev)) /
1971 intel_tile_width_bytes(fb, plane);
1974 /* Return the tile dimensions in pixel units */
1975 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
1976 unsigned int *tile_width,
1977 unsigned int *tile_height)
1979 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
1980 unsigned int cpp = fb->format->cpp[plane];
1982 *tile_width = tile_width_bytes / cpp;
1983 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1987 intel_fb_align_height(const struct drm_framebuffer *fb,
1988 int plane, unsigned int height)
1990 unsigned int tile_height = intel_tile_height(fb, plane);
1992 return ALIGN(height, tile_height);
1995 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1997 unsigned int size = 0;
2000 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2001 size += rot_info->plane[i].width * rot_info->plane[i].height;
2007 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2008 const struct drm_framebuffer *fb,
2009 unsigned int rotation)
2011 view->type = I915_GGTT_VIEW_NORMAL;
2012 if (drm_rotation_90_or_270(rotation)) {
2013 view->type = I915_GGTT_VIEW_ROTATED;
2014 view->rotated = to_intel_framebuffer(fb)->rot_info;
2018 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2020 if (IS_I830(dev_priv))
2022 else if (IS_I85X(dev_priv))
2024 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2030 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2032 if (INTEL_GEN(dev_priv) >= 9)
2034 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2035 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2037 else if (INTEL_GEN(dev_priv) >= 4)
2043 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2046 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2048 /* AUX_DIST needs only 4K alignment */
2052 switch (fb->modifier) {
2053 case DRM_FORMAT_MOD_LINEAR:
2054 return intel_linear_alignment(dev_priv);
2055 case I915_FORMAT_MOD_X_TILED:
2056 if (INTEL_GEN(dev_priv) >= 9)
2059 case I915_FORMAT_MOD_Y_TILED_CCS:
2060 case I915_FORMAT_MOD_Yf_TILED_CCS:
2061 case I915_FORMAT_MOD_Y_TILED:
2062 case I915_FORMAT_MOD_Yf_TILED:
2063 return 1 * 1024 * 1024;
2065 MISSING_CASE(fb->modifier);
2070 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2072 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2073 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2075 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2079 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2080 unsigned int rotation,
2082 unsigned long *out_flags)
2084 struct drm_device *dev = fb->dev;
2085 struct drm_i915_private *dev_priv = to_i915(dev);
2086 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2087 struct i915_ggtt_view view;
2088 struct i915_vma *vma;
2089 unsigned int pinctl;
2092 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2094 alignment = intel_surf_alignment(fb, 0);
2096 intel_fill_fb_ggtt_view(&view, fb, rotation);
2098 /* Note that the w/a also requires 64 PTE of padding following the
2099 * bo. We currently fill all unused PTE with the shadow page and so
2100 * we should always have valid PTE following the scanout preventing
2103 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2104 alignment = 256 * 1024;
2107 * Global gtt pte registers are special registers which actually forward
2108 * writes to a chunk of system memory. Which means that there is no risk
2109 * that the register values disappear as soon as we call
2110 * intel_runtime_pm_put(), so it is correct to wrap only the
2111 * pin/unpin/fence and not more.
2113 intel_runtime_pm_get(dev_priv);
2115 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2119 /* Valleyview is definitely limited to scanning out the first
2120 * 512MiB. Lets presume this behaviour was inherited from the
2121 * g4x display engine and that all earlier gen are similarly
2122 * limited. Testing suggests that it is a little more
2123 * complicated than this. For example, Cherryview appears quite
2124 * happy to scanout from anywhere within its global aperture.
2126 if (HAS_GMCH_DISPLAY(dev_priv))
2127 pinctl |= PIN_MAPPABLE;
2129 vma = i915_gem_object_pin_to_display_plane(obj,
2130 alignment, &view, pinctl);
2134 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2137 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2138 * fence, whereas 965+ only requires a fence if using
2139 * framebuffer compression. For simplicity, we always, when
2140 * possible, install a fence as the cost is not that onerous.
2142 * If we fail to fence the tiled scanout, then either the
2143 * modeset will reject the change (which is highly unlikely as
2144 * the affected systems, all but one, do not have unmappable
2145 * space) or we will not be able to enable full powersaving
2146 * techniques (also likely not to apply due to various limits
2147 * FBC and the like impose on the size of the buffer, which
2148 * presumably we violated anyway with this unmappable buffer).
2149 * Anyway, it is presumably better to stumble onwards with
2150 * something and try to run the system in a "less than optimal"
2151 * mode that matches the user configuration.
2153 ret = i915_vma_pin_fence(vma);
2154 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2155 i915_gem_object_unpin_from_display_plane(vma);
2160 if (ret == 0 && vma->fence)
2161 *out_flags |= PLANE_HAS_FENCE;
2166 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2168 intel_runtime_pm_put(dev_priv);
2172 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2174 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2176 if (flags & PLANE_HAS_FENCE)
2177 i915_vma_unpin_fence(vma);
2178 i915_gem_object_unpin_from_display_plane(vma);
2182 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2183 unsigned int rotation)
2185 if (drm_rotation_90_or_270(rotation))
2186 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2188 return fb->pitches[plane];
2192 * Convert the x/y offsets into a linear offset.
2193 * Only valid with 0/180 degree rotation, which is fine since linear
2194 * offset is only used with linear buffers on pre-hsw and tiled buffers
2195 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2197 u32 intel_fb_xy_to_linear(int x, int y,
2198 const struct intel_plane_state *state,
2201 const struct drm_framebuffer *fb = state->base.fb;
2202 unsigned int cpp = fb->format->cpp[plane];
2203 unsigned int pitch = fb->pitches[plane];
2205 return y * pitch + x * cpp;
2209 * Add the x/y offsets derived from fb->offsets[] to the user
2210 * specified plane src x/y offsets. The resulting x/y offsets
2211 * specify the start of scanout from the beginning of the gtt mapping.
2213 void intel_add_fb_offsets(int *x, int *y,
2214 const struct intel_plane_state *state,
2218 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2219 unsigned int rotation = state->base.rotation;
2221 if (drm_rotation_90_or_270(rotation)) {
2222 *x += intel_fb->rotated[plane].x;
2223 *y += intel_fb->rotated[plane].y;
2225 *x += intel_fb->normal[plane].x;
2226 *y += intel_fb->normal[plane].y;
2230 static u32 __intel_adjust_tile_offset(int *x, int *y,
2231 unsigned int tile_width,
2232 unsigned int tile_height,
2233 unsigned int tile_size,
2234 unsigned int pitch_tiles,
2238 unsigned int pitch_pixels = pitch_tiles * tile_width;
2241 WARN_ON(old_offset & (tile_size - 1));
2242 WARN_ON(new_offset & (tile_size - 1));
2243 WARN_ON(new_offset > old_offset);
2245 tiles = (old_offset - new_offset) / tile_size;
2247 *y += tiles / pitch_tiles * tile_height;
2248 *x += tiles % pitch_tiles * tile_width;
2250 /* minimize x in case it got needlessly big */
2251 *y += *x / pitch_pixels * tile_height;
2257 static u32 _intel_adjust_tile_offset(int *x, int *y,
2258 const struct drm_framebuffer *fb, int plane,
2259 unsigned int rotation,
2260 u32 old_offset, u32 new_offset)
2262 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2263 unsigned int cpp = fb->format->cpp[plane];
2264 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2266 WARN_ON(new_offset > old_offset);
2268 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2269 unsigned int tile_size, tile_width, tile_height;
2270 unsigned int pitch_tiles;
2272 tile_size = intel_tile_size(dev_priv);
2273 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2275 if (drm_rotation_90_or_270(rotation)) {
2276 pitch_tiles = pitch / tile_height;
2277 swap(tile_width, tile_height);
2279 pitch_tiles = pitch / (tile_width * cpp);
2282 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2283 tile_size, pitch_tiles,
2284 old_offset, new_offset);
2286 old_offset += *y * pitch + *x * cpp;
2288 *y = (old_offset - new_offset) / pitch;
2289 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2296 * Adjust the tile offset by moving the difference into
2299 static u32 intel_adjust_tile_offset(int *x, int *y,
2300 const struct intel_plane_state *state, int plane,
2301 u32 old_offset, u32 new_offset)
2303 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2304 state->base.rotation,
2305 old_offset, new_offset);
2309 * Computes the linear offset to the base tile and adjusts
2310 * x, y. bytes per pixel is assumed to be a power-of-two.
2312 * In the 90/270 rotated case, x and y are assumed
2313 * to be already rotated to match the rotated GTT view, and
2314 * pitch is the tile_height aligned framebuffer height.
2316 * This function is used when computing the derived information
2317 * under intel_framebuffer, so using any of that information
2318 * here is not allowed. Anything under drm_framebuffer can be
2319 * used. This is why the user has to pass in the pitch since it
2320 * is specified in the rotated orientation.
2322 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2324 const struct drm_framebuffer *fb, int plane,
2326 unsigned int rotation,
2329 uint64_t fb_modifier = fb->modifier;
2330 unsigned int cpp = fb->format->cpp[plane];
2331 u32 offset, offset_aligned;
2336 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2337 unsigned int tile_size, tile_width, tile_height;
2338 unsigned int tile_rows, tiles, pitch_tiles;
2340 tile_size = intel_tile_size(dev_priv);
2341 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2343 if (drm_rotation_90_or_270(rotation)) {
2344 pitch_tiles = pitch / tile_height;
2345 swap(tile_width, tile_height);
2347 pitch_tiles = pitch / (tile_width * cpp);
2350 tile_rows = *y / tile_height;
2353 tiles = *x / tile_width;
2356 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2357 offset_aligned = offset & ~alignment;
2359 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2360 tile_size, pitch_tiles,
2361 offset, offset_aligned);
2363 offset = *y * pitch + *x * cpp;
2364 offset_aligned = offset & ~alignment;
2366 *y = (offset & alignment) / pitch;
2367 *x = ((offset & alignment) - *y * pitch) / cpp;
2370 return offset_aligned;
2373 u32 intel_compute_tile_offset(int *x, int *y,
2374 const struct intel_plane_state *state,
2377 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2378 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2379 const struct drm_framebuffer *fb = state->base.fb;
2380 unsigned int rotation = state->base.rotation;
2381 int pitch = intel_fb_pitch(fb, plane, rotation);
2384 if (intel_plane->id == PLANE_CURSOR)
2385 alignment = intel_cursor_alignment(dev_priv);
2387 alignment = intel_surf_alignment(fb, plane);
2389 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2390 rotation, alignment);
2393 /* Convert the fb->offset[] into x/y offsets */
2394 static int intel_fb_offset_to_xy(int *x, int *y,
2395 const struct drm_framebuffer *fb, int plane)
2397 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2399 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2400 fb->offsets[plane] % intel_tile_size(dev_priv))
2406 _intel_adjust_tile_offset(x, y,
2407 fb, plane, DRM_MODE_ROTATE_0,
2408 fb->offsets[plane], 0);
2413 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2415 switch (fb_modifier) {
2416 case I915_FORMAT_MOD_X_TILED:
2417 return I915_TILING_X;
2418 case I915_FORMAT_MOD_Y_TILED:
2419 case I915_FORMAT_MOD_Y_TILED_CCS:
2420 return I915_TILING_Y;
2422 return I915_TILING_NONE;
2427 * From the Sky Lake PRM:
2428 * "The Color Control Surface (CCS) contains the compression status of
2429 * the cache-line pairs. The compression state of the cache-line pair
2430 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2431 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2432 * cache-line-pairs. CCS is always Y tiled."
2434 * Since cache line pairs refers to horizontally adjacent cache lines,
2435 * each cache line in the CCS corresponds to an area of 32x16 cache
2436 * lines on the main surface. Since each pixel is 4 bytes, this gives
2437 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2440 static const struct drm_format_info ccs_formats[] = {
2441 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2442 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2443 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2444 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2447 static const struct drm_format_info *
2448 lookup_format_info(const struct drm_format_info formats[],
2449 int num_formats, u32 format)
2453 for (i = 0; i < num_formats; i++) {
2454 if (formats[i].format == format)
2461 static const struct drm_format_info *
2462 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2464 switch (cmd->modifier[0]) {
2465 case I915_FORMAT_MOD_Y_TILED_CCS:
2466 case I915_FORMAT_MOD_Yf_TILED_CCS:
2467 return lookup_format_info(ccs_formats,
2468 ARRAY_SIZE(ccs_formats),
2476 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2477 struct drm_framebuffer *fb)
2479 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2480 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2481 u32 gtt_offset_rotated = 0;
2482 unsigned int max_size = 0;
2483 int i, num_planes = fb->format->num_planes;
2484 unsigned int tile_size = intel_tile_size(dev_priv);
2486 for (i = 0; i < num_planes; i++) {
2487 unsigned int width, height;
2488 unsigned int cpp, size;
2493 cpp = fb->format->cpp[i];
2494 width = drm_framebuffer_plane_width(fb->width, fb, i);
2495 height = drm_framebuffer_plane_height(fb->height, fb, i);
2497 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2499 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2504 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2505 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2506 int hsub = fb->format->hsub;
2507 int vsub = fb->format->vsub;
2508 int tile_width, tile_height;
2512 intel_tile_dims(fb, i, &tile_width, &tile_height);
2514 tile_height *= vsub;
2516 ccs_x = (x * hsub) % tile_width;
2517 ccs_y = (y * vsub) % tile_height;
2518 main_x = intel_fb->normal[0].x % tile_width;
2519 main_y = intel_fb->normal[0].y % tile_height;
2522 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2523 * x/y offsets must match between CCS and the main surface.
2525 if (main_x != ccs_x || main_y != ccs_y) {
2526 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2529 intel_fb->normal[0].x,
2530 intel_fb->normal[0].y,
2537 * The fence (if used) is aligned to the start of the object
2538 * so having the framebuffer wrap around across the edge of the
2539 * fenced region doesn't really work. We have no API to configure
2540 * the fence start offset within the object (nor could we probably
2541 * on gen2/3). So it's just easier if we just require that the
2542 * fb layout agrees with the fence layout. We already check that the
2543 * fb stride matches the fence stride elsewhere.
2545 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2546 (x + width) * cpp > fb->pitches[i]) {
2547 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2553 * First pixel of the framebuffer from
2554 * the start of the normal gtt mapping.
2556 intel_fb->normal[i].x = x;
2557 intel_fb->normal[i].y = y;
2559 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2560 fb, i, fb->pitches[i],
2561 DRM_MODE_ROTATE_0, tile_size);
2562 offset /= tile_size;
2564 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2565 unsigned int tile_width, tile_height;
2566 unsigned int pitch_tiles;
2569 intel_tile_dims(fb, i, &tile_width, &tile_height);
2571 rot_info->plane[i].offset = offset;
2572 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2573 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2574 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2576 intel_fb->rotated[i].pitch =
2577 rot_info->plane[i].height * tile_height;
2579 /* how many tiles does this plane need */
2580 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2582 * If the plane isn't horizontally tile aligned,
2583 * we need one more tile.
2588 /* rotate the x/y offsets to match the GTT view */
2594 rot_info->plane[i].width * tile_width,
2595 rot_info->plane[i].height * tile_height,
2596 DRM_MODE_ROTATE_270);
2600 /* rotate the tile dimensions to match the GTT view */
2601 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2602 swap(tile_width, tile_height);
2605 * We only keep the x/y offsets, so push all of the
2606 * gtt offset into the x/y offsets.
2608 __intel_adjust_tile_offset(&x, &y,
2609 tile_width, tile_height,
2610 tile_size, pitch_tiles,
2611 gtt_offset_rotated * tile_size, 0);
2613 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2616 * First pixel of the framebuffer from
2617 * the start of the rotated gtt mapping.
2619 intel_fb->rotated[i].x = x;
2620 intel_fb->rotated[i].y = y;
2622 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2623 x * cpp, tile_size);
2626 /* how many tiles in total needed in the bo */
2627 max_size = max(max_size, offset + size);
2630 if (max_size * tile_size > intel_fb->obj->base.size) {
2631 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2632 max_size * tile_size, intel_fb->obj->base.size);
2639 static int i9xx_format_to_fourcc(int format)
2642 case DISPPLANE_8BPP:
2643 return DRM_FORMAT_C8;
2644 case DISPPLANE_BGRX555:
2645 return DRM_FORMAT_XRGB1555;
2646 case DISPPLANE_BGRX565:
2647 return DRM_FORMAT_RGB565;
2649 case DISPPLANE_BGRX888:
2650 return DRM_FORMAT_XRGB8888;
2651 case DISPPLANE_RGBX888:
2652 return DRM_FORMAT_XBGR8888;
2653 case DISPPLANE_BGRX101010:
2654 return DRM_FORMAT_XRGB2101010;
2655 case DISPPLANE_RGBX101010:
2656 return DRM_FORMAT_XBGR2101010;
2660 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2663 case PLANE_CTL_FORMAT_RGB_565:
2664 return DRM_FORMAT_RGB565;
2666 case PLANE_CTL_FORMAT_XRGB_8888:
2669 return DRM_FORMAT_ABGR8888;
2671 return DRM_FORMAT_XBGR8888;
2674 return DRM_FORMAT_ARGB8888;
2676 return DRM_FORMAT_XRGB8888;
2678 case PLANE_CTL_FORMAT_XRGB_2101010:
2680 return DRM_FORMAT_XBGR2101010;
2682 return DRM_FORMAT_XRGB2101010;
2687 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2688 struct intel_initial_plane_config *plane_config)
2690 struct drm_device *dev = crtc->base.dev;
2691 struct drm_i915_private *dev_priv = to_i915(dev);
2692 struct drm_i915_gem_object *obj = NULL;
2693 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2694 struct drm_framebuffer *fb = &plane_config->fb->base;
2695 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2696 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2699 size_aligned -= base_aligned;
2701 if (plane_config->size == 0)
2704 /* If the FB is too big, just don't use it since fbdev is not very
2705 * important and we should probably use that space with FBC or other
2707 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2710 mutex_lock(&dev->struct_mutex);
2711 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2715 mutex_unlock(&dev->struct_mutex);
2719 if (plane_config->tiling == I915_TILING_X)
2720 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2722 mode_cmd.pixel_format = fb->format->format;
2723 mode_cmd.width = fb->width;
2724 mode_cmd.height = fb->height;
2725 mode_cmd.pitches[0] = fb->pitches[0];
2726 mode_cmd.modifier[0] = fb->modifier;
2727 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2729 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2730 DRM_DEBUG_KMS("intel fb init failed\n");
2735 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2739 i915_gem_object_put(obj);
2744 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2745 struct intel_plane_state *plane_state,
2748 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2750 plane_state->base.visible = visible;
2752 /* FIXME pre-g4x don't work like this */
2754 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2755 crtc_state->active_planes |= BIT(plane->id);
2757 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2758 crtc_state->active_planes &= ~BIT(plane->id);
2761 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2762 crtc_state->base.crtc->name,
2763 crtc_state->active_planes);
2766 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2767 struct intel_plane *plane)
2769 struct intel_crtc_state *crtc_state =
2770 to_intel_crtc_state(crtc->base.state);
2771 struct intel_plane_state *plane_state =
2772 to_intel_plane_state(plane->base.state);
2774 intel_set_plane_visible(crtc_state, plane_state, false);
2776 if (plane->id == PLANE_PRIMARY)
2777 intel_pre_disable_primary_noatomic(&crtc->base);
2779 trace_intel_disable_plane(&plane->base, crtc);
2780 plane->disable_plane(plane, crtc);
2784 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2785 struct intel_initial_plane_config *plane_config)
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = to_i915(dev);
2790 struct drm_i915_gem_object *obj;
2791 struct drm_plane *primary = intel_crtc->base.primary;
2792 struct drm_plane_state *plane_state = primary->state;
2793 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2794 struct intel_plane *intel_plane = to_intel_plane(primary);
2795 struct intel_plane_state *intel_state =
2796 to_intel_plane_state(plane_state);
2797 struct drm_framebuffer *fb;
2799 if (!plane_config->fb)
2802 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2803 fb = &plane_config->fb->base;
2807 kfree(plane_config->fb);
2810 * Failed to alloc the obj, check to see if we should share
2811 * an fb with another CRTC instead
2813 for_each_crtc(dev, c) {
2814 struct intel_plane_state *state;
2816 if (c == &intel_crtc->base)
2819 if (!to_intel_crtc(c)->active)
2822 state = to_intel_plane_state(c->primary->state);
2826 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2827 fb = state->base.fb;
2828 drm_framebuffer_get(fb);
2834 * We've failed to reconstruct the BIOS FB. Current display state
2835 * indicates that the primary plane is visible, but has a NULL FB,
2836 * which will lead to problems later if we don't fix it up. The
2837 * simplest solution is to just disable the primary plane now and
2838 * pretend the BIOS never had it enabled.
2840 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2845 mutex_lock(&dev->struct_mutex);
2847 intel_pin_and_fence_fb_obj(fb,
2848 primary->state->rotation,
2849 intel_plane_uses_fence(intel_state),
2850 &intel_state->flags);
2851 mutex_unlock(&dev->struct_mutex);
2852 if (IS_ERR(intel_state->vma)) {
2853 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2854 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2856 intel_state->vma = NULL;
2857 drm_framebuffer_put(fb);
2861 plane_state->src_x = 0;
2862 plane_state->src_y = 0;
2863 plane_state->src_w = fb->width << 16;
2864 plane_state->src_h = fb->height << 16;
2866 plane_state->crtc_x = 0;
2867 plane_state->crtc_y = 0;
2868 plane_state->crtc_w = fb->width;
2869 plane_state->crtc_h = fb->height;
2871 intel_state->base.src = drm_plane_state_src(plane_state);
2872 intel_state->base.dst = drm_plane_state_dest(plane_state);
2874 obj = intel_fb_obj(fb);
2875 if (i915_gem_object_is_tiled(obj))
2876 dev_priv->preserve_bios_swizzle = true;
2878 drm_framebuffer_get(fb);
2879 primary->fb = primary->state->fb = fb;
2880 primary->crtc = primary->state->crtc = &intel_crtc->base;
2882 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2883 to_intel_plane_state(plane_state),
2886 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2887 &obj->frontbuffer_bits);
2890 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2891 unsigned int rotation)
2893 int cpp = fb->format->cpp[plane];
2895 switch (fb->modifier) {
2896 case DRM_FORMAT_MOD_LINEAR:
2897 case I915_FORMAT_MOD_X_TILED:
2910 case I915_FORMAT_MOD_Y_TILED_CCS:
2911 case I915_FORMAT_MOD_Yf_TILED_CCS:
2912 /* FIXME AUX plane? */
2913 case I915_FORMAT_MOD_Y_TILED:
2914 case I915_FORMAT_MOD_Yf_TILED:
2929 MISSING_CASE(fb->modifier);
2935 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2936 int main_x, int main_y, u32 main_offset)
2938 const struct drm_framebuffer *fb = plane_state->base.fb;
2939 int hsub = fb->format->hsub;
2940 int vsub = fb->format->vsub;
2941 int aux_x = plane_state->aux.x;
2942 int aux_y = plane_state->aux.y;
2943 u32 aux_offset = plane_state->aux.offset;
2944 u32 alignment = intel_surf_alignment(fb, 1);
2946 while (aux_offset >= main_offset && aux_y <= main_y) {
2949 if (aux_x == main_x && aux_y == main_y)
2952 if (aux_offset == 0)
2957 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2958 aux_offset, aux_offset - alignment);
2959 aux_x = x * hsub + aux_x % hsub;
2960 aux_y = y * vsub + aux_y % vsub;
2963 if (aux_x != main_x || aux_y != main_y)
2966 plane_state->aux.offset = aux_offset;
2967 plane_state->aux.x = aux_x;
2968 plane_state->aux.y = aux_y;
2973 static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
2974 struct intel_plane_state *plane_state)
2976 struct drm_i915_private *dev_priv =
2977 to_i915(plane_state->base.plane->dev);
2978 const struct drm_framebuffer *fb = plane_state->base.fb;
2979 unsigned int rotation = plane_state->base.rotation;
2980 int x = plane_state->base.src.x1 >> 16;
2981 int y = plane_state->base.src.y1 >> 16;
2982 int w = drm_rect_width(&plane_state->base.src) >> 16;
2983 int h = drm_rect_height(&plane_state->base.src) >> 16;
2984 int dst_x = plane_state->base.dst.x1;
2985 int pipe_src_w = crtc_state->pipe_src_w;
2986 int max_width = skl_max_plane_width(fb, 0, rotation);
2987 int max_height = 4096;
2988 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2990 if (w > max_width || h > max_height) {
2991 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2992 w, h, max_width, max_height);
2997 * Display WA #1175: cnl,glk
2998 * Planes other than the cursor may cause FIFO underflow and display
2999 * corruption if starting less than 4 pixels from the right edge of
3001 * Besides the above WA fix the similar problem, where planes other
3002 * than the cursor ending less than 4 pixels from the left edge of the
3003 * screen may cause FIFO underflow and display corruption.
3005 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3006 (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
3007 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
3008 dst_x + w < 4 ? "end" : "start",
3009 dst_x + w < 4 ? dst_x + w : dst_x,
3014 intel_add_fb_offsets(&x, &y, plane_state, 0);
3015 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3016 alignment = intel_surf_alignment(fb, 0);
3019 * AUX surface offset is specified as the distance from the
3020 * main surface offset, and it must be non-negative. Make
3021 * sure that is what we will get.
3023 if (offset > aux_offset)
3024 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3025 offset, aux_offset & ~(alignment - 1));
3028 * When using an X-tiled surface, the plane blows up
3029 * if the x offset + width exceed the stride.
3031 * TODO: linear and Y-tiled seem fine, Yf untested,
3033 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3034 int cpp = fb->format->cpp[0];
3036 while ((x + w) * cpp > fb->pitches[0]) {
3038 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3042 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3043 offset, offset - alignment);
3048 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3049 * they match with the main surface x/y offsets.
3051 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3052 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3053 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3057 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3058 offset, offset - alignment);
3061 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3062 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3067 plane_state->main.offset = offset;
3068 plane_state->main.x = x;
3069 plane_state->main.y = y;
3074 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3076 const struct drm_framebuffer *fb = plane_state->base.fb;
3077 unsigned int rotation = plane_state->base.rotation;
3078 int max_width = skl_max_plane_width(fb, 1, rotation);
3079 int max_height = 4096;
3080 int x = plane_state->base.src.x1 >> 17;
3081 int y = plane_state->base.src.y1 >> 17;
3082 int w = drm_rect_width(&plane_state->base.src) >> 17;
3083 int h = drm_rect_height(&plane_state->base.src) >> 17;
3086 intel_add_fb_offsets(&x, &y, plane_state, 1);
3087 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3089 /* FIXME not quite sure how/if these apply to the chroma plane */
3090 if (w > max_width || h > max_height) {
3091 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3092 w, h, max_width, max_height);
3096 plane_state->aux.offset = offset;
3097 plane_state->aux.x = x;
3098 plane_state->aux.y = y;
3103 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3105 const struct drm_framebuffer *fb = plane_state->base.fb;
3106 int src_x = plane_state->base.src.x1 >> 16;
3107 int src_y = plane_state->base.src.y1 >> 16;
3108 int hsub = fb->format->hsub;
3109 int vsub = fb->format->vsub;
3110 int x = src_x / hsub;
3111 int y = src_y / vsub;
3114 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3115 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3116 plane_state->base.rotation);
3120 intel_add_fb_offsets(&x, &y, plane_state, 1);
3121 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3123 plane_state->aux.offset = offset;
3124 plane_state->aux.x = x * hsub + src_x % hsub;
3125 plane_state->aux.y = y * vsub + src_y % vsub;
3130 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
3131 struct intel_plane_state *plane_state)
3133 const struct drm_framebuffer *fb = plane_state->base.fb;
3134 unsigned int rotation = plane_state->base.rotation;
3137 if (rotation & DRM_MODE_REFLECT_X &&
3138 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
3139 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
3143 if (!plane_state->base.visible)
3146 /* Rotate src coordinates to match rotated GTT view */
3147 if (drm_rotation_90_or_270(rotation))
3148 drm_rect_rotate(&plane_state->base.src,
3149 fb->width << 16, fb->height << 16,
3150 DRM_MODE_ROTATE_270);
3153 * Handle the AUX surface first since
3154 * the main surface setup depends on it.
3156 if (fb->format->format == DRM_FORMAT_NV12) {
3157 ret = skl_check_nv12_aux_surface(plane_state);
3160 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3161 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3162 ret = skl_check_ccs_aux_surface(plane_state);
3166 plane_state->aux.offset = ~0xfff;
3167 plane_state->aux.x = 0;
3168 plane_state->aux.y = 0;
3171 ret = skl_check_main_surface(crtc_state, plane_state);
3178 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3179 const struct intel_plane_state *plane_state)
3181 struct drm_i915_private *dev_priv =
3182 to_i915(plane_state->base.plane->dev);
3183 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3184 const struct drm_framebuffer *fb = plane_state->base.fb;
3185 unsigned int rotation = plane_state->base.rotation;
3188 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3190 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3191 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3192 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3194 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3195 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3197 if (INTEL_GEN(dev_priv) < 5)
3198 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3200 switch (fb->format->format) {
3202 dspcntr |= DISPPLANE_8BPP;
3204 case DRM_FORMAT_XRGB1555:
3205 dspcntr |= DISPPLANE_BGRX555;
3207 case DRM_FORMAT_RGB565:
3208 dspcntr |= DISPPLANE_BGRX565;
3210 case DRM_FORMAT_XRGB8888:
3211 dspcntr |= DISPPLANE_BGRX888;
3213 case DRM_FORMAT_XBGR8888:
3214 dspcntr |= DISPPLANE_RGBX888;
3216 case DRM_FORMAT_XRGB2101010:
3217 dspcntr |= DISPPLANE_BGRX101010;
3219 case DRM_FORMAT_XBGR2101010:
3220 dspcntr |= DISPPLANE_RGBX101010;
3223 MISSING_CASE(fb->format->format);
3227 if (INTEL_GEN(dev_priv) >= 4 &&
3228 fb->modifier == I915_FORMAT_MOD_X_TILED)
3229 dspcntr |= DISPPLANE_TILED;
3231 if (rotation & DRM_MODE_ROTATE_180)
3232 dspcntr |= DISPPLANE_ROTATE_180;
3234 if (rotation & DRM_MODE_REFLECT_X)
3235 dspcntr |= DISPPLANE_MIRROR;
3240 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3242 struct drm_i915_private *dev_priv =
3243 to_i915(plane_state->base.plane->dev);
3244 int src_x = plane_state->base.src.x1 >> 16;
3245 int src_y = plane_state->base.src.y1 >> 16;
3248 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3250 if (INTEL_GEN(dev_priv) >= 4)
3251 offset = intel_compute_tile_offset(&src_x, &src_y,
3256 /* HSW/BDW do this automagically in hardware */
3257 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3258 unsigned int rotation = plane_state->base.rotation;
3259 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3260 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3262 if (rotation & DRM_MODE_ROTATE_180) {
3265 } else if (rotation & DRM_MODE_REFLECT_X) {
3270 plane_state->main.offset = offset;
3271 plane_state->main.x = src_x;
3272 plane_state->main.y = src_y;
3277 static void i9xx_update_plane(struct intel_plane *plane,
3278 const struct intel_crtc_state *crtc_state,
3279 const struct intel_plane_state *plane_state)
3281 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3282 const struct drm_framebuffer *fb = plane_state->base.fb;
3283 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3285 u32 dspcntr = plane_state->ctl;
3286 i915_reg_t reg = DSPCNTR(i9xx_plane);
3287 int x = plane_state->main.x;
3288 int y = plane_state->main.y;
3289 unsigned long irqflags;
3292 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3294 if (INTEL_GEN(dev_priv) >= 4)
3295 dspaddr_offset = plane_state->main.offset;
3297 dspaddr_offset = linear_offset;
3299 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3301 if (INTEL_GEN(dev_priv) < 4) {
3302 /* pipesrc and dspsize control the size that is scaled from,
3303 * which should always be the user's requested size.
3305 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3306 ((crtc_state->pipe_src_h - 1) << 16) |
3307 (crtc_state->pipe_src_w - 1));
3308 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3309 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3310 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3311 ((crtc_state->pipe_src_h - 1) << 16) |
3312 (crtc_state->pipe_src_w - 1));
3313 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3314 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3317 I915_WRITE_FW(reg, dspcntr);
3319 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
3320 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3321 I915_WRITE_FW(DSPSURF(i9xx_plane),
3322 intel_plane_ggtt_offset(plane_state) +
3324 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3325 } else if (INTEL_GEN(dev_priv) >= 4) {
3326 I915_WRITE_FW(DSPSURF(i9xx_plane),
3327 intel_plane_ggtt_offset(plane_state) +
3329 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3330 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3332 I915_WRITE_FW(DSPADDR(i9xx_plane),
3333 intel_plane_ggtt_offset(plane_state) +
3336 POSTING_READ_FW(reg);
3338 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3341 static void i9xx_disable_plane(struct intel_plane *plane,
3342 struct intel_crtc *crtc)
3344 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3345 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3346 unsigned long irqflags;
3348 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3350 I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3351 if (INTEL_GEN(dev_priv) >= 4)
3352 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3354 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3355 POSTING_READ_FW(DSPCNTR(i9xx_plane));
3357 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3360 static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
3362 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3363 enum intel_display_power_domain power_domain;
3364 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3365 enum pipe pipe = plane->pipe;
3369 * Not 100% correct for planes that can move between pipes,
3370 * but that's only the case for gen2-4 which don't have any
3371 * display power wells.
3373 power_domain = POWER_DOMAIN_PIPE(pipe);
3374 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3377 ret = I915_READ(DSPCNTR(i9xx_plane)) & DISPLAY_PLANE_ENABLE;
3379 intel_display_power_put(dev_priv, power_domain);
3385 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3387 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3390 return intel_tile_width_bytes(fb, plane);
3393 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3395 struct drm_device *dev = intel_crtc->base.dev;
3396 struct drm_i915_private *dev_priv = to_i915(dev);
3398 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3399 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3400 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3404 * This function detaches (aka. unbinds) unused scalers in hardware
3406 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3408 struct intel_crtc_scaler_state *scaler_state;
3411 scaler_state = &intel_crtc->config->scaler_state;
3413 /* loop through and disable scalers that aren't in use */
3414 for (i = 0; i < intel_crtc->num_scalers; i++) {
3415 if (!scaler_state->scalers[i].in_use)
3416 skl_detach_scaler(intel_crtc, i);
3420 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3421 unsigned int rotation)
3425 if (plane >= fb->format->num_planes)
3428 stride = intel_fb_pitch(fb, plane, rotation);
3431 * The stride is either expressed as a multiple of 64 bytes chunks for
3432 * linear buffers or in number of tiles for tiled buffers.
3434 if (drm_rotation_90_or_270(rotation))
3435 stride /= intel_tile_height(fb, plane);
3437 stride /= intel_fb_stride_alignment(fb, plane);
3442 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3444 switch (pixel_format) {
3446 return PLANE_CTL_FORMAT_INDEXED;
3447 case DRM_FORMAT_RGB565:
3448 return PLANE_CTL_FORMAT_RGB_565;
3449 case DRM_FORMAT_XBGR8888:
3450 case DRM_FORMAT_ABGR8888:
3451 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3452 case DRM_FORMAT_XRGB8888:
3453 case DRM_FORMAT_ARGB8888:
3454 return PLANE_CTL_FORMAT_XRGB_8888;
3455 case DRM_FORMAT_XRGB2101010:
3456 return PLANE_CTL_FORMAT_XRGB_2101010;
3457 case DRM_FORMAT_XBGR2101010:
3458 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3459 case DRM_FORMAT_YUYV:
3460 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3461 case DRM_FORMAT_YVYU:
3462 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3463 case DRM_FORMAT_UYVY:
3464 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3465 case DRM_FORMAT_VYUY:
3466 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3468 MISSING_CASE(pixel_format);
3475 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3476 * to be already pre-multiplied. We need to add a knob (or a different
3477 * DRM_FORMAT) for user-space to configure that.
3479 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3481 switch (pixel_format) {
3482 case DRM_FORMAT_ABGR8888:
3483 case DRM_FORMAT_ARGB8888:
3484 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3486 return PLANE_CTL_ALPHA_DISABLE;
3490 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3492 switch (pixel_format) {
3493 case DRM_FORMAT_ABGR8888:
3494 case DRM_FORMAT_ARGB8888:
3495 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3497 return PLANE_COLOR_ALPHA_DISABLE;
3501 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3503 switch (fb_modifier) {
3504 case DRM_FORMAT_MOD_LINEAR:
3506 case I915_FORMAT_MOD_X_TILED:
3507 return PLANE_CTL_TILED_X;
3508 case I915_FORMAT_MOD_Y_TILED:
3509 return PLANE_CTL_TILED_Y;
3510 case I915_FORMAT_MOD_Y_TILED_CCS:
3511 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3512 case I915_FORMAT_MOD_Yf_TILED:
3513 return PLANE_CTL_TILED_YF;
3514 case I915_FORMAT_MOD_Yf_TILED_CCS:
3515 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3517 MISSING_CASE(fb_modifier);
3523 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3526 case DRM_MODE_ROTATE_0:
3529 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3530 * while i915 HW rotation is clockwise, thats why this swapping.
3532 case DRM_MODE_ROTATE_90:
3533 return PLANE_CTL_ROTATE_270;
3534 case DRM_MODE_ROTATE_180:
3535 return PLANE_CTL_ROTATE_180;
3536 case DRM_MODE_ROTATE_270:
3537 return PLANE_CTL_ROTATE_90;
3539 MISSING_CASE(rotate);
3545 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3550 case DRM_MODE_REFLECT_X:
3551 return PLANE_CTL_FLIP_HORIZONTAL;
3552 case DRM_MODE_REFLECT_Y:
3554 MISSING_CASE(reflect);
3560 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3561 const struct intel_plane_state *plane_state)
3563 struct drm_i915_private *dev_priv =
3564 to_i915(plane_state->base.plane->dev);
3565 const struct drm_framebuffer *fb = plane_state->base.fb;
3566 unsigned int rotation = plane_state->base.rotation;
3567 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3570 plane_ctl = PLANE_CTL_ENABLE;
3572 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3573 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3575 PLANE_CTL_PIPE_GAMMA_ENABLE |
3576 PLANE_CTL_PIPE_CSC_ENABLE |
3577 PLANE_CTL_PLANE_GAMMA_DISABLE;
3579 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3580 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3582 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3583 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3586 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3587 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3588 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3590 if (INTEL_GEN(dev_priv) >= 10)
3591 plane_ctl |= cnl_plane_ctl_flip(rotation &
3592 DRM_MODE_REFLECT_MASK);
3594 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3595 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3596 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3597 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3602 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3603 const struct intel_plane_state *plane_state)
3605 const struct drm_framebuffer *fb = plane_state->base.fb;
3606 u32 plane_color_ctl = 0;
3608 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3609 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3610 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3611 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3613 if (intel_format_is_yuv(fb->format->format)) {
3614 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3615 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3617 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3619 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3620 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3623 return plane_color_ctl;
3627 __intel_display_resume(struct drm_device *dev,
3628 struct drm_atomic_state *state,
3629 struct drm_modeset_acquire_ctx *ctx)
3631 struct drm_crtc_state *crtc_state;
3632 struct drm_crtc *crtc;
3635 intel_modeset_setup_hw_state(dev, ctx);
3636 i915_redisable_vga(to_i915(dev));
3642 * We've duplicated the state, pointers to the old state are invalid.
3644 * Don't attempt to use the old state until we commit the duplicated state.
3646 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3648 * Force recalculation even if we restore
3649 * current state. With fast modeset this may not result
3650 * in a modeset when the state is compatible.
3652 crtc_state->mode_changed = true;
3655 /* ignore any reset values/BIOS leftovers in the WM registers */
3656 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3657 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3659 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3661 WARN_ON(ret == -EDEADLK);
3665 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3667 return intel_has_gpu_reset(dev_priv) &&
3668 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3671 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3673 struct drm_device *dev = &dev_priv->drm;
3674 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3675 struct drm_atomic_state *state;
3679 /* reset doesn't touch the display */
3680 if (!i915_modparams.force_reset_modeset_test &&
3681 !gpu_reset_clobbers_display(dev_priv))
3684 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3685 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3686 wake_up_all(&dev_priv->gpu_error.wait_queue);
3688 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3689 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3690 i915_gem_set_wedged(dev_priv);
3694 * Need mode_config.mutex so that we don't
3695 * trample ongoing ->detect() and whatnot.
3697 mutex_lock(&dev->mode_config.mutex);
3698 drm_modeset_acquire_init(ctx, 0);
3700 ret = drm_modeset_lock_all_ctx(dev, ctx);
3701 if (ret != -EDEADLK)
3704 drm_modeset_backoff(ctx);
3707 * Disabling the crtcs gracefully seems nicer. Also the
3708 * g33 docs say we should at least disable all the planes.
3710 state = drm_atomic_helper_duplicate_state(dev, ctx);
3711 if (IS_ERR(state)) {
3712 ret = PTR_ERR(state);
3713 DRM_ERROR("Duplicating state failed with %i\n", ret);
3717 ret = drm_atomic_helper_disable_all(dev, ctx);
3719 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3720 drm_atomic_state_put(state);
3724 dev_priv->modeset_restore_state = state;
3725 state->acquire_ctx = ctx;
3728 void intel_finish_reset(struct drm_i915_private *dev_priv)
3730 struct drm_device *dev = &dev_priv->drm;
3731 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3732 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3735 /* reset doesn't touch the display */
3736 if (!i915_modparams.force_reset_modeset_test &&
3737 !gpu_reset_clobbers_display(dev_priv))
3743 dev_priv->modeset_restore_state = NULL;
3745 /* reset doesn't touch the display */
3746 if (!gpu_reset_clobbers_display(dev_priv)) {
3747 /* for testing only restore the display */
3748 ret = __intel_display_resume(dev, state, ctx);
3750 DRM_ERROR("Restoring old state failed with %i\n", ret);
3753 * The display has been reset as well,
3754 * so need a full re-initialization.
3756 intel_runtime_pm_disable_interrupts(dev_priv);
3757 intel_runtime_pm_enable_interrupts(dev_priv);
3759 intel_pps_unlock_regs_wa(dev_priv);
3760 intel_modeset_init_hw(dev);
3761 intel_init_clock_gating(dev_priv);
3763 spin_lock_irq(&dev_priv->irq_lock);
3764 if (dev_priv->display.hpd_irq_setup)
3765 dev_priv->display.hpd_irq_setup(dev_priv);
3766 spin_unlock_irq(&dev_priv->irq_lock);
3768 ret = __intel_display_resume(dev, state, ctx);
3770 DRM_ERROR("Restoring old state failed with %i\n", ret);
3772 intel_hpd_init(dev_priv);
3775 drm_atomic_state_put(state);
3777 drm_modeset_drop_locks(ctx);
3778 drm_modeset_acquire_fini(ctx);
3779 mutex_unlock(&dev->mode_config.mutex);
3781 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3784 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3785 const struct intel_crtc_state *new_crtc_state)
3787 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3788 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3790 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3791 crtc->base.mode = new_crtc_state->base.mode;
3794 * Update pipe size and adjust fitter if needed: the reason for this is
3795 * that in compute_mode_changes we check the native mode (not the pfit
3796 * mode) to see if we can flip rather than do a full mode set. In the
3797 * fastboot case, we'll flip, but if we don't update the pipesrc and
3798 * pfit state, we'll end up with a big fb scanned out into the wrong
3802 I915_WRITE(PIPESRC(crtc->pipe),
3803 ((new_crtc_state->pipe_src_w - 1) << 16) |
3804 (new_crtc_state->pipe_src_h - 1));
3806 /* on skylake this is done by detaching scalers */
3807 if (INTEL_GEN(dev_priv) >= 9) {
3808 skl_detach_scalers(crtc);
3810 if (new_crtc_state->pch_pfit.enabled)
3811 skylake_pfit_enable(crtc);
3812 } else if (HAS_PCH_SPLIT(dev_priv)) {
3813 if (new_crtc_state->pch_pfit.enabled)
3814 ironlake_pfit_enable(crtc);
3815 else if (old_crtc_state->pch_pfit.enabled)
3816 ironlake_pfit_disable(crtc, true);
3820 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3822 struct drm_device *dev = crtc->base.dev;
3823 struct drm_i915_private *dev_priv = to_i915(dev);
3824 int pipe = crtc->pipe;
3828 /* enable normal train */
3829 reg = FDI_TX_CTL(pipe);
3830 temp = I915_READ(reg);
3831 if (IS_IVYBRIDGE(dev_priv)) {
3832 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3833 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3835 temp &= ~FDI_LINK_TRAIN_NONE;
3836 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3838 I915_WRITE(reg, temp);
3840 reg = FDI_RX_CTL(pipe);
3841 temp = I915_READ(reg);
3842 if (HAS_PCH_CPT(dev_priv)) {
3843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3844 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3846 temp &= ~FDI_LINK_TRAIN_NONE;
3847 temp |= FDI_LINK_TRAIN_NONE;
3849 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3851 /* wait one idle pattern time */
3855 /* IVB wants error correction enabled */
3856 if (IS_IVYBRIDGE(dev_priv))
3857 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3858 FDI_FE_ERRC_ENABLE);
3861 /* The FDI link training functions for ILK/Ibexpeak. */
3862 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3863 const struct intel_crtc_state *crtc_state)
3865 struct drm_device *dev = crtc->base.dev;
3866 struct drm_i915_private *dev_priv = to_i915(dev);
3867 int pipe = crtc->pipe;
3871 /* FDI needs bits from pipe first */
3872 assert_pipe_enabled(dev_priv, pipe);
3874 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3876 reg = FDI_RX_IMR(pipe);
3877 temp = I915_READ(reg);
3878 temp &= ~FDI_RX_SYMBOL_LOCK;
3879 temp &= ~FDI_RX_BIT_LOCK;
3880 I915_WRITE(reg, temp);
3884 /* enable CPU FDI TX and PCH FDI RX */
3885 reg = FDI_TX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3888 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3889 temp &= ~FDI_LINK_TRAIN_NONE;
3890 temp |= FDI_LINK_TRAIN_PATTERN_1;
3891 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3893 reg = FDI_RX_CTL(pipe);
3894 temp = I915_READ(reg);
3895 temp &= ~FDI_LINK_TRAIN_NONE;
3896 temp |= FDI_LINK_TRAIN_PATTERN_1;
3897 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3902 /* Ironlake workaround, enable clock pointer after FDI enable*/
3903 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3904 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3905 FDI_RX_PHASE_SYNC_POINTER_EN);
3907 reg = FDI_RX_IIR(pipe);
3908 for (tries = 0; tries < 5; tries++) {
3909 temp = I915_READ(reg);
3910 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3912 if ((temp & FDI_RX_BIT_LOCK)) {
3913 DRM_DEBUG_KMS("FDI train 1 done.\n");
3914 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3919 DRM_ERROR("FDI train 1 fail!\n");
3922 reg = FDI_TX_CTL(pipe);
3923 temp = I915_READ(reg);
3924 temp &= ~FDI_LINK_TRAIN_NONE;
3925 temp |= FDI_LINK_TRAIN_PATTERN_2;
3926 I915_WRITE(reg, temp);
3928 reg = FDI_RX_CTL(pipe);
3929 temp = I915_READ(reg);
3930 temp &= ~FDI_LINK_TRAIN_NONE;
3931 temp |= FDI_LINK_TRAIN_PATTERN_2;
3932 I915_WRITE(reg, temp);
3937 reg = FDI_RX_IIR(pipe);
3938 for (tries = 0; tries < 5; tries++) {
3939 temp = I915_READ(reg);
3940 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3942 if (temp & FDI_RX_SYMBOL_LOCK) {
3943 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3944 DRM_DEBUG_KMS("FDI train 2 done.\n");
3949 DRM_ERROR("FDI train 2 fail!\n");
3951 DRM_DEBUG_KMS("FDI train done\n");
3955 static const int snb_b_fdi_train_param[] = {
3956 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3957 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3958 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3959 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3962 /* The FDI link training functions for SNB/Cougarpoint. */
3963 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3964 const struct intel_crtc_state *crtc_state)
3966 struct drm_device *dev = crtc->base.dev;
3967 struct drm_i915_private *dev_priv = to_i915(dev);
3968 int pipe = crtc->pipe;
3972 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3974 reg = FDI_RX_IMR(pipe);
3975 temp = I915_READ(reg);
3976 temp &= ~FDI_RX_SYMBOL_LOCK;
3977 temp &= ~FDI_RX_BIT_LOCK;
3978 I915_WRITE(reg, temp);
3983 /* enable CPU FDI TX and PCH FDI RX */
3984 reg = FDI_TX_CTL(pipe);
3985 temp = I915_READ(reg);
3986 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3987 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3988 temp &= ~FDI_LINK_TRAIN_NONE;
3989 temp |= FDI_LINK_TRAIN_PATTERN_1;
3990 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3992 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3993 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3995 I915_WRITE(FDI_RX_MISC(pipe),
3996 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3998 reg = FDI_RX_CTL(pipe);
3999 temp = I915_READ(reg);
4000 if (HAS_PCH_CPT(dev_priv)) {
4001 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4002 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4004 temp &= ~FDI_LINK_TRAIN_NONE;
4005 temp |= FDI_LINK_TRAIN_PATTERN_1;
4007 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4012 for (i = 0; i < 4; i++) {
4013 reg = FDI_TX_CTL(pipe);
4014 temp = I915_READ(reg);
4015 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4016 temp |= snb_b_fdi_train_param[i];
4017 I915_WRITE(reg, temp);
4022 for (retry = 0; retry < 5; retry++) {
4023 reg = FDI_RX_IIR(pipe);
4024 temp = I915_READ(reg);
4025 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4026 if (temp & FDI_RX_BIT_LOCK) {
4027 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4028 DRM_DEBUG_KMS("FDI train 1 done.\n");
4037 DRM_ERROR("FDI train 1 fail!\n");
4040 reg = FDI_TX_CTL(pipe);
4041 temp = I915_READ(reg);
4042 temp &= ~FDI_LINK_TRAIN_NONE;
4043 temp |= FDI_LINK_TRAIN_PATTERN_2;
4044 if (IS_GEN6(dev_priv)) {
4045 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4047 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4049 I915_WRITE(reg, temp);
4051 reg = FDI_RX_CTL(pipe);
4052 temp = I915_READ(reg);
4053 if (HAS_PCH_CPT(dev_priv)) {
4054 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4055 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4057 temp &= ~FDI_LINK_TRAIN_NONE;
4058 temp |= FDI_LINK_TRAIN_PATTERN_2;
4060 I915_WRITE(reg, temp);
4065 for (i = 0; i < 4; i++) {
4066 reg = FDI_TX_CTL(pipe);
4067 temp = I915_READ(reg);
4068 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4069 temp |= snb_b_fdi_train_param[i];
4070 I915_WRITE(reg, temp);
4075 for (retry = 0; retry < 5; retry++) {
4076 reg = FDI_RX_IIR(pipe);
4077 temp = I915_READ(reg);
4078 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4079 if (temp & FDI_RX_SYMBOL_LOCK) {
4080 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4081 DRM_DEBUG_KMS("FDI train 2 done.\n");
4090 DRM_ERROR("FDI train 2 fail!\n");
4092 DRM_DEBUG_KMS("FDI train done.\n");
4095 /* Manual link training for Ivy Bridge A0 parts */
4096 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4097 const struct intel_crtc_state *crtc_state)
4099 struct drm_device *dev = crtc->base.dev;
4100 struct drm_i915_private *dev_priv = to_i915(dev);
4101 int pipe = crtc->pipe;
4105 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4107 reg = FDI_RX_IMR(pipe);
4108 temp = I915_READ(reg);
4109 temp &= ~FDI_RX_SYMBOL_LOCK;
4110 temp &= ~FDI_RX_BIT_LOCK;
4111 I915_WRITE(reg, temp);
4116 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4117 I915_READ(FDI_RX_IIR(pipe)));
4119 /* Try each vswing and preemphasis setting twice before moving on */
4120 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4121 /* disable first in case we need to retry */
4122 reg = FDI_TX_CTL(pipe);
4123 temp = I915_READ(reg);
4124 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4125 temp &= ~FDI_TX_ENABLE;
4126 I915_WRITE(reg, temp);
4128 reg = FDI_RX_CTL(pipe);
4129 temp = I915_READ(reg);
4130 temp &= ~FDI_LINK_TRAIN_AUTO;
4131 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4132 temp &= ~FDI_RX_ENABLE;
4133 I915_WRITE(reg, temp);
4135 /* enable CPU FDI TX and PCH FDI RX */
4136 reg = FDI_TX_CTL(pipe);
4137 temp = I915_READ(reg);
4138 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4139 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4140 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4141 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4142 temp |= snb_b_fdi_train_param[j/2];
4143 temp |= FDI_COMPOSITE_SYNC;
4144 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4146 I915_WRITE(FDI_RX_MISC(pipe),
4147 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4149 reg = FDI_RX_CTL(pipe);
4150 temp = I915_READ(reg);
4151 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4152 temp |= FDI_COMPOSITE_SYNC;
4153 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4156 udelay(1); /* should be 0.5us */
4158 for (i = 0; i < 4; i++) {
4159 reg = FDI_RX_IIR(pipe);
4160 temp = I915_READ(reg);
4161 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4163 if (temp & FDI_RX_BIT_LOCK ||
4164 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4165 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4166 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4170 udelay(1); /* should be 0.5us */
4173 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4178 reg = FDI_TX_CTL(pipe);
4179 temp = I915_READ(reg);
4180 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4181 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4182 I915_WRITE(reg, temp);
4184 reg = FDI_RX_CTL(pipe);
4185 temp = I915_READ(reg);
4186 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4187 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4188 I915_WRITE(reg, temp);
4191 udelay(2); /* should be 1.5us */
4193 for (i = 0; i < 4; i++) {
4194 reg = FDI_RX_IIR(pipe);
4195 temp = I915_READ(reg);
4196 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4198 if (temp & FDI_RX_SYMBOL_LOCK ||
4199 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4200 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4201 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4205 udelay(2); /* should be 1.5us */
4208 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4212 DRM_DEBUG_KMS("FDI train done.\n");
4215 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4217 struct drm_device *dev = intel_crtc->base.dev;
4218 struct drm_i915_private *dev_priv = to_i915(dev);
4219 int pipe = intel_crtc->pipe;
4223 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4224 reg = FDI_RX_CTL(pipe);
4225 temp = I915_READ(reg);
4226 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4227 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4228 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4229 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4234 /* Switch from Rawclk to PCDclk */
4235 temp = I915_READ(reg);
4236 I915_WRITE(reg, temp | FDI_PCDCLK);
4241 /* Enable CPU FDI TX PLL, always on for Ironlake */
4242 reg = FDI_TX_CTL(pipe);
4243 temp = I915_READ(reg);
4244 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4245 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4252 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4254 struct drm_device *dev = intel_crtc->base.dev;
4255 struct drm_i915_private *dev_priv = to_i915(dev);
4256 int pipe = intel_crtc->pipe;
4260 /* Switch from PCDclk to Rawclk */
4261 reg = FDI_RX_CTL(pipe);
4262 temp = I915_READ(reg);
4263 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4265 /* Disable CPU FDI TX PLL */
4266 reg = FDI_TX_CTL(pipe);
4267 temp = I915_READ(reg);
4268 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4273 reg = FDI_RX_CTL(pipe);
4274 temp = I915_READ(reg);
4275 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4277 /* Wait for the clocks to turn off. */
4282 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4284 struct drm_device *dev = crtc->dev;
4285 struct drm_i915_private *dev_priv = to_i915(dev);
4286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4287 int pipe = intel_crtc->pipe;
4291 /* disable CPU FDI tx and PCH FDI rx */
4292 reg = FDI_TX_CTL(pipe);
4293 temp = I915_READ(reg);
4294 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4297 reg = FDI_RX_CTL(pipe);
4298 temp = I915_READ(reg);
4299 temp &= ~(0x7 << 16);
4300 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4301 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4306 /* Ironlake workaround, disable clock pointer after downing FDI */
4307 if (HAS_PCH_IBX(dev_priv))
4308 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4310 /* still set train pattern 1 */
4311 reg = FDI_TX_CTL(pipe);
4312 temp = I915_READ(reg);
4313 temp &= ~FDI_LINK_TRAIN_NONE;
4314 temp |= FDI_LINK_TRAIN_PATTERN_1;
4315 I915_WRITE(reg, temp);
4317 reg = FDI_RX_CTL(pipe);
4318 temp = I915_READ(reg);
4319 if (HAS_PCH_CPT(dev_priv)) {
4320 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4321 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4323 temp &= ~FDI_LINK_TRAIN_NONE;
4324 temp |= FDI_LINK_TRAIN_PATTERN_1;
4326 /* BPC in FDI rx is consistent with that in PIPECONF */
4327 temp &= ~(0x07 << 16);
4328 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4329 I915_WRITE(reg, temp);
4335 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4337 struct drm_crtc *crtc;
4340 drm_for_each_crtc(crtc, &dev_priv->drm) {
4341 struct drm_crtc_commit *commit;
4342 spin_lock(&crtc->commit_lock);
4343 commit = list_first_entry_or_null(&crtc->commit_list,
4344 struct drm_crtc_commit, commit_entry);
4345 cleanup_done = commit ?
4346 try_wait_for_completion(&commit->cleanup_done) : true;
4347 spin_unlock(&crtc->commit_lock);
4352 drm_crtc_wait_one_vblank(crtc);
4360 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4364 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4366 mutex_lock(&dev_priv->sb_lock);
4368 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4369 temp |= SBI_SSCCTL_DISABLE;
4370 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4372 mutex_unlock(&dev_priv->sb_lock);
4375 /* Program iCLKIP clock to the desired frequency */
4376 static void lpt_program_iclkip(struct intel_crtc *crtc)
4378 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4379 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4380 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4383 lpt_disable_iclkip(dev_priv);
4385 /* The iCLK virtual clock root frequency is in MHz,
4386 * but the adjusted_mode->crtc_clock in in KHz. To get the
4387 * divisors, it is necessary to divide one by another, so we
4388 * convert the virtual clock precision to KHz here for higher
4391 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4392 u32 iclk_virtual_root_freq = 172800 * 1000;
4393 u32 iclk_pi_range = 64;
4394 u32 desired_divisor;
4396 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4398 divsel = (desired_divisor / iclk_pi_range) - 2;
4399 phaseinc = desired_divisor % iclk_pi_range;
4402 * Near 20MHz is a corner case which is
4403 * out of range for the 7-bit divisor
4409 /* This should not happen with any sane values */
4410 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4411 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4412 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4413 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4415 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4422 mutex_lock(&dev_priv->sb_lock);
4424 /* Program SSCDIVINTPHASE6 */
4425 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4426 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4427 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4428 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4429 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4430 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4431 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4432 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4434 /* Program SSCAUXDIV */
4435 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4436 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4437 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4438 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4440 /* Enable modulator and associated divider */
4441 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4442 temp &= ~SBI_SSCCTL_DISABLE;
4443 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4445 mutex_unlock(&dev_priv->sb_lock);
4447 /* Wait for initialization time */
4450 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4453 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4455 u32 divsel, phaseinc, auxdiv;
4456 u32 iclk_virtual_root_freq = 172800 * 1000;
4457 u32 iclk_pi_range = 64;
4458 u32 desired_divisor;
4461 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4464 mutex_lock(&dev_priv->sb_lock);
4466 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4467 if (temp & SBI_SSCCTL_DISABLE) {
4468 mutex_unlock(&dev_priv->sb_lock);
4472 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4473 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4474 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4475 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4476 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4478 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4479 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4480 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4482 mutex_unlock(&dev_priv->sb_lock);
4484 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4486 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4487 desired_divisor << auxdiv);
4490 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4491 enum pipe pch_transcoder)
4493 struct drm_device *dev = crtc->base.dev;
4494 struct drm_i915_private *dev_priv = to_i915(dev);
4495 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4497 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4498 I915_READ(HTOTAL(cpu_transcoder)));
4499 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4500 I915_READ(HBLANK(cpu_transcoder)));
4501 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4502 I915_READ(HSYNC(cpu_transcoder)));
4504 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4505 I915_READ(VTOTAL(cpu_transcoder)));
4506 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4507 I915_READ(VBLANK(cpu_transcoder)));
4508 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4509 I915_READ(VSYNC(cpu_transcoder)));
4510 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4511 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4514 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4516 struct drm_i915_private *dev_priv = to_i915(dev);
4519 temp = I915_READ(SOUTH_CHICKEN1);
4520 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4523 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4524 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4526 temp &= ~FDI_BC_BIFURCATION_SELECT;
4528 temp |= FDI_BC_BIFURCATION_SELECT;
4530 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4531 I915_WRITE(SOUTH_CHICKEN1, temp);
4532 POSTING_READ(SOUTH_CHICKEN1);
4535 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4537 struct drm_device *dev = intel_crtc->base.dev;
4539 switch (intel_crtc->pipe) {
4543 if (intel_crtc->config->fdi_lanes > 2)
4544 cpt_set_fdi_bc_bifurcation(dev, false);
4546 cpt_set_fdi_bc_bifurcation(dev, true);
4550 cpt_set_fdi_bc_bifurcation(dev, true);
4558 /* Return which DP Port should be selected for Transcoder DP control */
4560 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4562 struct drm_device *dev = crtc->base.dev;
4563 struct intel_encoder *encoder;
4565 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4566 if (encoder->type == INTEL_OUTPUT_DP ||
4567 encoder->type == INTEL_OUTPUT_EDP)
4568 return encoder->port;
4575 * Enable PCH resources required for PCH ports:
4577 * - FDI training & RX/TX
4578 * - update transcoder timings
4579 * - DP transcoding bits
4582 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4585 struct drm_device *dev = crtc->base.dev;
4586 struct drm_i915_private *dev_priv = to_i915(dev);
4587 int pipe = crtc->pipe;
4590 assert_pch_transcoder_disabled(dev_priv, pipe);
4592 if (IS_IVYBRIDGE(dev_priv))
4593 ivybridge_update_fdi_bc_bifurcation(crtc);
4595 /* Write the TU size bits before fdi link training, so that error
4596 * detection works. */
4597 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4598 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4600 /* For PCH output, training FDI link */
4601 dev_priv->display.fdi_link_train(crtc, crtc_state);
4603 /* We need to program the right clock selection before writing the pixel
4604 * mutliplier into the DPLL. */
4605 if (HAS_PCH_CPT(dev_priv)) {
4608 temp = I915_READ(PCH_DPLL_SEL);
4609 temp |= TRANS_DPLL_ENABLE(pipe);
4610 sel = TRANS_DPLLB_SEL(pipe);
4611 if (crtc_state->shared_dpll ==
4612 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4616 I915_WRITE(PCH_DPLL_SEL, temp);
4619 /* XXX: pch pll's can be enabled any time before we enable the PCH
4620 * transcoder, and we actually should do this to not upset any PCH
4621 * transcoder that already use the clock when we share it.
4623 * Note that enable_shared_dpll tries to do the right thing, but
4624 * get_shared_dpll unconditionally resets the pll - we need that to have
4625 * the right LVDS enable sequence. */
4626 intel_enable_shared_dpll(crtc);
4628 /* set transcoder timing, panel must allow it */
4629 assert_panel_unlocked(dev_priv, pipe);
4630 ironlake_pch_transcoder_set_timings(crtc, pipe);
4632 intel_fdi_normal_train(crtc);
4634 /* For PCH DP, enable TRANS_DP_CTL */
4635 if (HAS_PCH_CPT(dev_priv) &&
4636 intel_crtc_has_dp_encoder(crtc_state)) {
4637 const struct drm_display_mode *adjusted_mode =
4638 &crtc_state->base.adjusted_mode;
4639 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4640 i915_reg_t reg = TRANS_DP_CTL(pipe);
4641 temp = I915_READ(reg);
4642 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4643 TRANS_DP_SYNC_MASK |
4645 temp |= TRANS_DP_OUTPUT_ENABLE;
4646 temp |= bpc << 9; /* same format but at 11:9 */
4648 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4649 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4650 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4651 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4653 switch (intel_trans_dp_port_sel(crtc)) {
4655 temp |= TRANS_DP_PORT_SEL_B;
4658 temp |= TRANS_DP_PORT_SEL_C;
4661 temp |= TRANS_DP_PORT_SEL_D;
4667 I915_WRITE(reg, temp);
4670 ironlake_enable_pch_transcoder(dev_priv, pipe);
4673 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4676 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4677 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4679 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4681 lpt_program_iclkip(crtc);
4683 /* Set transcoder timing. */
4684 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4686 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4689 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4691 struct drm_i915_private *dev_priv = to_i915(dev);
4692 i915_reg_t dslreg = PIPEDSL(pipe);
4695 temp = I915_READ(dslreg);
4697 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4698 if (wait_for(I915_READ(dslreg) != temp, 5))
4699 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4704 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4705 unsigned int scaler_user, int *scaler_id,
4706 int src_w, int src_h, int dst_w, int dst_h)
4708 struct intel_crtc_scaler_state *scaler_state =
4709 &crtc_state->scaler_state;
4710 struct intel_crtc *intel_crtc =
4711 to_intel_crtc(crtc_state->base.crtc);
4712 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4713 const struct drm_display_mode *adjusted_mode =
4714 &crtc_state->base.adjusted_mode;
4718 * Src coordinates are already rotated by 270 degrees for
4719 * the 90/270 degree plane rotation cases (to match the
4720 * GTT mapping), hence no need to account for rotation here.
4722 need_scaling = src_w != dst_w || src_h != dst_h;
4724 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4725 need_scaling = true;
4728 * Scaling/fitting not supported in IF-ID mode in GEN9+
4729 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4730 * Once NV12 is enabled, handle it here while allocating scaler
4733 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4734 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4735 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4740 * if plane is being disabled or scaler is no more required or force detach
4741 * - free scaler binded to this plane/crtc
4742 * - in order to do this, update crtc->scaler_usage
4744 * Here scaler state in crtc_state is set free so that
4745 * scaler can be assigned to other user. Actual register
4746 * update to free the scaler is done in plane/panel-fit programming.
4747 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4749 if (force_detach || !need_scaling) {
4750 if (*scaler_id >= 0) {
4751 scaler_state->scaler_users &= ~(1 << scaler_user);
4752 scaler_state->scalers[*scaler_id].in_use = 0;
4754 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4755 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4756 intel_crtc->pipe, scaler_user, *scaler_id,
4757 scaler_state->scaler_users);
4764 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4765 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4767 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4768 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4769 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4770 "size is out of scaler range\n",
4771 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4775 /* mark this plane as a scaler user in crtc_state */
4776 scaler_state->scaler_users |= (1 << scaler_user);
4777 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4778 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4779 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4780 scaler_state->scaler_users);
4786 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4788 * @state: crtc's scaler state
4791 * 0 - scaler_usage updated successfully
4792 * error - requested scaling cannot be supported or other error condition
4794 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4796 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4798 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4799 &state->scaler_state.scaler_id,
4800 state->pipe_src_w, state->pipe_src_h,
4801 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4805 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4806 * @crtc_state: crtc's scaler state
4807 * @plane_state: atomic plane state to update
4810 * 0 - scaler_usage updated successfully
4811 * error - requested scaling cannot be supported or other error condition
4813 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4814 struct intel_plane_state *plane_state)
4817 struct intel_plane *intel_plane =
4818 to_intel_plane(plane_state->base.plane);
4819 struct drm_framebuffer *fb = plane_state->base.fb;
4822 bool force_detach = !fb || !plane_state->base.visible;
4824 ret = skl_update_scaler(crtc_state, force_detach,
4825 drm_plane_index(&intel_plane->base),
4826 &plane_state->scaler_id,
4827 drm_rect_width(&plane_state->base.src) >> 16,
4828 drm_rect_height(&plane_state->base.src) >> 16,
4829 drm_rect_width(&plane_state->base.dst),
4830 drm_rect_height(&plane_state->base.dst));
4832 if (ret || plane_state->scaler_id < 0)
4835 /* check colorkey */
4836 if (plane_state->ckey.flags) {
4837 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4838 intel_plane->base.base.id,
4839 intel_plane->base.name);
4843 /* Check src format */
4844 switch (fb->format->format) {
4845 case DRM_FORMAT_RGB565:
4846 case DRM_FORMAT_XBGR8888:
4847 case DRM_FORMAT_XRGB8888:
4848 case DRM_FORMAT_ABGR8888:
4849 case DRM_FORMAT_ARGB8888:
4850 case DRM_FORMAT_XRGB2101010:
4851 case DRM_FORMAT_XBGR2101010:
4852 case DRM_FORMAT_YUYV:
4853 case DRM_FORMAT_YVYU:
4854 case DRM_FORMAT_UYVY:
4855 case DRM_FORMAT_VYUY:
4858 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4859 intel_plane->base.base.id, intel_plane->base.name,
4860 fb->base.id, fb->format->format);
4867 static void skylake_scaler_disable(struct intel_crtc *crtc)
4871 for (i = 0; i < crtc->num_scalers; i++)
4872 skl_detach_scaler(crtc, i);
4875 static void skylake_pfit_enable(struct intel_crtc *crtc)
4877 struct drm_device *dev = crtc->base.dev;
4878 struct drm_i915_private *dev_priv = to_i915(dev);
4879 int pipe = crtc->pipe;
4880 struct intel_crtc_scaler_state *scaler_state =
4881 &crtc->config->scaler_state;
4883 if (crtc->config->pch_pfit.enabled) {
4886 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4889 id = scaler_state->scaler_id;
4890 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4891 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4892 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4893 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4897 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4899 struct drm_device *dev = crtc->base.dev;
4900 struct drm_i915_private *dev_priv = to_i915(dev);
4901 int pipe = crtc->pipe;
4903 if (crtc->config->pch_pfit.enabled) {
4904 /* Force use of hard-coded filter coefficients
4905 * as some pre-programmed values are broken,
4908 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4909 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4910 PF_PIPE_SEL_IVB(pipe));
4912 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4913 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4914 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4918 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
4920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4921 struct drm_device *dev = crtc->base.dev;
4922 struct drm_i915_private *dev_priv = to_i915(dev);
4924 if (!crtc_state->ips_enabled)
4928 * We can only enable IPS after we enable a plane and wait for a vblank
4929 * This function is called from post_plane_update, which is run after
4932 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
4934 if (IS_BROADWELL(dev_priv)) {
4935 mutex_lock(&dev_priv->pcu_lock);
4936 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4937 IPS_ENABLE | IPS_PCODE_CONTROL));
4938 mutex_unlock(&dev_priv->pcu_lock);
4939 /* Quoting Art Runyan: "its not safe to expect any particular
4940 * value in IPS_CTL bit 31 after enabling IPS through the
4941 * mailbox." Moreover, the mailbox may return a bogus state,
4942 * so we need to just enable it and continue on.
4945 I915_WRITE(IPS_CTL, IPS_ENABLE);
4946 /* The bit only becomes 1 in the next vblank, so this wait here
4947 * is essentially intel_wait_for_vblank. If we don't have this
4948 * and don't wait for vblanks until the end of crtc_enable, then
4949 * the HW state readout code will complain that the expected
4950 * IPS_CTL value is not the one we read. */
4951 if (intel_wait_for_register(dev_priv,
4952 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4954 DRM_ERROR("Timed out waiting for IPS enable\n");
4958 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
4960 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4961 struct drm_device *dev = crtc->base.dev;
4962 struct drm_i915_private *dev_priv = to_i915(dev);
4964 if (!crtc_state->ips_enabled)
4967 if (IS_BROADWELL(dev_priv)) {
4968 mutex_lock(&dev_priv->pcu_lock);
4969 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4970 mutex_unlock(&dev_priv->pcu_lock);
4971 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4972 if (intel_wait_for_register(dev_priv,
4973 IPS_CTL, IPS_ENABLE, 0,
4975 DRM_ERROR("Timed out waiting for IPS disable\n");
4977 I915_WRITE(IPS_CTL, 0);
4978 POSTING_READ(IPS_CTL);
4981 /* We need to wait for a vblank before we can disable the plane. */
4982 intel_wait_for_vblank(dev_priv, crtc->pipe);
4985 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4987 if (intel_crtc->overlay) {
4988 struct drm_device *dev = intel_crtc->base.dev;
4990 mutex_lock(&dev->struct_mutex);
4991 (void) intel_overlay_switch_off(intel_crtc->overlay);
4992 mutex_unlock(&dev->struct_mutex);
4995 /* Let userspace switch the overlay on again. In most cases userspace
4996 * has to recompute where to put it anyway.
5001 * intel_post_enable_primary - Perform operations after enabling primary plane
5002 * @crtc: the CRTC whose primary plane was just enabled
5003 * @new_crtc_state: the enabling state
5005 * Performs potentially sleeping operations that must be done after the primary
5006 * plane is enabled, such as updating FBC and IPS. Note that this may be
5007 * called due to an explicit primary plane update, or due to an implicit
5008 * re-enable that is caused when a sprite plane is updated to no longer
5009 * completely hide the primary plane.
5012 intel_post_enable_primary(struct drm_crtc *crtc,
5013 const struct intel_crtc_state *new_crtc_state)
5015 struct drm_device *dev = crtc->dev;
5016 struct drm_i915_private *dev_priv = to_i915(dev);
5017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5018 int pipe = intel_crtc->pipe;
5021 * Gen2 reports pipe underruns whenever all planes are disabled.
5022 * So don't enable underrun reporting before at least some planes
5024 * FIXME: Need to fix the logic to work when we turn off all planes
5025 * but leave the pipe running.
5027 if (IS_GEN2(dev_priv))
5028 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5030 /* Underruns don't always raise interrupts, so check manually. */
5031 intel_check_cpu_fifo_underruns(dev_priv);
5032 intel_check_pch_fifo_underruns(dev_priv);
5035 /* FIXME get rid of this and use pre_plane_update */
5037 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5039 struct drm_device *dev = crtc->dev;
5040 struct drm_i915_private *dev_priv = to_i915(dev);
5041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5042 int pipe = intel_crtc->pipe;
5045 * Gen2 reports pipe underruns whenever all planes are disabled.
5046 * So disable underrun reporting before all the planes get disabled.
5048 if (IS_GEN2(dev_priv))
5049 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5051 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5054 * Vblank time updates from the shadow to live plane control register
5055 * are blocked if the memory self-refresh mode is active at that
5056 * moment. So to make sure the plane gets truly disabled, disable
5057 * first the self-refresh mode. The self-refresh enable bit in turn
5058 * will be checked/applied by the HW only at the next frame start
5059 * event which is after the vblank start event, so we need to have a
5060 * wait-for-vblank between disabling the plane and the pipe.
5062 if (HAS_GMCH_DISPLAY(dev_priv) &&
5063 intel_set_memory_cxsr(dev_priv, false))
5064 intel_wait_for_vblank(dev_priv, pipe);
5067 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5068 const struct intel_crtc_state *new_crtc_state)
5070 if (!old_crtc_state->ips_enabled)
5073 if (needs_modeset(&new_crtc_state->base))
5076 return !new_crtc_state->ips_enabled;
5079 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5080 const struct intel_crtc_state *new_crtc_state)
5082 if (!new_crtc_state->ips_enabled)
5085 if (needs_modeset(&new_crtc_state->base))
5089 * We can't read out IPS on broadwell, assume the worst and
5090 * forcibly enable IPS on the first fastset.
5092 if (new_crtc_state->update_pipe &&
5093 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5096 return !old_crtc_state->ips_enabled;
5099 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5101 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5102 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5103 struct intel_crtc_state *pipe_config =
5104 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5106 struct drm_plane *primary = crtc->base.primary;
5107 struct drm_plane_state *old_pri_state =
5108 drm_atomic_get_existing_plane_state(old_state, primary);
5110 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5112 if (pipe_config->update_wm_post && pipe_config->base.active)
5113 intel_update_watermarks(crtc);
5115 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5116 hsw_enable_ips(pipe_config);
5118 if (old_pri_state) {
5119 struct intel_plane_state *primary_state =
5120 intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5121 to_intel_plane(primary));
5122 struct intel_plane_state *old_primary_state =
5123 to_intel_plane_state(old_pri_state);
5125 intel_fbc_post_update(crtc);
5127 if (primary_state->base.visible &&
5128 (needs_modeset(&pipe_config->base) ||
5129 !old_primary_state->base.visible))
5130 intel_post_enable_primary(&crtc->base, pipe_config);
5134 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5135 struct intel_crtc_state *pipe_config)
5137 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5138 struct drm_device *dev = crtc->base.dev;
5139 struct drm_i915_private *dev_priv = to_i915(dev);
5140 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5141 struct drm_plane *primary = crtc->base.primary;
5142 struct drm_plane_state *old_pri_state =
5143 drm_atomic_get_existing_plane_state(old_state, primary);
5144 bool modeset = needs_modeset(&pipe_config->base);
5145 struct intel_atomic_state *old_intel_state =
5146 to_intel_atomic_state(old_state);
5148 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5149 hsw_disable_ips(old_crtc_state);
5151 if (old_pri_state) {
5152 struct intel_plane_state *primary_state =
5153 intel_atomic_get_new_plane_state(old_intel_state,
5154 to_intel_plane(primary));
5155 struct intel_plane_state *old_primary_state =
5156 to_intel_plane_state(old_pri_state);
5158 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5160 * Gen2 reports pipe underruns whenever all planes are disabled.
5161 * So disable underrun reporting before all the planes get disabled.
5163 if (IS_GEN2(dev_priv) && old_primary_state->base.visible &&
5164 (modeset || !primary_state->base.visible))
5165 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5169 * Vblank time updates from the shadow to live plane control register
5170 * are blocked if the memory self-refresh mode is active at that
5171 * moment. So to make sure the plane gets truly disabled, disable
5172 * first the self-refresh mode. The self-refresh enable bit in turn
5173 * will be checked/applied by the HW only at the next frame start
5174 * event which is after the vblank start event, so we need to have a
5175 * wait-for-vblank between disabling the plane and the pipe.
5177 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5178 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5179 intel_wait_for_vblank(dev_priv, crtc->pipe);
5182 * IVB workaround: must disable low power watermarks for at least
5183 * one frame before enabling scaling. LP watermarks can be re-enabled
5184 * when scaling is disabled.
5186 * WaCxSRDisabledForSpriteScaling:ivb
5188 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5189 intel_wait_for_vblank(dev_priv, crtc->pipe);
5192 * If we're doing a modeset, we're done. No need to do any pre-vblank
5193 * watermark programming here.
5195 if (needs_modeset(&pipe_config->base))
5199 * For platforms that support atomic watermarks, program the
5200 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5201 * will be the intermediate values that are safe for both pre- and
5202 * post- vblank; when vblank happens, the 'active' values will be set
5203 * to the final 'target' values and we'll do this again to get the
5204 * optimal watermarks. For gen9+ platforms, the values we program here
5205 * will be the final target values which will get automatically latched
5206 * at vblank time; no further programming will be necessary.
5208 * If a platform hasn't been transitioned to atomic watermarks yet,
5209 * we'll continue to update watermarks the old way, if flags tell
5212 if (dev_priv->display.initial_watermarks != NULL)
5213 dev_priv->display.initial_watermarks(old_intel_state,
5215 else if (pipe_config->update_wm_pre)
5216 intel_update_watermarks(crtc);
5219 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5221 struct drm_device *dev = crtc->dev;
5222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223 struct drm_plane *p;
5224 int pipe = intel_crtc->pipe;
5226 intel_crtc_dpms_overlay_disable(intel_crtc);
5228 drm_for_each_plane_mask(p, dev, plane_mask)
5229 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5232 * FIXME: Once we grow proper nuclear flip support out of this we need
5233 * to compute the mask of flip planes precisely. For the time being
5234 * consider this a flip to a NULL plane.
5236 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5239 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5240 struct intel_crtc_state *crtc_state,
5241 struct drm_atomic_state *old_state)
5243 struct drm_connector_state *conn_state;
5244 struct drm_connector *conn;
5247 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5248 struct intel_encoder *encoder =
5249 to_intel_encoder(conn_state->best_encoder);
5251 if (conn_state->crtc != crtc)
5254 if (encoder->pre_pll_enable)
5255 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5259 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5260 struct intel_crtc_state *crtc_state,
5261 struct drm_atomic_state *old_state)
5263 struct drm_connector_state *conn_state;
5264 struct drm_connector *conn;
5267 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5268 struct intel_encoder *encoder =
5269 to_intel_encoder(conn_state->best_encoder);
5271 if (conn_state->crtc != crtc)
5274 if (encoder->pre_enable)
5275 encoder->pre_enable(encoder, crtc_state, conn_state);
5279 static void intel_encoders_enable(struct drm_crtc *crtc,
5280 struct intel_crtc_state *crtc_state,
5281 struct drm_atomic_state *old_state)
5283 struct drm_connector_state *conn_state;
5284 struct drm_connector *conn;
5287 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5288 struct intel_encoder *encoder =
5289 to_intel_encoder(conn_state->best_encoder);
5291 if (conn_state->crtc != crtc)
5294 encoder->enable(encoder, crtc_state, conn_state);
5295 intel_opregion_notify_encoder(encoder, true);
5299 static void intel_encoders_disable(struct drm_crtc *crtc,
5300 struct intel_crtc_state *old_crtc_state,
5301 struct drm_atomic_state *old_state)
5303 struct drm_connector_state *old_conn_state;
5304 struct drm_connector *conn;
5307 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5308 struct intel_encoder *encoder =
5309 to_intel_encoder(old_conn_state->best_encoder);
5311 if (old_conn_state->crtc != crtc)
5314 intel_opregion_notify_encoder(encoder, false);
5315 encoder->disable(encoder, old_crtc_state, old_conn_state);
5319 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5320 struct intel_crtc_state *old_crtc_state,
5321 struct drm_atomic_state *old_state)
5323 struct drm_connector_state *old_conn_state;
5324 struct drm_connector *conn;
5327 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5328 struct intel_encoder *encoder =
5329 to_intel_encoder(old_conn_state->best_encoder);
5331 if (old_conn_state->crtc != crtc)
5334 if (encoder->post_disable)
5335 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5339 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5340 struct intel_crtc_state *old_crtc_state,
5341 struct drm_atomic_state *old_state)
5343 struct drm_connector_state *old_conn_state;
5344 struct drm_connector *conn;
5347 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5348 struct intel_encoder *encoder =
5349 to_intel_encoder(old_conn_state->best_encoder);
5351 if (old_conn_state->crtc != crtc)
5354 if (encoder->post_pll_disable)
5355 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5359 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5360 struct drm_atomic_state *old_state)
5362 struct drm_crtc *crtc = pipe_config->base.crtc;
5363 struct drm_device *dev = crtc->dev;
5364 struct drm_i915_private *dev_priv = to_i915(dev);
5365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5366 int pipe = intel_crtc->pipe;
5367 struct intel_atomic_state *old_intel_state =
5368 to_intel_atomic_state(old_state);
5370 if (WARN_ON(intel_crtc->active))
5374 * Sometimes spurious CPU pipe underruns happen during FDI
5375 * training, at least with VGA+HDMI cloning. Suppress them.
5377 * On ILK we get an occasional spurious CPU pipe underruns
5378 * between eDP port A enable and vdd enable. Also PCH port
5379 * enable seems to result in the occasional CPU pipe underrun.
5381 * Spurious PCH underruns also occur during PCH enabling.
5383 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5384 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5385 if (intel_crtc->config->has_pch_encoder)
5386 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5388 if (intel_crtc->config->has_pch_encoder)
5389 intel_prepare_shared_dpll(intel_crtc);
5391 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5392 intel_dp_set_m_n(intel_crtc, M1_N1);
5394 intel_set_pipe_timings(intel_crtc);
5395 intel_set_pipe_src_size(intel_crtc);
5397 if (intel_crtc->config->has_pch_encoder) {
5398 intel_cpu_transcoder_set_m_n(intel_crtc,
5399 &intel_crtc->config->fdi_m_n, NULL);
5402 ironlake_set_pipeconf(crtc);
5404 intel_crtc->active = true;
5406 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5408 if (intel_crtc->config->has_pch_encoder) {
5409 /* Note: FDI PLL enabling _must_ be done before we enable the
5410 * cpu pipes, hence this is separate from all the other fdi/pch
5412 ironlake_fdi_pll_enable(intel_crtc);
5414 assert_fdi_tx_disabled(dev_priv, pipe);
5415 assert_fdi_rx_disabled(dev_priv, pipe);
5418 ironlake_pfit_enable(intel_crtc);
5421 * On ILK+ LUT must be loaded before the pipe is running but with
5424 intel_color_load_luts(&pipe_config->base);
5426 if (dev_priv->display.initial_watermarks != NULL)
5427 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5428 intel_enable_pipe(pipe_config);
5430 if (intel_crtc->config->has_pch_encoder)
5431 ironlake_pch_enable(pipe_config);
5433 assert_vblank_disabled(crtc);
5434 drm_crtc_vblank_on(crtc);
5436 intel_encoders_enable(crtc, pipe_config, old_state);
5438 if (HAS_PCH_CPT(dev_priv))
5439 cpt_verify_modeset(dev, intel_crtc->pipe);
5441 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5442 if (intel_crtc->config->has_pch_encoder)
5443 intel_wait_for_vblank(dev_priv, pipe);
5444 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5445 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5448 /* IPS only exists on ULT machines and is tied to pipe A. */
5449 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5451 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5454 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5455 enum pipe pipe, bool apply)
5457 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5458 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5465 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5468 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5470 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5471 enum pipe pipe = crtc->pipe;
5474 val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5476 /* Program B credit equally to all pipes */
5477 val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5479 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5482 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5483 struct drm_atomic_state *old_state)
5485 struct drm_crtc *crtc = pipe_config->base.crtc;
5486 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5488 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5489 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5490 struct intel_atomic_state *old_intel_state =
5491 to_intel_atomic_state(old_state);
5492 bool psl_clkgate_wa;
5494 if (WARN_ON(intel_crtc->active))
5497 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5499 if (intel_crtc->config->shared_dpll)
5500 intel_enable_shared_dpll(intel_crtc);
5502 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5503 intel_dp_set_m_n(intel_crtc, M1_N1);
5505 if (!transcoder_is_dsi(cpu_transcoder))
5506 intel_set_pipe_timings(intel_crtc);
5508 intel_set_pipe_src_size(intel_crtc);
5510 if (cpu_transcoder != TRANSCODER_EDP &&
5511 !transcoder_is_dsi(cpu_transcoder)) {
5512 I915_WRITE(PIPE_MULT(cpu_transcoder),
5513 intel_crtc->config->pixel_multiplier - 1);
5516 if (intel_crtc->config->has_pch_encoder) {
5517 intel_cpu_transcoder_set_m_n(intel_crtc,
5518 &intel_crtc->config->fdi_m_n, NULL);
5521 if (!transcoder_is_dsi(cpu_transcoder))
5522 haswell_set_pipeconf(crtc);
5524 haswell_set_pipemisc(crtc);
5526 intel_color_set_csc(&pipe_config->base);
5528 intel_crtc->active = true;
5530 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5532 if (!transcoder_is_dsi(cpu_transcoder))
5533 intel_ddi_enable_pipe_clock(pipe_config);
5535 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5536 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5537 intel_crtc->config->pch_pfit.enabled;
5539 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5541 if (INTEL_GEN(dev_priv) >= 9)
5542 skylake_pfit_enable(intel_crtc);
5544 ironlake_pfit_enable(intel_crtc);
5547 * On ILK+ LUT must be loaded before the pipe is running but with
5550 intel_color_load_luts(&pipe_config->base);
5552 intel_ddi_set_pipe_settings(pipe_config);
5553 if (!transcoder_is_dsi(cpu_transcoder))
5554 intel_ddi_enable_transcoder_func(pipe_config);
5556 if (dev_priv->display.initial_watermarks != NULL)
5557 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5559 if (INTEL_GEN(dev_priv) >= 11)
5560 icl_pipe_mbus_enable(intel_crtc);
5562 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5563 if (!transcoder_is_dsi(cpu_transcoder))
5564 intel_enable_pipe(pipe_config);
5566 if (intel_crtc->config->has_pch_encoder)
5567 lpt_pch_enable(pipe_config);
5569 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5570 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5572 assert_vblank_disabled(crtc);
5573 drm_crtc_vblank_on(crtc);
5575 intel_encoders_enable(crtc, pipe_config, old_state);
5577 if (psl_clkgate_wa) {
5578 intel_wait_for_vblank(dev_priv, pipe);
5579 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5582 /* If we change the relative order between pipe/planes enabling, we need
5583 * to change the workaround. */
5584 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5585 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5586 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5587 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5591 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5593 struct drm_device *dev = crtc->base.dev;
5594 struct drm_i915_private *dev_priv = to_i915(dev);
5595 int pipe = crtc->pipe;
5597 /* To avoid upsetting the power well on haswell only disable the pfit if
5598 * it's in use. The hw state code will make sure we get this right. */
5599 if (force || crtc->config->pch_pfit.enabled) {
5600 I915_WRITE(PF_CTL(pipe), 0);
5601 I915_WRITE(PF_WIN_POS(pipe), 0);
5602 I915_WRITE(PF_WIN_SZ(pipe), 0);
5606 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5607 struct drm_atomic_state *old_state)
5609 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5610 struct drm_device *dev = crtc->dev;
5611 struct drm_i915_private *dev_priv = to_i915(dev);
5612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5613 int pipe = intel_crtc->pipe;
5616 * Sometimes spurious CPU pipe underruns happen when the
5617 * pipe is already disabled, but FDI RX/TX is still enabled.
5618 * Happens at least with VGA+HDMI cloning. Suppress them.
5620 if (intel_crtc->config->has_pch_encoder) {
5621 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5622 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5625 intel_encoders_disable(crtc, old_crtc_state, old_state);
5627 drm_crtc_vblank_off(crtc);
5628 assert_vblank_disabled(crtc);
5630 intel_disable_pipe(old_crtc_state);
5632 ironlake_pfit_disable(intel_crtc, false);
5634 if (intel_crtc->config->has_pch_encoder)
5635 ironlake_fdi_disable(crtc);
5637 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5639 if (intel_crtc->config->has_pch_encoder) {
5640 ironlake_disable_pch_transcoder(dev_priv, pipe);
5642 if (HAS_PCH_CPT(dev_priv)) {
5646 /* disable TRANS_DP_CTL */
5647 reg = TRANS_DP_CTL(pipe);
5648 temp = I915_READ(reg);
5649 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5650 TRANS_DP_PORT_SEL_MASK);
5651 temp |= TRANS_DP_PORT_SEL_NONE;
5652 I915_WRITE(reg, temp);
5654 /* disable DPLL_SEL */
5655 temp = I915_READ(PCH_DPLL_SEL);
5656 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5657 I915_WRITE(PCH_DPLL_SEL, temp);
5660 ironlake_fdi_pll_disable(intel_crtc);
5663 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5664 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5667 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5668 struct drm_atomic_state *old_state)
5670 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5671 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5673 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5675 intel_encoders_disable(crtc, old_crtc_state, old_state);
5677 drm_crtc_vblank_off(crtc);
5678 assert_vblank_disabled(crtc);
5680 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5681 if (!transcoder_is_dsi(cpu_transcoder))
5682 intel_disable_pipe(old_crtc_state);
5684 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5685 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5687 if (!transcoder_is_dsi(cpu_transcoder))
5688 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5690 if (INTEL_GEN(dev_priv) >= 9)
5691 skylake_scaler_disable(intel_crtc);
5693 ironlake_pfit_disable(intel_crtc, false);
5695 if (!transcoder_is_dsi(cpu_transcoder))
5696 intel_ddi_disable_pipe_clock(intel_crtc->config);
5698 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5701 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5703 struct drm_device *dev = crtc->base.dev;
5704 struct drm_i915_private *dev_priv = to_i915(dev);
5705 struct intel_crtc_state *pipe_config = crtc->config;
5707 if (!pipe_config->gmch_pfit.control)
5711 * The panel fitter should only be adjusted whilst the pipe is disabled,
5712 * according to register description and PRM.
5714 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5715 assert_pipe_disabled(dev_priv, crtc->pipe);
5717 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5718 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5720 /* Border color in case we don't scale up to the full screen. Black by
5721 * default, change to something else for debugging. */
5722 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5725 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5729 return POWER_DOMAIN_PORT_DDI_A_LANES;
5731 return POWER_DOMAIN_PORT_DDI_B_LANES;
5733 return POWER_DOMAIN_PORT_DDI_C_LANES;
5735 return POWER_DOMAIN_PORT_DDI_D_LANES;
5737 return POWER_DOMAIN_PORT_DDI_E_LANES;
5739 return POWER_DOMAIN_PORT_DDI_F_LANES;
5742 return POWER_DOMAIN_PORT_OTHER;
5746 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5747 struct intel_crtc_state *crtc_state)
5749 struct drm_device *dev = crtc->dev;
5750 struct drm_i915_private *dev_priv = to_i915(dev);
5751 struct drm_encoder *encoder;
5752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5753 enum pipe pipe = intel_crtc->pipe;
5755 enum transcoder transcoder = crtc_state->cpu_transcoder;
5757 if (!crtc_state->base.active)
5760 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5761 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5762 if (crtc_state->pch_pfit.enabled ||
5763 crtc_state->pch_pfit.force_thru)
5764 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5766 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5767 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5769 mask |= BIT_ULL(intel_encoder->power_domain);
5772 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5773 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5775 if (crtc_state->shared_dpll)
5776 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5782 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5783 struct intel_crtc_state *crtc_state)
5785 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5787 enum intel_display_power_domain domain;
5788 u64 domains, new_domains, old_domains;
5790 old_domains = intel_crtc->enabled_power_domains;
5791 intel_crtc->enabled_power_domains = new_domains =
5792 get_crtc_power_domains(crtc, crtc_state);
5794 domains = new_domains & ~old_domains;
5796 for_each_power_domain(domain, domains)
5797 intel_display_power_get(dev_priv, domain);
5799 return old_domains & ~new_domains;
5802 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5805 enum intel_display_power_domain domain;
5807 for_each_power_domain(domain, domains)
5808 intel_display_power_put(dev_priv, domain);
5811 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5812 struct drm_atomic_state *old_state)
5814 struct intel_atomic_state *old_intel_state =
5815 to_intel_atomic_state(old_state);
5816 struct drm_crtc *crtc = pipe_config->base.crtc;
5817 struct drm_device *dev = crtc->dev;
5818 struct drm_i915_private *dev_priv = to_i915(dev);
5819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5820 int pipe = intel_crtc->pipe;
5822 if (WARN_ON(intel_crtc->active))
5825 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5826 intel_dp_set_m_n(intel_crtc, M1_N1);
5828 intel_set_pipe_timings(intel_crtc);
5829 intel_set_pipe_src_size(intel_crtc);
5831 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5832 struct drm_i915_private *dev_priv = to_i915(dev);
5834 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5835 I915_WRITE(CHV_CANVAS(pipe), 0);
5838 i9xx_set_pipeconf(intel_crtc);
5840 intel_crtc->active = true;
5842 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5844 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5846 if (IS_CHERRYVIEW(dev_priv)) {
5847 chv_prepare_pll(intel_crtc, intel_crtc->config);
5848 chv_enable_pll(intel_crtc, intel_crtc->config);
5850 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5851 vlv_enable_pll(intel_crtc, intel_crtc->config);
5854 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5856 i9xx_pfit_enable(intel_crtc);
5858 intel_color_load_luts(&pipe_config->base);
5860 dev_priv->display.initial_watermarks(old_intel_state,
5862 intel_enable_pipe(pipe_config);
5864 assert_vblank_disabled(crtc);
5865 drm_crtc_vblank_on(crtc);
5867 intel_encoders_enable(crtc, pipe_config, old_state);
5870 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5872 struct drm_device *dev = crtc->base.dev;
5873 struct drm_i915_private *dev_priv = to_i915(dev);
5875 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5876 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5879 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5880 struct drm_atomic_state *old_state)
5882 struct intel_atomic_state *old_intel_state =
5883 to_intel_atomic_state(old_state);
5884 struct drm_crtc *crtc = pipe_config->base.crtc;
5885 struct drm_device *dev = crtc->dev;
5886 struct drm_i915_private *dev_priv = to_i915(dev);
5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5888 enum pipe pipe = intel_crtc->pipe;
5890 if (WARN_ON(intel_crtc->active))
5893 i9xx_set_pll_dividers(intel_crtc);
5895 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5896 intel_dp_set_m_n(intel_crtc, M1_N1);
5898 intel_set_pipe_timings(intel_crtc);
5899 intel_set_pipe_src_size(intel_crtc);
5901 i9xx_set_pipeconf(intel_crtc);
5903 intel_crtc->active = true;
5905 if (!IS_GEN2(dev_priv))
5906 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5908 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5910 i9xx_enable_pll(intel_crtc, pipe_config);
5912 i9xx_pfit_enable(intel_crtc);
5914 intel_color_load_luts(&pipe_config->base);
5916 if (dev_priv->display.initial_watermarks != NULL)
5917 dev_priv->display.initial_watermarks(old_intel_state,
5918 intel_crtc->config);
5920 intel_update_watermarks(intel_crtc);
5921 intel_enable_pipe(pipe_config);
5923 assert_vblank_disabled(crtc);
5924 drm_crtc_vblank_on(crtc);
5926 intel_encoders_enable(crtc, pipe_config, old_state);
5929 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5931 struct drm_device *dev = crtc->base.dev;
5932 struct drm_i915_private *dev_priv = to_i915(dev);
5934 if (!crtc->config->gmch_pfit.control)
5937 assert_pipe_disabled(dev_priv, crtc->pipe);
5939 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5940 I915_READ(PFIT_CONTROL));
5941 I915_WRITE(PFIT_CONTROL, 0);
5944 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5945 struct drm_atomic_state *old_state)
5947 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5948 struct drm_device *dev = crtc->dev;
5949 struct drm_i915_private *dev_priv = to_i915(dev);
5950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951 int pipe = intel_crtc->pipe;
5954 * On gen2 planes are double buffered but the pipe isn't, so we must
5955 * wait for planes to fully turn off before disabling the pipe.
5957 if (IS_GEN2(dev_priv))
5958 intel_wait_for_vblank(dev_priv, pipe);
5960 intel_encoders_disable(crtc, old_crtc_state, old_state);
5962 drm_crtc_vblank_off(crtc);
5963 assert_vblank_disabled(crtc);
5965 intel_disable_pipe(old_crtc_state);
5967 i9xx_pfit_disable(intel_crtc);
5969 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5971 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5972 if (IS_CHERRYVIEW(dev_priv))
5973 chv_disable_pll(dev_priv, pipe);
5974 else if (IS_VALLEYVIEW(dev_priv))
5975 vlv_disable_pll(dev_priv, pipe);
5977 i9xx_disable_pll(intel_crtc);
5980 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5982 if (!IS_GEN2(dev_priv))
5983 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5985 if (!dev_priv->display.initial_watermarks)
5986 intel_update_watermarks(intel_crtc);
5988 /* clock the pipe down to 640x480@60 to potentially save power */
5989 if (IS_I830(dev_priv))
5990 i830_enable_pipe(dev_priv, pipe);
5993 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5994 struct drm_modeset_acquire_ctx *ctx)
5996 struct intel_encoder *encoder;
5997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5999 enum intel_display_power_domain domain;
6000 struct intel_plane *plane;
6002 struct drm_atomic_state *state;
6003 struct intel_crtc_state *crtc_state;
6006 if (!intel_crtc->active)
6009 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6010 const struct intel_plane_state *plane_state =
6011 to_intel_plane_state(plane->base.state);
6013 if (plane_state->base.visible)
6014 intel_plane_disable_noatomic(intel_crtc, plane);
6017 state = drm_atomic_state_alloc(crtc->dev);
6019 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6020 crtc->base.id, crtc->name);
6024 state->acquire_ctx = ctx;
6026 /* Everything's already locked, -EDEADLK can't happen. */
6027 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6028 ret = drm_atomic_add_affected_connectors(state, crtc);
6030 WARN_ON(IS_ERR(crtc_state) || ret);
6032 dev_priv->display.crtc_disable(crtc_state, state);
6034 drm_atomic_state_put(state);
6036 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6037 crtc->base.id, crtc->name);
6039 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6040 crtc->state->active = false;
6041 intel_crtc->active = false;
6042 crtc->enabled = false;
6043 crtc->state->connector_mask = 0;
6044 crtc->state->encoder_mask = 0;
6046 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6047 encoder->base.crtc = NULL;
6049 intel_fbc_disable(intel_crtc);
6050 intel_update_watermarks(intel_crtc);
6051 intel_disable_shared_dpll(intel_crtc);
6053 domains = intel_crtc->enabled_power_domains;
6054 for_each_power_domain(domain, domains)
6055 intel_display_power_put(dev_priv, domain);
6056 intel_crtc->enabled_power_domains = 0;
6058 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6059 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6060 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6064 * turn all crtc's off, but do not adjust state
6065 * This has to be paired with a call to intel_modeset_setup_hw_state.
6067 int intel_display_suspend(struct drm_device *dev)
6069 struct drm_i915_private *dev_priv = to_i915(dev);
6070 struct drm_atomic_state *state;
6073 state = drm_atomic_helper_suspend(dev);
6074 ret = PTR_ERR_OR_ZERO(state);
6076 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6078 dev_priv->modeset_restore_state = state;
6082 void intel_encoder_destroy(struct drm_encoder *encoder)
6084 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6086 drm_encoder_cleanup(encoder);
6087 kfree(intel_encoder);
6090 /* Cross check the actual hw state with our own modeset state tracking (and it's
6091 * internal consistency). */
6092 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6093 struct drm_connector_state *conn_state)
6095 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6097 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6098 connector->base.base.id,
6099 connector->base.name);
6101 if (connector->get_hw_state(connector)) {
6102 struct intel_encoder *encoder = connector->encoder;
6104 I915_STATE_WARN(!crtc_state,
6105 "connector enabled without attached crtc\n");
6110 I915_STATE_WARN(!crtc_state->active,
6111 "connector is active, but attached crtc isn't\n");
6113 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6116 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6117 "atomic encoder doesn't match attached encoder\n");
6119 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6120 "attached encoder crtc differs from connector crtc\n");
6122 I915_STATE_WARN(crtc_state && crtc_state->active,
6123 "attached crtc is active, but connector isn't\n");
6124 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6125 "best encoder set without crtc!\n");
6129 int intel_connector_init(struct intel_connector *connector)
6131 struct intel_digital_connector_state *conn_state;
6134 * Allocate enough memory to hold intel_digital_connector_state,
6135 * This might be a few bytes too many, but for connectors that don't
6136 * need it we'll free the state and allocate a smaller one on the first
6137 * succesful commit anyway.
6139 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6143 __drm_atomic_helper_connector_reset(&connector->base,
6149 struct intel_connector *intel_connector_alloc(void)
6151 struct intel_connector *connector;
6153 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6157 if (intel_connector_init(connector) < 0) {
6166 * Free the bits allocated by intel_connector_alloc.
6167 * This should only be used after intel_connector_alloc has returned
6168 * successfully, and before drm_connector_init returns successfully.
6169 * Otherwise the destroy callbacks for the connector and the state should
6170 * take care of proper cleanup/free
6172 void intel_connector_free(struct intel_connector *connector)
6174 kfree(to_intel_digital_connector_state(connector->base.state));
6178 /* Simple connector->get_hw_state implementation for encoders that support only
6179 * one connector and no cloning and hence the encoder state determines the state
6180 * of the connector. */
6181 bool intel_connector_get_hw_state(struct intel_connector *connector)
6184 struct intel_encoder *encoder = connector->encoder;
6186 return encoder->get_hw_state(encoder, &pipe);
6189 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6191 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6192 return crtc_state->fdi_lanes;
6197 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6198 struct intel_crtc_state *pipe_config)
6200 struct drm_i915_private *dev_priv = to_i915(dev);
6201 struct drm_atomic_state *state = pipe_config->base.state;
6202 struct intel_crtc *other_crtc;
6203 struct intel_crtc_state *other_crtc_state;
6205 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6206 pipe_name(pipe), pipe_config->fdi_lanes);
6207 if (pipe_config->fdi_lanes > 4) {
6208 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6209 pipe_name(pipe), pipe_config->fdi_lanes);
6213 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6214 if (pipe_config->fdi_lanes > 2) {
6215 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6216 pipe_config->fdi_lanes);
6223 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6226 /* Ivybridge 3 pipe is really complicated */
6231 if (pipe_config->fdi_lanes <= 2)
6234 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6236 intel_atomic_get_crtc_state(state, other_crtc);
6237 if (IS_ERR(other_crtc_state))
6238 return PTR_ERR(other_crtc_state);
6240 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6241 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6242 pipe_name(pipe), pipe_config->fdi_lanes);
6247 if (pipe_config->fdi_lanes > 2) {
6248 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6249 pipe_name(pipe), pipe_config->fdi_lanes);
6253 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6255 intel_atomic_get_crtc_state(state, other_crtc);
6256 if (IS_ERR(other_crtc_state))
6257 return PTR_ERR(other_crtc_state);
6259 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6260 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6270 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6271 struct intel_crtc_state *pipe_config)
6273 struct drm_device *dev = intel_crtc->base.dev;
6274 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6275 int lane, link_bw, fdi_dotclock, ret;
6276 bool needs_recompute = false;
6279 /* FDI is a binary signal running at ~2.7GHz, encoding
6280 * each output octet as 10 bits. The actual frequency
6281 * is stored as a divider into a 100MHz clock, and the
6282 * mode pixel clock is stored in units of 1KHz.
6283 * Hence the bw of each lane in terms of the mode signal
6286 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6288 fdi_dotclock = adjusted_mode->crtc_clock;
6290 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6291 pipe_config->pipe_bpp);
6293 pipe_config->fdi_lanes = lane;
6295 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6296 link_bw, &pipe_config->fdi_m_n, false);
6298 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6299 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6300 pipe_config->pipe_bpp -= 2*3;
6301 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6302 pipe_config->pipe_bpp);
6303 needs_recompute = true;
6304 pipe_config->bw_constrained = true;
6309 if (needs_recompute)
6315 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6317 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6318 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6320 /* IPS only exists on ULT machines and is tied to pipe A. */
6321 if (!hsw_crtc_supports_ips(crtc))
6324 if (!i915_modparams.enable_ips)
6327 if (crtc_state->pipe_bpp > 24)
6331 * We compare against max which means we must take
6332 * the increased cdclk requirement into account when
6333 * calculating the new cdclk.
6335 * Should measure whether using a lower cdclk w/o IPS
6337 if (IS_BROADWELL(dev_priv) &&
6338 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6344 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6346 struct drm_i915_private *dev_priv =
6347 to_i915(crtc_state->base.crtc->dev);
6348 struct intel_atomic_state *intel_state =
6349 to_intel_atomic_state(crtc_state->base.state);
6351 if (!hsw_crtc_state_ips_capable(crtc_state))
6354 if (crtc_state->ips_force_disable)
6357 /* IPS should be fine as long as at least one plane is enabled. */
6358 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6361 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6362 if (IS_BROADWELL(dev_priv) &&
6363 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6369 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6371 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6373 /* GDG double wide on either pipe, otherwise pipe A only */
6374 return INTEL_GEN(dev_priv) < 4 &&
6375 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6378 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6380 uint32_t pixel_rate;
6382 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6385 * We only use IF-ID interlacing. If we ever use
6386 * PF-ID we'll need to adjust the pixel_rate here.
6389 if (pipe_config->pch_pfit.enabled) {
6390 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6391 uint32_t pfit_size = pipe_config->pch_pfit.size;
6393 pipe_w = pipe_config->pipe_src_w;
6394 pipe_h = pipe_config->pipe_src_h;
6396 pfit_w = (pfit_size >> 16) & 0xFFFF;
6397 pfit_h = pfit_size & 0xFFFF;
6398 if (pipe_w < pfit_w)
6400 if (pipe_h < pfit_h)
6403 if (WARN_ON(!pfit_w || !pfit_h))
6406 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6413 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6415 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6417 if (HAS_GMCH_DISPLAY(dev_priv))
6418 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6419 crtc_state->pixel_rate =
6420 crtc_state->base.adjusted_mode.crtc_clock;
6422 crtc_state->pixel_rate =
6423 ilk_pipe_pixel_rate(crtc_state);
6426 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6427 struct intel_crtc_state *pipe_config)
6429 struct drm_device *dev = crtc->base.dev;
6430 struct drm_i915_private *dev_priv = to_i915(dev);
6431 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6432 int clock_limit = dev_priv->max_dotclk_freq;
6434 if (INTEL_GEN(dev_priv) < 4) {
6435 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6438 * Enable double wide mode when the dot clock
6439 * is > 90% of the (display) core speed.
6441 if (intel_crtc_supports_double_wide(crtc) &&
6442 adjusted_mode->crtc_clock > clock_limit) {
6443 clock_limit = dev_priv->max_dotclk_freq;
6444 pipe_config->double_wide = true;
6448 if (adjusted_mode->crtc_clock > clock_limit) {
6449 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6450 adjusted_mode->crtc_clock, clock_limit,
6451 yesno(pipe_config->double_wide));
6455 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6457 * There is only one pipe CSC unit per pipe, and we need that
6458 * for output conversion from RGB->YCBCR. So if CTM is already
6459 * applied we can't support YCBCR420 output.
6461 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6466 * Pipe horizontal size must be even in:
6468 * - LVDS dual channel mode
6469 * - Double wide pipe
6471 if (pipe_config->pipe_src_w & 1) {
6472 if (pipe_config->double_wide) {
6473 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6477 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6478 intel_is_dual_link_lvds(dev)) {
6479 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6484 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6485 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6487 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6488 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6491 intel_crtc_compute_pixel_rate(pipe_config);
6493 if (pipe_config->has_pch_encoder)
6494 return ironlake_fdi_compute_config(crtc, pipe_config);
6500 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6502 while (*num > DATA_LINK_M_N_MASK ||
6503 *den > DATA_LINK_M_N_MASK) {
6509 static void compute_m_n(unsigned int m, unsigned int n,
6510 uint32_t *ret_m, uint32_t *ret_n,
6514 * Reduce M/N as much as possible without loss in precision. Several DP
6515 * dongles in particular seem to be fussy about too large *link* M/N
6516 * values. The passed in values are more likely to have the least
6517 * significant bits zero than M after rounding below, so do this first.
6520 while ((m & 1) == 0 && (n & 1) == 0) {
6526 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6527 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6528 intel_reduce_m_n_ratio(ret_m, ret_n);
6532 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6533 int pixel_clock, int link_clock,
6534 struct intel_link_m_n *m_n,
6539 compute_m_n(bits_per_pixel * pixel_clock,
6540 link_clock * nlanes * 8,
6541 &m_n->gmch_m, &m_n->gmch_n,
6544 compute_m_n(pixel_clock, link_clock,
6545 &m_n->link_m, &m_n->link_n,
6549 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6551 if (i915_modparams.panel_use_ssc >= 0)
6552 return i915_modparams.panel_use_ssc != 0;
6553 return dev_priv->vbt.lvds_use_ssc
6554 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6557 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6559 return (1 << dpll->n) << 16 | dpll->m2;
6562 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6564 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6567 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6568 struct intel_crtc_state *crtc_state,
6569 struct dpll *reduced_clock)
6571 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6574 if (IS_PINEVIEW(dev_priv)) {
6575 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6577 fp2 = pnv_dpll_compute_fp(reduced_clock);
6579 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6581 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6584 crtc_state->dpll_hw_state.fp0 = fp;
6586 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6588 crtc_state->dpll_hw_state.fp1 = fp2;
6590 crtc_state->dpll_hw_state.fp1 = fp;
6594 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6600 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6601 * and set it to a reasonable value instead.
6603 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6604 reg_val &= 0xffffff00;
6605 reg_val |= 0x00000030;
6606 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6608 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6609 reg_val &= 0x00ffffff;
6610 reg_val |= 0x8c000000;
6611 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6613 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6614 reg_val &= 0xffffff00;
6615 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6617 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6618 reg_val &= 0x00ffffff;
6619 reg_val |= 0xb0000000;
6620 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6623 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6624 struct intel_link_m_n *m_n)
6626 struct drm_device *dev = crtc->base.dev;
6627 struct drm_i915_private *dev_priv = to_i915(dev);
6628 int pipe = crtc->pipe;
6630 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6631 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6632 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6633 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6636 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6637 struct intel_link_m_n *m_n,
6638 struct intel_link_m_n *m2_n2)
6640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6641 int pipe = crtc->pipe;
6642 enum transcoder transcoder = crtc->config->cpu_transcoder;
6644 if (INTEL_GEN(dev_priv) >= 5) {
6645 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6646 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6647 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6648 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6649 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6650 * for gen < 8) and if DRRS is supported (to make sure the
6651 * registers are not unnecessarily accessed).
6653 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6654 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6655 I915_WRITE(PIPE_DATA_M2(transcoder),
6656 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6657 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6658 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6659 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6662 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6663 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6664 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6665 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6669 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6671 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6674 dp_m_n = &crtc->config->dp_m_n;
6675 dp_m2_n2 = &crtc->config->dp_m2_n2;
6676 } else if (m_n == M2_N2) {
6679 * M2_N2 registers are not supported. Hence m2_n2 divider value
6680 * needs to be programmed into M1_N1.
6682 dp_m_n = &crtc->config->dp_m2_n2;
6684 DRM_ERROR("Unsupported divider value\n");
6688 if (crtc->config->has_pch_encoder)
6689 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6691 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6694 static void vlv_compute_dpll(struct intel_crtc *crtc,
6695 struct intel_crtc_state *pipe_config)
6697 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6698 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6699 if (crtc->pipe != PIPE_A)
6700 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6702 /* DPLL not used with DSI, but still need the rest set up */
6703 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6704 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6705 DPLL_EXT_BUFFER_ENABLE_VLV;
6707 pipe_config->dpll_hw_state.dpll_md =
6708 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6711 static void chv_compute_dpll(struct intel_crtc *crtc,
6712 struct intel_crtc_state *pipe_config)
6714 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6715 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6716 if (crtc->pipe != PIPE_A)
6717 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6719 /* DPLL not used with DSI, but still need the rest set up */
6720 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6721 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6723 pipe_config->dpll_hw_state.dpll_md =
6724 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6727 static void vlv_prepare_pll(struct intel_crtc *crtc,
6728 const struct intel_crtc_state *pipe_config)
6730 struct drm_device *dev = crtc->base.dev;
6731 struct drm_i915_private *dev_priv = to_i915(dev);
6732 enum pipe pipe = crtc->pipe;
6734 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6735 u32 coreclk, reg_val;
6738 I915_WRITE(DPLL(pipe),
6739 pipe_config->dpll_hw_state.dpll &
6740 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6742 /* No need to actually set up the DPLL with DSI */
6743 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6746 mutex_lock(&dev_priv->sb_lock);
6748 bestn = pipe_config->dpll.n;
6749 bestm1 = pipe_config->dpll.m1;
6750 bestm2 = pipe_config->dpll.m2;
6751 bestp1 = pipe_config->dpll.p1;
6752 bestp2 = pipe_config->dpll.p2;
6754 /* See eDP HDMI DPIO driver vbios notes doc */
6756 /* PLL B needs special handling */
6758 vlv_pllb_recal_opamp(dev_priv, pipe);
6760 /* Set up Tx target for periodic Rcomp update */
6761 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6763 /* Disable target IRef on PLL */
6764 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6765 reg_val &= 0x00ffffff;
6766 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6768 /* Disable fast lock */
6769 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6771 /* Set idtafcrecal before PLL is enabled */
6772 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6773 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6774 mdiv |= ((bestn << DPIO_N_SHIFT));
6775 mdiv |= (1 << DPIO_K_SHIFT);
6778 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6779 * but we don't support that).
6780 * Note: don't use the DAC post divider as it seems unstable.
6782 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6783 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6785 mdiv |= DPIO_ENABLE_CALIBRATION;
6786 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6788 /* Set HBR and RBR LPF coefficients */
6789 if (pipe_config->port_clock == 162000 ||
6790 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6791 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6792 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6795 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6798 if (intel_crtc_has_dp_encoder(pipe_config)) {
6799 /* Use SSC source */
6801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6804 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6806 } else { /* HDMI or VGA */
6807 /* Use bend source */
6809 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6812 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6816 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6817 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6818 if (intel_crtc_has_dp_encoder(crtc->config))
6819 coreclk |= 0x01000000;
6820 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6822 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6823 mutex_unlock(&dev_priv->sb_lock);
6826 static void chv_prepare_pll(struct intel_crtc *crtc,
6827 const struct intel_crtc_state *pipe_config)
6829 struct drm_device *dev = crtc->base.dev;
6830 struct drm_i915_private *dev_priv = to_i915(dev);
6831 enum pipe pipe = crtc->pipe;
6832 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6833 u32 loopfilter, tribuf_calcntr;
6834 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6838 /* Enable Refclk and SSC */
6839 I915_WRITE(DPLL(pipe),
6840 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6842 /* No need to actually set up the DPLL with DSI */
6843 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6846 bestn = pipe_config->dpll.n;
6847 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6848 bestm1 = pipe_config->dpll.m1;
6849 bestm2 = pipe_config->dpll.m2 >> 22;
6850 bestp1 = pipe_config->dpll.p1;
6851 bestp2 = pipe_config->dpll.p2;
6852 vco = pipe_config->dpll.vco;
6856 mutex_lock(&dev_priv->sb_lock);
6858 /* p1 and p2 divider */
6859 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6860 5 << DPIO_CHV_S1_DIV_SHIFT |
6861 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6862 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6863 1 << DPIO_CHV_K_DIV_SHIFT);
6865 /* Feedback post-divider - m2 */
6866 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6868 /* Feedback refclk divider - n and m1 */
6869 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6870 DPIO_CHV_M1_DIV_BY_2 |
6871 1 << DPIO_CHV_N_DIV_SHIFT);
6873 /* M2 fraction division */
6874 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6876 /* M2 fraction division enable */
6877 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6878 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6879 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6881 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6882 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6884 /* Program digital lock detect threshold */
6885 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6886 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6887 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6888 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6890 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6891 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6894 if (vco == 5400000) {
6895 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6896 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6897 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6898 tribuf_calcntr = 0x9;
6899 } else if (vco <= 6200000) {
6900 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6901 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6902 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6903 tribuf_calcntr = 0x9;
6904 } else if (vco <= 6480000) {
6905 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6906 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6907 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6908 tribuf_calcntr = 0x8;
6910 /* Not supported. Apply the same limits as in the max case */
6911 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6912 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6913 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6916 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6918 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6919 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6920 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6921 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6924 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6925 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6928 mutex_unlock(&dev_priv->sb_lock);
6932 * vlv_force_pll_on - forcibly enable just the PLL
6933 * @dev_priv: i915 private structure
6934 * @pipe: pipe PLL to enable
6935 * @dpll: PLL configuration
6937 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6938 * in cases where we need the PLL enabled even when @pipe is not going to
6941 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6942 const struct dpll *dpll)
6944 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6945 struct intel_crtc_state *pipe_config;
6947 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6951 pipe_config->base.crtc = &crtc->base;
6952 pipe_config->pixel_multiplier = 1;
6953 pipe_config->dpll = *dpll;
6955 if (IS_CHERRYVIEW(dev_priv)) {
6956 chv_compute_dpll(crtc, pipe_config);
6957 chv_prepare_pll(crtc, pipe_config);
6958 chv_enable_pll(crtc, pipe_config);
6960 vlv_compute_dpll(crtc, pipe_config);
6961 vlv_prepare_pll(crtc, pipe_config);
6962 vlv_enable_pll(crtc, pipe_config);
6971 * vlv_force_pll_off - forcibly disable just the PLL
6972 * @dev_priv: i915 private structure
6973 * @pipe: pipe PLL to disable
6975 * Disable the PLL for @pipe. To be used in cases where we need
6976 * the PLL enabled even when @pipe is not going to be enabled.
6978 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6980 if (IS_CHERRYVIEW(dev_priv))
6981 chv_disable_pll(dev_priv, pipe);
6983 vlv_disable_pll(dev_priv, pipe);
6986 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6987 struct intel_crtc_state *crtc_state,
6988 struct dpll *reduced_clock)
6990 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6992 struct dpll *clock = &crtc_state->dpll;
6994 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6996 dpll = DPLL_VGA_MODE_DIS;
6998 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6999 dpll |= DPLLB_MODE_LVDS;
7001 dpll |= DPLLB_MODE_DAC_SERIAL;
7003 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7004 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7005 dpll |= (crtc_state->pixel_multiplier - 1)
7006 << SDVO_MULTIPLIER_SHIFT_HIRES;
7009 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7010 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7011 dpll |= DPLL_SDVO_HIGH_SPEED;
7013 if (intel_crtc_has_dp_encoder(crtc_state))
7014 dpll |= DPLL_SDVO_HIGH_SPEED;
7016 /* compute bitmask from p1 value */
7017 if (IS_PINEVIEW(dev_priv))
7018 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7020 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7021 if (IS_G4X(dev_priv) && reduced_clock)
7022 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7024 switch (clock->p2) {
7026 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7029 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7032 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7035 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7038 if (INTEL_GEN(dev_priv) >= 4)
7039 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7041 if (crtc_state->sdvo_tv_clock)
7042 dpll |= PLL_REF_INPUT_TVCLKINBC;
7043 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7044 intel_panel_use_ssc(dev_priv))
7045 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7047 dpll |= PLL_REF_INPUT_DREFCLK;
7049 dpll |= DPLL_VCO_ENABLE;
7050 crtc_state->dpll_hw_state.dpll = dpll;
7052 if (INTEL_GEN(dev_priv) >= 4) {
7053 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7054 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7055 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7059 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7060 struct intel_crtc_state *crtc_state,
7061 struct dpll *reduced_clock)
7063 struct drm_device *dev = crtc->base.dev;
7064 struct drm_i915_private *dev_priv = to_i915(dev);
7066 struct dpll *clock = &crtc_state->dpll;
7068 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7070 dpll = DPLL_VGA_MODE_DIS;
7072 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7073 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7076 dpll |= PLL_P1_DIVIDE_BY_TWO;
7078 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7080 dpll |= PLL_P2_DIVIDE_BY_4;
7083 if (!IS_I830(dev_priv) &&
7084 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7085 dpll |= DPLL_DVO_2X_MODE;
7087 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7088 intel_panel_use_ssc(dev_priv))
7089 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7091 dpll |= PLL_REF_INPUT_DREFCLK;
7093 dpll |= DPLL_VCO_ENABLE;
7094 crtc_state->dpll_hw_state.dpll = dpll;
7097 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7099 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7100 enum pipe pipe = intel_crtc->pipe;
7101 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7102 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7103 uint32_t crtc_vtotal, crtc_vblank_end;
7106 /* We need to be careful not to changed the adjusted mode, for otherwise
7107 * the hw state checker will get angry at the mismatch. */
7108 crtc_vtotal = adjusted_mode->crtc_vtotal;
7109 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7111 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7112 /* the chip adds 2 halflines automatically */
7114 crtc_vblank_end -= 1;
7116 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7117 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7119 vsyncshift = adjusted_mode->crtc_hsync_start -
7120 adjusted_mode->crtc_htotal / 2;
7122 vsyncshift += adjusted_mode->crtc_htotal;
7125 if (INTEL_GEN(dev_priv) > 3)
7126 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7128 I915_WRITE(HTOTAL(cpu_transcoder),
7129 (adjusted_mode->crtc_hdisplay - 1) |
7130 ((adjusted_mode->crtc_htotal - 1) << 16));
7131 I915_WRITE(HBLANK(cpu_transcoder),
7132 (adjusted_mode->crtc_hblank_start - 1) |
7133 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7134 I915_WRITE(HSYNC(cpu_transcoder),
7135 (adjusted_mode->crtc_hsync_start - 1) |
7136 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7138 I915_WRITE(VTOTAL(cpu_transcoder),
7139 (adjusted_mode->crtc_vdisplay - 1) |
7140 ((crtc_vtotal - 1) << 16));
7141 I915_WRITE(VBLANK(cpu_transcoder),
7142 (adjusted_mode->crtc_vblank_start - 1) |
7143 ((crtc_vblank_end - 1) << 16));
7144 I915_WRITE(VSYNC(cpu_transcoder),
7145 (adjusted_mode->crtc_vsync_start - 1) |
7146 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7148 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7149 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7150 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7152 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7153 (pipe == PIPE_B || pipe == PIPE_C))
7154 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7158 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7160 struct drm_device *dev = intel_crtc->base.dev;
7161 struct drm_i915_private *dev_priv = to_i915(dev);
7162 enum pipe pipe = intel_crtc->pipe;
7164 /* pipesrc controls the size that is scaled from, which should
7165 * always be the user's requested size.
7167 I915_WRITE(PIPESRC(pipe),
7168 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7169 (intel_crtc->config->pipe_src_h - 1));
7172 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7173 struct intel_crtc_state *pipe_config)
7175 struct drm_device *dev = crtc->base.dev;
7176 struct drm_i915_private *dev_priv = to_i915(dev);
7177 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7180 tmp = I915_READ(HTOTAL(cpu_transcoder));
7181 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7182 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7183 tmp = I915_READ(HBLANK(cpu_transcoder));
7184 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7185 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7186 tmp = I915_READ(HSYNC(cpu_transcoder));
7187 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7188 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7190 tmp = I915_READ(VTOTAL(cpu_transcoder));
7191 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7192 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7193 tmp = I915_READ(VBLANK(cpu_transcoder));
7194 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7195 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7196 tmp = I915_READ(VSYNC(cpu_transcoder));
7197 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7198 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7200 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7201 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7202 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7203 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7207 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7208 struct intel_crtc_state *pipe_config)
7210 struct drm_device *dev = crtc->base.dev;
7211 struct drm_i915_private *dev_priv = to_i915(dev);
7214 tmp = I915_READ(PIPESRC(crtc->pipe));
7215 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7216 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7218 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7219 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7222 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7223 struct intel_crtc_state *pipe_config)
7225 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7226 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7227 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7228 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7230 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7231 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7232 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7233 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7235 mode->flags = pipe_config->base.adjusted_mode.flags;
7236 mode->type = DRM_MODE_TYPE_DRIVER;
7238 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7240 mode->hsync = drm_mode_hsync(mode);
7241 mode->vrefresh = drm_mode_vrefresh(mode);
7242 drm_mode_set_name(mode);
7245 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7247 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7252 /* we keep both pipes enabled on 830 */
7253 if (IS_I830(dev_priv))
7254 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7256 if (intel_crtc->config->double_wide)
7257 pipeconf |= PIPECONF_DOUBLE_WIDE;
7259 /* only g4x and later have fancy bpc/dither controls */
7260 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7261 IS_CHERRYVIEW(dev_priv)) {
7262 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7263 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7264 pipeconf |= PIPECONF_DITHER_EN |
7265 PIPECONF_DITHER_TYPE_SP;
7267 switch (intel_crtc->config->pipe_bpp) {
7269 pipeconf |= PIPECONF_6BPC;
7272 pipeconf |= PIPECONF_8BPC;
7275 pipeconf |= PIPECONF_10BPC;
7278 /* Case prevented by intel_choose_pipe_bpp_dither. */
7283 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7284 if (INTEL_GEN(dev_priv) < 4 ||
7285 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7286 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7288 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7290 pipeconf |= PIPECONF_PROGRESSIVE;
7292 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7293 intel_crtc->config->limited_color_range)
7294 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7296 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7297 POSTING_READ(PIPECONF(intel_crtc->pipe));
7300 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7301 struct intel_crtc_state *crtc_state)
7303 struct drm_device *dev = crtc->base.dev;
7304 struct drm_i915_private *dev_priv = to_i915(dev);
7305 const struct intel_limit *limit;
7308 memset(&crtc_state->dpll_hw_state, 0,
7309 sizeof(crtc_state->dpll_hw_state));
7311 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7312 if (intel_panel_use_ssc(dev_priv)) {
7313 refclk = dev_priv->vbt.lvds_ssc_freq;
7314 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7317 limit = &intel_limits_i8xx_lvds;
7318 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7319 limit = &intel_limits_i8xx_dvo;
7321 limit = &intel_limits_i8xx_dac;
7324 if (!crtc_state->clock_set &&
7325 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7326 refclk, NULL, &crtc_state->dpll)) {
7327 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7331 i8xx_compute_dpll(crtc, crtc_state, NULL);
7336 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7337 struct intel_crtc_state *crtc_state)
7339 struct drm_device *dev = crtc->base.dev;
7340 struct drm_i915_private *dev_priv = to_i915(dev);
7341 const struct intel_limit *limit;
7344 memset(&crtc_state->dpll_hw_state, 0,
7345 sizeof(crtc_state->dpll_hw_state));
7347 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7348 if (intel_panel_use_ssc(dev_priv)) {
7349 refclk = dev_priv->vbt.lvds_ssc_freq;
7350 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7353 if (intel_is_dual_link_lvds(dev))
7354 limit = &intel_limits_g4x_dual_channel_lvds;
7356 limit = &intel_limits_g4x_single_channel_lvds;
7357 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7358 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7359 limit = &intel_limits_g4x_hdmi;
7360 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7361 limit = &intel_limits_g4x_sdvo;
7363 /* The option is for other outputs */
7364 limit = &intel_limits_i9xx_sdvo;
7367 if (!crtc_state->clock_set &&
7368 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7369 refclk, NULL, &crtc_state->dpll)) {
7370 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7374 i9xx_compute_dpll(crtc, crtc_state, NULL);
7379 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7380 struct intel_crtc_state *crtc_state)
7382 struct drm_device *dev = crtc->base.dev;
7383 struct drm_i915_private *dev_priv = to_i915(dev);
7384 const struct intel_limit *limit;
7387 memset(&crtc_state->dpll_hw_state, 0,
7388 sizeof(crtc_state->dpll_hw_state));
7390 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7391 if (intel_panel_use_ssc(dev_priv)) {
7392 refclk = dev_priv->vbt.lvds_ssc_freq;
7393 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7396 limit = &intel_limits_pineview_lvds;
7398 limit = &intel_limits_pineview_sdvo;
7401 if (!crtc_state->clock_set &&
7402 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7403 refclk, NULL, &crtc_state->dpll)) {
7404 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7408 i9xx_compute_dpll(crtc, crtc_state, NULL);
7413 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7414 struct intel_crtc_state *crtc_state)
7416 struct drm_device *dev = crtc->base.dev;
7417 struct drm_i915_private *dev_priv = to_i915(dev);
7418 const struct intel_limit *limit;
7421 memset(&crtc_state->dpll_hw_state, 0,
7422 sizeof(crtc_state->dpll_hw_state));
7424 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7425 if (intel_panel_use_ssc(dev_priv)) {
7426 refclk = dev_priv->vbt.lvds_ssc_freq;
7427 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7430 limit = &intel_limits_i9xx_lvds;
7432 limit = &intel_limits_i9xx_sdvo;
7435 if (!crtc_state->clock_set &&
7436 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7437 refclk, NULL, &crtc_state->dpll)) {
7438 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7442 i9xx_compute_dpll(crtc, crtc_state, NULL);
7447 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7448 struct intel_crtc_state *crtc_state)
7450 int refclk = 100000;
7451 const struct intel_limit *limit = &intel_limits_chv;
7453 memset(&crtc_state->dpll_hw_state, 0,
7454 sizeof(crtc_state->dpll_hw_state));
7456 if (!crtc_state->clock_set &&
7457 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7458 refclk, NULL, &crtc_state->dpll)) {
7459 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7463 chv_compute_dpll(crtc, crtc_state);
7468 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7469 struct intel_crtc_state *crtc_state)
7471 int refclk = 100000;
7472 const struct intel_limit *limit = &intel_limits_vlv;
7474 memset(&crtc_state->dpll_hw_state, 0,
7475 sizeof(crtc_state->dpll_hw_state));
7477 if (!crtc_state->clock_set &&
7478 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7479 refclk, NULL, &crtc_state->dpll)) {
7480 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7484 vlv_compute_dpll(crtc, crtc_state);
7489 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7490 struct intel_crtc_state *pipe_config)
7492 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7495 if (INTEL_GEN(dev_priv) <= 3 &&
7496 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7499 tmp = I915_READ(PFIT_CONTROL);
7500 if (!(tmp & PFIT_ENABLE))
7503 /* Check whether the pfit is attached to our pipe. */
7504 if (INTEL_GEN(dev_priv) < 4) {
7505 if (crtc->pipe != PIPE_B)
7508 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7512 pipe_config->gmch_pfit.control = tmp;
7513 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7516 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7517 struct intel_crtc_state *pipe_config)
7519 struct drm_device *dev = crtc->base.dev;
7520 struct drm_i915_private *dev_priv = to_i915(dev);
7521 int pipe = pipe_config->cpu_transcoder;
7524 int refclk = 100000;
7526 /* In case of DSI, DPLL will not be used */
7527 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7530 mutex_lock(&dev_priv->sb_lock);
7531 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7532 mutex_unlock(&dev_priv->sb_lock);
7534 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7535 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7536 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7537 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7538 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7540 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7544 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7545 struct intel_initial_plane_config *plane_config)
7547 struct drm_device *dev = crtc->base.dev;
7548 struct drm_i915_private *dev_priv = to_i915(dev);
7549 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7550 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7551 enum pipe pipe = crtc->pipe;
7552 u32 val, base, offset;
7553 int fourcc, pixel_format;
7554 unsigned int aligned_height;
7555 struct drm_framebuffer *fb;
7556 struct intel_framebuffer *intel_fb;
7558 if (!plane->get_hw_state(plane))
7561 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7563 DRM_DEBUG_KMS("failed to alloc fb\n");
7567 fb = &intel_fb->base;
7571 val = I915_READ(DSPCNTR(i9xx_plane));
7573 if (INTEL_GEN(dev_priv) >= 4) {
7574 if (val & DISPPLANE_TILED) {
7575 plane_config->tiling = I915_TILING_X;
7576 fb->modifier = I915_FORMAT_MOD_X_TILED;
7580 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7581 fourcc = i9xx_format_to_fourcc(pixel_format);
7582 fb->format = drm_format_info(fourcc);
7584 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7585 offset = I915_READ(DSPOFFSET(i9xx_plane));
7586 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7587 } else if (INTEL_GEN(dev_priv) >= 4) {
7588 if (plane_config->tiling)
7589 offset = I915_READ(DSPTILEOFF(i9xx_plane));
7591 offset = I915_READ(DSPLINOFF(i9xx_plane));
7592 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7594 base = I915_READ(DSPADDR(i9xx_plane));
7596 plane_config->base = base;
7598 val = I915_READ(PIPESRC(pipe));
7599 fb->width = ((val >> 16) & 0xfff) + 1;
7600 fb->height = ((val >> 0) & 0xfff) + 1;
7602 val = I915_READ(DSPSTRIDE(i9xx_plane));
7603 fb->pitches[0] = val & 0xffffffc0;
7605 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7607 plane_config->size = fb->pitches[0] * aligned_height;
7609 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7610 crtc->base.name, plane->base.name, fb->width, fb->height,
7611 fb->format->cpp[0] * 8, base, fb->pitches[0],
7612 plane_config->size);
7614 plane_config->fb = intel_fb;
7617 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7618 struct intel_crtc_state *pipe_config)
7620 struct drm_device *dev = crtc->base.dev;
7621 struct drm_i915_private *dev_priv = to_i915(dev);
7622 int pipe = pipe_config->cpu_transcoder;
7623 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7625 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7626 int refclk = 100000;
7628 /* In case of DSI, DPLL will not be used */
7629 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7632 mutex_lock(&dev_priv->sb_lock);
7633 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7634 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7635 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7636 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7637 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7638 mutex_unlock(&dev_priv->sb_lock);
7640 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7641 clock.m2 = (pll_dw0 & 0xff) << 22;
7642 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7643 clock.m2 |= pll_dw2 & 0x3fffff;
7644 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7645 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7646 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7648 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7651 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7652 struct intel_crtc_state *pipe_config)
7654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7655 enum intel_display_power_domain power_domain;
7659 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7660 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7663 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7664 pipe_config->shared_dpll = NULL;
7668 tmp = I915_READ(PIPECONF(crtc->pipe));
7669 if (!(tmp & PIPECONF_ENABLE))
7672 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7673 IS_CHERRYVIEW(dev_priv)) {
7674 switch (tmp & PIPECONF_BPC_MASK) {
7676 pipe_config->pipe_bpp = 18;
7679 pipe_config->pipe_bpp = 24;
7681 case PIPECONF_10BPC:
7682 pipe_config->pipe_bpp = 30;
7689 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7690 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7691 pipe_config->limited_color_range = true;
7693 if (INTEL_GEN(dev_priv) < 4)
7694 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7696 intel_get_pipe_timings(crtc, pipe_config);
7697 intel_get_pipe_src_size(crtc, pipe_config);
7699 i9xx_get_pfit_config(crtc, pipe_config);
7701 if (INTEL_GEN(dev_priv) >= 4) {
7702 /* No way to read it out on pipes B and C */
7703 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7704 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7706 tmp = I915_READ(DPLL_MD(crtc->pipe));
7707 pipe_config->pixel_multiplier =
7708 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7709 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7710 pipe_config->dpll_hw_state.dpll_md = tmp;
7711 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7712 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7713 tmp = I915_READ(DPLL(crtc->pipe));
7714 pipe_config->pixel_multiplier =
7715 ((tmp & SDVO_MULTIPLIER_MASK)
7716 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7718 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7719 * port and will be fixed up in the encoder->get_config
7721 pipe_config->pixel_multiplier = 1;
7723 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7724 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7726 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7727 * on 830. Filter it out here so that we don't
7728 * report errors due to that.
7730 if (IS_I830(dev_priv))
7731 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7733 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7734 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7736 /* Mask out read-only status bits. */
7737 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7738 DPLL_PORTC_READY_MASK |
7739 DPLL_PORTB_READY_MASK);
7742 if (IS_CHERRYVIEW(dev_priv))
7743 chv_crtc_clock_get(crtc, pipe_config);
7744 else if (IS_VALLEYVIEW(dev_priv))
7745 vlv_crtc_clock_get(crtc, pipe_config);
7747 i9xx_crtc_clock_get(crtc, pipe_config);
7750 * Normally the dotclock is filled in by the encoder .get_config()
7751 * but in case the pipe is enabled w/o any ports we need a sane
7754 pipe_config->base.adjusted_mode.crtc_clock =
7755 pipe_config->port_clock / pipe_config->pixel_multiplier;
7760 intel_display_power_put(dev_priv, power_domain);
7765 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7767 struct intel_encoder *encoder;
7770 bool has_lvds = false;
7771 bool has_cpu_edp = false;
7772 bool has_panel = false;
7773 bool has_ck505 = false;
7774 bool can_ssc = false;
7775 bool using_ssc_source = false;
7777 /* We need to take the global config into account */
7778 for_each_intel_encoder(&dev_priv->drm, encoder) {
7779 switch (encoder->type) {
7780 case INTEL_OUTPUT_LVDS:
7784 case INTEL_OUTPUT_EDP:
7786 if (encoder->port == PORT_A)
7794 if (HAS_PCH_IBX(dev_priv)) {
7795 has_ck505 = dev_priv->vbt.display_clock_mode;
7796 can_ssc = has_ck505;
7802 /* Check if any DPLLs are using the SSC source */
7803 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7804 u32 temp = I915_READ(PCH_DPLL(i));
7806 if (!(temp & DPLL_VCO_ENABLE))
7809 if ((temp & PLL_REF_INPUT_MASK) ==
7810 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7811 using_ssc_source = true;
7816 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7817 has_panel, has_lvds, has_ck505, using_ssc_source);
7819 /* Ironlake: try to setup display ref clock before DPLL
7820 * enabling. This is only under driver's control after
7821 * PCH B stepping, previous chipset stepping should be
7822 * ignoring this setting.
7824 val = I915_READ(PCH_DREF_CONTROL);
7826 /* As we must carefully and slowly disable/enable each source in turn,
7827 * compute the final state we want first and check if we need to
7828 * make any changes at all.
7831 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7833 final |= DREF_NONSPREAD_CK505_ENABLE;
7835 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7837 final &= ~DREF_SSC_SOURCE_MASK;
7838 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7839 final &= ~DREF_SSC1_ENABLE;
7842 final |= DREF_SSC_SOURCE_ENABLE;
7844 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7845 final |= DREF_SSC1_ENABLE;
7848 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7849 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7851 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7853 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7854 } else if (using_ssc_source) {
7855 final |= DREF_SSC_SOURCE_ENABLE;
7856 final |= DREF_SSC1_ENABLE;
7862 /* Always enable nonspread source */
7863 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7866 val |= DREF_NONSPREAD_CK505_ENABLE;
7868 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7871 val &= ~DREF_SSC_SOURCE_MASK;
7872 val |= DREF_SSC_SOURCE_ENABLE;
7874 /* SSC must be turned on before enabling the CPU output */
7875 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7876 DRM_DEBUG_KMS("Using SSC on panel\n");
7877 val |= DREF_SSC1_ENABLE;
7879 val &= ~DREF_SSC1_ENABLE;
7881 /* Get SSC going before enabling the outputs */
7882 I915_WRITE(PCH_DREF_CONTROL, val);
7883 POSTING_READ(PCH_DREF_CONTROL);
7886 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7888 /* Enable CPU source on CPU attached eDP */
7890 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7891 DRM_DEBUG_KMS("Using SSC on eDP\n");
7892 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7894 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7896 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7898 I915_WRITE(PCH_DREF_CONTROL, val);
7899 POSTING_READ(PCH_DREF_CONTROL);
7902 DRM_DEBUG_KMS("Disabling CPU source output\n");
7904 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7906 /* Turn off CPU output */
7907 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7909 I915_WRITE(PCH_DREF_CONTROL, val);
7910 POSTING_READ(PCH_DREF_CONTROL);
7913 if (!using_ssc_source) {
7914 DRM_DEBUG_KMS("Disabling SSC source\n");
7916 /* Turn off the SSC source */
7917 val &= ~DREF_SSC_SOURCE_MASK;
7918 val |= DREF_SSC_SOURCE_DISABLE;
7921 val &= ~DREF_SSC1_ENABLE;
7923 I915_WRITE(PCH_DREF_CONTROL, val);
7924 POSTING_READ(PCH_DREF_CONTROL);
7929 BUG_ON(val != final);
7932 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7936 tmp = I915_READ(SOUTH_CHICKEN2);
7937 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7938 I915_WRITE(SOUTH_CHICKEN2, tmp);
7940 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7941 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7942 DRM_ERROR("FDI mPHY reset assert timeout\n");
7944 tmp = I915_READ(SOUTH_CHICKEN2);
7945 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7946 I915_WRITE(SOUTH_CHICKEN2, tmp);
7948 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7949 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7950 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7953 /* WaMPhyProgramming:hsw */
7954 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7958 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7959 tmp &= ~(0xFF << 24);
7960 tmp |= (0x12 << 24);
7961 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7963 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7965 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7967 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7969 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7971 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7972 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7973 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7975 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7976 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7977 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7979 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7982 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7984 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7987 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7989 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7992 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7994 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7997 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7999 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8000 tmp &= ~(0xFF << 16);
8001 tmp |= (0x1C << 16);
8002 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8004 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8005 tmp &= ~(0xFF << 16);
8006 tmp |= (0x1C << 16);
8007 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8009 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8011 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8013 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8015 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8017 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8018 tmp &= ~(0xF << 28);
8020 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8022 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8023 tmp &= ~(0xF << 28);
8025 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8028 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8029 * Programming" based on the parameters passed:
8030 * - Sequence to enable CLKOUT_DP
8031 * - Sequence to enable CLKOUT_DP without spread
8032 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8034 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8035 bool with_spread, bool with_fdi)
8039 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8041 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8042 with_fdi, "LP PCH doesn't have FDI\n"))
8045 mutex_lock(&dev_priv->sb_lock);
8047 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8048 tmp &= ~SBI_SSCCTL_DISABLE;
8049 tmp |= SBI_SSCCTL_PATHALT;
8050 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8055 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8056 tmp &= ~SBI_SSCCTL_PATHALT;
8057 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8060 lpt_reset_fdi_mphy(dev_priv);
8061 lpt_program_fdi_mphy(dev_priv);
8065 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8066 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8067 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8068 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8070 mutex_unlock(&dev_priv->sb_lock);
8073 /* Sequence to disable CLKOUT_DP */
8074 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8078 mutex_lock(&dev_priv->sb_lock);
8080 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8081 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8082 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8083 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8085 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8086 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8087 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8088 tmp |= SBI_SSCCTL_PATHALT;
8089 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8092 tmp |= SBI_SSCCTL_DISABLE;
8093 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8096 mutex_unlock(&dev_priv->sb_lock);
8099 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8101 static const uint16_t sscdivintphase[] = {
8102 [BEND_IDX( 50)] = 0x3B23,
8103 [BEND_IDX( 45)] = 0x3B23,
8104 [BEND_IDX( 40)] = 0x3C23,
8105 [BEND_IDX( 35)] = 0x3C23,
8106 [BEND_IDX( 30)] = 0x3D23,
8107 [BEND_IDX( 25)] = 0x3D23,
8108 [BEND_IDX( 20)] = 0x3E23,
8109 [BEND_IDX( 15)] = 0x3E23,
8110 [BEND_IDX( 10)] = 0x3F23,
8111 [BEND_IDX( 5)] = 0x3F23,
8112 [BEND_IDX( 0)] = 0x0025,
8113 [BEND_IDX( -5)] = 0x0025,
8114 [BEND_IDX(-10)] = 0x0125,
8115 [BEND_IDX(-15)] = 0x0125,
8116 [BEND_IDX(-20)] = 0x0225,
8117 [BEND_IDX(-25)] = 0x0225,
8118 [BEND_IDX(-30)] = 0x0325,
8119 [BEND_IDX(-35)] = 0x0325,
8120 [BEND_IDX(-40)] = 0x0425,
8121 [BEND_IDX(-45)] = 0x0425,
8122 [BEND_IDX(-50)] = 0x0525,
8127 * steps -50 to 50 inclusive, in steps of 5
8128 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8129 * change in clock period = -(steps / 10) * 5.787 ps
8131 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8134 int idx = BEND_IDX(steps);
8136 if (WARN_ON(steps % 5 != 0))
8139 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8142 mutex_lock(&dev_priv->sb_lock);
8144 if (steps % 10 != 0)
8148 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8150 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8152 tmp |= sscdivintphase[idx];
8153 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8155 mutex_unlock(&dev_priv->sb_lock);
8160 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8162 struct intel_encoder *encoder;
8163 bool has_vga = false;
8165 for_each_intel_encoder(&dev_priv->drm, encoder) {
8166 switch (encoder->type) {
8167 case INTEL_OUTPUT_ANALOG:
8176 lpt_bend_clkout_dp(dev_priv, 0);
8177 lpt_enable_clkout_dp(dev_priv, true, true);
8179 lpt_disable_clkout_dp(dev_priv);
8184 * Initialize reference clocks when the driver loads
8186 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8188 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8189 ironlake_init_pch_refclk(dev_priv);
8190 else if (HAS_PCH_LPT(dev_priv))
8191 lpt_init_pch_refclk(dev_priv);
8194 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8196 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8198 int pipe = intel_crtc->pipe;
8203 switch (intel_crtc->config->pipe_bpp) {
8205 val |= PIPECONF_6BPC;
8208 val |= PIPECONF_8BPC;
8211 val |= PIPECONF_10BPC;
8214 val |= PIPECONF_12BPC;
8217 /* Case prevented by intel_choose_pipe_bpp_dither. */
8221 if (intel_crtc->config->dither)
8222 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8224 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8225 val |= PIPECONF_INTERLACED_ILK;
8227 val |= PIPECONF_PROGRESSIVE;
8229 if (intel_crtc->config->limited_color_range)
8230 val |= PIPECONF_COLOR_RANGE_SELECT;
8232 I915_WRITE(PIPECONF(pipe), val);
8233 POSTING_READ(PIPECONF(pipe));
8236 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8238 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8240 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8243 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8244 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8246 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8247 val |= PIPECONF_INTERLACED_ILK;
8249 val |= PIPECONF_PROGRESSIVE;
8251 I915_WRITE(PIPECONF(cpu_transcoder), val);
8252 POSTING_READ(PIPECONF(cpu_transcoder));
8255 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8257 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8259 struct intel_crtc_state *config = intel_crtc->config;
8261 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8264 switch (intel_crtc->config->pipe_bpp) {
8266 val |= PIPEMISC_DITHER_6_BPC;
8269 val |= PIPEMISC_DITHER_8_BPC;
8272 val |= PIPEMISC_DITHER_10_BPC;
8275 val |= PIPEMISC_DITHER_12_BPC;
8278 /* Case prevented by pipe_config_set_bpp. */
8282 if (intel_crtc->config->dither)
8283 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8285 if (config->ycbcr420) {
8286 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8287 PIPEMISC_YUV420_ENABLE |
8288 PIPEMISC_YUV420_MODE_FULL_BLEND;
8291 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8295 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8298 * Account for spread spectrum to avoid
8299 * oversubscribing the link. Max center spread
8300 * is 2.5%; use 5% for safety's sake.
8302 u32 bps = target_clock * bpp * 21 / 20;
8303 return DIV_ROUND_UP(bps, link_bw * 8);
8306 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8308 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8311 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8312 struct intel_crtc_state *crtc_state,
8313 struct dpll *reduced_clock)
8315 struct drm_crtc *crtc = &intel_crtc->base;
8316 struct drm_device *dev = crtc->dev;
8317 struct drm_i915_private *dev_priv = to_i915(dev);
8321 /* Enable autotuning of the PLL clock (if permissible) */
8323 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8324 if ((intel_panel_use_ssc(dev_priv) &&
8325 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8326 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8328 } else if (crtc_state->sdvo_tv_clock)
8331 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8333 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8336 if (reduced_clock) {
8337 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8339 if (reduced_clock->m < factor * reduced_clock->n)
8347 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8348 dpll |= DPLLB_MODE_LVDS;
8350 dpll |= DPLLB_MODE_DAC_SERIAL;
8352 dpll |= (crtc_state->pixel_multiplier - 1)
8353 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8355 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8356 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8357 dpll |= DPLL_SDVO_HIGH_SPEED;
8359 if (intel_crtc_has_dp_encoder(crtc_state))
8360 dpll |= DPLL_SDVO_HIGH_SPEED;
8363 * The high speed IO clock is only really required for
8364 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8365 * possible to share the DPLL between CRT and HDMI. Enabling
8366 * the clock needlessly does no real harm, except use up a
8367 * bit of power potentially.
8369 * We'll limit this to IVB with 3 pipes, since it has only two
8370 * DPLLs and so DPLL sharing is the only way to get three pipes
8371 * driving PCH ports at the same time. On SNB we could do this,
8372 * and potentially avoid enabling the second DPLL, but it's not
8373 * clear if it''s a win or loss power wise. No point in doing
8374 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8376 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8377 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8378 dpll |= DPLL_SDVO_HIGH_SPEED;
8380 /* compute bitmask from p1 value */
8381 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8383 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8385 switch (crtc_state->dpll.p2) {
8387 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8390 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8393 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8396 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8400 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8401 intel_panel_use_ssc(dev_priv))
8402 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8404 dpll |= PLL_REF_INPUT_DREFCLK;
8406 dpll |= DPLL_VCO_ENABLE;
8408 crtc_state->dpll_hw_state.dpll = dpll;
8409 crtc_state->dpll_hw_state.fp0 = fp;
8410 crtc_state->dpll_hw_state.fp1 = fp2;
8413 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8414 struct intel_crtc_state *crtc_state)
8416 struct drm_device *dev = crtc->base.dev;
8417 struct drm_i915_private *dev_priv = to_i915(dev);
8418 const struct intel_limit *limit;
8419 int refclk = 120000;
8421 memset(&crtc_state->dpll_hw_state, 0,
8422 sizeof(crtc_state->dpll_hw_state));
8424 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8425 if (!crtc_state->has_pch_encoder)
8428 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8429 if (intel_panel_use_ssc(dev_priv)) {
8430 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8431 dev_priv->vbt.lvds_ssc_freq);
8432 refclk = dev_priv->vbt.lvds_ssc_freq;
8435 if (intel_is_dual_link_lvds(dev)) {
8436 if (refclk == 100000)
8437 limit = &intel_limits_ironlake_dual_lvds_100m;
8439 limit = &intel_limits_ironlake_dual_lvds;
8441 if (refclk == 100000)
8442 limit = &intel_limits_ironlake_single_lvds_100m;
8444 limit = &intel_limits_ironlake_single_lvds;
8447 limit = &intel_limits_ironlake_dac;
8450 if (!crtc_state->clock_set &&
8451 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8452 refclk, NULL, &crtc_state->dpll)) {
8453 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8457 ironlake_compute_dpll(crtc, crtc_state, NULL);
8459 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8460 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8461 pipe_name(crtc->pipe));
8468 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8469 struct intel_link_m_n *m_n)
8471 struct drm_device *dev = crtc->base.dev;
8472 struct drm_i915_private *dev_priv = to_i915(dev);
8473 enum pipe pipe = crtc->pipe;
8475 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8476 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8477 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8479 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8480 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8481 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8484 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8485 enum transcoder transcoder,
8486 struct intel_link_m_n *m_n,
8487 struct intel_link_m_n *m2_n2)
8489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8490 enum pipe pipe = crtc->pipe;
8492 if (INTEL_GEN(dev_priv) >= 5) {
8493 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8494 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8495 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8497 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8498 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8499 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8500 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8501 * gen < 8) and if DRRS is supported (to make sure the
8502 * registers are not unnecessarily read).
8504 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8505 crtc->config->has_drrs) {
8506 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8507 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8508 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8510 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8511 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8512 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8515 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8516 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8517 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8519 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8520 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8521 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8525 void intel_dp_get_m_n(struct intel_crtc *crtc,
8526 struct intel_crtc_state *pipe_config)
8528 if (pipe_config->has_pch_encoder)
8529 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8531 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8532 &pipe_config->dp_m_n,
8533 &pipe_config->dp_m2_n2);
8536 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8537 struct intel_crtc_state *pipe_config)
8539 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8540 &pipe_config->fdi_m_n, NULL);
8543 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8544 struct intel_crtc_state *pipe_config)
8546 struct drm_device *dev = crtc->base.dev;
8547 struct drm_i915_private *dev_priv = to_i915(dev);
8548 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8549 uint32_t ps_ctrl = 0;
8553 /* find scaler attached to this pipe */
8554 for (i = 0; i < crtc->num_scalers; i++) {
8555 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8556 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8558 pipe_config->pch_pfit.enabled = true;
8559 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8560 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8565 scaler_state->scaler_id = id;
8567 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8569 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8574 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8575 struct intel_initial_plane_config *plane_config)
8577 struct drm_device *dev = crtc->base.dev;
8578 struct drm_i915_private *dev_priv = to_i915(dev);
8579 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8580 enum plane_id plane_id = plane->id;
8581 enum pipe pipe = crtc->pipe;
8582 u32 val, base, offset, stride_mult, tiling, alpha;
8583 int fourcc, pixel_format;
8584 unsigned int aligned_height;
8585 struct drm_framebuffer *fb;
8586 struct intel_framebuffer *intel_fb;
8588 if (!plane->get_hw_state(plane))
8591 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8593 DRM_DEBUG_KMS("failed to alloc fb\n");
8597 fb = &intel_fb->base;
8601 val = I915_READ(PLANE_CTL(pipe, plane_id));
8603 if (INTEL_GEN(dev_priv) >= 11)
8604 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8606 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8608 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8609 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8610 alpha &= PLANE_COLOR_ALPHA_MASK;
8612 alpha = val & PLANE_CTL_ALPHA_MASK;
8615 fourcc = skl_format_to_fourcc(pixel_format,
8616 val & PLANE_CTL_ORDER_RGBX, alpha);
8617 fb->format = drm_format_info(fourcc);
8619 tiling = val & PLANE_CTL_TILED_MASK;
8621 case PLANE_CTL_TILED_LINEAR:
8622 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8624 case PLANE_CTL_TILED_X:
8625 plane_config->tiling = I915_TILING_X;
8626 fb->modifier = I915_FORMAT_MOD_X_TILED;
8628 case PLANE_CTL_TILED_Y:
8629 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8630 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8632 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8634 case PLANE_CTL_TILED_YF:
8635 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8636 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8638 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8641 MISSING_CASE(tiling);
8645 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8646 plane_config->base = base;
8648 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8650 val = I915_READ(PLANE_SIZE(pipe, plane_id));
8651 fb->height = ((val >> 16) & 0xfff) + 1;
8652 fb->width = ((val >> 0) & 0x1fff) + 1;
8654 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8655 stride_mult = intel_fb_stride_alignment(fb, 0);
8656 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8658 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8660 plane_config->size = fb->pitches[0] * aligned_height;
8662 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8663 crtc->base.name, plane->base.name, fb->width, fb->height,
8664 fb->format->cpp[0] * 8, base, fb->pitches[0],
8665 plane_config->size);
8667 plane_config->fb = intel_fb;
8674 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8675 struct intel_crtc_state *pipe_config)
8677 struct drm_device *dev = crtc->base.dev;
8678 struct drm_i915_private *dev_priv = to_i915(dev);
8681 tmp = I915_READ(PF_CTL(crtc->pipe));
8683 if (tmp & PF_ENABLE) {
8684 pipe_config->pch_pfit.enabled = true;
8685 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8686 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8688 /* We currently do not free assignements of panel fitters on
8689 * ivb/hsw (since we don't use the higher upscaling modes which
8690 * differentiates them) so just WARN about this case for now. */
8691 if (IS_GEN7(dev_priv)) {
8692 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8693 PF_PIPE_SEL_IVB(crtc->pipe));
8698 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8699 struct intel_crtc_state *pipe_config)
8701 struct drm_device *dev = crtc->base.dev;
8702 struct drm_i915_private *dev_priv = to_i915(dev);
8703 enum intel_display_power_domain power_domain;
8707 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8708 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8711 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8712 pipe_config->shared_dpll = NULL;
8715 tmp = I915_READ(PIPECONF(crtc->pipe));
8716 if (!(tmp & PIPECONF_ENABLE))
8719 switch (tmp & PIPECONF_BPC_MASK) {
8721 pipe_config->pipe_bpp = 18;
8724 pipe_config->pipe_bpp = 24;
8726 case PIPECONF_10BPC:
8727 pipe_config->pipe_bpp = 30;
8729 case PIPECONF_12BPC:
8730 pipe_config->pipe_bpp = 36;
8736 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8737 pipe_config->limited_color_range = true;
8739 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8740 struct intel_shared_dpll *pll;
8741 enum intel_dpll_id pll_id;
8743 pipe_config->has_pch_encoder = true;
8745 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8746 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8747 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8749 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8751 if (HAS_PCH_IBX(dev_priv)) {
8753 * The pipe->pch transcoder and pch transcoder->pll
8756 pll_id = (enum intel_dpll_id) crtc->pipe;
8758 tmp = I915_READ(PCH_DPLL_SEL);
8759 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8760 pll_id = DPLL_ID_PCH_PLL_B;
8762 pll_id= DPLL_ID_PCH_PLL_A;
8765 pipe_config->shared_dpll =
8766 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8767 pll = pipe_config->shared_dpll;
8769 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8770 &pipe_config->dpll_hw_state));
8772 tmp = pipe_config->dpll_hw_state.dpll;
8773 pipe_config->pixel_multiplier =
8774 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8775 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8777 ironlake_pch_clock_get(crtc, pipe_config);
8779 pipe_config->pixel_multiplier = 1;
8782 intel_get_pipe_timings(crtc, pipe_config);
8783 intel_get_pipe_src_size(crtc, pipe_config);
8785 ironlake_get_pfit_config(crtc, pipe_config);
8790 intel_display_power_put(dev_priv, power_domain);
8795 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8797 struct drm_device *dev = &dev_priv->drm;
8798 struct intel_crtc *crtc;
8800 for_each_intel_crtc(dev, crtc)
8801 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8802 pipe_name(crtc->pipe));
8804 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8805 "Display power well on\n");
8806 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8807 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8808 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8809 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8810 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8811 "CPU PWM1 enabled\n");
8812 if (IS_HASWELL(dev_priv))
8813 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8814 "CPU PWM2 enabled\n");
8815 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8816 "PCH PWM1 enabled\n");
8817 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8818 "Utility pin enabled\n");
8819 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8822 * In theory we can still leave IRQs enabled, as long as only the HPD
8823 * interrupts remain enabled. We used to check for that, but since it's
8824 * gen-specific and since we only disable LCPLL after we fully disable
8825 * the interrupts, the check below should be enough.
8827 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8830 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8832 if (IS_HASWELL(dev_priv))
8833 return I915_READ(D_COMP_HSW);
8835 return I915_READ(D_COMP_BDW);
8838 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8840 if (IS_HASWELL(dev_priv)) {
8841 mutex_lock(&dev_priv->pcu_lock);
8842 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8844 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8845 mutex_unlock(&dev_priv->pcu_lock);
8847 I915_WRITE(D_COMP_BDW, val);
8848 POSTING_READ(D_COMP_BDW);
8853 * This function implements pieces of two sequences from BSpec:
8854 * - Sequence for display software to disable LCPLL
8855 * - Sequence for display software to allow package C8+
8856 * The steps implemented here are just the steps that actually touch the LCPLL
8857 * register. Callers should take care of disabling all the display engine
8858 * functions, doing the mode unset, fixing interrupts, etc.
8860 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8861 bool switch_to_fclk, bool allow_power_down)
8865 assert_can_disable_lcpll(dev_priv);
8867 val = I915_READ(LCPLL_CTL);
8869 if (switch_to_fclk) {
8870 val |= LCPLL_CD_SOURCE_FCLK;
8871 I915_WRITE(LCPLL_CTL, val);
8873 if (wait_for_us(I915_READ(LCPLL_CTL) &
8874 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8875 DRM_ERROR("Switching to FCLK failed\n");
8877 val = I915_READ(LCPLL_CTL);
8880 val |= LCPLL_PLL_DISABLE;
8881 I915_WRITE(LCPLL_CTL, val);
8882 POSTING_READ(LCPLL_CTL);
8884 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8885 DRM_ERROR("LCPLL still locked\n");
8887 val = hsw_read_dcomp(dev_priv);
8888 val |= D_COMP_COMP_DISABLE;
8889 hsw_write_dcomp(dev_priv, val);
8892 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8894 DRM_ERROR("D_COMP RCOMP still in progress\n");
8896 if (allow_power_down) {
8897 val = I915_READ(LCPLL_CTL);
8898 val |= LCPLL_POWER_DOWN_ALLOW;
8899 I915_WRITE(LCPLL_CTL, val);
8900 POSTING_READ(LCPLL_CTL);
8905 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8908 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8912 val = I915_READ(LCPLL_CTL);
8914 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8915 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8919 * Make sure we're not on PC8 state before disabling PC8, otherwise
8920 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8922 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8924 if (val & LCPLL_POWER_DOWN_ALLOW) {
8925 val &= ~LCPLL_POWER_DOWN_ALLOW;
8926 I915_WRITE(LCPLL_CTL, val);
8927 POSTING_READ(LCPLL_CTL);
8930 val = hsw_read_dcomp(dev_priv);
8931 val |= D_COMP_COMP_FORCE;
8932 val &= ~D_COMP_COMP_DISABLE;
8933 hsw_write_dcomp(dev_priv, val);
8935 val = I915_READ(LCPLL_CTL);
8936 val &= ~LCPLL_PLL_DISABLE;
8937 I915_WRITE(LCPLL_CTL, val);
8939 if (intel_wait_for_register(dev_priv,
8940 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8942 DRM_ERROR("LCPLL not locked yet\n");
8944 if (val & LCPLL_CD_SOURCE_FCLK) {
8945 val = I915_READ(LCPLL_CTL);
8946 val &= ~LCPLL_CD_SOURCE_FCLK;
8947 I915_WRITE(LCPLL_CTL, val);
8949 if (wait_for_us((I915_READ(LCPLL_CTL) &
8950 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8951 DRM_ERROR("Switching back to LCPLL failed\n");
8954 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8956 intel_update_cdclk(dev_priv);
8957 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
8961 * Package states C8 and deeper are really deep PC states that can only be
8962 * reached when all the devices on the system allow it, so even if the graphics
8963 * device allows PC8+, it doesn't mean the system will actually get to these
8964 * states. Our driver only allows PC8+ when going into runtime PM.
8966 * The requirements for PC8+ are that all the outputs are disabled, the power
8967 * well is disabled and most interrupts are disabled, and these are also
8968 * requirements for runtime PM. When these conditions are met, we manually do
8969 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8970 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8973 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8974 * the state of some registers, so when we come back from PC8+ we need to
8975 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8976 * need to take care of the registers kept by RC6. Notice that this happens even
8977 * if we don't put the device in PCI D3 state (which is what currently happens
8978 * because of the runtime PM support).
8980 * For more, read "Display Sequences for Package C8" on the hardware
8983 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8987 DRM_DEBUG_KMS("Enabling package C8+\n");
8989 if (HAS_PCH_LPT_LP(dev_priv)) {
8990 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8991 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8992 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8995 lpt_disable_clkout_dp(dev_priv);
8996 hsw_disable_lcpll(dev_priv, true, true);
8999 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9003 DRM_DEBUG_KMS("Disabling package C8+\n");
9005 hsw_restore_lcpll(dev_priv);
9006 lpt_init_pch_refclk(dev_priv);
9008 if (HAS_PCH_LPT_LP(dev_priv)) {
9009 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9010 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9011 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9015 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9016 struct intel_crtc_state *crtc_state)
9018 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9019 struct intel_encoder *encoder =
9020 intel_ddi_get_crtc_new_encoder(crtc_state);
9022 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9023 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9024 pipe_name(crtc->pipe));
9032 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9034 struct intel_crtc_state *pipe_config)
9036 enum intel_dpll_id id;
9039 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9040 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9042 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9045 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9048 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9050 struct intel_crtc_state *pipe_config)
9052 enum intel_dpll_id id;
9056 id = DPLL_ID_SKL_DPLL0;
9059 id = DPLL_ID_SKL_DPLL1;
9062 id = DPLL_ID_SKL_DPLL2;
9065 DRM_ERROR("Incorrect port type\n");
9069 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9072 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9074 struct intel_crtc_state *pipe_config)
9076 enum intel_dpll_id id;
9079 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9080 id = temp >> (port * 3 + 1);
9082 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9085 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9088 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9090 struct intel_crtc_state *pipe_config)
9092 enum intel_dpll_id id;
9093 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9095 switch (ddi_pll_sel) {
9096 case PORT_CLK_SEL_WRPLL1:
9097 id = DPLL_ID_WRPLL1;
9099 case PORT_CLK_SEL_WRPLL2:
9100 id = DPLL_ID_WRPLL2;
9102 case PORT_CLK_SEL_SPLL:
9105 case PORT_CLK_SEL_LCPLL_810:
9106 id = DPLL_ID_LCPLL_810;
9108 case PORT_CLK_SEL_LCPLL_1350:
9109 id = DPLL_ID_LCPLL_1350;
9111 case PORT_CLK_SEL_LCPLL_2700:
9112 id = DPLL_ID_LCPLL_2700;
9115 MISSING_CASE(ddi_pll_sel);
9117 case PORT_CLK_SEL_NONE:
9121 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9124 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9125 struct intel_crtc_state *pipe_config,
9126 u64 *power_domain_mask)
9128 struct drm_device *dev = crtc->base.dev;
9129 struct drm_i915_private *dev_priv = to_i915(dev);
9130 enum intel_display_power_domain power_domain;
9134 * The pipe->transcoder mapping is fixed with the exception of the eDP
9135 * transcoder handled below.
9137 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9140 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9141 * consistency and less surprising code; it's in always on power).
9143 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9144 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9145 enum pipe trans_edp_pipe;
9146 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9148 WARN(1, "unknown pipe linked to edp transcoder\n");
9149 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9150 case TRANS_DDI_EDP_INPUT_A_ON:
9151 trans_edp_pipe = PIPE_A;
9153 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9154 trans_edp_pipe = PIPE_B;
9156 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9157 trans_edp_pipe = PIPE_C;
9161 if (trans_edp_pipe == crtc->pipe)
9162 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9165 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9166 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9168 *power_domain_mask |= BIT_ULL(power_domain);
9170 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9172 return tmp & PIPECONF_ENABLE;
9175 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9176 struct intel_crtc_state *pipe_config,
9177 u64 *power_domain_mask)
9179 struct drm_device *dev = crtc->base.dev;
9180 struct drm_i915_private *dev_priv = to_i915(dev);
9181 enum intel_display_power_domain power_domain;
9183 enum transcoder cpu_transcoder;
9186 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9188 cpu_transcoder = TRANSCODER_DSI_A;
9190 cpu_transcoder = TRANSCODER_DSI_C;
9192 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9193 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9195 *power_domain_mask |= BIT_ULL(power_domain);
9198 * The PLL needs to be enabled with a valid divider
9199 * configuration, otherwise accessing DSI registers will hang
9200 * the machine. See BSpec North Display Engine
9201 * registers/MIPI[BXT]. We can break out here early, since we
9202 * need the same DSI PLL to be enabled for both DSI ports.
9204 if (!intel_dsi_pll_is_enabled(dev_priv))
9207 /* XXX: this works for video mode only */
9208 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9209 if (!(tmp & DPI_ENABLE))
9212 tmp = I915_READ(MIPI_CTRL(port));
9213 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9216 pipe_config->cpu_transcoder = cpu_transcoder;
9220 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9223 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9224 struct intel_crtc_state *pipe_config)
9226 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9227 struct intel_shared_dpll *pll;
9231 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9233 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9235 if (IS_CANNONLAKE(dev_priv))
9236 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9237 else if (IS_GEN9_BC(dev_priv))
9238 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9239 else if (IS_GEN9_LP(dev_priv))
9240 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9242 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9244 pll = pipe_config->shared_dpll;
9246 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9247 &pipe_config->dpll_hw_state));
9251 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9252 * DDI E. So just check whether this pipe is wired to DDI E and whether
9253 * the PCH transcoder is on.
9255 if (INTEL_GEN(dev_priv) < 9 &&
9256 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9257 pipe_config->has_pch_encoder = true;
9259 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9260 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9261 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9263 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9267 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9268 struct intel_crtc_state *pipe_config)
9270 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9271 enum intel_display_power_domain power_domain;
9272 u64 power_domain_mask;
9275 intel_crtc_init_scalers(crtc, pipe_config);
9277 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9278 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9280 power_domain_mask = BIT_ULL(power_domain);
9282 pipe_config->shared_dpll = NULL;
9284 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9286 if (IS_GEN9_LP(dev_priv) &&
9287 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9295 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9296 haswell_get_ddi_port_state(crtc, pipe_config);
9297 intel_get_pipe_timings(crtc, pipe_config);
9300 intel_get_pipe_src_size(crtc, pipe_config);
9302 pipe_config->gamma_mode =
9303 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9305 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9306 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9307 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9309 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9310 bool blend_mode_420 = tmp &
9311 PIPEMISC_YUV420_MODE_FULL_BLEND;
9313 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9314 if (pipe_config->ycbcr420 != clrspace_yuv ||
9315 pipe_config->ycbcr420 != blend_mode_420)
9316 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9317 } else if (clrspace_yuv) {
9318 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9322 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9323 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9324 power_domain_mask |= BIT_ULL(power_domain);
9325 if (INTEL_GEN(dev_priv) >= 9)
9326 skylake_get_pfit_config(crtc, pipe_config);
9328 ironlake_get_pfit_config(crtc, pipe_config);
9331 if (hsw_crtc_supports_ips(crtc)) {
9332 if (IS_HASWELL(dev_priv))
9333 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9336 * We cannot readout IPS state on broadwell, set to
9337 * true so we can set it to a defined state on first
9340 pipe_config->ips_enabled = true;
9344 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9345 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9346 pipe_config->pixel_multiplier =
9347 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9349 pipe_config->pixel_multiplier = 1;
9353 for_each_power_domain(power_domain, power_domain_mask)
9354 intel_display_power_put(dev_priv, power_domain);
9359 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9361 struct drm_i915_private *dev_priv =
9362 to_i915(plane_state->base.plane->dev);
9363 const struct drm_framebuffer *fb = plane_state->base.fb;
9364 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9367 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9368 base = obj->phys_handle->busaddr;
9370 base = intel_plane_ggtt_offset(plane_state);
9372 base += plane_state->main.offset;
9374 /* ILK+ do this automagically */
9375 if (HAS_GMCH_DISPLAY(dev_priv) &&
9376 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9377 base += (plane_state->base.crtc_h *
9378 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9383 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9385 int x = plane_state->base.crtc_x;
9386 int y = plane_state->base.crtc_y;
9390 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9393 pos |= x << CURSOR_X_SHIFT;
9396 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9399 pos |= y << CURSOR_Y_SHIFT;
9404 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9406 const struct drm_mode_config *config =
9407 &plane_state->base.plane->dev->mode_config;
9408 int width = plane_state->base.crtc_w;
9409 int height = plane_state->base.crtc_h;
9411 return width > 0 && width <= config->cursor_width &&
9412 height > 0 && height <= config->cursor_height;
9415 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9416 struct intel_plane_state *plane_state)
9418 const struct drm_framebuffer *fb = plane_state->base.fb;
9423 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9425 DRM_PLANE_HELPER_NO_SCALING,
9426 DRM_PLANE_HELPER_NO_SCALING,
9434 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9435 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9439 src_x = plane_state->base.src_x >> 16;
9440 src_y = plane_state->base.src_y >> 16;
9442 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9443 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9445 if (src_x != 0 || src_y != 0) {
9446 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9450 plane_state->main.offset = offset;
9455 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9456 const struct intel_plane_state *plane_state)
9458 const struct drm_framebuffer *fb = plane_state->base.fb;
9460 return CURSOR_ENABLE |
9461 CURSOR_GAMMA_ENABLE |
9462 CURSOR_FORMAT_ARGB |
9463 CURSOR_STRIDE(fb->pitches[0]);
9466 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9468 int width = plane_state->base.crtc_w;
9471 * 845g/865g are only limited by the width of their cursors,
9472 * the height is arbitrary up to the precision of the register.
9474 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9477 static int i845_check_cursor(struct intel_plane *plane,
9478 struct intel_crtc_state *crtc_state,
9479 struct intel_plane_state *plane_state)
9481 const struct drm_framebuffer *fb = plane_state->base.fb;
9484 ret = intel_check_cursor(crtc_state, plane_state);
9488 /* if we want to turn off the cursor ignore width and height */
9492 /* Check for which cursor types we support */
9493 if (!i845_cursor_size_ok(plane_state)) {
9494 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9495 plane_state->base.crtc_w,
9496 plane_state->base.crtc_h);
9500 switch (fb->pitches[0]) {
9507 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9512 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9517 static void i845_update_cursor(struct intel_plane *plane,
9518 const struct intel_crtc_state *crtc_state,
9519 const struct intel_plane_state *plane_state)
9521 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9522 u32 cntl = 0, base = 0, pos = 0, size = 0;
9523 unsigned long irqflags;
9525 if (plane_state && plane_state->base.visible) {
9526 unsigned int width = plane_state->base.crtc_w;
9527 unsigned int height = plane_state->base.crtc_h;
9529 cntl = plane_state->ctl;
9530 size = (height << 12) | width;
9532 base = intel_cursor_base(plane_state);
9533 pos = intel_cursor_position(plane_state);
9536 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9538 /* On these chipsets we can only modify the base/size/stride
9539 * whilst the cursor is disabled.
9541 if (plane->cursor.base != base ||
9542 plane->cursor.size != size ||
9543 plane->cursor.cntl != cntl) {
9544 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9545 I915_WRITE_FW(CURBASE(PIPE_A), base);
9546 I915_WRITE_FW(CURSIZE, size);
9547 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9548 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9550 plane->cursor.base = base;
9551 plane->cursor.size = size;
9552 plane->cursor.cntl = cntl;
9554 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9557 POSTING_READ_FW(CURCNTR(PIPE_A));
9559 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9562 static void i845_disable_cursor(struct intel_plane *plane,
9563 struct intel_crtc *crtc)
9565 i845_update_cursor(plane, NULL, NULL);
9568 static bool i845_cursor_get_hw_state(struct intel_plane *plane)
9570 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9571 enum intel_display_power_domain power_domain;
9574 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9575 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9578 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9580 intel_display_power_put(dev_priv, power_domain);
9585 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9586 const struct intel_plane_state *plane_state)
9588 struct drm_i915_private *dev_priv =
9589 to_i915(plane_state->base.plane->dev);
9590 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9593 cntl = MCURSOR_GAMMA_ENABLE;
9595 if (HAS_DDI(dev_priv))
9596 cntl |= CURSOR_PIPE_CSC_ENABLE;
9598 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9599 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9601 switch (plane_state->base.crtc_w) {
9603 cntl |= CURSOR_MODE_64_ARGB_AX;
9606 cntl |= CURSOR_MODE_128_ARGB_AX;
9609 cntl |= CURSOR_MODE_256_ARGB_AX;
9612 MISSING_CASE(plane_state->base.crtc_w);
9616 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9617 cntl |= CURSOR_ROTATE_180;
9622 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9624 struct drm_i915_private *dev_priv =
9625 to_i915(plane_state->base.plane->dev);
9626 int width = plane_state->base.crtc_w;
9627 int height = plane_state->base.crtc_h;
9629 if (!intel_cursor_size_ok(plane_state))
9632 /* Cursor width is limited to a few power-of-two sizes */
9643 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9644 * height from 8 lines up to the cursor width, when the
9645 * cursor is not rotated. Everything else requires square
9648 if (HAS_CUR_FBC(dev_priv) &&
9649 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9650 if (height < 8 || height > width)
9653 if (height != width)
9660 static int i9xx_check_cursor(struct intel_plane *plane,
9661 struct intel_crtc_state *crtc_state,
9662 struct intel_plane_state *plane_state)
9664 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9665 const struct drm_framebuffer *fb = plane_state->base.fb;
9666 enum pipe pipe = plane->pipe;
9669 ret = intel_check_cursor(crtc_state, plane_state);
9673 /* if we want to turn off the cursor ignore width and height */
9677 /* Check for which cursor types we support */
9678 if (!i9xx_cursor_size_ok(plane_state)) {
9679 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9680 plane_state->base.crtc_w,
9681 plane_state->base.crtc_h);
9685 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9686 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9687 fb->pitches[0], plane_state->base.crtc_w);
9692 * There's something wrong with the cursor on CHV pipe C.
9693 * If it straddles the left edge of the screen then
9694 * moving it away from the edge or disabling it often
9695 * results in a pipe underrun, and often that can lead to
9696 * dead pipe (constant underrun reported, and it scans
9697 * out just a solid color). To recover from that, the
9698 * display power well must be turned off and on again.
9699 * Refuse the put the cursor into that compromised position.
9701 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9702 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9703 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9707 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9712 static void i9xx_update_cursor(struct intel_plane *plane,
9713 const struct intel_crtc_state *crtc_state,
9714 const struct intel_plane_state *plane_state)
9716 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9717 enum pipe pipe = plane->pipe;
9718 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9719 unsigned long irqflags;
9721 if (plane_state && plane_state->base.visible) {
9722 cntl = plane_state->ctl;
9724 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9725 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9727 base = intel_cursor_base(plane_state);
9728 pos = intel_cursor_position(plane_state);
9731 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9734 * On some platforms writing CURCNTR first will also
9735 * cause CURPOS to be armed by the CURBASE write.
9736 * Without the CURCNTR write the CURPOS write would
9737 * arm itself. Thus we always start the full update
9738 * with a CURCNTR write.
9740 * On other platforms CURPOS always requires the
9741 * CURBASE write to arm the update. Additonally
9742 * a write to any of the cursor register will cancel
9743 * an already armed cursor update. Thus leaving out
9744 * the CURBASE write after CURPOS could lead to a
9745 * cursor that doesn't appear to move, or even change
9746 * shape. Thus we always write CURBASE.
9748 * CURCNTR and CUR_FBC_CTL are always
9749 * armed by the CURBASE write only.
9751 if (plane->cursor.base != base ||
9752 plane->cursor.size != fbc_ctl ||
9753 plane->cursor.cntl != cntl) {
9754 I915_WRITE_FW(CURCNTR(pipe), cntl);
9755 if (HAS_CUR_FBC(dev_priv))
9756 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9757 I915_WRITE_FW(CURPOS(pipe), pos);
9758 I915_WRITE_FW(CURBASE(pipe), base);
9760 plane->cursor.base = base;
9761 plane->cursor.size = fbc_ctl;
9762 plane->cursor.cntl = cntl;
9764 I915_WRITE_FW(CURPOS(pipe), pos);
9765 I915_WRITE_FW(CURBASE(pipe), base);
9768 POSTING_READ_FW(CURBASE(pipe));
9770 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9773 static void i9xx_disable_cursor(struct intel_plane *plane,
9774 struct intel_crtc *crtc)
9776 i9xx_update_cursor(plane, NULL, NULL);
9779 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
9781 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9782 enum intel_display_power_domain power_domain;
9783 enum pipe pipe = plane->pipe;
9787 * Not 100% correct for planes that can move between pipes,
9788 * but that's only the case for gen2-3 which don't have any
9789 * display power wells.
9791 power_domain = POWER_DOMAIN_PIPE(pipe);
9792 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9795 ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
9797 intel_display_power_put(dev_priv, power_domain);
9802 /* VESA 640x480x72Hz mode to set on the pipe */
9803 static const struct drm_display_mode load_detect_mode = {
9804 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9805 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9808 struct drm_framebuffer *
9809 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9810 struct drm_mode_fb_cmd2 *mode_cmd)
9812 struct intel_framebuffer *intel_fb;
9815 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9817 return ERR_PTR(-ENOMEM);
9819 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9823 return &intel_fb->base;
9827 return ERR_PTR(ret);
9830 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
9831 struct drm_crtc *crtc)
9833 struct drm_plane *plane;
9834 struct drm_plane_state *plane_state;
9837 ret = drm_atomic_add_affected_planes(state, crtc);
9841 for_each_new_plane_in_state(state, plane, plane_state, i) {
9842 if (plane_state->crtc != crtc)
9845 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
9849 drm_atomic_set_fb_for_plane(plane_state, NULL);
9855 int intel_get_load_detect_pipe(struct drm_connector *connector,
9856 const struct drm_display_mode *mode,
9857 struct intel_load_detect_pipe *old,
9858 struct drm_modeset_acquire_ctx *ctx)
9860 struct intel_crtc *intel_crtc;
9861 struct intel_encoder *intel_encoder =
9862 intel_attached_encoder(connector);
9863 struct drm_crtc *possible_crtc;
9864 struct drm_encoder *encoder = &intel_encoder->base;
9865 struct drm_crtc *crtc = NULL;
9866 struct drm_device *dev = encoder->dev;
9867 struct drm_i915_private *dev_priv = to_i915(dev);
9868 struct drm_mode_config *config = &dev->mode_config;
9869 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9870 struct drm_connector_state *connector_state;
9871 struct intel_crtc_state *crtc_state;
9874 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9875 connector->base.id, connector->name,
9876 encoder->base.id, encoder->name);
9878 old->restore_state = NULL;
9880 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9883 * Algorithm gets a little messy:
9885 * - if the connector already has an assigned crtc, use it (but make
9886 * sure it's on first)
9888 * - try to find the first unused crtc that can drive this connector,
9889 * and use that if we find one
9892 /* See if we already have a CRTC for this connector */
9893 if (connector->state->crtc) {
9894 crtc = connector->state->crtc;
9896 ret = drm_modeset_lock(&crtc->mutex, ctx);
9900 /* Make sure the crtc and connector are running */
9904 /* Find an unused one (if possible) */
9905 for_each_crtc(dev, possible_crtc) {
9907 if (!(encoder->possible_crtcs & (1 << i)))
9910 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9914 if (possible_crtc->state->enable) {
9915 drm_modeset_unlock(&possible_crtc->mutex);
9919 crtc = possible_crtc;
9924 * If we didn't find an unused CRTC, don't use any.
9927 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9933 intel_crtc = to_intel_crtc(crtc);
9935 state = drm_atomic_state_alloc(dev);
9936 restore_state = drm_atomic_state_alloc(dev);
9937 if (!state || !restore_state) {
9942 state->acquire_ctx = ctx;
9943 restore_state->acquire_ctx = ctx;
9945 connector_state = drm_atomic_get_connector_state(state, connector);
9946 if (IS_ERR(connector_state)) {
9947 ret = PTR_ERR(connector_state);
9951 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9955 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9956 if (IS_ERR(crtc_state)) {
9957 ret = PTR_ERR(crtc_state);
9961 crtc_state->base.active = crtc_state->base.enable = true;
9964 mode = &load_detect_mode;
9966 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9970 ret = intel_modeset_disable_planes(state, crtc);
9974 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9976 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9978 ret = drm_atomic_add_affected_planes(restore_state, crtc);
9980 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9984 ret = drm_atomic_commit(state);
9986 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9990 old->restore_state = restore_state;
9991 drm_atomic_state_put(state);
9993 /* let the connector get through one full cycle before testing */
9994 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9999 drm_atomic_state_put(state);
10002 if (restore_state) {
10003 drm_atomic_state_put(restore_state);
10004 restore_state = NULL;
10007 if (ret == -EDEADLK)
10013 void intel_release_load_detect_pipe(struct drm_connector *connector,
10014 struct intel_load_detect_pipe *old,
10015 struct drm_modeset_acquire_ctx *ctx)
10017 struct intel_encoder *intel_encoder =
10018 intel_attached_encoder(connector);
10019 struct drm_encoder *encoder = &intel_encoder->base;
10020 struct drm_atomic_state *state = old->restore_state;
10023 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10024 connector->base.id, connector->name,
10025 encoder->base.id, encoder->name);
10030 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10032 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10033 drm_atomic_state_put(state);
10036 static int i9xx_pll_refclk(struct drm_device *dev,
10037 const struct intel_crtc_state *pipe_config)
10039 struct drm_i915_private *dev_priv = to_i915(dev);
10040 u32 dpll = pipe_config->dpll_hw_state.dpll;
10042 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10043 return dev_priv->vbt.lvds_ssc_freq;
10044 else if (HAS_PCH_SPLIT(dev_priv))
10046 else if (!IS_GEN2(dev_priv))
10052 /* Returns the clock of the currently programmed mode of the given pipe. */
10053 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10054 struct intel_crtc_state *pipe_config)
10056 struct drm_device *dev = crtc->base.dev;
10057 struct drm_i915_private *dev_priv = to_i915(dev);
10058 int pipe = pipe_config->cpu_transcoder;
10059 u32 dpll = pipe_config->dpll_hw_state.dpll;
10063 int refclk = i9xx_pll_refclk(dev, pipe_config);
10065 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10066 fp = pipe_config->dpll_hw_state.fp0;
10068 fp = pipe_config->dpll_hw_state.fp1;
10070 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10071 if (IS_PINEVIEW(dev_priv)) {
10072 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10073 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10075 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10076 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10079 if (!IS_GEN2(dev_priv)) {
10080 if (IS_PINEVIEW(dev_priv))
10081 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10082 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10084 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10085 DPLL_FPA01_P1_POST_DIV_SHIFT);
10087 switch (dpll & DPLL_MODE_MASK) {
10088 case DPLLB_MODE_DAC_SERIAL:
10089 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10092 case DPLLB_MODE_LVDS:
10093 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10097 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10098 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10102 if (IS_PINEVIEW(dev_priv))
10103 port_clock = pnv_calc_dpll_params(refclk, &clock);
10105 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10107 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10108 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10111 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10112 DPLL_FPA01_P1_POST_DIV_SHIFT);
10114 if (lvds & LVDS_CLKB_POWER_UP)
10119 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10122 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10123 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10125 if (dpll & PLL_P2_DIVIDE_BY_4)
10131 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10135 * This value includes pixel_multiplier. We will use
10136 * port_clock to compute adjusted_mode.crtc_clock in the
10137 * encoder's get_config() function.
10139 pipe_config->port_clock = port_clock;
10142 int intel_dotclock_calculate(int link_freq,
10143 const struct intel_link_m_n *m_n)
10146 * The calculation for the data clock is:
10147 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10148 * But we want to avoid losing precison if possible, so:
10149 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10151 * and the link clock is simpler:
10152 * link_clock = (m * link_clock) / n
10158 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10161 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10162 struct intel_crtc_state *pipe_config)
10164 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10166 /* read out port_clock from the DPLL */
10167 i9xx_crtc_clock_get(crtc, pipe_config);
10170 * In case there is an active pipe without active ports,
10171 * we may need some idea for the dotclock anyway.
10172 * Calculate one based on the FDI configuration.
10174 pipe_config->base.adjusted_mode.crtc_clock =
10175 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10176 &pipe_config->fdi_m_n);
10179 /* Returns the currently programmed mode of the given encoder. */
10180 struct drm_display_mode *
10181 intel_encoder_current_mode(struct intel_encoder *encoder)
10183 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10184 struct intel_crtc_state *crtc_state;
10185 struct drm_display_mode *mode;
10186 struct intel_crtc *crtc;
10189 if (!encoder->get_hw_state(encoder, &pipe))
10192 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10194 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10198 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10204 crtc_state->base.crtc = &crtc->base;
10206 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10212 encoder->get_config(encoder, crtc_state);
10214 intel_mode_from_pipe_config(mode, crtc_state);
10221 static void intel_crtc_destroy(struct drm_crtc *crtc)
10223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10225 drm_crtc_cleanup(crtc);
10230 * intel_wm_need_update - Check whether watermarks need updating
10231 * @plane: drm plane
10232 * @state: new plane state
10234 * Check current plane state versus the new one to determine whether
10235 * watermarks need to be recalculated.
10237 * Returns true or false.
10239 static bool intel_wm_need_update(struct drm_plane *plane,
10240 struct drm_plane_state *state)
10242 struct intel_plane_state *new = to_intel_plane_state(state);
10243 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10245 /* Update watermarks on tiling or size changes. */
10246 if (new->base.visible != cur->base.visible)
10249 if (!cur->base.fb || !new->base.fb)
10252 if (cur->base.fb->modifier != new->base.fb->modifier ||
10253 cur->base.rotation != new->base.rotation ||
10254 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10255 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10256 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10257 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10263 static bool needs_scaling(const struct intel_plane_state *state)
10265 int src_w = drm_rect_width(&state->base.src) >> 16;
10266 int src_h = drm_rect_height(&state->base.src) >> 16;
10267 int dst_w = drm_rect_width(&state->base.dst);
10268 int dst_h = drm_rect_height(&state->base.dst);
10270 return (src_w != dst_w || src_h != dst_h);
10273 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10274 struct drm_crtc_state *crtc_state,
10275 const struct intel_plane_state *old_plane_state,
10276 struct drm_plane_state *plane_state)
10278 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10279 struct drm_crtc *crtc = crtc_state->crtc;
10280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10281 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10282 struct drm_device *dev = crtc->dev;
10283 struct drm_i915_private *dev_priv = to_i915(dev);
10284 bool mode_changed = needs_modeset(crtc_state);
10285 bool was_crtc_enabled = old_crtc_state->base.active;
10286 bool is_crtc_enabled = crtc_state->active;
10287 bool turn_off, turn_on, visible, was_visible;
10288 struct drm_framebuffer *fb = plane_state->fb;
10291 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10292 ret = skl_update_scaler_plane(
10293 to_intel_crtc_state(crtc_state),
10294 to_intel_plane_state(plane_state));
10299 was_visible = old_plane_state->base.visible;
10300 visible = plane_state->visible;
10302 if (!was_crtc_enabled && WARN_ON(was_visible))
10303 was_visible = false;
10306 * Visibility is calculated as if the crtc was on, but
10307 * after scaler setup everything depends on it being off
10308 * when the crtc isn't active.
10310 * FIXME this is wrong for watermarks. Watermarks should also
10311 * be computed as if the pipe would be active. Perhaps move
10312 * per-plane wm computation to the .check_plane() hook, and
10313 * only combine the results from all planes in the current place?
10315 if (!is_crtc_enabled) {
10316 plane_state->visible = visible = false;
10317 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10320 if (!was_visible && !visible)
10323 if (fb != old_plane_state->base.fb)
10324 pipe_config->fb_changed = true;
10326 turn_off = was_visible && (!visible || mode_changed);
10327 turn_on = visible && (!was_visible || mode_changed);
10329 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10330 intel_crtc->base.base.id, intel_crtc->base.name,
10331 plane->base.base.id, plane->base.name,
10332 fb ? fb->base.id : -1);
10334 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10335 plane->base.base.id, plane->base.name,
10336 was_visible, visible,
10337 turn_off, turn_on, mode_changed);
10340 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10341 pipe_config->update_wm_pre = true;
10343 /* must disable cxsr around plane enable/disable */
10344 if (plane->id != PLANE_CURSOR)
10345 pipe_config->disable_cxsr = true;
10346 } else if (turn_off) {
10347 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10348 pipe_config->update_wm_post = true;
10350 /* must disable cxsr around plane enable/disable */
10351 if (plane->id != PLANE_CURSOR)
10352 pipe_config->disable_cxsr = true;
10353 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10354 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10355 /* FIXME bollocks */
10356 pipe_config->update_wm_pre = true;
10357 pipe_config->update_wm_post = true;
10361 if (visible || was_visible)
10362 pipe_config->fb_bits |= plane->frontbuffer_bit;
10365 * WaCxSRDisabledForSpriteScaling:ivb
10367 * cstate->update_wm was already set above, so this flag will
10368 * take effect when we commit and program watermarks.
10370 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10371 needs_scaling(to_intel_plane_state(plane_state)) &&
10372 !needs_scaling(old_plane_state))
10373 pipe_config->disable_lp_wm = true;
10378 static bool encoders_cloneable(const struct intel_encoder *a,
10379 const struct intel_encoder *b)
10381 /* masks could be asymmetric, so check both ways */
10382 return a == b || (a->cloneable & (1 << b->type) &&
10383 b->cloneable & (1 << a->type));
10386 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10387 struct intel_crtc *crtc,
10388 struct intel_encoder *encoder)
10390 struct intel_encoder *source_encoder;
10391 struct drm_connector *connector;
10392 struct drm_connector_state *connector_state;
10395 for_each_new_connector_in_state(state, connector, connector_state, i) {
10396 if (connector_state->crtc != &crtc->base)
10400 to_intel_encoder(connector_state->best_encoder);
10401 if (!encoders_cloneable(encoder, source_encoder))
10408 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10409 struct drm_crtc_state *crtc_state)
10411 struct drm_device *dev = crtc->dev;
10412 struct drm_i915_private *dev_priv = to_i915(dev);
10413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10414 struct intel_crtc_state *pipe_config =
10415 to_intel_crtc_state(crtc_state);
10416 struct drm_atomic_state *state = crtc_state->state;
10418 bool mode_changed = needs_modeset(crtc_state);
10420 if (mode_changed && !crtc_state->active)
10421 pipe_config->update_wm_post = true;
10423 if (mode_changed && crtc_state->enable &&
10424 dev_priv->display.crtc_compute_clock &&
10425 !WARN_ON(pipe_config->shared_dpll)) {
10426 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10432 if (crtc_state->color_mgmt_changed) {
10433 ret = intel_color_check(crtc, crtc_state);
10438 * Changing color management on Intel hardware is
10439 * handled as part of planes update.
10441 crtc_state->planes_changed = true;
10445 if (dev_priv->display.compute_pipe_wm) {
10446 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10448 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10453 if (dev_priv->display.compute_intermediate_wm &&
10454 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10455 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10459 * Calculate 'intermediate' watermarks that satisfy both the
10460 * old state and the new state. We can program these
10463 ret = dev_priv->display.compute_intermediate_wm(dev,
10467 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10470 } else if (dev_priv->display.compute_intermediate_wm) {
10471 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10472 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10475 if (INTEL_GEN(dev_priv) >= 9) {
10477 ret = skl_update_scaler_crtc(pipe_config);
10480 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10483 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10487 if (HAS_IPS(dev_priv))
10488 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10493 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10494 .atomic_begin = intel_begin_crtc_commit,
10495 .atomic_flush = intel_finish_crtc_commit,
10496 .atomic_check = intel_crtc_atomic_check,
10499 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10501 struct intel_connector *connector;
10502 struct drm_connector_list_iter conn_iter;
10504 drm_connector_list_iter_begin(dev, &conn_iter);
10505 for_each_intel_connector_iter(connector, &conn_iter) {
10506 if (connector->base.state->crtc)
10507 drm_connector_unreference(&connector->base);
10509 if (connector->base.encoder) {
10510 connector->base.state->best_encoder =
10511 connector->base.encoder;
10512 connector->base.state->crtc =
10513 connector->base.encoder->crtc;
10515 drm_connector_reference(&connector->base);
10517 connector->base.state->best_encoder = NULL;
10518 connector->base.state->crtc = NULL;
10521 drm_connector_list_iter_end(&conn_iter);
10525 connected_sink_compute_bpp(struct intel_connector *connector,
10526 struct intel_crtc_state *pipe_config)
10528 const struct drm_display_info *info = &connector->base.display_info;
10529 int bpp = pipe_config->pipe_bpp;
10531 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10532 connector->base.base.id,
10533 connector->base.name);
10535 /* Don't use an invalid EDID bpc value */
10536 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10537 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10538 bpp, info->bpc * 3);
10539 pipe_config->pipe_bpp = info->bpc * 3;
10542 /* Clamp bpp to 8 on screens without EDID 1.4 */
10543 if (info->bpc == 0 && bpp > 24) {
10544 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10546 pipe_config->pipe_bpp = 24;
10551 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10552 struct intel_crtc_state *pipe_config)
10554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10555 struct drm_atomic_state *state;
10556 struct drm_connector *connector;
10557 struct drm_connector_state *connector_state;
10560 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10561 IS_CHERRYVIEW(dev_priv)))
10563 else if (INTEL_GEN(dev_priv) >= 5)
10569 pipe_config->pipe_bpp = bpp;
10571 state = pipe_config->base.state;
10573 /* Clamp display bpp to EDID value */
10574 for_each_new_connector_in_state(state, connector, connector_state, i) {
10575 if (connector_state->crtc != &crtc->base)
10578 connected_sink_compute_bpp(to_intel_connector(connector),
10585 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10587 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10588 "type: 0x%x flags: 0x%x\n",
10590 mode->crtc_hdisplay, mode->crtc_hsync_start,
10591 mode->crtc_hsync_end, mode->crtc_htotal,
10592 mode->crtc_vdisplay, mode->crtc_vsync_start,
10593 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10597 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10598 unsigned int lane_count, struct intel_link_m_n *m_n)
10600 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10602 m_n->gmch_m, m_n->gmch_n,
10603 m_n->link_m, m_n->link_n, m_n->tu);
10606 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10608 static const char * const output_type_str[] = {
10609 OUTPUT_TYPE(UNUSED),
10610 OUTPUT_TYPE(ANALOG),
10614 OUTPUT_TYPE(TVOUT),
10620 OUTPUT_TYPE(DP_MST),
10625 static void snprintf_output_types(char *buf, size_t len,
10626 unsigned int output_types)
10633 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10636 if ((output_types & BIT(i)) == 0)
10639 r = snprintf(str, len, "%s%s",
10640 str != buf ? "," : "", output_type_str[i]);
10646 output_types &= ~BIT(i);
10649 WARN_ON_ONCE(output_types != 0);
10652 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10653 struct intel_crtc_state *pipe_config,
10654 const char *context)
10656 struct drm_device *dev = crtc->base.dev;
10657 struct drm_i915_private *dev_priv = to_i915(dev);
10658 struct drm_plane *plane;
10659 struct intel_plane *intel_plane;
10660 struct intel_plane_state *state;
10661 struct drm_framebuffer *fb;
10664 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10665 crtc->base.base.id, crtc->base.name, context);
10667 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10668 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10669 buf, pipe_config->output_types);
10671 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10672 transcoder_name(pipe_config->cpu_transcoder),
10673 pipe_config->pipe_bpp, pipe_config->dither);
10675 if (pipe_config->has_pch_encoder)
10676 intel_dump_m_n_config(pipe_config, "fdi",
10677 pipe_config->fdi_lanes,
10678 &pipe_config->fdi_m_n);
10680 if (pipe_config->ycbcr420)
10681 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10683 if (intel_crtc_has_dp_encoder(pipe_config)) {
10684 intel_dump_m_n_config(pipe_config, "dp m_n",
10685 pipe_config->lane_count, &pipe_config->dp_m_n);
10686 if (pipe_config->has_drrs)
10687 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10688 pipe_config->lane_count,
10689 &pipe_config->dp_m2_n2);
10692 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10693 pipe_config->has_audio, pipe_config->has_infoframe);
10695 DRM_DEBUG_KMS("requested mode:\n");
10696 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10697 DRM_DEBUG_KMS("adjusted mode:\n");
10698 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10699 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10700 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10701 pipe_config->port_clock,
10702 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10703 pipe_config->pixel_rate);
10705 if (INTEL_GEN(dev_priv) >= 9)
10706 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10708 pipe_config->scaler_state.scaler_users,
10709 pipe_config->scaler_state.scaler_id);
10711 if (HAS_GMCH_DISPLAY(dev_priv))
10712 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10713 pipe_config->gmch_pfit.control,
10714 pipe_config->gmch_pfit.pgm_ratios,
10715 pipe_config->gmch_pfit.lvds_border_bits);
10717 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10718 pipe_config->pch_pfit.pos,
10719 pipe_config->pch_pfit.size,
10720 enableddisabled(pipe_config->pch_pfit.enabled));
10722 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10723 pipe_config->ips_enabled, pipe_config->double_wide);
10725 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10727 DRM_DEBUG_KMS("planes on this crtc\n");
10728 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10729 struct drm_format_name_buf format_name;
10730 intel_plane = to_intel_plane(plane);
10731 if (intel_plane->pipe != crtc->pipe)
10734 state = to_intel_plane_state(plane->state);
10735 fb = state->base.fb;
10737 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10738 plane->base.id, plane->name, state->scaler_id);
10742 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10743 plane->base.id, plane->name,
10744 fb->base.id, fb->width, fb->height,
10745 drm_get_format_name(fb->format->format, &format_name));
10746 if (INTEL_GEN(dev_priv) >= 9)
10747 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10749 state->base.src.x1 >> 16,
10750 state->base.src.y1 >> 16,
10751 drm_rect_width(&state->base.src) >> 16,
10752 drm_rect_height(&state->base.src) >> 16,
10753 state->base.dst.x1, state->base.dst.y1,
10754 drm_rect_width(&state->base.dst),
10755 drm_rect_height(&state->base.dst));
10759 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10761 struct drm_device *dev = state->dev;
10762 struct drm_connector *connector;
10763 struct drm_connector_list_iter conn_iter;
10764 unsigned int used_ports = 0;
10765 unsigned int used_mst_ports = 0;
10769 * Walk the connector list instead of the encoder
10770 * list to detect the problem on ddi platforms
10771 * where there's just one encoder per digital port.
10773 drm_connector_list_iter_begin(dev, &conn_iter);
10774 drm_for_each_connector_iter(connector, &conn_iter) {
10775 struct drm_connector_state *connector_state;
10776 struct intel_encoder *encoder;
10778 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10779 if (!connector_state)
10780 connector_state = connector->state;
10782 if (!connector_state->best_encoder)
10785 encoder = to_intel_encoder(connector_state->best_encoder);
10787 WARN_ON(!connector_state->crtc);
10789 switch (encoder->type) {
10790 unsigned int port_mask;
10791 case INTEL_OUTPUT_DDI:
10792 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10794 case INTEL_OUTPUT_DP:
10795 case INTEL_OUTPUT_HDMI:
10796 case INTEL_OUTPUT_EDP:
10797 port_mask = 1 << encoder->port;
10799 /* the same port mustn't appear more than once */
10800 if (used_ports & port_mask)
10803 used_ports |= port_mask;
10805 case INTEL_OUTPUT_DP_MST:
10807 1 << encoder->port;
10813 drm_connector_list_iter_end(&conn_iter);
10815 /* can't mix MST and SST/HDMI on the same port */
10816 if (used_ports & used_mst_ports)
10823 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10825 struct drm_i915_private *dev_priv =
10826 to_i915(crtc_state->base.crtc->dev);
10827 struct intel_crtc_scaler_state scaler_state;
10828 struct intel_dpll_hw_state dpll_hw_state;
10829 struct intel_shared_dpll *shared_dpll;
10830 struct intel_crtc_wm_state wm_state;
10831 bool force_thru, ips_force_disable;
10833 /* FIXME: before the switch to atomic started, a new pipe_config was
10834 * kzalloc'd. Code that depends on any field being zero should be
10835 * fixed, so that the crtc_state can be safely duplicated. For now,
10836 * only fields that are know to not cause problems are preserved. */
10838 scaler_state = crtc_state->scaler_state;
10839 shared_dpll = crtc_state->shared_dpll;
10840 dpll_hw_state = crtc_state->dpll_hw_state;
10841 force_thru = crtc_state->pch_pfit.force_thru;
10842 ips_force_disable = crtc_state->ips_force_disable;
10843 if (IS_G4X(dev_priv) ||
10844 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10845 wm_state = crtc_state->wm;
10847 /* Keep base drm_crtc_state intact, only clear our extended struct */
10848 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10849 memset(&crtc_state->base + 1, 0,
10850 sizeof(*crtc_state) - sizeof(crtc_state->base));
10852 crtc_state->scaler_state = scaler_state;
10853 crtc_state->shared_dpll = shared_dpll;
10854 crtc_state->dpll_hw_state = dpll_hw_state;
10855 crtc_state->pch_pfit.force_thru = force_thru;
10856 crtc_state->ips_force_disable = ips_force_disable;
10857 if (IS_G4X(dev_priv) ||
10858 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10859 crtc_state->wm = wm_state;
10863 intel_modeset_pipe_config(struct drm_crtc *crtc,
10864 struct intel_crtc_state *pipe_config)
10866 struct drm_atomic_state *state = pipe_config->base.state;
10867 struct intel_encoder *encoder;
10868 struct drm_connector *connector;
10869 struct drm_connector_state *connector_state;
10870 int base_bpp, ret = -EINVAL;
10874 clear_intel_crtc_state(pipe_config);
10876 pipe_config->cpu_transcoder =
10877 (enum transcoder) to_intel_crtc(crtc)->pipe;
10880 * Sanitize sync polarity flags based on requested ones. If neither
10881 * positive or negative polarity is requested, treat this as meaning
10882 * negative polarity.
10884 if (!(pipe_config->base.adjusted_mode.flags &
10885 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10886 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10888 if (!(pipe_config->base.adjusted_mode.flags &
10889 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10890 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10892 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10898 * Determine the real pipe dimensions. Note that stereo modes can
10899 * increase the actual pipe size due to the frame doubling and
10900 * insertion of additional space for blanks between the frame. This
10901 * is stored in the crtc timings. We use the requested mode to do this
10902 * computation to clearly distinguish it from the adjusted mode, which
10903 * can be changed by the connectors in the below retry loop.
10905 drm_mode_get_hv_timing(&pipe_config->base.mode,
10906 &pipe_config->pipe_src_w,
10907 &pipe_config->pipe_src_h);
10909 for_each_new_connector_in_state(state, connector, connector_state, i) {
10910 if (connector_state->crtc != crtc)
10913 encoder = to_intel_encoder(connector_state->best_encoder);
10915 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10916 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10921 * Determine output_types before calling the .compute_config()
10922 * hooks so that the hooks can use this information safely.
10924 if (encoder->compute_output_type)
10925 pipe_config->output_types |=
10926 BIT(encoder->compute_output_type(encoder, pipe_config,
10929 pipe_config->output_types |= BIT(encoder->type);
10933 /* Ensure the port clock defaults are reset when retrying. */
10934 pipe_config->port_clock = 0;
10935 pipe_config->pixel_multiplier = 1;
10937 /* Fill in default crtc timings, allow encoders to overwrite them. */
10938 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10939 CRTC_STEREO_DOUBLE);
10941 /* Pass our mode to the connectors and the CRTC to give them a chance to
10942 * adjust it according to limitations or connector properties, and also
10943 * a chance to reject the mode entirely.
10945 for_each_new_connector_in_state(state, connector, connector_state, i) {
10946 if (connector_state->crtc != crtc)
10949 encoder = to_intel_encoder(connector_state->best_encoder);
10951 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10952 DRM_DEBUG_KMS("Encoder config failure\n");
10957 /* Set default port clock if not overwritten by the encoder. Needs to be
10958 * done afterwards in case the encoder adjusts the mode. */
10959 if (!pipe_config->port_clock)
10960 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10961 * pipe_config->pixel_multiplier;
10963 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10965 DRM_DEBUG_KMS("CRTC fixup failed\n");
10969 if (ret == RETRY) {
10970 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10975 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10977 goto encoder_retry;
10980 /* Dithering seems to not pass-through bits correctly when it should, so
10981 * only enable it on 6bpc panels and when its not a compliance
10982 * test requesting 6bpc video pattern.
10984 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10985 !pipe_config->dither_force_disable;
10986 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10987 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10993 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10997 if (clock1 == clock2)
11000 if (!clock1 || !clock2)
11003 diff = abs(clock1 - clock2);
11005 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11012 intel_compare_m_n(unsigned int m, unsigned int n,
11013 unsigned int m2, unsigned int n2,
11016 if (m == m2 && n == n2)
11019 if (exact || !m || !n || !m2 || !n2)
11022 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11029 } else if (n < n2) {
11039 return intel_fuzzy_clock_check(m, m2);
11043 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11044 struct intel_link_m_n *m2_n2,
11047 if (m_n->tu == m2_n2->tu &&
11048 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11049 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11050 intel_compare_m_n(m_n->link_m, m_n->link_n,
11051 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11061 static void __printf(3, 4)
11062 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11064 struct va_format vaf;
11067 va_start(args, format);
11072 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11074 drm_err("mismatch in %s %pV", name, &vaf);
11080 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11081 struct intel_crtc_state *current_config,
11082 struct intel_crtc_state *pipe_config,
11086 bool fixup_inherited = adjust &&
11087 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11088 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11090 #define PIPE_CONF_CHECK_X(name) \
11091 if (current_config->name != pipe_config->name) { \
11092 pipe_config_err(adjust, __stringify(name), \
11093 "(expected 0x%08x, found 0x%08x)\n", \
11094 current_config->name, \
11095 pipe_config->name); \
11099 #define PIPE_CONF_CHECK_I(name) \
11100 if (current_config->name != pipe_config->name) { \
11101 pipe_config_err(adjust, __stringify(name), \
11102 "(expected %i, found %i)\n", \
11103 current_config->name, \
11104 pipe_config->name); \
11108 #define PIPE_CONF_CHECK_BOOL(name) \
11109 if (current_config->name != pipe_config->name) { \
11110 pipe_config_err(adjust, __stringify(name), \
11111 "(expected %s, found %s)\n", \
11112 yesno(current_config->name), \
11113 yesno(pipe_config->name)); \
11118 * Checks state where we only read out the enabling, but not the entire
11119 * state itself (like full infoframes or ELD for audio). These states
11120 * require a full modeset on bootup to fix up.
11122 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) \
11123 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11124 PIPE_CONF_CHECK_BOOL(name); \
11126 pipe_config_err(adjust, __stringify(name), \
11127 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11128 yesno(current_config->name), \
11129 yesno(pipe_config->name)); \
11133 #define PIPE_CONF_CHECK_P(name) \
11134 if (current_config->name != pipe_config->name) { \
11135 pipe_config_err(adjust, __stringify(name), \
11136 "(expected %p, found %p)\n", \
11137 current_config->name, \
11138 pipe_config->name); \
11142 #define PIPE_CONF_CHECK_M_N(name) \
11143 if (!intel_compare_link_m_n(¤t_config->name, \
11144 &pipe_config->name,\
11146 pipe_config_err(adjust, __stringify(name), \
11147 "(expected tu %i gmch %i/%i link %i/%i, " \
11148 "found tu %i, gmch %i/%i link %i/%i)\n", \
11149 current_config->name.tu, \
11150 current_config->name.gmch_m, \
11151 current_config->name.gmch_n, \
11152 current_config->name.link_m, \
11153 current_config->name.link_n, \
11154 pipe_config->name.tu, \
11155 pipe_config->name.gmch_m, \
11156 pipe_config->name.gmch_n, \
11157 pipe_config->name.link_m, \
11158 pipe_config->name.link_n); \
11162 /* This is required for BDW+ where there is only one set of registers for
11163 * switching between high and low RR.
11164 * This macro can be used whenever a comparison has to be made between one
11165 * hw state and multiple sw state variables.
11167 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11168 if (!intel_compare_link_m_n(¤t_config->name, \
11169 &pipe_config->name, adjust) && \
11170 !intel_compare_link_m_n(¤t_config->alt_name, \
11171 &pipe_config->name, adjust)) { \
11172 pipe_config_err(adjust, __stringify(name), \
11173 "(expected tu %i gmch %i/%i link %i/%i, " \
11174 "or tu %i gmch %i/%i link %i/%i, " \
11175 "found tu %i, gmch %i/%i link %i/%i)\n", \
11176 current_config->name.tu, \
11177 current_config->name.gmch_m, \
11178 current_config->name.gmch_n, \
11179 current_config->name.link_m, \
11180 current_config->name.link_n, \
11181 current_config->alt_name.tu, \
11182 current_config->alt_name.gmch_m, \
11183 current_config->alt_name.gmch_n, \
11184 current_config->alt_name.link_m, \
11185 current_config->alt_name.link_n, \
11186 pipe_config->name.tu, \
11187 pipe_config->name.gmch_m, \
11188 pipe_config->name.gmch_n, \
11189 pipe_config->name.link_m, \
11190 pipe_config->name.link_n); \
11194 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11195 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11196 pipe_config_err(adjust, __stringify(name), \
11197 "(%x) (expected %i, found %i)\n", \
11199 current_config->name & (mask), \
11200 pipe_config->name & (mask)); \
11204 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11205 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11206 pipe_config_err(adjust, __stringify(name), \
11207 "(expected %i, found %i)\n", \
11208 current_config->name, \
11209 pipe_config->name); \
11213 #define PIPE_CONF_QUIRK(quirk) \
11214 ((current_config->quirks | pipe_config->quirks) & (quirk))
11216 PIPE_CONF_CHECK_I(cpu_transcoder);
11218 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11219 PIPE_CONF_CHECK_I(fdi_lanes);
11220 PIPE_CONF_CHECK_M_N(fdi_m_n);
11222 PIPE_CONF_CHECK_I(lane_count);
11223 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11225 if (INTEL_GEN(dev_priv) < 8) {
11226 PIPE_CONF_CHECK_M_N(dp_m_n);
11228 if (current_config->has_drrs)
11229 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11231 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11233 PIPE_CONF_CHECK_X(output_types);
11235 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11236 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11237 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11238 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11239 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11240 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11242 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11243 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11244 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11245 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11246 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11247 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11249 PIPE_CONF_CHECK_I(pixel_multiplier);
11250 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11251 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11252 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11253 PIPE_CONF_CHECK_BOOL(limited_color_range);
11255 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11256 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11257 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11258 PIPE_CONF_CHECK_BOOL(ycbcr420);
11260 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11262 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11263 DRM_MODE_FLAG_INTERLACE);
11265 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11266 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11267 DRM_MODE_FLAG_PHSYNC);
11268 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11269 DRM_MODE_FLAG_NHSYNC);
11270 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11271 DRM_MODE_FLAG_PVSYNC);
11272 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11273 DRM_MODE_FLAG_NVSYNC);
11276 PIPE_CONF_CHECK_X(gmch_pfit.control);
11277 /* pfit ratios are autocomputed by the hw on gen4+ */
11278 if (INTEL_GEN(dev_priv) < 4)
11279 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11280 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11283 PIPE_CONF_CHECK_I(pipe_src_w);
11284 PIPE_CONF_CHECK_I(pipe_src_h);
11286 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11287 if (current_config->pch_pfit.enabled) {
11288 PIPE_CONF_CHECK_X(pch_pfit.pos);
11289 PIPE_CONF_CHECK_X(pch_pfit.size);
11292 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11293 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11296 PIPE_CONF_CHECK_BOOL(double_wide);
11298 PIPE_CONF_CHECK_P(shared_dpll);
11299 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11300 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11301 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11302 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11303 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11304 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11305 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11306 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11307 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11308 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11309 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11310 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11311 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11312 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11313 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11314 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11315 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11316 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11317 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11318 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11319 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11321 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11322 PIPE_CONF_CHECK_X(dsi_pll.div);
11324 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11325 PIPE_CONF_CHECK_I(pipe_bpp);
11327 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11328 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11330 PIPE_CONF_CHECK_I(min_voltage_level);
11332 #undef PIPE_CONF_CHECK_X
11333 #undef PIPE_CONF_CHECK_I
11334 #undef PIPE_CONF_CHECK_BOOL
11335 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11336 #undef PIPE_CONF_CHECK_P
11337 #undef PIPE_CONF_CHECK_FLAGS
11338 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11339 #undef PIPE_CONF_QUIRK
11344 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11345 const struct intel_crtc_state *pipe_config)
11347 if (pipe_config->has_pch_encoder) {
11348 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11349 &pipe_config->fdi_m_n);
11350 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11353 * FDI already provided one idea for the dotclock.
11354 * Yell if the encoder disagrees.
11356 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11357 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11358 fdi_dotclock, dotclock);
11362 static void verify_wm_state(struct drm_crtc *crtc,
11363 struct drm_crtc_state *new_state)
11365 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11366 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11367 struct skl_pipe_wm hw_wm, *sw_wm;
11368 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11369 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11371 const enum pipe pipe = intel_crtc->pipe;
11372 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11374 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11377 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11378 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11380 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11381 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11384 for_each_universal_plane(dev_priv, pipe, plane) {
11385 hw_plane_wm = &hw_wm.planes[plane];
11386 sw_plane_wm = &sw_wm->planes[plane];
11389 for (level = 0; level <= max_level; level++) {
11390 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11391 &sw_plane_wm->wm[level]))
11394 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11395 pipe_name(pipe), plane + 1, level,
11396 sw_plane_wm->wm[level].plane_en,
11397 sw_plane_wm->wm[level].plane_res_b,
11398 sw_plane_wm->wm[level].plane_res_l,
11399 hw_plane_wm->wm[level].plane_en,
11400 hw_plane_wm->wm[level].plane_res_b,
11401 hw_plane_wm->wm[level].plane_res_l);
11404 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11405 &sw_plane_wm->trans_wm)) {
11406 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11407 pipe_name(pipe), plane + 1,
11408 sw_plane_wm->trans_wm.plane_en,
11409 sw_plane_wm->trans_wm.plane_res_b,
11410 sw_plane_wm->trans_wm.plane_res_l,
11411 hw_plane_wm->trans_wm.plane_en,
11412 hw_plane_wm->trans_wm.plane_res_b,
11413 hw_plane_wm->trans_wm.plane_res_l);
11417 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11418 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11420 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11421 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11422 pipe_name(pipe), plane + 1,
11423 sw_ddb_entry->start, sw_ddb_entry->end,
11424 hw_ddb_entry->start, hw_ddb_entry->end);
11430 * If the cursor plane isn't active, we may not have updated it's ddb
11431 * allocation. In that case since the ddb allocation will be updated
11432 * once the plane becomes visible, we can skip this check
11435 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11436 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11439 for (level = 0; level <= max_level; level++) {
11440 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11441 &sw_plane_wm->wm[level]))
11444 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11445 pipe_name(pipe), level,
11446 sw_plane_wm->wm[level].plane_en,
11447 sw_plane_wm->wm[level].plane_res_b,
11448 sw_plane_wm->wm[level].plane_res_l,
11449 hw_plane_wm->wm[level].plane_en,
11450 hw_plane_wm->wm[level].plane_res_b,
11451 hw_plane_wm->wm[level].plane_res_l);
11454 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11455 &sw_plane_wm->trans_wm)) {
11456 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11458 sw_plane_wm->trans_wm.plane_en,
11459 sw_plane_wm->trans_wm.plane_res_b,
11460 sw_plane_wm->trans_wm.plane_res_l,
11461 hw_plane_wm->trans_wm.plane_en,
11462 hw_plane_wm->trans_wm.plane_res_b,
11463 hw_plane_wm->trans_wm.plane_res_l);
11467 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11468 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11470 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11471 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11473 sw_ddb_entry->start, sw_ddb_entry->end,
11474 hw_ddb_entry->start, hw_ddb_entry->end);
11480 verify_connector_state(struct drm_device *dev,
11481 struct drm_atomic_state *state,
11482 struct drm_crtc *crtc)
11484 struct drm_connector *connector;
11485 struct drm_connector_state *new_conn_state;
11488 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11489 struct drm_encoder *encoder = connector->encoder;
11490 struct drm_crtc_state *crtc_state = NULL;
11492 if (new_conn_state->crtc != crtc)
11496 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11498 intel_connector_verify_state(crtc_state, new_conn_state);
11500 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11501 "connector's atomic encoder doesn't match legacy encoder\n");
11506 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11508 struct intel_encoder *encoder;
11509 struct drm_connector *connector;
11510 struct drm_connector_state *old_conn_state, *new_conn_state;
11513 for_each_intel_encoder(dev, encoder) {
11514 bool enabled = false, found = false;
11517 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11518 encoder->base.base.id,
11519 encoder->base.name);
11521 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11522 new_conn_state, i) {
11523 if (old_conn_state->best_encoder == &encoder->base)
11526 if (new_conn_state->best_encoder != &encoder->base)
11528 found = enabled = true;
11530 I915_STATE_WARN(new_conn_state->crtc !=
11531 encoder->base.crtc,
11532 "connector's crtc doesn't match encoder crtc\n");
11538 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11539 "encoder's enabled state mismatch "
11540 "(expected %i, found %i)\n",
11541 !!encoder->base.crtc, enabled);
11543 if (!encoder->base.crtc) {
11546 active = encoder->get_hw_state(encoder, &pipe);
11547 I915_STATE_WARN(active,
11548 "encoder detached but still enabled on pipe %c.\n",
11555 verify_crtc_state(struct drm_crtc *crtc,
11556 struct drm_crtc_state *old_crtc_state,
11557 struct drm_crtc_state *new_crtc_state)
11559 struct drm_device *dev = crtc->dev;
11560 struct drm_i915_private *dev_priv = to_i915(dev);
11561 struct intel_encoder *encoder;
11562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11563 struct intel_crtc_state *pipe_config, *sw_config;
11564 struct drm_atomic_state *old_state;
11567 old_state = old_crtc_state->state;
11568 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11569 pipe_config = to_intel_crtc_state(old_crtc_state);
11570 memset(pipe_config, 0, sizeof(*pipe_config));
11571 pipe_config->base.crtc = crtc;
11572 pipe_config->base.state = old_state;
11574 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11576 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11578 /* we keep both pipes enabled on 830 */
11579 if (IS_I830(dev_priv))
11580 active = new_crtc_state->active;
11582 I915_STATE_WARN(new_crtc_state->active != active,
11583 "crtc active state doesn't match with hw state "
11584 "(expected %i, found %i)\n", new_crtc_state->active, active);
11586 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11587 "transitional active state does not match atomic hw state "
11588 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11590 for_each_encoder_on_crtc(dev, crtc, encoder) {
11593 active = encoder->get_hw_state(encoder, &pipe);
11594 I915_STATE_WARN(active != new_crtc_state->active,
11595 "[ENCODER:%i] active %i with crtc active %i\n",
11596 encoder->base.base.id, active, new_crtc_state->active);
11598 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11599 "Encoder connected to wrong pipe %c\n",
11603 encoder->get_config(encoder, pipe_config);
11606 intel_crtc_compute_pixel_rate(pipe_config);
11608 if (!new_crtc_state->active)
11611 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11613 sw_config = to_intel_crtc_state(new_crtc_state);
11614 if (!intel_pipe_config_compare(dev_priv, sw_config,
11615 pipe_config, false)) {
11616 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11617 intel_dump_pipe_config(intel_crtc, pipe_config,
11619 intel_dump_pipe_config(intel_crtc, sw_config,
11625 intel_verify_planes(struct intel_atomic_state *state)
11627 struct intel_plane *plane;
11628 const struct intel_plane_state *plane_state;
11631 for_each_new_intel_plane_in_state(state, plane,
11633 assert_plane(plane, plane_state->base.visible);
11637 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11638 struct intel_shared_dpll *pll,
11639 struct drm_crtc *crtc,
11640 struct drm_crtc_state *new_state)
11642 struct intel_dpll_hw_state dpll_hw_state;
11643 unsigned crtc_mask;
11646 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11648 DRM_DEBUG_KMS("%s\n", pll->name);
11650 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11652 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11653 I915_STATE_WARN(!pll->on && pll->active_mask,
11654 "pll in active use but not on in sw tracking\n");
11655 I915_STATE_WARN(pll->on && !pll->active_mask,
11656 "pll is on but not used by any active crtc\n");
11657 I915_STATE_WARN(pll->on != active,
11658 "pll on state mismatch (expected %i, found %i)\n",
11663 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11664 "more active pll users than references: %x vs %x\n",
11665 pll->active_mask, pll->state.crtc_mask);
11670 crtc_mask = 1 << drm_crtc_index(crtc);
11672 if (new_state->active)
11673 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11674 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11675 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11677 I915_STATE_WARN(pll->active_mask & crtc_mask,
11678 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11679 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11681 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11682 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11683 crtc_mask, pll->state.crtc_mask);
11685 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11687 sizeof(dpll_hw_state)),
11688 "pll hw state mismatch\n");
11692 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11693 struct drm_crtc_state *old_crtc_state,
11694 struct drm_crtc_state *new_crtc_state)
11696 struct drm_i915_private *dev_priv = to_i915(dev);
11697 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11698 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11700 if (new_state->shared_dpll)
11701 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11703 if (old_state->shared_dpll &&
11704 old_state->shared_dpll != new_state->shared_dpll) {
11705 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11706 struct intel_shared_dpll *pll = old_state->shared_dpll;
11708 I915_STATE_WARN(pll->active_mask & crtc_mask,
11709 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11710 pipe_name(drm_crtc_index(crtc)));
11711 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11712 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11713 pipe_name(drm_crtc_index(crtc)));
11718 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11719 struct drm_atomic_state *state,
11720 struct drm_crtc_state *old_state,
11721 struct drm_crtc_state *new_state)
11723 if (!needs_modeset(new_state) &&
11724 !to_intel_crtc_state(new_state)->update_pipe)
11727 verify_wm_state(crtc, new_state);
11728 verify_connector_state(crtc->dev, state, crtc);
11729 verify_crtc_state(crtc, old_state, new_state);
11730 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11734 verify_disabled_dpll_state(struct drm_device *dev)
11736 struct drm_i915_private *dev_priv = to_i915(dev);
11739 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11740 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11744 intel_modeset_verify_disabled(struct drm_device *dev,
11745 struct drm_atomic_state *state)
11747 verify_encoder_state(dev, state);
11748 verify_connector_state(dev, state, NULL);
11749 verify_disabled_dpll_state(dev);
11752 static void update_scanline_offset(struct intel_crtc *crtc)
11754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11757 * The scanline counter increments at the leading edge of hsync.
11759 * On most platforms it starts counting from vtotal-1 on the
11760 * first active line. That means the scanline counter value is
11761 * always one less than what we would expect. Ie. just after
11762 * start of vblank, which also occurs at start of hsync (on the
11763 * last active line), the scanline counter will read vblank_start-1.
11765 * On gen2 the scanline counter starts counting from 1 instead
11766 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11767 * to keep the value positive), instead of adding one.
11769 * On HSW+ the behaviour of the scanline counter depends on the output
11770 * type. For DP ports it behaves like most other platforms, but on HDMI
11771 * there's an extra 1 line difference. So we need to add two instead of
11772 * one to the value.
11774 * On VLV/CHV DSI the scanline counter would appear to increment
11775 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11776 * that means we can't tell whether we're in vblank or not while
11777 * we're on that particular line. We must still set scanline_offset
11778 * to 1 so that the vblank timestamps come out correct when we query
11779 * the scanline counter from within the vblank interrupt handler.
11780 * However if queried just before the start of vblank we'll get an
11781 * answer that's slightly in the future.
11783 if (IS_GEN2(dev_priv)) {
11784 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11787 vtotal = adjusted_mode->crtc_vtotal;
11788 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11791 crtc->scanline_offset = vtotal - 1;
11792 } else if (HAS_DDI(dev_priv) &&
11793 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11794 crtc->scanline_offset = 2;
11796 crtc->scanline_offset = 1;
11799 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11801 struct drm_device *dev = state->dev;
11802 struct drm_i915_private *dev_priv = to_i915(dev);
11803 struct drm_crtc *crtc;
11804 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11807 if (!dev_priv->display.crtc_compute_clock)
11810 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11812 struct intel_shared_dpll *old_dpll =
11813 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11815 if (!needs_modeset(new_crtc_state))
11818 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11823 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11828 * This implements the workaround described in the "notes" section of the mode
11829 * set sequence documentation. When going from no pipes or single pipe to
11830 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11831 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11833 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11835 struct drm_crtc_state *crtc_state;
11836 struct intel_crtc *intel_crtc;
11837 struct drm_crtc *crtc;
11838 struct intel_crtc_state *first_crtc_state = NULL;
11839 struct intel_crtc_state *other_crtc_state = NULL;
11840 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11843 /* look at all crtc's that are going to be enabled in during modeset */
11844 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11845 intel_crtc = to_intel_crtc(crtc);
11847 if (!crtc_state->active || !needs_modeset(crtc_state))
11850 if (first_crtc_state) {
11851 other_crtc_state = to_intel_crtc_state(crtc_state);
11854 first_crtc_state = to_intel_crtc_state(crtc_state);
11855 first_pipe = intel_crtc->pipe;
11859 /* No workaround needed? */
11860 if (!first_crtc_state)
11863 /* w/a possibly needed, check how many crtc's are already enabled. */
11864 for_each_intel_crtc(state->dev, intel_crtc) {
11865 struct intel_crtc_state *pipe_config;
11867 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11868 if (IS_ERR(pipe_config))
11869 return PTR_ERR(pipe_config);
11871 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11873 if (!pipe_config->base.active ||
11874 needs_modeset(&pipe_config->base))
11877 /* 2 or more enabled crtcs means no need for w/a */
11878 if (enabled_pipe != INVALID_PIPE)
11881 enabled_pipe = intel_crtc->pipe;
11884 if (enabled_pipe != INVALID_PIPE)
11885 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11886 else if (other_crtc_state)
11887 other_crtc_state->hsw_workaround_pipe = first_pipe;
11892 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11894 struct drm_crtc *crtc;
11896 /* Add all pipes to the state */
11897 for_each_crtc(state->dev, crtc) {
11898 struct drm_crtc_state *crtc_state;
11900 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11901 if (IS_ERR(crtc_state))
11902 return PTR_ERR(crtc_state);
11908 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11910 struct drm_crtc *crtc;
11913 * Add all pipes to the state, and force
11914 * a modeset on all the active ones.
11916 for_each_crtc(state->dev, crtc) {
11917 struct drm_crtc_state *crtc_state;
11920 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11921 if (IS_ERR(crtc_state))
11922 return PTR_ERR(crtc_state);
11924 if (!crtc_state->active || needs_modeset(crtc_state))
11927 crtc_state->mode_changed = true;
11929 ret = drm_atomic_add_affected_connectors(state, crtc);
11933 ret = drm_atomic_add_affected_planes(state, crtc);
11941 static int intel_modeset_checks(struct drm_atomic_state *state)
11943 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11944 struct drm_i915_private *dev_priv = to_i915(state->dev);
11945 struct drm_crtc *crtc;
11946 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11949 if (!check_digital_port_conflicts(state)) {
11950 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11954 intel_state->modeset = true;
11955 intel_state->active_crtcs = dev_priv->active_crtcs;
11956 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11957 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11959 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11960 if (new_crtc_state->active)
11961 intel_state->active_crtcs |= 1 << i;
11963 intel_state->active_crtcs &= ~(1 << i);
11965 if (old_crtc_state->active != new_crtc_state->active)
11966 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11970 * See if the config requires any additional preparation, e.g.
11971 * to adjust global state with pipes off. We need to do this
11972 * here so we can get the modeset_pipe updated config for the new
11973 * mode set on this crtc. For other crtcs we need to use the
11974 * adjusted_mode bits in the crtc directly.
11976 if (dev_priv->display.modeset_calc_cdclk) {
11977 ret = dev_priv->display.modeset_calc_cdclk(state);
11982 * Writes to dev_priv->cdclk.logical must protected by
11983 * holding all the crtc locks, even if we don't end up
11984 * touching the hardware
11986 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
11987 &intel_state->cdclk.logical)) {
11988 ret = intel_lock_all_pipes(state);
11993 /* All pipes must be switched off while we change the cdclk. */
11994 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
11995 &intel_state->cdclk.actual)) {
11996 ret = intel_modeset_all_pipes(state);
12001 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12002 intel_state->cdclk.logical.cdclk,
12003 intel_state->cdclk.actual.cdclk);
12004 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12005 intel_state->cdclk.logical.voltage_level,
12006 intel_state->cdclk.actual.voltage_level);
12008 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12011 intel_modeset_clear_plls(state);
12013 if (IS_HASWELL(dev_priv))
12014 return haswell_mode_set_planes_workaround(state);
12020 * Handle calculation of various watermark data at the end of the atomic check
12021 * phase. The code here should be run after the per-crtc and per-plane 'check'
12022 * handlers to ensure that all derived state has been updated.
12024 static int calc_watermark_data(struct drm_atomic_state *state)
12026 struct drm_device *dev = state->dev;
12027 struct drm_i915_private *dev_priv = to_i915(dev);
12029 /* Is there platform-specific watermark information to calculate? */
12030 if (dev_priv->display.compute_global_watermarks)
12031 return dev_priv->display.compute_global_watermarks(state);
12037 * intel_atomic_check - validate state object
12039 * @state: state to validate
12041 static int intel_atomic_check(struct drm_device *dev,
12042 struct drm_atomic_state *state)
12044 struct drm_i915_private *dev_priv = to_i915(dev);
12045 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12046 struct drm_crtc *crtc;
12047 struct drm_crtc_state *old_crtc_state, *crtc_state;
12049 bool any_ms = false;
12051 /* Catch I915_MODE_FLAG_INHERITED */
12052 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12054 if (crtc_state->mode.private_flags !=
12055 old_crtc_state->mode.private_flags)
12056 crtc_state->mode_changed = true;
12059 ret = drm_atomic_helper_check_modeset(dev, state);
12063 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12064 struct intel_crtc_state *pipe_config =
12065 to_intel_crtc_state(crtc_state);
12067 if (!needs_modeset(crtc_state))
12070 if (!crtc_state->enable) {
12075 ret = intel_modeset_pipe_config(crtc, pipe_config);
12077 intel_dump_pipe_config(to_intel_crtc(crtc),
12078 pipe_config, "[failed]");
12082 if (i915_modparams.fastboot &&
12083 intel_pipe_config_compare(dev_priv,
12084 to_intel_crtc_state(old_crtc_state),
12085 pipe_config, true)) {
12086 crtc_state->mode_changed = false;
12087 pipe_config->update_pipe = true;
12090 if (needs_modeset(crtc_state))
12093 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12094 needs_modeset(crtc_state) ?
12095 "[modeset]" : "[fastset]");
12099 ret = intel_modeset_checks(state);
12104 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12107 ret = drm_atomic_helper_check_planes(dev, state);
12111 intel_fbc_choose_crtc(dev_priv, intel_state);
12112 return calc_watermark_data(state);
12115 static int intel_atomic_prepare_commit(struct drm_device *dev,
12116 struct drm_atomic_state *state)
12118 return drm_atomic_helper_prepare_planes(dev, state);
12121 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12123 struct drm_device *dev = crtc->base.dev;
12125 if (!dev->max_vblank_count)
12126 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12128 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12131 static void intel_update_crtc(struct drm_crtc *crtc,
12132 struct drm_atomic_state *state,
12133 struct drm_crtc_state *old_crtc_state,
12134 struct drm_crtc_state *new_crtc_state)
12136 struct drm_device *dev = crtc->dev;
12137 struct drm_i915_private *dev_priv = to_i915(dev);
12138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12139 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12140 bool modeset = needs_modeset(new_crtc_state);
12143 update_scanline_offset(intel_crtc);
12144 dev_priv->display.crtc_enable(pipe_config, state);
12146 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12150 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12152 intel_crtc, pipe_config,
12153 to_intel_plane_state(crtc->primary->state));
12156 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12159 static void intel_update_crtcs(struct drm_atomic_state *state)
12161 struct drm_crtc *crtc;
12162 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12165 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12166 if (!new_crtc_state->active)
12169 intel_update_crtc(crtc, state, old_crtc_state,
12174 static void skl_update_crtcs(struct drm_atomic_state *state)
12176 struct drm_i915_private *dev_priv = to_i915(state->dev);
12177 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12178 struct drm_crtc *crtc;
12179 struct intel_crtc *intel_crtc;
12180 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12181 struct intel_crtc_state *cstate;
12182 unsigned int updated = 0;
12187 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12189 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12190 /* ignore allocations for crtc's that have been turned off. */
12191 if (new_crtc_state->active)
12192 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12195 * Whenever the number of active pipes changes, we need to make sure we
12196 * update the pipes in the right order so that their ddb allocations
12197 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12198 * cause pipe underruns and other bad stuff.
12203 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12204 bool vbl_wait = false;
12205 unsigned int cmask = drm_crtc_mask(crtc);
12207 intel_crtc = to_intel_crtc(crtc);
12208 cstate = to_intel_crtc_state(new_crtc_state);
12209 pipe = intel_crtc->pipe;
12211 if (updated & cmask || !cstate->base.active)
12214 if (skl_ddb_allocation_overlaps(dev_priv,
12216 &cstate->wm.skl.ddb,
12221 entries[i] = &cstate->wm.skl.ddb;
12224 * If this is an already active pipe, it's DDB changed,
12225 * and this isn't the last pipe that needs updating
12226 * then we need to wait for a vblank to pass for the
12227 * new ddb allocation to take effect.
12229 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12230 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12231 !new_crtc_state->active_changed &&
12232 intel_state->wm_results.dirty_pipes != updated)
12235 intel_update_crtc(crtc, state, old_crtc_state,
12239 intel_wait_for_vblank(dev_priv, pipe);
12243 } while (progress);
12246 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12248 struct intel_atomic_state *state, *next;
12249 struct llist_node *freed;
12251 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12252 llist_for_each_entry_safe(state, next, freed, freed)
12253 drm_atomic_state_put(&state->base);
12256 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12258 struct drm_i915_private *dev_priv =
12259 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12261 intel_atomic_helper_free_state(dev_priv);
12264 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12266 struct wait_queue_entry wait_fence, wait_reset;
12267 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12269 init_wait_entry(&wait_fence, 0);
12270 init_wait_entry(&wait_reset, 0);
12272 prepare_to_wait(&intel_state->commit_ready.wait,
12273 &wait_fence, TASK_UNINTERRUPTIBLE);
12274 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12275 &wait_reset, TASK_UNINTERRUPTIBLE);
12278 if (i915_sw_fence_done(&intel_state->commit_ready)
12279 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12284 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12285 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12288 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12290 struct drm_device *dev = state->dev;
12291 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12292 struct drm_i915_private *dev_priv = to_i915(dev);
12293 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12294 struct drm_crtc *crtc;
12295 struct intel_crtc_state *intel_cstate;
12296 u64 put_domains[I915_MAX_PIPES] = {};
12299 intel_atomic_commit_fence_wait(intel_state);
12301 drm_atomic_helper_wait_for_dependencies(state);
12303 if (intel_state->modeset)
12304 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12306 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12309 if (needs_modeset(new_crtc_state) ||
12310 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12312 put_domains[to_intel_crtc(crtc)->pipe] =
12313 modeset_get_crtc_power_domains(crtc,
12314 to_intel_crtc_state(new_crtc_state));
12317 if (!needs_modeset(new_crtc_state))
12320 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12321 to_intel_crtc_state(new_crtc_state));
12323 if (old_crtc_state->active) {
12324 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12325 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12326 intel_crtc->active = false;
12327 intel_fbc_disable(intel_crtc);
12328 intel_disable_shared_dpll(intel_crtc);
12331 * Underruns don't always raise
12332 * interrupts, so check manually.
12334 intel_check_cpu_fifo_underruns(dev_priv);
12335 intel_check_pch_fifo_underruns(dev_priv);
12337 if (!new_crtc_state->active) {
12339 * Make sure we don't call initial_watermarks
12340 * for ILK-style watermark updates.
12342 * No clue what this is supposed to achieve.
12344 if (INTEL_GEN(dev_priv) >= 9)
12345 dev_priv->display.initial_watermarks(intel_state,
12346 to_intel_crtc_state(new_crtc_state));
12351 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12352 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12353 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12355 if (intel_state->modeset) {
12356 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12358 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12361 * SKL workaround: bspec recommends we disable the SAGV when we
12362 * have more then one pipe enabled
12364 if (!intel_can_enable_sagv(state))
12365 intel_disable_sagv(dev_priv);
12367 intel_modeset_verify_disabled(dev, state);
12370 /* Complete the events for pipes that have now been disabled */
12371 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12372 bool modeset = needs_modeset(new_crtc_state);
12374 /* Complete events for now disable pipes here. */
12375 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12376 spin_lock_irq(&dev->event_lock);
12377 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12378 spin_unlock_irq(&dev->event_lock);
12380 new_crtc_state->event = NULL;
12384 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12385 dev_priv->display.update_crtcs(state);
12387 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12388 * already, but still need the state for the delayed optimization. To
12390 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12391 * - schedule that vblank worker _before_ calling hw_done
12392 * - at the start of commit_tail, cancel it _synchrously
12393 * - switch over to the vblank wait helper in the core after that since
12394 * we don't need out special handling any more.
12396 drm_atomic_helper_wait_for_flip_done(dev, state);
12399 * Now that the vblank has passed, we can go ahead and program the
12400 * optimal watermarks on platforms that need two-step watermark
12403 * TODO: Move this (and other cleanup) to an async worker eventually.
12405 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12406 intel_cstate = to_intel_crtc_state(new_crtc_state);
12408 if (dev_priv->display.optimize_watermarks)
12409 dev_priv->display.optimize_watermarks(intel_state,
12413 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12414 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12416 if (put_domains[i])
12417 modeset_put_power_domains(dev_priv, put_domains[i]);
12419 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12422 if (intel_state->modeset)
12423 intel_verify_planes(intel_state);
12425 if (intel_state->modeset && intel_can_enable_sagv(state))
12426 intel_enable_sagv(dev_priv);
12428 drm_atomic_helper_commit_hw_done(state);
12430 if (intel_state->modeset) {
12431 /* As one of the primary mmio accessors, KMS has a high
12432 * likelihood of triggering bugs in unclaimed access. After we
12433 * finish modesetting, see if an error has been flagged, and if
12434 * so enable debugging for the next modeset - and hope we catch
12437 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12438 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12441 drm_atomic_helper_cleanup_planes(dev, state);
12443 drm_atomic_helper_commit_cleanup_done(state);
12445 drm_atomic_state_put(state);
12447 intel_atomic_helper_free_state(dev_priv);
12450 static void intel_atomic_commit_work(struct work_struct *work)
12452 struct drm_atomic_state *state =
12453 container_of(work, struct drm_atomic_state, commit_work);
12455 intel_atomic_commit_tail(state);
12458 static int __i915_sw_fence_call
12459 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12460 enum i915_sw_fence_notify notify)
12462 struct intel_atomic_state *state =
12463 container_of(fence, struct intel_atomic_state, commit_ready);
12466 case FENCE_COMPLETE:
12467 /* we do blocking waits in the worker, nothing to do here */
12471 struct intel_atomic_helper *helper =
12472 &to_i915(state->base.dev)->atomic_helper;
12474 if (llist_add(&state->freed, &helper->free_list))
12475 schedule_work(&helper->free_work);
12480 return NOTIFY_DONE;
12483 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12485 struct drm_plane_state *old_plane_state, *new_plane_state;
12486 struct drm_plane *plane;
12489 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12490 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12491 intel_fb_obj(new_plane_state->fb),
12492 to_intel_plane(plane)->frontbuffer_bit);
12496 * intel_atomic_commit - commit validated state object
12498 * @state: the top-level driver state object
12499 * @nonblock: nonblocking commit
12501 * This function commits a top-level state object that has been validated
12502 * with drm_atomic_helper_check().
12505 * Zero for success or -errno.
12507 static int intel_atomic_commit(struct drm_device *dev,
12508 struct drm_atomic_state *state,
12511 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12512 struct drm_i915_private *dev_priv = to_i915(dev);
12515 drm_atomic_state_get(state);
12516 i915_sw_fence_init(&intel_state->commit_ready,
12517 intel_atomic_commit_ready);
12520 * The intel_legacy_cursor_update() fast path takes care
12521 * of avoiding the vblank waits for simple cursor
12522 * movement and flips. For cursor on/off and size changes,
12523 * we want to perform the vblank waits so that watermark
12524 * updates happen during the correct frames. Gen9+ have
12525 * double buffered watermarks and so shouldn't need this.
12527 * Unset state->legacy_cursor_update before the call to
12528 * drm_atomic_helper_setup_commit() because otherwise
12529 * drm_atomic_helper_wait_for_flip_done() is a noop and
12530 * we get FIFO underruns because we didn't wait
12533 * FIXME doing watermarks and fb cleanup from a vblank worker
12534 * (assuming we had any) would solve these problems.
12536 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12537 struct intel_crtc_state *new_crtc_state;
12538 struct intel_crtc *crtc;
12541 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12542 if (new_crtc_state->wm.need_postvbl_update ||
12543 new_crtc_state->update_wm_post)
12544 state->legacy_cursor_update = false;
12547 ret = intel_atomic_prepare_commit(dev, state);
12549 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12550 i915_sw_fence_commit(&intel_state->commit_ready);
12554 ret = drm_atomic_helper_setup_commit(state, nonblock);
12556 ret = drm_atomic_helper_swap_state(state, true);
12559 i915_sw_fence_commit(&intel_state->commit_ready);
12561 drm_atomic_helper_cleanup_planes(dev, state);
12564 dev_priv->wm.distrust_bios_wm = false;
12565 intel_shared_dpll_swap_state(state);
12566 intel_atomic_track_fbs(state);
12568 if (intel_state->modeset) {
12569 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12570 sizeof(intel_state->min_cdclk));
12571 memcpy(dev_priv->min_voltage_level,
12572 intel_state->min_voltage_level,
12573 sizeof(intel_state->min_voltage_level));
12574 dev_priv->active_crtcs = intel_state->active_crtcs;
12575 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12576 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12579 drm_atomic_state_get(state);
12580 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12582 i915_sw_fence_commit(&intel_state->commit_ready);
12583 if (nonblock && intel_state->modeset) {
12584 queue_work(dev_priv->modeset_wq, &state->commit_work);
12585 } else if (nonblock) {
12586 queue_work(system_unbound_wq, &state->commit_work);
12588 if (intel_state->modeset)
12589 flush_workqueue(dev_priv->modeset_wq);
12590 intel_atomic_commit_tail(state);
12596 static const struct drm_crtc_funcs intel_crtc_funcs = {
12597 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12598 .set_config = drm_atomic_helper_set_config,
12599 .destroy = intel_crtc_destroy,
12600 .page_flip = drm_atomic_helper_page_flip,
12601 .atomic_duplicate_state = intel_crtc_duplicate_state,
12602 .atomic_destroy_state = intel_crtc_destroy_state,
12603 .set_crc_source = intel_crtc_set_crc_source,
12606 struct wait_rps_boost {
12607 struct wait_queue_entry wait;
12609 struct drm_crtc *crtc;
12610 struct i915_request *request;
12613 static int do_rps_boost(struct wait_queue_entry *_wait,
12614 unsigned mode, int sync, void *key)
12616 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12617 struct i915_request *rq = wait->request;
12620 * If we missed the vblank, but the request is already running it
12621 * is reasonable to assume that it will complete before the next
12622 * vblank without our intervention, so leave RPS alone.
12624 if (!i915_request_started(rq))
12625 gen6_rps_boost(rq, NULL);
12626 i915_request_put(rq);
12628 drm_crtc_vblank_put(wait->crtc);
12630 list_del(&wait->wait.entry);
12635 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12636 struct dma_fence *fence)
12638 struct wait_rps_boost *wait;
12640 if (!dma_fence_is_i915(fence))
12643 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12646 if (drm_crtc_vblank_get(crtc))
12649 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12651 drm_crtc_vblank_put(crtc);
12655 wait->request = to_request(dma_fence_get(fence));
12658 wait->wait.func = do_rps_boost;
12659 wait->wait.flags = 0;
12661 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12664 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
12666 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12667 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12668 struct drm_framebuffer *fb = plane_state->base.fb;
12669 struct i915_vma *vma;
12671 if (plane->id == PLANE_CURSOR &&
12672 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12673 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12674 const int align = intel_cursor_alignment(dev_priv);
12676 return i915_gem_object_attach_phys(obj, align);
12679 vma = intel_pin_and_fence_fb_obj(fb,
12680 plane_state->base.rotation,
12681 intel_plane_uses_fence(plane_state),
12682 &plane_state->flags);
12684 return PTR_ERR(vma);
12686 plane_state->vma = vma;
12691 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
12693 struct i915_vma *vma;
12695 vma = fetch_and_zero(&old_plane_state->vma);
12697 intel_unpin_fb_vma(vma, old_plane_state->flags);
12701 * intel_prepare_plane_fb - Prepare fb for usage on plane
12702 * @plane: drm plane to prepare for
12703 * @new_state: the plane state being prepared
12705 * Prepares a framebuffer for usage on a display plane. Generally this
12706 * involves pinning the underlying object and updating the frontbuffer tracking
12707 * bits. Some older platforms need special physical address handling for
12710 * Must be called with struct_mutex held.
12712 * Returns 0 on success, negative error code on failure.
12715 intel_prepare_plane_fb(struct drm_plane *plane,
12716 struct drm_plane_state *new_state)
12718 struct intel_atomic_state *intel_state =
12719 to_intel_atomic_state(new_state->state);
12720 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12721 struct drm_framebuffer *fb = new_state->fb;
12722 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12723 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12727 struct drm_crtc_state *crtc_state =
12728 drm_atomic_get_existing_crtc_state(new_state->state,
12729 plane->state->crtc);
12731 /* Big Hammer, we also need to ensure that any pending
12732 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12733 * current scanout is retired before unpinning the old
12734 * framebuffer. Note that we rely on userspace rendering
12735 * into the buffer attached to the pipe they are waiting
12736 * on. If not, userspace generates a GPU hang with IPEHR
12737 * point to the MI_WAIT_FOR_EVENT.
12739 * This should only fail upon a hung GPU, in which case we
12740 * can safely continue.
12742 if (needs_modeset(crtc_state)) {
12743 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12744 old_obj->resv, NULL,
12752 if (new_state->fence) { /* explicit fencing */
12753 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12755 I915_FENCE_TIMEOUT,
12764 ret = i915_gem_object_pin_pages(obj);
12768 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12770 i915_gem_object_unpin_pages(obj);
12774 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
12776 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12778 mutex_unlock(&dev_priv->drm.struct_mutex);
12779 i915_gem_object_unpin_pages(obj);
12783 if (!new_state->fence) { /* implicit fencing */
12784 struct dma_fence *fence;
12786 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12788 false, I915_FENCE_TIMEOUT,
12793 fence = reservation_object_get_excl_rcu(obj->resv);
12795 add_rps_boost_after_vblank(new_state->crtc, fence);
12796 dma_fence_put(fence);
12799 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12806 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12807 * @plane: drm plane to clean up for
12808 * @old_state: the state from the previous modeset
12810 * Cleans up a framebuffer that has just been removed from a plane.
12812 * Must be called with struct_mutex held.
12815 intel_cleanup_plane_fb(struct drm_plane *plane,
12816 struct drm_plane_state *old_state)
12818 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12820 /* Should only be called after a successful intel_prepare_plane_fb()! */
12821 mutex_lock(&dev_priv->drm.struct_mutex);
12822 intel_plane_unpin_fb(to_intel_plane_state(old_state));
12823 mutex_unlock(&dev_priv->drm.struct_mutex);
12827 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12829 struct drm_i915_private *dev_priv;
12831 int crtc_clock, max_dotclk;
12833 if (!intel_crtc || !crtc_state->base.enable)
12834 return DRM_PLANE_HELPER_NO_SCALING;
12836 dev_priv = to_i915(intel_crtc->base.dev);
12838 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12839 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12841 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
12844 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12845 return DRM_PLANE_HELPER_NO_SCALING;
12848 * skl max scale is lower of:
12849 * close to 3 but not 3, -1 is for that purpose
12853 max_scale = min((1 << 16) * 3 - 1,
12854 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12860 intel_check_primary_plane(struct intel_plane *plane,
12861 struct intel_crtc_state *crtc_state,
12862 struct intel_plane_state *state)
12864 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12865 struct drm_crtc *crtc = state->base.crtc;
12866 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12867 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12868 bool can_position = false;
12871 if (INTEL_GEN(dev_priv) >= 9) {
12872 /* use scaler when colorkey is not required */
12873 if (!state->ckey.flags) {
12875 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12877 can_position = true;
12880 ret = drm_atomic_helper_check_plane_state(&state->base,
12882 min_scale, max_scale,
12883 can_position, true);
12887 if (!state->base.fb)
12890 if (INTEL_GEN(dev_priv) >= 9) {
12891 ret = skl_check_plane_surface(crtc_state, state);
12895 state->ctl = skl_plane_ctl(crtc_state, state);
12897 ret = i9xx_check_plane_surface(state);
12901 state->ctl = i9xx_plane_ctl(crtc_state, state);
12904 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
12905 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
12910 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12911 struct drm_crtc_state *old_crtc_state)
12913 struct drm_device *dev = crtc->dev;
12914 struct drm_i915_private *dev_priv = to_i915(dev);
12915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12916 struct intel_crtc_state *old_intel_cstate =
12917 to_intel_crtc_state(old_crtc_state);
12918 struct intel_atomic_state *old_intel_state =
12919 to_intel_atomic_state(old_crtc_state->state);
12920 struct intel_crtc_state *intel_cstate =
12921 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12922 bool modeset = needs_modeset(&intel_cstate->base);
12925 (intel_cstate->base.color_mgmt_changed ||
12926 intel_cstate->update_pipe)) {
12927 intel_color_set_csc(&intel_cstate->base);
12928 intel_color_load_luts(&intel_cstate->base);
12931 /* Perform vblank evasion around commit operation */
12932 intel_pipe_update_start(intel_cstate);
12937 if (intel_cstate->update_pipe)
12938 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12939 else if (INTEL_GEN(dev_priv) >= 9)
12940 skl_detach_scalers(intel_crtc);
12943 if (dev_priv->display.atomic_update_watermarks)
12944 dev_priv->display.atomic_update_watermarks(old_intel_state,
12948 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12949 struct drm_crtc_state *old_crtc_state)
12951 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12953 struct intel_atomic_state *old_intel_state =
12954 to_intel_atomic_state(old_crtc_state->state);
12955 struct intel_crtc_state *new_crtc_state =
12956 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12958 intel_pipe_update_end(new_crtc_state);
12960 if (new_crtc_state->update_pipe &&
12961 !needs_modeset(&new_crtc_state->base) &&
12962 old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED) {
12963 if (!IS_GEN2(dev_priv))
12964 intel_set_cpu_fifo_underrun_reporting(dev_priv, intel_crtc->pipe, true);
12966 if (new_crtc_state->has_pch_encoder) {
12967 enum pipe pch_transcoder =
12968 intel_crtc_pch_transcoder(intel_crtc);
12970 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
12976 * intel_plane_destroy - destroy a plane
12977 * @plane: plane to destroy
12979 * Common destruction function for all types of planes (primary, cursor,
12982 void intel_plane_destroy(struct drm_plane *plane)
12984 drm_plane_cleanup(plane);
12985 kfree(to_intel_plane(plane));
12988 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12991 case DRM_FORMAT_C8:
12992 case DRM_FORMAT_RGB565:
12993 case DRM_FORMAT_XRGB1555:
12994 case DRM_FORMAT_XRGB8888:
12995 return modifier == DRM_FORMAT_MOD_LINEAR ||
12996 modifier == I915_FORMAT_MOD_X_TILED;
13002 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
13005 case DRM_FORMAT_C8:
13006 case DRM_FORMAT_RGB565:
13007 case DRM_FORMAT_XRGB8888:
13008 case DRM_FORMAT_XBGR8888:
13009 case DRM_FORMAT_XRGB2101010:
13010 case DRM_FORMAT_XBGR2101010:
13011 return modifier == DRM_FORMAT_MOD_LINEAR ||
13012 modifier == I915_FORMAT_MOD_X_TILED;
13018 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13021 case DRM_FORMAT_XRGB8888:
13022 case DRM_FORMAT_XBGR8888:
13023 case DRM_FORMAT_ARGB8888:
13024 case DRM_FORMAT_ABGR8888:
13025 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13026 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13029 case DRM_FORMAT_RGB565:
13030 case DRM_FORMAT_XRGB2101010:
13031 case DRM_FORMAT_XBGR2101010:
13032 case DRM_FORMAT_YUYV:
13033 case DRM_FORMAT_YVYU:
13034 case DRM_FORMAT_UYVY:
13035 case DRM_FORMAT_VYUY:
13036 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13039 case DRM_FORMAT_C8:
13040 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13041 modifier == I915_FORMAT_MOD_X_TILED ||
13042 modifier == I915_FORMAT_MOD_Y_TILED)
13050 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13054 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13056 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13059 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13060 modifier != DRM_FORMAT_MOD_LINEAR)
13063 if (INTEL_GEN(dev_priv) >= 9)
13064 return skl_mod_supported(format, modifier);
13065 else if (INTEL_GEN(dev_priv) >= 4)
13066 return i965_mod_supported(format, modifier);
13068 return i8xx_mod_supported(format, modifier);
13071 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13075 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13078 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13081 static struct drm_plane_funcs intel_plane_funcs = {
13082 .update_plane = drm_atomic_helper_update_plane,
13083 .disable_plane = drm_atomic_helper_disable_plane,
13084 .destroy = intel_plane_destroy,
13085 .atomic_get_property = intel_plane_atomic_get_property,
13086 .atomic_set_property = intel_plane_atomic_set_property,
13087 .atomic_duplicate_state = intel_plane_duplicate_state,
13088 .atomic_destroy_state = intel_plane_destroy_state,
13089 .format_mod_supported = intel_primary_plane_format_mod_supported,
13093 intel_legacy_cursor_update(struct drm_plane *plane,
13094 struct drm_crtc *crtc,
13095 struct drm_framebuffer *fb,
13096 int crtc_x, int crtc_y,
13097 unsigned int crtc_w, unsigned int crtc_h,
13098 uint32_t src_x, uint32_t src_y,
13099 uint32_t src_w, uint32_t src_h,
13100 struct drm_modeset_acquire_ctx *ctx)
13102 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13104 struct drm_plane_state *old_plane_state, *new_plane_state;
13105 struct intel_plane *intel_plane = to_intel_plane(plane);
13106 struct drm_framebuffer *old_fb;
13107 struct drm_crtc_state *crtc_state = crtc->state;
13110 * When crtc is inactive or there is a modeset pending,
13111 * wait for it to complete in the slowpath
13113 if (!crtc_state->active || needs_modeset(crtc_state) ||
13114 to_intel_crtc_state(crtc_state)->update_pipe)
13117 old_plane_state = plane->state;
13119 * Don't do an async update if there is an outstanding commit modifying
13120 * the plane. This prevents our async update's changes from getting
13121 * overridden by a previous synchronous update's state.
13123 if (old_plane_state->commit &&
13124 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13128 * If any parameters change that may affect watermarks,
13129 * take the slowpath. Only changing fb or position should be
13132 if (old_plane_state->crtc != crtc ||
13133 old_plane_state->src_w != src_w ||
13134 old_plane_state->src_h != src_h ||
13135 old_plane_state->crtc_w != crtc_w ||
13136 old_plane_state->crtc_h != crtc_h ||
13137 !old_plane_state->fb != !fb)
13140 new_plane_state = intel_plane_duplicate_state(plane);
13141 if (!new_plane_state)
13144 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13146 new_plane_state->src_x = src_x;
13147 new_plane_state->src_y = src_y;
13148 new_plane_state->src_w = src_w;
13149 new_plane_state->src_h = src_h;
13150 new_plane_state->crtc_x = crtc_x;
13151 new_plane_state->crtc_y = crtc_y;
13152 new_plane_state->crtc_w = crtc_w;
13153 new_plane_state->crtc_h = crtc_h;
13155 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13156 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13157 to_intel_plane_state(plane->state),
13158 to_intel_plane_state(new_plane_state));
13162 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13166 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13170 old_fb = old_plane_state->fb;
13172 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13173 intel_plane->frontbuffer_bit);
13175 /* Swap plane state */
13176 plane->state = new_plane_state;
13178 if (plane->state->visible) {
13179 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13180 intel_plane->update_plane(intel_plane,
13181 to_intel_crtc_state(crtc->state),
13182 to_intel_plane_state(plane->state));
13184 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13185 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13188 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13191 mutex_unlock(&dev_priv->drm.struct_mutex);
13194 intel_plane_destroy_state(plane, new_plane_state);
13196 intel_plane_destroy_state(plane, old_plane_state);
13200 return drm_atomic_helper_update_plane(plane, crtc, fb,
13201 crtc_x, crtc_y, crtc_w, crtc_h,
13202 src_x, src_y, src_w, src_h, ctx);
13205 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13206 .update_plane = intel_legacy_cursor_update,
13207 .disable_plane = drm_atomic_helper_disable_plane,
13208 .destroy = intel_plane_destroy,
13209 .atomic_get_property = intel_plane_atomic_get_property,
13210 .atomic_set_property = intel_plane_atomic_set_property,
13211 .atomic_duplicate_state = intel_plane_duplicate_state,
13212 .atomic_destroy_state = intel_plane_destroy_state,
13213 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13216 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13217 enum i9xx_plane_id i9xx_plane)
13219 if (!HAS_FBC(dev_priv))
13222 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13223 return i9xx_plane == PLANE_A; /* tied to pipe A */
13224 else if (IS_IVYBRIDGE(dev_priv))
13225 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13226 i9xx_plane == PLANE_C;
13227 else if (INTEL_GEN(dev_priv) >= 4)
13228 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13230 return i9xx_plane == PLANE_A;
13233 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13234 enum pipe pipe, enum plane_id plane_id)
13236 if (!HAS_FBC(dev_priv))
13239 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13242 static struct intel_plane *
13243 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13245 struct intel_plane *primary = NULL;
13246 struct intel_plane_state *state = NULL;
13247 const uint32_t *intel_primary_formats;
13248 unsigned int supported_rotations;
13249 unsigned int num_formats;
13250 const uint64_t *modifiers;
13253 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13259 state = intel_create_plane_state(&primary->base);
13265 primary->base.state = &state->base;
13267 primary->can_scale = false;
13268 primary->max_downscale = 1;
13269 if (INTEL_GEN(dev_priv) >= 9) {
13270 primary->can_scale = true;
13271 state->scaler_id = -1;
13273 primary->pipe = pipe;
13275 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13276 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13278 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13279 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13281 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13282 primary->id = PLANE_PRIMARY;
13283 primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13285 if (INTEL_GEN(dev_priv) >= 9)
13286 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13290 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13291 primary->i9xx_plane);
13293 if (primary->has_fbc) {
13294 struct intel_fbc *fbc = &dev_priv->fbc;
13296 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13299 primary->check_plane = intel_check_primary_plane;
13301 if (INTEL_GEN(dev_priv) >= 9) {
13302 intel_primary_formats = skl_primary_formats;
13303 num_formats = ARRAY_SIZE(skl_primary_formats);
13305 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
13306 modifiers = skl_format_modifiers_ccs;
13308 modifiers = skl_format_modifiers_noccs;
13310 primary->update_plane = skl_update_plane;
13311 primary->disable_plane = skl_disable_plane;
13312 primary->get_hw_state = skl_plane_get_hw_state;
13313 } else if (INTEL_GEN(dev_priv) >= 4) {
13314 intel_primary_formats = i965_primary_formats;
13315 num_formats = ARRAY_SIZE(i965_primary_formats);
13316 modifiers = i9xx_format_modifiers;
13318 primary->update_plane = i9xx_update_plane;
13319 primary->disable_plane = i9xx_disable_plane;
13320 primary->get_hw_state = i9xx_plane_get_hw_state;
13322 intel_primary_formats = i8xx_primary_formats;
13323 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13324 modifiers = i9xx_format_modifiers;
13326 primary->update_plane = i9xx_update_plane;
13327 primary->disable_plane = i9xx_disable_plane;
13328 primary->get_hw_state = i9xx_plane_get_hw_state;
13331 if (INTEL_GEN(dev_priv) >= 9)
13332 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13333 0, &intel_plane_funcs,
13334 intel_primary_formats, num_formats,
13336 DRM_PLANE_TYPE_PRIMARY,
13337 "plane 1%c", pipe_name(pipe));
13338 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13339 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13340 0, &intel_plane_funcs,
13341 intel_primary_formats, num_formats,
13343 DRM_PLANE_TYPE_PRIMARY,
13344 "primary %c", pipe_name(pipe));
13346 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13347 0, &intel_plane_funcs,
13348 intel_primary_formats, num_formats,
13350 DRM_PLANE_TYPE_PRIMARY,
13352 plane_name(primary->i9xx_plane));
13356 if (INTEL_GEN(dev_priv) >= 10) {
13357 supported_rotations =
13358 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13359 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13360 DRM_MODE_REFLECT_X;
13361 } else if (INTEL_GEN(dev_priv) >= 9) {
13362 supported_rotations =
13363 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13364 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13365 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13366 supported_rotations =
13367 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13368 DRM_MODE_REFLECT_X;
13369 } else if (INTEL_GEN(dev_priv) >= 4) {
13370 supported_rotations =
13371 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13373 supported_rotations = DRM_MODE_ROTATE_0;
13376 if (INTEL_GEN(dev_priv) >= 4)
13377 drm_plane_create_rotation_property(&primary->base,
13379 supported_rotations);
13381 if (INTEL_GEN(dev_priv) >= 9)
13382 drm_plane_create_color_properties(&primary->base,
13383 BIT(DRM_COLOR_YCBCR_BT601) |
13384 BIT(DRM_COLOR_YCBCR_BT709),
13385 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13386 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13387 DRM_COLOR_YCBCR_BT709,
13388 DRM_COLOR_YCBCR_LIMITED_RANGE);
13390 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13398 return ERR_PTR(ret);
13401 static struct intel_plane *
13402 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13405 struct intel_plane *cursor = NULL;
13406 struct intel_plane_state *state = NULL;
13409 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13415 state = intel_create_plane_state(&cursor->base);
13421 cursor->base.state = &state->base;
13423 cursor->can_scale = false;
13424 cursor->max_downscale = 1;
13425 cursor->pipe = pipe;
13426 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13427 cursor->id = PLANE_CURSOR;
13428 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13430 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13431 cursor->update_plane = i845_update_cursor;
13432 cursor->disable_plane = i845_disable_cursor;
13433 cursor->get_hw_state = i845_cursor_get_hw_state;
13434 cursor->check_plane = i845_check_cursor;
13436 cursor->update_plane = i9xx_update_cursor;
13437 cursor->disable_plane = i9xx_disable_cursor;
13438 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13439 cursor->check_plane = i9xx_check_cursor;
13442 cursor->cursor.base = ~0;
13443 cursor->cursor.cntl = ~0;
13445 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13446 cursor->cursor.size = ~0;
13448 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13449 0, &intel_cursor_plane_funcs,
13450 intel_cursor_formats,
13451 ARRAY_SIZE(intel_cursor_formats),
13452 cursor_format_modifiers,
13453 DRM_PLANE_TYPE_CURSOR,
13454 "cursor %c", pipe_name(pipe));
13458 if (INTEL_GEN(dev_priv) >= 4)
13459 drm_plane_create_rotation_property(&cursor->base,
13461 DRM_MODE_ROTATE_0 |
13462 DRM_MODE_ROTATE_180);
13464 if (INTEL_GEN(dev_priv) >= 9)
13465 state->scaler_id = -1;
13467 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13475 return ERR_PTR(ret);
13478 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13479 struct intel_crtc_state *crtc_state)
13481 struct intel_crtc_scaler_state *scaler_state =
13482 &crtc_state->scaler_state;
13483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13486 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13487 if (!crtc->num_scalers)
13490 for (i = 0; i < crtc->num_scalers; i++) {
13491 struct intel_scaler *scaler = &scaler_state->scalers[i];
13493 scaler->in_use = 0;
13494 scaler->mode = PS_SCALER_MODE_DYN;
13497 scaler_state->scaler_id = -1;
13500 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13502 struct intel_crtc *intel_crtc;
13503 struct intel_crtc_state *crtc_state = NULL;
13504 struct intel_plane *primary = NULL;
13505 struct intel_plane *cursor = NULL;
13508 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13512 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13517 intel_crtc->config = crtc_state;
13518 intel_crtc->base.state = &crtc_state->base;
13519 crtc_state->base.crtc = &intel_crtc->base;
13521 primary = intel_primary_plane_create(dev_priv, pipe);
13522 if (IS_ERR(primary)) {
13523 ret = PTR_ERR(primary);
13526 intel_crtc->plane_ids_mask |= BIT(primary->id);
13528 for_each_sprite(dev_priv, pipe, sprite) {
13529 struct intel_plane *plane;
13531 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13532 if (IS_ERR(plane)) {
13533 ret = PTR_ERR(plane);
13536 intel_crtc->plane_ids_mask |= BIT(plane->id);
13539 cursor = intel_cursor_plane_create(dev_priv, pipe);
13540 if (IS_ERR(cursor)) {
13541 ret = PTR_ERR(cursor);
13544 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13546 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13547 &primary->base, &cursor->base,
13549 "pipe %c", pipe_name(pipe));
13553 intel_crtc->pipe = pipe;
13555 /* initialize shared scalers */
13556 intel_crtc_init_scalers(intel_crtc, crtc_state);
13558 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13559 dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] != NULL);
13560 dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] = intel_crtc;
13561 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13563 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13565 intel_color_init(&intel_crtc->base);
13567 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13573 * drm_mode_config_cleanup() will free up any
13574 * crtcs/planes already initialized.
13582 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13584 struct drm_device *dev = connector->base.dev;
13586 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13588 if (!connector->base.state->crtc)
13589 return INVALID_PIPE;
13591 return to_intel_crtc(connector->base.state->crtc)->pipe;
13594 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
13595 struct drm_file *file)
13597 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13598 struct drm_crtc *drmmode_crtc;
13599 struct intel_crtc *crtc;
13601 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13605 crtc = to_intel_crtc(drmmode_crtc);
13606 pipe_from_crtc_id->pipe = crtc->pipe;
13611 static int intel_encoder_clones(struct intel_encoder *encoder)
13613 struct drm_device *dev = encoder->base.dev;
13614 struct intel_encoder *source_encoder;
13615 int index_mask = 0;
13618 for_each_intel_encoder(dev, source_encoder) {
13619 if (encoders_cloneable(encoder, source_encoder))
13620 index_mask |= (1 << entry);
13628 static bool has_edp_a(struct drm_i915_private *dev_priv)
13630 if (!IS_MOBILE(dev_priv))
13633 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13636 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13642 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13644 if (INTEL_GEN(dev_priv) >= 9)
13647 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13650 if (IS_CHERRYVIEW(dev_priv))
13653 if (HAS_PCH_LPT_H(dev_priv) &&
13654 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13657 /* DDI E can't be used if DDI A requires 4 lanes */
13658 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13661 if (!dev_priv->vbt.int_crt_support)
13667 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13672 if (HAS_DDI(dev_priv))
13675 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13676 * everywhere where registers can be write protected.
13678 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13683 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13684 u32 val = I915_READ(PP_CONTROL(pps_idx));
13686 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13687 I915_WRITE(PP_CONTROL(pps_idx), val);
13691 static void intel_pps_init(struct drm_i915_private *dev_priv)
13693 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13694 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13695 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13696 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13698 dev_priv->pps_mmio_base = PPS_BASE;
13700 intel_pps_unlock_regs_wa(dev_priv);
13703 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13705 struct intel_encoder *encoder;
13706 bool dpd_is_edp = false;
13708 intel_pps_init(dev_priv);
13711 * intel_edp_init_connector() depends on this completing first, to
13712 * prevent the registeration of both eDP and LVDS and the incorrect
13713 * sharing of the PPS.
13715 intel_lvds_init(dev_priv);
13717 if (intel_crt_present(dev_priv))
13718 intel_crt_init(dev_priv);
13720 if (IS_GEN9_LP(dev_priv)) {
13722 * FIXME: Broxton doesn't support port detection via the
13723 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13724 * detect the ports.
13726 intel_ddi_init(dev_priv, PORT_A);
13727 intel_ddi_init(dev_priv, PORT_B);
13728 intel_ddi_init(dev_priv, PORT_C);
13730 intel_dsi_init(dev_priv);
13731 } else if (HAS_DDI(dev_priv)) {
13735 * Haswell uses DDI functions to detect digital outputs.
13736 * On SKL pre-D0 the strap isn't connected, so we assume
13739 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13740 /* WaIgnoreDDIAStrap: skl */
13741 if (found || IS_GEN9_BC(dev_priv))
13742 intel_ddi_init(dev_priv, PORT_A);
13744 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
13746 found = I915_READ(SFUSE_STRAP);
13748 if (found & SFUSE_STRAP_DDIB_DETECTED)
13749 intel_ddi_init(dev_priv, PORT_B);
13750 if (found & SFUSE_STRAP_DDIC_DETECTED)
13751 intel_ddi_init(dev_priv, PORT_C);
13752 if (found & SFUSE_STRAP_DDID_DETECTED)
13753 intel_ddi_init(dev_priv, PORT_D);
13754 if (found & SFUSE_STRAP_DDIF_DETECTED)
13755 intel_ddi_init(dev_priv, PORT_F);
13757 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13759 if (IS_GEN9_BC(dev_priv) &&
13760 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13761 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13762 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13763 intel_ddi_init(dev_priv, PORT_E);
13765 } else if (HAS_PCH_SPLIT(dev_priv)) {
13767 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13769 if (has_edp_a(dev_priv))
13770 intel_dp_init(dev_priv, DP_A, PORT_A);
13772 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13773 /* PCH SDVOB multiplex with HDMIB */
13774 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13776 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13777 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13778 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13781 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13782 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13784 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13785 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13787 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13788 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13790 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13791 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13792 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13793 bool has_edp, has_port;
13796 * The DP_DETECTED bit is the latched state of the DDC
13797 * SDA pin at boot. However since eDP doesn't require DDC
13798 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13799 * eDP ports may have been muxed to an alternate function.
13800 * Thus we can't rely on the DP_DETECTED bit alone to detect
13801 * eDP ports. Consult the VBT as well as DP_DETECTED to
13802 * detect eDP ports.
13804 * Sadly the straps seem to be missing sometimes even for HDMI
13805 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13806 * and VBT for the presence of the port. Additionally we can't
13807 * trust the port type the VBT declares as we've seen at least
13808 * HDMI ports that the VBT claim are DP or eDP.
13810 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13811 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13812 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13813 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13814 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13815 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13817 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13818 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13819 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13820 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13821 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13822 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13824 if (IS_CHERRYVIEW(dev_priv)) {
13826 * eDP not supported on port D,
13827 * so no need to worry about it
13829 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13830 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13831 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13832 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13833 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13836 intel_dsi_init(dev_priv);
13837 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13838 bool found = false;
13840 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13841 DRM_DEBUG_KMS("probing SDVOB\n");
13842 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13843 if (!found && IS_G4X(dev_priv)) {
13844 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13845 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13848 if (!found && IS_G4X(dev_priv))
13849 intel_dp_init(dev_priv, DP_B, PORT_B);
13852 /* Before G4X SDVOC doesn't have its own detect register */
13854 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13855 DRM_DEBUG_KMS("probing SDVOC\n");
13856 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13859 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13861 if (IS_G4X(dev_priv)) {
13862 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13863 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13865 if (IS_G4X(dev_priv))
13866 intel_dp_init(dev_priv, DP_C, PORT_C);
13869 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13870 intel_dp_init(dev_priv, DP_D, PORT_D);
13871 } else if (IS_GEN2(dev_priv))
13872 intel_dvo_init(dev_priv);
13874 if (SUPPORTS_TV(dev_priv))
13875 intel_tv_init(dev_priv);
13877 intel_psr_init(dev_priv);
13879 for_each_intel_encoder(&dev_priv->drm, encoder) {
13880 encoder->base.possible_crtcs = encoder->crtc_mask;
13881 encoder->base.possible_clones =
13882 intel_encoder_clones(encoder);
13885 intel_init_pch_refclk(dev_priv);
13887 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13890 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13892 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13894 drm_framebuffer_cleanup(fb);
13896 i915_gem_object_lock(intel_fb->obj);
13897 WARN_ON(!intel_fb->obj->framebuffer_references--);
13898 i915_gem_object_unlock(intel_fb->obj);
13900 i915_gem_object_put(intel_fb->obj);
13905 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13906 struct drm_file *file,
13907 unsigned int *handle)
13909 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13910 struct drm_i915_gem_object *obj = intel_fb->obj;
13912 if (obj->userptr.mm) {
13913 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13917 return drm_gem_handle_create(file, &obj->base, handle);
13920 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13921 struct drm_file *file,
13922 unsigned flags, unsigned color,
13923 struct drm_clip_rect *clips,
13924 unsigned num_clips)
13926 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13928 i915_gem_object_flush_if_display(obj);
13929 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13934 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13935 .destroy = intel_user_framebuffer_destroy,
13936 .create_handle = intel_user_framebuffer_create_handle,
13937 .dirty = intel_user_framebuffer_dirty,
13941 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13942 uint64_t fb_modifier, uint32_t pixel_format)
13944 u32 gen = INTEL_GEN(dev_priv);
13947 int cpp = drm_format_plane_cpp(pixel_format, 0);
13949 /* "The stride in bytes must not exceed the of the size of 8K
13950 * pixels and 32K bytes."
13952 return min(8192 * cpp, 32768);
13953 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13955 } else if (gen >= 4) {
13956 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13960 } else if (gen >= 3) {
13961 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13966 /* XXX DSPC is limited to 4k tiled */
13971 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13972 struct drm_i915_gem_object *obj,
13973 struct drm_mode_fb_cmd2 *mode_cmd)
13975 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13976 struct drm_framebuffer *fb = &intel_fb->base;
13977 struct drm_format_name_buf format_name;
13979 unsigned int tiling, stride;
13983 i915_gem_object_lock(obj);
13984 obj->framebuffer_references++;
13985 tiling = i915_gem_object_get_tiling(obj);
13986 stride = i915_gem_object_get_stride(obj);
13987 i915_gem_object_unlock(obj);
13989 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13991 * If there's a fence, enforce that
13992 * the fb modifier and tiling mode match.
13994 if (tiling != I915_TILING_NONE &&
13995 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13996 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14000 if (tiling == I915_TILING_X) {
14001 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14002 } else if (tiling == I915_TILING_Y) {
14003 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14008 /* Passed in modifier sanity checking. */
14009 switch (mode_cmd->modifier[0]) {
14010 case I915_FORMAT_MOD_Y_TILED_CCS:
14011 case I915_FORMAT_MOD_Yf_TILED_CCS:
14012 switch (mode_cmd->pixel_format) {
14013 case DRM_FORMAT_XBGR8888:
14014 case DRM_FORMAT_ABGR8888:
14015 case DRM_FORMAT_XRGB8888:
14016 case DRM_FORMAT_ARGB8888:
14019 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14023 case I915_FORMAT_MOD_Y_TILED:
14024 case I915_FORMAT_MOD_Yf_TILED:
14025 if (INTEL_GEN(dev_priv) < 9) {
14026 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14027 mode_cmd->modifier[0]);
14030 case DRM_FORMAT_MOD_LINEAR:
14031 case I915_FORMAT_MOD_X_TILED:
14034 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14035 mode_cmd->modifier[0]);
14040 * gen2/3 display engine uses the fence if present,
14041 * so the tiling mode must match the fb modifier exactly.
14043 if (INTEL_GEN(dev_priv) < 4 &&
14044 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14045 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14049 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14050 mode_cmd->pixel_format);
14051 if (mode_cmd->pitches[0] > pitch_limit) {
14052 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14053 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14054 "tiled" : "linear",
14055 mode_cmd->pitches[0], pitch_limit);
14060 * If there's a fence, enforce that
14061 * the fb pitch and fence stride match.
14063 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14064 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14065 mode_cmd->pitches[0], stride);
14069 /* Reject formats not supported by any plane early. */
14070 switch (mode_cmd->pixel_format) {
14071 case DRM_FORMAT_C8:
14072 case DRM_FORMAT_RGB565:
14073 case DRM_FORMAT_XRGB8888:
14074 case DRM_FORMAT_ARGB8888:
14076 case DRM_FORMAT_XRGB1555:
14077 if (INTEL_GEN(dev_priv) > 3) {
14078 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14079 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14083 case DRM_FORMAT_ABGR8888:
14084 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14085 INTEL_GEN(dev_priv) < 9) {
14086 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14087 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14091 case DRM_FORMAT_XBGR8888:
14092 case DRM_FORMAT_XRGB2101010:
14093 case DRM_FORMAT_XBGR2101010:
14094 if (INTEL_GEN(dev_priv) < 4) {
14095 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14096 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14100 case DRM_FORMAT_ABGR2101010:
14101 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14102 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14103 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14107 case DRM_FORMAT_YUYV:
14108 case DRM_FORMAT_UYVY:
14109 case DRM_FORMAT_YVYU:
14110 case DRM_FORMAT_VYUY:
14111 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14112 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14113 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14118 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14119 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14123 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14124 if (mode_cmd->offsets[0] != 0)
14127 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14129 for (i = 0; i < fb->format->num_planes; i++) {
14130 u32 stride_alignment;
14132 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14133 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14137 stride_alignment = intel_fb_stride_alignment(fb, i);
14140 * Display WA #0531: skl,bxt,kbl,glk
14142 * Render decompression and plane width > 3840
14143 * combined with horizontal panning requires the
14144 * plane stride to be a multiple of 4. We'll just
14145 * require the entire fb to accommodate that to avoid
14146 * potential runtime errors at plane configuration time.
14148 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14149 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14150 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14151 stride_alignment *= 4;
14153 if (fb->pitches[i] & (stride_alignment - 1)) {
14154 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14155 i, fb->pitches[i], stride_alignment);
14160 intel_fb->obj = obj;
14162 ret = intel_fill_fb_info(dev_priv, fb);
14166 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14168 DRM_ERROR("framebuffer init failed %d\n", ret);
14175 i915_gem_object_lock(obj);
14176 obj->framebuffer_references--;
14177 i915_gem_object_unlock(obj);
14181 static struct drm_framebuffer *
14182 intel_user_framebuffer_create(struct drm_device *dev,
14183 struct drm_file *filp,
14184 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14186 struct drm_framebuffer *fb;
14187 struct drm_i915_gem_object *obj;
14188 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14190 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14192 return ERR_PTR(-ENOENT);
14194 fb = intel_framebuffer_create(obj, &mode_cmd);
14196 i915_gem_object_put(obj);
14201 static void intel_atomic_state_free(struct drm_atomic_state *state)
14203 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14205 drm_atomic_state_default_release(state);
14207 i915_sw_fence_fini(&intel_state->commit_ready);
14212 static enum drm_mode_status
14213 intel_mode_valid(struct drm_device *dev,
14214 const struct drm_display_mode *mode)
14216 if (mode->vscan > 1)
14217 return MODE_NO_VSCAN;
14219 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
14220 return MODE_NO_DBLESCAN;
14222 if (mode->flags & DRM_MODE_FLAG_HSKEW)
14223 return MODE_H_ILLEGAL;
14225 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14226 DRM_MODE_FLAG_NCSYNC |
14227 DRM_MODE_FLAG_PCSYNC))
14230 if (mode->flags & (DRM_MODE_FLAG_BCAST |
14231 DRM_MODE_FLAG_PIXMUX |
14232 DRM_MODE_FLAG_CLKDIV2))
14238 static const struct drm_mode_config_funcs intel_mode_funcs = {
14239 .fb_create = intel_user_framebuffer_create,
14240 .get_format_info = intel_get_format_info,
14241 .output_poll_changed = intel_fbdev_output_poll_changed,
14242 .mode_valid = intel_mode_valid,
14243 .atomic_check = intel_atomic_check,
14244 .atomic_commit = intel_atomic_commit,
14245 .atomic_state_alloc = intel_atomic_state_alloc,
14246 .atomic_state_clear = intel_atomic_state_clear,
14247 .atomic_state_free = intel_atomic_state_free,
14251 * intel_init_display_hooks - initialize the display modesetting hooks
14252 * @dev_priv: device private
14254 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14256 intel_init_cdclk_hooks(dev_priv);
14258 if (INTEL_GEN(dev_priv) >= 9) {
14259 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14260 dev_priv->display.get_initial_plane_config =
14261 skylake_get_initial_plane_config;
14262 dev_priv->display.crtc_compute_clock =
14263 haswell_crtc_compute_clock;
14264 dev_priv->display.crtc_enable = haswell_crtc_enable;
14265 dev_priv->display.crtc_disable = haswell_crtc_disable;
14266 } else if (HAS_DDI(dev_priv)) {
14267 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14268 dev_priv->display.get_initial_plane_config =
14269 i9xx_get_initial_plane_config;
14270 dev_priv->display.crtc_compute_clock =
14271 haswell_crtc_compute_clock;
14272 dev_priv->display.crtc_enable = haswell_crtc_enable;
14273 dev_priv->display.crtc_disable = haswell_crtc_disable;
14274 } else if (HAS_PCH_SPLIT(dev_priv)) {
14275 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14276 dev_priv->display.get_initial_plane_config =
14277 i9xx_get_initial_plane_config;
14278 dev_priv->display.crtc_compute_clock =
14279 ironlake_crtc_compute_clock;
14280 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14281 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14282 } else if (IS_CHERRYVIEW(dev_priv)) {
14283 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14284 dev_priv->display.get_initial_plane_config =
14285 i9xx_get_initial_plane_config;
14286 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14287 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14288 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14289 } else if (IS_VALLEYVIEW(dev_priv)) {
14290 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14291 dev_priv->display.get_initial_plane_config =
14292 i9xx_get_initial_plane_config;
14293 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14294 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14295 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14296 } else if (IS_G4X(dev_priv)) {
14297 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14298 dev_priv->display.get_initial_plane_config =
14299 i9xx_get_initial_plane_config;
14300 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14301 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14302 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14303 } else if (IS_PINEVIEW(dev_priv)) {
14304 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14305 dev_priv->display.get_initial_plane_config =
14306 i9xx_get_initial_plane_config;
14307 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14308 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14309 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14310 } else if (!IS_GEN2(dev_priv)) {
14311 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14312 dev_priv->display.get_initial_plane_config =
14313 i9xx_get_initial_plane_config;
14314 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14315 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14316 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14318 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14319 dev_priv->display.get_initial_plane_config =
14320 i9xx_get_initial_plane_config;
14321 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14322 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14323 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14326 if (IS_GEN5(dev_priv)) {
14327 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14328 } else if (IS_GEN6(dev_priv)) {
14329 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14330 } else if (IS_IVYBRIDGE(dev_priv)) {
14331 /* FIXME: detect B0+ stepping and use auto training */
14332 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14333 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14334 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14337 if (INTEL_GEN(dev_priv) >= 9)
14338 dev_priv->display.update_crtcs = skl_update_crtcs;
14340 dev_priv->display.update_crtcs = intel_update_crtcs;
14344 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14346 static void quirk_ssc_force_disable(struct drm_device *dev)
14348 struct drm_i915_private *dev_priv = to_i915(dev);
14349 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14350 DRM_INFO("applying lvds SSC disable quirk\n");
14354 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14357 static void quirk_invert_brightness(struct drm_device *dev)
14359 struct drm_i915_private *dev_priv = to_i915(dev);
14360 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14361 DRM_INFO("applying inverted panel brightness quirk\n");
14364 /* Some VBT's incorrectly indicate no backlight is present */
14365 static void quirk_backlight_present(struct drm_device *dev)
14367 struct drm_i915_private *dev_priv = to_i915(dev);
14368 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14369 DRM_INFO("applying backlight present quirk\n");
14372 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14373 * which is 300 ms greater than eDP spec T12 min.
14375 static void quirk_increase_t12_delay(struct drm_device *dev)
14377 struct drm_i915_private *dev_priv = to_i915(dev);
14379 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14380 DRM_INFO("Applying T12 delay quirk\n");
14383 struct intel_quirk {
14385 int subsystem_vendor;
14386 int subsystem_device;
14387 void (*hook)(struct drm_device *dev);
14390 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14391 struct intel_dmi_quirk {
14392 void (*hook)(struct drm_device *dev);
14393 const struct dmi_system_id (*dmi_id_list)[];
14396 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14398 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14402 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14404 .dmi_id_list = &(const struct dmi_system_id[]) {
14406 .callback = intel_dmi_reverse_brightness,
14407 .ident = "NCR Corporation",
14408 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14409 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14412 { } /* terminating entry */
14414 .hook = quirk_invert_brightness,
14418 static struct intel_quirk intel_quirks[] = {
14419 /* Lenovo U160 cannot use SSC on LVDS */
14420 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14422 /* Sony Vaio Y cannot use SSC on LVDS */
14423 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14425 /* Acer Aspire 5734Z must invert backlight brightness */
14426 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14428 /* Acer/eMachines G725 */
14429 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14431 /* Acer/eMachines e725 */
14432 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14434 /* Acer/Packard Bell NCL20 */
14435 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14437 /* Acer Aspire 4736Z */
14438 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14440 /* Acer Aspire 5336 */
14441 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14443 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14444 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14446 /* Acer C720 Chromebook (Core i3 4005U) */
14447 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14449 /* Apple Macbook 2,1 (Core 2 T7400) */
14450 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14452 /* Apple Macbook 4,1 */
14453 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14455 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14456 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14458 /* HP Chromebook 14 (Celeron 2955U) */
14459 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14461 /* Dell Chromebook 11 */
14462 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14464 /* Dell Chromebook 11 (2015 version) */
14465 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14467 /* Toshiba Satellite P50-C-18C */
14468 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14471 static void intel_init_quirks(struct drm_device *dev)
14473 struct pci_dev *d = dev->pdev;
14476 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14477 struct intel_quirk *q = &intel_quirks[i];
14479 if (d->device == q->device &&
14480 (d->subsystem_vendor == q->subsystem_vendor ||
14481 q->subsystem_vendor == PCI_ANY_ID) &&
14482 (d->subsystem_device == q->subsystem_device ||
14483 q->subsystem_device == PCI_ANY_ID))
14486 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14487 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14488 intel_dmi_quirks[i].hook(dev);
14492 /* Disable the VGA plane that we never use */
14493 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14495 struct pci_dev *pdev = dev_priv->drm.pdev;
14497 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14499 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14500 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14501 outb(SR01, VGA_SR_INDEX);
14502 sr1 = inb(VGA_SR_DATA);
14503 outb(sr1 | 1<<5, VGA_SR_DATA);
14504 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14507 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14508 POSTING_READ(vga_reg);
14511 void intel_modeset_init_hw(struct drm_device *dev)
14513 struct drm_i915_private *dev_priv = to_i915(dev);
14515 intel_update_cdclk(dev_priv);
14516 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14517 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14521 * Calculate what we think the watermarks should be for the state we've read
14522 * out of the hardware and then immediately program those watermarks so that
14523 * we ensure the hardware settings match our internal state.
14525 * We can calculate what we think WM's should be by creating a duplicate of the
14526 * current state (which was constructed during hardware readout) and running it
14527 * through the atomic check code to calculate new watermark values in the
14530 static void sanitize_watermarks(struct drm_device *dev)
14532 struct drm_i915_private *dev_priv = to_i915(dev);
14533 struct drm_atomic_state *state;
14534 struct intel_atomic_state *intel_state;
14535 struct drm_crtc *crtc;
14536 struct drm_crtc_state *cstate;
14537 struct drm_modeset_acquire_ctx ctx;
14541 /* Only supported on platforms that use atomic watermark design */
14542 if (!dev_priv->display.optimize_watermarks)
14546 * We need to hold connection_mutex before calling duplicate_state so
14547 * that the connector loop is protected.
14549 drm_modeset_acquire_init(&ctx, 0);
14551 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14552 if (ret == -EDEADLK) {
14553 drm_modeset_backoff(&ctx);
14555 } else if (WARN_ON(ret)) {
14559 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14560 if (WARN_ON(IS_ERR(state)))
14563 intel_state = to_intel_atomic_state(state);
14566 * Hardware readout is the only time we don't want to calculate
14567 * intermediate watermarks (since we don't trust the current
14570 if (!HAS_GMCH_DISPLAY(dev_priv))
14571 intel_state->skip_intermediate_wm = true;
14573 ret = intel_atomic_check(dev, state);
14576 * If we fail here, it means that the hardware appears to be
14577 * programmed in a way that shouldn't be possible, given our
14578 * understanding of watermark requirements. This might mean a
14579 * mistake in the hardware readout code or a mistake in the
14580 * watermark calculations for a given platform. Raise a WARN
14581 * so that this is noticeable.
14583 * If this actually happens, we'll have to just leave the
14584 * BIOS-programmed watermarks untouched and hope for the best.
14586 WARN(true, "Could not determine valid watermarks for inherited state\n");
14590 /* Write calculated watermark values back */
14591 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14592 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14594 cs->wm.need_postvbl_update = true;
14595 dev_priv->display.optimize_watermarks(intel_state, cs);
14597 to_intel_crtc_state(crtc->state)->wm = cs->wm;
14601 drm_atomic_state_put(state);
14603 drm_modeset_drop_locks(&ctx);
14604 drm_modeset_acquire_fini(&ctx);
14607 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14609 if (IS_GEN5(dev_priv)) {
14611 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14613 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14614 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
14615 dev_priv->fdi_pll_freq = 270000;
14620 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14623 int intel_modeset_init(struct drm_device *dev)
14625 struct drm_i915_private *dev_priv = to_i915(dev);
14626 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14628 struct intel_crtc *crtc;
14630 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
14632 drm_mode_config_init(dev);
14634 dev->mode_config.min_width = 0;
14635 dev->mode_config.min_height = 0;
14637 dev->mode_config.preferred_depth = 24;
14638 dev->mode_config.prefer_shadow = 1;
14640 dev->mode_config.allow_fb_modifiers = true;
14642 dev->mode_config.funcs = &intel_mode_funcs;
14644 init_llist_head(&dev_priv->atomic_helper.free_list);
14645 INIT_WORK(&dev_priv->atomic_helper.free_work,
14646 intel_atomic_helper_free_state_worker);
14648 intel_init_quirks(dev);
14650 intel_init_pm(dev_priv);
14652 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14656 * There may be no VBT; and if the BIOS enabled SSC we can
14657 * just keep using it to avoid unnecessary flicker. Whereas if the
14658 * BIOS isn't using it, don't assume it will work even if the VBT
14659 * indicates as much.
14661 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14662 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14665 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14666 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14667 bios_lvds_use_ssc ? "en" : "dis",
14668 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14669 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14673 if (IS_GEN2(dev_priv)) {
14674 dev->mode_config.max_width = 2048;
14675 dev->mode_config.max_height = 2048;
14676 } else if (IS_GEN3(dev_priv)) {
14677 dev->mode_config.max_width = 4096;
14678 dev->mode_config.max_height = 4096;
14680 dev->mode_config.max_width = 8192;
14681 dev->mode_config.max_height = 8192;
14684 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14685 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14686 dev->mode_config.cursor_height = 1023;
14687 } else if (IS_GEN2(dev_priv)) {
14688 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14689 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14691 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14692 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14695 dev->mode_config.fb_base = ggtt->gmadr.start;
14697 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14698 INTEL_INFO(dev_priv)->num_pipes,
14699 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14701 for_each_pipe(dev_priv, pipe) {
14704 ret = intel_crtc_init(dev_priv, pipe);
14706 drm_mode_config_cleanup(dev);
14711 intel_shared_dpll_init(dev);
14712 intel_update_fdi_pll_freq(dev_priv);
14714 intel_update_czclk(dev_priv);
14715 intel_modeset_init_hw(dev);
14717 if (dev_priv->max_cdclk_freq == 0)
14718 intel_update_max_cdclk(dev_priv);
14720 /* Just disable it once at startup */
14721 i915_disable_vga(dev_priv);
14722 intel_setup_outputs(dev_priv);
14724 drm_modeset_lock_all(dev);
14725 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14726 drm_modeset_unlock_all(dev);
14728 for_each_intel_crtc(dev, crtc) {
14729 struct intel_initial_plane_config plane_config = {};
14735 * Note that reserving the BIOS fb up front prevents us
14736 * from stuffing other stolen allocations like the ring
14737 * on top. This prevents some ugliness at boot time, and
14738 * can even allow for smooth boot transitions if the BIOS
14739 * fb is large enough for the active pipe configuration.
14741 dev_priv->display.get_initial_plane_config(crtc,
14745 * If the fb is shared between multiple heads, we'll
14746 * just get the first one.
14748 intel_find_initial_plane_obj(crtc, &plane_config);
14752 * Make sure hardware watermarks really match the state we read out.
14753 * Note that we need to do this after reconstructing the BIOS fb's
14754 * since the watermark calculation done here will use pstate->fb.
14756 if (!HAS_GMCH_DISPLAY(dev_priv))
14757 sanitize_watermarks(dev);
14762 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14764 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14765 /* 640x480@60Hz, ~25175 kHz */
14766 struct dpll clock = {
14776 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14778 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14779 pipe_name(pipe), clock.vco, clock.dot);
14781 fp = i9xx_dpll_compute_fp(&clock);
14782 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14783 DPLL_VGA_MODE_DIS |
14784 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14785 PLL_P2_DIVIDE_BY_4 |
14786 PLL_REF_INPUT_DREFCLK |
14789 I915_WRITE(FP0(pipe), fp);
14790 I915_WRITE(FP1(pipe), fp);
14792 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14793 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14794 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14795 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14796 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14797 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14798 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14801 * Apparently we need to have VGA mode enabled prior to changing
14802 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14803 * dividers, even though the register value does change.
14805 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14806 I915_WRITE(DPLL(pipe), dpll);
14808 /* Wait for the clocks to stabilize. */
14809 POSTING_READ(DPLL(pipe));
14812 /* The pixel multiplier can only be updated once the
14813 * DPLL is enabled and the clocks are stable.
14815 * So write it again.
14817 I915_WRITE(DPLL(pipe), dpll);
14819 /* We do this three times for luck */
14820 for (i = 0; i < 3 ; i++) {
14821 I915_WRITE(DPLL(pipe), dpll);
14822 POSTING_READ(DPLL(pipe));
14823 udelay(150); /* wait for warmup */
14826 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14827 POSTING_READ(PIPECONF(pipe));
14829 intel_wait_for_pipe_scanline_moving(crtc);
14832 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14834 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14836 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14839 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
14840 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
14841 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
14842 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
14843 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
14845 I915_WRITE(PIPECONF(pipe), 0);
14846 POSTING_READ(PIPECONF(pipe));
14848 intel_wait_for_pipe_scanline_stopped(crtc);
14850 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14851 POSTING_READ(DPLL(pipe));
14854 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
14855 struct intel_plane *plane)
14857 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14858 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
14859 u32 val = I915_READ(DSPCNTR(i9xx_plane));
14861 return (val & DISPLAY_PLANE_ENABLE) == 0 ||
14862 (val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
14866 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
14868 struct intel_crtc *crtc;
14870 if (INTEL_GEN(dev_priv) >= 4)
14873 for_each_intel_crtc(&dev_priv->drm, crtc) {
14874 struct intel_plane *plane =
14875 to_intel_plane(crtc->base.primary);
14877 if (intel_plane_mapping_ok(crtc, plane))
14880 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
14882 intel_plane_disable_noatomic(crtc, plane);
14886 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14888 struct drm_device *dev = crtc->base.dev;
14889 struct intel_encoder *encoder;
14891 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14897 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14899 struct drm_device *dev = encoder->base.dev;
14900 struct intel_connector *connector;
14902 for_each_connector_on_encoder(dev, &encoder->base, connector)
14908 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14909 enum pipe pch_transcoder)
14911 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14912 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14915 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14916 struct drm_modeset_acquire_ctx *ctx)
14918 struct drm_device *dev = crtc->base.dev;
14919 struct drm_i915_private *dev_priv = to_i915(dev);
14920 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14922 /* Clear any frame start delays used for debugging left by the BIOS */
14923 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
14924 i915_reg_t reg = PIPECONF(cpu_transcoder);
14927 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14930 /* restore vblank interrupts to correct state */
14931 drm_crtc_vblank_reset(&crtc->base);
14932 if (crtc->active) {
14933 struct intel_plane *plane;
14935 drm_crtc_vblank_on(&crtc->base);
14937 /* Disable everything but the primary plane */
14938 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14939 const struct intel_plane_state *plane_state =
14940 to_intel_plane_state(plane->base.state);
14942 if (plane_state->base.visible &&
14943 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
14944 intel_plane_disable_noatomic(crtc, plane);
14948 /* Adjust the state of the output pipe according to whether we
14949 * have active connectors/encoders. */
14950 if (crtc->active && !intel_crtc_has_encoders(crtc))
14951 intel_crtc_disable_noatomic(&crtc->base, ctx);
14953 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14955 * We start out with underrun reporting disabled to avoid races.
14956 * For correct bookkeeping mark this on active crtcs.
14958 * Also on gmch platforms we dont have any hardware bits to
14959 * disable the underrun reporting. Which means we need to start
14960 * out with underrun reporting disabled also on inactive pipes,
14961 * since otherwise we'll complain about the garbage we read when
14962 * e.g. coming up after runtime pm.
14964 * No protection against concurrent access is required - at
14965 * worst a fifo underrun happens which also sets this to false.
14967 crtc->cpu_fifo_underrun_disabled = true;
14969 * We track the PCH trancoder underrun reporting state
14970 * within the crtc. With crtc for pipe A housing the underrun
14971 * reporting state for PCH transcoder A, crtc for pipe B housing
14972 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14973 * and marking underrun reporting as disabled for the non-existing
14974 * PCH transcoders B and C would prevent enabling the south
14975 * error interrupt (see cpt_can_enable_serr_int()).
14977 if (has_pch_trancoder(dev_priv, crtc->pipe))
14978 crtc->pch_fifo_underrun_disabled = true;
14982 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14984 struct intel_connector *connector;
14986 /* We need to check both for a crtc link (meaning that the
14987 * encoder is active and trying to read from a pipe) and the
14988 * pipe itself being active. */
14989 bool has_active_crtc = encoder->base.crtc &&
14990 to_intel_crtc(encoder->base.crtc)->active;
14992 connector = intel_encoder_find_connector(encoder);
14993 if (connector && !has_active_crtc) {
14994 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14995 encoder->base.base.id,
14996 encoder->base.name);
14998 /* Connector is active, but has no active pipe. This is
14999 * fallout from our resume register restoring. Disable
15000 * the encoder manually again. */
15001 if (encoder->base.crtc) {
15002 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15004 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15005 encoder->base.base.id,
15006 encoder->base.name);
15007 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15008 if (encoder->post_disable)
15009 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15011 encoder->base.crtc = NULL;
15013 /* Inconsistent output/port/pipe state happens presumably due to
15014 * a bug in one of the get_hw_state functions. Or someplace else
15015 * in our code, like the register restore mess on resume. Clamp
15016 * things to off as a safer default. */
15018 connector->base.dpms = DRM_MODE_DPMS_OFF;
15019 connector->base.encoder = NULL;
15023 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15025 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15027 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15028 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15029 i915_disable_vga(dev_priv);
15033 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15035 /* This function can be called both from intel_modeset_setup_hw_state or
15036 * at a very early point in our resume sequence, where the power well
15037 * structures are not yet restored. Since this function is at a very
15038 * paranoid "someone might have enabled VGA while we were not looking"
15039 * level, just check if the power well is enabled instead of trying to
15040 * follow the "don't touch the power well if we don't need it" policy
15041 * the rest of the driver uses. */
15042 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15045 i915_redisable_vga_power_on(dev_priv);
15047 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15050 /* FIXME read out full plane state for all planes */
15051 static void readout_plane_state(struct intel_crtc *crtc)
15053 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15054 struct intel_crtc_state *crtc_state =
15055 to_intel_crtc_state(crtc->base.state);
15056 struct intel_plane *plane;
15058 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15059 struct intel_plane_state *plane_state =
15060 to_intel_plane_state(plane->base.state);
15061 bool visible = plane->get_hw_state(plane);
15063 intel_set_plane_visible(crtc_state, plane_state, visible);
15067 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15069 struct drm_i915_private *dev_priv = to_i915(dev);
15071 struct intel_crtc *crtc;
15072 struct intel_encoder *encoder;
15073 struct intel_connector *connector;
15074 struct drm_connector_list_iter conn_iter;
15077 dev_priv->active_crtcs = 0;
15079 for_each_intel_crtc(dev, crtc) {
15080 struct intel_crtc_state *crtc_state =
15081 to_intel_crtc_state(crtc->base.state);
15083 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15084 memset(crtc_state, 0, sizeof(*crtc_state));
15085 crtc_state->base.crtc = &crtc->base;
15087 crtc_state->base.active = crtc_state->base.enable =
15088 dev_priv->display.get_pipe_config(crtc, crtc_state);
15090 crtc->base.enabled = crtc_state->base.enable;
15091 crtc->active = crtc_state->base.active;
15093 if (crtc_state->base.active)
15094 dev_priv->active_crtcs |= 1 << crtc->pipe;
15096 readout_plane_state(crtc);
15098 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15099 crtc->base.base.id, crtc->base.name,
15100 enableddisabled(crtc_state->base.active));
15103 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15104 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15106 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15107 &pll->state.hw_state);
15108 pll->state.crtc_mask = 0;
15109 for_each_intel_crtc(dev, crtc) {
15110 struct intel_crtc_state *crtc_state =
15111 to_intel_crtc_state(crtc->base.state);
15113 if (crtc_state->base.active &&
15114 crtc_state->shared_dpll == pll)
15115 pll->state.crtc_mask |= 1 << crtc->pipe;
15117 pll->active_mask = pll->state.crtc_mask;
15119 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15120 pll->name, pll->state.crtc_mask, pll->on);
15123 for_each_intel_encoder(dev, encoder) {
15126 if (encoder->get_hw_state(encoder, &pipe)) {
15127 struct intel_crtc_state *crtc_state;
15129 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15130 crtc_state = to_intel_crtc_state(crtc->base.state);
15132 encoder->base.crtc = &crtc->base;
15133 encoder->get_config(encoder, crtc_state);
15135 encoder->base.crtc = NULL;
15138 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15139 encoder->base.base.id, encoder->base.name,
15140 enableddisabled(encoder->base.crtc),
15144 drm_connector_list_iter_begin(dev, &conn_iter);
15145 for_each_intel_connector_iter(connector, &conn_iter) {
15146 if (connector->get_hw_state(connector)) {
15147 connector->base.dpms = DRM_MODE_DPMS_ON;
15149 encoder = connector->encoder;
15150 connector->base.encoder = &encoder->base;
15152 if (encoder->base.crtc &&
15153 encoder->base.crtc->state->active) {
15155 * This has to be done during hardware readout
15156 * because anything calling .crtc_disable may
15157 * rely on the connector_mask being accurate.
15159 encoder->base.crtc->state->connector_mask |=
15160 1 << drm_connector_index(&connector->base);
15161 encoder->base.crtc->state->encoder_mask |=
15162 1 << drm_encoder_index(&encoder->base);
15166 connector->base.dpms = DRM_MODE_DPMS_OFF;
15167 connector->base.encoder = NULL;
15169 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15170 connector->base.base.id, connector->base.name,
15171 enableddisabled(connector->base.encoder));
15173 drm_connector_list_iter_end(&conn_iter);
15175 for_each_intel_crtc(dev, crtc) {
15176 struct intel_crtc_state *crtc_state =
15177 to_intel_crtc_state(crtc->base.state);
15180 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15181 if (crtc_state->base.active) {
15182 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15183 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15184 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15187 * The initial mode needs to be set in order to keep
15188 * the atomic core happy. It wants a valid mode if the
15189 * crtc's enabled, so we do the above call.
15191 * But we don't set all the derived state fully, hence
15192 * set a flag to indicate that a full recalculation is
15193 * needed on the next commit.
15195 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15197 intel_crtc_compute_pixel_rate(crtc_state);
15199 if (dev_priv->display.modeset_calc_cdclk) {
15200 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15201 if (WARN_ON(min_cdclk < 0))
15205 drm_calc_timestamping_constants(&crtc->base,
15206 &crtc_state->base.adjusted_mode);
15207 update_scanline_offset(crtc);
15210 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15211 dev_priv->min_voltage_level[crtc->pipe] =
15212 crtc_state->min_voltage_level;
15214 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15219 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15221 struct intel_encoder *encoder;
15223 for_each_intel_encoder(&dev_priv->drm, encoder) {
15225 enum intel_display_power_domain domain;
15227 if (!encoder->get_power_domains)
15230 get_domains = encoder->get_power_domains(encoder);
15231 for_each_power_domain(domain, get_domains)
15232 intel_display_power_get(dev_priv, domain);
15236 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15238 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15239 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15240 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15243 if (IS_HASWELL(dev_priv)) {
15245 * WaRsPkgCStateDisplayPMReq:hsw
15246 * System hang if this isn't done before disabling all planes!
15248 I915_WRITE(CHICKEN_PAR1_1,
15249 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15253 /* Scan out the current hw modeset state,
15254 * and sanitizes it to the current state
15257 intel_modeset_setup_hw_state(struct drm_device *dev,
15258 struct drm_modeset_acquire_ctx *ctx)
15260 struct drm_i915_private *dev_priv = to_i915(dev);
15262 struct intel_crtc *crtc;
15263 struct intel_encoder *encoder;
15266 intel_early_display_was(dev_priv);
15267 intel_modeset_readout_hw_state(dev);
15269 /* HW state is read out, now we need to sanitize this mess. */
15270 get_encoder_power_domains(dev_priv);
15272 intel_sanitize_plane_mapping(dev_priv);
15274 for_each_intel_encoder(dev, encoder) {
15275 intel_sanitize_encoder(encoder);
15278 for_each_pipe(dev_priv, pipe) {
15279 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15281 intel_sanitize_crtc(crtc, ctx);
15282 intel_dump_pipe_config(crtc, crtc->config,
15283 "[setup_hw_state]");
15286 intel_modeset_update_connector_atomic_state(dev);
15288 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15289 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15291 if (!pll->on || pll->active_mask)
15294 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15296 pll->funcs.disable(dev_priv, pll);
15300 if (IS_G4X(dev_priv)) {
15301 g4x_wm_get_hw_state(dev);
15302 g4x_wm_sanitize(dev_priv);
15303 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15304 vlv_wm_get_hw_state(dev);
15305 vlv_wm_sanitize(dev_priv);
15306 } else if (INTEL_GEN(dev_priv) >= 9) {
15307 skl_wm_get_hw_state(dev);
15308 } else if (HAS_PCH_SPLIT(dev_priv)) {
15309 ilk_wm_get_hw_state(dev);
15312 for_each_intel_crtc(dev, crtc) {
15315 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15316 if (WARN_ON(put_domains))
15317 modeset_put_power_domains(dev_priv, put_domains);
15319 intel_display_set_init_power(dev_priv, false);
15321 intel_power_domains_verify_state(dev_priv);
15323 intel_fbc_init_pipe_state(dev_priv);
15326 void intel_display_resume(struct drm_device *dev)
15328 struct drm_i915_private *dev_priv = to_i915(dev);
15329 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15330 struct drm_modeset_acquire_ctx ctx;
15333 dev_priv->modeset_restore_state = NULL;
15335 state->acquire_ctx = &ctx;
15337 drm_modeset_acquire_init(&ctx, 0);
15340 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15341 if (ret != -EDEADLK)
15344 drm_modeset_backoff(&ctx);
15348 ret = __intel_display_resume(dev, state, &ctx);
15350 intel_enable_ipc(dev_priv);
15351 drm_modeset_drop_locks(&ctx);
15352 drm_modeset_acquire_fini(&ctx);
15355 DRM_ERROR("Restoring old state failed with %i\n", ret);
15357 drm_atomic_state_put(state);
15360 int intel_connector_register(struct drm_connector *connector)
15362 struct intel_connector *intel_connector = to_intel_connector(connector);
15365 ret = intel_backlight_device_register(intel_connector);
15375 void intel_connector_unregister(struct drm_connector *connector)
15377 struct intel_connector *intel_connector = to_intel_connector(connector);
15379 intel_backlight_device_unregister(intel_connector);
15380 intel_panel_destroy_backlight(connector);
15383 static void intel_hpd_poll_fini(struct drm_device *dev)
15385 struct intel_connector *connector;
15386 struct drm_connector_list_iter conn_iter;
15388 /* Kill all the work that may have been queued by hpd. */
15389 drm_connector_list_iter_begin(dev, &conn_iter);
15390 for_each_intel_connector_iter(connector, &conn_iter) {
15391 if (connector->modeset_retry_work.func)
15392 cancel_work_sync(&connector->modeset_retry_work);
15393 if (connector->hdcp_shim) {
15394 cancel_delayed_work_sync(&connector->hdcp_check_work);
15395 cancel_work_sync(&connector->hdcp_prop_work);
15398 drm_connector_list_iter_end(&conn_iter);
15401 void intel_modeset_cleanup(struct drm_device *dev)
15403 struct drm_i915_private *dev_priv = to_i915(dev);
15405 flush_work(&dev_priv->atomic_helper.free_work);
15406 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15408 intel_disable_gt_powersave(dev_priv);
15411 * Interrupts and polling as the first thing to avoid creating havoc.
15412 * Too much stuff here (turning of connectors, ...) would
15413 * experience fancy races otherwise.
15415 intel_irq_uninstall(dev_priv);
15418 * Due to the hpd irq storm handling the hotplug work can re-arm the
15419 * poll handlers. Hence disable polling after hpd handling is shut down.
15421 intel_hpd_poll_fini(dev);
15423 /* poll work can call into fbdev, hence clean that up afterwards */
15424 intel_fbdev_fini(dev_priv);
15426 intel_unregister_dsm_handler();
15428 intel_fbc_global_disable(dev_priv);
15430 /* flush any delayed tasks or pending work */
15431 flush_scheduled_work();
15433 drm_mode_config_cleanup(dev);
15435 intel_cleanup_overlay(dev_priv);
15437 intel_cleanup_gt_powersave(dev_priv);
15439 intel_teardown_gmbus(dev_priv);
15441 destroy_workqueue(dev_priv->modeset_wq);
15444 void intel_connector_attach_encoder(struct intel_connector *connector,
15445 struct intel_encoder *encoder)
15447 connector->encoder = encoder;
15448 drm_mode_connector_attach_encoder(&connector->base,
15453 * set vga decode state - true == enable VGA decode
15455 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15457 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15460 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15461 DRM_ERROR("failed to read control word\n");
15465 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15469 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15471 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15473 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15474 DRM_ERROR("failed to write control word\n");
15481 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15483 struct intel_display_error_state {
15485 u32 power_well_driver;
15487 int num_transcoders;
15489 struct intel_cursor_error_state {
15494 } cursor[I915_MAX_PIPES];
15496 struct intel_pipe_error_state {
15497 bool power_domain_on;
15500 } pipe[I915_MAX_PIPES];
15502 struct intel_plane_error_state {
15510 } plane[I915_MAX_PIPES];
15512 struct intel_transcoder_error_state {
15513 bool power_domain_on;
15514 enum transcoder cpu_transcoder;
15527 struct intel_display_error_state *
15528 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15530 struct intel_display_error_state *error;
15531 int transcoders[] = {
15539 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15542 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15546 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15547 error->power_well_driver =
15548 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15550 for_each_pipe(dev_priv, i) {
15551 error->pipe[i].power_domain_on =
15552 __intel_display_power_is_enabled(dev_priv,
15553 POWER_DOMAIN_PIPE(i));
15554 if (!error->pipe[i].power_domain_on)
15557 error->cursor[i].control = I915_READ(CURCNTR(i));
15558 error->cursor[i].position = I915_READ(CURPOS(i));
15559 error->cursor[i].base = I915_READ(CURBASE(i));
15561 error->plane[i].control = I915_READ(DSPCNTR(i));
15562 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15563 if (INTEL_GEN(dev_priv) <= 3) {
15564 error->plane[i].size = I915_READ(DSPSIZE(i));
15565 error->plane[i].pos = I915_READ(DSPPOS(i));
15567 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15568 error->plane[i].addr = I915_READ(DSPADDR(i));
15569 if (INTEL_GEN(dev_priv) >= 4) {
15570 error->plane[i].surface = I915_READ(DSPSURF(i));
15571 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15574 error->pipe[i].source = I915_READ(PIPESRC(i));
15576 if (HAS_GMCH_DISPLAY(dev_priv))
15577 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15580 /* Note: this does not include DSI transcoders. */
15581 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15582 if (HAS_DDI(dev_priv))
15583 error->num_transcoders++; /* Account for eDP. */
15585 for (i = 0; i < error->num_transcoders; i++) {
15586 enum transcoder cpu_transcoder = transcoders[i];
15588 error->transcoder[i].power_domain_on =
15589 __intel_display_power_is_enabled(dev_priv,
15590 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15591 if (!error->transcoder[i].power_domain_on)
15594 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15596 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15597 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15598 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15599 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15600 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15601 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15602 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15608 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15611 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15612 struct intel_display_error_state *error)
15614 struct drm_i915_private *dev_priv = m->i915;
15620 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15621 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15622 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15623 error->power_well_driver);
15624 for_each_pipe(dev_priv, i) {
15625 err_printf(m, "Pipe [%d]:\n", i);
15626 err_printf(m, " Power: %s\n",
15627 onoff(error->pipe[i].power_domain_on));
15628 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15629 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15631 err_printf(m, "Plane [%d]:\n", i);
15632 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15633 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15634 if (INTEL_GEN(dev_priv) <= 3) {
15635 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15636 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15638 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15639 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15640 if (INTEL_GEN(dev_priv) >= 4) {
15641 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15642 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15645 err_printf(m, "Cursor [%d]:\n", i);
15646 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15647 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15648 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15651 for (i = 0; i < error->num_transcoders; i++) {
15652 err_printf(m, "CPU transcoder: %s\n",
15653 transcoder_name(error->transcoder[i].cpu_transcoder));
15654 err_printf(m, " Power: %s\n",
15655 onoff(error->transcoder[i].power_domain_on));
15656 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15657 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15658 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15659 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15660 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15661 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15662 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);