2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
65 typedef struct intel_limit intel_limit_t;
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
72 intel_pch_rawclk(struct drm_device *dev)
74 struct drm_i915_private *dev_priv = dev->dev_private;
76 WARN_ON(!HAS_PCH_SPLIT(dev));
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 908000, .max = 1512000 },
94 .n = { .min = 2, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 908000, .max = 1512000 },
107 .n = { .min = 2, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 908000, .max = 1512000 },
120 .n = { .min = 2, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
312 static const intel_limit_t intel_limits_vlv = {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk, intel_clock_t *clock)
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 if (WARN_ON(clock->n == 0 || clock->p == 0))
334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 struct drm_device *dev = crtc->dev;
357 const intel_limit_t *limit;
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
360 if (intel_is_dual_link_lvds(dev)) {
361 if (refclk == 100000)
362 limit = &intel_limits_ironlake_dual_lvds_100m;
364 limit = &intel_limits_ironlake_dual_lvds;
366 if (refclk == 100000)
367 limit = &intel_limits_ironlake_single_lvds_100m;
369 limit = &intel_limits_ironlake_single_lvds;
372 limit = &intel_limits_ironlake_dac;
377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
379 struct drm_device *dev = crtc->dev;
380 const intel_limit_t *limit;
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
383 if (intel_is_dual_link_lvds(dev))
384 limit = &intel_limits_g4x_dual_channel_lvds;
386 limit = &intel_limits_g4x_single_channel_lvds;
387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
389 limit = &intel_limits_g4x_hdmi;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
391 limit = &intel_limits_g4x_sdvo;
392 } else /* The option is for other outputs */
393 limit = &intel_limits_i9xx_sdvo;
398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
403 if (HAS_PCH_SPLIT(dev))
404 limit = intel_ironlake_limit(crtc, refclk);
405 else if (IS_G4X(dev)) {
406 limit = intel_g4x_limit(crtc);
407 } else if (IS_PINEVIEW(dev)) {
408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
409 limit = &intel_limits_pineview_lvds;
411 limit = &intel_limits_pineview_sdvo;
412 } else if (IS_VALLEYVIEW(dev)) {
413 limit = &intel_limits_vlv;
414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
418 limit = &intel_limits_i9xx_sdvo;
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
421 limit = &intel_limits_i8xx_lvds;
422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
423 limit = &intel_limits_i8xx_dvo;
425 limit = &intel_limits_i8xx_dac;
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk, intel_clock_t *clock)
433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
435 if (WARN_ON(clock->n == 0 || clock->p == 0))
437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
446 static void i9xx_clock(int refclk, intel_clock_t *clock)
448 clock->m = i9xx_dpll_compute_m(clock);
449 clock->p = clock->p1 * clock->p2;
450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
492 INTELPllInvalid("dot out of range\n");
498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
502 struct drm_device *dev = crtc->dev;
506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
512 if (intel_is_dual_link_lvds(dev))
513 clock.p2 = limit->p2.p2_fast;
515 clock.p2 = limit->p2.p2_slow;
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
520 clock.p2 = limit->p2.p2_fast;
523 memset(best_clock, 0, sizeof(*best_clock));
525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
529 if (clock.m2 >= clock.m1)
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
537 i9xx_clock(refclk, &clock);
538 if (!intel_PLL_is_valid(dev, limit,
542 clock.p != match_clock->p)
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
555 return (err != target);
559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
563 struct drm_device *dev = crtc->dev;
567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
573 if (intel_is_dual_link_lvds(dev))
574 clock.p2 = limit->p2.p2_fast;
576 clock.p2 = limit->p2.p2_slow;
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
581 clock.p2 = limit->p2.p2_fast;
584 memset(best_clock, 0, sizeof(*best_clock));
586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
596 pineview_clock(refclk, &clock);
597 if (!intel_PLL_is_valid(dev, limit,
601 clock.p != match_clock->p)
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
614 return (err != target);
618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
622 struct drm_device *dev = crtc->dev;
626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
631 if (intel_is_dual_link_lvds(dev))
632 clock.p2 = limit->p2.p2_fast;
634 clock.p2 = limit->p2.p2_slow;
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
639 clock.p2 = limit->p2.p2_fast;
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
655 i9xx_clock(refclk, &clock);
656 if (!intel_PLL_is_valid(dev, limit,
660 this_err = abs(clock.dot - target);
661 if (this_err < err_most) {
675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
679 struct drm_device *dev = crtc->dev;
681 unsigned int bestppm = 1000000;
682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
686 target *= 5; /* fast clock */
688 memset(best_clock, 0, sizeof(*best_clock));
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
695 clock.p = clock.p1 * clock.p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
698 unsigned int ppm, diff;
700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
703 vlv_clock(refclk, &clock);
705 if (!intel_PLL_is_valid(dev, limit,
709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
712 if (ppm < 100 && clock.p > best_clock->p) {
718 if (bestppm >= 10 && ppm < bestppm - 10) {
731 bool intel_crtc_active(struct drm_crtc *crtc)
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
744 return intel_crtc->active && crtc->fb &&
745 intel_crtc->config.adjusted_mode.crtc_clock;
748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
754 return intel_crtc->config.cpu_transcoder;
757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
762 frame = I915_READ(frame_reg);
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
769 * intel_wait_for_vblank - wait for vblank on a given pipe
771 * @pipe: pipe to wait for
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 int pipestat_reg = PIPESTAT(pipe);
781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
806 DRM_DEBUG_KMS("vblank wait timed out\n");
809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
817 line_mask = DSL_LINEMASK_GEN2;
819 line_mask = DSL_LINEMASK_GEN3;
821 line1 = I915_READ(reg) & line_mask;
823 line2 = I915_READ(reg) & line_mask;
825 return line1 == line2;
829 * intel_wait_for_pipe_off - wait for pipe to turn off
831 * @pipe: pipe to wait for
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
838 * wait for the pipe register state bit to turn off
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
851 if (INTEL_INFO(dev)->gen >= 4) {
852 int reg = PIPECONF(cpu_transcoder);
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
857 WARN(1, "pipe_off wait timed out\n");
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
877 if (HAS_PCH_IBX(dev_priv->dev)) {
880 bit = SDE_PORTB_HOTPLUG;
883 bit = SDE_PORTC_HOTPLUG;
886 bit = SDE_PORTD_HOTPLUG;
894 bit = SDE_PORTB_HOTPLUG_CPT;
897 bit = SDE_PORTC_HOTPLUG_CPT;
900 bit = SDE_PORTD_HOTPLUG_CPT;
907 return I915_READ(SDEISR) & bit;
910 static const char *state_string(bool enabled)
912 return enabled ? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954 if (crtc->config.shared_dpll < 0)
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
966 struct intel_dpll_hw_state hw_state;
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1063 int pp_reg, lvds_reg;
1065 enum pipe panel_pipe = PIPE_A;
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1072 pp_reg = PP_CONTROL;
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1092 struct drm_device *dev = dev_priv->dev;
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1157 struct drm_device *dev = dev_priv->dev;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1187 struct drm_device *dev = dev_priv->dev;
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1248 if ((val & DP_PORT_EN) == 0)
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1266 if ((val & SDVO_ENABLE) == 0)
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1282 if ((val & LVDS_PORT_EN) == 0)
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1363 static void intel_init_dpio(struct drm_device *dev)
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1367 if (!IS_VALLEYVIEW(dev))
1370 /* Enable the CRI clock source so we can get at the display */
1371 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1372 DPLL_INTEGRATED_CRI_CLK_VLV);
1374 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1377 static void intel_reset_dpio(struct drm_device *dev)
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1381 if (!IS_VALLEYVIEW(dev))
1385 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1386 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1387 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1388 * b. The other bits such as sfr settings / modesel may all be set
1391 * This should only be done on init and resume from S3 with both
1392 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1394 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1397 static void vlv_enable_pll(struct intel_crtc *crtc)
1399 struct drm_device *dev = crtc->base.dev;
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401 int reg = DPLL(crtc->pipe);
1402 u32 dpll = crtc->config.dpll_hw_state.dpll;
1404 assert_pipe_disabled(dev_priv, crtc->pipe);
1406 /* No really, not for ILK+ */
1407 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1409 /* PLL is protected by panel, make sure we can write it */
1410 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1411 assert_panel_unlocked(dev_priv, crtc->pipe);
1413 I915_WRITE(reg, dpll);
1417 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1418 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1420 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1421 POSTING_READ(DPLL_MD(crtc->pipe));
1423 /* We do this three times for luck */
1424 I915_WRITE(reg, dpll);
1426 udelay(150); /* wait for warmup */
1427 I915_WRITE(reg, dpll);
1429 udelay(150); /* wait for warmup */
1430 I915_WRITE(reg, dpll);
1432 udelay(150); /* wait for warmup */
1435 static void i9xx_enable_pll(struct intel_crtc *crtc)
1437 struct drm_device *dev = crtc->base.dev;
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 int reg = DPLL(crtc->pipe);
1440 u32 dpll = crtc->config.dpll_hw_state.dpll;
1442 assert_pipe_disabled(dev_priv, crtc->pipe);
1444 /* No really, not for ILK+ */
1445 BUG_ON(dev_priv->info->gen >= 5);
1447 /* PLL is protected by panel, make sure we can write it */
1448 if (IS_MOBILE(dev) && !IS_I830(dev))
1449 assert_panel_unlocked(dev_priv, crtc->pipe);
1451 I915_WRITE(reg, dpll);
1453 /* Wait for the clocks to stabilize. */
1457 if (INTEL_INFO(dev)->gen >= 4) {
1458 I915_WRITE(DPLL_MD(crtc->pipe),
1459 crtc->config.dpll_hw_state.dpll_md);
1461 /* The pixel multiplier can only be updated once the
1462 * DPLL is enabled and the clocks are stable.
1464 * So write it again.
1466 I915_WRITE(reg, dpll);
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, dpll);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, dpll);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, dpll);
1478 udelay(150); /* wait for warmup */
1482 * i9xx_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1488 * Note! This is for pre-ILK only.
1490 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1492 /* Don't disable pipe A or pipe A PLLs if needed */
1493 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1496 /* Make sure the pipe isn't still relying on us */
1497 assert_pipe_disabled(dev_priv, pipe);
1499 I915_WRITE(DPLL(pipe), 0);
1500 POSTING_READ(DPLL(pipe));
1503 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1507 /* Make sure the pipe isn't still relying on us */
1508 assert_pipe_disabled(dev_priv, pipe);
1510 /* Leave integrated clock source enabled */
1512 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1513 I915_WRITE(DPLL(pipe), val);
1514 POSTING_READ(DPLL(pipe));
1517 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1518 struct intel_digital_port *dport)
1522 switch (dport->port) {
1524 port_mask = DPLL_PORTB_READY_MASK;
1527 port_mask = DPLL_PORTC_READY_MASK;
1533 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1534 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1535 port_name(dport->port), I915_READ(DPLL(0)));
1539 * ironlake_enable_shared_dpll - enable PCH PLL
1540 * @dev_priv: i915 private structure
1541 * @pipe: pipe PLL to enable
1543 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1544 * drives the transcoder clock.
1546 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1548 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1549 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1551 /* PCH PLLs only available on ILK, SNB and IVB */
1552 BUG_ON(dev_priv->info->gen < 5);
1553 if (WARN_ON(pll == NULL))
1556 if (WARN_ON(pll->refcount == 0))
1559 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1560 pll->name, pll->active, pll->on,
1561 crtc->base.base.id);
1563 if (pll->active++) {
1565 assert_shared_dpll_enabled(dev_priv, pll);
1570 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1571 pll->enable(dev_priv, pll);
1575 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1577 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1578 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1580 /* PCH only available on ILK+ */
1581 BUG_ON(dev_priv->info->gen < 5);
1582 if (WARN_ON(pll == NULL))
1585 if (WARN_ON(pll->refcount == 0))
1588 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1589 pll->name, pll->active, pll->on,
1590 crtc->base.base.id);
1592 if (WARN_ON(pll->active == 0)) {
1593 assert_shared_dpll_disabled(dev_priv, pll);
1597 assert_shared_dpll_enabled(dev_priv, pll);
1602 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1603 pll->disable(dev_priv, pll);
1607 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1610 struct drm_device *dev = dev_priv->dev;
1611 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1613 uint32_t reg, val, pipeconf_val;
1615 /* PCH only available on ILK+ */
1616 BUG_ON(dev_priv->info->gen < 5);
1618 /* Make sure PCH DPLL is enabled */
1619 assert_shared_dpll_enabled(dev_priv,
1620 intel_crtc_to_shared_dpll(intel_crtc));
1622 /* FDI must be feeding us bits for PCH ports */
1623 assert_fdi_tx_enabled(dev_priv, pipe);
1624 assert_fdi_rx_enabled(dev_priv, pipe);
1626 if (HAS_PCH_CPT(dev)) {
1627 /* Workaround: Set the timing override bit before enabling the
1628 * pch transcoder. */
1629 reg = TRANS_CHICKEN2(pipe);
1630 val = I915_READ(reg);
1631 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1632 I915_WRITE(reg, val);
1635 reg = PCH_TRANSCONF(pipe);
1636 val = I915_READ(reg);
1637 pipeconf_val = I915_READ(PIPECONF(pipe));
1639 if (HAS_PCH_IBX(dev_priv->dev)) {
1641 * make the BPC in transcoder be consistent with
1642 * that in pipeconf reg.
1644 val &= ~PIPECONF_BPC_MASK;
1645 val |= pipeconf_val & PIPECONF_BPC_MASK;
1648 val &= ~TRANS_INTERLACE_MASK;
1649 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1650 if (HAS_PCH_IBX(dev_priv->dev) &&
1651 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1652 val |= TRANS_LEGACY_INTERLACED_ILK;
1654 val |= TRANS_INTERLACED;
1656 val |= TRANS_PROGRESSIVE;
1658 I915_WRITE(reg, val | TRANS_ENABLE);
1659 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1660 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1663 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1664 enum transcoder cpu_transcoder)
1666 u32 val, pipeconf_val;
1668 /* PCH only available on ILK+ */
1669 BUG_ON(dev_priv->info->gen < 5);
1671 /* FDI must be feeding us bits for PCH ports */
1672 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1673 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1675 /* Workaround: set timing override bit. */
1676 val = I915_READ(_TRANSA_CHICKEN2);
1677 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1678 I915_WRITE(_TRANSA_CHICKEN2, val);
1681 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1684 PIPECONF_INTERLACED_ILK)
1685 val |= TRANS_INTERLACED;
1687 val |= TRANS_PROGRESSIVE;
1689 I915_WRITE(LPT_TRANSCONF, val);
1690 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1691 DRM_ERROR("Failed to enable PCH transcoder\n");
1694 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1697 struct drm_device *dev = dev_priv->dev;
1700 /* FDI relies on the transcoder */
1701 assert_fdi_tx_disabled(dev_priv, pipe);
1702 assert_fdi_rx_disabled(dev_priv, pipe);
1704 /* Ports must be off as well */
1705 assert_pch_ports_disabled(dev_priv, pipe);
1707 reg = PCH_TRANSCONF(pipe);
1708 val = I915_READ(reg);
1709 val &= ~TRANS_ENABLE;
1710 I915_WRITE(reg, val);
1711 /* wait for PCH transcoder off, transcoder state */
1712 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1713 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1715 if (!HAS_PCH_IBX(dev)) {
1716 /* Workaround: Clear the timing override chicken bit again. */
1717 reg = TRANS_CHICKEN2(pipe);
1718 val = I915_READ(reg);
1719 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1720 I915_WRITE(reg, val);
1724 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1728 val = I915_READ(LPT_TRANSCONF);
1729 val &= ~TRANS_ENABLE;
1730 I915_WRITE(LPT_TRANSCONF, val);
1731 /* wait for PCH transcoder off, transcoder state */
1732 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1733 DRM_ERROR("Failed to disable PCH transcoder\n");
1735 /* Workaround: clear timing override bit. */
1736 val = I915_READ(_TRANSA_CHICKEN2);
1737 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1738 I915_WRITE(_TRANSA_CHICKEN2, val);
1742 * intel_enable_pipe - enable a pipe, asserting requirements
1743 * @dev_priv: i915 private structure
1744 * @pipe: pipe to enable
1745 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1747 * Enable @pipe, making sure that various hardware specific requirements
1748 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1750 * @pipe should be %PIPE_A or %PIPE_B.
1752 * Will wait until the pipe is actually running (i.e. first vblank) before
1755 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1756 bool pch_port, bool dsi)
1758 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1760 enum pipe pch_transcoder;
1764 assert_planes_disabled(dev_priv, pipe);
1765 assert_cursor_disabled(dev_priv, pipe);
1766 assert_sprites_disabled(dev_priv, pipe);
1768 if (HAS_PCH_LPT(dev_priv->dev))
1769 pch_transcoder = TRANSCODER_A;
1771 pch_transcoder = pipe;
1774 * A pipe without a PLL won't actually be able to drive bits from
1775 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1778 if (!HAS_PCH_SPLIT(dev_priv->dev))
1780 assert_dsi_pll_enabled(dev_priv);
1782 assert_pll_enabled(dev_priv, pipe);
1785 /* if driving the PCH, we need FDI enabled */
1786 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1787 assert_fdi_tx_pll_enabled(dev_priv,
1788 (enum pipe) cpu_transcoder);
1790 /* FIXME: assert CPU port conditions for SNB+ */
1793 reg = PIPECONF(cpu_transcoder);
1794 val = I915_READ(reg);
1795 if (val & PIPECONF_ENABLE)
1798 I915_WRITE(reg, val | PIPECONF_ENABLE);
1799 intel_wait_for_vblank(dev_priv->dev, pipe);
1803 * intel_disable_pipe - disable a pipe, asserting requirements
1804 * @dev_priv: i915 private structure
1805 * @pipe: pipe to disable
1807 * Disable @pipe, making sure that various hardware specific requirements
1808 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1810 * @pipe should be %PIPE_A or %PIPE_B.
1812 * Will wait until the pipe has shut down before returning.
1814 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1823 * Make sure planes won't keep trying to pump pixels to us,
1824 * or we might hang the display.
1826 assert_planes_disabled(dev_priv, pipe);
1827 assert_cursor_disabled(dev_priv, pipe);
1828 assert_sprites_disabled(dev_priv, pipe);
1830 /* Don't disable pipe A or pipe A PLLs if needed */
1831 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1834 reg = PIPECONF(cpu_transcoder);
1835 val = I915_READ(reg);
1836 if ((val & PIPECONF_ENABLE) == 0)
1839 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1840 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1844 * Plane regs are double buffered, going from enabled->disabled needs a
1845 * trigger in order to latch. The display address reg provides this.
1847 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1850 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1852 I915_WRITE(reg, I915_READ(reg));
1857 * intel_enable_primary_plane - enable the primary plane on a given pipe
1858 * @dev_priv: i915 private structure
1859 * @plane: plane to enable
1860 * @pipe: pipe being fed
1862 * Enable @plane on @pipe, making sure that @pipe is running first.
1864 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1865 enum plane plane, enum pipe pipe)
1867 struct intel_crtc *intel_crtc =
1868 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1872 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1873 assert_pipe_enabled(dev_priv, pipe);
1875 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1877 intel_crtc->primary_enabled = true;
1879 reg = DSPCNTR(plane);
1880 val = I915_READ(reg);
1881 if (val & DISPLAY_PLANE_ENABLE)
1884 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1885 intel_flush_primary_plane(dev_priv, plane);
1886 intel_wait_for_vblank(dev_priv->dev, pipe);
1890 * intel_disable_primary_plane - disable the primary plane
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to disable
1893 * @pipe: pipe consuming the data
1895 * Disable @plane; should be an independent operation.
1897 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1900 struct intel_crtc *intel_crtc =
1901 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1905 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1907 intel_crtc->primary_enabled = false;
1909 reg = DSPCNTR(plane);
1910 val = I915_READ(reg);
1911 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1914 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1915 intel_flush_primary_plane(dev_priv, plane);
1916 intel_wait_for_vblank(dev_priv->dev, pipe);
1919 static bool need_vtd_wa(struct drm_device *dev)
1921 #ifdef CONFIG_INTEL_IOMMU
1922 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1929 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1930 struct drm_i915_gem_object *obj,
1931 struct intel_ring_buffer *pipelined)
1933 struct drm_i915_private *dev_priv = dev->dev_private;
1937 switch (obj->tiling_mode) {
1938 case I915_TILING_NONE:
1939 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1940 alignment = 128 * 1024;
1941 else if (INTEL_INFO(dev)->gen >= 4)
1942 alignment = 4 * 1024;
1944 alignment = 64 * 1024;
1947 /* pin() will align the object as required by fence */
1951 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1957 /* Note that the w/a also requires 64 PTE of padding following the
1958 * bo. We currently fill all unused PTE with the shadow page and so
1959 * we should always have valid PTE following the scanout preventing
1962 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1963 alignment = 256 * 1024;
1965 dev_priv->mm.interruptible = false;
1966 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1968 goto err_interruptible;
1970 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1971 * fence, whereas 965+ only requires a fence if using
1972 * framebuffer compression. For simplicity, we always install
1973 * a fence as the cost is not that onerous.
1975 ret = i915_gem_object_get_fence(obj);
1979 i915_gem_object_pin_fence(obj);
1981 dev_priv->mm.interruptible = true;
1985 i915_gem_object_unpin_from_display_plane(obj);
1987 dev_priv->mm.interruptible = true;
1991 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1993 i915_gem_object_unpin_fence(obj);
1994 i915_gem_object_unpin_from_display_plane(obj);
1997 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1998 * is assumed to be a power-of-two. */
1999 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2000 unsigned int tiling_mode,
2004 if (tiling_mode != I915_TILING_NONE) {
2005 unsigned int tile_rows, tiles;
2010 tiles = *x / (512/cpp);
2013 return tile_rows * pitch * 8 + tiles * 4096;
2015 unsigned int offset;
2017 offset = *y * pitch + *x * cpp;
2019 *x = (offset & 4095) / cpp;
2020 return offset & -4096;
2024 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2027 struct drm_device *dev = crtc->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030 struct intel_framebuffer *intel_fb;
2031 struct drm_i915_gem_object *obj;
2032 int plane = intel_crtc->plane;
2033 unsigned long linear_offset;
2042 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2046 intel_fb = to_intel_framebuffer(fb);
2047 obj = intel_fb->obj;
2049 reg = DSPCNTR(plane);
2050 dspcntr = I915_READ(reg);
2051 /* Mask out pixel format bits in case we change it */
2052 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2053 switch (fb->pixel_format) {
2055 dspcntr |= DISPPLANE_8BPP;
2057 case DRM_FORMAT_XRGB1555:
2058 case DRM_FORMAT_ARGB1555:
2059 dspcntr |= DISPPLANE_BGRX555;
2061 case DRM_FORMAT_RGB565:
2062 dspcntr |= DISPPLANE_BGRX565;
2064 case DRM_FORMAT_XRGB8888:
2065 case DRM_FORMAT_ARGB8888:
2066 dspcntr |= DISPPLANE_BGRX888;
2068 case DRM_FORMAT_XBGR8888:
2069 case DRM_FORMAT_ABGR8888:
2070 dspcntr |= DISPPLANE_RGBX888;
2072 case DRM_FORMAT_XRGB2101010:
2073 case DRM_FORMAT_ARGB2101010:
2074 dspcntr |= DISPPLANE_BGRX101010;
2076 case DRM_FORMAT_XBGR2101010:
2077 case DRM_FORMAT_ABGR2101010:
2078 dspcntr |= DISPPLANE_RGBX101010;
2084 if (INTEL_INFO(dev)->gen >= 4) {
2085 if (obj->tiling_mode != I915_TILING_NONE)
2086 dspcntr |= DISPPLANE_TILED;
2088 dspcntr &= ~DISPPLANE_TILED;
2092 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2094 I915_WRITE(reg, dspcntr);
2096 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2098 if (INTEL_INFO(dev)->gen >= 4) {
2099 intel_crtc->dspaddr_offset =
2100 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2101 fb->bits_per_pixel / 8,
2103 linear_offset -= intel_crtc->dspaddr_offset;
2105 intel_crtc->dspaddr_offset = linear_offset;
2108 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2109 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2112 if (INTEL_INFO(dev)->gen >= 4) {
2113 I915_MODIFY_DISPBASE(DSPSURF(plane),
2114 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2115 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2116 I915_WRITE(DSPLINOFF(plane), linear_offset);
2118 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2124 static int ironlake_update_plane(struct drm_crtc *crtc,
2125 struct drm_framebuffer *fb, int x, int y)
2127 struct drm_device *dev = crtc->dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130 struct intel_framebuffer *intel_fb;
2131 struct drm_i915_gem_object *obj;
2132 int plane = intel_crtc->plane;
2133 unsigned long linear_offset;
2143 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2147 intel_fb = to_intel_framebuffer(fb);
2148 obj = intel_fb->obj;
2150 reg = DSPCNTR(plane);
2151 dspcntr = I915_READ(reg);
2152 /* Mask out pixel format bits in case we change it */
2153 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2154 switch (fb->pixel_format) {
2156 dspcntr |= DISPPLANE_8BPP;
2158 case DRM_FORMAT_RGB565:
2159 dspcntr |= DISPPLANE_BGRX565;
2161 case DRM_FORMAT_XRGB8888:
2162 case DRM_FORMAT_ARGB8888:
2163 dspcntr |= DISPPLANE_BGRX888;
2165 case DRM_FORMAT_XBGR8888:
2166 case DRM_FORMAT_ABGR8888:
2167 dspcntr |= DISPPLANE_RGBX888;
2169 case DRM_FORMAT_XRGB2101010:
2170 case DRM_FORMAT_ARGB2101010:
2171 dspcntr |= DISPPLANE_BGRX101010;
2173 case DRM_FORMAT_XBGR2101010:
2174 case DRM_FORMAT_ABGR2101010:
2175 dspcntr |= DISPPLANE_RGBX101010;
2181 if (obj->tiling_mode != I915_TILING_NONE)
2182 dspcntr |= DISPPLANE_TILED;
2184 dspcntr &= ~DISPPLANE_TILED;
2186 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2187 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2189 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2191 I915_WRITE(reg, dspcntr);
2193 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2194 intel_crtc->dspaddr_offset =
2195 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2196 fb->bits_per_pixel / 8,
2198 linear_offset -= intel_crtc->dspaddr_offset;
2200 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2201 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2203 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2204 I915_MODIFY_DISPBASE(DSPSURF(plane),
2205 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2206 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2207 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2209 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210 I915_WRITE(DSPLINOFF(plane), linear_offset);
2217 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2219 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220 int x, int y, enum mode_set_atomic state)
2222 struct drm_device *dev = crtc->dev;
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2225 if (dev_priv->display.disable_fbc)
2226 dev_priv->display.disable_fbc(dev);
2227 intel_increase_pllclock(crtc);
2229 return dev_priv->display.update_plane(crtc, fb, x, y);
2232 void intel_display_handle_reset(struct drm_device *dev)
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct drm_crtc *crtc;
2238 * Flips in the rings have been nuked by the reset,
2239 * so complete all pending flips so that user space
2240 * will get its events and not get stuck.
2242 * Also update the base address of all primary
2243 * planes to the the last fb to make sure we're
2244 * showing the correct fb after a reset.
2246 * Need to make two loops over the crtcs so that we
2247 * don't try to grab a crtc mutex before the
2248 * pending_flip_queue really got woken up.
2251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253 enum plane plane = intel_crtc->plane;
2255 intel_prepare_page_flip(dev, plane);
2256 intel_finish_page_flip_plane(dev, plane);
2259 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2262 mutex_lock(&crtc->mutex);
2264 * FIXME: Once we have proper support for primary planes (and
2265 * disabling them without disabling the entire crtc) allow again
2268 if (intel_crtc->active && crtc->fb)
2269 dev_priv->display.update_plane(crtc, crtc->fb,
2271 mutex_unlock(&crtc->mutex);
2276 intel_finish_fb(struct drm_framebuffer *old_fb)
2278 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2279 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2280 bool was_interruptible = dev_priv->mm.interruptible;
2283 /* Big Hammer, we also need to ensure that any pending
2284 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2285 * current scanout is retired before unpinning the old
2288 * This should only fail upon a hung GPU, in which case we
2289 * can safely continue.
2291 dev_priv->mm.interruptible = false;
2292 ret = i915_gem_object_finish_gpu(obj);
2293 dev_priv->mm.interruptible = was_interruptible;
2298 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2300 struct drm_device *dev = crtc->dev;
2301 struct drm_i915_master_private *master_priv;
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 if (!dev->primary->master)
2307 master_priv = dev->primary->master->driver_priv;
2308 if (!master_priv->sarea_priv)
2311 switch (intel_crtc->pipe) {
2313 master_priv->sarea_priv->pipeA_x = x;
2314 master_priv->sarea_priv->pipeA_y = y;
2317 master_priv->sarea_priv->pipeB_x = x;
2318 master_priv->sarea_priv->pipeB_y = y;
2326 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2327 struct drm_framebuffer *fb)
2329 struct drm_device *dev = crtc->dev;
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332 struct drm_framebuffer *old_fb;
2337 DRM_ERROR("No FB bound\n");
2341 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2342 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2343 plane_name(intel_crtc->plane),
2344 INTEL_INFO(dev)->num_pipes);
2348 mutex_lock(&dev->struct_mutex);
2349 ret = intel_pin_and_fence_fb_obj(dev,
2350 to_intel_framebuffer(fb)->obj,
2353 mutex_unlock(&dev->struct_mutex);
2354 DRM_ERROR("pin & fence failed\n");
2359 * Update pipe size and adjust fitter if needed: the reason for this is
2360 * that in compute_mode_changes we check the native mode (not the pfit
2361 * mode) to see if we can flip rather than do a full mode set. In the
2362 * fastboot case, we'll flip, but if we don't update the pipesrc and
2363 * pfit state, we'll end up with a big fb scanned out into the wrong
2366 * To fix this properly, we need to hoist the checks up into
2367 * compute_mode_changes (or above), check the actual pfit state and
2368 * whether the platform allows pfit disable with pipe active, and only
2369 * then update the pipesrc and pfit state, even on the flip path.
2371 if (i915_fastboot) {
2372 const struct drm_display_mode *adjusted_mode =
2373 &intel_crtc->config.adjusted_mode;
2375 I915_WRITE(PIPESRC(intel_crtc->pipe),
2376 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2377 (adjusted_mode->crtc_vdisplay - 1));
2378 if (!intel_crtc->config.pch_pfit.enabled &&
2379 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2381 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2382 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2383 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2387 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2389 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2390 mutex_unlock(&dev->struct_mutex);
2391 DRM_ERROR("failed to update base address\n");
2401 if (intel_crtc->active && old_fb != fb)
2402 intel_wait_for_vblank(dev, intel_crtc->pipe);
2403 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2406 intel_update_fbc(dev);
2407 intel_edp_psr_update(dev);
2408 mutex_unlock(&dev->struct_mutex);
2410 intel_crtc_update_sarea_pos(crtc, x, y);
2415 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2417 struct drm_device *dev = crtc->dev;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420 int pipe = intel_crtc->pipe;
2423 /* enable normal train */
2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
2426 if (IS_IVYBRIDGE(dev)) {
2427 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2428 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2433 I915_WRITE(reg, temp);
2435 reg = FDI_RX_CTL(pipe);
2436 temp = I915_READ(reg);
2437 if (HAS_PCH_CPT(dev)) {
2438 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2439 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_NONE;
2444 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2446 /* wait one idle pattern time */
2450 /* IVB wants error correction enabled */
2451 if (IS_IVYBRIDGE(dev))
2452 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2453 FDI_FE_ERRC_ENABLE);
2456 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2458 return crtc->base.enabled && crtc->active &&
2459 crtc->config.has_pch_encoder;
2462 static void ivb_modeset_global_resources(struct drm_device *dev)
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 struct intel_crtc *pipe_B_crtc =
2466 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2467 struct intel_crtc *pipe_C_crtc =
2468 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2472 * When everything is off disable fdi C so that we could enable fdi B
2473 * with all lanes. Note that we don't care about enabled pipes without
2474 * an enabled pch encoder.
2476 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2477 !pipe_has_enabled_pch(pipe_C_crtc)) {
2478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2481 temp = I915_READ(SOUTH_CHICKEN1);
2482 temp &= ~FDI_BC_BIFURCATION_SELECT;
2483 DRM_DEBUG_KMS("disabling fdi C rx\n");
2484 I915_WRITE(SOUTH_CHICKEN1, temp);
2488 /* The FDI link training functions for ILK/Ibexpeak. */
2489 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2491 struct drm_device *dev = crtc->dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494 int pipe = intel_crtc->pipe;
2495 int plane = intel_crtc->plane;
2496 u32 reg, temp, tries;
2498 /* FDI needs bits from pipe & plane first */
2499 assert_pipe_enabled(dev_priv, pipe);
2500 assert_plane_enabled(dev_priv, plane);
2502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2504 reg = FDI_RX_IMR(pipe);
2505 temp = I915_READ(reg);
2506 temp &= ~FDI_RX_SYMBOL_LOCK;
2507 temp &= ~FDI_RX_BIT_LOCK;
2508 I915_WRITE(reg, temp);
2512 /* enable CPU FDI TX and PCH FDI RX */
2513 reg = FDI_TX_CTL(pipe);
2514 temp = I915_READ(reg);
2515 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2516 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2517 temp &= ~FDI_LINK_TRAIN_NONE;
2518 temp |= FDI_LINK_TRAIN_PATTERN_1;
2519 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_1;
2525 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2530 /* Ironlake workaround, enable clock pointer after FDI enable*/
2531 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2532 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2533 FDI_RX_PHASE_SYNC_POINTER_EN);
2535 reg = FDI_RX_IIR(pipe);
2536 for (tries = 0; tries < 5; tries++) {
2537 temp = I915_READ(reg);
2538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2540 if ((temp & FDI_RX_BIT_LOCK)) {
2541 DRM_DEBUG_KMS("FDI train 1 done.\n");
2542 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2547 DRM_ERROR("FDI train 1 fail!\n");
2550 reg = FDI_TX_CTL(pipe);
2551 temp = I915_READ(reg);
2552 temp &= ~FDI_LINK_TRAIN_NONE;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2;
2554 I915_WRITE(reg, temp);
2556 reg = FDI_RX_CTL(pipe);
2557 temp = I915_READ(reg);
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2560 I915_WRITE(reg, temp);
2565 reg = FDI_RX_IIR(pipe);
2566 for (tries = 0; tries < 5; tries++) {
2567 temp = I915_READ(reg);
2568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2570 if (temp & FDI_RX_SYMBOL_LOCK) {
2571 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2572 DRM_DEBUG_KMS("FDI train 2 done.\n");
2577 DRM_ERROR("FDI train 2 fail!\n");
2579 DRM_DEBUG_KMS("FDI train done\n");
2583 static const int snb_b_fdi_train_param[] = {
2584 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2585 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2586 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2587 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2590 /* The FDI link training functions for SNB/Cougarpoint. */
2591 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2593 struct drm_device *dev = crtc->dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2596 int pipe = intel_crtc->pipe;
2597 u32 reg, temp, i, retry;
2599 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2601 reg = FDI_RX_IMR(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_RX_SYMBOL_LOCK;
2604 temp &= ~FDI_RX_BIT_LOCK;
2605 I915_WRITE(reg, temp);
2610 /* enable CPU FDI TX and PCH FDI RX */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2614 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2615 temp &= ~FDI_LINK_TRAIN_NONE;
2616 temp |= FDI_LINK_TRAIN_PATTERN_1;
2617 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2620 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2622 I915_WRITE(FDI_RX_MISC(pipe),
2623 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2625 reg = FDI_RX_CTL(pipe);
2626 temp = I915_READ(reg);
2627 if (HAS_PCH_CPT(dev)) {
2628 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2629 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2631 temp &= ~FDI_LINK_TRAIN_NONE;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1;
2634 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2639 for (i = 0; i < 4; i++) {
2640 reg = FDI_TX_CTL(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643 temp |= snb_b_fdi_train_param[i];
2644 I915_WRITE(reg, temp);
2649 for (retry = 0; retry < 5; retry++) {
2650 reg = FDI_RX_IIR(pipe);
2651 temp = I915_READ(reg);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653 if (temp & FDI_RX_BIT_LOCK) {
2654 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2655 DRM_DEBUG_KMS("FDI train 1 done.\n");
2664 DRM_ERROR("FDI train 1 fail!\n");
2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_NONE;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2;
2672 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676 I915_WRITE(reg, temp);
2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 if (HAS_PCH_CPT(dev)) {
2681 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2682 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2684 temp &= ~FDI_LINK_TRAIN_NONE;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2;
2687 I915_WRITE(reg, temp);
2692 for (i = 0; i < 4; i++) {
2693 reg = FDI_TX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2696 temp |= snb_b_fdi_train_param[i];
2697 I915_WRITE(reg, temp);
2702 for (retry = 0; retry < 5; retry++) {
2703 reg = FDI_RX_IIR(pipe);
2704 temp = I915_READ(reg);
2705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2706 if (temp & FDI_RX_SYMBOL_LOCK) {
2707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2708 DRM_DEBUG_KMS("FDI train 2 done.\n");
2717 DRM_ERROR("FDI train 2 fail!\n");
2719 DRM_DEBUG_KMS("FDI train done.\n");
2722 /* Manual link training for Ivy Bridge A0 parts */
2723 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2725 struct drm_device *dev = crtc->dev;
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2728 int pipe = intel_crtc->pipe;
2729 u32 reg, temp, i, j;
2731 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2733 reg = FDI_RX_IMR(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_RX_SYMBOL_LOCK;
2736 temp &= ~FDI_RX_BIT_LOCK;
2737 I915_WRITE(reg, temp);
2742 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2743 I915_READ(FDI_RX_IIR(pipe)));
2745 /* Try each vswing and preemphasis setting twice before moving on */
2746 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2747 /* disable first in case we need to retry */
2748 reg = FDI_TX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2751 temp &= ~FDI_TX_ENABLE;
2752 I915_WRITE(reg, temp);
2754 reg = FDI_RX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~FDI_LINK_TRAIN_AUTO;
2757 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2758 temp &= ~FDI_RX_ENABLE;
2759 I915_WRITE(reg, temp);
2761 /* enable CPU FDI TX and PCH FDI RX */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2765 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2766 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2767 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2768 temp |= snb_b_fdi_train_param[j/2];
2769 temp |= FDI_COMPOSITE_SYNC;
2770 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2772 I915_WRITE(FDI_RX_MISC(pipe),
2773 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2775 reg = FDI_RX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2778 temp |= FDI_COMPOSITE_SYNC;
2779 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2782 udelay(1); /* should be 0.5us */
2784 for (i = 0; i < 4; i++) {
2785 reg = FDI_RX_IIR(pipe);
2786 temp = I915_READ(reg);
2787 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789 if (temp & FDI_RX_BIT_LOCK ||
2790 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2791 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2792 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2796 udelay(1); /* should be 0.5us */
2799 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2807 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2808 I915_WRITE(reg, temp);
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2813 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2814 I915_WRITE(reg, temp);
2817 udelay(2); /* should be 1.5us */
2819 for (i = 0; i < 4; i++) {
2820 reg = FDI_RX_IIR(pipe);
2821 temp = I915_READ(reg);
2822 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2824 if (temp & FDI_RX_SYMBOL_LOCK ||
2825 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2826 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2827 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2831 udelay(2); /* should be 1.5us */
2834 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2838 DRM_DEBUG_KMS("FDI train done.\n");
2841 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2843 struct drm_device *dev = intel_crtc->base.dev;
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 int pipe = intel_crtc->pipe;
2849 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2853 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2854 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2855 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2860 /* Switch from Rawclk to PCDclk */
2861 temp = I915_READ(reg);
2862 I915_WRITE(reg, temp | FDI_PCDCLK);
2867 /* Enable CPU FDI TX PLL, always on for Ironlake */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2871 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2878 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880 struct drm_device *dev = intel_crtc->base.dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 int pipe = intel_crtc->pipe;
2885 /* Switch from PCDclk to Rawclk */
2886 reg = FDI_RX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890 /* Disable CPU FDI TX PLL */
2891 reg = FDI_TX_CTL(pipe);
2892 temp = I915_READ(reg);
2893 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2898 reg = FDI_RX_CTL(pipe);
2899 temp = I915_READ(reg);
2900 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902 /* Wait for the clocks to turn off. */
2907 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909 struct drm_device *dev = crtc->dev;
2910 struct drm_i915_private *dev_priv = dev->dev_private;
2911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2912 int pipe = intel_crtc->pipe;
2915 /* disable CPU FDI tx and PCH FDI rx */
2916 reg = FDI_TX_CTL(pipe);
2917 temp = I915_READ(reg);
2918 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2921 reg = FDI_RX_CTL(pipe);
2922 temp = I915_READ(reg);
2923 temp &= ~(0x7 << 16);
2924 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2925 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2930 /* Ironlake workaround, disable clock pointer after downing FDI */
2931 if (HAS_PCH_IBX(dev)) {
2932 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2935 /* still set train pattern 1 */
2936 reg = FDI_TX_CTL(pipe);
2937 temp = I915_READ(reg);
2938 temp &= ~FDI_LINK_TRAIN_NONE;
2939 temp |= FDI_LINK_TRAIN_PATTERN_1;
2940 I915_WRITE(reg, temp);
2942 reg = FDI_RX_CTL(pipe);
2943 temp = I915_READ(reg);
2944 if (HAS_PCH_CPT(dev)) {
2945 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2946 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 temp &= ~FDI_LINK_TRAIN_NONE;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 /* BPC in FDI rx is consistent with that in PIPECONF */
2952 temp &= ~(0x07 << 16);
2953 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2954 I915_WRITE(reg, temp);
2960 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 unsigned long flags;
2968 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2969 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2972 spin_lock_irqsave(&dev->event_lock, flags);
2973 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2974 spin_unlock_irqrestore(&dev->event_lock, flags);
2979 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981 struct drm_device *dev = crtc->dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2984 if (crtc->fb == NULL)
2987 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989 wait_event(dev_priv->pending_flip_queue,
2990 !intel_crtc_has_pending_flip(crtc));
2992 mutex_lock(&dev->struct_mutex);
2993 intel_finish_fb(crtc->fb);
2994 mutex_unlock(&dev->struct_mutex);
2997 /* Program iCLKIP clock to the desired frequency */
2998 static void lpt_program_iclkip(struct drm_crtc *crtc)
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3003 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006 mutex_lock(&dev_priv->dpio_lock);
3008 /* It is necessary to ungate the pixclk gate prior to programming
3009 * the divisors, and gate it back when it is done.
3011 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3013 /* Disable SSCCTL */
3014 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3015 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3019 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3020 if (clock == 20000) {
3025 /* The iCLK virtual clock root frequency is in MHz,
3026 * but the adjusted_mode->crtc_clock in in KHz. To get the
3027 * divisors, it is necessary to divide one by another, so we
3028 * convert the virtual clock precision to KHz here for higher
3031 u32 iclk_virtual_root_freq = 172800 * 1000;
3032 u32 iclk_pi_range = 64;
3033 u32 desired_divisor, msb_divisor_value, pi_value;
3035 desired_divisor = (iclk_virtual_root_freq / clock);
3036 msb_divisor_value = desired_divisor / iclk_pi_range;
3037 pi_value = desired_divisor % iclk_pi_range;
3040 divsel = msb_divisor_value - 2;
3041 phaseinc = pi_value;
3044 /* This should not happen with any sane values */
3045 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3046 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3048 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3050 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3057 /* Program SSCDIVINTPHASE6 */
3058 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3059 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3060 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3061 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3063 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3064 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3065 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3067 /* Program SSCAUXDIV */
3068 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3069 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3070 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3071 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3073 /* Enable modulator and associated divider */
3074 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3075 temp &= ~SBI_SSCCTL_DISABLE;
3076 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3078 /* Wait for initialization time */
3081 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3083 mutex_unlock(&dev_priv->dpio_lock);
3086 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3087 enum pipe pch_transcoder)
3089 struct drm_device *dev = crtc->base.dev;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3093 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3094 I915_READ(HTOTAL(cpu_transcoder)));
3095 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3096 I915_READ(HBLANK(cpu_transcoder)));
3097 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3098 I915_READ(HSYNC(cpu_transcoder)));
3100 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3101 I915_READ(VTOTAL(cpu_transcoder)));
3102 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3103 I915_READ(VBLANK(cpu_transcoder)));
3104 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3105 I915_READ(VSYNC(cpu_transcoder)));
3106 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3107 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3110 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3115 temp = I915_READ(SOUTH_CHICKEN1);
3116 if (temp & FDI_BC_BIFURCATION_SELECT)
3119 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3120 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3122 temp |= FDI_BC_BIFURCATION_SELECT;
3123 DRM_DEBUG_KMS("enabling fdi C rx\n");
3124 I915_WRITE(SOUTH_CHICKEN1, temp);
3125 POSTING_READ(SOUTH_CHICKEN1);
3128 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3130 struct drm_device *dev = intel_crtc->base.dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3133 switch (intel_crtc->pipe) {
3137 if (intel_crtc->config.fdi_lanes > 2)
3138 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3140 cpt_enable_fdi_bc_bifurcation(dev);
3144 cpt_enable_fdi_bc_bifurcation(dev);
3153 * Enable PCH resources required for PCH ports:
3155 * - FDI training & RX/TX
3156 * - update transcoder timings
3157 * - DP transcoding bits
3160 static void ironlake_pch_enable(struct drm_crtc *crtc)
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165 int pipe = intel_crtc->pipe;
3168 assert_pch_transcoder_disabled(dev_priv, pipe);
3170 if (IS_IVYBRIDGE(dev))
3171 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3173 /* Write the TU size bits before fdi link training, so that error
3174 * detection works. */
3175 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3176 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3178 /* For PCH output, training FDI link */
3179 dev_priv->display.fdi_link_train(crtc);
3181 /* We need to program the right clock selection before writing the pixel
3182 * mutliplier into the DPLL. */
3183 if (HAS_PCH_CPT(dev)) {
3186 temp = I915_READ(PCH_DPLL_SEL);
3187 temp |= TRANS_DPLL_ENABLE(pipe);
3188 sel = TRANS_DPLLB_SEL(pipe);
3189 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3193 I915_WRITE(PCH_DPLL_SEL, temp);
3196 /* XXX: pch pll's can be enabled any time before we enable the PCH
3197 * transcoder, and we actually should do this to not upset any PCH
3198 * transcoder that already use the clock when we share it.
3200 * Note that enable_shared_dpll tries to do the right thing, but
3201 * get_shared_dpll unconditionally resets the pll - we need that to have
3202 * the right LVDS enable sequence. */
3203 ironlake_enable_shared_dpll(intel_crtc);
3205 /* set transcoder timing, panel must allow it */
3206 assert_panel_unlocked(dev_priv, pipe);
3207 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3209 intel_fdi_normal_train(crtc);
3211 /* For PCH DP, enable TRANS_DP_CTL */
3212 if (HAS_PCH_CPT(dev) &&
3213 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3214 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3215 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3216 reg = TRANS_DP_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3219 TRANS_DP_SYNC_MASK |
3221 temp |= (TRANS_DP_OUTPUT_ENABLE |
3222 TRANS_DP_ENH_FRAMING);
3223 temp |= bpc << 9; /* same format but at 11:9 */
3225 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3226 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3227 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3228 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3230 switch (intel_trans_dp_port_sel(crtc)) {
3232 temp |= TRANS_DP_PORT_SEL_B;
3235 temp |= TRANS_DP_PORT_SEL_C;
3238 temp |= TRANS_DP_PORT_SEL_D;
3244 I915_WRITE(reg, temp);
3247 ironlake_enable_pch_transcoder(dev_priv, pipe);
3250 static void lpt_pch_enable(struct drm_crtc *crtc)
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3257 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3259 lpt_program_iclkip(crtc);
3261 /* Set transcoder timing. */
3262 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3264 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3267 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3269 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3274 if (pll->refcount == 0) {
3275 WARN(1, "bad %s refcount\n", pll->name);
3279 if (--pll->refcount == 0) {
3281 WARN_ON(pll->active);
3284 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3287 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3289 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3290 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3291 enum intel_dpll_id i;
3294 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3295 crtc->base.base.id, pll->name);
3296 intel_put_shared_dpll(crtc);
3299 if (HAS_PCH_IBX(dev_priv->dev)) {
3300 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3301 i = (enum intel_dpll_id) crtc->pipe;
3302 pll = &dev_priv->shared_dplls[i];
3304 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3305 crtc->base.base.id, pll->name);
3310 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3311 pll = &dev_priv->shared_dplls[i];
3313 /* Only want to check enabled timings first */
3314 if (pll->refcount == 0)
3317 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3318 sizeof(pll->hw_state)) == 0) {
3319 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3321 pll->name, pll->refcount, pll->active);
3327 /* Ok no matching timings, maybe there's a free one? */
3328 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3329 pll = &dev_priv->shared_dplls[i];
3330 if (pll->refcount == 0) {
3331 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3332 crtc->base.base.id, pll->name);
3340 crtc->config.shared_dpll = i;
3341 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3342 pipe_name(crtc->pipe));
3344 if (pll->active == 0) {
3345 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3346 sizeof(pll->hw_state));
3348 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3350 assert_shared_dpll_disabled(dev_priv, pll);
3352 pll->mode_set(dev_priv, pll);
3359 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 int dslreg = PIPEDSL(pipe);
3365 temp = I915_READ(dslreg);
3367 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3368 if (wait_for(I915_READ(dslreg) != temp, 5))
3369 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3373 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3375 struct drm_device *dev = crtc->base.dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 int pipe = crtc->pipe;
3379 if (crtc->config.pch_pfit.enabled) {
3380 /* Force use of hard-coded filter coefficients
3381 * as some pre-programmed values are broken,
3384 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3385 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3386 PF_PIPE_SEL_IVB(pipe));
3388 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3389 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3390 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3394 static void intel_enable_planes(struct drm_crtc *crtc)
3396 struct drm_device *dev = crtc->dev;
3397 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3398 struct intel_plane *intel_plane;
3400 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3401 if (intel_plane->pipe == pipe)
3402 intel_plane_restore(&intel_plane->base);
3405 static void intel_disable_planes(struct drm_crtc *crtc)
3407 struct drm_device *dev = crtc->dev;
3408 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3409 struct intel_plane *intel_plane;
3411 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3412 if (intel_plane->pipe == pipe)
3413 intel_plane_disable(&intel_plane->base);
3416 void hsw_enable_ips(struct intel_crtc *crtc)
3418 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3420 if (!crtc->config.ips_enabled)
3423 /* We can only enable IPS after we enable a plane and wait for a vblank.
3424 * We guarantee that the plane is enabled by calling intel_enable_ips
3425 * only after intel_enable_plane. And intel_enable_plane already waits
3426 * for a vblank, so all we need to do here is to enable the IPS bit. */
3427 assert_plane_enabled(dev_priv, crtc->plane);
3428 if (IS_BROADWELL(crtc->base.dev)) {
3429 mutex_lock(&dev_priv->rps.hw_lock);
3430 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3431 mutex_unlock(&dev_priv->rps.hw_lock);
3432 /* Quoting Art Runyan: "its not safe to expect any particular
3433 * value in IPS_CTL bit 31 after enabling IPS through the
3434 * mailbox." Therefore we need to defer waiting on the state
3436 * TODO: need to fix this for state checker
3439 I915_WRITE(IPS_CTL, IPS_ENABLE);
3440 /* The bit only becomes 1 in the next vblank, so this wait here
3441 * is essentially intel_wait_for_vblank. If we don't have this
3442 * and don't wait for vblanks until the end of crtc_enable, then
3443 * the HW state readout code will complain that the expected
3444 * IPS_CTL value is not the one we read. */
3445 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3446 DRM_ERROR("Timed out waiting for IPS enable\n");
3450 void hsw_disable_ips(struct intel_crtc *crtc)
3452 struct drm_device *dev = crtc->base.dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3455 if (!crtc->config.ips_enabled)
3458 assert_plane_enabled(dev_priv, crtc->plane);
3459 if (IS_BROADWELL(crtc->base.dev)) {
3460 mutex_lock(&dev_priv->rps.hw_lock);
3461 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3462 mutex_unlock(&dev_priv->rps.hw_lock);
3464 I915_WRITE(IPS_CTL, 0);
3465 POSTING_READ(IPS_CTL);
3467 /* We need to wait for a vblank before we can disable the plane. */
3468 intel_wait_for_vblank(dev, crtc->pipe);
3471 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3472 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477 enum pipe pipe = intel_crtc->pipe;
3478 int palreg = PALETTE(pipe);
3480 bool reenable_ips = false;
3482 /* The clocks have to be on to load the palette. */
3483 if (!crtc->enabled || !intel_crtc->active)
3486 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3487 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3488 assert_dsi_pll_enabled(dev_priv);
3490 assert_pll_enabled(dev_priv, pipe);
3493 /* use legacy palette for Ironlake */
3494 if (HAS_PCH_SPLIT(dev))
3495 palreg = LGC_PALETTE(pipe);
3497 /* Workaround : Do not read or write the pipe palette/gamma data while
3498 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3500 if (intel_crtc->config.ips_enabled &&
3501 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3502 GAMMA_MODE_MODE_SPLIT)) {
3503 hsw_disable_ips(intel_crtc);
3504 reenable_ips = true;
3507 for (i = 0; i < 256; i++) {
3508 I915_WRITE(palreg + 4 * i,
3509 (intel_crtc->lut_r[i] << 16) |
3510 (intel_crtc->lut_g[i] << 8) |
3511 intel_crtc->lut_b[i]);
3515 hsw_enable_ips(intel_crtc);
3518 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3520 struct drm_device *dev = crtc->dev;
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3523 struct intel_encoder *encoder;
3524 int pipe = intel_crtc->pipe;
3525 int plane = intel_crtc->plane;
3527 WARN_ON(!crtc->enabled);
3529 if (intel_crtc->active)
3532 intel_crtc->active = true;
3534 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3535 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3537 for_each_encoder_on_crtc(dev, crtc, encoder)
3538 if (encoder->pre_enable)
3539 encoder->pre_enable(encoder);
3541 if (intel_crtc->config.has_pch_encoder) {
3542 /* Note: FDI PLL enabling _must_ be done before we enable the
3543 * cpu pipes, hence this is separate from all the other fdi/pch
3545 ironlake_fdi_pll_enable(intel_crtc);
3547 assert_fdi_tx_disabled(dev_priv, pipe);
3548 assert_fdi_rx_disabled(dev_priv, pipe);
3551 ironlake_pfit_enable(intel_crtc);
3554 * On ILK+ LUT must be loaded before the pipe is running but with
3557 intel_crtc_load_lut(crtc);
3559 intel_update_watermarks(crtc);
3560 intel_enable_pipe(dev_priv, pipe,
3561 intel_crtc->config.has_pch_encoder, false);
3562 intel_enable_primary_plane(dev_priv, plane, pipe);
3563 intel_enable_planes(crtc);
3564 intel_crtc_update_cursor(crtc, true);
3566 if (intel_crtc->config.has_pch_encoder)
3567 ironlake_pch_enable(crtc);
3569 mutex_lock(&dev->struct_mutex);
3570 intel_update_fbc(dev);
3571 mutex_unlock(&dev->struct_mutex);
3573 for_each_encoder_on_crtc(dev, crtc, encoder)
3574 encoder->enable(encoder);
3576 if (HAS_PCH_CPT(dev))
3577 cpt_verify_modeset(dev, intel_crtc->pipe);
3580 * There seems to be a race in PCH platform hw (at least on some
3581 * outputs) where an enabled pipe still completes any pageflip right
3582 * away (as if the pipe is off) instead of waiting for vblank. As soon
3583 * as the first vblank happend, everything works as expected. Hence just
3584 * wait for one vblank before returning to avoid strange things
3587 intel_wait_for_vblank(dev, intel_crtc->pipe);
3590 /* IPS only exists on ULT machines and is tied to pipe A. */
3591 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3593 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3596 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3598 struct drm_device *dev = crtc->dev;
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3601 int pipe = intel_crtc->pipe;
3602 int plane = intel_crtc->plane;
3604 intel_enable_primary_plane(dev_priv, plane, pipe);
3605 intel_enable_planes(crtc);
3606 intel_crtc_update_cursor(crtc, true);
3608 hsw_enable_ips(intel_crtc);
3610 mutex_lock(&dev->struct_mutex);
3611 intel_update_fbc(dev);
3612 mutex_unlock(&dev->struct_mutex);
3615 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3617 struct drm_device *dev = crtc->dev;
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620 int pipe = intel_crtc->pipe;
3621 int plane = intel_crtc->plane;
3623 intel_crtc_wait_for_pending_flips(crtc);
3624 drm_vblank_off(dev, pipe);
3626 /* FBC must be disabled before disabling the plane on HSW. */
3627 if (dev_priv->fbc.plane == plane)
3628 intel_disable_fbc(dev);
3630 hsw_disable_ips(intel_crtc);
3632 intel_crtc_update_cursor(crtc, false);
3633 intel_disable_planes(crtc);
3634 intel_disable_primary_plane(dev_priv, plane, pipe);
3638 * This implements the workaround described in the "notes" section of the mode
3639 * set sequence documentation. When going from no pipes or single pipe to
3640 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3641 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3643 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3645 struct drm_device *dev = crtc->base.dev;
3646 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3648 /* We want to get the other_active_crtc only if there's only 1 other
3650 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3651 if (!crtc_it->active || crtc_it == crtc)
3654 if (other_active_crtc)
3657 other_active_crtc = crtc_it;
3659 if (!other_active_crtc)
3662 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3663 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3666 static void haswell_crtc_enable(struct drm_crtc *crtc)
3668 struct drm_device *dev = crtc->dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671 struct intel_encoder *encoder;
3672 int pipe = intel_crtc->pipe;
3674 WARN_ON(!crtc->enabled);
3676 if (intel_crtc->active)
3679 intel_crtc->active = true;
3681 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3682 if (intel_crtc->config.has_pch_encoder)
3683 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3685 if (intel_crtc->config.has_pch_encoder)
3686 dev_priv->display.fdi_link_train(crtc);
3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 if (encoder->pre_enable)
3690 encoder->pre_enable(encoder);
3692 intel_ddi_enable_pipe_clock(intel_crtc);
3694 ironlake_pfit_enable(intel_crtc);
3697 * On ILK+ LUT must be loaded before the pipe is running but with
3700 intel_crtc_load_lut(crtc);
3702 intel_ddi_set_pipe_settings(crtc);
3703 intel_ddi_enable_transcoder_func(crtc);
3705 intel_update_watermarks(crtc);
3706 intel_enable_pipe(dev_priv, pipe,
3707 intel_crtc->config.has_pch_encoder, false);
3709 if (intel_crtc->config.has_pch_encoder)
3710 lpt_pch_enable(crtc);
3712 for_each_encoder_on_crtc(dev, crtc, encoder) {
3713 encoder->enable(encoder);
3714 intel_opregion_notify_encoder(encoder, true);
3717 /* If we change the relative order between pipe/planes enabling, we need
3718 * to change the workaround. */
3719 haswell_mode_set_planes_workaround(intel_crtc);
3720 haswell_crtc_enable_planes(crtc);
3723 * There seems to be a race in PCH platform hw (at least on some
3724 * outputs) where an enabled pipe still completes any pageflip right
3725 * away (as if the pipe is off) instead of waiting for vblank. As soon
3726 * as the first vblank happend, everything works as expected. Hence just
3727 * wait for one vblank before returning to avoid strange things
3730 intel_wait_for_vblank(dev, intel_crtc->pipe);
3733 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3735 struct drm_device *dev = crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 int pipe = crtc->pipe;
3739 /* To avoid upsetting the power well on haswell only disable the pfit if
3740 * it's in use. The hw state code will make sure we get this right. */
3741 if (crtc->config.pch_pfit.enabled) {
3742 I915_WRITE(PF_CTL(pipe), 0);
3743 I915_WRITE(PF_WIN_POS(pipe), 0);
3744 I915_WRITE(PF_WIN_SZ(pipe), 0);
3748 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3750 struct drm_device *dev = crtc->dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3753 struct intel_encoder *encoder;
3754 int pipe = intel_crtc->pipe;
3755 int plane = intel_crtc->plane;
3759 if (!intel_crtc->active)
3762 for_each_encoder_on_crtc(dev, crtc, encoder)
3763 encoder->disable(encoder);
3765 intel_crtc_wait_for_pending_flips(crtc);
3766 drm_vblank_off(dev, pipe);
3768 if (dev_priv->fbc.plane == plane)
3769 intel_disable_fbc(dev);
3771 intel_crtc_update_cursor(crtc, false);
3772 intel_disable_planes(crtc);
3773 intel_disable_primary_plane(dev_priv, plane, pipe);
3775 if (intel_crtc->config.has_pch_encoder)
3776 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3778 intel_disable_pipe(dev_priv, pipe);
3780 ironlake_pfit_disable(intel_crtc);
3782 for_each_encoder_on_crtc(dev, crtc, encoder)
3783 if (encoder->post_disable)
3784 encoder->post_disable(encoder);
3786 if (intel_crtc->config.has_pch_encoder) {
3787 ironlake_fdi_disable(crtc);
3789 ironlake_disable_pch_transcoder(dev_priv, pipe);
3790 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3792 if (HAS_PCH_CPT(dev)) {
3793 /* disable TRANS_DP_CTL */
3794 reg = TRANS_DP_CTL(pipe);
3795 temp = I915_READ(reg);
3796 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3797 TRANS_DP_PORT_SEL_MASK);
3798 temp |= TRANS_DP_PORT_SEL_NONE;
3799 I915_WRITE(reg, temp);
3801 /* disable DPLL_SEL */
3802 temp = I915_READ(PCH_DPLL_SEL);
3803 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3804 I915_WRITE(PCH_DPLL_SEL, temp);
3807 /* disable PCH DPLL */
3808 intel_disable_shared_dpll(intel_crtc);
3810 ironlake_fdi_pll_disable(intel_crtc);
3813 intel_crtc->active = false;
3814 intel_update_watermarks(crtc);
3816 mutex_lock(&dev->struct_mutex);
3817 intel_update_fbc(dev);
3818 mutex_unlock(&dev->struct_mutex);
3821 static void haswell_crtc_disable(struct drm_crtc *crtc)
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3826 struct intel_encoder *encoder;
3827 int pipe = intel_crtc->pipe;
3828 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3830 if (!intel_crtc->active)
3833 haswell_crtc_disable_planes(crtc);
3835 for_each_encoder_on_crtc(dev, crtc, encoder) {
3836 intel_opregion_notify_encoder(encoder, false);
3837 encoder->disable(encoder);
3840 if (intel_crtc->config.has_pch_encoder)
3841 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3842 intel_disable_pipe(dev_priv, pipe);
3844 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3846 ironlake_pfit_disable(intel_crtc);
3848 intel_ddi_disable_pipe_clock(intel_crtc);
3850 for_each_encoder_on_crtc(dev, crtc, encoder)
3851 if (encoder->post_disable)
3852 encoder->post_disable(encoder);
3854 if (intel_crtc->config.has_pch_encoder) {
3855 lpt_disable_pch_transcoder(dev_priv);
3856 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3857 intel_ddi_fdi_disable(crtc);
3860 intel_crtc->active = false;
3861 intel_update_watermarks(crtc);
3863 mutex_lock(&dev->struct_mutex);
3864 intel_update_fbc(dev);
3865 mutex_unlock(&dev->struct_mutex);
3868 static void ironlake_crtc_off(struct drm_crtc *crtc)
3870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3871 intel_put_shared_dpll(intel_crtc);
3874 static void haswell_crtc_off(struct drm_crtc *crtc)
3876 intel_ddi_put_crtc_pll(crtc);
3879 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3881 if (!enable && intel_crtc->overlay) {
3882 struct drm_device *dev = intel_crtc->base.dev;
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3885 mutex_lock(&dev->struct_mutex);
3886 dev_priv->mm.interruptible = false;
3887 (void) intel_overlay_switch_off(intel_crtc->overlay);
3888 dev_priv->mm.interruptible = true;
3889 mutex_unlock(&dev->struct_mutex);
3892 /* Let userspace switch the overlay on again. In most cases userspace
3893 * has to recompute where to put it anyway.
3898 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3899 * cursor plane briefly if not already running after enabling the display
3901 * This workaround avoids occasional blank screens when self refresh is
3905 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3907 u32 cntl = I915_READ(CURCNTR(pipe));
3909 if ((cntl & CURSOR_MODE) == 0) {
3910 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3912 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3913 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3914 intel_wait_for_vblank(dev_priv->dev, pipe);
3915 I915_WRITE(CURCNTR(pipe), cntl);
3916 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3917 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3921 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3923 struct drm_device *dev = crtc->base.dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct intel_crtc_config *pipe_config = &crtc->config;
3927 if (!crtc->config.gmch_pfit.control)
3931 * The panel fitter should only be adjusted whilst the pipe is disabled,
3932 * according to register description and PRM.
3934 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3935 assert_pipe_disabled(dev_priv, crtc->pipe);
3937 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3938 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3940 /* Border color in case we don't scale up to the full screen. Black by
3941 * default, change to something else for debugging. */
3942 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3945 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3947 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3949 /* Obtain SKU information */
3950 mutex_lock(&dev_priv->dpio_lock);
3951 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3952 CCK_FUSE_HPLL_FREQ_MASK;
3953 mutex_unlock(&dev_priv->dpio_lock);
3955 return vco_freq[hpll_freq];
3958 /* Adjust CDclk dividers to allow high res or save power if possible */
3959 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3964 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3966 else if (cdclk == 266)
3971 mutex_lock(&dev_priv->rps.hw_lock);
3972 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3973 val &= ~DSPFREQGUAR_MASK;
3974 val |= (cmd << DSPFREQGUAR_SHIFT);
3975 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3976 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3977 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3979 DRM_ERROR("timed out waiting for CDclk change\n");
3981 mutex_unlock(&dev_priv->rps.hw_lock);
3986 vco = valleyview_get_vco(dev_priv);
3987 divider = ((vco << 1) / cdclk) - 1;
3989 mutex_lock(&dev_priv->dpio_lock);
3990 /* adjust cdclk divider */
3991 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3994 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3995 mutex_unlock(&dev_priv->dpio_lock);
3998 mutex_lock(&dev_priv->dpio_lock);
3999 /* adjust self-refresh exit latency value */
4000 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4004 * For high bandwidth configs, we set a higher latency in the bunit
4005 * so that the core display fetch happens in time to avoid underruns.
4008 val |= 4500 / 250; /* 4.5 usec */
4010 val |= 3000 / 250; /* 3.0 usec */
4011 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4012 mutex_unlock(&dev_priv->dpio_lock);
4014 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4015 intel_i2c_reset(dev);
4018 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4023 vco = valleyview_get_vco(dev_priv);
4025 mutex_lock(&dev_priv->dpio_lock);
4026 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4027 mutex_unlock(&dev_priv->dpio_lock);
4031 cur_cdclk = (vco << 1) / (divider + 1);
4036 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4041 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4044 * Really only a few cases to deal with, as only 4 CDclks are supported:
4049 * So we check to see whether we're above 90% of the lower bin and
4052 if (max_pixclk > 288000) {
4054 } else if (max_pixclk > 240000) {
4058 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4061 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4062 unsigned modeset_pipes,
4063 struct intel_crtc_config *pipe_config)
4065 struct drm_device *dev = dev_priv->dev;
4066 struct intel_crtc *intel_crtc;
4069 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4071 if (modeset_pipes & (1 << intel_crtc->pipe))
4072 max_pixclk = max(max_pixclk,
4073 pipe_config->adjusted_mode.crtc_clock);
4074 else if (intel_crtc->base.enabled)
4075 max_pixclk = max(max_pixclk,
4076 intel_crtc->config.adjusted_mode.crtc_clock);
4082 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4083 unsigned *prepare_pipes,
4084 unsigned modeset_pipes,
4085 struct intel_crtc_config *pipe_config)
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc;
4089 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4091 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4093 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4096 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4098 if (intel_crtc->base.enabled)
4099 *prepare_pipes |= (1 << intel_crtc->pipe);
4102 static void valleyview_modeset_global_resources(struct drm_device *dev)
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4106 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4107 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4109 if (req_cdclk != cur_cdclk)
4110 valleyview_set_cdclk(dev, req_cdclk);
4113 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4115 struct drm_device *dev = crtc->dev;
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4118 struct intel_encoder *encoder;
4119 int pipe = intel_crtc->pipe;
4120 int plane = intel_crtc->plane;
4123 WARN_ON(!crtc->enabled);
4125 if (intel_crtc->active)
4128 intel_crtc->active = true;
4130 for_each_encoder_on_crtc(dev, crtc, encoder)
4131 if (encoder->pre_pll_enable)
4132 encoder->pre_pll_enable(encoder);
4134 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4137 vlv_enable_pll(intel_crtc);
4139 for_each_encoder_on_crtc(dev, crtc, encoder)
4140 if (encoder->pre_enable)
4141 encoder->pre_enable(encoder);
4143 i9xx_pfit_enable(intel_crtc);
4145 intel_crtc_load_lut(crtc);
4147 intel_update_watermarks(crtc);
4148 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4149 intel_enable_primary_plane(dev_priv, plane, pipe);
4150 intel_enable_planes(crtc);
4151 intel_crtc_update_cursor(crtc, true);
4153 intel_update_fbc(dev);
4155 for_each_encoder_on_crtc(dev, crtc, encoder)
4156 encoder->enable(encoder);
4159 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4161 struct drm_device *dev = crtc->dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4164 struct intel_encoder *encoder;
4165 int pipe = intel_crtc->pipe;
4166 int plane = intel_crtc->plane;
4168 WARN_ON(!crtc->enabled);
4170 if (intel_crtc->active)
4173 intel_crtc->active = true;
4175 for_each_encoder_on_crtc(dev, crtc, encoder)
4176 if (encoder->pre_enable)
4177 encoder->pre_enable(encoder);
4179 i9xx_enable_pll(intel_crtc);
4181 i9xx_pfit_enable(intel_crtc);
4183 intel_crtc_load_lut(crtc);
4185 intel_update_watermarks(crtc);
4186 intel_enable_pipe(dev_priv, pipe, false, false);
4187 intel_enable_primary_plane(dev_priv, plane, pipe);
4188 intel_enable_planes(crtc);
4189 /* The fixup needs to happen before cursor is enabled */
4191 g4x_fixup_plane(dev_priv, pipe);
4192 intel_crtc_update_cursor(crtc, true);
4194 /* Give the overlay scaler a chance to enable if it's on this pipe */
4195 intel_crtc_dpms_overlay(intel_crtc, true);
4197 intel_update_fbc(dev);
4199 for_each_encoder_on_crtc(dev, crtc, encoder)
4200 encoder->enable(encoder);
4203 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4205 struct drm_device *dev = crtc->base.dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4208 if (!crtc->config.gmch_pfit.control)
4211 assert_pipe_disabled(dev_priv, crtc->pipe);
4213 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4214 I915_READ(PFIT_CONTROL));
4215 I915_WRITE(PFIT_CONTROL, 0);
4218 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223 struct intel_encoder *encoder;
4224 int pipe = intel_crtc->pipe;
4225 int plane = intel_crtc->plane;
4227 if (!intel_crtc->active)
4230 for_each_encoder_on_crtc(dev, crtc, encoder)
4231 encoder->disable(encoder);
4233 /* Give the overlay scaler a chance to disable if it's on this pipe */
4234 intel_crtc_wait_for_pending_flips(crtc);
4235 drm_vblank_off(dev, pipe);
4237 if (dev_priv->fbc.plane == plane)
4238 intel_disable_fbc(dev);
4240 intel_crtc_dpms_overlay(intel_crtc, false);
4241 intel_crtc_update_cursor(crtc, false);
4242 intel_disable_planes(crtc);
4243 intel_disable_primary_plane(dev_priv, plane, pipe);
4245 intel_disable_pipe(dev_priv, pipe);
4247 i9xx_pfit_disable(intel_crtc);
4249 for_each_encoder_on_crtc(dev, crtc, encoder)
4250 if (encoder->post_disable)
4251 encoder->post_disable(encoder);
4253 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4254 vlv_disable_pll(dev_priv, pipe);
4255 else if (!IS_VALLEYVIEW(dev))
4256 i9xx_disable_pll(dev_priv, pipe);
4258 intel_crtc->active = false;
4259 intel_update_watermarks(crtc);
4261 intel_update_fbc(dev);
4264 static void i9xx_crtc_off(struct drm_crtc *crtc)
4268 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4271 struct drm_device *dev = crtc->dev;
4272 struct drm_i915_master_private *master_priv;
4273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4274 int pipe = intel_crtc->pipe;
4276 if (!dev->primary->master)
4279 master_priv = dev->primary->master->driver_priv;
4280 if (!master_priv->sarea_priv)
4285 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4286 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4289 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4290 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4293 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4299 * Sets the power management mode of the pipe and plane.
4301 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4303 struct drm_device *dev = crtc->dev;
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 struct intel_encoder *intel_encoder;
4306 bool enable = false;
4308 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4309 enable |= intel_encoder->connectors_active;
4312 dev_priv->display.crtc_enable(crtc);
4314 dev_priv->display.crtc_disable(crtc);
4316 intel_crtc_update_sarea(crtc, enable);
4319 static void intel_crtc_disable(struct drm_crtc *crtc)
4321 struct drm_device *dev = crtc->dev;
4322 struct drm_connector *connector;
4323 struct drm_i915_private *dev_priv = dev->dev_private;
4324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326 /* crtc should still be enabled when we disable it. */
4327 WARN_ON(!crtc->enabled);
4329 dev_priv->display.crtc_disable(crtc);
4330 intel_crtc->eld_vld = false;
4331 intel_crtc_update_sarea(crtc, false);
4332 dev_priv->display.off(crtc);
4334 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4335 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4336 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4339 mutex_lock(&dev->struct_mutex);
4340 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4341 mutex_unlock(&dev->struct_mutex);
4345 /* Update computed state. */
4346 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4347 if (!connector->encoder || !connector->encoder->crtc)
4350 if (connector->encoder->crtc != crtc)
4353 connector->dpms = DRM_MODE_DPMS_OFF;
4354 to_intel_encoder(connector->encoder)->connectors_active = false;
4358 void intel_encoder_destroy(struct drm_encoder *encoder)
4360 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4362 drm_encoder_cleanup(encoder);
4363 kfree(intel_encoder);
4366 /* Simple dpms helper for encoders with just one connector, no cloning and only
4367 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4368 * state of the entire output pipe. */
4369 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4371 if (mode == DRM_MODE_DPMS_ON) {
4372 encoder->connectors_active = true;
4374 intel_crtc_update_dpms(encoder->base.crtc);
4376 encoder->connectors_active = false;
4378 intel_crtc_update_dpms(encoder->base.crtc);
4382 /* Cross check the actual hw state with our own modeset state tracking (and it's
4383 * internal consistency). */
4384 static void intel_connector_check_state(struct intel_connector *connector)
4386 if (connector->get_hw_state(connector)) {
4387 struct intel_encoder *encoder = connector->encoder;
4388 struct drm_crtc *crtc;
4389 bool encoder_enabled;
4392 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4393 connector->base.base.id,
4394 drm_get_connector_name(&connector->base));
4396 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4397 "wrong connector dpms state\n");
4398 WARN(connector->base.encoder != &encoder->base,
4399 "active connector not linked to encoder\n");
4400 WARN(!encoder->connectors_active,
4401 "encoder->connectors_active not set\n");
4403 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4404 WARN(!encoder_enabled, "encoder not enabled\n");
4405 if (WARN_ON(!encoder->base.crtc))
4408 crtc = encoder->base.crtc;
4410 WARN(!crtc->enabled, "crtc not enabled\n");
4411 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4412 WARN(pipe != to_intel_crtc(crtc)->pipe,
4413 "encoder active on the wrong pipe\n");
4417 /* Even simpler default implementation, if there's really no special case to
4419 void intel_connector_dpms(struct drm_connector *connector, int mode)
4421 /* All the simple cases only support two dpms states. */
4422 if (mode != DRM_MODE_DPMS_ON)
4423 mode = DRM_MODE_DPMS_OFF;
4425 if (mode == connector->dpms)
4428 connector->dpms = mode;
4430 /* Only need to change hw state when actually enabled */
4431 if (connector->encoder)
4432 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4434 intel_modeset_check_state(connector->dev);
4437 /* Simple connector->get_hw_state implementation for encoders that support only
4438 * one connector and no cloning and hence the encoder state determines the state
4439 * of the connector. */
4440 bool intel_connector_get_hw_state(struct intel_connector *connector)
4443 struct intel_encoder *encoder = connector->encoder;
4445 return encoder->get_hw_state(encoder, &pipe);
4448 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4449 struct intel_crtc_config *pipe_config)
4451 struct drm_i915_private *dev_priv = dev->dev_private;
4452 struct intel_crtc *pipe_B_crtc =
4453 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4455 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4456 pipe_name(pipe), pipe_config->fdi_lanes);
4457 if (pipe_config->fdi_lanes > 4) {
4458 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4459 pipe_name(pipe), pipe_config->fdi_lanes);
4463 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4464 if (pipe_config->fdi_lanes > 2) {
4465 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4466 pipe_config->fdi_lanes);
4473 if (INTEL_INFO(dev)->num_pipes == 2)
4476 /* Ivybridge 3 pipe is really complicated */
4481 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4482 pipe_config->fdi_lanes > 2) {
4483 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4484 pipe_name(pipe), pipe_config->fdi_lanes);
4489 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4490 pipe_B_crtc->config.fdi_lanes <= 2) {
4491 if (pipe_config->fdi_lanes > 2) {
4492 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4493 pipe_name(pipe), pipe_config->fdi_lanes);
4497 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4507 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4508 struct intel_crtc_config *pipe_config)
4510 struct drm_device *dev = intel_crtc->base.dev;
4511 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4512 int lane, link_bw, fdi_dotclock;
4513 bool setup_ok, needs_recompute = false;
4516 /* FDI is a binary signal running at ~2.7GHz, encoding
4517 * each output octet as 10 bits. The actual frequency
4518 * is stored as a divider into a 100MHz clock, and the
4519 * mode pixel clock is stored in units of 1KHz.
4520 * Hence the bw of each lane in terms of the mode signal
4523 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4525 fdi_dotclock = adjusted_mode->crtc_clock;
4527 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4528 pipe_config->pipe_bpp);
4530 pipe_config->fdi_lanes = lane;
4532 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4533 link_bw, &pipe_config->fdi_m_n);
4535 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4536 intel_crtc->pipe, pipe_config);
4537 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4538 pipe_config->pipe_bpp -= 2*3;
4539 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4540 pipe_config->pipe_bpp);
4541 needs_recompute = true;
4542 pipe_config->bw_constrained = true;
4547 if (needs_recompute)
4550 return setup_ok ? 0 : -EINVAL;
4553 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4554 struct intel_crtc_config *pipe_config)
4556 pipe_config->ips_enabled = i915_enable_ips &&
4557 hsw_crtc_supports_ips(crtc) &&
4558 pipe_config->pipe_bpp <= 24;
4561 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4562 struct intel_crtc_config *pipe_config)
4564 struct drm_device *dev = crtc->base.dev;
4565 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4567 /* FIXME should check pixel clock limits on all platforms */
4568 if (INTEL_INFO(dev)->gen < 4) {
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4571 dev_priv->display.get_display_clock_speed(dev);
4574 * Enable pixel doubling when the dot clock
4575 * is > 90% of the (display) core speed.
4577 * GDG double wide on either pipe,
4578 * otherwise pipe A only.
4580 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4581 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4583 pipe_config->double_wide = true;
4586 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4591 * Pipe horizontal size must be even in:
4593 * - LVDS dual channel mode
4594 * - Double wide pipe
4596 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4597 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4598 pipe_config->pipe_src_w &= ~1;
4600 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4601 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4603 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4604 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4607 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4608 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4609 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4610 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4612 pipe_config->pipe_bpp = 8*3;
4616 hsw_compute_ips_config(crtc, pipe_config);
4618 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4619 * clock survives for now. */
4620 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4621 pipe_config->shared_dpll = crtc->config.shared_dpll;
4623 if (pipe_config->has_pch_encoder)
4624 return ironlake_fdi_compute_config(crtc, pipe_config);
4629 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4631 return 400000; /* FIXME */
4634 static int i945_get_display_clock_speed(struct drm_device *dev)
4639 static int i915_get_display_clock_speed(struct drm_device *dev)
4644 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4649 static int pnv_get_display_clock_speed(struct drm_device *dev)
4653 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4655 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4656 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4658 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4660 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4662 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4665 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4666 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4668 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4673 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4677 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4679 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4682 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4683 case GC_DISPLAY_CLOCK_333_MHZ:
4686 case GC_DISPLAY_CLOCK_190_200_MHZ:
4692 static int i865_get_display_clock_speed(struct drm_device *dev)
4697 static int i855_get_display_clock_speed(struct drm_device *dev)
4700 /* Assume that the hardware is in the high speed state. This
4701 * should be the default.
4703 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4704 case GC_CLOCK_133_200:
4705 case GC_CLOCK_100_200:
4707 case GC_CLOCK_166_250:
4709 case GC_CLOCK_100_133:
4713 /* Shouldn't happen */
4717 static int i830_get_display_clock_speed(struct drm_device *dev)
4723 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4725 while (*num > DATA_LINK_M_N_MASK ||
4726 *den > DATA_LINK_M_N_MASK) {
4732 static void compute_m_n(unsigned int m, unsigned int n,
4733 uint32_t *ret_m, uint32_t *ret_n)
4735 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4736 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4737 intel_reduce_m_n_ratio(ret_m, ret_n);
4741 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4742 int pixel_clock, int link_clock,
4743 struct intel_link_m_n *m_n)
4747 compute_m_n(bits_per_pixel * pixel_clock,
4748 link_clock * nlanes * 8,
4749 &m_n->gmch_m, &m_n->gmch_n);
4751 compute_m_n(pixel_clock, link_clock,
4752 &m_n->link_m, &m_n->link_n);
4755 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4757 if (i915_panel_use_ssc >= 0)
4758 return i915_panel_use_ssc != 0;
4759 return dev_priv->vbt.lvds_use_ssc
4760 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4763 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4769 if (IS_VALLEYVIEW(dev)) {
4771 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4772 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4773 refclk = dev_priv->vbt.lvds_ssc_freq;
4774 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4775 } else if (!IS_GEN2(dev)) {
4784 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4786 return (1 << dpll->n) << 16 | dpll->m2;
4789 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4791 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4794 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4795 intel_clock_t *reduced_clock)
4797 struct drm_device *dev = crtc->base.dev;
4798 struct drm_i915_private *dev_priv = dev->dev_private;
4799 int pipe = crtc->pipe;
4802 if (IS_PINEVIEW(dev)) {
4803 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4805 fp2 = pnv_dpll_compute_fp(reduced_clock);
4807 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4809 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4812 I915_WRITE(FP0(pipe), fp);
4813 crtc->config.dpll_hw_state.fp0 = fp;
4815 crtc->lowfreq_avail = false;
4816 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4817 reduced_clock && i915_powersave) {
4818 I915_WRITE(FP1(pipe), fp2);
4819 crtc->config.dpll_hw_state.fp1 = fp2;
4820 crtc->lowfreq_avail = true;
4822 I915_WRITE(FP1(pipe), fp);
4823 crtc->config.dpll_hw_state.fp1 = fp;
4827 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4833 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4834 * and set it to a reasonable value instead.
4836 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4837 reg_val &= 0xffffff00;
4838 reg_val |= 0x00000030;
4839 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4841 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4842 reg_val &= 0x8cffffff;
4843 reg_val = 0x8c000000;
4844 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4846 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4847 reg_val &= 0xffffff00;
4848 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4850 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4851 reg_val &= 0x00ffffff;
4852 reg_val |= 0xb0000000;
4853 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4856 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4857 struct intel_link_m_n *m_n)
4859 struct drm_device *dev = crtc->base.dev;
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 int pipe = crtc->pipe;
4863 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4864 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4865 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4866 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4869 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4870 struct intel_link_m_n *m_n)
4872 struct drm_device *dev = crtc->base.dev;
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 int pipe = crtc->pipe;
4875 enum transcoder transcoder = crtc->config.cpu_transcoder;
4877 if (INTEL_INFO(dev)->gen >= 5) {
4878 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4879 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4880 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4881 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4883 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4884 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4885 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4886 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4890 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4892 if (crtc->config.has_pch_encoder)
4893 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4895 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4898 static void vlv_update_pll(struct intel_crtc *crtc)
4900 struct drm_device *dev = crtc->base.dev;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 int pipe = crtc->pipe;
4904 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4905 u32 coreclk, reg_val, dpll_md;
4907 mutex_lock(&dev_priv->dpio_lock);
4909 bestn = crtc->config.dpll.n;
4910 bestm1 = crtc->config.dpll.m1;
4911 bestm2 = crtc->config.dpll.m2;
4912 bestp1 = crtc->config.dpll.p1;
4913 bestp2 = crtc->config.dpll.p2;
4915 /* See eDP HDMI DPIO driver vbios notes doc */
4917 /* PLL B needs special handling */
4919 vlv_pllb_recal_opamp(dev_priv, pipe);
4921 /* Set up Tx target for periodic Rcomp update */
4922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4924 /* Disable target IRef on PLL */
4925 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4926 reg_val &= 0x00ffffff;
4927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4929 /* Disable fast lock */
4930 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4932 /* Set idtafcrecal before PLL is enabled */
4933 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4934 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4935 mdiv |= ((bestn << DPIO_N_SHIFT));
4936 mdiv |= (1 << DPIO_K_SHIFT);
4939 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4940 * but we don't support that).
4941 * Note: don't use the DAC post divider as it seems unstable.
4943 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4946 mdiv |= DPIO_ENABLE_CALIBRATION;
4947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4949 /* Set HBR and RBR LPF coefficients */
4950 if (crtc->config.port_clock == 162000 ||
4951 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4952 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4959 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4960 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4961 /* Use SSC source */
4963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4968 } else { /* HDMI or VGA */
4969 /* Use bend source */
4971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4978 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4979 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4980 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4981 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4982 coreclk |= 0x01000000;
4983 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4987 /* Enable DPIO clock input */
4988 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4989 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4990 /* We should never disable this, set it here for state tracking */
4992 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4993 dpll |= DPLL_VCO_ENABLE;
4994 crtc->config.dpll_hw_state.dpll = dpll;
4996 dpll_md = (crtc->config.pixel_multiplier - 1)
4997 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4998 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5000 if (crtc->config.has_dp_encoder)
5001 intel_dp_set_m_n(crtc);
5003 mutex_unlock(&dev_priv->dpio_lock);
5006 static void i9xx_update_pll(struct intel_crtc *crtc,
5007 intel_clock_t *reduced_clock,
5010 struct drm_device *dev = crtc->base.dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5014 struct dpll *clock = &crtc->config.dpll;
5016 i9xx_update_pll_dividers(crtc, reduced_clock);
5018 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5019 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5021 dpll = DPLL_VGA_MODE_DIS;
5023 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5024 dpll |= DPLLB_MODE_LVDS;
5026 dpll |= DPLLB_MODE_DAC_SERIAL;
5028 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5029 dpll |= (crtc->config.pixel_multiplier - 1)
5030 << SDVO_MULTIPLIER_SHIFT_HIRES;
5034 dpll |= DPLL_SDVO_HIGH_SPEED;
5036 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5037 dpll |= DPLL_SDVO_HIGH_SPEED;
5039 /* compute bitmask from p1 value */
5040 if (IS_PINEVIEW(dev))
5041 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5043 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5044 if (IS_G4X(dev) && reduced_clock)
5045 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5047 switch (clock->p2) {
5049 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5052 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5055 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5058 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5061 if (INTEL_INFO(dev)->gen >= 4)
5062 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5064 if (crtc->config.sdvo_tv_clock)
5065 dpll |= PLL_REF_INPUT_TVCLKINBC;
5066 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5067 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5068 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5070 dpll |= PLL_REF_INPUT_DREFCLK;
5072 dpll |= DPLL_VCO_ENABLE;
5073 crtc->config.dpll_hw_state.dpll = dpll;
5075 if (INTEL_INFO(dev)->gen >= 4) {
5076 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5077 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5078 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5081 if (crtc->config.has_dp_encoder)
5082 intel_dp_set_m_n(crtc);
5085 static void i8xx_update_pll(struct intel_crtc *crtc,
5086 intel_clock_t *reduced_clock,
5089 struct drm_device *dev = crtc->base.dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5092 struct dpll *clock = &crtc->config.dpll;
5094 i9xx_update_pll_dividers(crtc, reduced_clock);
5096 dpll = DPLL_VGA_MODE_DIS;
5098 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5099 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5102 dpll |= PLL_P1_DIVIDE_BY_TWO;
5104 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5106 dpll |= PLL_P2_DIVIDE_BY_4;
5109 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5110 dpll |= DPLL_DVO_2X_MODE;
5112 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5113 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5114 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5116 dpll |= PLL_REF_INPUT_DREFCLK;
5118 dpll |= DPLL_VCO_ENABLE;
5119 crtc->config.dpll_hw_state.dpll = dpll;
5122 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5124 struct drm_device *dev = intel_crtc->base.dev;
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126 enum pipe pipe = intel_crtc->pipe;
5127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5128 struct drm_display_mode *adjusted_mode =
5129 &intel_crtc->config.adjusted_mode;
5130 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5132 /* We need to be careful not to changed the adjusted mode, for otherwise
5133 * the hw state checker will get angry at the mismatch. */
5134 crtc_vtotal = adjusted_mode->crtc_vtotal;
5135 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5137 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5138 /* the chip adds 2 halflines automatically */
5140 crtc_vblank_end -= 1;
5141 vsyncshift = adjusted_mode->crtc_hsync_start
5142 - adjusted_mode->crtc_htotal / 2;
5147 if (INTEL_INFO(dev)->gen > 3)
5148 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5150 I915_WRITE(HTOTAL(cpu_transcoder),
5151 (adjusted_mode->crtc_hdisplay - 1) |
5152 ((adjusted_mode->crtc_htotal - 1) << 16));
5153 I915_WRITE(HBLANK(cpu_transcoder),
5154 (adjusted_mode->crtc_hblank_start - 1) |
5155 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5156 I915_WRITE(HSYNC(cpu_transcoder),
5157 (adjusted_mode->crtc_hsync_start - 1) |
5158 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5160 I915_WRITE(VTOTAL(cpu_transcoder),
5161 (adjusted_mode->crtc_vdisplay - 1) |
5162 ((crtc_vtotal - 1) << 16));
5163 I915_WRITE(VBLANK(cpu_transcoder),
5164 (adjusted_mode->crtc_vblank_start - 1) |
5165 ((crtc_vblank_end - 1) << 16));
5166 I915_WRITE(VSYNC(cpu_transcoder),
5167 (adjusted_mode->crtc_vsync_start - 1) |
5168 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5170 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5171 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5172 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5174 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5175 (pipe == PIPE_B || pipe == PIPE_C))
5176 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5178 /* pipesrc controls the size that is scaled from, which should
5179 * always be the user's requested size.
5181 I915_WRITE(PIPESRC(pipe),
5182 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5183 (intel_crtc->config.pipe_src_h - 1));
5186 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5187 struct intel_crtc_config *pipe_config)
5189 struct drm_device *dev = crtc->base.dev;
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5194 tmp = I915_READ(HTOTAL(cpu_transcoder));
5195 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5196 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5197 tmp = I915_READ(HBLANK(cpu_transcoder));
5198 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5199 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5200 tmp = I915_READ(HSYNC(cpu_transcoder));
5201 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5202 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5204 tmp = I915_READ(VTOTAL(cpu_transcoder));
5205 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5206 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5207 tmp = I915_READ(VBLANK(cpu_transcoder));
5208 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5209 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5210 tmp = I915_READ(VSYNC(cpu_transcoder));
5211 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5212 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5214 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5215 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5216 pipe_config->adjusted_mode.crtc_vtotal += 1;
5217 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5220 tmp = I915_READ(PIPESRC(crtc->pipe));
5221 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5222 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5224 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5225 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5228 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5229 struct intel_crtc_config *pipe_config)
5231 struct drm_crtc *crtc = &intel_crtc->base;
5233 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5234 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5235 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5236 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5238 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5239 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5240 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5241 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5243 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5245 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5246 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5249 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5251 struct drm_device *dev = intel_crtc->base.dev;
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5257 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5258 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5259 pipeconf |= PIPECONF_ENABLE;
5261 if (intel_crtc->config.double_wide)
5262 pipeconf |= PIPECONF_DOUBLE_WIDE;
5264 /* only g4x and later have fancy bpc/dither controls */
5265 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5266 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5267 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5268 pipeconf |= PIPECONF_DITHER_EN |
5269 PIPECONF_DITHER_TYPE_SP;
5271 switch (intel_crtc->config.pipe_bpp) {
5273 pipeconf |= PIPECONF_6BPC;
5276 pipeconf |= PIPECONF_8BPC;
5279 pipeconf |= PIPECONF_10BPC;
5282 /* Case prevented by intel_choose_pipe_bpp_dither. */
5287 if (HAS_PIPE_CXSR(dev)) {
5288 if (intel_crtc->lowfreq_avail) {
5289 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5290 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5292 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5296 if (!IS_GEN2(dev) &&
5297 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5298 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5300 pipeconf |= PIPECONF_PROGRESSIVE;
5302 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5303 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5305 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5306 POSTING_READ(PIPECONF(intel_crtc->pipe));
5309 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5311 struct drm_framebuffer *fb)
5313 struct drm_device *dev = crtc->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5316 int pipe = intel_crtc->pipe;
5317 int plane = intel_crtc->plane;
5318 int refclk, num_connectors = 0;
5319 intel_clock_t clock, reduced_clock;
5321 bool ok, has_reduced_clock = false;
5322 bool is_lvds = false, is_dsi = false;
5323 struct intel_encoder *encoder;
5324 const intel_limit_t *limit;
5327 for_each_encoder_on_crtc(dev, crtc, encoder) {
5328 switch (encoder->type) {
5329 case INTEL_OUTPUT_LVDS:
5332 case INTEL_OUTPUT_DSI:
5343 if (!intel_crtc->config.clock_set) {
5344 refclk = i9xx_get_refclk(crtc, num_connectors);
5347 * Returns a set of divisors for the desired target clock with
5348 * the given refclk, or FALSE. The returned values represent
5349 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5352 limit = intel_limit(crtc, refclk);
5353 ok = dev_priv->display.find_dpll(limit, crtc,
5354 intel_crtc->config.port_clock,
5355 refclk, NULL, &clock);
5357 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5361 if (is_lvds && dev_priv->lvds_downclock_avail) {
5363 * Ensure we match the reduced clock's P to the target
5364 * clock. If the clocks don't match, we can't switch
5365 * the display clock by using the FP0/FP1. In such case
5366 * we will disable the LVDS downclock feature.
5369 dev_priv->display.find_dpll(limit, crtc,
5370 dev_priv->lvds_downclock,
5374 /* Compat-code for transition, will disappear. */
5375 intel_crtc->config.dpll.n = clock.n;
5376 intel_crtc->config.dpll.m1 = clock.m1;
5377 intel_crtc->config.dpll.m2 = clock.m2;
5378 intel_crtc->config.dpll.p1 = clock.p1;
5379 intel_crtc->config.dpll.p2 = clock.p2;
5383 i8xx_update_pll(intel_crtc,
5384 has_reduced_clock ? &reduced_clock : NULL,
5386 } else if (IS_VALLEYVIEW(dev)) {
5387 vlv_update_pll(intel_crtc);
5389 i9xx_update_pll(intel_crtc,
5390 has_reduced_clock ? &reduced_clock : NULL,
5395 /* Set up the display plane register */
5396 dspcntr = DISPPLANE_GAMMA_ENABLE;
5398 if (!IS_VALLEYVIEW(dev)) {
5400 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5402 dspcntr |= DISPPLANE_SEL_PIPE_B;
5405 intel_set_pipe_timings(intel_crtc);
5407 /* pipesrc and dspsize control the size that is scaled from,
5408 * which should always be the user's requested size.
5410 I915_WRITE(DSPSIZE(plane),
5411 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5412 (intel_crtc->config.pipe_src_w - 1));
5413 I915_WRITE(DSPPOS(plane), 0);
5415 i9xx_set_pipeconf(intel_crtc);
5417 I915_WRITE(DSPCNTR(plane), dspcntr);
5418 POSTING_READ(DSPCNTR(plane));
5420 ret = intel_pipe_set_base(crtc, x, y, fb);
5425 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5426 struct intel_crtc_config *pipe_config)
5428 struct drm_device *dev = crtc->base.dev;
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5432 tmp = I915_READ(PFIT_CONTROL);
5433 if (!(tmp & PFIT_ENABLE))
5436 /* Check whether the pfit is attached to our pipe. */
5437 if (INTEL_INFO(dev)->gen < 4) {
5438 if (crtc->pipe != PIPE_B)
5441 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5445 pipe_config->gmch_pfit.control = tmp;
5446 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5447 if (INTEL_INFO(dev)->gen < 5)
5448 pipe_config->gmch_pfit.lvds_border_bits =
5449 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5452 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5453 struct intel_crtc_config *pipe_config)
5455 struct drm_device *dev = crtc->base.dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 int pipe = pipe_config->cpu_transcoder;
5458 intel_clock_t clock;
5460 int refclk = 100000;
5462 mutex_lock(&dev_priv->dpio_lock);
5463 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5464 mutex_unlock(&dev_priv->dpio_lock);
5466 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5467 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5468 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5469 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5470 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5472 vlv_clock(refclk, &clock);
5474 /* clock.dot is the fast clock */
5475 pipe_config->port_clock = clock.dot / 5;
5478 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5479 struct intel_crtc_config *pipe_config)
5481 struct drm_device *dev = crtc->base.dev;
5482 struct drm_i915_private *dev_priv = dev->dev_private;
5485 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5486 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5488 tmp = I915_READ(PIPECONF(crtc->pipe));
5489 if (!(tmp & PIPECONF_ENABLE))
5492 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5493 switch (tmp & PIPECONF_BPC_MASK) {
5495 pipe_config->pipe_bpp = 18;
5498 pipe_config->pipe_bpp = 24;
5500 case PIPECONF_10BPC:
5501 pipe_config->pipe_bpp = 30;
5508 if (INTEL_INFO(dev)->gen < 4)
5509 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5511 intel_get_pipe_timings(crtc, pipe_config);
5513 i9xx_get_pfit_config(crtc, pipe_config);
5515 if (INTEL_INFO(dev)->gen >= 4) {
5516 tmp = I915_READ(DPLL_MD(crtc->pipe));
5517 pipe_config->pixel_multiplier =
5518 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5519 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5520 pipe_config->dpll_hw_state.dpll_md = tmp;
5521 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5522 tmp = I915_READ(DPLL(crtc->pipe));
5523 pipe_config->pixel_multiplier =
5524 ((tmp & SDVO_MULTIPLIER_MASK)
5525 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5527 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5528 * port and will be fixed up in the encoder->get_config
5530 pipe_config->pixel_multiplier = 1;
5532 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5533 if (!IS_VALLEYVIEW(dev)) {
5534 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5535 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5537 /* Mask out read-only status bits. */
5538 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5539 DPLL_PORTC_READY_MASK |
5540 DPLL_PORTB_READY_MASK);
5543 if (IS_VALLEYVIEW(dev))
5544 vlv_crtc_clock_get(crtc, pipe_config);
5546 i9xx_crtc_clock_get(crtc, pipe_config);
5551 static void ironlake_init_pch_refclk(struct drm_device *dev)
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct drm_mode_config *mode_config = &dev->mode_config;
5555 struct intel_encoder *encoder;
5557 bool has_lvds = false;
5558 bool has_cpu_edp = false;
5559 bool has_panel = false;
5560 bool has_ck505 = false;
5561 bool can_ssc = false;
5563 /* We need to take the global config into account */
5564 list_for_each_entry(encoder, &mode_config->encoder_list,
5566 switch (encoder->type) {
5567 case INTEL_OUTPUT_LVDS:
5571 case INTEL_OUTPUT_EDP:
5573 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5579 if (HAS_PCH_IBX(dev)) {
5580 has_ck505 = dev_priv->vbt.display_clock_mode;
5581 can_ssc = has_ck505;
5587 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5588 has_panel, has_lvds, has_ck505);
5590 /* Ironlake: try to setup display ref clock before DPLL
5591 * enabling. This is only under driver's control after
5592 * PCH B stepping, previous chipset stepping should be
5593 * ignoring this setting.
5595 val = I915_READ(PCH_DREF_CONTROL);
5597 /* As we must carefully and slowly disable/enable each source in turn,
5598 * compute the final state we want first and check if we need to
5599 * make any changes at all.
5602 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5604 final |= DREF_NONSPREAD_CK505_ENABLE;
5606 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5608 final &= ~DREF_SSC_SOURCE_MASK;
5609 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5610 final &= ~DREF_SSC1_ENABLE;
5613 final |= DREF_SSC_SOURCE_ENABLE;
5615 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5616 final |= DREF_SSC1_ENABLE;
5619 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5620 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5622 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5624 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5626 final |= DREF_SSC_SOURCE_DISABLE;
5627 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5633 /* Always enable nonspread source */
5634 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5637 val |= DREF_NONSPREAD_CK505_ENABLE;
5639 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5642 val &= ~DREF_SSC_SOURCE_MASK;
5643 val |= DREF_SSC_SOURCE_ENABLE;
5645 /* SSC must be turned on before enabling the CPU output */
5646 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5647 DRM_DEBUG_KMS("Using SSC on panel\n");
5648 val |= DREF_SSC1_ENABLE;
5650 val &= ~DREF_SSC1_ENABLE;
5652 /* Get SSC going before enabling the outputs */
5653 I915_WRITE(PCH_DREF_CONTROL, val);
5654 POSTING_READ(PCH_DREF_CONTROL);
5657 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5659 /* Enable CPU source on CPU attached eDP */
5661 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5662 DRM_DEBUG_KMS("Using SSC on eDP\n");
5663 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5666 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5668 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5670 I915_WRITE(PCH_DREF_CONTROL, val);
5671 POSTING_READ(PCH_DREF_CONTROL);
5674 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5676 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5678 /* Turn off CPU output */
5679 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5681 I915_WRITE(PCH_DREF_CONTROL, val);
5682 POSTING_READ(PCH_DREF_CONTROL);
5685 /* Turn off the SSC source */
5686 val &= ~DREF_SSC_SOURCE_MASK;
5687 val |= DREF_SSC_SOURCE_DISABLE;
5690 val &= ~DREF_SSC1_ENABLE;
5692 I915_WRITE(PCH_DREF_CONTROL, val);
5693 POSTING_READ(PCH_DREF_CONTROL);
5697 BUG_ON(val != final);
5700 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5704 tmp = I915_READ(SOUTH_CHICKEN2);
5705 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5706 I915_WRITE(SOUTH_CHICKEN2, tmp);
5708 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5709 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5710 DRM_ERROR("FDI mPHY reset assert timeout\n");
5712 tmp = I915_READ(SOUTH_CHICKEN2);
5713 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5714 I915_WRITE(SOUTH_CHICKEN2, tmp);
5716 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5717 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5718 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5721 /* WaMPhyProgramming:hsw */
5722 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5726 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5727 tmp &= ~(0xFF << 24);
5728 tmp |= (0x12 << 24);
5729 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5731 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5733 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5735 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5737 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5739 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5740 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5741 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5743 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5744 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5745 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5747 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5750 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5752 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5755 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5757 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5760 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5762 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5765 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5767 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5768 tmp &= ~(0xFF << 16);
5769 tmp |= (0x1C << 16);
5770 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5772 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5773 tmp &= ~(0xFF << 16);
5774 tmp |= (0x1C << 16);
5775 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5777 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5779 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5781 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5783 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5785 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5786 tmp &= ~(0xF << 28);
5788 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5790 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5791 tmp &= ~(0xF << 28);
5793 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5796 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5797 * Programming" based on the parameters passed:
5798 * - Sequence to enable CLKOUT_DP
5799 * - Sequence to enable CLKOUT_DP without spread
5800 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5802 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5805 struct drm_i915_private *dev_priv = dev->dev_private;
5808 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5810 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5811 with_fdi, "LP PCH doesn't have FDI\n"))
5814 mutex_lock(&dev_priv->dpio_lock);
5816 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5817 tmp &= ~SBI_SSCCTL_DISABLE;
5818 tmp |= SBI_SSCCTL_PATHALT;
5819 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5824 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5825 tmp &= ~SBI_SSCCTL_PATHALT;
5826 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5829 lpt_reset_fdi_mphy(dev_priv);
5830 lpt_program_fdi_mphy(dev_priv);
5834 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5835 SBI_GEN0 : SBI_DBUFF0;
5836 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5837 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5838 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5840 mutex_unlock(&dev_priv->dpio_lock);
5843 /* Sequence to disable CLKOUT_DP */
5844 static void lpt_disable_clkout_dp(struct drm_device *dev)
5846 struct drm_i915_private *dev_priv = dev->dev_private;
5849 mutex_lock(&dev_priv->dpio_lock);
5851 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5852 SBI_GEN0 : SBI_DBUFF0;
5853 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5854 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5855 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5857 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5858 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5859 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5860 tmp |= SBI_SSCCTL_PATHALT;
5861 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5864 tmp |= SBI_SSCCTL_DISABLE;
5865 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5868 mutex_unlock(&dev_priv->dpio_lock);
5871 static void lpt_init_pch_refclk(struct drm_device *dev)
5873 struct drm_mode_config *mode_config = &dev->mode_config;
5874 struct intel_encoder *encoder;
5875 bool has_vga = false;
5877 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5878 switch (encoder->type) {
5879 case INTEL_OUTPUT_ANALOG:
5886 lpt_enable_clkout_dp(dev, true, true);
5888 lpt_disable_clkout_dp(dev);
5892 * Initialize reference clocks when the driver loads
5894 void intel_init_pch_refclk(struct drm_device *dev)
5896 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5897 ironlake_init_pch_refclk(dev);
5898 else if (HAS_PCH_LPT(dev))
5899 lpt_init_pch_refclk(dev);
5902 static int ironlake_get_refclk(struct drm_crtc *crtc)
5904 struct drm_device *dev = crtc->dev;
5905 struct drm_i915_private *dev_priv = dev->dev_private;
5906 struct intel_encoder *encoder;
5907 int num_connectors = 0;
5908 bool is_lvds = false;
5910 for_each_encoder_on_crtc(dev, crtc, encoder) {
5911 switch (encoder->type) {
5912 case INTEL_OUTPUT_LVDS:
5919 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5920 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5921 dev_priv->vbt.lvds_ssc_freq);
5922 return dev_priv->vbt.lvds_ssc_freq;
5928 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5930 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5932 int pipe = intel_crtc->pipe;
5937 switch (intel_crtc->config.pipe_bpp) {
5939 val |= PIPECONF_6BPC;
5942 val |= PIPECONF_8BPC;
5945 val |= PIPECONF_10BPC;
5948 val |= PIPECONF_12BPC;
5951 /* Case prevented by intel_choose_pipe_bpp_dither. */
5955 if (intel_crtc->config.dither)
5956 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5958 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5959 val |= PIPECONF_INTERLACED_ILK;
5961 val |= PIPECONF_PROGRESSIVE;
5963 if (intel_crtc->config.limited_color_range)
5964 val |= PIPECONF_COLOR_RANGE_SELECT;
5966 I915_WRITE(PIPECONF(pipe), val);
5967 POSTING_READ(PIPECONF(pipe));
5971 * Set up the pipe CSC unit.
5973 * Currently only full range RGB to limited range RGB conversion
5974 * is supported, but eventually this should handle various
5975 * RGB<->YCbCr scenarios as well.
5977 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5979 struct drm_device *dev = crtc->dev;
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982 int pipe = intel_crtc->pipe;
5983 uint16_t coeff = 0x7800; /* 1.0 */
5986 * TODO: Check what kind of values actually come out of the pipe
5987 * with these coeff/postoff values and adjust to get the best
5988 * accuracy. Perhaps we even need to take the bpc value into
5992 if (intel_crtc->config.limited_color_range)
5993 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5996 * GY/GU and RY/RU should be the other way around according
5997 * to BSpec, but reality doesn't agree. Just set them up in
5998 * a way that results in the correct picture.
6000 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6001 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6003 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6004 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6006 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6007 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6009 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6010 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6011 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6013 if (INTEL_INFO(dev)->gen > 6) {
6014 uint16_t postoff = 0;
6016 if (intel_crtc->config.limited_color_range)
6017 postoff = (16 * (1 << 13) / 255) & 0x1fff;
6019 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6020 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6021 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6023 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6025 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6027 if (intel_crtc->config.limited_color_range)
6028 mode |= CSC_BLACK_SCREEN_OFFSET;
6030 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6034 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6036 struct drm_device *dev = crtc->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
6038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6039 enum pipe pipe = intel_crtc->pipe;
6040 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6045 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6046 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6048 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6049 val |= PIPECONF_INTERLACED_ILK;
6051 val |= PIPECONF_PROGRESSIVE;
6053 I915_WRITE(PIPECONF(cpu_transcoder), val);
6054 POSTING_READ(PIPECONF(cpu_transcoder));
6056 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6057 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6059 if (IS_BROADWELL(dev)) {
6062 switch (intel_crtc->config.pipe_bpp) {
6064 val |= PIPEMISC_DITHER_6_BPC;
6067 val |= PIPEMISC_DITHER_8_BPC;
6070 val |= PIPEMISC_DITHER_10_BPC;
6073 val |= PIPEMISC_DITHER_12_BPC;
6076 /* Case prevented by pipe_config_set_bpp. */
6080 if (intel_crtc->config.dither)
6081 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6083 I915_WRITE(PIPEMISC(pipe), val);
6087 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6088 intel_clock_t *clock,
6089 bool *has_reduced_clock,
6090 intel_clock_t *reduced_clock)
6092 struct drm_device *dev = crtc->dev;
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094 struct intel_encoder *intel_encoder;
6096 const intel_limit_t *limit;
6097 bool ret, is_lvds = false;
6099 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6100 switch (intel_encoder->type) {
6101 case INTEL_OUTPUT_LVDS:
6107 refclk = ironlake_get_refclk(crtc);
6110 * Returns a set of divisors for the desired target clock with the given
6111 * refclk, or FALSE. The returned values represent the clock equation:
6112 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6114 limit = intel_limit(crtc, refclk);
6115 ret = dev_priv->display.find_dpll(limit, crtc,
6116 to_intel_crtc(crtc)->config.port_clock,
6117 refclk, NULL, clock);
6121 if (is_lvds && dev_priv->lvds_downclock_avail) {
6123 * Ensure we match the reduced clock's P to the target clock.
6124 * If the clocks don't match, we can't switch the display clock
6125 * by using the FP0/FP1. In such case we will disable the LVDS
6126 * downclock feature.
6128 *has_reduced_clock =
6129 dev_priv->display.find_dpll(limit, crtc,
6130 dev_priv->lvds_downclock,
6138 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6141 * Account for spread spectrum to avoid
6142 * oversubscribing the link. Max center spread
6143 * is 2.5%; use 5% for safety's sake.
6145 u32 bps = target_clock * bpp * 21 / 20;
6146 return bps / (link_bw * 8) + 1;
6149 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6151 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6154 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6156 intel_clock_t *reduced_clock, u32 *fp2)
6158 struct drm_crtc *crtc = &intel_crtc->base;
6159 struct drm_device *dev = crtc->dev;
6160 struct drm_i915_private *dev_priv = dev->dev_private;
6161 struct intel_encoder *intel_encoder;
6163 int factor, num_connectors = 0;
6164 bool is_lvds = false, is_sdvo = false;
6166 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6167 switch (intel_encoder->type) {
6168 case INTEL_OUTPUT_LVDS:
6171 case INTEL_OUTPUT_SDVO:
6172 case INTEL_OUTPUT_HDMI:
6180 /* Enable autotuning of the PLL clock (if permissible) */
6183 if ((intel_panel_use_ssc(dev_priv) &&
6184 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6185 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6187 } else if (intel_crtc->config.sdvo_tv_clock)
6190 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6193 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6199 dpll |= DPLLB_MODE_LVDS;
6201 dpll |= DPLLB_MODE_DAC_SERIAL;
6203 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6204 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6207 dpll |= DPLL_SDVO_HIGH_SPEED;
6208 if (intel_crtc->config.has_dp_encoder)
6209 dpll |= DPLL_SDVO_HIGH_SPEED;
6211 /* compute bitmask from p1 value */
6212 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6214 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6216 switch (intel_crtc->config.dpll.p2) {
6218 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6221 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6224 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6227 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6231 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6232 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6234 dpll |= PLL_REF_INPUT_DREFCLK;
6236 return dpll | DPLL_VCO_ENABLE;
6239 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6241 struct drm_framebuffer *fb)
6243 struct drm_device *dev = crtc->dev;
6244 struct drm_i915_private *dev_priv = dev->dev_private;
6245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6246 int pipe = intel_crtc->pipe;
6247 int plane = intel_crtc->plane;
6248 int num_connectors = 0;
6249 intel_clock_t clock, reduced_clock;
6250 u32 dpll = 0, fp = 0, fp2 = 0;
6251 bool ok, has_reduced_clock = false;
6252 bool is_lvds = false;
6253 struct intel_encoder *encoder;
6254 struct intel_shared_dpll *pll;
6257 for_each_encoder_on_crtc(dev, crtc, encoder) {
6258 switch (encoder->type) {
6259 case INTEL_OUTPUT_LVDS:
6267 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6268 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6270 ok = ironlake_compute_clocks(crtc, &clock,
6271 &has_reduced_clock, &reduced_clock);
6272 if (!ok && !intel_crtc->config.clock_set) {
6273 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6276 /* Compat-code for transition, will disappear. */
6277 if (!intel_crtc->config.clock_set) {
6278 intel_crtc->config.dpll.n = clock.n;
6279 intel_crtc->config.dpll.m1 = clock.m1;
6280 intel_crtc->config.dpll.m2 = clock.m2;
6281 intel_crtc->config.dpll.p1 = clock.p1;
6282 intel_crtc->config.dpll.p2 = clock.p2;
6285 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6286 if (intel_crtc->config.has_pch_encoder) {
6287 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6288 if (has_reduced_clock)
6289 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6291 dpll = ironlake_compute_dpll(intel_crtc,
6292 &fp, &reduced_clock,
6293 has_reduced_clock ? &fp2 : NULL);
6295 intel_crtc->config.dpll_hw_state.dpll = dpll;
6296 intel_crtc->config.dpll_hw_state.fp0 = fp;
6297 if (has_reduced_clock)
6298 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6300 intel_crtc->config.dpll_hw_state.fp1 = fp;
6302 pll = intel_get_shared_dpll(intel_crtc);
6304 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6309 intel_put_shared_dpll(intel_crtc);
6311 if (intel_crtc->config.has_dp_encoder)
6312 intel_dp_set_m_n(intel_crtc);
6314 if (is_lvds && has_reduced_clock && i915_powersave)
6315 intel_crtc->lowfreq_avail = true;
6317 intel_crtc->lowfreq_avail = false;
6319 intel_set_pipe_timings(intel_crtc);
6321 if (intel_crtc->config.has_pch_encoder) {
6322 intel_cpu_transcoder_set_m_n(intel_crtc,
6323 &intel_crtc->config.fdi_m_n);
6326 ironlake_set_pipeconf(crtc);
6328 /* Set up the display plane register */
6329 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6330 POSTING_READ(DSPCNTR(plane));
6332 ret = intel_pipe_set_base(crtc, x, y, fb);
6337 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6338 struct intel_link_m_n *m_n)
6340 struct drm_device *dev = crtc->base.dev;
6341 struct drm_i915_private *dev_priv = dev->dev_private;
6342 enum pipe pipe = crtc->pipe;
6344 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6345 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6346 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6348 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6349 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6350 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6353 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6354 enum transcoder transcoder,
6355 struct intel_link_m_n *m_n)
6357 struct drm_device *dev = crtc->base.dev;
6358 struct drm_i915_private *dev_priv = dev->dev_private;
6359 enum pipe pipe = crtc->pipe;
6361 if (INTEL_INFO(dev)->gen >= 5) {
6362 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6363 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6364 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6366 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6367 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6368 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6370 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6371 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6372 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6374 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6375 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6376 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6380 void intel_dp_get_m_n(struct intel_crtc *crtc,
6381 struct intel_crtc_config *pipe_config)
6383 if (crtc->config.has_pch_encoder)
6384 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6386 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6387 &pipe_config->dp_m_n);
6390 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6391 struct intel_crtc_config *pipe_config)
6393 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6394 &pipe_config->fdi_m_n);
6397 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6398 struct intel_crtc_config *pipe_config)
6400 struct drm_device *dev = crtc->base.dev;
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6404 tmp = I915_READ(PF_CTL(crtc->pipe));
6406 if (tmp & PF_ENABLE) {
6407 pipe_config->pch_pfit.enabled = true;
6408 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6409 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6411 /* We currently do not free assignements of panel fitters on
6412 * ivb/hsw (since we don't use the higher upscaling modes which
6413 * differentiates them) so just WARN about this case for now. */
6415 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6416 PF_PIPE_SEL_IVB(crtc->pipe));
6421 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6422 struct intel_crtc_config *pipe_config)
6424 struct drm_device *dev = crtc->base.dev;
6425 struct drm_i915_private *dev_priv = dev->dev_private;
6428 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6429 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6431 tmp = I915_READ(PIPECONF(crtc->pipe));
6432 if (!(tmp & PIPECONF_ENABLE))
6435 switch (tmp & PIPECONF_BPC_MASK) {
6437 pipe_config->pipe_bpp = 18;
6440 pipe_config->pipe_bpp = 24;
6442 case PIPECONF_10BPC:
6443 pipe_config->pipe_bpp = 30;
6445 case PIPECONF_12BPC:
6446 pipe_config->pipe_bpp = 36;
6452 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6453 struct intel_shared_dpll *pll;
6455 pipe_config->has_pch_encoder = true;
6457 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6458 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6459 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6461 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6463 if (HAS_PCH_IBX(dev_priv->dev)) {
6464 pipe_config->shared_dpll =
6465 (enum intel_dpll_id) crtc->pipe;
6467 tmp = I915_READ(PCH_DPLL_SEL);
6468 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6469 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6471 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6474 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6476 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6477 &pipe_config->dpll_hw_state));
6479 tmp = pipe_config->dpll_hw_state.dpll;
6480 pipe_config->pixel_multiplier =
6481 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6482 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6484 ironlake_pch_clock_get(crtc, pipe_config);
6486 pipe_config->pixel_multiplier = 1;
6489 intel_get_pipe_timings(crtc, pipe_config);
6491 ironlake_get_pfit_config(crtc, pipe_config);
6496 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6498 struct drm_device *dev = dev_priv->dev;
6499 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6500 struct intel_crtc *crtc;
6501 unsigned long irqflags;
6504 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6505 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6506 pipe_name(crtc->pipe));
6508 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6509 WARN(plls->spll_refcount, "SPLL enabled\n");
6510 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6511 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6512 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6513 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6514 "CPU PWM1 enabled\n");
6515 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6516 "CPU PWM2 enabled\n");
6517 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6518 "PCH PWM1 enabled\n");
6519 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6520 "Utility pin enabled\n");
6521 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6523 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6524 val = I915_READ(DEIMR);
6525 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6526 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6527 val = I915_READ(SDEIMR);
6528 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6529 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6530 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6534 * This function implements pieces of two sequences from BSpec:
6535 * - Sequence for display software to disable LCPLL
6536 * - Sequence for display software to allow package C8+
6537 * The steps implemented here are just the steps that actually touch the LCPLL
6538 * register. Callers should take care of disabling all the display engine
6539 * functions, doing the mode unset, fixing interrupts, etc.
6541 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6542 bool switch_to_fclk, bool allow_power_down)
6546 assert_can_disable_lcpll(dev_priv);
6548 val = I915_READ(LCPLL_CTL);
6550 if (switch_to_fclk) {
6551 val |= LCPLL_CD_SOURCE_FCLK;
6552 I915_WRITE(LCPLL_CTL, val);
6554 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6555 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6556 DRM_ERROR("Switching to FCLK failed\n");
6558 val = I915_READ(LCPLL_CTL);
6561 val |= LCPLL_PLL_DISABLE;
6562 I915_WRITE(LCPLL_CTL, val);
6563 POSTING_READ(LCPLL_CTL);
6565 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6566 DRM_ERROR("LCPLL still locked\n");
6568 val = I915_READ(D_COMP);
6569 val |= D_COMP_COMP_DISABLE;
6570 mutex_lock(&dev_priv->rps.hw_lock);
6571 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6572 DRM_ERROR("Failed to disable D_COMP\n");
6573 mutex_unlock(&dev_priv->rps.hw_lock);
6574 POSTING_READ(D_COMP);
6577 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6578 DRM_ERROR("D_COMP RCOMP still in progress\n");
6580 if (allow_power_down) {
6581 val = I915_READ(LCPLL_CTL);
6582 val |= LCPLL_POWER_DOWN_ALLOW;
6583 I915_WRITE(LCPLL_CTL, val);
6584 POSTING_READ(LCPLL_CTL);
6589 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6592 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6596 val = I915_READ(LCPLL_CTL);
6598 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6599 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6602 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6603 * we'll hang the machine! */
6604 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6606 if (val & LCPLL_POWER_DOWN_ALLOW) {
6607 val &= ~LCPLL_POWER_DOWN_ALLOW;
6608 I915_WRITE(LCPLL_CTL, val);
6609 POSTING_READ(LCPLL_CTL);
6612 val = I915_READ(D_COMP);
6613 val |= D_COMP_COMP_FORCE;
6614 val &= ~D_COMP_COMP_DISABLE;
6615 mutex_lock(&dev_priv->rps.hw_lock);
6616 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6617 DRM_ERROR("Failed to enable D_COMP\n");
6618 mutex_unlock(&dev_priv->rps.hw_lock);
6619 POSTING_READ(D_COMP);
6621 val = I915_READ(LCPLL_CTL);
6622 val &= ~LCPLL_PLL_DISABLE;
6623 I915_WRITE(LCPLL_CTL, val);
6625 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6626 DRM_ERROR("LCPLL not locked yet\n");
6628 if (val & LCPLL_CD_SOURCE_FCLK) {
6629 val = I915_READ(LCPLL_CTL);
6630 val &= ~LCPLL_CD_SOURCE_FCLK;
6631 I915_WRITE(LCPLL_CTL, val);
6633 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6634 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6635 DRM_ERROR("Switching back to LCPLL failed\n");
6638 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6641 void hsw_enable_pc8_work(struct work_struct *__work)
6643 struct drm_i915_private *dev_priv =
6644 container_of(to_delayed_work(__work), struct drm_i915_private,
6646 struct drm_device *dev = dev_priv->dev;
6649 WARN_ON(!HAS_PC8(dev));
6651 if (dev_priv->pc8.enabled)
6654 DRM_DEBUG_KMS("Enabling package C8+\n");
6656 dev_priv->pc8.enabled = true;
6658 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6659 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6660 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6661 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6664 lpt_disable_clkout_dp(dev);
6665 hsw_pc8_disable_interrupts(dev);
6666 hsw_disable_lcpll(dev_priv, true, true);
6668 intel_runtime_pm_put(dev_priv);
6671 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6673 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6674 WARN(dev_priv->pc8.disable_count < 1,
6675 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6677 dev_priv->pc8.disable_count--;
6678 if (dev_priv->pc8.disable_count != 0)
6681 schedule_delayed_work(&dev_priv->pc8.enable_work,
6682 msecs_to_jiffies(i915_pc8_timeout));
6685 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6687 struct drm_device *dev = dev_priv->dev;
6690 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6691 WARN(dev_priv->pc8.disable_count < 0,
6692 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6694 dev_priv->pc8.disable_count++;
6695 if (dev_priv->pc8.disable_count != 1)
6698 WARN_ON(!HAS_PC8(dev));
6700 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6701 if (!dev_priv->pc8.enabled)
6704 DRM_DEBUG_KMS("Disabling package C8+\n");
6706 intel_runtime_pm_get(dev_priv);
6708 hsw_restore_lcpll(dev_priv);
6709 hsw_pc8_restore_interrupts(dev);
6710 lpt_init_pch_refclk(dev);
6712 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6713 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6714 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6715 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6718 intel_prepare_ddi(dev);
6719 i915_gem_init_swizzling(dev);
6720 mutex_lock(&dev_priv->rps.hw_lock);
6721 gen6_update_ring_freq(dev);
6722 mutex_unlock(&dev_priv->rps.hw_lock);
6723 dev_priv->pc8.enabled = false;
6726 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6728 if (!HAS_PC8(dev_priv->dev))
6731 mutex_lock(&dev_priv->pc8.lock);
6732 __hsw_enable_package_c8(dev_priv);
6733 mutex_unlock(&dev_priv->pc8.lock);
6736 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6738 if (!HAS_PC8(dev_priv->dev))
6741 mutex_lock(&dev_priv->pc8.lock);
6742 __hsw_disable_package_c8(dev_priv);
6743 mutex_unlock(&dev_priv->pc8.lock);
6746 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6748 struct drm_device *dev = dev_priv->dev;
6749 struct intel_crtc *crtc;
6752 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6753 if (crtc->base.enabled)
6756 /* This case is still possible since we have the i915.disable_power_well
6757 * parameter and also the KVMr or something else might be requesting the
6759 val = I915_READ(HSW_PWR_WELL_DRIVER);
6761 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6768 /* Since we're called from modeset_global_resources there's no way to
6769 * symmetrically increase and decrease the refcount, so we use
6770 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6773 static void hsw_update_package_c8(struct drm_device *dev)
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6778 if (!HAS_PC8(dev_priv->dev))
6781 if (!i915_enable_pc8)
6784 mutex_lock(&dev_priv->pc8.lock);
6786 allow = hsw_can_enable_package_c8(dev_priv);
6788 if (allow == dev_priv->pc8.requirements_met)
6791 dev_priv->pc8.requirements_met = allow;
6794 __hsw_enable_package_c8(dev_priv);
6796 __hsw_disable_package_c8(dev_priv);
6799 mutex_unlock(&dev_priv->pc8.lock);
6802 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6804 if (!HAS_PC8(dev_priv->dev))
6807 mutex_lock(&dev_priv->pc8.lock);
6808 if (!dev_priv->pc8.gpu_idle) {
6809 dev_priv->pc8.gpu_idle = true;
6810 __hsw_enable_package_c8(dev_priv);
6812 mutex_unlock(&dev_priv->pc8.lock);
6815 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6817 if (!HAS_PC8(dev_priv->dev))
6820 mutex_lock(&dev_priv->pc8.lock);
6821 if (dev_priv->pc8.gpu_idle) {
6822 dev_priv->pc8.gpu_idle = false;
6823 __hsw_disable_package_c8(dev_priv);
6825 mutex_unlock(&dev_priv->pc8.lock);
6828 #define for_each_power_domain(domain, mask) \
6829 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6830 if ((1 << (domain)) & (mask))
6832 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6833 enum pipe pipe, bool pfit_enabled)
6836 enum transcoder transcoder;
6838 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6840 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6841 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6843 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6848 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6850 struct drm_i915_private *dev_priv = dev->dev_private;
6852 if (dev_priv->power_domains.init_power_on == enable)
6856 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6858 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6860 dev_priv->power_domains.init_power_on = enable;
6863 static void modeset_update_power_wells(struct drm_device *dev)
6865 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6866 struct intel_crtc *crtc;
6869 * First get all needed power domains, then put all unneeded, to avoid
6870 * any unnecessary toggling of the power wells.
6872 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6873 enum intel_display_power_domain domain;
6875 if (!crtc->base.enabled)
6878 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6880 crtc->config.pch_pfit.enabled);
6882 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6883 intel_display_power_get(dev, domain);
6886 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6887 enum intel_display_power_domain domain;
6889 for_each_power_domain(domain, crtc->enabled_power_domains)
6890 intel_display_power_put(dev, domain);
6892 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6895 intel_display_set_init_power(dev, false);
6898 static void haswell_modeset_global_resources(struct drm_device *dev)
6900 modeset_update_power_wells(dev);
6901 hsw_update_package_c8(dev);
6904 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6906 struct drm_framebuffer *fb)
6908 struct drm_device *dev = crtc->dev;
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6911 int plane = intel_crtc->plane;
6914 if (!intel_ddi_pll_select(intel_crtc))
6916 intel_ddi_pll_enable(intel_crtc);
6918 if (intel_crtc->config.has_dp_encoder)
6919 intel_dp_set_m_n(intel_crtc);
6921 intel_crtc->lowfreq_avail = false;
6923 intel_set_pipe_timings(intel_crtc);
6925 if (intel_crtc->config.has_pch_encoder) {
6926 intel_cpu_transcoder_set_m_n(intel_crtc,
6927 &intel_crtc->config.fdi_m_n);
6930 haswell_set_pipeconf(crtc);
6932 intel_set_pipe_csc(crtc);
6934 /* Set up the display plane register */
6935 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6936 POSTING_READ(DSPCNTR(plane));
6938 ret = intel_pipe_set_base(crtc, x, y, fb);
6943 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6944 struct intel_crtc_config *pipe_config)
6946 struct drm_device *dev = crtc->base.dev;
6947 struct drm_i915_private *dev_priv = dev->dev_private;
6948 enum intel_display_power_domain pfit_domain;
6951 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6952 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6954 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6955 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6956 enum pipe trans_edp_pipe;
6957 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6959 WARN(1, "unknown pipe linked to edp transcoder\n");
6960 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6961 case TRANS_DDI_EDP_INPUT_A_ON:
6962 trans_edp_pipe = PIPE_A;
6964 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6965 trans_edp_pipe = PIPE_B;
6967 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6968 trans_edp_pipe = PIPE_C;
6972 if (trans_edp_pipe == crtc->pipe)
6973 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6976 if (!intel_display_power_enabled(dev,
6977 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6980 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6981 if (!(tmp & PIPECONF_ENABLE))
6985 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6986 * DDI E. So just check whether this pipe is wired to DDI E and whether
6987 * the PCH transcoder is on.
6989 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6990 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6991 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6992 pipe_config->has_pch_encoder = true;
6994 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6995 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6996 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6998 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7001 intel_get_pipe_timings(crtc, pipe_config);
7003 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7004 if (intel_display_power_enabled(dev, pfit_domain))
7005 ironlake_get_pfit_config(crtc, pipe_config);
7007 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7008 (I915_READ(IPS_CTL) & IPS_ENABLE);
7010 pipe_config->pixel_multiplier = 1;
7015 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7017 struct drm_framebuffer *fb)
7019 struct drm_device *dev = crtc->dev;
7020 struct drm_i915_private *dev_priv = dev->dev_private;
7021 struct intel_encoder *encoder;
7022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7024 int pipe = intel_crtc->pipe;
7027 drm_vblank_pre_modeset(dev, pipe);
7029 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7031 drm_vblank_post_modeset(dev, pipe);
7036 for_each_encoder_on_crtc(dev, crtc, encoder) {
7037 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7038 encoder->base.base.id,
7039 drm_get_encoder_name(&encoder->base),
7040 mode->base.id, mode->name);
7041 encoder->mode_set(encoder);
7050 } hdmi_audio_clock[] = {
7051 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7052 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7053 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7054 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7055 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7056 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7057 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7058 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7059 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7060 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7063 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7064 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7068 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7069 if (mode->clock == hdmi_audio_clock[i].clock)
7073 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7074 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7078 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7079 hdmi_audio_clock[i].clock,
7080 hdmi_audio_clock[i].config);
7082 return hdmi_audio_clock[i].config;
7085 static bool intel_eld_uptodate(struct drm_connector *connector,
7086 int reg_eldv, uint32_t bits_eldv,
7087 int reg_elda, uint32_t bits_elda,
7090 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7091 uint8_t *eld = connector->eld;
7094 i = I915_READ(reg_eldv);
7103 i = I915_READ(reg_elda);
7105 I915_WRITE(reg_elda, i);
7107 for (i = 0; i < eld[2]; i++)
7108 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7114 static void g4x_write_eld(struct drm_connector *connector,
7115 struct drm_crtc *crtc,
7116 struct drm_display_mode *mode)
7118 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7119 uint8_t *eld = connector->eld;
7124 i = I915_READ(G4X_AUD_VID_DID);
7126 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7127 eldv = G4X_ELDV_DEVCL_DEVBLC;
7129 eldv = G4X_ELDV_DEVCTG;
7131 if (intel_eld_uptodate(connector,
7132 G4X_AUD_CNTL_ST, eldv,
7133 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7134 G4X_HDMIW_HDMIEDID))
7137 i = I915_READ(G4X_AUD_CNTL_ST);
7138 i &= ~(eldv | G4X_ELD_ADDR);
7139 len = (i >> 9) & 0x1f; /* ELD buffer size */
7140 I915_WRITE(G4X_AUD_CNTL_ST, i);
7145 len = min_t(uint8_t, eld[2], len);
7146 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7147 for (i = 0; i < len; i++)
7148 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7150 i = I915_READ(G4X_AUD_CNTL_ST);
7152 I915_WRITE(G4X_AUD_CNTL_ST, i);
7155 static void haswell_write_eld(struct drm_connector *connector,
7156 struct drm_crtc *crtc,
7157 struct drm_display_mode *mode)
7159 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7160 uint8_t *eld = connector->eld;
7161 struct drm_device *dev = crtc->dev;
7162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7166 int pipe = to_intel_crtc(crtc)->pipe;
7169 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7170 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7171 int aud_config = HSW_AUD_CFG(pipe);
7172 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7175 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7177 /* Audio output enable */
7178 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7179 tmp = I915_READ(aud_cntrl_st2);
7180 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7181 I915_WRITE(aud_cntrl_st2, tmp);
7183 /* Wait for 1 vertical blank */
7184 intel_wait_for_vblank(dev, pipe);
7186 /* Set ELD valid state */
7187 tmp = I915_READ(aud_cntrl_st2);
7188 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7189 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7190 I915_WRITE(aud_cntrl_st2, tmp);
7191 tmp = I915_READ(aud_cntrl_st2);
7192 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7194 /* Enable HDMI mode */
7195 tmp = I915_READ(aud_config);
7196 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7197 /* clear N_programing_enable and N_value_index */
7198 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7199 I915_WRITE(aud_config, tmp);
7201 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7203 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7204 intel_crtc->eld_vld = true;
7206 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7207 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7208 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7209 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7211 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7214 if (intel_eld_uptodate(connector,
7215 aud_cntrl_st2, eldv,
7216 aud_cntl_st, IBX_ELD_ADDRESS,
7220 i = I915_READ(aud_cntrl_st2);
7222 I915_WRITE(aud_cntrl_st2, i);
7227 i = I915_READ(aud_cntl_st);
7228 i &= ~IBX_ELD_ADDRESS;
7229 I915_WRITE(aud_cntl_st, i);
7230 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7231 DRM_DEBUG_DRIVER("port num:%d\n", i);
7233 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7234 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7235 for (i = 0; i < len; i++)
7236 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7238 i = I915_READ(aud_cntrl_st2);
7240 I915_WRITE(aud_cntrl_st2, i);
7244 static void ironlake_write_eld(struct drm_connector *connector,
7245 struct drm_crtc *crtc,
7246 struct drm_display_mode *mode)
7248 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7249 uint8_t *eld = connector->eld;
7257 int pipe = to_intel_crtc(crtc)->pipe;
7259 if (HAS_PCH_IBX(connector->dev)) {
7260 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7261 aud_config = IBX_AUD_CFG(pipe);
7262 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7263 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7264 } else if (IS_VALLEYVIEW(connector->dev)) {
7265 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7266 aud_config = VLV_AUD_CFG(pipe);
7267 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7268 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7270 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7271 aud_config = CPT_AUD_CFG(pipe);
7272 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7273 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7276 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7278 if (IS_VALLEYVIEW(connector->dev)) {
7279 struct intel_encoder *intel_encoder;
7280 struct intel_digital_port *intel_dig_port;
7282 intel_encoder = intel_attached_encoder(connector);
7283 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7284 i = intel_dig_port->port;
7286 i = I915_READ(aud_cntl_st);
7287 i = (i >> 29) & DIP_PORT_SEL_MASK;
7288 /* DIP_Port_Select, 0x1 = PortB */
7292 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7293 /* operate blindly on all ports */
7294 eldv = IBX_ELD_VALIDB;
7295 eldv |= IBX_ELD_VALIDB << 4;
7296 eldv |= IBX_ELD_VALIDB << 8;
7298 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7299 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7302 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7303 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7304 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7305 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7307 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7310 if (intel_eld_uptodate(connector,
7311 aud_cntrl_st2, eldv,
7312 aud_cntl_st, IBX_ELD_ADDRESS,
7316 i = I915_READ(aud_cntrl_st2);
7318 I915_WRITE(aud_cntrl_st2, i);
7323 i = I915_READ(aud_cntl_st);
7324 i &= ~IBX_ELD_ADDRESS;
7325 I915_WRITE(aud_cntl_st, i);
7327 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7328 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7329 for (i = 0; i < len; i++)
7330 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7332 i = I915_READ(aud_cntrl_st2);
7334 I915_WRITE(aud_cntrl_st2, i);
7337 void intel_write_eld(struct drm_encoder *encoder,
7338 struct drm_display_mode *mode)
7340 struct drm_crtc *crtc = encoder->crtc;
7341 struct drm_connector *connector;
7342 struct drm_device *dev = encoder->dev;
7343 struct drm_i915_private *dev_priv = dev->dev_private;
7345 connector = drm_select_eld(encoder, mode);
7349 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7351 drm_get_connector_name(connector),
7352 connector->encoder->base.id,
7353 drm_get_encoder_name(connector->encoder));
7355 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7357 if (dev_priv->display.write_eld)
7358 dev_priv->display.write_eld(connector, crtc, mode);
7361 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7363 struct drm_device *dev = crtc->dev;
7364 struct drm_i915_private *dev_priv = dev->dev_private;
7365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7366 bool visible = base != 0;
7369 if (intel_crtc->cursor_visible == visible)
7372 cntl = I915_READ(_CURACNTR);
7374 /* On these chipsets we can only modify the base whilst
7375 * the cursor is disabled.
7377 I915_WRITE(_CURABASE, base);
7379 cntl &= ~(CURSOR_FORMAT_MASK);
7380 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7381 cntl |= CURSOR_ENABLE |
7382 CURSOR_GAMMA_ENABLE |
7385 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7386 I915_WRITE(_CURACNTR, cntl);
7388 intel_crtc->cursor_visible = visible;
7391 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7393 struct drm_device *dev = crtc->dev;
7394 struct drm_i915_private *dev_priv = dev->dev_private;
7395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7396 int pipe = intel_crtc->pipe;
7397 bool visible = base != 0;
7399 if (intel_crtc->cursor_visible != visible) {
7400 uint32_t cntl = I915_READ(CURCNTR(pipe));
7402 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7403 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7404 cntl |= pipe << 28; /* Connect to correct pipe */
7406 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7407 cntl |= CURSOR_MODE_DISABLE;
7409 I915_WRITE(CURCNTR(pipe), cntl);
7411 intel_crtc->cursor_visible = visible;
7413 /* and commit changes on next vblank */
7414 POSTING_READ(CURCNTR(pipe));
7415 I915_WRITE(CURBASE(pipe), base);
7416 POSTING_READ(CURBASE(pipe));
7419 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7421 struct drm_device *dev = crtc->dev;
7422 struct drm_i915_private *dev_priv = dev->dev_private;
7423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7424 int pipe = intel_crtc->pipe;
7425 bool visible = base != 0;
7427 if (intel_crtc->cursor_visible != visible) {
7428 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7430 cntl &= ~CURSOR_MODE;
7431 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7433 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7434 cntl |= CURSOR_MODE_DISABLE;
7436 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7437 cntl |= CURSOR_PIPE_CSC_ENABLE;
7438 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7440 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7442 intel_crtc->cursor_visible = visible;
7444 /* and commit changes on next vblank */
7445 POSTING_READ(CURCNTR_IVB(pipe));
7446 I915_WRITE(CURBASE_IVB(pipe), base);
7447 POSTING_READ(CURBASE_IVB(pipe));
7450 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7451 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7454 struct drm_device *dev = crtc->dev;
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457 int pipe = intel_crtc->pipe;
7458 int x = intel_crtc->cursor_x;
7459 int y = intel_crtc->cursor_y;
7460 u32 base = 0, pos = 0;
7464 base = intel_crtc->cursor_addr;
7466 if (x >= intel_crtc->config.pipe_src_w)
7469 if (y >= intel_crtc->config.pipe_src_h)
7473 if (x + intel_crtc->cursor_width <= 0)
7476 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7479 pos |= x << CURSOR_X_SHIFT;
7482 if (y + intel_crtc->cursor_height <= 0)
7485 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7488 pos |= y << CURSOR_Y_SHIFT;
7490 visible = base != 0;
7491 if (!visible && !intel_crtc->cursor_visible)
7494 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7495 I915_WRITE(CURPOS_IVB(pipe), pos);
7496 ivb_update_cursor(crtc, base);
7498 I915_WRITE(CURPOS(pipe), pos);
7499 if (IS_845G(dev) || IS_I865G(dev))
7500 i845_update_cursor(crtc, base);
7502 i9xx_update_cursor(crtc, base);
7506 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7507 struct drm_file *file,
7509 uint32_t width, uint32_t height)
7511 struct drm_device *dev = crtc->dev;
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7514 struct drm_i915_gem_object *obj;
7518 /* if we want to turn off the cursor ignore width and height */
7520 DRM_DEBUG_KMS("cursor off\n");
7523 mutex_lock(&dev->struct_mutex);
7527 /* Currently we only support 64x64 cursors */
7528 if (width != 64 || height != 64) {
7529 DRM_ERROR("we currently only support 64x64 cursors\n");
7533 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7534 if (&obj->base == NULL)
7537 if (obj->base.size < width * height * 4) {
7538 DRM_ERROR("buffer is to small\n");
7543 /* we only need to pin inside GTT if cursor is non-phy */
7544 mutex_lock(&dev->struct_mutex);
7545 if (!dev_priv->info->cursor_needs_physical) {
7548 if (obj->tiling_mode) {
7549 DRM_ERROR("cursor cannot be tiled\n");
7554 /* Note that the w/a also requires 2 PTE of padding following
7555 * the bo. We currently fill all unused PTE with the shadow
7556 * page and so we should always have valid PTE following the
7557 * cursor preventing the VT-d warning.
7560 if (need_vtd_wa(dev))
7561 alignment = 64*1024;
7563 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7565 DRM_ERROR("failed to move cursor bo into the GTT\n");
7569 ret = i915_gem_object_put_fence(obj);
7571 DRM_ERROR("failed to release fence for cursor");
7575 addr = i915_gem_obj_ggtt_offset(obj);
7577 int align = IS_I830(dev) ? 16 * 1024 : 256;
7578 ret = i915_gem_attach_phys_object(dev, obj,
7579 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7582 DRM_ERROR("failed to attach phys object\n");
7585 addr = obj->phys_obj->handle->busaddr;
7589 I915_WRITE(CURSIZE, (height << 12) | width);
7592 if (intel_crtc->cursor_bo) {
7593 if (dev_priv->info->cursor_needs_physical) {
7594 if (intel_crtc->cursor_bo != obj)
7595 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7597 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7598 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7601 mutex_unlock(&dev->struct_mutex);
7603 intel_crtc->cursor_addr = addr;
7604 intel_crtc->cursor_bo = obj;
7605 intel_crtc->cursor_width = width;
7606 intel_crtc->cursor_height = height;
7608 if (intel_crtc->active)
7609 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7613 i915_gem_object_unpin_from_display_plane(obj);
7615 mutex_unlock(&dev->struct_mutex);
7617 drm_gem_object_unreference_unlocked(&obj->base);
7621 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7625 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7626 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7628 if (intel_crtc->active)
7629 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7634 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7635 u16 *blue, uint32_t start, uint32_t size)
7637 int end = (start + size > 256) ? 256 : start + size, i;
7638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7640 for (i = start; i < end; i++) {
7641 intel_crtc->lut_r[i] = red[i] >> 8;
7642 intel_crtc->lut_g[i] = green[i] >> 8;
7643 intel_crtc->lut_b[i] = blue[i] >> 8;
7646 intel_crtc_load_lut(crtc);
7649 /* VESA 640x480x72Hz mode to set on the pipe */
7650 static struct drm_display_mode load_detect_mode = {
7651 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7652 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7655 static struct drm_framebuffer *
7656 intel_framebuffer_create(struct drm_device *dev,
7657 struct drm_mode_fb_cmd2 *mode_cmd,
7658 struct drm_i915_gem_object *obj)
7660 struct intel_framebuffer *intel_fb;
7663 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7665 drm_gem_object_unreference_unlocked(&obj->base);
7666 return ERR_PTR(-ENOMEM);
7669 ret = i915_mutex_lock_interruptible(dev);
7673 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7674 mutex_unlock(&dev->struct_mutex);
7678 return &intel_fb->base;
7680 drm_gem_object_unreference_unlocked(&obj->base);
7683 return ERR_PTR(ret);
7687 intel_framebuffer_pitch_for_width(int width, int bpp)
7689 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7690 return ALIGN(pitch, 64);
7694 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7696 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7697 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7700 static struct drm_framebuffer *
7701 intel_framebuffer_create_for_mode(struct drm_device *dev,
7702 struct drm_display_mode *mode,
7705 struct drm_i915_gem_object *obj;
7706 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7708 obj = i915_gem_alloc_object(dev,
7709 intel_framebuffer_size_for_mode(mode, bpp));
7711 return ERR_PTR(-ENOMEM);
7713 mode_cmd.width = mode->hdisplay;
7714 mode_cmd.height = mode->vdisplay;
7715 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7717 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7719 return intel_framebuffer_create(dev, &mode_cmd, obj);
7722 static struct drm_framebuffer *
7723 mode_fits_in_fbdev(struct drm_device *dev,
7724 struct drm_display_mode *mode)
7726 #ifdef CONFIG_DRM_I915_FBDEV
7727 struct drm_i915_private *dev_priv = dev->dev_private;
7728 struct drm_i915_gem_object *obj;
7729 struct drm_framebuffer *fb;
7731 if (dev_priv->fbdev == NULL)
7734 obj = dev_priv->fbdev->ifb.obj;
7738 fb = &dev_priv->fbdev->ifb.base;
7739 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7740 fb->bits_per_pixel))
7743 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7752 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7753 struct drm_display_mode *mode,
7754 struct intel_load_detect_pipe *old)
7756 struct intel_crtc *intel_crtc;
7757 struct intel_encoder *intel_encoder =
7758 intel_attached_encoder(connector);
7759 struct drm_crtc *possible_crtc;
7760 struct drm_encoder *encoder = &intel_encoder->base;
7761 struct drm_crtc *crtc = NULL;
7762 struct drm_device *dev = encoder->dev;
7763 struct drm_framebuffer *fb;
7766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7767 connector->base.id, drm_get_connector_name(connector),
7768 encoder->base.id, drm_get_encoder_name(encoder));
7771 * Algorithm gets a little messy:
7773 * - if the connector already has an assigned crtc, use it (but make
7774 * sure it's on first)
7776 * - try to find the first unused crtc that can drive this connector,
7777 * and use that if we find one
7780 /* See if we already have a CRTC for this connector */
7781 if (encoder->crtc) {
7782 crtc = encoder->crtc;
7784 mutex_lock(&crtc->mutex);
7786 old->dpms_mode = connector->dpms;
7787 old->load_detect_temp = false;
7789 /* Make sure the crtc and connector are running */
7790 if (connector->dpms != DRM_MODE_DPMS_ON)
7791 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7796 /* Find an unused one (if possible) */
7797 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7799 if (!(encoder->possible_crtcs & (1 << i)))
7801 if (!possible_crtc->enabled) {
7802 crtc = possible_crtc;
7808 * If we didn't find an unused CRTC, don't use any.
7811 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7815 mutex_lock(&crtc->mutex);
7816 intel_encoder->new_crtc = to_intel_crtc(crtc);
7817 to_intel_connector(connector)->new_encoder = intel_encoder;
7819 intel_crtc = to_intel_crtc(crtc);
7820 old->dpms_mode = connector->dpms;
7821 old->load_detect_temp = true;
7822 old->release_fb = NULL;
7825 mode = &load_detect_mode;
7827 /* We need a framebuffer large enough to accommodate all accesses
7828 * that the plane may generate whilst we perform load detection.
7829 * We can not rely on the fbcon either being present (we get called
7830 * during its initialisation to detect all boot displays, or it may
7831 * not even exist) or that it is large enough to satisfy the
7834 fb = mode_fits_in_fbdev(dev, mode);
7836 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7837 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7838 old->release_fb = fb;
7840 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7842 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7843 mutex_unlock(&crtc->mutex);
7847 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7848 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7849 if (old->release_fb)
7850 old->release_fb->funcs->destroy(old->release_fb);
7851 mutex_unlock(&crtc->mutex);
7855 /* let the connector get through one full cycle before testing */
7856 intel_wait_for_vblank(dev, intel_crtc->pipe);
7860 void intel_release_load_detect_pipe(struct drm_connector *connector,
7861 struct intel_load_detect_pipe *old)
7863 struct intel_encoder *intel_encoder =
7864 intel_attached_encoder(connector);
7865 struct drm_encoder *encoder = &intel_encoder->base;
7866 struct drm_crtc *crtc = encoder->crtc;
7868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7869 connector->base.id, drm_get_connector_name(connector),
7870 encoder->base.id, drm_get_encoder_name(encoder));
7872 if (old->load_detect_temp) {
7873 to_intel_connector(connector)->new_encoder = NULL;
7874 intel_encoder->new_crtc = NULL;
7875 intel_set_mode(crtc, NULL, 0, 0, NULL);
7877 if (old->release_fb) {
7878 drm_framebuffer_unregister_private(old->release_fb);
7879 drm_framebuffer_unreference(old->release_fb);
7882 mutex_unlock(&crtc->mutex);
7886 /* Switch crtc and encoder back off if necessary */
7887 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7888 connector->funcs->dpms(connector, old->dpms_mode);
7890 mutex_unlock(&crtc->mutex);
7893 static int i9xx_pll_refclk(struct drm_device *dev,
7894 const struct intel_crtc_config *pipe_config)
7896 struct drm_i915_private *dev_priv = dev->dev_private;
7897 u32 dpll = pipe_config->dpll_hw_state.dpll;
7899 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7900 return dev_priv->vbt.lvds_ssc_freq;
7901 else if (HAS_PCH_SPLIT(dev))
7903 else if (!IS_GEN2(dev))
7909 /* Returns the clock of the currently programmed mode of the given pipe. */
7910 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7911 struct intel_crtc_config *pipe_config)
7913 struct drm_device *dev = crtc->base.dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 int pipe = pipe_config->cpu_transcoder;
7916 u32 dpll = pipe_config->dpll_hw_state.dpll;
7918 intel_clock_t clock;
7919 int refclk = i9xx_pll_refclk(dev, pipe_config);
7921 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7922 fp = pipe_config->dpll_hw_state.fp0;
7924 fp = pipe_config->dpll_hw_state.fp1;
7926 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7927 if (IS_PINEVIEW(dev)) {
7928 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7929 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7931 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7932 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7935 if (!IS_GEN2(dev)) {
7936 if (IS_PINEVIEW(dev))
7937 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7938 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7940 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7941 DPLL_FPA01_P1_POST_DIV_SHIFT);
7943 switch (dpll & DPLL_MODE_MASK) {
7944 case DPLLB_MODE_DAC_SERIAL:
7945 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7948 case DPLLB_MODE_LVDS:
7949 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7953 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7954 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7958 if (IS_PINEVIEW(dev))
7959 pineview_clock(refclk, &clock);
7961 i9xx_clock(refclk, &clock);
7963 u32 lvds = I915_READ(LVDS);
7964 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7967 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7968 DPLL_FPA01_P1_POST_DIV_SHIFT);
7970 if (lvds & LVDS_CLKB_POWER_UP)
7975 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7978 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7979 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7981 if (dpll & PLL_P2_DIVIDE_BY_4)
7987 i9xx_clock(refclk, &clock);
7991 * This value includes pixel_multiplier. We will use
7992 * port_clock to compute adjusted_mode.crtc_clock in the
7993 * encoder's get_config() function.
7995 pipe_config->port_clock = clock.dot;
7998 int intel_dotclock_calculate(int link_freq,
7999 const struct intel_link_m_n *m_n)
8002 * The calculation for the data clock is:
8003 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8004 * But we want to avoid losing precison if possible, so:
8005 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8007 * and the link clock is simpler:
8008 * link_clock = (m * link_clock) / n
8014 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8017 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8018 struct intel_crtc_config *pipe_config)
8020 struct drm_device *dev = crtc->base.dev;
8022 /* read out port_clock from the DPLL */
8023 i9xx_crtc_clock_get(crtc, pipe_config);
8026 * This value does not include pixel_multiplier.
8027 * We will check that port_clock and adjusted_mode.crtc_clock
8028 * agree once we know their relationship in the encoder's
8029 * get_config() function.
8031 pipe_config->adjusted_mode.crtc_clock =
8032 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8033 &pipe_config->fdi_m_n);
8036 /** Returns the currently programmed mode of the given pipe. */
8037 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8038 struct drm_crtc *crtc)
8040 struct drm_i915_private *dev_priv = dev->dev_private;
8041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8042 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8043 struct drm_display_mode *mode;
8044 struct intel_crtc_config pipe_config;
8045 int htot = I915_READ(HTOTAL(cpu_transcoder));
8046 int hsync = I915_READ(HSYNC(cpu_transcoder));
8047 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8048 int vsync = I915_READ(VSYNC(cpu_transcoder));
8049 enum pipe pipe = intel_crtc->pipe;
8051 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8056 * Construct a pipe_config sufficient for getting the clock info
8057 * back out of crtc_clock_get.
8059 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8060 * to use a real value here instead.
8062 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8063 pipe_config.pixel_multiplier = 1;
8064 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8065 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8066 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8067 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8069 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8070 mode->hdisplay = (htot & 0xffff) + 1;
8071 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8072 mode->hsync_start = (hsync & 0xffff) + 1;
8073 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8074 mode->vdisplay = (vtot & 0xffff) + 1;
8075 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8076 mode->vsync_start = (vsync & 0xffff) + 1;
8077 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8079 drm_mode_set_name(mode);
8084 static void intel_increase_pllclock(struct drm_crtc *crtc)
8086 struct drm_device *dev = crtc->dev;
8087 drm_i915_private_t *dev_priv = dev->dev_private;
8088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8089 int pipe = intel_crtc->pipe;
8090 int dpll_reg = DPLL(pipe);
8093 if (HAS_PCH_SPLIT(dev))
8096 if (!dev_priv->lvds_downclock_avail)
8099 dpll = I915_READ(dpll_reg);
8100 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8101 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8103 assert_panel_unlocked(dev_priv, pipe);
8105 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8106 I915_WRITE(dpll_reg, dpll);
8107 intel_wait_for_vblank(dev, pipe);
8109 dpll = I915_READ(dpll_reg);
8110 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8111 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8115 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8117 struct drm_device *dev = crtc->dev;
8118 drm_i915_private_t *dev_priv = dev->dev_private;
8119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8121 if (HAS_PCH_SPLIT(dev))
8124 if (!dev_priv->lvds_downclock_avail)
8128 * Since this is called by a timer, we should never get here in
8131 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8132 int pipe = intel_crtc->pipe;
8133 int dpll_reg = DPLL(pipe);
8136 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8138 assert_panel_unlocked(dev_priv, pipe);
8140 dpll = I915_READ(dpll_reg);
8141 dpll |= DISPLAY_RATE_SELECT_FPA1;
8142 I915_WRITE(dpll_reg, dpll);
8143 intel_wait_for_vblank(dev, pipe);
8144 dpll = I915_READ(dpll_reg);
8145 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8146 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8151 void intel_mark_busy(struct drm_device *dev)
8153 struct drm_i915_private *dev_priv = dev->dev_private;
8155 hsw_package_c8_gpu_busy(dev_priv);
8156 i915_update_gfx_val(dev_priv);
8159 void intel_mark_idle(struct drm_device *dev)
8161 struct drm_i915_private *dev_priv = dev->dev_private;
8162 struct drm_crtc *crtc;
8164 hsw_package_c8_gpu_idle(dev_priv);
8166 if (!i915_powersave)
8169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8173 intel_decrease_pllclock(crtc);
8176 if (dev_priv->info->gen >= 6)
8177 gen6_rps_idle(dev->dev_private);
8180 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8181 struct intel_ring_buffer *ring)
8183 struct drm_device *dev = obj->base.dev;
8184 struct drm_crtc *crtc;
8186 if (!i915_powersave)
8189 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8193 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8196 intel_increase_pllclock(crtc);
8197 if (ring && intel_fbc_enabled(dev))
8198 ring->fbc_dirty = true;
8202 static void intel_crtc_destroy(struct drm_crtc *crtc)
8204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8205 struct drm_device *dev = crtc->dev;
8206 struct intel_unpin_work *work;
8207 unsigned long flags;
8209 spin_lock_irqsave(&dev->event_lock, flags);
8210 work = intel_crtc->unpin_work;
8211 intel_crtc->unpin_work = NULL;
8212 spin_unlock_irqrestore(&dev->event_lock, flags);
8215 cancel_work_sync(&work->work);
8219 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8221 drm_crtc_cleanup(crtc);
8226 static void intel_unpin_work_fn(struct work_struct *__work)
8228 struct intel_unpin_work *work =
8229 container_of(__work, struct intel_unpin_work, work);
8230 struct drm_device *dev = work->crtc->dev;
8232 mutex_lock(&dev->struct_mutex);
8233 intel_unpin_fb_obj(work->old_fb_obj);
8234 drm_gem_object_unreference(&work->pending_flip_obj->base);
8235 drm_gem_object_unreference(&work->old_fb_obj->base);
8237 intel_update_fbc(dev);
8238 mutex_unlock(&dev->struct_mutex);
8240 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8241 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8246 static void do_intel_finish_page_flip(struct drm_device *dev,
8247 struct drm_crtc *crtc)
8249 drm_i915_private_t *dev_priv = dev->dev_private;
8250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8251 struct intel_unpin_work *work;
8252 unsigned long flags;
8254 /* Ignore early vblank irqs */
8255 if (intel_crtc == NULL)
8258 spin_lock_irqsave(&dev->event_lock, flags);
8259 work = intel_crtc->unpin_work;
8261 /* Ensure we don't miss a work->pending update ... */
8264 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8265 spin_unlock_irqrestore(&dev->event_lock, flags);
8269 /* and that the unpin work is consistent wrt ->pending. */
8272 intel_crtc->unpin_work = NULL;
8275 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8277 drm_vblank_put(dev, intel_crtc->pipe);
8279 spin_unlock_irqrestore(&dev->event_lock, flags);
8281 wake_up_all(&dev_priv->pending_flip_queue);
8283 queue_work(dev_priv->wq, &work->work);
8285 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8288 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8290 drm_i915_private_t *dev_priv = dev->dev_private;
8291 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8293 do_intel_finish_page_flip(dev, crtc);
8296 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8298 drm_i915_private_t *dev_priv = dev->dev_private;
8299 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8301 do_intel_finish_page_flip(dev, crtc);
8304 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8306 drm_i915_private_t *dev_priv = dev->dev_private;
8307 struct intel_crtc *intel_crtc =
8308 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8309 unsigned long flags;
8311 /* NB: An MMIO update of the plane base pointer will also
8312 * generate a page-flip completion irq, i.e. every modeset
8313 * is also accompanied by a spurious intel_prepare_page_flip().
8315 spin_lock_irqsave(&dev->event_lock, flags);
8316 if (intel_crtc->unpin_work)
8317 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8318 spin_unlock_irqrestore(&dev->event_lock, flags);
8321 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8323 /* Ensure that the work item is consistent when activating it ... */
8325 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8326 /* and that it is marked active as soon as the irq could fire. */
8330 static int intel_gen2_queue_flip(struct drm_device *dev,
8331 struct drm_crtc *crtc,
8332 struct drm_framebuffer *fb,
8333 struct drm_i915_gem_object *obj,
8336 struct drm_i915_private *dev_priv = dev->dev_private;
8337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8339 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8342 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8346 ret = intel_ring_begin(ring, 6);
8350 /* Can't queue multiple flips, so wait for the previous
8351 * one to finish before executing the next.
8353 if (intel_crtc->plane)
8354 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8356 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8357 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8358 intel_ring_emit(ring, MI_NOOP);
8359 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8360 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8361 intel_ring_emit(ring, fb->pitches[0]);
8362 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8363 intel_ring_emit(ring, 0); /* aux display base address, unused */
8365 intel_mark_page_flip_active(intel_crtc);
8366 __intel_ring_advance(ring);
8370 intel_unpin_fb_obj(obj);
8375 static int intel_gen3_queue_flip(struct drm_device *dev,
8376 struct drm_crtc *crtc,
8377 struct drm_framebuffer *fb,
8378 struct drm_i915_gem_object *obj,
8381 struct drm_i915_private *dev_priv = dev->dev_private;
8382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8384 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8387 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8391 ret = intel_ring_begin(ring, 6);
8395 if (intel_crtc->plane)
8396 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8398 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8399 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8400 intel_ring_emit(ring, MI_NOOP);
8401 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8402 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8403 intel_ring_emit(ring, fb->pitches[0]);
8404 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8405 intel_ring_emit(ring, MI_NOOP);
8407 intel_mark_page_flip_active(intel_crtc);
8408 __intel_ring_advance(ring);
8412 intel_unpin_fb_obj(obj);
8417 static int intel_gen4_queue_flip(struct drm_device *dev,
8418 struct drm_crtc *crtc,
8419 struct drm_framebuffer *fb,
8420 struct drm_i915_gem_object *obj,
8423 struct drm_i915_private *dev_priv = dev->dev_private;
8424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8425 uint32_t pf, pipesrc;
8426 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8429 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8433 ret = intel_ring_begin(ring, 4);
8437 /* i965+ uses the linear or tiled offsets from the
8438 * Display Registers (which do not change across a page-flip)
8439 * so we need only reprogram the base address.
8441 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8442 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8443 intel_ring_emit(ring, fb->pitches[0]);
8444 intel_ring_emit(ring,
8445 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8448 /* XXX Enabling the panel-fitter across page-flip is so far
8449 * untested on non-native modes, so ignore it for now.
8450 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8453 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8454 intel_ring_emit(ring, pf | pipesrc);
8456 intel_mark_page_flip_active(intel_crtc);
8457 __intel_ring_advance(ring);
8461 intel_unpin_fb_obj(obj);
8466 static int intel_gen6_queue_flip(struct drm_device *dev,
8467 struct drm_crtc *crtc,
8468 struct drm_framebuffer *fb,
8469 struct drm_i915_gem_object *obj,
8472 struct drm_i915_private *dev_priv = dev->dev_private;
8473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8474 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8475 uint32_t pf, pipesrc;
8478 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8482 ret = intel_ring_begin(ring, 4);
8486 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8487 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8488 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8489 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8491 /* Contrary to the suggestions in the documentation,
8492 * "Enable Panel Fitter" does not seem to be required when page
8493 * flipping with a non-native mode, and worse causes a normal
8495 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8498 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8499 intel_ring_emit(ring, pf | pipesrc);
8501 intel_mark_page_flip_active(intel_crtc);
8502 __intel_ring_advance(ring);
8506 intel_unpin_fb_obj(obj);
8511 static int intel_gen7_queue_flip(struct drm_device *dev,
8512 struct drm_crtc *crtc,
8513 struct drm_framebuffer *fb,
8514 struct drm_i915_gem_object *obj,
8517 struct drm_i915_private *dev_priv = dev->dev_private;
8518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8519 struct intel_ring_buffer *ring;
8520 uint32_t plane_bit = 0;
8524 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8525 ring = &dev_priv->ring[BCS];
8527 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8531 switch(intel_crtc->plane) {
8533 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8536 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8539 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8542 WARN_ONCE(1, "unknown plane in flip command\n");
8548 if (ring->id == RCS)
8551 ret = intel_ring_begin(ring, len);
8555 /* Unmask the flip-done completion message. Note that the bspec says that
8556 * we should do this for both the BCS and RCS, and that we must not unmask
8557 * more than one flip event at any time (or ensure that one flip message
8558 * can be sent by waiting for flip-done prior to queueing new flips).
8559 * Experimentation says that BCS works despite DERRMR masking all
8560 * flip-done completion events and that unmasking all planes at once
8561 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8562 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8564 if (ring->id == RCS) {
8565 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8566 intel_ring_emit(ring, DERRMR);
8567 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8568 DERRMR_PIPEB_PRI_FLIP_DONE |
8569 DERRMR_PIPEC_PRI_FLIP_DONE));
8570 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8571 intel_ring_emit(ring, DERRMR);
8572 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8575 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8576 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8577 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8578 intel_ring_emit(ring, (MI_NOOP));
8580 intel_mark_page_flip_active(intel_crtc);
8581 __intel_ring_advance(ring);
8585 intel_unpin_fb_obj(obj);
8590 static int intel_default_queue_flip(struct drm_device *dev,
8591 struct drm_crtc *crtc,
8592 struct drm_framebuffer *fb,
8593 struct drm_i915_gem_object *obj,
8599 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8600 struct drm_framebuffer *fb,
8601 struct drm_pending_vblank_event *event,
8602 uint32_t page_flip_flags)
8604 struct drm_device *dev = crtc->dev;
8605 struct drm_i915_private *dev_priv = dev->dev_private;
8606 struct drm_framebuffer *old_fb = crtc->fb;
8607 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8609 struct intel_unpin_work *work;
8610 unsigned long flags;
8613 /* Can't change pixel format via MI display flips. */
8614 if (fb->pixel_format != crtc->fb->pixel_format)
8618 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8619 * Note that pitch changes could also affect these register.
8621 if (INTEL_INFO(dev)->gen > 3 &&
8622 (fb->offsets[0] != crtc->fb->offsets[0] ||
8623 fb->pitches[0] != crtc->fb->pitches[0]))
8626 work = kzalloc(sizeof(*work), GFP_KERNEL);
8630 work->event = event;
8632 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8633 INIT_WORK(&work->work, intel_unpin_work_fn);
8635 ret = drm_vblank_get(dev, intel_crtc->pipe);
8639 /* We borrow the event spin lock for protecting unpin_work */
8640 spin_lock_irqsave(&dev->event_lock, flags);
8641 if (intel_crtc->unpin_work) {
8642 spin_unlock_irqrestore(&dev->event_lock, flags);
8644 drm_vblank_put(dev, intel_crtc->pipe);
8646 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8649 intel_crtc->unpin_work = work;
8650 spin_unlock_irqrestore(&dev->event_lock, flags);
8652 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8653 flush_workqueue(dev_priv->wq);
8655 ret = i915_mutex_lock_interruptible(dev);
8659 /* Reference the objects for the scheduled work. */
8660 drm_gem_object_reference(&work->old_fb_obj->base);
8661 drm_gem_object_reference(&obj->base);
8665 work->pending_flip_obj = obj;
8667 work->enable_stall_check = true;
8669 atomic_inc(&intel_crtc->unpin_work_count);
8670 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8672 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8674 goto cleanup_pending;
8676 intel_disable_fbc(dev);
8677 intel_mark_fb_busy(obj, NULL);
8678 mutex_unlock(&dev->struct_mutex);
8680 trace_i915_flip_request(intel_crtc->plane, obj);
8685 atomic_dec(&intel_crtc->unpin_work_count);
8687 drm_gem_object_unreference(&work->old_fb_obj->base);
8688 drm_gem_object_unreference(&obj->base);
8689 mutex_unlock(&dev->struct_mutex);
8692 spin_lock_irqsave(&dev->event_lock, flags);
8693 intel_crtc->unpin_work = NULL;
8694 spin_unlock_irqrestore(&dev->event_lock, flags);
8696 drm_vblank_put(dev, intel_crtc->pipe);
8703 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8704 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8705 .load_lut = intel_crtc_load_lut,
8708 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8709 struct drm_crtc *crtc)
8711 struct drm_device *dev;
8712 struct drm_crtc *tmp;
8715 WARN(!crtc, "checking null crtc?\n");
8719 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8725 if (encoder->possible_crtcs & crtc_mask)
8731 * intel_modeset_update_staged_output_state
8733 * Updates the staged output configuration state, e.g. after we've read out the
8736 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8738 struct intel_encoder *encoder;
8739 struct intel_connector *connector;
8741 list_for_each_entry(connector, &dev->mode_config.connector_list,
8743 connector->new_encoder =
8744 to_intel_encoder(connector->base.encoder);
8747 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8750 to_intel_crtc(encoder->base.crtc);
8755 * intel_modeset_commit_output_state
8757 * This function copies the stage display pipe configuration to the real one.
8759 static void intel_modeset_commit_output_state(struct drm_device *dev)
8761 struct intel_encoder *encoder;
8762 struct intel_connector *connector;
8764 list_for_each_entry(connector, &dev->mode_config.connector_list,
8766 connector->base.encoder = &connector->new_encoder->base;
8769 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8771 encoder->base.crtc = &encoder->new_crtc->base;
8776 connected_sink_compute_bpp(struct intel_connector * connector,
8777 struct intel_crtc_config *pipe_config)
8779 int bpp = pipe_config->pipe_bpp;
8781 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8782 connector->base.base.id,
8783 drm_get_connector_name(&connector->base));
8785 /* Don't use an invalid EDID bpc value */
8786 if (connector->base.display_info.bpc &&
8787 connector->base.display_info.bpc * 3 < bpp) {
8788 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8789 bpp, connector->base.display_info.bpc*3);
8790 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8793 /* Clamp bpp to 8 on screens without EDID 1.4 */
8794 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8795 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8797 pipe_config->pipe_bpp = 24;
8802 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8803 struct drm_framebuffer *fb,
8804 struct intel_crtc_config *pipe_config)
8806 struct drm_device *dev = crtc->base.dev;
8807 struct intel_connector *connector;
8810 switch (fb->pixel_format) {
8812 bpp = 8*3; /* since we go through a colormap */
8814 case DRM_FORMAT_XRGB1555:
8815 case DRM_FORMAT_ARGB1555:
8816 /* checked in intel_framebuffer_init already */
8817 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8819 case DRM_FORMAT_RGB565:
8820 bpp = 6*3; /* min is 18bpp */
8822 case DRM_FORMAT_XBGR8888:
8823 case DRM_FORMAT_ABGR8888:
8824 /* checked in intel_framebuffer_init already */
8825 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8827 case DRM_FORMAT_XRGB8888:
8828 case DRM_FORMAT_ARGB8888:
8831 case DRM_FORMAT_XRGB2101010:
8832 case DRM_FORMAT_ARGB2101010:
8833 case DRM_FORMAT_XBGR2101010:
8834 case DRM_FORMAT_ABGR2101010:
8835 /* checked in intel_framebuffer_init already */
8836 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8840 /* TODO: gen4+ supports 16 bpc floating point, too. */
8842 DRM_DEBUG_KMS("unsupported depth\n");
8846 pipe_config->pipe_bpp = bpp;
8848 /* Clamp display bpp to EDID value */
8849 list_for_each_entry(connector, &dev->mode_config.connector_list,
8851 if (!connector->new_encoder ||
8852 connector->new_encoder->new_crtc != crtc)
8855 connected_sink_compute_bpp(connector, pipe_config);
8861 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8863 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8864 "type: 0x%x flags: 0x%x\n",
8866 mode->crtc_hdisplay, mode->crtc_hsync_start,
8867 mode->crtc_hsync_end, mode->crtc_htotal,
8868 mode->crtc_vdisplay, mode->crtc_vsync_start,
8869 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8872 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8873 struct intel_crtc_config *pipe_config,
8874 const char *context)
8876 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8877 context, pipe_name(crtc->pipe));
8879 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8880 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8881 pipe_config->pipe_bpp, pipe_config->dither);
8882 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8883 pipe_config->has_pch_encoder,
8884 pipe_config->fdi_lanes,
8885 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8886 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8887 pipe_config->fdi_m_n.tu);
8888 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8889 pipe_config->has_dp_encoder,
8890 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8891 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8892 pipe_config->dp_m_n.tu);
8893 DRM_DEBUG_KMS("requested mode:\n");
8894 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8895 DRM_DEBUG_KMS("adjusted mode:\n");
8896 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8897 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8898 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8899 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8900 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8901 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8902 pipe_config->gmch_pfit.control,
8903 pipe_config->gmch_pfit.pgm_ratios,
8904 pipe_config->gmch_pfit.lvds_border_bits);
8905 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8906 pipe_config->pch_pfit.pos,
8907 pipe_config->pch_pfit.size,
8908 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8909 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8910 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8913 static bool check_encoder_cloning(struct drm_crtc *crtc)
8915 int num_encoders = 0;
8916 bool uncloneable_encoders = false;
8917 struct intel_encoder *encoder;
8919 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8921 if (&encoder->new_crtc->base != crtc)
8925 if (!encoder->cloneable)
8926 uncloneable_encoders = true;
8929 return !(num_encoders > 1 && uncloneable_encoders);
8932 static struct intel_crtc_config *
8933 intel_modeset_pipe_config(struct drm_crtc *crtc,
8934 struct drm_framebuffer *fb,
8935 struct drm_display_mode *mode)
8937 struct drm_device *dev = crtc->dev;
8938 struct intel_encoder *encoder;
8939 struct intel_crtc_config *pipe_config;
8940 int plane_bpp, ret = -EINVAL;
8943 if (!check_encoder_cloning(crtc)) {
8944 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8945 return ERR_PTR(-EINVAL);
8948 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8950 return ERR_PTR(-ENOMEM);
8952 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8953 drm_mode_copy(&pipe_config->requested_mode, mode);
8955 pipe_config->cpu_transcoder =
8956 (enum transcoder) to_intel_crtc(crtc)->pipe;
8957 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8960 * Sanitize sync polarity flags based on requested ones. If neither
8961 * positive or negative polarity is requested, treat this as meaning
8962 * negative polarity.
8964 if (!(pipe_config->adjusted_mode.flags &
8965 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8966 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8968 if (!(pipe_config->adjusted_mode.flags &
8969 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8970 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8972 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8973 * plane pixel format and any sink constraints into account. Returns the
8974 * source plane bpp so that dithering can be selected on mismatches
8975 * after encoders and crtc also have had their say. */
8976 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8982 * Determine the real pipe dimensions. Note that stereo modes can
8983 * increase the actual pipe size due to the frame doubling and
8984 * insertion of additional space for blanks between the frame. This
8985 * is stored in the crtc timings. We use the requested mode to do this
8986 * computation to clearly distinguish it from the adjusted mode, which
8987 * can be changed by the connectors in the below retry loop.
8989 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8990 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8991 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8994 /* Ensure the port clock defaults are reset when retrying. */
8995 pipe_config->port_clock = 0;
8996 pipe_config->pixel_multiplier = 1;
8998 /* Fill in default crtc timings, allow encoders to overwrite them. */
8999 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9001 /* Pass our mode to the connectors and the CRTC to give them a chance to
9002 * adjust it according to limitations or connector properties, and also
9003 * a chance to reject the mode entirely.
9005 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9008 if (&encoder->new_crtc->base != crtc)
9011 if (!(encoder->compute_config(encoder, pipe_config))) {
9012 DRM_DEBUG_KMS("Encoder config failure\n");
9017 /* Set default port clock if not overwritten by the encoder. Needs to be
9018 * done afterwards in case the encoder adjusts the mode. */
9019 if (!pipe_config->port_clock)
9020 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9021 * pipe_config->pixel_multiplier;
9023 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9025 DRM_DEBUG_KMS("CRTC fixup failed\n");
9030 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9035 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9040 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9041 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9042 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9047 return ERR_PTR(ret);
9050 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9051 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9053 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9054 unsigned *prepare_pipes, unsigned *disable_pipes)
9056 struct intel_crtc *intel_crtc;
9057 struct drm_device *dev = crtc->dev;
9058 struct intel_encoder *encoder;
9059 struct intel_connector *connector;
9060 struct drm_crtc *tmp_crtc;
9062 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9064 /* Check which crtcs have changed outputs connected to them, these need
9065 * to be part of the prepare_pipes mask. We don't (yet) support global
9066 * modeset across multiple crtcs, so modeset_pipes will only have one
9067 * bit set at most. */
9068 list_for_each_entry(connector, &dev->mode_config.connector_list,
9070 if (connector->base.encoder == &connector->new_encoder->base)
9073 if (connector->base.encoder) {
9074 tmp_crtc = connector->base.encoder->crtc;
9076 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9079 if (connector->new_encoder)
9081 1 << connector->new_encoder->new_crtc->pipe;
9084 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9086 if (encoder->base.crtc == &encoder->new_crtc->base)
9089 if (encoder->base.crtc) {
9090 tmp_crtc = encoder->base.crtc;
9092 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9095 if (encoder->new_crtc)
9096 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9099 /* Check for any pipes that will be fully disabled ... */
9100 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9104 /* Don't try to disable disabled crtcs. */
9105 if (!intel_crtc->base.enabled)
9108 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9110 if (encoder->new_crtc == intel_crtc)
9115 *disable_pipes |= 1 << intel_crtc->pipe;
9119 /* set_mode is also used to update properties on life display pipes. */
9120 intel_crtc = to_intel_crtc(crtc);
9122 *prepare_pipes |= 1 << intel_crtc->pipe;
9125 * For simplicity do a full modeset on any pipe where the output routing
9126 * changed. We could be more clever, but that would require us to be
9127 * more careful with calling the relevant encoder->mode_set functions.
9130 *modeset_pipes = *prepare_pipes;
9132 /* ... and mask these out. */
9133 *modeset_pipes &= ~(*disable_pipes);
9134 *prepare_pipes &= ~(*disable_pipes);
9137 * HACK: We don't (yet) fully support global modesets. intel_set_config
9138 * obies this rule, but the modeset restore mode of
9139 * intel_modeset_setup_hw_state does not.
9141 *modeset_pipes &= 1 << intel_crtc->pipe;
9142 *prepare_pipes &= 1 << intel_crtc->pipe;
9144 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9145 *modeset_pipes, *prepare_pipes, *disable_pipes);
9148 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9150 struct drm_encoder *encoder;
9151 struct drm_device *dev = crtc->dev;
9153 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9154 if (encoder->crtc == crtc)
9161 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9163 struct intel_encoder *intel_encoder;
9164 struct intel_crtc *intel_crtc;
9165 struct drm_connector *connector;
9167 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9169 if (!intel_encoder->base.crtc)
9172 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9174 if (prepare_pipes & (1 << intel_crtc->pipe))
9175 intel_encoder->connectors_active = false;
9178 intel_modeset_commit_output_state(dev);
9180 /* Update computed state. */
9181 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9183 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9186 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9187 if (!connector->encoder || !connector->encoder->crtc)
9190 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9192 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9193 struct drm_property *dpms_property =
9194 dev->mode_config.dpms_property;
9196 connector->dpms = DRM_MODE_DPMS_ON;
9197 drm_object_property_set_value(&connector->base,
9201 intel_encoder = to_intel_encoder(connector->encoder);
9202 intel_encoder->connectors_active = true;
9208 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9212 if (clock1 == clock2)
9215 if (!clock1 || !clock2)
9218 diff = abs(clock1 - clock2);
9220 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9226 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9227 list_for_each_entry((intel_crtc), \
9228 &(dev)->mode_config.crtc_list, \
9230 if (mask & (1 <<(intel_crtc)->pipe))
9233 intel_pipe_config_compare(struct drm_device *dev,
9234 struct intel_crtc_config *current_config,
9235 struct intel_crtc_config *pipe_config)
9237 #define PIPE_CONF_CHECK_X(name) \
9238 if (current_config->name != pipe_config->name) { \
9239 DRM_ERROR("mismatch in " #name " " \
9240 "(expected 0x%08x, found 0x%08x)\n", \
9241 current_config->name, \
9242 pipe_config->name); \
9246 #define PIPE_CONF_CHECK_I(name) \
9247 if (current_config->name != pipe_config->name) { \
9248 DRM_ERROR("mismatch in " #name " " \
9249 "(expected %i, found %i)\n", \
9250 current_config->name, \
9251 pipe_config->name); \
9255 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9256 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9257 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9258 "(expected %i, found %i)\n", \
9259 current_config->name & (mask), \
9260 pipe_config->name & (mask)); \
9264 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9265 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9266 DRM_ERROR("mismatch in " #name " " \
9267 "(expected %i, found %i)\n", \
9268 current_config->name, \
9269 pipe_config->name); \
9273 #define PIPE_CONF_QUIRK(quirk) \
9274 ((current_config->quirks | pipe_config->quirks) & (quirk))
9276 PIPE_CONF_CHECK_I(cpu_transcoder);
9278 PIPE_CONF_CHECK_I(has_pch_encoder);
9279 PIPE_CONF_CHECK_I(fdi_lanes);
9280 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9281 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9282 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9283 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9284 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9286 PIPE_CONF_CHECK_I(has_dp_encoder);
9287 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9288 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9289 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9290 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9291 PIPE_CONF_CHECK_I(dp_m_n.tu);
9293 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9294 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9295 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9296 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9297 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9298 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9300 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9301 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9302 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9303 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9304 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9305 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9307 PIPE_CONF_CHECK_I(pixel_multiplier);
9309 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9310 DRM_MODE_FLAG_INTERLACE);
9312 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9313 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9314 DRM_MODE_FLAG_PHSYNC);
9315 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9316 DRM_MODE_FLAG_NHSYNC);
9317 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9318 DRM_MODE_FLAG_PVSYNC);
9319 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9320 DRM_MODE_FLAG_NVSYNC);
9323 PIPE_CONF_CHECK_I(pipe_src_w);
9324 PIPE_CONF_CHECK_I(pipe_src_h);
9326 PIPE_CONF_CHECK_I(gmch_pfit.control);
9327 /* pfit ratios are autocomputed by the hw on gen4+ */
9328 if (INTEL_INFO(dev)->gen < 4)
9329 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9330 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9331 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9332 if (current_config->pch_pfit.enabled) {
9333 PIPE_CONF_CHECK_I(pch_pfit.pos);
9334 PIPE_CONF_CHECK_I(pch_pfit.size);
9337 PIPE_CONF_CHECK_I(ips_enabled);
9339 PIPE_CONF_CHECK_I(double_wide);
9341 PIPE_CONF_CHECK_I(shared_dpll);
9342 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9343 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9344 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9345 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9347 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9348 PIPE_CONF_CHECK_I(pipe_bpp);
9350 if (!IS_HASWELL(dev)) {
9351 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9352 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9355 #undef PIPE_CONF_CHECK_X
9356 #undef PIPE_CONF_CHECK_I
9357 #undef PIPE_CONF_CHECK_FLAGS
9358 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9359 #undef PIPE_CONF_QUIRK
9365 check_connector_state(struct drm_device *dev)
9367 struct intel_connector *connector;
9369 list_for_each_entry(connector, &dev->mode_config.connector_list,
9371 /* This also checks the encoder/connector hw state with the
9372 * ->get_hw_state callbacks. */
9373 intel_connector_check_state(connector);
9375 WARN(&connector->new_encoder->base != connector->base.encoder,
9376 "connector's staged encoder doesn't match current encoder\n");
9381 check_encoder_state(struct drm_device *dev)
9383 struct intel_encoder *encoder;
9384 struct intel_connector *connector;
9386 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9388 bool enabled = false;
9389 bool active = false;
9390 enum pipe pipe, tracked_pipe;
9392 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9393 encoder->base.base.id,
9394 drm_get_encoder_name(&encoder->base));
9396 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9397 "encoder's stage crtc doesn't match current crtc\n");
9398 WARN(encoder->connectors_active && !encoder->base.crtc,
9399 "encoder's active_connectors set, but no crtc\n");
9401 list_for_each_entry(connector, &dev->mode_config.connector_list,
9403 if (connector->base.encoder != &encoder->base)
9406 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9409 WARN(!!encoder->base.crtc != enabled,
9410 "encoder's enabled state mismatch "
9411 "(expected %i, found %i)\n",
9412 !!encoder->base.crtc, enabled);
9413 WARN(active && !encoder->base.crtc,
9414 "active encoder with no crtc\n");
9416 WARN(encoder->connectors_active != active,
9417 "encoder's computed active state doesn't match tracked active state "
9418 "(expected %i, found %i)\n", active, encoder->connectors_active);
9420 active = encoder->get_hw_state(encoder, &pipe);
9421 WARN(active != encoder->connectors_active,
9422 "encoder's hw state doesn't match sw tracking "
9423 "(expected %i, found %i)\n",
9424 encoder->connectors_active, active);
9426 if (!encoder->base.crtc)
9429 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9430 WARN(active && pipe != tracked_pipe,
9431 "active encoder's pipe doesn't match"
9432 "(expected %i, found %i)\n",
9433 tracked_pipe, pipe);
9439 check_crtc_state(struct drm_device *dev)
9441 drm_i915_private_t *dev_priv = dev->dev_private;
9442 struct intel_crtc *crtc;
9443 struct intel_encoder *encoder;
9444 struct intel_crtc_config pipe_config;
9446 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9448 bool enabled = false;
9449 bool active = false;
9451 memset(&pipe_config, 0, sizeof(pipe_config));
9453 DRM_DEBUG_KMS("[CRTC:%d]\n",
9454 crtc->base.base.id);
9456 WARN(crtc->active && !crtc->base.enabled,
9457 "active crtc, but not enabled in sw tracking\n");
9459 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9461 if (encoder->base.crtc != &crtc->base)
9464 if (encoder->connectors_active)
9468 WARN(active != crtc->active,
9469 "crtc's computed active state doesn't match tracked active state "
9470 "(expected %i, found %i)\n", active, crtc->active);
9471 WARN(enabled != crtc->base.enabled,
9472 "crtc's computed enabled state doesn't match tracked enabled state "
9473 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9475 active = dev_priv->display.get_pipe_config(crtc,
9478 /* hw state is inconsistent with the pipe A quirk */
9479 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9480 active = crtc->active;
9482 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9485 if (encoder->base.crtc != &crtc->base)
9487 if (encoder->get_hw_state(encoder, &pipe))
9488 encoder->get_config(encoder, &pipe_config);
9491 WARN(crtc->active != active,
9492 "crtc active state doesn't match with hw state "
9493 "(expected %i, found %i)\n", crtc->active, active);
9496 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9497 WARN(1, "pipe state doesn't match!\n");
9498 intel_dump_pipe_config(crtc, &pipe_config,
9500 intel_dump_pipe_config(crtc, &crtc->config,
9507 check_shared_dpll_state(struct drm_device *dev)
9509 drm_i915_private_t *dev_priv = dev->dev_private;
9510 struct intel_crtc *crtc;
9511 struct intel_dpll_hw_state dpll_hw_state;
9514 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9515 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9516 int enabled_crtcs = 0, active_crtcs = 0;
9519 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9521 DRM_DEBUG_KMS("%s\n", pll->name);
9523 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9525 WARN(pll->active > pll->refcount,
9526 "more active pll users than references: %i vs %i\n",
9527 pll->active, pll->refcount);
9528 WARN(pll->active && !pll->on,
9529 "pll in active use but not on in sw tracking\n");
9530 WARN(pll->on && !pll->active,
9531 "pll in on but not on in use in sw tracking\n");
9532 WARN(pll->on != active,
9533 "pll on state mismatch (expected %i, found %i)\n",
9536 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9538 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9540 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9543 WARN(pll->active != active_crtcs,
9544 "pll active crtcs mismatch (expected %i, found %i)\n",
9545 pll->active, active_crtcs);
9546 WARN(pll->refcount != enabled_crtcs,
9547 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9548 pll->refcount, enabled_crtcs);
9550 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9551 sizeof(dpll_hw_state)),
9552 "pll hw state mismatch\n");
9557 intel_modeset_check_state(struct drm_device *dev)
9559 check_connector_state(dev);
9560 check_encoder_state(dev);
9561 check_crtc_state(dev);
9562 check_shared_dpll_state(dev);
9565 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9569 * FDI already provided one idea for the dotclock.
9570 * Yell if the encoder disagrees.
9572 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9573 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9574 pipe_config->adjusted_mode.crtc_clock, dotclock);
9577 static int __intel_set_mode(struct drm_crtc *crtc,
9578 struct drm_display_mode *mode,
9579 int x, int y, struct drm_framebuffer *fb)
9581 struct drm_device *dev = crtc->dev;
9582 drm_i915_private_t *dev_priv = dev->dev_private;
9583 struct drm_display_mode *saved_mode, *saved_hwmode;
9584 struct intel_crtc_config *pipe_config = NULL;
9585 struct intel_crtc *intel_crtc;
9586 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9589 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9592 saved_hwmode = saved_mode + 1;
9594 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9595 &prepare_pipes, &disable_pipes);
9597 *saved_hwmode = crtc->hwmode;
9598 *saved_mode = crtc->mode;
9600 /* Hack: Because we don't (yet) support global modeset on multiple
9601 * crtcs, we don't keep track of the new mode for more than one crtc.
9602 * Hence simply check whether any bit is set in modeset_pipes in all the
9603 * pieces of code that are not yet converted to deal with mutliple crtcs
9604 * changing their mode at the same time. */
9605 if (modeset_pipes) {
9606 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9607 if (IS_ERR(pipe_config)) {
9608 ret = PTR_ERR(pipe_config);
9613 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9618 * See if the config requires any additional preparation, e.g.
9619 * to adjust global state with pipes off. We need to do this
9620 * here so we can get the modeset_pipe updated config for the new
9621 * mode set on this crtc. For other crtcs we need to use the
9622 * adjusted_mode bits in the crtc directly.
9624 if (IS_VALLEYVIEW(dev)) {
9625 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9626 modeset_pipes, pipe_config);
9628 /* may have added more to prepare_pipes than we should */
9629 prepare_pipes &= ~disable_pipes;
9632 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9633 intel_crtc_disable(&intel_crtc->base);
9635 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9636 if (intel_crtc->base.enabled)
9637 dev_priv->display.crtc_disable(&intel_crtc->base);
9640 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9641 * to set it here already despite that we pass it down the callchain.
9643 if (modeset_pipes) {
9645 /* mode_set/enable/disable functions rely on a correct pipe
9647 to_intel_crtc(crtc)->config = *pipe_config;
9650 /* Only after disabling all output pipelines that will be changed can we
9651 * update the the output configuration. */
9652 intel_modeset_update_state(dev, prepare_pipes);
9654 if (dev_priv->display.modeset_global_resources)
9655 dev_priv->display.modeset_global_resources(dev);
9657 /* Set up the DPLL and any encoders state that needs to adjust or depend
9660 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9661 ret = intel_crtc_mode_set(&intel_crtc->base,
9667 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9668 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9669 dev_priv->display.crtc_enable(&intel_crtc->base);
9671 if (modeset_pipes) {
9672 /* Store real post-adjustment hardware mode. */
9673 crtc->hwmode = pipe_config->adjusted_mode;
9675 /* Calculate and store various constants which
9676 * are later needed by vblank and swap-completion
9677 * timestamping. They are derived from true hwmode.
9679 drm_calc_timestamping_constants(crtc);
9682 /* FIXME: add subpixel order */
9684 if (ret && crtc->enabled) {
9685 crtc->hwmode = *saved_hwmode;
9686 crtc->mode = *saved_mode;
9695 static int intel_set_mode(struct drm_crtc *crtc,
9696 struct drm_display_mode *mode,
9697 int x, int y, struct drm_framebuffer *fb)
9701 ret = __intel_set_mode(crtc, mode, x, y, fb);
9704 intel_modeset_check_state(crtc->dev);
9709 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9711 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9714 #undef for_each_intel_crtc_masked
9716 static void intel_set_config_free(struct intel_set_config *config)
9721 kfree(config->save_connector_encoders);
9722 kfree(config->save_encoder_crtcs);
9726 static int intel_set_config_save_state(struct drm_device *dev,
9727 struct intel_set_config *config)
9729 struct drm_encoder *encoder;
9730 struct drm_connector *connector;
9733 config->save_encoder_crtcs =
9734 kcalloc(dev->mode_config.num_encoder,
9735 sizeof(struct drm_crtc *), GFP_KERNEL);
9736 if (!config->save_encoder_crtcs)
9739 config->save_connector_encoders =
9740 kcalloc(dev->mode_config.num_connector,
9741 sizeof(struct drm_encoder *), GFP_KERNEL);
9742 if (!config->save_connector_encoders)
9745 /* Copy data. Note that driver private data is not affected.
9746 * Should anything bad happen only the expected state is
9747 * restored, not the drivers personal bookkeeping.
9750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9751 config->save_encoder_crtcs[count++] = encoder->crtc;
9755 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9756 config->save_connector_encoders[count++] = connector->encoder;
9762 static void intel_set_config_restore_state(struct drm_device *dev,
9763 struct intel_set_config *config)
9765 struct intel_encoder *encoder;
9766 struct intel_connector *connector;
9770 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9772 to_intel_crtc(config->save_encoder_crtcs[count++]);
9776 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9777 connector->new_encoder =
9778 to_intel_encoder(config->save_connector_encoders[count++]);
9783 is_crtc_connector_off(struct drm_mode_set *set)
9787 if (set->num_connectors == 0)
9790 if (WARN_ON(set->connectors == NULL))
9793 for (i = 0; i < set->num_connectors; i++)
9794 if (set->connectors[i]->encoder &&
9795 set->connectors[i]->encoder->crtc == set->crtc &&
9796 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9803 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9804 struct intel_set_config *config)
9807 /* We should be able to check here if the fb has the same properties
9808 * and then just flip_or_move it */
9809 if (is_crtc_connector_off(set)) {
9810 config->mode_changed = true;
9811 } else if (set->crtc->fb != set->fb) {
9812 /* If we have no fb then treat it as a full mode set */
9813 if (set->crtc->fb == NULL) {
9814 struct intel_crtc *intel_crtc =
9815 to_intel_crtc(set->crtc);
9817 if (intel_crtc->active && i915_fastboot) {
9818 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9819 config->fb_changed = true;
9821 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9822 config->mode_changed = true;
9824 } else if (set->fb == NULL) {
9825 config->mode_changed = true;
9826 } else if (set->fb->pixel_format !=
9827 set->crtc->fb->pixel_format) {
9828 config->mode_changed = true;
9830 config->fb_changed = true;
9834 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9835 config->fb_changed = true;
9837 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9838 DRM_DEBUG_KMS("modes are different, full mode set\n");
9839 drm_mode_debug_printmodeline(&set->crtc->mode);
9840 drm_mode_debug_printmodeline(set->mode);
9841 config->mode_changed = true;
9844 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9845 set->crtc->base.id, config->mode_changed, config->fb_changed);
9849 intel_modeset_stage_output_state(struct drm_device *dev,
9850 struct drm_mode_set *set,
9851 struct intel_set_config *config)
9853 struct drm_crtc *new_crtc;
9854 struct intel_connector *connector;
9855 struct intel_encoder *encoder;
9858 /* The upper layers ensure that we either disable a crtc or have a list
9859 * of connectors. For paranoia, double-check this. */
9860 WARN_ON(!set->fb && (set->num_connectors != 0));
9861 WARN_ON(set->fb && (set->num_connectors == 0));
9863 list_for_each_entry(connector, &dev->mode_config.connector_list,
9865 /* Otherwise traverse passed in connector list and get encoders
9867 for (ro = 0; ro < set->num_connectors; ro++) {
9868 if (set->connectors[ro] == &connector->base) {
9869 connector->new_encoder = connector->encoder;
9874 /* If we disable the crtc, disable all its connectors. Also, if
9875 * the connector is on the changing crtc but not on the new
9876 * connector list, disable it. */
9877 if ((!set->fb || ro == set->num_connectors) &&
9878 connector->base.encoder &&
9879 connector->base.encoder->crtc == set->crtc) {
9880 connector->new_encoder = NULL;
9882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9883 connector->base.base.id,
9884 drm_get_connector_name(&connector->base));
9888 if (&connector->new_encoder->base != connector->base.encoder) {
9889 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9890 config->mode_changed = true;
9893 /* connector->new_encoder is now updated for all connectors. */
9895 /* Update crtc of enabled connectors. */
9896 list_for_each_entry(connector, &dev->mode_config.connector_list,
9898 if (!connector->new_encoder)
9901 new_crtc = connector->new_encoder->base.crtc;
9903 for (ro = 0; ro < set->num_connectors; ro++) {
9904 if (set->connectors[ro] == &connector->base)
9905 new_crtc = set->crtc;
9908 /* Make sure the new CRTC will work with the encoder */
9909 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9913 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9916 connector->base.base.id,
9917 drm_get_connector_name(&connector->base),
9921 /* Check for any encoders that needs to be disabled. */
9922 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9924 list_for_each_entry(connector,
9925 &dev->mode_config.connector_list,
9927 if (connector->new_encoder == encoder) {
9928 WARN_ON(!connector->new_encoder->new_crtc);
9933 encoder->new_crtc = NULL;
9935 /* Only now check for crtc changes so we don't miss encoders
9936 * that will be disabled. */
9937 if (&encoder->new_crtc->base != encoder->base.crtc) {
9938 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9939 config->mode_changed = true;
9942 /* Now we've also updated encoder->new_crtc for all encoders. */
9947 static int intel_crtc_set_config(struct drm_mode_set *set)
9949 struct drm_device *dev;
9950 struct drm_mode_set save_set;
9951 struct intel_set_config *config;
9956 BUG_ON(!set->crtc->helper_private);
9958 /* Enforce sane interface api - has been abused by the fb helper. */
9959 BUG_ON(!set->mode && set->fb);
9960 BUG_ON(set->fb && set->num_connectors == 0);
9963 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9964 set->crtc->base.id, set->fb->base.id,
9965 (int)set->num_connectors, set->x, set->y);
9967 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9970 dev = set->crtc->dev;
9973 config = kzalloc(sizeof(*config), GFP_KERNEL);
9977 ret = intel_set_config_save_state(dev, config);
9981 save_set.crtc = set->crtc;
9982 save_set.mode = &set->crtc->mode;
9983 save_set.x = set->crtc->x;
9984 save_set.y = set->crtc->y;
9985 save_set.fb = set->crtc->fb;
9987 /* Compute whether we need a full modeset, only an fb base update or no
9988 * change at all. In the future we might also check whether only the
9989 * mode changed, e.g. for LVDS where we only change the panel fitter in
9991 intel_set_config_compute_mode_changes(set, config);
9993 ret = intel_modeset_stage_output_state(dev, set, config);
9997 if (config->mode_changed) {
9998 ret = intel_set_mode(set->crtc, set->mode,
9999 set->x, set->y, set->fb);
10000 } else if (config->fb_changed) {
10001 intel_crtc_wait_for_pending_flips(set->crtc);
10003 ret = intel_pipe_set_base(set->crtc,
10004 set->x, set->y, set->fb);
10006 * In the fastboot case this may be our only check of the
10007 * state after boot. It would be better to only do it on
10008 * the first update, but we don't have a nice way of doing that
10009 * (and really, set_config isn't used much for high freq page
10010 * flipping, so increasing its cost here shouldn't be a big
10013 if (i915_fastboot && ret == 0)
10014 intel_modeset_check_state(set->crtc->dev);
10018 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10019 set->crtc->base.id, ret);
10021 intel_set_config_restore_state(dev, config);
10023 /* Try to restore the config */
10024 if (config->mode_changed &&
10025 intel_set_mode(save_set.crtc, save_set.mode,
10026 save_set.x, save_set.y, save_set.fb))
10027 DRM_ERROR("failed to restore config after modeset failure\n");
10031 intel_set_config_free(config);
10035 static const struct drm_crtc_funcs intel_crtc_funcs = {
10036 .cursor_set = intel_crtc_cursor_set,
10037 .cursor_move = intel_crtc_cursor_move,
10038 .gamma_set = intel_crtc_gamma_set,
10039 .set_config = intel_crtc_set_config,
10040 .destroy = intel_crtc_destroy,
10041 .page_flip = intel_crtc_page_flip,
10044 static void intel_cpu_pll_init(struct drm_device *dev)
10047 intel_ddi_pll_init(dev);
10050 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10051 struct intel_shared_dpll *pll,
10052 struct intel_dpll_hw_state *hw_state)
10056 val = I915_READ(PCH_DPLL(pll->id));
10057 hw_state->dpll = val;
10058 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10059 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10061 return val & DPLL_VCO_ENABLE;
10064 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10065 struct intel_shared_dpll *pll)
10067 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10068 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10071 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10072 struct intel_shared_dpll *pll)
10074 /* PCH refclock must be enabled first */
10075 assert_pch_refclk_enabled(dev_priv);
10077 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10079 /* Wait for the clocks to stabilize. */
10080 POSTING_READ(PCH_DPLL(pll->id));
10083 /* The pixel multiplier can only be updated once the
10084 * DPLL is enabled and the clocks are stable.
10086 * So write it again.
10088 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10089 POSTING_READ(PCH_DPLL(pll->id));
10093 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10094 struct intel_shared_dpll *pll)
10096 struct drm_device *dev = dev_priv->dev;
10097 struct intel_crtc *crtc;
10099 /* Make sure no transcoder isn't still depending on us. */
10100 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10101 if (intel_crtc_to_shared_dpll(crtc) == pll)
10102 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10105 I915_WRITE(PCH_DPLL(pll->id), 0);
10106 POSTING_READ(PCH_DPLL(pll->id));
10110 static char *ibx_pch_dpll_names[] = {
10115 static void ibx_pch_dpll_init(struct drm_device *dev)
10117 struct drm_i915_private *dev_priv = dev->dev_private;
10120 dev_priv->num_shared_dpll = 2;
10122 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10123 dev_priv->shared_dplls[i].id = i;
10124 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10125 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10126 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10127 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10128 dev_priv->shared_dplls[i].get_hw_state =
10129 ibx_pch_dpll_get_hw_state;
10133 static void intel_shared_dpll_init(struct drm_device *dev)
10135 struct drm_i915_private *dev_priv = dev->dev_private;
10137 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10138 ibx_pch_dpll_init(dev);
10140 dev_priv->num_shared_dpll = 0;
10142 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10143 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10144 dev_priv->num_shared_dpll);
10147 static void intel_crtc_init(struct drm_device *dev, int pipe)
10149 drm_i915_private_t *dev_priv = dev->dev_private;
10150 struct intel_crtc *intel_crtc;
10153 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10154 if (intel_crtc == NULL)
10157 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10159 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10160 for (i = 0; i < 256; i++) {
10161 intel_crtc->lut_r[i] = i;
10162 intel_crtc->lut_g[i] = i;
10163 intel_crtc->lut_b[i] = i;
10167 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10168 * is hooked to plane B. Hence we want plane A feeding pipe B.
10170 intel_crtc->pipe = pipe;
10171 intel_crtc->plane = pipe;
10172 if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
10173 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10174 intel_crtc->plane = !pipe;
10177 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10178 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10179 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10180 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10182 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10185 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10187 struct drm_encoder *encoder = connector->base.encoder;
10189 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10192 return INVALID_PIPE;
10194 return to_intel_crtc(encoder->crtc)->pipe;
10197 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10198 struct drm_file *file)
10200 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10201 struct drm_mode_object *drmmode_obj;
10202 struct intel_crtc *crtc;
10204 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10207 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10208 DRM_MODE_OBJECT_CRTC);
10210 if (!drmmode_obj) {
10211 DRM_ERROR("no such CRTC id\n");
10215 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10216 pipe_from_crtc_id->pipe = crtc->pipe;
10221 static int intel_encoder_clones(struct intel_encoder *encoder)
10223 struct drm_device *dev = encoder->base.dev;
10224 struct intel_encoder *source_encoder;
10225 int index_mask = 0;
10228 list_for_each_entry(source_encoder,
10229 &dev->mode_config.encoder_list, base.head) {
10231 if (encoder == source_encoder)
10232 index_mask |= (1 << entry);
10234 /* Intel hw has only one MUX where enocoders could be cloned. */
10235 if (encoder->cloneable && source_encoder->cloneable)
10236 index_mask |= (1 << entry);
10244 static bool has_edp_a(struct drm_device *dev)
10246 struct drm_i915_private *dev_priv = dev->dev_private;
10248 if (!IS_MOBILE(dev))
10251 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10254 if (IS_GEN5(dev) &&
10255 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10261 static void intel_setup_outputs(struct drm_device *dev)
10263 struct drm_i915_private *dev_priv = dev->dev_private;
10264 struct intel_encoder *encoder;
10265 bool dpd_is_edp = false;
10267 intel_lvds_init(dev);
10270 intel_crt_init(dev);
10272 if (HAS_DDI(dev)) {
10275 /* Haswell uses DDI functions to detect digital outputs */
10276 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10277 /* DDI A only supports eDP */
10279 intel_ddi_init(dev, PORT_A);
10281 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10283 found = I915_READ(SFUSE_STRAP);
10285 if (found & SFUSE_STRAP_DDIB_DETECTED)
10286 intel_ddi_init(dev, PORT_B);
10287 if (found & SFUSE_STRAP_DDIC_DETECTED)
10288 intel_ddi_init(dev, PORT_C);
10289 if (found & SFUSE_STRAP_DDID_DETECTED)
10290 intel_ddi_init(dev, PORT_D);
10291 } else if (HAS_PCH_SPLIT(dev)) {
10293 dpd_is_edp = intel_dpd_is_edp(dev);
10295 if (has_edp_a(dev))
10296 intel_dp_init(dev, DP_A, PORT_A);
10298 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10299 /* PCH SDVOB multiplex with HDMIB */
10300 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10302 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10303 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10304 intel_dp_init(dev, PCH_DP_B, PORT_B);
10307 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10308 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10310 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10311 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10313 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10314 intel_dp_init(dev, PCH_DP_C, PORT_C);
10316 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10317 intel_dp_init(dev, PCH_DP_D, PORT_D);
10318 } else if (IS_VALLEYVIEW(dev)) {
10319 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10320 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10322 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10323 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10326 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10327 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10329 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10330 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10334 intel_dsi_init(dev);
10335 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10336 bool found = false;
10338 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10339 DRM_DEBUG_KMS("probing SDVOB\n");
10340 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10341 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10342 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10343 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10346 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10347 intel_dp_init(dev, DP_B, PORT_B);
10350 /* Before G4X SDVOC doesn't have its own detect register */
10352 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10353 DRM_DEBUG_KMS("probing SDVOC\n");
10354 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10357 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10359 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10360 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10361 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10363 if (SUPPORTS_INTEGRATED_DP(dev))
10364 intel_dp_init(dev, DP_C, PORT_C);
10367 if (SUPPORTS_INTEGRATED_DP(dev) &&
10368 (I915_READ(DP_D) & DP_DETECTED))
10369 intel_dp_init(dev, DP_D, PORT_D);
10370 } else if (IS_GEN2(dev))
10371 intel_dvo_init(dev);
10373 if (SUPPORTS_TV(dev))
10374 intel_tv_init(dev);
10376 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10377 encoder->base.possible_crtcs = encoder->crtc_mask;
10378 encoder->base.possible_clones =
10379 intel_encoder_clones(encoder);
10382 intel_init_pch_refclk(dev);
10384 drm_helper_move_panel_connectors_to_head(dev);
10387 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10389 drm_framebuffer_cleanup(&fb->base);
10390 WARN_ON(!fb->obj->framebuffer_references--);
10391 drm_gem_object_unreference_unlocked(&fb->obj->base);
10394 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10396 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10398 intel_framebuffer_fini(intel_fb);
10402 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10403 struct drm_file *file,
10404 unsigned int *handle)
10406 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10407 struct drm_i915_gem_object *obj = intel_fb->obj;
10409 return drm_gem_handle_create(file, &obj->base, handle);
10412 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10413 .destroy = intel_user_framebuffer_destroy,
10414 .create_handle = intel_user_framebuffer_create_handle,
10417 int intel_framebuffer_init(struct drm_device *dev,
10418 struct intel_framebuffer *intel_fb,
10419 struct drm_mode_fb_cmd2 *mode_cmd,
10420 struct drm_i915_gem_object *obj)
10422 int aligned_height, tile_height;
10426 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10428 if (obj->tiling_mode == I915_TILING_Y) {
10429 DRM_DEBUG("hardware does not support tiling Y\n");
10433 if (mode_cmd->pitches[0] & 63) {
10434 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10435 mode_cmd->pitches[0]);
10439 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10440 pitch_limit = 32*1024;
10441 } else if (INTEL_INFO(dev)->gen >= 4) {
10442 if (obj->tiling_mode)
10443 pitch_limit = 16*1024;
10445 pitch_limit = 32*1024;
10446 } else if (INTEL_INFO(dev)->gen >= 3) {
10447 if (obj->tiling_mode)
10448 pitch_limit = 8*1024;
10450 pitch_limit = 16*1024;
10452 /* XXX DSPC is limited to 4k tiled */
10453 pitch_limit = 8*1024;
10455 if (mode_cmd->pitches[0] > pitch_limit) {
10456 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10457 obj->tiling_mode ? "tiled" : "linear",
10458 mode_cmd->pitches[0], pitch_limit);
10462 if (obj->tiling_mode != I915_TILING_NONE &&
10463 mode_cmd->pitches[0] != obj->stride) {
10464 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10465 mode_cmd->pitches[0], obj->stride);
10469 /* Reject formats not supported by any plane early. */
10470 switch (mode_cmd->pixel_format) {
10471 case DRM_FORMAT_C8:
10472 case DRM_FORMAT_RGB565:
10473 case DRM_FORMAT_XRGB8888:
10474 case DRM_FORMAT_ARGB8888:
10476 case DRM_FORMAT_XRGB1555:
10477 case DRM_FORMAT_ARGB1555:
10478 if (INTEL_INFO(dev)->gen > 3) {
10479 DRM_DEBUG("unsupported pixel format: %s\n",
10480 drm_get_format_name(mode_cmd->pixel_format));
10484 case DRM_FORMAT_XBGR8888:
10485 case DRM_FORMAT_ABGR8888:
10486 case DRM_FORMAT_XRGB2101010:
10487 case DRM_FORMAT_ARGB2101010:
10488 case DRM_FORMAT_XBGR2101010:
10489 case DRM_FORMAT_ABGR2101010:
10490 if (INTEL_INFO(dev)->gen < 4) {
10491 DRM_DEBUG("unsupported pixel format: %s\n",
10492 drm_get_format_name(mode_cmd->pixel_format));
10496 case DRM_FORMAT_YUYV:
10497 case DRM_FORMAT_UYVY:
10498 case DRM_FORMAT_YVYU:
10499 case DRM_FORMAT_VYUY:
10500 if (INTEL_INFO(dev)->gen < 5) {
10501 DRM_DEBUG("unsupported pixel format: %s\n",
10502 drm_get_format_name(mode_cmd->pixel_format));
10507 DRM_DEBUG("unsupported pixel format: %s\n",
10508 drm_get_format_name(mode_cmd->pixel_format));
10512 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10513 if (mode_cmd->offsets[0] != 0)
10516 tile_height = IS_GEN2(dev) ? 16 : 8;
10517 aligned_height = ALIGN(mode_cmd->height,
10518 obj->tiling_mode ? tile_height : 1);
10519 /* FIXME drm helper for size checks (especially planar formats)? */
10520 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10523 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10524 intel_fb->obj = obj;
10525 intel_fb->obj->framebuffer_references++;
10527 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10529 DRM_ERROR("framebuffer init failed %d\n", ret);
10536 static struct drm_framebuffer *
10537 intel_user_framebuffer_create(struct drm_device *dev,
10538 struct drm_file *filp,
10539 struct drm_mode_fb_cmd2 *mode_cmd)
10541 struct drm_i915_gem_object *obj;
10543 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10544 mode_cmd->handles[0]));
10545 if (&obj->base == NULL)
10546 return ERR_PTR(-ENOENT);
10548 return intel_framebuffer_create(dev, mode_cmd, obj);
10551 #ifndef CONFIG_DRM_I915_FBDEV
10552 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10557 static const struct drm_mode_config_funcs intel_mode_funcs = {
10558 .fb_create = intel_user_framebuffer_create,
10559 .output_poll_changed = intel_fbdev_output_poll_changed,
10562 /* Set up chip specific display functions */
10563 static void intel_init_display(struct drm_device *dev)
10565 struct drm_i915_private *dev_priv = dev->dev_private;
10567 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10568 dev_priv->display.find_dpll = g4x_find_best_dpll;
10569 else if (IS_VALLEYVIEW(dev))
10570 dev_priv->display.find_dpll = vlv_find_best_dpll;
10571 else if (IS_PINEVIEW(dev))
10572 dev_priv->display.find_dpll = pnv_find_best_dpll;
10574 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10576 if (HAS_DDI(dev)) {
10577 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10578 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10579 dev_priv->display.crtc_enable = haswell_crtc_enable;
10580 dev_priv->display.crtc_disable = haswell_crtc_disable;
10581 dev_priv->display.off = haswell_crtc_off;
10582 dev_priv->display.update_plane = ironlake_update_plane;
10583 } else if (HAS_PCH_SPLIT(dev)) {
10584 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10585 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10586 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10587 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10588 dev_priv->display.off = ironlake_crtc_off;
10589 dev_priv->display.update_plane = ironlake_update_plane;
10590 } else if (IS_VALLEYVIEW(dev)) {
10591 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10592 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10593 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10594 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10595 dev_priv->display.off = i9xx_crtc_off;
10596 dev_priv->display.update_plane = i9xx_update_plane;
10598 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10599 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10600 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10601 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10602 dev_priv->display.off = i9xx_crtc_off;
10603 dev_priv->display.update_plane = i9xx_update_plane;
10606 /* Returns the core display clock speed */
10607 if (IS_VALLEYVIEW(dev))
10608 dev_priv->display.get_display_clock_speed =
10609 valleyview_get_display_clock_speed;
10610 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10611 dev_priv->display.get_display_clock_speed =
10612 i945_get_display_clock_speed;
10613 else if (IS_I915G(dev))
10614 dev_priv->display.get_display_clock_speed =
10615 i915_get_display_clock_speed;
10616 else if (IS_I945GM(dev) || IS_845G(dev))
10617 dev_priv->display.get_display_clock_speed =
10618 i9xx_misc_get_display_clock_speed;
10619 else if (IS_PINEVIEW(dev))
10620 dev_priv->display.get_display_clock_speed =
10621 pnv_get_display_clock_speed;
10622 else if (IS_I915GM(dev))
10623 dev_priv->display.get_display_clock_speed =
10624 i915gm_get_display_clock_speed;
10625 else if (IS_I865G(dev))
10626 dev_priv->display.get_display_clock_speed =
10627 i865_get_display_clock_speed;
10628 else if (IS_I85X(dev))
10629 dev_priv->display.get_display_clock_speed =
10630 i855_get_display_clock_speed;
10631 else /* 852, 830 */
10632 dev_priv->display.get_display_clock_speed =
10633 i830_get_display_clock_speed;
10635 if (HAS_PCH_SPLIT(dev)) {
10636 if (IS_GEN5(dev)) {
10637 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10638 dev_priv->display.write_eld = ironlake_write_eld;
10639 } else if (IS_GEN6(dev)) {
10640 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10641 dev_priv->display.write_eld = ironlake_write_eld;
10642 } else if (IS_IVYBRIDGE(dev)) {
10643 /* FIXME: detect B0+ stepping and use auto training */
10644 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10645 dev_priv->display.write_eld = ironlake_write_eld;
10646 dev_priv->display.modeset_global_resources =
10647 ivb_modeset_global_resources;
10648 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10649 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10650 dev_priv->display.write_eld = haswell_write_eld;
10651 dev_priv->display.modeset_global_resources =
10652 haswell_modeset_global_resources;
10654 } else if (IS_G4X(dev)) {
10655 dev_priv->display.write_eld = g4x_write_eld;
10656 } else if (IS_VALLEYVIEW(dev)) {
10657 dev_priv->display.modeset_global_resources =
10658 valleyview_modeset_global_resources;
10659 dev_priv->display.write_eld = ironlake_write_eld;
10662 /* Default just returns -ENODEV to indicate unsupported */
10663 dev_priv->display.queue_flip = intel_default_queue_flip;
10665 switch (INTEL_INFO(dev)->gen) {
10667 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10671 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10676 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10680 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10683 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10684 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10688 intel_panel_init_backlight_funcs(dev);
10692 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10693 * resume, or other times. This quirk makes sure that's the case for
10694 * affected systems.
10696 static void quirk_pipea_force(struct drm_device *dev)
10698 struct drm_i915_private *dev_priv = dev->dev_private;
10700 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10701 DRM_INFO("applying pipe a force quirk\n");
10705 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10707 static void quirk_ssc_force_disable(struct drm_device *dev)
10709 struct drm_i915_private *dev_priv = dev->dev_private;
10710 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10711 DRM_INFO("applying lvds SSC disable quirk\n");
10715 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10718 static void quirk_invert_brightness(struct drm_device *dev)
10720 struct drm_i915_private *dev_priv = dev->dev_private;
10721 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10722 DRM_INFO("applying inverted panel brightness quirk\n");
10725 struct intel_quirk {
10727 int subsystem_vendor;
10728 int subsystem_device;
10729 void (*hook)(struct drm_device *dev);
10732 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10733 struct intel_dmi_quirk {
10734 void (*hook)(struct drm_device *dev);
10735 const struct dmi_system_id (*dmi_id_list)[];
10738 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10740 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10744 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10746 .dmi_id_list = &(const struct dmi_system_id[]) {
10748 .callback = intel_dmi_reverse_brightness,
10749 .ident = "NCR Corporation",
10750 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10751 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10754 { } /* terminating entry */
10756 .hook = quirk_invert_brightness,
10760 static struct intel_quirk intel_quirks[] = {
10761 /* HP Mini needs pipe A force quirk (LP: #322104) */
10762 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10764 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10765 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10767 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10768 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10770 /* 830 needs to leave pipe A & dpll A up */
10771 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10773 /* Lenovo U160 cannot use SSC on LVDS */
10774 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10776 /* Sony Vaio Y cannot use SSC on LVDS */
10777 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10780 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10781 * seem to use inverted backlight PWM.
10783 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10786 static void intel_init_quirks(struct drm_device *dev)
10788 struct pci_dev *d = dev->pdev;
10791 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10792 struct intel_quirk *q = &intel_quirks[i];
10794 if (d->device == q->device &&
10795 (d->subsystem_vendor == q->subsystem_vendor ||
10796 q->subsystem_vendor == PCI_ANY_ID) &&
10797 (d->subsystem_device == q->subsystem_device ||
10798 q->subsystem_device == PCI_ANY_ID))
10801 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10802 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10803 intel_dmi_quirks[i].hook(dev);
10807 /* Disable the VGA plane that we never use */
10808 static void i915_disable_vga(struct drm_device *dev)
10810 struct drm_i915_private *dev_priv = dev->dev_private;
10812 u32 vga_reg = i915_vgacntrl_reg(dev);
10814 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10815 outb(SR01, VGA_SR_INDEX);
10816 sr1 = inb(VGA_SR_DATA);
10817 outb(sr1 | 1<<5, VGA_SR_DATA);
10818 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10821 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10822 POSTING_READ(vga_reg);
10825 void intel_modeset_init_hw(struct drm_device *dev)
10827 intel_prepare_ddi(dev);
10829 intel_init_clock_gating(dev);
10831 intel_reset_dpio(dev);
10833 mutex_lock(&dev->struct_mutex);
10834 intel_enable_gt_powersave(dev);
10835 mutex_unlock(&dev->struct_mutex);
10838 void intel_modeset_suspend_hw(struct drm_device *dev)
10840 intel_suspend_hw(dev);
10843 void intel_modeset_init(struct drm_device *dev)
10845 struct drm_i915_private *dev_priv = dev->dev_private;
10848 drm_mode_config_init(dev);
10850 dev->mode_config.min_width = 0;
10851 dev->mode_config.min_height = 0;
10853 dev->mode_config.preferred_depth = 24;
10854 dev->mode_config.prefer_shadow = 1;
10856 dev->mode_config.funcs = &intel_mode_funcs;
10858 intel_init_quirks(dev);
10860 intel_init_pm(dev);
10862 if (INTEL_INFO(dev)->num_pipes == 0)
10865 intel_init_display(dev);
10867 if (IS_GEN2(dev)) {
10868 dev->mode_config.max_width = 2048;
10869 dev->mode_config.max_height = 2048;
10870 } else if (IS_GEN3(dev)) {
10871 dev->mode_config.max_width = 4096;
10872 dev->mode_config.max_height = 4096;
10874 dev->mode_config.max_width = 8192;
10875 dev->mode_config.max_height = 8192;
10877 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10879 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10880 INTEL_INFO(dev)->num_pipes,
10881 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10884 intel_crtc_init(dev, i);
10885 for (j = 0; j < dev_priv->num_plane; j++) {
10886 ret = intel_plane_init(dev, i, j);
10888 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10889 pipe_name(i), sprite_name(i, j), ret);
10893 intel_init_dpio(dev);
10894 intel_reset_dpio(dev);
10896 intel_cpu_pll_init(dev);
10897 intel_shared_dpll_init(dev);
10899 /* Just disable it once at startup */
10900 i915_disable_vga(dev);
10901 intel_setup_outputs(dev);
10903 /* Just in case the BIOS is doing something questionable. */
10904 intel_disable_fbc(dev);
10908 intel_connector_break_all_links(struct intel_connector *connector)
10910 connector->base.dpms = DRM_MODE_DPMS_OFF;
10911 connector->base.encoder = NULL;
10912 connector->encoder->connectors_active = false;
10913 connector->encoder->base.crtc = NULL;
10916 static void intel_enable_pipe_a(struct drm_device *dev)
10918 struct intel_connector *connector;
10919 struct drm_connector *crt = NULL;
10920 struct intel_load_detect_pipe load_detect_temp;
10922 /* We can't just switch on the pipe A, we need to set things up with a
10923 * proper mode and output configuration. As a gross hack, enable pipe A
10924 * by enabling the load detect pipe once. */
10925 list_for_each_entry(connector,
10926 &dev->mode_config.connector_list,
10928 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10929 crt = &connector->base;
10937 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10938 intel_release_load_detect_pipe(crt, &load_detect_temp);
10944 intel_check_plane_mapping(struct intel_crtc *crtc)
10946 struct drm_device *dev = crtc->base.dev;
10947 struct drm_i915_private *dev_priv = dev->dev_private;
10950 if (INTEL_INFO(dev)->num_pipes == 1)
10953 reg = DSPCNTR(!crtc->plane);
10954 val = I915_READ(reg);
10956 if ((val & DISPLAY_PLANE_ENABLE) &&
10957 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10963 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10965 struct drm_device *dev = crtc->base.dev;
10966 struct drm_i915_private *dev_priv = dev->dev_private;
10969 /* Clear any frame start delays used for debugging left by the BIOS */
10970 reg = PIPECONF(crtc->config.cpu_transcoder);
10971 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10973 /* We need to sanitize the plane -> pipe mapping first because this will
10974 * disable the crtc (and hence change the state) if it is wrong. Note
10975 * that gen4+ has a fixed plane -> pipe mapping. */
10976 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10977 struct intel_connector *connector;
10980 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10981 crtc->base.base.id);
10983 /* Pipe has the wrong plane attached and the plane is active.
10984 * Temporarily change the plane mapping and disable everything
10986 plane = crtc->plane;
10987 crtc->plane = !plane;
10988 dev_priv->display.crtc_disable(&crtc->base);
10989 crtc->plane = plane;
10991 /* ... and break all links. */
10992 list_for_each_entry(connector, &dev->mode_config.connector_list,
10994 if (connector->encoder->base.crtc != &crtc->base)
10997 intel_connector_break_all_links(connector);
11000 WARN_ON(crtc->active);
11001 crtc->base.enabled = false;
11004 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11005 crtc->pipe == PIPE_A && !crtc->active) {
11006 /* BIOS forgot to enable pipe A, this mostly happens after
11007 * resume. Force-enable the pipe to fix this, the update_dpms
11008 * call below we restore the pipe to the right state, but leave
11009 * the required bits on. */
11010 intel_enable_pipe_a(dev);
11013 /* Adjust the state of the output pipe according to whether we
11014 * have active connectors/encoders. */
11015 intel_crtc_update_dpms(&crtc->base);
11017 if (crtc->active != crtc->base.enabled) {
11018 struct intel_encoder *encoder;
11020 /* This can happen either due to bugs in the get_hw_state
11021 * functions or because the pipe is force-enabled due to the
11023 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11024 crtc->base.base.id,
11025 crtc->base.enabled ? "enabled" : "disabled",
11026 crtc->active ? "enabled" : "disabled");
11028 crtc->base.enabled = crtc->active;
11030 /* Because we only establish the connector -> encoder ->
11031 * crtc links if something is active, this means the
11032 * crtc is now deactivated. Break the links. connector
11033 * -> encoder links are only establish when things are
11034 * actually up, hence no need to break them. */
11035 WARN_ON(crtc->active);
11037 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11038 WARN_ON(encoder->connectors_active);
11039 encoder->base.crtc = NULL;
11044 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11046 struct intel_connector *connector;
11047 struct drm_device *dev = encoder->base.dev;
11049 /* We need to check both for a crtc link (meaning that the
11050 * encoder is active and trying to read from a pipe) and the
11051 * pipe itself being active. */
11052 bool has_active_crtc = encoder->base.crtc &&
11053 to_intel_crtc(encoder->base.crtc)->active;
11055 if (encoder->connectors_active && !has_active_crtc) {
11056 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11057 encoder->base.base.id,
11058 drm_get_encoder_name(&encoder->base));
11060 /* Connector is active, but has no active pipe. This is
11061 * fallout from our resume register restoring. Disable
11062 * the encoder manually again. */
11063 if (encoder->base.crtc) {
11064 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11065 encoder->base.base.id,
11066 drm_get_encoder_name(&encoder->base));
11067 encoder->disable(encoder);
11070 /* Inconsistent output/port/pipe state happens presumably due to
11071 * a bug in one of the get_hw_state functions. Or someplace else
11072 * in our code, like the register restore mess on resume. Clamp
11073 * things to off as a safer default. */
11074 list_for_each_entry(connector,
11075 &dev->mode_config.connector_list,
11077 if (connector->encoder != encoder)
11080 intel_connector_break_all_links(connector);
11083 /* Enabled encoders without active connectors will be fixed in
11084 * the crtc fixup. */
11087 void i915_redisable_vga(struct drm_device *dev)
11089 struct drm_i915_private *dev_priv = dev->dev_private;
11090 u32 vga_reg = i915_vgacntrl_reg(dev);
11092 /* This function can be called both from intel_modeset_setup_hw_state or
11093 * at a very early point in our resume sequence, where the power well
11094 * structures are not yet restored. Since this function is at a very
11095 * paranoid "someone might have enabled VGA while we were not looking"
11096 * level, just check if the power well is enabled instead of trying to
11097 * follow the "don't touch the power well if we don't need it" policy
11098 * the rest of the driver uses. */
11099 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11100 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11103 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11104 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11105 i915_disable_vga(dev);
11109 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11111 struct drm_i915_private *dev_priv = dev->dev_private;
11113 struct intel_crtc *crtc;
11114 struct intel_encoder *encoder;
11115 struct intel_connector *connector;
11118 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11120 memset(&crtc->config, 0, sizeof(crtc->config));
11122 crtc->active = dev_priv->display.get_pipe_config(crtc,
11125 crtc->base.enabled = crtc->active;
11126 crtc->primary_enabled = crtc->active;
11128 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11129 crtc->base.base.id,
11130 crtc->active ? "enabled" : "disabled");
11133 /* FIXME: Smash this into the new shared dpll infrastructure. */
11135 intel_ddi_setup_hw_pll_state(dev);
11137 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11138 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11140 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11142 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11144 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11147 pll->refcount = pll->active;
11149 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11150 pll->name, pll->refcount, pll->on);
11153 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11157 if (encoder->get_hw_state(encoder, &pipe)) {
11158 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11159 encoder->base.crtc = &crtc->base;
11160 encoder->get_config(encoder, &crtc->config);
11162 encoder->base.crtc = NULL;
11165 encoder->connectors_active = false;
11166 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11167 encoder->base.base.id,
11168 drm_get_encoder_name(&encoder->base),
11169 encoder->base.crtc ? "enabled" : "disabled",
11173 list_for_each_entry(connector, &dev->mode_config.connector_list,
11175 if (connector->get_hw_state(connector)) {
11176 connector->base.dpms = DRM_MODE_DPMS_ON;
11177 connector->encoder->connectors_active = true;
11178 connector->base.encoder = &connector->encoder->base;
11180 connector->base.dpms = DRM_MODE_DPMS_OFF;
11181 connector->base.encoder = NULL;
11183 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11184 connector->base.base.id,
11185 drm_get_connector_name(&connector->base),
11186 connector->base.encoder ? "enabled" : "disabled");
11190 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11191 * and i915 state tracking structures. */
11192 void intel_modeset_setup_hw_state(struct drm_device *dev,
11193 bool force_restore)
11195 struct drm_i915_private *dev_priv = dev->dev_private;
11197 struct intel_crtc *crtc;
11198 struct intel_encoder *encoder;
11201 intel_modeset_readout_hw_state(dev);
11204 * Now that we have the config, copy it to each CRTC struct
11205 * Note that this could go away if we move to using crtc_config
11206 * checking everywhere.
11208 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11210 if (crtc->active && i915_fastboot) {
11211 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11213 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11214 crtc->base.base.id);
11215 drm_mode_debug_printmodeline(&crtc->base.mode);
11219 /* HW state is read out, now we need to sanitize this mess. */
11220 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11222 intel_sanitize_encoder(encoder);
11225 for_each_pipe(pipe) {
11226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11227 intel_sanitize_crtc(crtc);
11228 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11231 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11232 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11234 if (!pll->on || pll->active)
11237 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11239 pll->disable(dev_priv, pll);
11243 if (HAS_PCH_SPLIT(dev))
11244 ilk_wm_get_hw_state(dev);
11246 if (force_restore) {
11247 i915_redisable_vga(dev);
11250 * We need to use raw interfaces for restoring state to avoid
11251 * checking (bogus) intermediate states.
11253 for_each_pipe(pipe) {
11254 struct drm_crtc *crtc =
11255 dev_priv->pipe_to_crtc_mapping[pipe];
11257 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11261 intel_modeset_update_staged_output_state(dev);
11264 intel_modeset_check_state(dev);
11266 drm_mode_config_reset(dev);
11269 void intel_modeset_gem_init(struct drm_device *dev)
11271 intel_modeset_init_hw(dev);
11273 intel_setup_overlay(dev);
11275 intel_modeset_setup_hw_state(dev, false);
11278 void intel_modeset_cleanup(struct drm_device *dev)
11280 struct drm_i915_private *dev_priv = dev->dev_private;
11281 struct drm_crtc *crtc;
11282 struct drm_connector *connector;
11285 * Interrupts and polling as the first thing to avoid creating havoc.
11286 * Too much stuff here (turning of rps, connectors, ...) would
11287 * experience fancy races otherwise.
11289 drm_irq_uninstall(dev);
11290 cancel_work_sync(&dev_priv->hotplug_work);
11292 * Due to the hpd irq storm handling the hotplug work can re-arm the
11293 * poll handlers. Hence disable polling after hpd handling is shut down.
11295 drm_kms_helper_poll_fini(dev);
11297 mutex_lock(&dev->struct_mutex);
11299 intel_unregister_dsm_handler();
11301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11302 /* Skip inactive CRTCs */
11306 intel_increase_pllclock(crtc);
11309 intel_disable_fbc(dev);
11311 intel_disable_gt_powersave(dev);
11313 ironlake_teardown_rc6(dev);
11315 mutex_unlock(&dev->struct_mutex);
11317 /* flush any delayed tasks or pending work */
11318 flush_scheduled_work();
11320 /* destroy the backlight and sysfs files before encoders/connectors */
11321 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11322 intel_panel_destroy_backlight(connector);
11323 drm_sysfs_connector_remove(connector);
11326 drm_mode_config_cleanup(dev);
11328 intel_cleanup_overlay(dev);
11332 * Return which encoder is currently attached for connector.
11334 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11336 return &intel_attached_encoder(connector)->base;
11339 void intel_connector_attach_encoder(struct intel_connector *connector,
11340 struct intel_encoder *encoder)
11342 connector->encoder = encoder;
11343 drm_mode_connector_attach_encoder(&connector->base,
11348 * set vga decode state - true == enable VGA decode
11350 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11352 struct drm_i915_private *dev_priv = dev->dev_private;
11355 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11357 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11359 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11360 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11364 struct intel_display_error_state {
11366 u32 power_well_driver;
11368 int num_transcoders;
11370 struct intel_cursor_error_state {
11375 } cursor[I915_MAX_PIPES];
11377 struct intel_pipe_error_state {
11378 bool power_domain_on;
11380 } pipe[I915_MAX_PIPES];
11382 struct intel_plane_error_state {
11390 } plane[I915_MAX_PIPES];
11392 struct intel_transcoder_error_state {
11393 bool power_domain_on;
11394 enum transcoder cpu_transcoder;
11407 struct intel_display_error_state *
11408 intel_display_capture_error_state(struct drm_device *dev)
11410 drm_i915_private_t *dev_priv = dev->dev_private;
11411 struct intel_display_error_state *error;
11412 int transcoders[] = {
11420 if (INTEL_INFO(dev)->num_pipes == 0)
11423 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11427 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11428 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11431 error->pipe[i].power_domain_on =
11432 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11433 if (!error->pipe[i].power_domain_on)
11436 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11437 error->cursor[i].control = I915_READ(CURCNTR(i));
11438 error->cursor[i].position = I915_READ(CURPOS(i));
11439 error->cursor[i].base = I915_READ(CURBASE(i));
11441 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11442 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11443 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11446 error->plane[i].control = I915_READ(DSPCNTR(i));
11447 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11448 if (INTEL_INFO(dev)->gen <= 3) {
11449 error->plane[i].size = I915_READ(DSPSIZE(i));
11450 error->plane[i].pos = I915_READ(DSPPOS(i));
11452 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11453 error->plane[i].addr = I915_READ(DSPADDR(i));
11454 if (INTEL_INFO(dev)->gen >= 4) {
11455 error->plane[i].surface = I915_READ(DSPSURF(i));
11456 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11459 error->pipe[i].source = I915_READ(PIPESRC(i));
11462 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11463 if (HAS_DDI(dev_priv->dev))
11464 error->num_transcoders++; /* Account for eDP. */
11466 for (i = 0; i < error->num_transcoders; i++) {
11467 enum transcoder cpu_transcoder = transcoders[i];
11469 error->transcoder[i].power_domain_on =
11470 intel_display_power_enabled_sw(dev,
11471 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11472 if (!error->transcoder[i].power_domain_on)
11475 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11477 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11478 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11479 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11480 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11481 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11482 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11483 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11489 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11492 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11493 struct drm_device *dev,
11494 struct intel_display_error_state *error)
11501 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11502 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11503 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11504 error->power_well_driver);
11506 err_printf(m, "Pipe [%d]:\n", i);
11507 err_printf(m, " Power: %s\n",
11508 error->pipe[i].power_domain_on ? "on" : "off");
11509 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11511 err_printf(m, "Plane [%d]:\n", i);
11512 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11513 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11514 if (INTEL_INFO(dev)->gen <= 3) {
11515 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11516 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11518 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11519 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11520 if (INTEL_INFO(dev)->gen >= 4) {
11521 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11522 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11525 err_printf(m, "Cursor [%d]:\n", i);
11526 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11527 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11528 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11531 for (i = 0; i < error->num_transcoders; i++) {
11532 err_printf(m, "CPU transcoder: %c\n",
11533 transcoder_name(error->transcoder[i].cpu_transcoder));
11534 err_printf(m, " Power: %s\n",
11535 error->transcoder[i].power_domain_on ? "on" : "off");
11536 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11537 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11538 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11539 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11540 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11541 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11542 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);