drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 908000, .max = 1512000 },
  94         .n = { .min = 2, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 908000, .max = 1512000 },
 107         .n = { .min = 2, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 908000, .max = 1512000 },
 120         .n = { .min = 2, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         if (WARN_ON(clock->n == 0 || clock->p == 0))
 333                 return;
 334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 336 }
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 limit = &intel_limits_vlv;
 414         } else if (!IS_GEN2(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 416                         limit = &intel_limits_i9xx_lvds;
 417                 else
 418                         limit = &intel_limits_i9xx_sdvo;
 419         } else {
 420                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 421                         limit = &intel_limits_i8xx_lvds;
 422                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 423                         limit = &intel_limits_i8xx_dvo;
 424                 else
 425                         limit = &intel_limits_i8xx_dac;
 426         }
 427         return limit;
 428 }
 429
 430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 431 static void pineview_clock(int refclk, intel_clock_t *clock)
 432 {
 433         clock->m = clock->m2 + 2;
 434         clock->p = clock->p1 * clock->p2;
 435         if (WARN_ON(clock->n == 0 || clock->p == 0))
 436                 return;
 437         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 438         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 439 }
 440
 441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 442 {
 443         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 444 }
 445
 446 static void i9xx_clock(int refclk, intel_clock_t *clock)
 447 {
 448         clock->m = i9xx_dpll_compute_m(clock);
 449         clock->p = clock->p1 * clock->p2;
 450         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 451                 return;
 452         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 453         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 467                 INTELPllInvalid("n out of range\n");
 468         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 469                 INTELPllInvalid("p1 out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474
 475         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 476                 if (clock->m1 <= clock->m2)
 477                         INTELPllInvalid("m1 <= m2\n");
 478
 479         if (!IS_VALLEYVIEW(dev)) {
 480                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 481                         INTELPllInvalid("p out of range\n");
 482                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 483                         INTELPllInvalid("m out of range\n");
 484         }
 485
 486         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 487                 INTELPllInvalid("vco out of range\n");
 488         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 489          * connector, etc., rather than just a single range.
 490          */
 491         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 492                 INTELPllInvalid("dot out of range\n");
 493
 494         return true;
 495 }
 496
 497 static bool
 498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 499                     int target, int refclk, intel_clock_t *match_clock,
 500                     intel_clock_t *best_clock)
 501 {
 502         struct drm_device *dev = crtc->dev;
 503         intel_clock_t clock;
 504         int err = target;
 505
 506         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 507                 /*
 508                  * For LVDS just rely on its current settings for dual-channel.
 509                  * We haven't figured out how to reliably set up different
 510                  * single/dual channel state, if we even can.
 511                  */
 512                 if (intel_is_dual_link_lvds(dev))
 513                         clock.p2 = limit->p2.p2_fast;
 514                 else
 515                         clock.p2 = limit->p2.p2_slow;
 516         } else {
 517                 if (target < limit->p2.dot_limit)
 518                         clock.p2 = limit->p2.p2_slow;
 519                 else
 520                         clock.p2 = limit->p2.p2_fast;
 521         }
 522
 523         memset(best_clock, 0, sizeof(*best_clock));
 524
 525         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 526              clock.m1++) {
 527                 for (clock.m2 = limit->m2.min;
 528                      clock.m2 <= limit->m2.max; clock.m2++) {
 529                         if (clock.m2 >= clock.m1)
 530                                 break;
 531                         for (clock.n = limit->n.min;
 532                              clock.n <= limit->n.max; clock.n++) {
 533                                 for (clock.p1 = limit->p1.min;
 534                                         clock.p1 <= limit->p1.max; clock.p1++) {
 535                                         int this_err;
 536
 537                                         i9xx_clock(refclk, &clock);
 538                                         if (!intel_PLL_is_valid(dev, limit,
 539                                                                 &clock))
 540                                                 continue;
 541                                         if (match_clock &&
 542                                             clock.p != match_clock->p)
 543                                                 continue;
 544
 545                                         this_err = abs(clock.dot - target);
 546                                         if (this_err < err) {
 547                                                 *best_clock = clock;
 548                                                 err = this_err;
 549                                         }
 550                                 }
 551                         }
 552                 }
 553         }
 554
 555         return (err != target);
 556 }
 557
 558 static bool
 559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 560                    int target, int refclk, intel_clock_t *match_clock,
 561                    intel_clock_t *best_clock)
 562 {
 563         struct drm_device *dev = crtc->dev;
 564         intel_clock_t clock;
 565         int err = target;
 566
 567         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 568                 /*
 569                  * For LVDS just rely on its current settings for dual-channel.
 570                  * We haven't figured out how to reliably set up different
 571                  * single/dual channel state, if we even can.
 572                  */
 573                 if (intel_is_dual_link_lvds(dev))
 574                         clock.p2 = limit->p2.p2_fast;
 575                 else
 576                         clock.p2 = limit->p2.p2_slow;
 577         } else {
 578                 if (target < limit->p2.dot_limit)
 579                         clock.p2 = limit->p2.p2_slow;
 580                 else
 581                         clock.p2 = limit->p2.p2_fast;
 582         }
 583
 584         memset(best_clock, 0, sizeof(*best_clock));
 585
 586         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 587              clock.m1++) {
 588                 for (clock.m2 = limit->m2.min;
 589                      clock.m2 <= limit->m2.max; clock.m2++) {
 590                         for (clock.n = limit->n.min;
 591                              clock.n <= limit->n.max; clock.n++) {
 592                                 for (clock.p1 = limit->p1.min;
 593                                         clock.p1 <= limit->p1.max; clock.p1++) {
 594                                         int this_err;
 595
 596                                         pineview_clock(refclk, &clock);
 597                                         if (!intel_PLL_is_valid(dev, limit,
 598                                                                 &clock))
 599                                                 continue;
 600                                         if (match_clock &&
 601                                             clock.p != match_clock->p)
 602                                                 continue;
 603
 604                                         this_err = abs(clock.dot - target);
 605                                         if (this_err < err) {
 606                                                 *best_clock = clock;
 607                                                 err = this_err;
 608                                         }
 609                                 }
 610                         }
 611                 }
 612         }
 613
 614         return (err != target);
 615 }
 616
 617 static bool
 618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                    int target, int refclk, intel_clock_t *match_clock,
 620                    intel_clock_t *best_clock)
 621 {
 622         struct drm_device *dev = crtc->dev;
 623         intel_clock_t clock;
 624         int max_n;
 625         bool found;
 626         /* approximately equals target * 0.00585 */
 627         int err_most = (target >> 8) + (target >> 9);
 628         found = false;
 629
 630         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 631                 if (intel_is_dual_link_lvds(dev))
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         i9xx_clock(refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659
 660                                         this_err = abs(clock.dot - target);
 661                                         if (this_err < err_most) {
 662                                                 *best_clock = clock;
 663                                                 err_most = this_err;
 664                                                 max_n = clock.n;
 665                                                 found = true;
 666                                         }
 667                                 }
 668                         }
 669                 }
 670         }
 671         return found;
 672 }
 673
 674 static bool
 675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                    int target, int refclk, intel_clock_t *match_clock,
 677                    intel_clock_t *best_clock)
 678 {
 679         struct drm_device *dev = crtc->dev;
 680         intel_clock_t clock;
 681         unsigned int bestppm = 1000000;
 682         /* min update 19.2 MHz */
 683         int max_n = min(limit->n.max, refclk / 19200);
 684         bool found = false;
 685
 686         target *= 5; /* fast clock */
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         /* based on hardware requirement, prefer smaller n to precision */
 691         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 692                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 693                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 694                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 695                                 clock.p = clock.p1 * clock.p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 698                                         unsigned int ppm, diff;
 699
 700                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 701                                                                      refclk * clock.m1);
 702
 703                                         vlv_clock(refclk, &clock);
 704
 705                                         if (!intel_PLL_is_valid(dev, limit,
 706                                                                 &clock))
 707                                                 continue;
 708
 709                                         diff = abs(clock.dot - target);
 710                                         ppm = div_u64(1000000ULL * diff, target);
 711
 712                                         if (ppm < 100 && clock.p > best_clock->p) {
 713                                                 bestppm = 0;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717
 718                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 719                                                 bestppm = ppm;
 720                                                 *best_clock = clock;
 721                                                 found = true;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727
 728         return found;
 729 }
 730
 731 bool intel_crtc_active(struct drm_crtc *crtc)
 732 {
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         /* Be paranoid as we can arrive here with only partial
 736          * state retrieved from the hardware during setup.
 737          *
 738          * We can ditch the adjusted_mode.crtc_clock check as soon
 739          * as Haswell has gained clock readout/fastboot support.
 740          *
 741          * We can ditch the crtc->fb check as soon as we can
 742          * properly reconstruct framebuffers.
 743          */
 744         return intel_crtc->active && crtc->fb &&
 745                 intel_crtc->config.adjusted_mode.crtc_clock;
 746 }
 747
 748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 749                                              enum pipe pipe)
 750 {
 751         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 753
 754         return intel_crtc->config.cpu_transcoder;
 755 }
 756
 757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 761
 762         frame = I915_READ(frame_reg);
 763
 764         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 765                 DRM_DEBUG_KMS("vblank wait timed out\n");
 766 }
 767
 768 /**
 769  * intel_wait_for_vblank - wait for vblank on a given pipe
 770  * @dev: drm device
 771  * @pipe: pipe to wait for
 772  *
 773  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 774  * mode setting code.
 775  */
 776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         int pipestat_reg = PIPESTAT(pipe);
 780
 781         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 782                 g4x_wait_for_vblank(dev, pipe);
 783                 return;
 784         }
 785
 786         /* Clear existing vblank status. Note this will clear any other
 787          * sticky status fields as well.
 788          *
 789          * This races with i915_driver_irq_handler() with the result
 790          * that either function could miss a vblank event.  Here it is not
 791          * fatal, as we will either wait upon the next vblank interrupt or
 792          * timeout.  Generally speaking intel_wait_for_vblank() is only
 793          * called during modeset at which time the GPU should be idle and
 794          * should *not* be performing page flips and thus not waiting on
 795          * vblanks...
 796          * Currently, the result of us stealing a vblank from the irq
 797          * handler is that a single frame will be skipped during swapbuffers.
 798          */
 799         I915_WRITE(pipestat_reg,
 800                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 801
 802         /* Wait for vblank interrupt bit to set */
 803         if (wait_for(I915_READ(pipestat_reg) &
 804                      PIPE_VBLANK_INTERRUPT_STATUS,
 805                      50))
 806                 DRM_DEBUG_KMS("vblank wait timed out\n");
 807 }
 808
 809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         u32 reg = PIPEDSL(pipe);
 813         u32 line1, line2;
 814         u32 line_mask;
 815
 816         if (IS_GEN2(dev))
 817                 line_mask = DSL_LINEMASK_GEN2;
 818         else
 819                 line_mask = DSL_LINEMASK_GEN3;
 820
 821         line1 = I915_READ(reg) & line_mask;
 822         mdelay(5);
 823         line2 = I915_READ(reg) & line_mask;
 824
 825         return line1 == line2;
 826 }
 827
 828 /*
 829  * intel_wait_for_pipe_off - wait for pipe to turn off
 830  * @dev: drm device
 831  * @pipe: pipe to wait for
 832  *
 833  * After disabling a pipe, we can't wait for vblank in the usual way,
 834  * spinning on the vblank interrupt status bit, since we won't actually
 835  * see an interrupt when the pipe is disabled.
 836  *
 837  * On Gen4 and above:
 838  *   wait for the pipe register state bit to turn off
 839  *
 840  * Otherwise:
 841  *   wait for the display line value to settle (it usually
 842  *   ends up stopping at the start of the next frame).
 843  *
 844  */
 845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 849                                                                       pipe);
 850
 851         if (INTEL_INFO(dev)->gen >= 4) {
 852                 int reg = PIPECONF(cpu_transcoder);
 853
 854                 /* Wait for the Pipe State to go off */
 855                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 856                              100))
 857                         WARN(1, "pipe_off wait timed out\n");
 858         } else {
 859                 /* Wait for the display line to settle */
 860                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1220
1221         val = I915_READ(PCH_DREF_CONTROL);
1222         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1223                             DREF_SUPERSPREAD_SOURCE_MASK));
1224         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1225 }
1226
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228                                            enum pipe pipe)
1229 {
1230         int reg;
1231         u32 val;
1232         bool enabled;
1233
1234         reg = PCH_TRANSCONF(pipe);
1235         val = I915_READ(reg);
1236         enabled = !!(val & TRANS_ENABLE);
1237         WARN(enabled,
1238              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239              pipe_name(pipe));
1240 }
1241
1242 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1243                             enum pipe pipe, u32 port_sel, u32 val)
1244 {
1245         if ((val & DP_PORT_EN) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1250                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1251                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1252                         return false;
1253         } else {
1254                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1255                         return false;
1256         }
1257         return true;
1258 }
1259
1260 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1261                               enum pipe pipe, u32 val)
1262 {
1263         if ((val & SDVO_ENABLE) == 0)
1264                 return false;
1265
1266         if (HAS_PCH_CPT(dev_priv->dev)) {
1267                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1268                         return false;
1269         } else {
1270                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1271                         return false;
1272         }
1273         return true;
1274 }
1275
1276 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1277                               enum pipe pipe, u32 val)
1278 {
1279         if ((val & LVDS_PORT_EN) == 0)
1280                 return false;
1281
1282         if (HAS_PCH_CPT(dev_priv->dev)) {
1283                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284                         return false;
1285         } else {
1286                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1287                         return false;
1288         }
1289         return true;
1290 }
1291
1292 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1293                               enum pipe pipe, u32 val)
1294 {
1295         if ((val & ADPA_DAC_ENABLE) == 0)
1296                 return false;
1297         if (HAS_PCH_CPT(dev_priv->dev)) {
1298                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1299                         return false;
1300         } else {
1301                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1302                         return false;
1303         }
1304         return true;
1305 }
1306
1307 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1308                                    enum pipe pipe, int reg, u32 port_sel)
1309 {
1310         u32 val = I915_READ(reg);
1311         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1312              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313              reg, pipe_name(pipe));
1314
1315         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1316              && (val & DP_PIPEB_SELECT),
1317              "IBX PCH dp port still using transcoder B\n");
1318 }
1319
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1321                                      enum pipe pipe, int reg)
1322 {
1323         u32 val = I915_READ(reg);
1324         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1325              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326              reg, pipe_name(pipe));
1327
1328         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1329              && (val & SDVO_PIPE_B_SELECT),
1330              "IBX PCH hdmi port still using transcoder B\n");
1331 }
1332
1333 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1334                                       enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val;
1338
1339         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1340         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1341         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1342
1343         reg = PCH_ADPA;
1344         val = I915_READ(reg);
1345         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1346              "PCH VGA enabled on transcoder %c, should be disabled\n",
1347              pipe_name(pipe));
1348
1349         reg = PCH_LVDS;
1350         val = I915_READ(reg);
1351         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1352              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1353              pipe_name(pipe));
1354
1355         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1356         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1357         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1358 }
1359
1360 static void intel_init_dpio(struct drm_device *dev)
1361 {
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363
1364         if (!IS_VALLEYVIEW(dev))
1365                 return;
1366
1367         /* Enable the CRI clock source so we can get at the display */
1368         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1369                    DPLL_INTEGRATED_CRI_CLK_VLV);
1370
1371         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1372 }
1373
1374 static void intel_reset_dpio(struct drm_device *dev)
1375 {
1376         struct drm_i915_private *dev_priv = dev->dev_private;
1377
1378         if (!IS_VALLEYVIEW(dev))
1379                 return;
1380
1381         /*
1382          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1383          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1384          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1385          *   b. The other bits such as sfr settings / modesel may all be set
1386          *      to 0.
1387          *
1388          * This should only be done on init and resume from S3 with both
1389          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1390          */
1391         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1392 }
1393
1394 static void vlv_enable_pll(struct intel_crtc *crtc)
1395 {
1396         struct drm_device *dev = crtc->base.dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         int reg = DPLL(crtc->pipe);
1399         u32 dpll = crtc->config.dpll_hw_state.dpll;
1400
1401         assert_pipe_disabled(dev_priv, crtc->pipe);
1402
1403         /* No really, not for ILK+ */
1404         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1405
1406         /* PLL is protected by panel, make sure we can write it */
1407         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1408                 assert_panel_unlocked(dev_priv, crtc->pipe);
1409
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150);
1413
1414         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1415                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1416
1417         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1418         POSTING_READ(DPLL_MD(crtc->pipe));
1419
1420         /* We do this three times for luck */
1421         I915_WRITE(reg, dpll);
1422         POSTING_READ(reg);
1423         udelay(150); /* wait for warmup */
1424         I915_WRITE(reg, dpll);
1425         POSTING_READ(reg);
1426         udelay(150); /* wait for warmup */
1427         I915_WRITE(reg, dpll);
1428         POSTING_READ(reg);
1429         udelay(150); /* wait for warmup */
1430 }
1431
1432 static void i9xx_enable_pll(struct intel_crtc *crtc)
1433 {
1434         struct drm_device *dev = crtc->base.dev;
1435         struct drm_i915_private *dev_priv = dev->dev_private;
1436         int reg = DPLL(crtc->pipe);
1437         u32 dpll = crtc->config.dpll_hw_state.dpll;
1438
1439         assert_pipe_disabled(dev_priv, crtc->pipe);
1440
1441         /* No really, not for ILK+ */
1442         BUG_ON(dev_priv->info->gen >= 5);
1443
1444         /* PLL is protected by panel, make sure we can write it */
1445         if (IS_MOBILE(dev) && !IS_I830(dev))
1446                 assert_panel_unlocked(dev_priv, crtc->pipe);
1447
1448         I915_WRITE(reg, dpll);
1449
1450         /* Wait for the clocks to stabilize. */
1451         POSTING_READ(reg);
1452         udelay(150);
1453
1454         if (INTEL_INFO(dev)->gen >= 4) {
1455                 I915_WRITE(DPLL_MD(crtc->pipe),
1456                            crtc->config.dpll_hw_state.dpll_md);
1457         } else {
1458                 /* The pixel multiplier can only be updated once the
1459                  * DPLL is enabled and the clocks are stable.
1460                  *
1461                  * So write it again.
1462                  */
1463                 I915_WRITE(reg, dpll);
1464         }
1465
1466         /* We do this three times for luck */
1467         I915_WRITE(reg, dpll);
1468         POSTING_READ(reg);
1469         udelay(150); /* wait for warmup */
1470         I915_WRITE(reg, dpll);
1471         POSTING_READ(reg);
1472         udelay(150); /* wait for warmup */
1473         I915_WRITE(reg, dpll);
1474         POSTING_READ(reg);
1475         udelay(150); /* wait for warmup */
1476 }
1477
1478 /**
1479  * i9xx_disable_pll - disable a PLL
1480  * @dev_priv: i915 private structure
1481  * @pipe: pipe PLL to disable
1482  *
1483  * Disable the PLL for @pipe, making sure the pipe is off first.
1484  *
1485  * Note!  This is for pre-ILK only.
1486  */
1487 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1488 {
1489         /* Don't disable pipe A or pipe A PLLs if needed */
1490         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1491                 return;
1492
1493         /* Make sure the pipe isn't still relying on us */
1494         assert_pipe_disabled(dev_priv, pipe);
1495
1496         I915_WRITE(DPLL(pipe), 0);
1497         POSTING_READ(DPLL(pipe));
1498 }
1499
1500 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1501 {
1502         u32 val = 0;
1503
1504         /* Make sure the pipe isn't still relying on us */
1505         assert_pipe_disabled(dev_priv, pipe);
1506
1507         /* Leave integrated clock source enabled */
1508         if (pipe == PIPE_B)
1509                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1510         I915_WRITE(DPLL(pipe), val);
1511         POSTING_READ(DPLL(pipe));
1512 }
1513
1514 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1515                 struct intel_digital_port *dport)
1516 {
1517         u32 port_mask;
1518
1519         switch (dport->port) {
1520         case PORT_B:
1521                 port_mask = DPLL_PORTB_READY_MASK;
1522                 break;
1523         case PORT_C:
1524                 port_mask = DPLL_PORTC_READY_MASK;
1525                 break;
1526         default:
1527                 BUG();
1528         }
1529
1530         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1531                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1532                      port_name(dport->port), I915_READ(DPLL(0)));
1533 }
1534
1535 /**
1536  * ironlake_enable_shared_dpll - enable PCH PLL
1537  * @dev_priv: i915 private structure
1538  * @pipe: pipe PLL to enable
1539  *
1540  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1541  * drives the transcoder clock.
1542  */
1543 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1544 {
1545         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1546         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1547
1548         /* PCH PLLs only available on ILK, SNB and IVB */
1549         BUG_ON(dev_priv->info->gen < 5);
1550         if (WARN_ON(pll == NULL))
1551                 return;
1552
1553         if (WARN_ON(pll->refcount == 0))
1554                 return;
1555
1556         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1557                       pll->name, pll->active, pll->on,
1558                       crtc->base.base.id);
1559
1560         if (pll->active++) {
1561                 WARN_ON(!pll->on);
1562                 assert_shared_dpll_enabled(dev_priv, pll);
1563                 return;
1564         }
1565         WARN_ON(pll->on);
1566
1567         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1568         pll->enable(dev_priv, pll);
1569         pll->on = true;
1570 }
1571
1572 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1573 {
1574         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1575         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1576
1577         /* PCH only available on ILK+ */
1578         BUG_ON(dev_priv->info->gen < 5);
1579         if (WARN_ON(pll == NULL))
1580                return;
1581
1582         if (WARN_ON(pll->refcount == 0))
1583                 return;
1584
1585         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1586                       pll->name, pll->active, pll->on,
1587                       crtc->base.base.id);
1588
1589         if (WARN_ON(pll->active == 0)) {
1590                 assert_shared_dpll_disabled(dev_priv, pll);
1591                 return;
1592         }
1593
1594         assert_shared_dpll_enabled(dev_priv, pll);
1595         WARN_ON(!pll->on);
1596         if (--pll->active)
1597                 return;
1598
1599         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1600         pll->disable(dev_priv, pll);
1601         pll->on = false;
1602 }
1603
1604 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1605                                            enum pipe pipe)
1606 {
1607         struct drm_device *dev = dev_priv->dev;
1608         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1610         uint32_t reg, val, pipeconf_val;
1611
1612         /* PCH only available on ILK+ */
1613         BUG_ON(dev_priv->info->gen < 5);
1614
1615         /* Make sure PCH DPLL is enabled */
1616         assert_shared_dpll_enabled(dev_priv,
1617                                    intel_crtc_to_shared_dpll(intel_crtc));
1618
1619         /* FDI must be feeding us bits for PCH ports */
1620         assert_fdi_tx_enabled(dev_priv, pipe);
1621         assert_fdi_rx_enabled(dev_priv, pipe);
1622
1623         if (HAS_PCH_CPT(dev)) {
1624                 /* Workaround: Set the timing override bit before enabling the
1625                  * pch transcoder. */
1626                 reg = TRANS_CHICKEN2(pipe);
1627                 val = I915_READ(reg);
1628                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1629                 I915_WRITE(reg, val);
1630         }
1631
1632         reg = PCH_TRANSCONF(pipe);
1633         val = I915_READ(reg);
1634         pipeconf_val = I915_READ(PIPECONF(pipe));
1635
1636         if (HAS_PCH_IBX(dev_priv->dev)) {
1637                 /*
1638                  * make the BPC in transcoder be consistent with
1639                  * that in pipeconf reg.
1640                  */
1641                 val &= ~PIPECONF_BPC_MASK;
1642                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1643         }
1644
1645         val &= ~TRANS_INTERLACE_MASK;
1646         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1647                 if (HAS_PCH_IBX(dev_priv->dev) &&
1648                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1649                         val |= TRANS_LEGACY_INTERLACED_ILK;
1650                 else
1651                         val |= TRANS_INTERLACED;
1652         else
1653                 val |= TRANS_PROGRESSIVE;
1654
1655         I915_WRITE(reg, val | TRANS_ENABLE);
1656         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1657                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1658 }
1659
1660 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1661                                       enum transcoder cpu_transcoder)
1662 {
1663         u32 val, pipeconf_val;
1664
1665         /* PCH only available on ILK+ */
1666         BUG_ON(dev_priv->info->gen < 5);
1667
1668         /* FDI must be feeding us bits for PCH ports */
1669         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1670         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1671
1672         /* Workaround: set timing override bit. */
1673         val = I915_READ(_TRANSA_CHICKEN2);
1674         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1675         I915_WRITE(_TRANSA_CHICKEN2, val);
1676
1677         val = TRANS_ENABLE;
1678         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1679
1680         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1681             PIPECONF_INTERLACED_ILK)
1682                 val |= TRANS_INTERLACED;
1683         else
1684                 val |= TRANS_PROGRESSIVE;
1685
1686         I915_WRITE(LPT_TRANSCONF, val);
1687         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1688                 DRM_ERROR("Failed to enable PCH transcoder\n");
1689 }
1690
1691 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1692                                             enum pipe pipe)
1693 {
1694         struct drm_device *dev = dev_priv->dev;
1695         uint32_t reg, val;
1696
1697         /* FDI relies on the transcoder */
1698         assert_fdi_tx_disabled(dev_priv, pipe);
1699         assert_fdi_rx_disabled(dev_priv, pipe);
1700
1701         /* Ports must be off as well */
1702         assert_pch_ports_disabled(dev_priv, pipe);
1703
1704         reg = PCH_TRANSCONF(pipe);
1705         val = I915_READ(reg);
1706         val &= ~TRANS_ENABLE;
1707         I915_WRITE(reg, val);
1708         /* wait for PCH transcoder off, transcoder state */
1709         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1710                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1711
1712         if (!HAS_PCH_IBX(dev)) {
1713                 /* Workaround: Clear the timing override chicken bit again. */
1714                 reg = TRANS_CHICKEN2(pipe);
1715                 val = I915_READ(reg);
1716                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1717                 I915_WRITE(reg, val);
1718         }
1719 }
1720
1721 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1722 {
1723         u32 val;
1724
1725         val = I915_READ(LPT_TRANSCONF);
1726         val &= ~TRANS_ENABLE;
1727         I915_WRITE(LPT_TRANSCONF, val);
1728         /* wait for PCH transcoder off, transcoder state */
1729         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1730                 DRM_ERROR("Failed to disable PCH transcoder\n");
1731
1732         /* Workaround: clear timing override bit. */
1733         val = I915_READ(_TRANSA_CHICKEN2);
1734         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1735         I915_WRITE(_TRANSA_CHICKEN2, val);
1736 }
1737
1738 /**
1739  * intel_enable_pipe - enable a pipe, asserting requirements
1740  * @dev_priv: i915 private structure
1741  * @pipe: pipe to enable
1742  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1743  *
1744  * Enable @pipe, making sure that various hardware specific requirements
1745  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1746  *
1747  * @pipe should be %PIPE_A or %PIPE_B.
1748  *
1749  * Will wait until the pipe is actually running (i.e. first vblank) before
1750  * returning.
1751  */
1752 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1753                               bool pch_port, bool dsi)
1754 {
1755         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1756                                                                       pipe);
1757         enum pipe pch_transcoder;
1758         int reg;
1759         u32 val;
1760
1761         assert_planes_disabled(dev_priv, pipe);
1762         assert_cursor_disabled(dev_priv, pipe);
1763         assert_sprites_disabled(dev_priv, pipe);
1764
1765         if (HAS_PCH_LPT(dev_priv->dev))
1766                 pch_transcoder = TRANSCODER_A;
1767         else
1768                 pch_transcoder = pipe;
1769
1770         /*
1771          * A pipe without a PLL won't actually be able to drive bits from
1772          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1773          * need the check.
1774          */
1775         if (!HAS_PCH_SPLIT(dev_priv->dev))
1776                 if (dsi)
1777                         assert_dsi_pll_enabled(dev_priv);
1778                 else
1779                         assert_pll_enabled(dev_priv, pipe);
1780         else {
1781                 if (pch_port) {
1782                         /* if driving the PCH, we need FDI enabled */
1783                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1784                         assert_fdi_tx_pll_enabled(dev_priv,
1785                                                   (enum pipe) cpu_transcoder);
1786                 }
1787                 /* FIXME: assert CPU port conditions for SNB+ */
1788         }
1789
1790         reg = PIPECONF(cpu_transcoder);
1791         val = I915_READ(reg);
1792         if (val & PIPECONF_ENABLE)
1793                 return;
1794
1795         I915_WRITE(reg, val | PIPECONF_ENABLE);
1796         intel_wait_for_vblank(dev_priv->dev, pipe);
1797 }
1798
1799 /**
1800  * intel_disable_pipe - disable a pipe, asserting requirements
1801  * @dev_priv: i915 private structure
1802  * @pipe: pipe to disable
1803  *
1804  * Disable @pipe, making sure that various hardware specific requirements
1805  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1806  *
1807  * @pipe should be %PIPE_A or %PIPE_B.
1808  *
1809  * Will wait until the pipe has shut down before returning.
1810  */
1811 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1812                                enum pipe pipe)
1813 {
1814         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1815                                                                       pipe);
1816         int reg;
1817         u32 val;
1818
1819         /*
1820          * Make sure planes won't keep trying to pump pixels to us,
1821          * or we might hang the display.
1822          */
1823         assert_planes_disabled(dev_priv, pipe);
1824         assert_cursor_disabled(dev_priv, pipe);
1825         assert_sprites_disabled(dev_priv, pipe);
1826
1827         /* Don't disable pipe A or pipe A PLLs if needed */
1828         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1829                 return;
1830
1831         reg = PIPECONF(cpu_transcoder);
1832         val = I915_READ(reg);
1833         if ((val & PIPECONF_ENABLE) == 0)
1834                 return;
1835
1836         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1837         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1838 }
1839
1840 /*
1841  * Plane regs are double buffered, going from enabled->disabled needs a
1842  * trigger in order to latch.  The display address reg provides this.
1843  */
1844 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1845                                enum plane plane)
1846 {
1847         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1848
1849         I915_WRITE(reg, I915_READ(reg));
1850         POSTING_READ(reg);
1851 }
1852
1853 /**
1854  * intel_enable_primary_plane - enable the primary plane on a given pipe
1855  * @dev_priv: i915 private structure
1856  * @plane: plane to enable
1857  * @pipe: pipe being fed
1858  *
1859  * Enable @plane on @pipe, making sure that @pipe is running first.
1860  */
1861 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1862                                        enum plane plane, enum pipe pipe)
1863 {
1864         struct intel_crtc *intel_crtc =
1865                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1866         int reg;
1867         u32 val;
1868
1869         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1870         assert_pipe_enabled(dev_priv, pipe);
1871
1872         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1873
1874         intel_crtc->primary_enabled = true;
1875
1876         reg = DSPCNTR(plane);
1877         val = I915_READ(reg);
1878         if (val & DISPLAY_PLANE_ENABLE)
1879                 return;
1880
1881         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1882         intel_flush_primary_plane(dev_priv, plane);
1883         intel_wait_for_vblank(dev_priv->dev, pipe);
1884 }
1885
1886 /**
1887  * intel_disable_primary_plane - disable the primary plane
1888  * @dev_priv: i915 private structure
1889  * @plane: plane to disable
1890  * @pipe: pipe consuming the data
1891  *
1892  * Disable @plane; should be an independent operation.
1893  */
1894 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1895                                         enum plane plane, enum pipe pipe)
1896 {
1897         struct intel_crtc *intel_crtc =
1898                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1899         int reg;
1900         u32 val;
1901
1902         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1903
1904         intel_crtc->primary_enabled = false;
1905
1906         reg = DSPCNTR(plane);
1907         val = I915_READ(reg);
1908         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1909                 return;
1910
1911         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1912         intel_flush_primary_plane(dev_priv, plane);
1913         intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 static bool need_vtd_wa(struct drm_device *dev)
1917 {
1918 #ifdef CONFIG_INTEL_IOMMU
1919         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1920                 return true;
1921 #endif
1922         return false;
1923 }
1924
1925 int
1926 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1927                            struct drm_i915_gem_object *obj,
1928                            struct intel_ring_buffer *pipelined)
1929 {
1930         struct drm_i915_private *dev_priv = dev->dev_private;
1931         u32 alignment;
1932         int ret;
1933
1934         switch (obj->tiling_mode) {
1935         case I915_TILING_NONE:
1936                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1937                         alignment = 128 * 1024;
1938                 else if (INTEL_INFO(dev)->gen >= 4)
1939                         alignment = 4 * 1024;
1940                 else
1941                         alignment = 64 * 1024;
1942                 break;
1943         case I915_TILING_X:
1944                 /* pin() will align the object as required by fence */
1945                 alignment = 0;
1946                 break;
1947         case I915_TILING_Y:
1948                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1949                 return -EINVAL;
1950         default:
1951                 BUG();
1952         }
1953
1954         /* Note that the w/a also requires 64 PTE of padding following the
1955          * bo. We currently fill all unused PTE with the shadow page and so
1956          * we should always have valid PTE following the scanout preventing
1957          * the VT-d warning.
1958          */
1959         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1960                 alignment = 256 * 1024;
1961
1962         dev_priv->mm.interruptible = false;
1963         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1964         if (ret)
1965                 goto err_interruptible;
1966
1967         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1968          * fence, whereas 965+ only requires a fence if using
1969          * framebuffer compression.  For simplicity, we always install
1970          * a fence as the cost is not that onerous.
1971          */
1972         ret = i915_gem_object_get_fence(obj);
1973         if (ret)
1974                 goto err_unpin;
1975
1976         i915_gem_object_pin_fence(obj);
1977
1978         dev_priv->mm.interruptible = true;
1979         return 0;
1980
1981 err_unpin:
1982         i915_gem_object_unpin_from_display_plane(obj);
1983 err_interruptible:
1984         dev_priv->mm.interruptible = true;
1985         return ret;
1986 }
1987
1988 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1989 {
1990         i915_gem_object_unpin_fence(obj);
1991         i915_gem_object_unpin_from_display_plane(obj);
1992 }
1993
1994 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1995  * is assumed to be a power-of-two. */
1996 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1997                                              unsigned int tiling_mode,
1998                                              unsigned int cpp,
1999                                              unsigned int pitch)
2000 {
2001         if (tiling_mode != I915_TILING_NONE) {
2002                 unsigned int tile_rows, tiles;
2003
2004                 tile_rows = *y / 8;
2005                 *y %= 8;
2006
2007                 tiles = *x / (512/cpp);
2008                 *x %= 512/cpp;
2009
2010                 return tile_rows * pitch * 8 + tiles * 4096;
2011         } else {
2012                 unsigned int offset;
2013
2014                 offset = *y * pitch + *x * cpp;
2015                 *y = 0;
2016                 *x = (offset & 4095) / cpp;
2017                 return offset & -4096;
2018         }
2019 }
2020
2021 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2022                              int x, int y)
2023 {
2024         struct drm_device *dev = crtc->dev;
2025         struct drm_i915_private *dev_priv = dev->dev_private;
2026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2027         struct intel_framebuffer *intel_fb;
2028         struct drm_i915_gem_object *obj;
2029         int plane = intel_crtc->plane;
2030         unsigned long linear_offset;
2031         u32 dspcntr;
2032         u32 reg;
2033
2034         switch (plane) {
2035         case 0:
2036         case 1:
2037                 break;
2038         default:
2039                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2040                 return -EINVAL;
2041         }
2042
2043         intel_fb = to_intel_framebuffer(fb);
2044         obj = intel_fb->obj;
2045
2046         reg = DSPCNTR(plane);
2047         dspcntr = I915_READ(reg);
2048         /* Mask out pixel format bits in case we change it */
2049         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2050         switch (fb->pixel_format) {
2051         case DRM_FORMAT_C8:
2052                 dspcntr |= DISPPLANE_8BPP;
2053                 break;
2054         case DRM_FORMAT_XRGB1555:
2055         case DRM_FORMAT_ARGB1555:
2056                 dspcntr |= DISPPLANE_BGRX555;
2057                 break;
2058         case DRM_FORMAT_RGB565:
2059                 dspcntr |= DISPPLANE_BGRX565;
2060                 break;
2061         case DRM_FORMAT_XRGB8888:
2062         case DRM_FORMAT_ARGB8888:
2063                 dspcntr |= DISPPLANE_BGRX888;
2064                 break;
2065         case DRM_FORMAT_XBGR8888:
2066         case DRM_FORMAT_ABGR8888:
2067                 dspcntr |= DISPPLANE_RGBX888;
2068                 break;
2069         case DRM_FORMAT_XRGB2101010:
2070         case DRM_FORMAT_ARGB2101010:
2071                 dspcntr |= DISPPLANE_BGRX101010;
2072                 break;
2073         case DRM_FORMAT_XBGR2101010:
2074         case DRM_FORMAT_ABGR2101010:
2075                 dspcntr |= DISPPLANE_RGBX101010;
2076                 break;
2077         default:
2078                 BUG();
2079         }
2080
2081         if (INTEL_INFO(dev)->gen >= 4) {
2082                 if (obj->tiling_mode != I915_TILING_NONE)
2083                         dspcntr |= DISPPLANE_TILED;
2084                 else
2085                         dspcntr &= ~DISPPLANE_TILED;
2086         }
2087
2088         if (IS_G4X(dev))
2089                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2090
2091         I915_WRITE(reg, dspcntr);
2092
2093         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2094
2095         if (INTEL_INFO(dev)->gen >= 4) {
2096                 intel_crtc->dspaddr_offset =
2097                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2098                                                        fb->bits_per_pixel / 8,
2099                                                        fb->pitches[0]);
2100                 linear_offset -= intel_crtc->dspaddr_offset;
2101         } else {
2102                 intel_crtc->dspaddr_offset = linear_offset;
2103         }
2104
2105         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2106                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2107                       fb->pitches[0]);
2108         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2109         if (INTEL_INFO(dev)->gen >= 4) {
2110                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2111                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2112                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2113                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2114         } else
2115                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2116         POSTING_READ(reg);
2117
2118         return 0;
2119 }
2120
2121 static int ironlake_update_plane(struct drm_crtc *crtc,
2122                                  struct drm_framebuffer *fb, int x, int y)
2123 {
2124         struct drm_device *dev = crtc->dev;
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127         struct intel_framebuffer *intel_fb;
2128         struct drm_i915_gem_object *obj;
2129         int plane = intel_crtc->plane;
2130         unsigned long linear_offset;
2131         u32 dspcntr;
2132         u32 reg;
2133
2134         switch (plane) {
2135         case 0:
2136         case 1:
2137         case 2:
2138                 break;
2139         default:
2140                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2141                 return -EINVAL;
2142         }
2143
2144         intel_fb = to_intel_framebuffer(fb);
2145         obj = intel_fb->obj;
2146
2147         reg = DSPCNTR(plane);
2148         dspcntr = I915_READ(reg);
2149         /* Mask out pixel format bits in case we change it */
2150         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2151         switch (fb->pixel_format) {
2152         case DRM_FORMAT_C8:
2153                 dspcntr |= DISPPLANE_8BPP;
2154                 break;
2155         case DRM_FORMAT_RGB565:
2156                 dspcntr |= DISPPLANE_BGRX565;
2157                 break;
2158         case DRM_FORMAT_XRGB8888:
2159         case DRM_FORMAT_ARGB8888:
2160                 dspcntr |= DISPPLANE_BGRX888;
2161                 break;
2162         case DRM_FORMAT_XBGR8888:
2163         case DRM_FORMAT_ABGR8888:
2164                 dspcntr |= DISPPLANE_RGBX888;
2165                 break;
2166         case DRM_FORMAT_XRGB2101010:
2167         case DRM_FORMAT_ARGB2101010:
2168                 dspcntr |= DISPPLANE_BGRX101010;
2169                 break;
2170         case DRM_FORMAT_XBGR2101010:
2171         case DRM_FORMAT_ABGR2101010:
2172                 dspcntr |= DISPPLANE_RGBX101010;
2173                 break;
2174         default:
2175                 BUG();
2176         }
2177
2178         if (obj->tiling_mode != I915_TILING_NONE)
2179                 dspcntr |= DISPPLANE_TILED;
2180         else
2181                 dspcntr &= ~DISPPLANE_TILED;
2182
2183         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2184                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2185         else
2186                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2187
2188         I915_WRITE(reg, dspcntr);
2189
2190         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2191         intel_crtc->dspaddr_offset =
2192                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2193                                                fb->bits_per_pixel / 8,
2194                                                fb->pitches[0]);
2195         linear_offset -= intel_crtc->dspaddr_offset;
2196
2197         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2198                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2199                       fb->pitches[0]);
2200         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2201         I915_MODIFY_DISPBASE(DSPSURF(plane),
2202                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2203         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2204                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2205         } else {
2206                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2207                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2208         }
2209         POSTING_READ(reg);
2210
2211         return 0;
2212 }
2213
2214 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2215 static int
2216 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2217                            int x, int y, enum mode_set_atomic state)
2218 {
2219         struct drm_device *dev = crtc->dev;
2220         struct drm_i915_private *dev_priv = dev->dev_private;
2221
2222         if (dev_priv->display.disable_fbc)
2223                 dev_priv->display.disable_fbc(dev);
2224         intel_increase_pllclock(crtc);
2225
2226         return dev_priv->display.update_plane(crtc, fb, x, y);
2227 }
2228
2229 void intel_display_handle_reset(struct drm_device *dev)
2230 {
2231         struct drm_i915_private *dev_priv = dev->dev_private;
2232         struct drm_crtc *crtc;
2233
2234         /*
2235          * Flips in the rings have been nuked by the reset,
2236          * so complete all pending flips so that user space
2237          * will get its events and not get stuck.
2238          *
2239          * Also update the base address of all primary
2240          * planes to the the last fb to make sure we're
2241          * showing the correct fb after a reset.
2242          *
2243          * Need to make two loops over the crtcs so that we
2244          * don't try to grab a crtc mutex before the
2245          * pending_flip_queue really got woken up.
2246          */
2247
2248         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2249                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250                 enum plane plane = intel_crtc->plane;
2251
2252                 intel_prepare_page_flip(dev, plane);
2253                 intel_finish_page_flip_plane(dev, plane);
2254         }
2255
2256         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2257                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2258
2259                 mutex_lock(&crtc->mutex);
2260                 /*
2261                  * FIXME: Once we have proper support for primary planes (and
2262                  * disabling them without disabling the entire crtc) allow again
2263                  * a NULL crtc->fb.
2264                  */
2265                 if (intel_crtc->active && crtc->fb)
2266                         dev_priv->display.update_plane(crtc, crtc->fb,
2267                                                        crtc->x, crtc->y);
2268                 mutex_unlock(&crtc->mutex);
2269         }
2270 }
2271
2272 static int
2273 intel_finish_fb(struct drm_framebuffer *old_fb)
2274 {
2275         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2276         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2277         bool was_interruptible = dev_priv->mm.interruptible;
2278         int ret;
2279
2280         /* Big Hammer, we also need to ensure that any pending
2281          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2282          * current scanout is retired before unpinning the old
2283          * framebuffer.
2284          *
2285          * This should only fail upon a hung GPU, in which case we
2286          * can safely continue.
2287          */
2288         dev_priv->mm.interruptible = false;
2289         ret = i915_gem_object_finish_gpu(obj);
2290         dev_priv->mm.interruptible = was_interruptible;
2291
2292         return ret;
2293 }
2294
2295 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2296 {
2297         struct drm_device *dev = crtc->dev;
2298         struct drm_i915_master_private *master_priv;
2299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300
2301         if (!dev->primary->master)
2302                 return;
2303
2304         master_priv = dev->primary->master->driver_priv;
2305         if (!master_priv->sarea_priv)
2306                 return;
2307
2308         switch (intel_crtc->pipe) {
2309         case 0:
2310                 master_priv->sarea_priv->pipeA_x = x;
2311                 master_priv->sarea_priv->pipeA_y = y;
2312                 break;
2313         case 1:
2314                 master_priv->sarea_priv->pipeB_x = x;
2315                 master_priv->sarea_priv->pipeB_y = y;
2316                 break;
2317         default:
2318                 break;
2319         }
2320 }
2321
2322 static int
2323 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2324                     struct drm_framebuffer *fb)
2325 {
2326         struct drm_device *dev = crtc->dev;
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329         struct drm_framebuffer *old_fb;
2330         int ret;
2331
2332         /* no fb bound */
2333         if (!fb) {
2334                 DRM_ERROR("No FB bound\n");
2335                 return 0;
2336         }
2337
2338         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2339                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2340                           plane_name(intel_crtc->plane),
2341                           INTEL_INFO(dev)->num_pipes);
2342                 return -EINVAL;
2343         }
2344
2345         mutex_lock(&dev->struct_mutex);
2346         ret = intel_pin_and_fence_fb_obj(dev,
2347                                          to_intel_framebuffer(fb)->obj,
2348                                          NULL);
2349         if (ret != 0) {
2350                 mutex_unlock(&dev->struct_mutex);
2351                 DRM_ERROR("pin & fence failed\n");
2352                 return ret;
2353         }
2354
2355         /*
2356          * Update pipe size and adjust fitter if needed: the reason for this is
2357          * that in compute_mode_changes we check the native mode (not the pfit
2358          * mode) to see if we can flip rather than do a full mode set. In the
2359          * fastboot case, we'll flip, but if we don't update the pipesrc and
2360          * pfit state, we'll end up with a big fb scanned out into the wrong
2361          * sized surface.
2362          *
2363          * To fix this properly, we need to hoist the checks up into
2364          * compute_mode_changes (or above), check the actual pfit state and
2365          * whether the platform allows pfit disable with pipe active, and only
2366          * then update the pipesrc and pfit state, even on the flip path.
2367          */
2368         if (i915_fastboot) {
2369                 const struct drm_display_mode *adjusted_mode =
2370                         &intel_crtc->config.adjusted_mode;
2371
2372                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2373                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2374                            (adjusted_mode->crtc_vdisplay - 1));
2375                 if (!intel_crtc->config.pch_pfit.enabled &&
2376                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2377                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2378                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2379                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2380                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2381                 }
2382                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2383                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2384         }
2385
2386         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2387         if (ret) {
2388                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2389                 mutex_unlock(&dev->struct_mutex);
2390                 DRM_ERROR("failed to update base address\n");
2391                 return ret;
2392         }
2393
2394         old_fb = crtc->fb;
2395         crtc->fb = fb;
2396         crtc->x = x;
2397         crtc->y = y;
2398
2399         if (old_fb) {
2400                 if (intel_crtc->active && old_fb != fb)
2401                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2402                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2403         }
2404
2405         intel_update_fbc(dev);
2406         intel_edp_psr_update(dev);
2407         mutex_unlock(&dev->struct_mutex);
2408
2409         intel_crtc_update_sarea_pos(crtc, x, y);
2410
2411         return 0;
2412 }
2413
2414 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2415 {
2416         struct drm_device *dev = crtc->dev;
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2419         int pipe = intel_crtc->pipe;
2420         u32 reg, temp;
2421
2422         /* enable normal train */
2423         reg = FDI_TX_CTL(pipe);
2424         temp = I915_READ(reg);
2425         if (IS_IVYBRIDGE(dev)) {
2426                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2427                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2428         } else {
2429                 temp &= ~FDI_LINK_TRAIN_NONE;
2430                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2431         }
2432         I915_WRITE(reg, temp);
2433
2434         reg = FDI_RX_CTL(pipe);
2435         temp = I915_READ(reg);
2436         if (HAS_PCH_CPT(dev)) {
2437                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2438                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2439         } else {
2440                 temp &= ~FDI_LINK_TRAIN_NONE;
2441                 temp |= FDI_LINK_TRAIN_NONE;
2442         }
2443         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2444
2445         /* wait one idle pattern time */
2446         POSTING_READ(reg);
2447         udelay(1000);
2448
2449         /* IVB wants error correction enabled */
2450         if (IS_IVYBRIDGE(dev))
2451                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2452                            FDI_FE_ERRC_ENABLE);
2453 }
2454
2455 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2456 {
2457         return crtc->base.enabled && crtc->active &&
2458                 crtc->config.has_pch_encoder;
2459 }
2460
2461 static void ivb_modeset_global_resources(struct drm_device *dev)
2462 {
2463         struct drm_i915_private *dev_priv = dev->dev_private;
2464         struct intel_crtc *pipe_B_crtc =
2465                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2466         struct intel_crtc *pipe_C_crtc =
2467                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2468         uint32_t temp;
2469
2470         /*
2471          * When everything is off disable fdi C so that we could enable fdi B
2472          * with all lanes. Note that we don't care about enabled pipes without
2473          * an enabled pch encoder.
2474          */
2475         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2476             !pipe_has_enabled_pch(pipe_C_crtc)) {
2477                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2478                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2479
2480                 temp = I915_READ(SOUTH_CHICKEN1);
2481                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2482                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2483                 I915_WRITE(SOUTH_CHICKEN1, temp);
2484         }
2485 }
2486
2487 /* The FDI link training functions for ILK/Ibexpeak. */
2488 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2489 {
2490         struct drm_device *dev = crtc->dev;
2491         struct drm_i915_private *dev_priv = dev->dev_private;
2492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2493         int pipe = intel_crtc->pipe;
2494         int plane = intel_crtc->plane;
2495         u32 reg, temp, tries;
2496
2497         /* FDI needs bits from pipe & plane first */
2498         assert_pipe_enabled(dev_priv, pipe);
2499         assert_plane_enabled(dev_priv, plane);
2500
2501         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2502            for train result */
2503         reg = FDI_RX_IMR(pipe);
2504         temp = I915_READ(reg);
2505         temp &= ~FDI_RX_SYMBOL_LOCK;
2506         temp &= ~FDI_RX_BIT_LOCK;
2507         I915_WRITE(reg, temp);
2508         I915_READ(reg);
2509         udelay(150);
2510
2511         /* enable CPU FDI TX and PCH FDI RX */
2512         reg = FDI_TX_CTL(pipe);
2513         temp = I915_READ(reg);
2514         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2515         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2516         temp &= ~FDI_LINK_TRAIN_NONE;
2517         temp |= FDI_LINK_TRAIN_PATTERN_1;
2518         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2519
2520         reg = FDI_RX_CTL(pipe);
2521         temp = I915_READ(reg);
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_1;
2524         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2525
2526         POSTING_READ(reg);
2527         udelay(150);
2528
2529         /* Ironlake workaround, enable clock pointer after FDI enable*/
2530         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2531         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2532                    FDI_RX_PHASE_SYNC_POINTER_EN);
2533
2534         reg = FDI_RX_IIR(pipe);
2535         for (tries = 0; tries < 5; tries++) {
2536                 temp = I915_READ(reg);
2537                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2538
2539                 if ((temp & FDI_RX_BIT_LOCK)) {
2540                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2541                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2542                         break;
2543                 }
2544         }
2545         if (tries == 5)
2546                 DRM_ERROR("FDI train 1 fail!\n");
2547
2548         /* Train 2 */
2549         reg = FDI_TX_CTL(pipe);
2550         temp = I915_READ(reg);
2551         temp &= ~FDI_LINK_TRAIN_NONE;
2552         temp |= FDI_LINK_TRAIN_PATTERN_2;
2553         I915_WRITE(reg, temp);
2554
2555         reg = FDI_RX_CTL(pipe);
2556         temp = I915_READ(reg);
2557         temp &= ~FDI_LINK_TRAIN_NONE;
2558         temp |= FDI_LINK_TRAIN_PATTERN_2;
2559         I915_WRITE(reg, temp);
2560
2561         POSTING_READ(reg);
2562         udelay(150);
2563
2564         reg = FDI_RX_IIR(pipe);
2565         for (tries = 0; tries < 5; tries++) {
2566                 temp = I915_READ(reg);
2567                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568
2569                 if (temp & FDI_RX_SYMBOL_LOCK) {
2570                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2571                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2572                         break;
2573                 }
2574         }
2575         if (tries == 5)
2576                 DRM_ERROR("FDI train 2 fail!\n");
2577
2578         DRM_DEBUG_KMS("FDI train done\n");
2579
2580 }
2581
2582 static const int snb_b_fdi_train_param[] = {
2583         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2584         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2585         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2586         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2587 };
2588
2589 /* The FDI link training functions for SNB/Cougarpoint. */
2590 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2591 {
2592         struct drm_device *dev = crtc->dev;
2593         struct drm_i915_private *dev_priv = dev->dev_private;
2594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2595         int pipe = intel_crtc->pipe;
2596         u32 reg, temp, i, retry;
2597
2598         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2599            for train result */
2600         reg = FDI_RX_IMR(pipe);
2601         temp = I915_READ(reg);
2602         temp &= ~FDI_RX_SYMBOL_LOCK;
2603         temp &= ~FDI_RX_BIT_LOCK;
2604         I915_WRITE(reg, temp);
2605
2606         POSTING_READ(reg);
2607         udelay(150);
2608
2609         /* enable CPU FDI TX and PCH FDI RX */
2610         reg = FDI_TX_CTL(pipe);
2611         temp = I915_READ(reg);
2612         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2613         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2614         temp &= ~FDI_LINK_TRAIN_NONE;
2615         temp |= FDI_LINK_TRAIN_PATTERN_1;
2616         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2617         /* SNB-B */
2618         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2619         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2620
2621         I915_WRITE(FDI_RX_MISC(pipe),
2622                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2623
2624         reg = FDI_RX_CTL(pipe);
2625         temp = I915_READ(reg);
2626         if (HAS_PCH_CPT(dev)) {
2627                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2628                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2629         } else {
2630                 temp &= ~FDI_LINK_TRAIN_NONE;
2631                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2632         }
2633         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2634
2635         POSTING_READ(reg);
2636         udelay(150);
2637
2638         for (i = 0; i < 4; i++) {
2639                 reg = FDI_TX_CTL(pipe);
2640                 temp = I915_READ(reg);
2641                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2642                 temp |= snb_b_fdi_train_param[i];
2643                 I915_WRITE(reg, temp);
2644
2645                 POSTING_READ(reg);
2646                 udelay(500);
2647
2648                 for (retry = 0; retry < 5; retry++) {
2649                         reg = FDI_RX_IIR(pipe);
2650                         temp = I915_READ(reg);
2651                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652                         if (temp & FDI_RX_BIT_LOCK) {
2653                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2654                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2655                                 break;
2656                         }
2657                         udelay(50);
2658                 }
2659                 if (retry < 5)
2660                         break;
2661         }
2662         if (i == 4)
2663                 DRM_ERROR("FDI train 1 fail!\n");
2664
2665         /* Train 2 */
2666         reg = FDI_TX_CTL(pipe);
2667         temp = I915_READ(reg);
2668         temp &= ~FDI_LINK_TRAIN_NONE;
2669         temp |= FDI_LINK_TRAIN_PATTERN_2;
2670         if (IS_GEN6(dev)) {
2671                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672                 /* SNB-B */
2673                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674         }
2675         I915_WRITE(reg, temp);
2676
2677         reg = FDI_RX_CTL(pipe);
2678         temp = I915_READ(reg);
2679         if (HAS_PCH_CPT(dev)) {
2680                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682         } else {
2683                 temp &= ~FDI_LINK_TRAIN_NONE;
2684                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2685         }
2686         I915_WRITE(reg, temp);
2687
2688         POSTING_READ(reg);
2689         udelay(150);
2690
2691         for (i = 0; i < 4; i++) {
2692                 reg = FDI_TX_CTL(pipe);
2693                 temp = I915_READ(reg);
2694                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695                 temp |= snb_b_fdi_train_param[i];
2696                 I915_WRITE(reg, temp);
2697
2698                 POSTING_READ(reg);
2699                 udelay(500);
2700
2701                 for (retry = 0; retry < 5; retry++) {
2702                         reg = FDI_RX_IIR(pipe);
2703                         temp = I915_READ(reg);
2704                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2705                         if (temp & FDI_RX_SYMBOL_LOCK) {
2706                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2707                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2708                                 break;
2709                         }
2710                         udelay(50);
2711                 }
2712                 if (retry < 5)
2713                         break;
2714         }
2715         if (i == 4)
2716                 DRM_ERROR("FDI train 2 fail!\n");
2717
2718         DRM_DEBUG_KMS("FDI train done.\n");
2719 }
2720
2721 /* Manual link training for Ivy Bridge A0 parts */
2722 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2723 {
2724         struct drm_device *dev = crtc->dev;
2725         struct drm_i915_private *dev_priv = dev->dev_private;
2726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2727         int pipe = intel_crtc->pipe;
2728         u32 reg, temp, i, j;
2729
2730         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2731            for train result */
2732         reg = FDI_RX_IMR(pipe);
2733         temp = I915_READ(reg);
2734         temp &= ~FDI_RX_SYMBOL_LOCK;
2735         temp &= ~FDI_RX_BIT_LOCK;
2736         I915_WRITE(reg, temp);
2737
2738         POSTING_READ(reg);
2739         udelay(150);
2740
2741         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2742                       I915_READ(FDI_RX_IIR(pipe)));
2743
2744         /* Try each vswing and preemphasis setting twice before moving on */
2745         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2746                 /* disable first in case we need to retry */
2747                 reg = FDI_TX_CTL(pipe);
2748                 temp = I915_READ(reg);
2749                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2750                 temp &= ~FDI_TX_ENABLE;
2751                 I915_WRITE(reg, temp);
2752
2753                 reg = FDI_RX_CTL(pipe);
2754                 temp = I915_READ(reg);
2755                 temp &= ~FDI_LINK_TRAIN_AUTO;
2756                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2757                 temp &= ~FDI_RX_ENABLE;
2758                 I915_WRITE(reg, temp);
2759
2760                 /* enable CPU FDI TX and PCH FDI RX */
2761                 reg = FDI_TX_CTL(pipe);
2762                 temp = I915_READ(reg);
2763                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2764                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2765                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2766                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767                 temp |= snb_b_fdi_train_param[j/2];
2768                 temp |= FDI_COMPOSITE_SYNC;
2769                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2770
2771                 I915_WRITE(FDI_RX_MISC(pipe),
2772                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2773
2774                 reg = FDI_RX_CTL(pipe);
2775                 temp = I915_READ(reg);
2776                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2777                 temp |= FDI_COMPOSITE_SYNC;
2778                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2779
2780                 POSTING_READ(reg);
2781                 udelay(1); /* should be 0.5us */
2782
2783                 for (i = 0; i < 4; i++) {
2784                         reg = FDI_RX_IIR(pipe);
2785                         temp = I915_READ(reg);
2786                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788                         if (temp & FDI_RX_BIT_LOCK ||
2789                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2792                                               i);
2793                                 break;
2794                         }
2795                         udelay(1); /* should be 0.5us */
2796                 }
2797                 if (i == 4) {
2798                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2799                         continue;
2800                 }
2801
2802                 /* Train 2 */
2803                 reg = FDI_TX_CTL(pipe);
2804                 temp = I915_READ(reg);
2805                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2806                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2807                 I915_WRITE(reg, temp);
2808
2809                 reg = FDI_RX_CTL(pipe);
2810                 temp = I915_READ(reg);
2811                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2813                 I915_WRITE(reg, temp);
2814
2815                 POSTING_READ(reg);
2816                 udelay(2); /* should be 1.5us */
2817
2818                 for (i = 0; i < 4; i++) {
2819                         reg = FDI_RX_IIR(pipe);
2820                         temp = I915_READ(reg);
2821                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2822
2823                         if (temp & FDI_RX_SYMBOL_LOCK ||
2824                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2825                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2826                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2827                                               i);
2828                                 goto train_done;
2829                         }
2830                         udelay(2); /* should be 1.5us */
2831                 }
2832                 if (i == 4)
2833                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2834         }
2835
2836 train_done:
2837         DRM_DEBUG_KMS("FDI train done.\n");
2838 }
2839
2840 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2841 {
2842         struct drm_device *dev = intel_crtc->base.dev;
2843         struct drm_i915_private *dev_priv = dev->dev_private;
2844         int pipe = intel_crtc->pipe;
2845         u32 reg, temp;
2846
2847
2848         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2852         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2853         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2854         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2855
2856         POSTING_READ(reg);
2857         udelay(200);
2858
2859         /* Switch from Rawclk to PCDclk */
2860         temp = I915_READ(reg);
2861         I915_WRITE(reg, temp | FDI_PCDCLK);
2862
2863         POSTING_READ(reg);
2864         udelay(200);
2865
2866         /* Enable CPU FDI TX PLL, always on for Ironlake */
2867         reg = FDI_TX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2870                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2871
2872                 POSTING_READ(reg);
2873                 udelay(100);
2874         }
2875 }
2876
2877 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2878 {
2879         struct drm_device *dev = intel_crtc->base.dev;
2880         struct drm_i915_private *dev_priv = dev->dev_private;
2881         int pipe = intel_crtc->pipe;
2882         u32 reg, temp;
2883
2884         /* Switch from PCDclk to Rawclk */
2885         reg = FDI_RX_CTL(pipe);
2886         temp = I915_READ(reg);
2887         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2888
2889         /* Disable CPU FDI TX PLL */
2890         reg = FDI_TX_CTL(pipe);
2891         temp = I915_READ(reg);
2892         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2893
2894         POSTING_READ(reg);
2895         udelay(100);
2896
2897         reg = FDI_RX_CTL(pipe);
2898         temp = I915_READ(reg);
2899         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2900
2901         /* Wait for the clocks to turn off. */
2902         POSTING_READ(reg);
2903         udelay(100);
2904 }
2905
2906 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2907 {
2908         struct drm_device *dev = crtc->dev;
2909         struct drm_i915_private *dev_priv = dev->dev_private;
2910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2911         int pipe = intel_crtc->pipe;
2912         u32 reg, temp;
2913
2914         /* disable CPU FDI tx and PCH FDI rx */
2915         reg = FDI_TX_CTL(pipe);
2916         temp = I915_READ(reg);
2917         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2918         POSTING_READ(reg);
2919
2920         reg = FDI_RX_CTL(pipe);
2921         temp = I915_READ(reg);
2922         temp &= ~(0x7 << 16);
2923         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2924         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2925
2926         POSTING_READ(reg);
2927         udelay(100);
2928
2929         /* Ironlake workaround, disable clock pointer after downing FDI */
2930         if (HAS_PCH_IBX(dev)) {
2931                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2932         }
2933
2934         /* still set train pattern 1 */
2935         reg = FDI_TX_CTL(pipe);
2936         temp = I915_READ(reg);
2937         temp &= ~FDI_LINK_TRAIN_NONE;
2938         temp |= FDI_LINK_TRAIN_PATTERN_1;
2939         I915_WRITE(reg, temp);
2940
2941         reg = FDI_RX_CTL(pipe);
2942         temp = I915_READ(reg);
2943         if (HAS_PCH_CPT(dev)) {
2944                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2945                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2946         } else {
2947                 temp &= ~FDI_LINK_TRAIN_NONE;
2948                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2949         }
2950         /* BPC in FDI rx is consistent with that in PIPECONF */
2951         temp &= ~(0x07 << 16);
2952         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2953         I915_WRITE(reg, temp);
2954
2955         POSTING_READ(reg);
2956         udelay(100);
2957 }
2958
2959 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2960 {
2961         struct drm_device *dev = crtc->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964         unsigned long flags;
2965         bool pending;
2966
2967         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2968             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2969                 return false;
2970
2971         spin_lock_irqsave(&dev->event_lock, flags);
2972         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2973         spin_unlock_irqrestore(&dev->event_lock, flags);
2974
2975         return pending;
2976 }
2977
2978 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2979 {
2980         struct drm_device *dev = crtc->dev;
2981         struct drm_i915_private *dev_priv = dev->dev_private;
2982
2983         if (crtc->fb == NULL)
2984                 return;
2985
2986         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2987
2988         wait_event(dev_priv->pending_flip_queue,
2989                    !intel_crtc_has_pending_flip(crtc));
2990
2991         mutex_lock(&dev->struct_mutex);
2992         intel_finish_fb(crtc->fb);
2993         mutex_unlock(&dev->struct_mutex);
2994 }
2995
2996 /* Program iCLKIP clock to the desired frequency */
2997 static void lpt_program_iclkip(struct drm_crtc *crtc)
2998 {
2999         struct drm_device *dev = crtc->dev;
3000         struct drm_i915_private *dev_priv = dev->dev_private;
3001         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3002         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3003         u32 temp;
3004
3005         mutex_lock(&dev_priv->dpio_lock);
3006
3007         /* It is necessary to ungate the pixclk gate prior to programming
3008          * the divisors, and gate it back when it is done.
3009          */
3010         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3011
3012         /* Disable SSCCTL */
3013         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3014                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3015                                 SBI_SSCCTL_DISABLE,
3016                         SBI_ICLK);
3017
3018         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3019         if (clock == 20000) {
3020                 auxdiv = 1;
3021                 divsel = 0x41;
3022                 phaseinc = 0x20;
3023         } else {
3024                 /* The iCLK virtual clock root frequency is in MHz,
3025                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3026                  * divisors, it is necessary to divide one by another, so we
3027                  * convert the virtual clock precision to KHz here for higher
3028                  * precision.
3029                  */
3030                 u32 iclk_virtual_root_freq = 172800 * 1000;
3031                 u32 iclk_pi_range = 64;
3032                 u32 desired_divisor, msb_divisor_value, pi_value;
3033
3034                 desired_divisor = (iclk_virtual_root_freq / clock);
3035                 msb_divisor_value = desired_divisor / iclk_pi_range;
3036                 pi_value = desired_divisor % iclk_pi_range;
3037
3038                 auxdiv = 0;
3039                 divsel = msb_divisor_value - 2;
3040                 phaseinc = pi_value;
3041         }
3042
3043         /* This should not happen with any sane values */
3044         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3045                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3046         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3047                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3048
3049         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3050                         clock,
3051                         auxdiv,
3052                         divsel,
3053                         phasedir,
3054                         phaseinc);
3055
3056         /* Program SSCDIVINTPHASE6 */
3057         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3058         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3059         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3060         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3061         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3062         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3063         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3064         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3065
3066         /* Program SSCAUXDIV */
3067         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3068         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3069         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3070         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3071
3072         /* Enable modulator and associated divider */
3073         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3074         temp &= ~SBI_SSCCTL_DISABLE;
3075         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3076
3077         /* Wait for initialization time */
3078         udelay(24);
3079
3080         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3081
3082         mutex_unlock(&dev_priv->dpio_lock);
3083 }
3084
3085 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3086                                                 enum pipe pch_transcoder)
3087 {
3088         struct drm_device *dev = crtc->base.dev;
3089         struct drm_i915_private *dev_priv = dev->dev_private;
3090         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3091
3092         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3093                    I915_READ(HTOTAL(cpu_transcoder)));
3094         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3095                    I915_READ(HBLANK(cpu_transcoder)));
3096         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3097                    I915_READ(HSYNC(cpu_transcoder)));
3098
3099         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3100                    I915_READ(VTOTAL(cpu_transcoder)));
3101         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3102                    I915_READ(VBLANK(cpu_transcoder)));
3103         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3104                    I915_READ(VSYNC(cpu_transcoder)));
3105         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3106                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3107 }
3108
3109 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3110 {
3111         struct drm_i915_private *dev_priv = dev->dev_private;
3112         uint32_t temp;
3113
3114         temp = I915_READ(SOUTH_CHICKEN1);
3115         if (temp & FDI_BC_BIFURCATION_SELECT)
3116                 return;
3117
3118         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3119         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3120
3121         temp |= FDI_BC_BIFURCATION_SELECT;
3122         DRM_DEBUG_KMS("enabling fdi C rx\n");
3123         I915_WRITE(SOUTH_CHICKEN1, temp);
3124         POSTING_READ(SOUTH_CHICKEN1);
3125 }
3126
3127 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3128 {
3129         struct drm_device *dev = intel_crtc->base.dev;
3130         struct drm_i915_private *dev_priv = dev->dev_private;
3131
3132         switch (intel_crtc->pipe) {
3133         case PIPE_A:
3134                 break;
3135         case PIPE_B:
3136                 if (intel_crtc->config.fdi_lanes > 2)
3137                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3138                 else
3139                         cpt_enable_fdi_bc_bifurcation(dev);
3140
3141                 break;
3142         case PIPE_C:
3143                 cpt_enable_fdi_bc_bifurcation(dev);
3144
3145                 break;
3146         default:
3147                 BUG();
3148         }
3149 }
3150
3151 /*
3152  * Enable PCH resources required for PCH ports:
3153  *   - PCH PLLs
3154  *   - FDI training & RX/TX
3155  *   - update transcoder timings
3156  *   - DP transcoding bits
3157  *   - transcoder
3158  */
3159 static void ironlake_pch_enable(struct drm_crtc *crtc)
3160 {
3161         struct drm_device *dev = crtc->dev;
3162         struct drm_i915_private *dev_priv = dev->dev_private;
3163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3164         int pipe = intel_crtc->pipe;
3165         u32 reg, temp;
3166
3167         assert_pch_transcoder_disabled(dev_priv, pipe);
3168
3169         if (IS_IVYBRIDGE(dev))
3170                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3171
3172         /* Write the TU size bits before fdi link training, so that error
3173          * detection works. */
3174         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3175                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3176
3177         /* For PCH output, training FDI link */
3178         dev_priv->display.fdi_link_train(crtc);
3179
3180         /* We need to program the right clock selection before writing the pixel
3181          * mutliplier into the DPLL. */
3182         if (HAS_PCH_CPT(dev)) {
3183                 u32 sel;
3184
3185                 temp = I915_READ(PCH_DPLL_SEL);
3186                 temp |= TRANS_DPLL_ENABLE(pipe);
3187                 sel = TRANS_DPLLB_SEL(pipe);
3188                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3189                         temp |= sel;
3190                 else
3191                         temp &= ~sel;
3192                 I915_WRITE(PCH_DPLL_SEL, temp);
3193         }
3194
3195         /* XXX: pch pll's can be enabled any time before we enable the PCH
3196          * transcoder, and we actually should do this to not upset any PCH
3197          * transcoder that already use the clock when we share it.
3198          *
3199          * Note that enable_shared_dpll tries to do the right thing, but
3200          * get_shared_dpll unconditionally resets the pll - we need that to have
3201          * the right LVDS enable sequence. */
3202         ironlake_enable_shared_dpll(intel_crtc);
3203
3204         /* set transcoder timing, panel must allow it */
3205         assert_panel_unlocked(dev_priv, pipe);
3206         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3207
3208         intel_fdi_normal_train(crtc);
3209
3210         /* For PCH DP, enable TRANS_DP_CTL */
3211         if (HAS_PCH_CPT(dev) &&
3212             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3213              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3214                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3215                 reg = TRANS_DP_CTL(pipe);
3216                 temp = I915_READ(reg);
3217                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3218                           TRANS_DP_SYNC_MASK |
3219                           TRANS_DP_BPC_MASK);
3220                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3221                          TRANS_DP_ENH_FRAMING);
3222                 temp |= bpc << 9; /* same format but at 11:9 */
3223
3224                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3225                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3226                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3227                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3228
3229                 switch (intel_trans_dp_port_sel(crtc)) {
3230                 case PCH_DP_B:
3231                         temp |= TRANS_DP_PORT_SEL_B;
3232                         break;
3233                 case PCH_DP_C:
3234                         temp |= TRANS_DP_PORT_SEL_C;
3235                         break;
3236                 case PCH_DP_D:
3237                         temp |= TRANS_DP_PORT_SEL_D;
3238                         break;
3239                 default:
3240                         BUG();
3241                 }
3242
3243                 I915_WRITE(reg, temp);
3244         }
3245
3246         ironlake_enable_pch_transcoder(dev_priv, pipe);
3247 }
3248
3249 static void lpt_pch_enable(struct drm_crtc *crtc)
3250 {
3251         struct drm_device *dev = crtc->dev;
3252         struct drm_i915_private *dev_priv = dev->dev_private;
3253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3254         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3255
3256         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3257
3258         lpt_program_iclkip(crtc);
3259
3260         /* Set transcoder timing. */
3261         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3262
3263         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3264 }
3265
3266 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3267 {
3268         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3269
3270         if (pll == NULL)
3271                 return;
3272
3273         if (pll->refcount == 0) {
3274                 WARN(1, "bad %s refcount\n", pll->name);
3275                 return;
3276         }
3277
3278         if (--pll->refcount == 0) {
3279                 WARN_ON(pll->on);
3280                 WARN_ON(pll->active);
3281         }
3282
3283         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3284 }
3285
3286 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3287 {
3288         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3289         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3290         enum intel_dpll_id i;
3291
3292         if (pll) {
3293                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3294                               crtc->base.base.id, pll->name);
3295                 intel_put_shared_dpll(crtc);
3296         }
3297
3298         if (HAS_PCH_IBX(dev_priv->dev)) {
3299                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3300                 i = (enum intel_dpll_id) crtc->pipe;
3301                 pll = &dev_priv->shared_dplls[i];
3302
3303                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3304                               crtc->base.base.id, pll->name);
3305
3306                 goto found;
3307         }
3308
3309         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3310                 pll = &dev_priv->shared_dplls[i];
3311
3312                 /* Only want to check enabled timings first */
3313                 if (pll->refcount == 0)
3314                         continue;
3315
3316                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3317                            sizeof(pll->hw_state)) == 0) {
3318                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3319                                       crtc->base.base.id,
3320                                       pll->name, pll->refcount, pll->active);
3321
3322                         goto found;
3323                 }
3324         }
3325
3326         /* Ok no matching timings, maybe there's a free one? */
3327         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3328                 pll = &dev_priv->shared_dplls[i];
3329                 if (pll->refcount == 0) {
3330                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3331                                       crtc->base.base.id, pll->name);
3332                         goto found;
3333                 }
3334         }
3335
3336         return NULL;
3337
3338 found:
3339         crtc->config.shared_dpll = i;
3340         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3341                          pipe_name(crtc->pipe));
3342
3343         if (pll->active == 0) {
3344                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3345                        sizeof(pll->hw_state));
3346
3347                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3348                 WARN_ON(pll->on);
3349                 assert_shared_dpll_disabled(dev_priv, pll);
3350
3351                 pll->mode_set(dev_priv, pll);
3352         }
3353         pll->refcount++;
3354
3355         return pll;
3356 }
3357
3358 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3359 {
3360         struct drm_i915_private *dev_priv = dev->dev_private;
3361         int dslreg = PIPEDSL(pipe);
3362         u32 temp;
3363
3364         temp = I915_READ(dslreg);
3365         udelay(500);
3366         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3367                 if (wait_for(I915_READ(dslreg) != temp, 5))
3368                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3369         }
3370 }
3371
3372 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3373 {
3374         struct drm_device *dev = crtc->base.dev;
3375         struct drm_i915_private *dev_priv = dev->dev_private;
3376         int pipe = crtc->pipe;
3377
3378         if (crtc->config.pch_pfit.enabled) {
3379                 /* Force use of hard-coded filter coefficients
3380                  * as some pre-programmed values are broken,
3381                  * e.g. x201.
3382                  */
3383                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3384                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3385                                                  PF_PIPE_SEL_IVB(pipe));
3386                 else
3387                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3388                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3389                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3390         }
3391 }
3392
3393 static void intel_enable_planes(struct drm_crtc *crtc)
3394 {
3395         struct drm_device *dev = crtc->dev;
3396         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3397         struct intel_plane *intel_plane;
3398
3399         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3400                 if (intel_plane->pipe == pipe)
3401                         intel_plane_restore(&intel_plane->base);
3402 }
3403
3404 static void intel_disable_planes(struct drm_crtc *crtc)
3405 {
3406         struct drm_device *dev = crtc->dev;
3407         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3408         struct intel_plane *intel_plane;
3409
3410         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3411                 if (intel_plane->pipe == pipe)
3412                         intel_plane_disable(&intel_plane->base);
3413 }
3414
3415 void hsw_enable_ips(struct intel_crtc *crtc)
3416 {
3417         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3418
3419         if (!crtc->config.ips_enabled)
3420                 return;
3421
3422         /* We can only enable IPS after we enable a plane and wait for a vblank.
3423          * We guarantee that the plane is enabled by calling intel_enable_ips
3424          * only after intel_enable_plane. And intel_enable_plane already waits
3425          * for a vblank, so all we need to do here is to enable the IPS bit. */
3426         assert_plane_enabled(dev_priv, crtc->plane);
3427         if (IS_BROADWELL(crtc->base.dev)) {
3428                 mutex_lock(&dev_priv->rps.hw_lock);
3429                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3430                 mutex_unlock(&dev_priv->rps.hw_lock);
3431                 /* Quoting Art Runyan: "its not safe to expect any particular
3432                  * value in IPS_CTL bit 31 after enabling IPS through the
3433                  * mailbox." Moreover, the mailbox may return a bogus state,
3434                  * so we need to just enable it and continue on.
3435                  */
3436         } else {
3437                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3438                 /* The bit only becomes 1 in the next vblank, so this wait here
3439                  * is essentially intel_wait_for_vblank. If we don't have this
3440                  * and don't wait for vblanks until the end of crtc_enable, then
3441                  * the HW state readout code will complain that the expected
3442                  * IPS_CTL value is not the one we read. */
3443                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3444                         DRM_ERROR("Timed out waiting for IPS enable\n");
3445         }
3446 }
3447
3448 void hsw_disable_ips(struct intel_crtc *crtc)
3449 {
3450         struct drm_device *dev = crtc->base.dev;
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452
3453         if (!crtc->config.ips_enabled)
3454                 return;
3455
3456         assert_plane_enabled(dev_priv, crtc->plane);
3457         if (IS_BROADWELL(crtc->base.dev)) {
3458                 mutex_lock(&dev_priv->rps.hw_lock);
3459                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3460                 mutex_unlock(&dev_priv->rps.hw_lock);
3461         } else {
3462                 I915_WRITE(IPS_CTL, 0);
3463                 POSTING_READ(IPS_CTL);
3464         }
3465
3466         /* We need to wait for a vblank before we can disable the plane. */
3467         intel_wait_for_vblank(dev, crtc->pipe);
3468 }
3469
3470 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3471 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3472 {
3473         struct drm_device *dev = crtc->dev;
3474         struct drm_i915_private *dev_priv = dev->dev_private;
3475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3476         enum pipe pipe = intel_crtc->pipe;
3477         int palreg = PALETTE(pipe);
3478         int i;
3479         bool reenable_ips = false;
3480
3481         /* The clocks have to be on to load the palette. */
3482         if (!crtc->enabled || !intel_crtc->active)
3483                 return;
3484
3485         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3486                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3487                         assert_dsi_pll_enabled(dev_priv);
3488                 else
3489                         assert_pll_enabled(dev_priv, pipe);
3490         }
3491
3492         /* use legacy palette for Ironlake */
3493         if (HAS_PCH_SPLIT(dev))
3494                 palreg = LGC_PALETTE(pipe);
3495
3496         /* Workaround : Do not read or write the pipe palette/gamma data while
3497          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3498          */
3499         if (intel_crtc->config.ips_enabled &&
3500             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3501              GAMMA_MODE_MODE_SPLIT)) {
3502                 hsw_disable_ips(intel_crtc);
3503                 reenable_ips = true;
3504         }
3505
3506         for (i = 0; i < 256; i++) {
3507                 I915_WRITE(palreg + 4 * i,
3508                            (intel_crtc->lut_r[i] << 16) |
3509                            (intel_crtc->lut_g[i] << 8) |
3510                            intel_crtc->lut_b[i]);
3511         }
3512
3513         if (reenable_ips)
3514                 hsw_enable_ips(intel_crtc);
3515 }
3516
3517 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3518 {
3519         struct drm_device *dev = crtc->dev;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522         struct intel_encoder *encoder;
3523         int pipe = intel_crtc->pipe;
3524         int plane = intel_crtc->plane;
3525
3526         WARN_ON(!crtc->enabled);
3527
3528         if (intel_crtc->active)
3529                 return;
3530
3531         intel_crtc->active = true;
3532
3533         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3534         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3535
3536         for_each_encoder_on_crtc(dev, crtc, encoder)
3537                 if (encoder->pre_enable)
3538                         encoder->pre_enable(encoder);
3539
3540         if (intel_crtc->config.has_pch_encoder) {
3541                 /* Note: FDI PLL enabling _must_ be done before we enable the
3542                  * cpu pipes, hence this is separate from all the other fdi/pch
3543                  * enabling. */
3544                 ironlake_fdi_pll_enable(intel_crtc);
3545         } else {
3546                 assert_fdi_tx_disabled(dev_priv, pipe);
3547                 assert_fdi_rx_disabled(dev_priv, pipe);
3548         }
3549
3550         ironlake_pfit_enable(intel_crtc);
3551
3552         /*
3553          * On ILK+ LUT must be loaded before the pipe is running but with
3554          * clocks enabled
3555          */
3556         intel_crtc_load_lut(crtc);
3557
3558         intel_update_watermarks(crtc);
3559         intel_enable_pipe(dev_priv, pipe,
3560                           intel_crtc->config.has_pch_encoder, false);
3561         intel_enable_primary_plane(dev_priv, plane, pipe);
3562         intel_enable_planes(crtc);
3563         intel_crtc_update_cursor(crtc, true);
3564
3565         if (intel_crtc->config.has_pch_encoder)
3566                 ironlake_pch_enable(crtc);
3567
3568         mutex_lock(&dev->struct_mutex);
3569         intel_update_fbc(dev);
3570         mutex_unlock(&dev->struct_mutex);
3571
3572         for_each_encoder_on_crtc(dev, crtc, encoder)
3573                 encoder->enable(encoder);
3574
3575         if (HAS_PCH_CPT(dev))
3576                 cpt_verify_modeset(dev, intel_crtc->pipe);
3577
3578         /*
3579          * There seems to be a race in PCH platform hw (at least on some
3580          * outputs) where an enabled pipe still completes any pageflip right
3581          * away (as if the pipe is off) instead of waiting for vblank. As soon
3582          * as the first vblank happend, everything works as expected. Hence just
3583          * wait for one vblank before returning to avoid strange things
3584          * happening.
3585          */
3586         intel_wait_for_vblank(dev, intel_crtc->pipe);
3587 }
3588
3589 /* IPS only exists on ULT machines and is tied to pipe A. */
3590 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3591 {
3592         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3593 }
3594
3595 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3596 {
3597         struct drm_device *dev = crtc->dev;
3598         struct drm_i915_private *dev_priv = dev->dev_private;
3599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600         int pipe = intel_crtc->pipe;
3601         int plane = intel_crtc->plane;
3602
3603         intel_enable_primary_plane(dev_priv, plane, pipe);
3604         intel_enable_planes(crtc);
3605         intel_crtc_update_cursor(crtc, true);
3606
3607         hsw_enable_ips(intel_crtc);
3608
3609         mutex_lock(&dev->struct_mutex);
3610         intel_update_fbc(dev);
3611         mutex_unlock(&dev->struct_mutex);
3612 }
3613
3614 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3615 {
3616         struct drm_device *dev = crtc->dev;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619         int pipe = intel_crtc->pipe;
3620         int plane = intel_crtc->plane;
3621
3622         intel_crtc_wait_for_pending_flips(crtc);
3623         drm_vblank_off(dev, pipe);
3624
3625         /* FBC must be disabled before disabling the plane on HSW. */
3626         if (dev_priv->fbc.plane == plane)
3627                 intel_disable_fbc(dev);
3628
3629         hsw_disable_ips(intel_crtc);
3630
3631         intel_crtc_update_cursor(crtc, false);
3632         intel_disable_planes(crtc);
3633         intel_disable_primary_plane(dev_priv, plane, pipe);
3634 }
3635
3636 /*
3637  * This implements the workaround described in the "notes" section of the mode
3638  * set sequence documentation. When going from no pipes or single pipe to
3639  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3640  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3641  */
3642 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3643 {
3644         struct drm_device *dev = crtc->base.dev;
3645         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3646
3647         /* We want to get the other_active_crtc only if there's only 1 other
3648          * active crtc. */
3649         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3650                 if (!crtc_it->active || crtc_it == crtc)
3651                         continue;
3652
3653                 if (other_active_crtc)
3654                         return;
3655
3656                 other_active_crtc = crtc_it;
3657         }
3658         if (!other_active_crtc)
3659                 return;
3660
3661         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3662         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3663 }
3664
3665 static void haswell_crtc_enable(struct drm_crtc *crtc)
3666 {
3667         struct drm_device *dev = crtc->dev;
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670         struct intel_encoder *encoder;
3671         int pipe = intel_crtc->pipe;
3672
3673         WARN_ON(!crtc->enabled);
3674
3675         if (intel_crtc->active)
3676                 return;
3677
3678         intel_crtc->active = true;
3679
3680         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3681         if (intel_crtc->config.has_pch_encoder)
3682                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3683
3684         if (intel_crtc->config.has_pch_encoder)
3685                 dev_priv->display.fdi_link_train(crtc);
3686
3687         for_each_encoder_on_crtc(dev, crtc, encoder)
3688                 if (encoder->pre_enable)
3689                         encoder->pre_enable(encoder);
3690
3691         intel_ddi_enable_pipe_clock(intel_crtc);
3692
3693         ironlake_pfit_enable(intel_crtc);
3694
3695         /*
3696          * On ILK+ LUT must be loaded before the pipe is running but with
3697          * clocks enabled
3698          */
3699         intel_crtc_load_lut(crtc);
3700
3701         intel_ddi_set_pipe_settings(crtc);
3702         intel_ddi_enable_transcoder_func(crtc);
3703
3704         intel_update_watermarks(crtc);
3705         intel_enable_pipe(dev_priv, pipe,
3706                           intel_crtc->config.has_pch_encoder, false);
3707
3708         if (intel_crtc->config.has_pch_encoder)
3709                 lpt_pch_enable(crtc);
3710
3711         for_each_encoder_on_crtc(dev, crtc, encoder) {
3712                 encoder->enable(encoder);
3713                 intel_opregion_notify_encoder(encoder, true);
3714         }
3715
3716         /* If we change the relative order between pipe/planes enabling, we need
3717          * to change the workaround. */
3718         haswell_mode_set_planes_workaround(intel_crtc);
3719         haswell_crtc_enable_planes(crtc);
3720
3721         /*
3722          * There seems to be a race in PCH platform hw (at least on some
3723          * outputs) where an enabled pipe still completes any pageflip right
3724          * away (as if the pipe is off) instead of waiting for vblank. As soon
3725          * as the first vblank happend, everything works as expected. Hence just
3726          * wait for one vblank before returning to avoid strange things
3727          * happening.
3728          */
3729         intel_wait_for_vblank(dev, intel_crtc->pipe);
3730 }
3731
3732 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3733 {
3734         struct drm_device *dev = crtc->base.dev;
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         int pipe = crtc->pipe;
3737
3738         /* To avoid upsetting the power well on haswell only disable the pfit if
3739          * it's in use. The hw state code will make sure we get this right. */
3740         if (crtc->config.pch_pfit.enabled) {
3741                 I915_WRITE(PF_CTL(pipe), 0);
3742                 I915_WRITE(PF_WIN_POS(pipe), 0);
3743                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3744         }
3745 }
3746
3747 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3748 {
3749         struct drm_device *dev = crtc->dev;
3750         struct drm_i915_private *dev_priv = dev->dev_private;
3751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3752         struct intel_encoder *encoder;
3753         int pipe = intel_crtc->pipe;
3754         int plane = intel_crtc->plane;
3755         u32 reg, temp;
3756
3757
3758         if (!intel_crtc->active)
3759                 return;
3760
3761         for_each_encoder_on_crtc(dev, crtc, encoder)
3762                 encoder->disable(encoder);
3763
3764         intel_crtc_wait_for_pending_flips(crtc);
3765         drm_vblank_off(dev, pipe);
3766
3767         if (dev_priv->fbc.plane == plane)
3768                 intel_disable_fbc(dev);
3769
3770         intel_crtc_update_cursor(crtc, false);
3771         intel_disable_planes(crtc);
3772         intel_disable_primary_plane(dev_priv, plane, pipe);
3773
3774         if (intel_crtc->config.has_pch_encoder)
3775                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3776
3777         intel_disable_pipe(dev_priv, pipe);
3778
3779         ironlake_pfit_disable(intel_crtc);
3780
3781         for_each_encoder_on_crtc(dev, crtc, encoder)
3782                 if (encoder->post_disable)
3783                         encoder->post_disable(encoder);
3784
3785         if (intel_crtc->config.has_pch_encoder) {
3786                 ironlake_fdi_disable(crtc);
3787
3788                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3789                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3790
3791                 if (HAS_PCH_CPT(dev)) {
3792                         /* disable TRANS_DP_CTL */
3793                         reg = TRANS_DP_CTL(pipe);
3794                         temp = I915_READ(reg);
3795                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3796                                   TRANS_DP_PORT_SEL_MASK);
3797                         temp |= TRANS_DP_PORT_SEL_NONE;
3798                         I915_WRITE(reg, temp);
3799
3800                         /* disable DPLL_SEL */
3801                         temp = I915_READ(PCH_DPLL_SEL);
3802                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3803                         I915_WRITE(PCH_DPLL_SEL, temp);
3804                 }
3805
3806                 /* disable PCH DPLL */
3807                 intel_disable_shared_dpll(intel_crtc);
3808
3809                 ironlake_fdi_pll_disable(intel_crtc);
3810         }
3811
3812         intel_crtc->active = false;
3813         intel_update_watermarks(crtc);
3814
3815         mutex_lock(&dev->struct_mutex);
3816         intel_update_fbc(dev);
3817         mutex_unlock(&dev->struct_mutex);
3818 }
3819
3820 static void haswell_crtc_disable(struct drm_crtc *crtc)
3821 {
3822         struct drm_device *dev = crtc->dev;
3823         struct drm_i915_private *dev_priv = dev->dev_private;
3824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3825         struct intel_encoder *encoder;
3826         int pipe = intel_crtc->pipe;
3827         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3828
3829         if (!intel_crtc->active)
3830                 return;
3831
3832         haswell_crtc_disable_planes(crtc);
3833
3834         for_each_encoder_on_crtc(dev, crtc, encoder) {
3835                 intel_opregion_notify_encoder(encoder, false);
3836                 encoder->disable(encoder);
3837         }
3838
3839         if (intel_crtc->config.has_pch_encoder)
3840                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3841         intel_disable_pipe(dev_priv, pipe);
3842
3843         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3844
3845         ironlake_pfit_disable(intel_crtc);
3846
3847         intel_ddi_disable_pipe_clock(intel_crtc);
3848
3849         for_each_encoder_on_crtc(dev, crtc, encoder)
3850                 if (encoder->post_disable)
3851                         encoder->post_disable(encoder);
3852
3853         if (intel_crtc->config.has_pch_encoder) {
3854                 lpt_disable_pch_transcoder(dev_priv);
3855                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3856                 intel_ddi_fdi_disable(crtc);
3857         }
3858
3859         intel_crtc->active = false;
3860         intel_update_watermarks(crtc);
3861
3862         mutex_lock(&dev->struct_mutex);
3863         intel_update_fbc(dev);
3864         mutex_unlock(&dev->struct_mutex);
3865 }
3866
3867 static void ironlake_crtc_off(struct drm_crtc *crtc)
3868 {
3869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3870         intel_put_shared_dpll(intel_crtc);
3871 }
3872
3873 static void haswell_crtc_off(struct drm_crtc *crtc)
3874 {
3875         intel_ddi_put_crtc_pll(crtc);
3876 }
3877
3878 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3879 {
3880         if (!enable && intel_crtc->overlay) {
3881                 struct drm_device *dev = intel_crtc->base.dev;
3882                 struct drm_i915_private *dev_priv = dev->dev_private;
3883
3884                 mutex_lock(&dev->struct_mutex);
3885                 dev_priv->mm.interruptible = false;
3886                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3887                 dev_priv->mm.interruptible = true;
3888                 mutex_unlock(&dev->struct_mutex);
3889         }
3890
3891         /* Let userspace switch the overlay on again. In most cases userspace
3892          * has to recompute where to put it anyway.
3893          */
3894 }
3895
3896 /**
3897  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3898  * cursor plane briefly if not already running after enabling the display
3899  * plane.
3900  * This workaround avoids occasional blank screens when self refresh is
3901  * enabled.
3902  */
3903 static void
3904 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3905 {
3906         u32 cntl = I915_READ(CURCNTR(pipe));
3907
3908         if ((cntl & CURSOR_MODE) == 0) {
3909                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3910
3911                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3912                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3913                 intel_wait_for_vblank(dev_priv->dev, pipe);
3914                 I915_WRITE(CURCNTR(pipe), cntl);
3915                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3916                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3917         }
3918 }
3919
3920 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3921 {
3922         struct drm_device *dev = crtc->base.dev;
3923         struct drm_i915_private *dev_priv = dev->dev_private;
3924         struct intel_crtc_config *pipe_config = &crtc->config;
3925
3926         if (!crtc->config.gmch_pfit.control)
3927                 return;
3928
3929         /*
3930          * The panel fitter should only be adjusted whilst the pipe is disabled,
3931          * according to register description and PRM.
3932          */
3933         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3934         assert_pipe_disabled(dev_priv, crtc->pipe);
3935
3936         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3937         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3938
3939         /* Border color in case we don't scale up to the full screen. Black by
3940          * default, change to something else for debugging. */
3941         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3942 }
3943
3944 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3945 {
3946         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3947
3948         /* Obtain SKU information */
3949         mutex_lock(&dev_priv->dpio_lock);
3950         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3951                 CCK_FUSE_HPLL_FREQ_MASK;
3952         mutex_unlock(&dev_priv->dpio_lock);
3953
3954         return vco_freq[hpll_freq];
3955 }
3956
3957 /* Adjust CDclk dividers to allow high res or save power if possible */
3958 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3959 {
3960         struct drm_i915_private *dev_priv = dev->dev_private;
3961         u32 val, cmd;
3962
3963         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3964                 cmd = 2;
3965         else if (cdclk == 266)
3966                 cmd = 1;
3967         else
3968                 cmd = 0;
3969
3970         mutex_lock(&dev_priv->rps.hw_lock);
3971         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3972         val &= ~DSPFREQGUAR_MASK;
3973         val |= (cmd << DSPFREQGUAR_SHIFT);
3974         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3975         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3976                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3977                      50)) {
3978                 DRM_ERROR("timed out waiting for CDclk change\n");
3979         }
3980         mutex_unlock(&dev_priv->rps.hw_lock);
3981
3982         if (cdclk == 400) {
3983                 u32 divider, vco;
3984
3985                 vco = valleyview_get_vco(dev_priv);
3986                 divider = ((vco << 1) / cdclk) - 1;
3987
3988                 mutex_lock(&dev_priv->dpio_lock);
3989                 /* adjust cdclk divider */
3990                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3991                 val &= ~0xf;
3992                 val |= divider;
3993                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3994                 mutex_unlock(&dev_priv->dpio_lock);
3995         }
3996
3997         mutex_lock(&dev_priv->dpio_lock);
3998         /* adjust self-refresh exit latency value */
3999         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4000         val &= ~0x7f;
4001
4002         /*
4003          * For high bandwidth configs, we set a higher latency in the bunit
4004          * so that the core display fetch happens in time to avoid underruns.
4005          */
4006         if (cdclk == 400)
4007                 val |= 4500 / 250; /* 4.5 usec */
4008         else
4009                 val |= 3000 / 250; /* 3.0 usec */
4010         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4011         mutex_unlock(&dev_priv->dpio_lock);
4012
4013         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4014         intel_i2c_reset(dev);
4015 }
4016
4017 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4018 {
4019         int cur_cdclk, vco;
4020         int divider;
4021
4022         vco = valleyview_get_vco(dev_priv);
4023
4024         mutex_lock(&dev_priv->dpio_lock);
4025         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4026         mutex_unlock(&dev_priv->dpio_lock);
4027
4028         divider &= 0xf;
4029
4030         cur_cdclk = (vco << 1) / (divider + 1);
4031
4032         return cur_cdclk;
4033 }
4034
4035 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4036                                  int max_pixclk)
4037 {
4038         int cur_cdclk;
4039
4040         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4041
4042         /*
4043          * Really only a few cases to deal with, as only 4 CDclks are supported:
4044          *   200MHz
4045          *   267MHz
4046          *   320MHz
4047          *   400MHz
4048          * So we check to see whether we're above 90% of the lower bin and
4049          * adjust if needed.
4050          */
4051         if (max_pixclk > 288000) {
4052                 return 400;
4053         } else if (max_pixclk > 240000) {
4054                 return 320;
4055         } else
4056                 return 266;
4057         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4058 }
4059
4060 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4061                                  unsigned modeset_pipes,
4062                                  struct intel_crtc_config *pipe_config)
4063 {
4064         struct drm_device *dev = dev_priv->dev;
4065         struct intel_crtc *intel_crtc;
4066         int max_pixclk = 0;
4067
4068         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4069                             base.head) {
4070                 if (modeset_pipes & (1 << intel_crtc->pipe))
4071                         max_pixclk = max(max_pixclk,
4072                                          pipe_config->adjusted_mode.crtc_clock);
4073                 else if (intel_crtc->base.enabled)
4074                         max_pixclk = max(max_pixclk,
4075                                          intel_crtc->config.adjusted_mode.crtc_clock);
4076         }
4077
4078         return max_pixclk;
4079 }
4080
4081 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4082                                             unsigned *prepare_pipes,
4083                                             unsigned modeset_pipes,
4084                                             struct intel_crtc_config *pipe_config)
4085 {
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct intel_crtc *intel_crtc;
4088         int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4089                                                pipe_config);
4090         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4091
4092         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4093                 return;
4094
4095         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4096                             base.head)
4097                 if (intel_crtc->base.enabled)
4098                         *prepare_pipes |= (1 << intel_crtc->pipe);
4099 }
4100
4101 static void valleyview_modeset_global_resources(struct drm_device *dev)
4102 {
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4105         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4106         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4107
4108         if (req_cdclk != cur_cdclk)
4109                 valleyview_set_cdclk(dev, req_cdclk);
4110 }
4111
4112 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4113 {
4114         struct drm_device *dev = crtc->dev;
4115         struct drm_i915_private *dev_priv = dev->dev_private;
4116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117         struct intel_encoder *encoder;
4118         int pipe = intel_crtc->pipe;
4119         int plane = intel_crtc->plane;
4120         bool is_dsi;
4121
4122         WARN_ON(!crtc->enabled);
4123
4124         if (intel_crtc->active)
4125                 return;
4126
4127         intel_crtc->active = true;
4128
4129         for_each_encoder_on_crtc(dev, crtc, encoder)
4130                 if (encoder->pre_pll_enable)
4131                         encoder->pre_pll_enable(encoder);
4132
4133         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4134
4135         if (!is_dsi)
4136                 vlv_enable_pll(intel_crtc);
4137
4138         for_each_encoder_on_crtc(dev, crtc, encoder)
4139                 if (encoder->pre_enable)
4140                         encoder->pre_enable(encoder);
4141
4142         i9xx_pfit_enable(intel_crtc);
4143
4144         intel_crtc_load_lut(crtc);
4145
4146         intel_update_watermarks(crtc);
4147         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4148         intel_enable_primary_plane(dev_priv, plane, pipe);
4149         intel_enable_planes(crtc);
4150         intel_crtc_update_cursor(crtc, true);
4151
4152         intel_update_fbc(dev);
4153
4154         for_each_encoder_on_crtc(dev, crtc, encoder)
4155                 encoder->enable(encoder);
4156 }
4157
4158 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4159 {
4160         struct drm_device *dev = crtc->dev;
4161         struct drm_i915_private *dev_priv = dev->dev_private;
4162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4163         struct intel_encoder *encoder;
4164         int pipe = intel_crtc->pipe;
4165         int plane = intel_crtc->plane;
4166
4167         WARN_ON(!crtc->enabled);
4168
4169         if (intel_crtc->active)
4170                 return;
4171
4172         intel_crtc->active = true;
4173
4174         for_each_encoder_on_crtc(dev, crtc, encoder)
4175                 if (encoder->pre_enable)
4176                         encoder->pre_enable(encoder);
4177
4178         i9xx_enable_pll(intel_crtc);
4179
4180         i9xx_pfit_enable(intel_crtc);
4181
4182         intel_crtc_load_lut(crtc);
4183
4184         intel_update_watermarks(crtc);
4185         intel_enable_pipe(dev_priv, pipe, false, false);
4186         intel_enable_primary_plane(dev_priv, plane, pipe);
4187         intel_enable_planes(crtc);
4188         /* The fixup needs to happen before cursor is enabled */
4189         if (IS_G4X(dev))
4190                 g4x_fixup_plane(dev_priv, pipe);
4191         intel_crtc_update_cursor(crtc, true);
4192
4193         /* Give the overlay scaler a chance to enable if it's on this pipe */
4194         intel_crtc_dpms_overlay(intel_crtc, true);
4195
4196         intel_update_fbc(dev);
4197
4198         for_each_encoder_on_crtc(dev, crtc, encoder)
4199                 encoder->enable(encoder);
4200 }
4201
4202 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4203 {
4204         struct drm_device *dev = crtc->base.dev;
4205         struct drm_i915_private *dev_priv = dev->dev_private;
4206
4207         if (!crtc->config.gmch_pfit.control)
4208                 return;
4209
4210         assert_pipe_disabled(dev_priv, crtc->pipe);
4211
4212         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4213                          I915_READ(PFIT_CONTROL));
4214         I915_WRITE(PFIT_CONTROL, 0);
4215 }
4216
4217 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4218 {
4219         struct drm_device *dev = crtc->dev;
4220         struct drm_i915_private *dev_priv = dev->dev_private;
4221         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4222         struct intel_encoder *encoder;
4223         int pipe = intel_crtc->pipe;
4224         int plane = intel_crtc->plane;
4225
4226         if (!intel_crtc->active)
4227                 return;
4228
4229         for_each_encoder_on_crtc(dev, crtc, encoder)
4230                 encoder->disable(encoder);
4231
4232         /* Give the overlay scaler a chance to disable if it's on this pipe */
4233         intel_crtc_wait_for_pending_flips(crtc);
4234         drm_vblank_off(dev, pipe);
4235
4236         if (dev_priv->fbc.plane == plane)
4237                 intel_disable_fbc(dev);
4238
4239         intel_crtc_dpms_overlay(intel_crtc, false);
4240         intel_crtc_update_cursor(crtc, false);
4241         intel_disable_planes(crtc);
4242         intel_disable_primary_plane(dev_priv, plane, pipe);
4243
4244         intel_disable_pipe(dev_priv, pipe);
4245
4246         i9xx_pfit_disable(intel_crtc);
4247
4248         for_each_encoder_on_crtc(dev, crtc, encoder)
4249                 if (encoder->post_disable)
4250                         encoder->post_disable(encoder);
4251
4252         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4253                 vlv_disable_pll(dev_priv, pipe);
4254         else if (!IS_VALLEYVIEW(dev))
4255                 i9xx_disable_pll(dev_priv, pipe);
4256
4257         intel_crtc->active = false;
4258         intel_update_watermarks(crtc);
4259
4260         intel_update_fbc(dev);
4261 }
4262
4263 static void i9xx_crtc_off(struct drm_crtc *crtc)
4264 {
4265 }
4266
4267 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4268                                     bool enabled)
4269 {
4270         struct drm_device *dev = crtc->dev;
4271         struct drm_i915_master_private *master_priv;
4272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273         int pipe = intel_crtc->pipe;
4274
4275         if (!dev->primary->master)
4276                 return;
4277
4278         master_priv = dev->primary->master->driver_priv;
4279         if (!master_priv->sarea_priv)
4280                 return;
4281
4282         switch (pipe) {
4283         case 0:
4284                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4285                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4286                 break;
4287         case 1:
4288                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4289                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4290                 break;
4291         default:
4292                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4293                 break;
4294         }
4295 }
4296
4297 /**
4298  * Sets the power management mode of the pipe and plane.
4299  */
4300 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4301 {
4302         struct drm_device *dev = crtc->dev;
4303         struct drm_i915_private *dev_priv = dev->dev_private;
4304         struct intel_encoder *intel_encoder;
4305         bool enable = false;
4306
4307         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4308                 enable |= intel_encoder->connectors_active;
4309
4310         if (enable)
4311                 dev_priv->display.crtc_enable(crtc);
4312         else
4313                 dev_priv->display.crtc_disable(crtc);
4314
4315         intel_crtc_update_sarea(crtc, enable);
4316 }
4317
4318 static void intel_crtc_disable(struct drm_crtc *crtc)
4319 {
4320         struct drm_device *dev = crtc->dev;
4321         struct drm_connector *connector;
4322         struct drm_i915_private *dev_priv = dev->dev_private;
4323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4324
4325         /* crtc should still be enabled when we disable it. */
4326         WARN_ON(!crtc->enabled);
4327
4328         dev_priv->display.crtc_disable(crtc);
4329         intel_crtc->eld_vld = false;
4330         intel_crtc_update_sarea(crtc, false);
4331         dev_priv->display.off(crtc);
4332
4333         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4334         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4335         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4336
4337         if (crtc->fb) {
4338                 mutex_lock(&dev->struct_mutex);
4339                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4340                 mutex_unlock(&dev->struct_mutex);
4341                 crtc->fb = NULL;
4342         }
4343
4344         /* Update computed state. */
4345         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4346                 if (!connector->encoder || !connector->encoder->crtc)
4347                         continue;
4348
4349                 if (connector->encoder->crtc != crtc)
4350                         continue;
4351
4352                 connector->dpms = DRM_MODE_DPMS_OFF;
4353                 to_intel_encoder(connector->encoder)->connectors_active = false;
4354         }
4355 }
4356
4357 void intel_encoder_destroy(struct drm_encoder *encoder)
4358 {
4359         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4360
4361         drm_encoder_cleanup(encoder);
4362         kfree(intel_encoder);
4363 }
4364
4365 /* Simple dpms helper for encoders with just one connector, no cloning and only
4366  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4367  * state of the entire output pipe. */
4368 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4369 {
4370         if (mode == DRM_MODE_DPMS_ON) {
4371                 encoder->connectors_active = true;
4372
4373                 intel_crtc_update_dpms(encoder->base.crtc);
4374         } else {
4375                 encoder->connectors_active = false;
4376
4377                 intel_crtc_update_dpms(encoder->base.crtc);
4378         }
4379 }
4380
4381 /* Cross check the actual hw state with our own modeset state tracking (and it's
4382  * internal consistency). */
4383 static void intel_connector_check_state(struct intel_connector *connector)
4384 {
4385         if (connector->get_hw_state(connector)) {
4386                 struct intel_encoder *encoder = connector->encoder;
4387                 struct drm_crtc *crtc;
4388                 bool encoder_enabled;
4389                 enum pipe pipe;
4390
4391                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4392                               connector->base.base.id,
4393                               drm_get_connector_name(&connector->base));
4394
4395                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4396                      "wrong connector dpms state\n");
4397                 WARN(connector->base.encoder != &encoder->base,
4398                      "active connector not linked to encoder\n");
4399                 WARN(!encoder->connectors_active,
4400                      "encoder->connectors_active not set\n");
4401
4402                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4403                 WARN(!encoder_enabled, "encoder not enabled\n");
4404                 if (WARN_ON(!encoder->base.crtc))
4405                         return;
4406
4407                 crtc = encoder->base.crtc;
4408
4409                 WARN(!crtc->enabled, "crtc not enabled\n");
4410                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4411                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4412                      "encoder active on the wrong pipe\n");
4413         }
4414 }
4415
4416 /* Even simpler default implementation, if there's really no special case to
4417  * consider. */
4418 void intel_connector_dpms(struct drm_connector *connector, int mode)
4419 {
4420         /* All the simple cases only support two dpms states. */
4421         if (mode != DRM_MODE_DPMS_ON)
4422                 mode = DRM_MODE_DPMS_OFF;
4423
4424         if (mode == connector->dpms)
4425                 return;
4426
4427         connector->dpms = mode;
4428
4429         /* Only need to change hw state when actually enabled */
4430         if (connector->encoder)
4431                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4432
4433         intel_modeset_check_state(connector->dev);
4434 }
4435
4436 /* Simple connector->get_hw_state implementation for encoders that support only
4437  * one connector and no cloning and hence the encoder state determines the state
4438  * of the connector. */
4439 bool intel_connector_get_hw_state(struct intel_connector *connector)
4440 {
4441         enum pipe pipe = 0;
4442         struct intel_encoder *encoder = connector->encoder;
4443
4444         return encoder->get_hw_state(encoder, &pipe);
4445 }
4446
4447 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4448                                      struct intel_crtc_config *pipe_config)
4449 {
4450         struct drm_i915_private *dev_priv = dev->dev_private;
4451         struct intel_crtc *pipe_B_crtc =
4452                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4453
4454         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4455                       pipe_name(pipe), pipe_config->fdi_lanes);
4456         if (pipe_config->fdi_lanes > 4) {
4457                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4458                               pipe_name(pipe), pipe_config->fdi_lanes);
4459                 return false;
4460         }
4461
4462         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4463                 if (pipe_config->fdi_lanes > 2) {
4464                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4465                                       pipe_config->fdi_lanes);
4466                         return false;
4467                 } else {
4468                         return true;
4469                 }
4470         }
4471
4472         if (INTEL_INFO(dev)->num_pipes == 2)
4473                 return true;
4474
4475         /* Ivybridge 3 pipe is really complicated */
4476         switch (pipe) {
4477         case PIPE_A:
4478                 return true;
4479         case PIPE_B:
4480                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4481                     pipe_config->fdi_lanes > 2) {
4482                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4483                                       pipe_name(pipe), pipe_config->fdi_lanes);
4484                         return false;
4485                 }
4486                 return true;
4487         case PIPE_C:
4488                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4489                     pipe_B_crtc->config.fdi_lanes <= 2) {
4490                         if (pipe_config->fdi_lanes > 2) {
4491                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4492                                               pipe_name(pipe), pipe_config->fdi_lanes);
4493                                 return false;
4494                         }
4495                 } else {
4496                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4497                         return false;
4498                 }
4499                 return true;
4500         default:
4501                 BUG();
4502         }
4503 }
4504
4505 #define RETRY 1
4506 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4507                                        struct intel_crtc_config *pipe_config)
4508 {
4509         struct drm_device *dev = intel_crtc->base.dev;
4510         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4511         int lane, link_bw, fdi_dotclock;
4512         bool setup_ok, needs_recompute = false;
4513
4514 retry:
4515         /* FDI is a binary signal running at ~2.7GHz, encoding
4516          * each output octet as 10 bits. The actual frequency
4517          * is stored as a divider into a 100MHz clock, and the
4518          * mode pixel clock is stored in units of 1KHz.
4519          * Hence the bw of each lane in terms of the mode signal
4520          * is:
4521          */
4522         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4523
4524         fdi_dotclock = adjusted_mode->crtc_clock;
4525
4526         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4527                                            pipe_config->pipe_bpp);
4528
4529         pipe_config->fdi_lanes = lane;
4530
4531         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4532                                link_bw, &pipe_config->fdi_m_n);
4533
4534         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4535                                             intel_crtc->pipe, pipe_config);
4536         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4537                 pipe_config->pipe_bpp -= 2*3;
4538                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4539                               pipe_config->pipe_bpp);
4540                 needs_recompute = true;
4541                 pipe_config->bw_constrained = true;
4542
4543                 goto retry;
4544         }
4545
4546         if (needs_recompute)
4547                 return RETRY;
4548
4549         return setup_ok ? 0 : -EINVAL;
4550 }
4551
4552 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4553                                    struct intel_crtc_config *pipe_config)
4554 {
4555         pipe_config->ips_enabled = i915_enable_ips &&
4556                                    hsw_crtc_supports_ips(crtc) &&
4557                                    pipe_config->pipe_bpp <= 24;
4558 }
4559
4560 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4561                                      struct intel_crtc_config *pipe_config)
4562 {
4563         struct drm_device *dev = crtc->base.dev;
4564         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4565
4566         /* FIXME should check pixel clock limits on all platforms */
4567         if (INTEL_INFO(dev)->gen < 4) {
4568                 struct drm_i915_private *dev_priv = dev->dev_private;
4569                 int clock_limit =
4570                         dev_priv->display.get_display_clock_speed(dev);
4571
4572                 /*
4573                  * Enable pixel doubling when the dot clock
4574                  * is > 90% of the (display) core speed.
4575                  *
4576                  * GDG double wide on either pipe,
4577                  * otherwise pipe A only.
4578                  */
4579                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4580                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4581                         clock_limit *= 2;
4582                         pipe_config->double_wide = true;
4583                 }
4584
4585                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4586                         return -EINVAL;
4587         }
4588
4589         /*
4590          * Pipe horizontal size must be even in:
4591          * - DVO ganged mode
4592          * - LVDS dual channel mode
4593          * - Double wide pipe
4594          */
4595         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4596              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4597                 pipe_config->pipe_src_w &= ~1;
4598
4599         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4600          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4601          */
4602         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4603                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4604                 return -EINVAL;
4605
4606         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4607                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4608         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4609                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4610                  * for lvds. */
4611                 pipe_config->pipe_bpp = 8*3;
4612         }
4613
4614         if (HAS_IPS(dev))
4615                 hsw_compute_ips_config(crtc, pipe_config);
4616
4617         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4618          * clock survives for now. */
4619         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4620                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4621
4622         if (pipe_config->has_pch_encoder)
4623                 return ironlake_fdi_compute_config(crtc, pipe_config);
4624
4625         return 0;
4626 }
4627
4628 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4629 {
4630         return 400000; /* FIXME */
4631 }
4632
4633 static int i945_get_display_clock_speed(struct drm_device *dev)
4634 {
4635         return 400000;
4636 }
4637
4638 static int i915_get_display_clock_speed(struct drm_device *dev)
4639 {
4640         return 333000;
4641 }
4642
4643 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4644 {
4645         return 200000;
4646 }
4647
4648 static int pnv_get_display_clock_speed(struct drm_device *dev)
4649 {
4650         u16 gcfgc = 0;
4651
4652         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4653
4654         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4655         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4656                 return 267000;
4657         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4658                 return 333000;
4659         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4660                 return 444000;
4661         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4662                 return 200000;
4663         default:
4664                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4665         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4666                 return 133000;
4667         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4668                 return 167000;
4669         }
4670 }
4671
4672 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4673 {
4674         u16 gcfgc = 0;
4675
4676         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4677
4678         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4679                 return 133000;
4680         else {
4681                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4682                 case GC_DISPLAY_CLOCK_333_MHZ:
4683                         return 333000;
4684                 default:
4685                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4686                         return 190000;
4687                 }
4688         }
4689 }
4690
4691 static int i865_get_display_clock_speed(struct drm_device *dev)
4692 {
4693         return 266000;
4694 }
4695
4696 static int i855_get_display_clock_speed(struct drm_device *dev)
4697 {
4698         u16 hpllcc = 0;
4699         /* Assume that the hardware is in the high speed state.  This
4700          * should be the default.
4701          */
4702         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4703         case GC_CLOCK_133_200:
4704         case GC_CLOCK_100_200:
4705                 return 200000;
4706         case GC_CLOCK_166_250:
4707                 return 250000;
4708         case GC_CLOCK_100_133:
4709                 return 133000;
4710         }
4711
4712         /* Shouldn't happen */
4713         return 0;
4714 }
4715
4716 static int i830_get_display_clock_speed(struct drm_device *dev)
4717 {
4718         return 133000;
4719 }
4720
4721 static void
4722 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4723 {
4724         while (*num > DATA_LINK_M_N_MASK ||
4725                *den > DATA_LINK_M_N_MASK) {
4726                 *num >>= 1;
4727                 *den >>= 1;
4728         }
4729 }
4730
4731 static void compute_m_n(unsigned int m, unsigned int n,
4732                         uint32_t *ret_m, uint32_t *ret_n)
4733 {
4734         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4735         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4736         intel_reduce_m_n_ratio(ret_m, ret_n);
4737 }
4738
4739 void
4740 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4741                        int pixel_clock, int link_clock,
4742                        struct intel_link_m_n *m_n)
4743 {
4744         m_n->tu = 64;
4745
4746         compute_m_n(bits_per_pixel * pixel_clock,
4747                     link_clock * nlanes * 8,
4748                     &m_n->gmch_m, &m_n->gmch_n);
4749
4750         compute_m_n(pixel_clock, link_clock,
4751                     &m_n->link_m, &m_n->link_n);
4752 }
4753
4754 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4755 {
4756         if (i915_panel_use_ssc >= 0)
4757                 return i915_panel_use_ssc != 0;
4758         return dev_priv->vbt.lvds_use_ssc
4759                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4760 }
4761
4762 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4763 {
4764         struct drm_device *dev = crtc->dev;
4765         struct drm_i915_private *dev_priv = dev->dev_private;
4766         int refclk;
4767
4768         if (IS_VALLEYVIEW(dev)) {
4769                 refclk = 100000;
4770         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4771             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4772                 refclk = dev_priv->vbt.lvds_ssc_freq;
4773                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4774         } else if (!IS_GEN2(dev)) {
4775                 refclk = 96000;
4776         } else {
4777                 refclk = 48000;
4778         }
4779
4780         return refclk;
4781 }
4782
4783 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4784 {
4785         return (1 << dpll->n) << 16 | dpll->m2;
4786 }
4787
4788 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4789 {
4790         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4791 }
4792
4793 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4794                                      intel_clock_t *reduced_clock)
4795 {
4796         struct drm_device *dev = crtc->base.dev;
4797         struct drm_i915_private *dev_priv = dev->dev_private;
4798         int pipe = crtc->pipe;
4799         u32 fp, fp2 = 0;
4800
4801         if (IS_PINEVIEW(dev)) {
4802                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4803                 if (reduced_clock)
4804                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4805         } else {
4806                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4807                 if (reduced_clock)
4808                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4809         }
4810
4811         I915_WRITE(FP0(pipe), fp);
4812         crtc->config.dpll_hw_state.fp0 = fp;
4813
4814         crtc->lowfreq_avail = false;
4815         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4816             reduced_clock && i915_powersave) {
4817                 I915_WRITE(FP1(pipe), fp2);
4818                 crtc->config.dpll_hw_state.fp1 = fp2;
4819                 crtc->lowfreq_avail = true;
4820         } else {
4821                 I915_WRITE(FP1(pipe), fp);
4822                 crtc->config.dpll_hw_state.fp1 = fp;
4823         }
4824 }
4825
4826 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4827                 pipe)
4828 {
4829         u32 reg_val;
4830
4831         /*
4832          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4833          * and set it to a reasonable value instead.
4834          */
4835         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4836         reg_val &= 0xffffff00;
4837         reg_val |= 0x00000030;
4838         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4839
4840         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4841         reg_val &= 0x8cffffff;
4842         reg_val = 0x8c000000;
4843         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4844
4845         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4846         reg_val &= 0xffffff00;
4847         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4848
4849         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4850         reg_val &= 0x00ffffff;
4851         reg_val |= 0xb0000000;
4852         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4853 }
4854
4855 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4856                                          struct intel_link_m_n *m_n)
4857 {
4858         struct drm_device *dev = crtc->base.dev;
4859         struct drm_i915_private *dev_priv = dev->dev_private;
4860         int pipe = crtc->pipe;
4861
4862         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4863         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4864         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4865         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4866 }
4867
4868 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4869                                          struct intel_link_m_n *m_n)
4870 {
4871         struct drm_device *dev = crtc->base.dev;
4872         struct drm_i915_private *dev_priv = dev->dev_private;
4873         int pipe = crtc->pipe;
4874         enum transcoder transcoder = crtc->config.cpu_transcoder;
4875
4876         if (INTEL_INFO(dev)->gen >= 5) {
4877                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4878                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4879                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4880                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4881         } else {
4882                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4883                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4884                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4885                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4886         }
4887 }
4888
4889 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4890 {
4891         if (crtc->config.has_pch_encoder)
4892                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4893         else
4894                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4895 }
4896
4897 static void vlv_update_pll(struct intel_crtc *crtc)
4898 {
4899         struct drm_device *dev = crtc->base.dev;
4900         struct drm_i915_private *dev_priv = dev->dev_private;
4901         int pipe = crtc->pipe;
4902         u32 dpll, mdiv;
4903         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4904         u32 coreclk, reg_val, dpll_md;
4905
4906         mutex_lock(&dev_priv->dpio_lock);
4907
4908         bestn = crtc->config.dpll.n;
4909         bestm1 = crtc->config.dpll.m1;
4910         bestm2 = crtc->config.dpll.m2;
4911         bestp1 = crtc->config.dpll.p1;
4912         bestp2 = crtc->config.dpll.p2;
4913
4914         /* See eDP HDMI DPIO driver vbios notes doc */
4915
4916         /* PLL B needs special handling */
4917         if (pipe)
4918                 vlv_pllb_recal_opamp(dev_priv, pipe);
4919
4920         /* Set up Tx target for periodic Rcomp update */
4921         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4922
4923         /* Disable target IRef on PLL */
4924         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4925         reg_val &= 0x00ffffff;
4926         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4927
4928         /* Disable fast lock */
4929         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4930
4931         /* Set idtafcrecal before PLL is enabled */
4932         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4933         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4934         mdiv |= ((bestn << DPIO_N_SHIFT));
4935         mdiv |= (1 << DPIO_K_SHIFT);
4936
4937         /*
4938          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4939          * but we don't support that).
4940          * Note: don't use the DAC post divider as it seems unstable.
4941          */
4942         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4943         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4944
4945         mdiv |= DPIO_ENABLE_CALIBRATION;
4946         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4947
4948         /* Set HBR and RBR LPF coefficients */
4949         if (crtc->config.port_clock == 162000 ||
4950             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4951             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4952                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4953                                  0x009f0003);
4954         else
4955                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4956                                  0x00d0000f);
4957
4958         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4959             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4960                 /* Use SSC source */
4961                 if (!pipe)
4962                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4963                                          0x0df40000);
4964                 else
4965                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4966                                          0x0df70000);
4967         } else { /* HDMI or VGA */
4968                 /* Use bend source */
4969                 if (!pipe)
4970                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4971                                          0x0df70000);
4972                 else
4973                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4974                                          0x0df40000);
4975         }
4976
4977         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4978         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4979         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4980             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4981                 coreclk |= 0x01000000;
4982         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4983
4984         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4985
4986         /* Enable DPIO clock input */
4987         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4988                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4989         /* We should never disable this, set it here for state tracking */
4990         if (pipe == PIPE_B)
4991                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4992         dpll |= DPLL_VCO_ENABLE;
4993         crtc->config.dpll_hw_state.dpll = dpll;
4994
4995         dpll_md = (crtc->config.pixel_multiplier - 1)
4996                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4997         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4998
4999         if (crtc->config.has_dp_encoder)
5000                 intel_dp_set_m_n(crtc);
5001
5002         mutex_unlock(&dev_priv->dpio_lock);
5003 }
5004
5005 static void i9xx_update_pll(struct intel_crtc *crtc,
5006                             intel_clock_t *reduced_clock,
5007                             int num_connectors)
5008 {
5009         struct drm_device *dev = crtc->base.dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         u32 dpll;
5012         bool is_sdvo;
5013         struct dpll *clock = &crtc->config.dpll;
5014
5015         i9xx_update_pll_dividers(crtc, reduced_clock);
5016
5017         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5018                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5019
5020         dpll = DPLL_VGA_MODE_DIS;
5021
5022         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5023                 dpll |= DPLLB_MODE_LVDS;
5024         else
5025                 dpll |= DPLLB_MODE_DAC_SERIAL;
5026
5027         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5028                 dpll |= (crtc->config.pixel_multiplier - 1)
5029                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5030         }
5031
5032         if (is_sdvo)
5033                 dpll |= DPLL_SDVO_HIGH_SPEED;
5034
5035         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5036                 dpll |= DPLL_SDVO_HIGH_SPEED;
5037
5038         /* compute bitmask from p1 value */
5039         if (IS_PINEVIEW(dev))
5040                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5041         else {
5042                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5043                 if (IS_G4X(dev) && reduced_clock)
5044                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5045         }
5046         switch (clock->p2) {
5047         case 5:
5048                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5049                 break;
5050         case 7:
5051                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5052                 break;
5053         case 10:
5054                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5055                 break;
5056         case 14:
5057                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5058                 break;
5059         }
5060         if (INTEL_INFO(dev)->gen >= 4)
5061                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5062
5063         if (crtc->config.sdvo_tv_clock)
5064                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5065         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5066                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5067                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5068         else
5069                 dpll |= PLL_REF_INPUT_DREFCLK;
5070
5071         dpll |= DPLL_VCO_ENABLE;
5072         crtc->config.dpll_hw_state.dpll = dpll;
5073
5074         if (INTEL_INFO(dev)->gen >= 4) {
5075                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5076                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5077                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5078         }
5079
5080         if (crtc->config.has_dp_encoder)
5081                 intel_dp_set_m_n(crtc);
5082 }
5083
5084 static void i8xx_update_pll(struct intel_crtc *crtc,
5085                             intel_clock_t *reduced_clock,
5086                             int num_connectors)
5087 {
5088         struct drm_device *dev = crtc->base.dev;
5089         struct drm_i915_private *dev_priv = dev->dev_private;
5090         u32 dpll;
5091         struct dpll *clock = &crtc->config.dpll;
5092
5093         i9xx_update_pll_dividers(crtc, reduced_clock);
5094
5095         dpll = DPLL_VGA_MODE_DIS;
5096
5097         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5098                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5099         } else {
5100                 if (clock->p1 == 2)
5101                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5102                 else
5103                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5104                 if (clock->p2 == 4)
5105                         dpll |= PLL_P2_DIVIDE_BY_4;
5106         }
5107
5108         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5109                 dpll |= DPLL_DVO_2X_MODE;
5110
5111         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5112                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5113                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5114         else
5115                 dpll |= PLL_REF_INPUT_DREFCLK;
5116
5117         dpll |= DPLL_VCO_ENABLE;
5118         crtc->config.dpll_hw_state.dpll = dpll;
5119 }
5120
5121 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5122 {
5123         struct drm_device *dev = intel_crtc->base.dev;
5124         struct drm_i915_private *dev_priv = dev->dev_private;
5125         enum pipe pipe = intel_crtc->pipe;
5126         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5127         struct drm_display_mode *adjusted_mode =
5128                 &intel_crtc->config.adjusted_mode;
5129         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5130
5131         /* We need to be careful not to changed the adjusted mode, for otherwise
5132          * the hw state checker will get angry at the mismatch. */
5133         crtc_vtotal = adjusted_mode->crtc_vtotal;
5134         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5135
5136         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5137                 /* the chip adds 2 halflines automatically */
5138                 crtc_vtotal -= 1;
5139                 crtc_vblank_end -= 1;
5140                 vsyncshift = adjusted_mode->crtc_hsync_start
5141                              - adjusted_mode->crtc_htotal / 2;
5142         } else {
5143                 vsyncshift = 0;
5144         }
5145
5146         if (INTEL_INFO(dev)->gen > 3)
5147                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5148
5149         I915_WRITE(HTOTAL(cpu_transcoder),
5150                    (adjusted_mode->crtc_hdisplay - 1) |
5151                    ((adjusted_mode->crtc_htotal - 1) << 16));
5152         I915_WRITE(HBLANK(cpu_transcoder),
5153                    (adjusted_mode->crtc_hblank_start - 1) |
5154                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5155         I915_WRITE(HSYNC(cpu_transcoder),
5156                    (adjusted_mode->crtc_hsync_start - 1) |
5157                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5158
5159         I915_WRITE(VTOTAL(cpu_transcoder),
5160                    (adjusted_mode->crtc_vdisplay - 1) |
5161                    ((crtc_vtotal - 1) << 16));
5162         I915_WRITE(VBLANK(cpu_transcoder),
5163                    (adjusted_mode->crtc_vblank_start - 1) |
5164                    ((crtc_vblank_end - 1) << 16));
5165         I915_WRITE(VSYNC(cpu_transcoder),
5166                    (adjusted_mode->crtc_vsync_start - 1) |
5167                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5168
5169         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5170          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5171          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5172          * bits. */
5173         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5174             (pipe == PIPE_B || pipe == PIPE_C))
5175                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5176
5177         /* pipesrc controls the size that is scaled from, which should
5178          * always be the user's requested size.
5179          */
5180         I915_WRITE(PIPESRC(pipe),
5181                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5182                    (intel_crtc->config.pipe_src_h - 1));
5183 }
5184
5185 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5186                                    struct intel_crtc_config *pipe_config)
5187 {
5188         struct drm_device *dev = crtc->base.dev;
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5191         uint32_t tmp;
5192
5193         tmp = I915_READ(HTOTAL(cpu_transcoder));
5194         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5195         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5196         tmp = I915_READ(HBLANK(cpu_transcoder));
5197         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5198         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5199         tmp = I915_READ(HSYNC(cpu_transcoder));
5200         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5201         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5202
5203         tmp = I915_READ(VTOTAL(cpu_transcoder));
5204         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5205         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5206         tmp = I915_READ(VBLANK(cpu_transcoder));
5207         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5208         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5209         tmp = I915_READ(VSYNC(cpu_transcoder));
5210         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5211         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5212
5213         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5214                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5215                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5216                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5217         }
5218
5219         tmp = I915_READ(PIPESRC(crtc->pipe));
5220         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5221         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5222
5223         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5224         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5225 }
5226
5227 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5228                                              struct intel_crtc_config *pipe_config)
5229 {
5230         struct drm_crtc *crtc = &intel_crtc->base;
5231
5232         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5233         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5234         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5235         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5236
5237         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5238         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5239         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5240         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5241
5242         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5243
5244         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5245         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5246 }
5247
5248 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5249 {
5250         struct drm_device *dev = intel_crtc->base.dev;
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252         uint32_t pipeconf;
5253
5254         pipeconf = 0;
5255
5256         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5257             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5258                 pipeconf |= PIPECONF_ENABLE;
5259
5260         if (intel_crtc->config.double_wide)
5261                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5262
5263         /* only g4x and later have fancy bpc/dither controls */
5264         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5265                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5266                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5267                         pipeconf |= PIPECONF_DITHER_EN |
5268                                     PIPECONF_DITHER_TYPE_SP;
5269
5270                 switch (intel_crtc->config.pipe_bpp) {
5271                 case 18:
5272                         pipeconf |= PIPECONF_6BPC;
5273                         break;
5274                 case 24:
5275                         pipeconf |= PIPECONF_8BPC;
5276                         break;
5277                 case 30:
5278                         pipeconf |= PIPECONF_10BPC;
5279                         break;
5280                 default:
5281                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5282                         BUG();
5283                 }
5284         }
5285
5286         if (HAS_PIPE_CXSR(dev)) {
5287                 if (intel_crtc->lowfreq_avail) {
5288                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5289                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5290                 } else {
5291                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5292                 }
5293         }
5294
5295         if (!IS_GEN2(dev) &&
5296             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5297                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5298         else
5299                 pipeconf |= PIPECONF_PROGRESSIVE;
5300
5301         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5302                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5303
5304         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5305         POSTING_READ(PIPECONF(intel_crtc->pipe));
5306 }
5307
5308 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5309                               int x, int y,
5310                               struct drm_framebuffer *fb)
5311 {
5312         struct drm_device *dev = crtc->dev;
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5315         int pipe = intel_crtc->pipe;
5316         int plane = intel_crtc->plane;
5317         int refclk, num_connectors = 0;
5318         intel_clock_t clock, reduced_clock;
5319         u32 dspcntr;
5320         bool ok, has_reduced_clock = false;
5321         bool is_lvds = false, is_dsi = false;
5322         struct intel_encoder *encoder;
5323         const intel_limit_t *limit;
5324         int ret;
5325
5326         for_each_encoder_on_crtc(dev, crtc, encoder) {
5327                 switch (encoder->type) {
5328                 case INTEL_OUTPUT_LVDS:
5329                         is_lvds = true;
5330                         break;
5331                 case INTEL_OUTPUT_DSI:
5332                         is_dsi = true;
5333                         break;
5334                 }
5335
5336                 num_connectors++;
5337         }
5338
5339         if (is_dsi)
5340                 goto skip_dpll;
5341
5342         if (!intel_crtc->config.clock_set) {
5343                 refclk = i9xx_get_refclk(crtc, num_connectors);
5344
5345                 /*
5346                  * Returns a set of divisors for the desired target clock with
5347                  * the given refclk, or FALSE.  The returned values represent
5348                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5349                  * 2) / p1 / p2.
5350                  */
5351                 limit = intel_limit(crtc, refclk);
5352                 ok = dev_priv->display.find_dpll(limit, crtc,
5353                                                  intel_crtc->config.port_clock,
5354                                                  refclk, NULL, &clock);
5355                 if (!ok) {
5356                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5357                         return -EINVAL;
5358                 }
5359
5360                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5361                         /*
5362                          * Ensure we match the reduced clock's P to the target
5363                          * clock.  If the clocks don't match, we can't switch
5364                          * the display clock by using the FP0/FP1. In such case
5365                          * we will disable the LVDS downclock feature.
5366                          */
5367                         has_reduced_clock =
5368                                 dev_priv->display.find_dpll(limit, crtc,
5369                                                             dev_priv->lvds_downclock,
5370                                                             refclk, &clock,
5371                                                             &reduced_clock);
5372                 }
5373                 /* Compat-code for transition, will disappear. */
5374                 intel_crtc->config.dpll.n = clock.n;
5375                 intel_crtc->config.dpll.m1 = clock.m1;
5376                 intel_crtc->config.dpll.m2 = clock.m2;
5377                 intel_crtc->config.dpll.p1 = clock.p1;
5378                 intel_crtc->config.dpll.p2 = clock.p2;
5379         }
5380
5381         if (IS_GEN2(dev)) {
5382                 i8xx_update_pll(intel_crtc,
5383                                 has_reduced_clock ? &reduced_clock : NULL,
5384                                 num_connectors);
5385         } else if (IS_VALLEYVIEW(dev)) {
5386                 vlv_update_pll(intel_crtc);
5387         } else {
5388                 i9xx_update_pll(intel_crtc,
5389                                 has_reduced_clock ? &reduced_clock : NULL,
5390                                 num_connectors);
5391         }
5392
5393 skip_dpll:
5394         /* Set up the display plane register */
5395         dspcntr = DISPPLANE_GAMMA_ENABLE;
5396
5397         if (!IS_VALLEYVIEW(dev)) {
5398                 if (pipe == 0)
5399                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5400                 else
5401                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5402         }
5403
5404         intel_set_pipe_timings(intel_crtc);
5405
5406         /* pipesrc and dspsize control the size that is scaled from,
5407          * which should always be the user's requested size.
5408          */
5409         I915_WRITE(DSPSIZE(plane),
5410                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5411                    (intel_crtc->config.pipe_src_w - 1));
5412         I915_WRITE(DSPPOS(plane), 0);
5413
5414         i9xx_set_pipeconf(intel_crtc);
5415
5416         I915_WRITE(DSPCNTR(plane), dspcntr);
5417         POSTING_READ(DSPCNTR(plane));
5418
5419         ret = intel_pipe_set_base(crtc, x, y, fb);
5420
5421         return ret;
5422 }
5423
5424 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5425                                  struct intel_crtc_config *pipe_config)
5426 {
5427         struct drm_device *dev = crtc->base.dev;
5428         struct drm_i915_private *dev_priv = dev->dev_private;
5429         uint32_t tmp;
5430
5431         tmp = I915_READ(PFIT_CONTROL);
5432         if (!(tmp & PFIT_ENABLE))
5433                 return;
5434
5435         /* Check whether the pfit is attached to our pipe. */
5436         if (INTEL_INFO(dev)->gen < 4) {
5437                 if (crtc->pipe != PIPE_B)
5438                         return;
5439         } else {
5440                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5441                         return;
5442         }
5443
5444         pipe_config->gmch_pfit.control = tmp;
5445         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5446         if (INTEL_INFO(dev)->gen < 5)
5447                 pipe_config->gmch_pfit.lvds_border_bits =
5448                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5449 }
5450
5451 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5452                                struct intel_crtc_config *pipe_config)
5453 {
5454         struct drm_device *dev = crtc->base.dev;
5455         struct drm_i915_private *dev_priv = dev->dev_private;
5456         int pipe = pipe_config->cpu_transcoder;
5457         intel_clock_t clock;
5458         u32 mdiv;
5459         int refclk = 100000;
5460
5461         mutex_lock(&dev_priv->dpio_lock);
5462         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5463         mutex_unlock(&dev_priv->dpio_lock);
5464
5465         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5466         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5467         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5468         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5469         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5470
5471         vlv_clock(refclk, &clock);
5472
5473         /* clock.dot is the fast clock */
5474         pipe_config->port_clock = clock.dot / 5;
5475 }
5476
5477 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5478                                  struct intel_crtc_config *pipe_config)
5479 {
5480         struct drm_device *dev = crtc->base.dev;
5481         struct drm_i915_private *dev_priv = dev->dev_private;
5482         uint32_t tmp;
5483
5484         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5485         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5486
5487         tmp = I915_READ(PIPECONF(crtc->pipe));
5488         if (!(tmp & PIPECONF_ENABLE))
5489                 return false;
5490
5491         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5492                 switch (tmp & PIPECONF_BPC_MASK) {
5493                 case PIPECONF_6BPC:
5494                         pipe_config->pipe_bpp = 18;
5495                         break;
5496                 case PIPECONF_8BPC:
5497                         pipe_config->pipe_bpp = 24;
5498                         break;
5499                 case PIPECONF_10BPC:
5500                         pipe_config->pipe_bpp = 30;
5501                         break;
5502                 default:
5503                         break;
5504                 }
5505         }
5506
5507         if (INTEL_INFO(dev)->gen < 4)
5508                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5509
5510         intel_get_pipe_timings(crtc, pipe_config);
5511
5512         i9xx_get_pfit_config(crtc, pipe_config);
5513
5514         if (INTEL_INFO(dev)->gen >= 4) {
5515                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5516                 pipe_config->pixel_multiplier =
5517                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5518                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5519                 pipe_config->dpll_hw_state.dpll_md = tmp;
5520         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5521                 tmp = I915_READ(DPLL(crtc->pipe));
5522                 pipe_config->pixel_multiplier =
5523                         ((tmp & SDVO_MULTIPLIER_MASK)
5524                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5525         } else {
5526                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5527                  * port and will be fixed up in the encoder->get_config
5528                  * function. */
5529                 pipe_config->pixel_multiplier = 1;
5530         }
5531         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5532         if (!IS_VALLEYVIEW(dev)) {
5533                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5534                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5535         } else {
5536                 /* Mask out read-only status bits. */
5537                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5538                                                      DPLL_PORTC_READY_MASK |
5539                                                      DPLL_PORTB_READY_MASK);
5540         }
5541
5542         if (IS_VALLEYVIEW(dev))
5543                 vlv_crtc_clock_get(crtc, pipe_config);
5544         else
5545                 i9xx_crtc_clock_get(crtc, pipe_config);
5546
5547         return true;
5548 }
5549
5550 static void ironlake_init_pch_refclk(struct drm_device *dev)
5551 {
5552         struct drm_i915_private *dev_priv = dev->dev_private;
5553         struct drm_mode_config *mode_config = &dev->mode_config;
5554         struct intel_encoder *encoder;
5555         u32 val, final;
5556         bool has_lvds = false;
5557         bool has_cpu_edp = false;
5558         bool has_panel = false;
5559         bool has_ck505 = false;
5560         bool can_ssc = false;
5561
5562         /* We need to take the global config into account */
5563         list_for_each_entry(encoder, &mode_config->encoder_list,
5564                             base.head) {
5565                 switch (encoder->type) {
5566                 case INTEL_OUTPUT_LVDS:
5567                         has_panel = true;
5568                         has_lvds = true;
5569                         break;
5570                 case INTEL_OUTPUT_EDP:
5571                         has_panel = true;
5572                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5573                                 has_cpu_edp = true;
5574                         break;
5575                 }
5576         }
5577
5578         if (HAS_PCH_IBX(dev)) {
5579                 has_ck505 = dev_priv->vbt.display_clock_mode;
5580                 can_ssc = has_ck505;
5581         } else {
5582                 has_ck505 = false;
5583                 can_ssc = true;
5584         }
5585
5586         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5587                       has_panel, has_lvds, has_ck505);
5588
5589         /* Ironlake: try to setup display ref clock before DPLL
5590          * enabling. This is only under driver's control after
5591          * PCH B stepping, previous chipset stepping should be
5592          * ignoring this setting.
5593          */
5594         val = I915_READ(PCH_DREF_CONTROL);
5595
5596         /* As we must carefully and slowly disable/enable each source in turn,
5597          * compute the final state we want first and check if we need to
5598          * make any changes at all.
5599          */
5600         final = val;
5601         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5602         if (has_ck505)
5603                 final |= DREF_NONSPREAD_CK505_ENABLE;
5604         else
5605                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5606
5607         final &= ~DREF_SSC_SOURCE_MASK;
5608         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5609         final &= ~DREF_SSC1_ENABLE;
5610
5611         if (has_panel) {
5612                 final |= DREF_SSC_SOURCE_ENABLE;
5613
5614                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5615                         final |= DREF_SSC1_ENABLE;
5616
5617                 if (has_cpu_edp) {
5618                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5619                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5620                         else
5621                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5622                 } else
5623                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5624         } else {
5625                 final |= DREF_SSC_SOURCE_DISABLE;
5626                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5627         }
5628
5629         if (final == val)
5630                 return;
5631
5632         /* Always enable nonspread source */
5633         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5634
5635         if (has_ck505)
5636                 val |= DREF_NONSPREAD_CK505_ENABLE;
5637         else
5638                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5639
5640         if (has_panel) {
5641                 val &= ~DREF_SSC_SOURCE_MASK;
5642                 val |= DREF_SSC_SOURCE_ENABLE;
5643
5644                 /* SSC must be turned on before enabling the CPU output  */
5645                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5646                         DRM_DEBUG_KMS("Using SSC on panel\n");
5647                         val |= DREF_SSC1_ENABLE;
5648                 } else
5649                         val &= ~DREF_SSC1_ENABLE;
5650
5651                 /* Get SSC going before enabling the outputs */
5652                 I915_WRITE(PCH_DREF_CONTROL, val);
5653                 POSTING_READ(PCH_DREF_CONTROL);
5654                 udelay(200);
5655
5656                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5657
5658                 /* Enable CPU source on CPU attached eDP */
5659                 if (has_cpu_edp) {
5660                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5661                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5662                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5663                         }
5664                         else
5665                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5666                 } else
5667                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5668
5669                 I915_WRITE(PCH_DREF_CONTROL, val);
5670                 POSTING_READ(PCH_DREF_CONTROL);
5671                 udelay(200);
5672         } else {
5673                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5674
5675                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5676
5677                 /* Turn off CPU output */
5678                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5679
5680                 I915_WRITE(PCH_DREF_CONTROL, val);
5681                 POSTING_READ(PCH_DREF_CONTROL);
5682                 udelay(200);
5683
5684                 /* Turn off the SSC source */
5685                 val &= ~DREF_SSC_SOURCE_MASK;
5686                 val |= DREF_SSC_SOURCE_DISABLE;
5687
5688                 /* Turn off SSC1 */
5689                 val &= ~DREF_SSC1_ENABLE;
5690
5691                 I915_WRITE(PCH_DREF_CONTROL, val);
5692                 POSTING_READ(PCH_DREF_CONTROL);
5693                 udelay(200);
5694         }
5695
5696         BUG_ON(val != final);
5697 }
5698
5699 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5700 {
5701         uint32_t tmp;
5702
5703         tmp = I915_READ(SOUTH_CHICKEN2);
5704         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5705         I915_WRITE(SOUTH_CHICKEN2, tmp);
5706
5707         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5708                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5709                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5710
5711         tmp = I915_READ(SOUTH_CHICKEN2);
5712         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5713         I915_WRITE(SOUTH_CHICKEN2, tmp);
5714
5715         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5716                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5717                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5718 }
5719
5720 /* WaMPhyProgramming:hsw */
5721 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5722 {
5723         uint32_t tmp;
5724
5725         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5726         tmp &= ~(0xFF << 24);
5727         tmp |= (0x12 << 24);
5728         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5729
5730         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5731         tmp |= (1 << 11);
5732         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5733
5734         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5735         tmp |= (1 << 11);
5736         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5737
5738         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5739         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5740         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5741
5742         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5743         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5744         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5745
5746         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5747         tmp &= ~(7 << 13);
5748         tmp |= (5 << 13);
5749         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5750
5751         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5752         tmp &= ~(7 << 13);
5753         tmp |= (5 << 13);
5754         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5755
5756         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5757         tmp &= ~0xFF;
5758         tmp |= 0x1C;
5759         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5760
5761         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5762         tmp &= ~0xFF;
5763         tmp |= 0x1C;
5764         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5765
5766         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5767         tmp &= ~(0xFF << 16);
5768         tmp |= (0x1C << 16);
5769         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5770
5771         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5772         tmp &= ~(0xFF << 16);
5773         tmp |= (0x1C << 16);
5774         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5775
5776         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5777         tmp |= (1 << 27);
5778         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5779
5780         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5781         tmp |= (1 << 27);
5782         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5783
5784         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5785         tmp &= ~(0xF << 28);
5786         tmp |= (4 << 28);
5787         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5788
5789         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5790         tmp &= ~(0xF << 28);
5791         tmp |= (4 << 28);
5792         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5793 }
5794
5795 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5796  * Programming" based on the parameters passed:
5797  * - Sequence to enable CLKOUT_DP
5798  * - Sequence to enable CLKOUT_DP without spread
5799  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5800  */
5801 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5802                                  bool with_fdi)
5803 {
5804         struct drm_i915_private *dev_priv = dev->dev_private;
5805         uint32_t reg, tmp;
5806
5807         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5808                 with_spread = true;
5809         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5810                  with_fdi, "LP PCH doesn't have FDI\n"))
5811                 with_fdi = false;
5812
5813         mutex_lock(&dev_priv->dpio_lock);
5814
5815         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5816         tmp &= ~SBI_SSCCTL_DISABLE;
5817         tmp |= SBI_SSCCTL_PATHALT;
5818         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5819
5820         udelay(24);
5821
5822         if (with_spread) {
5823                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5824                 tmp &= ~SBI_SSCCTL_PATHALT;
5825                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5826
5827                 if (with_fdi) {
5828                         lpt_reset_fdi_mphy(dev_priv);
5829                         lpt_program_fdi_mphy(dev_priv);
5830                 }
5831         }
5832
5833         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5834                SBI_GEN0 : SBI_DBUFF0;
5835         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5836         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5837         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5838
5839         mutex_unlock(&dev_priv->dpio_lock);
5840 }
5841
5842 /* Sequence to disable CLKOUT_DP */
5843 static void lpt_disable_clkout_dp(struct drm_device *dev)
5844 {
5845         struct drm_i915_private *dev_priv = dev->dev_private;
5846         uint32_t reg, tmp;
5847
5848         mutex_lock(&dev_priv->dpio_lock);
5849
5850         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5851                SBI_GEN0 : SBI_DBUFF0;
5852         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5853         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5854         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5855
5856         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5857         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5858                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5859                         tmp |= SBI_SSCCTL_PATHALT;
5860                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5861                         udelay(32);
5862                 }
5863                 tmp |= SBI_SSCCTL_DISABLE;
5864                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5865         }
5866
5867         mutex_unlock(&dev_priv->dpio_lock);
5868 }
5869
5870 static void lpt_init_pch_refclk(struct drm_device *dev)
5871 {
5872         struct drm_mode_config *mode_config = &dev->mode_config;
5873         struct intel_encoder *encoder;
5874         bool has_vga = false;
5875
5876         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5877                 switch (encoder->type) {
5878                 case INTEL_OUTPUT_ANALOG:
5879                         has_vga = true;
5880                         break;
5881                 }
5882         }
5883
5884         if (has_vga)
5885                 lpt_enable_clkout_dp(dev, true, true);
5886         else
5887                 lpt_disable_clkout_dp(dev);
5888 }
5889
5890 /*
5891  * Initialize reference clocks when the driver loads
5892  */
5893 void intel_init_pch_refclk(struct drm_device *dev)
5894 {
5895         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5896                 ironlake_init_pch_refclk(dev);
5897         else if (HAS_PCH_LPT(dev))
5898                 lpt_init_pch_refclk(dev);
5899 }
5900
5901 static int ironlake_get_refclk(struct drm_crtc *crtc)
5902 {
5903         struct drm_device *dev = crtc->dev;
5904         struct drm_i915_private *dev_priv = dev->dev_private;
5905         struct intel_encoder *encoder;
5906         int num_connectors = 0;
5907         bool is_lvds = false;
5908
5909         for_each_encoder_on_crtc(dev, crtc, encoder) {
5910                 switch (encoder->type) {
5911                 case INTEL_OUTPUT_LVDS:
5912                         is_lvds = true;
5913                         break;
5914                 }
5915                 num_connectors++;
5916         }
5917
5918         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5919                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5920                               dev_priv->vbt.lvds_ssc_freq);
5921                 return dev_priv->vbt.lvds_ssc_freq;
5922         }
5923
5924         return 120000;
5925 }
5926
5927 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5928 {
5929         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5931         int pipe = intel_crtc->pipe;
5932         uint32_t val;
5933
5934         val = 0;
5935
5936         switch (intel_crtc->config.pipe_bpp) {
5937         case 18:
5938                 val |= PIPECONF_6BPC;
5939                 break;
5940         case 24:
5941                 val |= PIPECONF_8BPC;
5942                 break;
5943         case 30:
5944                 val |= PIPECONF_10BPC;
5945                 break;
5946         case 36:
5947                 val |= PIPECONF_12BPC;
5948                 break;
5949         default:
5950                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5951                 BUG();
5952         }
5953
5954         if (intel_crtc->config.dither)
5955                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5956
5957         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5958                 val |= PIPECONF_INTERLACED_ILK;
5959         else
5960                 val |= PIPECONF_PROGRESSIVE;
5961
5962         if (intel_crtc->config.limited_color_range)
5963                 val |= PIPECONF_COLOR_RANGE_SELECT;
5964
5965         I915_WRITE(PIPECONF(pipe), val);
5966         POSTING_READ(PIPECONF(pipe));
5967 }
5968
5969 /*
5970  * Set up the pipe CSC unit.
5971  *
5972  * Currently only full range RGB to limited range RGB conversion
5973  * is supported, but eventually this should handle various
5974  * RGB<->YCbCr scenarios as well.
5975  */
5976 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5977 {
5978         struct drm_device *dev = crtc->dev;
5979         struct drm_i915_private *dev_priv = dev->dev_private;
5980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5981         int pipe = intel_crtc->pipe;
5982         uint16_t coeff = 0x7800; /* 1.0 */
5983
5984         /*
5985          * TODO: Check what kind of values actually come out of the pipe
5986          * with these coeff/postoff values and adjust to get the best
5987          * accuracy. Perhaps we even need to take the bpc value into
5988          * consideration.
5989          */
5990
5991         if (intel_crtc->config.limited_color_range)
5992                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5993
5994         /*
5995          * GY/GU and RY/RU should be the other way around according
5996          * to BSpec, but reality doesn't agree. Just set them up in
5997          * a way that results in the correct picture.
5998          */
5999         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6000         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6001
6002         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6003         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6004
6005         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6006         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6007
6008         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6009         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6010         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6011
6012         if (INTEL_INFO(dev)->gen > 6) {
6013                 uint16_t postoff = 0;
6014
6015                 if (intel_crtc->config.limited_color_range)
6016                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
6017
6018                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6019                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6020                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6021
6022                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6023         } else {
6024                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6025
6026                 if (intel_crtc->config.limited_color_range)
6027                         mode |= CSC_BLACK_SCREEN_OFFSET;
6028
6029                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6030         }
6031 }
6032
6033 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6034 {
6035         struct drm_device *dev = crtc->dev;
6036         struct drm_i915_private *dev_priv = dev->dev_private;
6037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6038         enum pipe pipe = intel_crtc->pipe;
6039         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6040         uint32_t val;
6041
6042         val = 0;
6043
6044         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6045                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6046
6047         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6048                 val |= PIPECONF_INTERLACED_ILK;
6049         else
6050                 val |= PIPECONF_PROGRESSIVE;
6051
6052         I915_WRITE(PIPECONF(cpu_transcoder), val);
6053         POSTING_READ(PIPECONF(cpu_transcoder));
6054
6055         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6056         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6057
6058         if (IS_BROADWELL(dev)) {
6059                 val = 0;
6060
6061                 switch (intel_crtc->config.pipe_bpp) {
6062                 case 18:
6063                         val |= PIPEMISC_DITHER_6_BPC;
6064                         break;
6065                 case 24:
6066                         val |= PIPEMISC_DITHER_8_BPC;
6067                         break;
6068                 case 30:
6069                         val |= PIPEMISC_DITHER_10_BPC;
6070                         break;
6071                 case 36:
6072                         val |= PIPEMISC_DITHER_12_BPC;
6073                         break;
6074                 default:
6075                         /* Case prevented by pipe_config_set_bpp. */
6076                         BUG();
6077                 }
6078
6079                 if (intel_crtc->config.dither)
6080                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6081
6082                 I915_WRITE(PIPEMISC(pipe), val);
6083         }
6084 }
6085
6086 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6087                                     intel_clock_t *clock,
6088                                     bool *has_reduced_clock,
6089                                     intel_clock_t *reduced_clock)
6090 {
6091         struct drm_device *dev = crtc->dev;
6092         struct drm_i915_private *dev_priv = dev->dev_private;
6093         struct intel_encoder *intel_encoder;
6094         int refclk;
6095         const intel_limit_t *limit;
6096         bool ret, is_lvds = false;
6097
6098         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6099                 switch (intel_encoder->type) {
6100                 case INTEL_OUTPUT_LVDS:
6101                         is_lvds = true;
6102                         break;
6103                 }
6104         }
6105
6106         refclk = ironlake_get_refclk(crtc);
6107
6108         /*
6109          * Returns a set of divisors for the desired target clock with the given
6110          * refclk, or FALSE.  The returned values represent the clock equation:
6111          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6112          */
6113         limit = intel_limit(crtc, refclk);
6114         ret = dev_priv->display.find_dpll(limit, crtc,
6115                                           to_intel_crtc(crtc)->config.port_clock,
6116                                           refclk, NULL, clock);
6117         if (!ret)
6118                 return false;
6119
6120         if (is_lvds && dev_priv->lvds_downclock_avail) {
6121                 /*
6122                  * Ensure we match the reduced clock's P to the target clock.
6123                  * If the clocks don't match, we can't switch the display clock
6124                  * by using the FP0/FP1. In such case we will disable the LVDS
6125                  * downclock feature.
6126                 */
6127                 *has_reduced_clock =
6128                         dev_priv->display.find_dpll(limit, crtc,
6129                                                     dev_priv->lvds_downclock,
6130                                                     refclk, clock,
6131                                                     reduced_clock);
6132         }
6133
6134         return true;
6135 }
6136
6137 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6138 {
6139         /*
6140          * Account for spread spectrum to avoid
6141          * oversubscribing the link. Max center spread
6142          * is 2.5%; use 5% for safety's sake.
6143          */
6144         u32 bps = target_clock * bpp * 21 / 20;
6145         return bps / (link_bw * 8) + 1;
6146 }
6147
6148 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6149 {
6150         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6151 }
6152
6153 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6154                                       u32 *fp,
6155                                       intel_clock_t *reduced_clock, u32 *fp2)
6156 {
6157         struct drm_crtc *crtc = &intel_crtc->base;
6158         struct drm_device *dev = crtc->dev;
6159         struct drm_i915_private *dev_priv = dev->dev_private;
6160         struct intel_encoder *intel_encoder;
6161         uint32_t dpll;
6162         int factor, num_connectors = 0;
6163         bool is_lvds = false, is_sdvo = false;
6164
6165         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6166                 switch (intel_encoder->type) {
6167                 case INTEL_OUTPUT_LVDS:
6168                         is_lvds = true;
6169                         break;
6170                 case INTEL_OUTPUT_SDVO:
6171                 case INTEL_OUTPUT_HDMI:
6172                         is_sdvo = true;
6173                         break;
6174                 }
6175
6176                 num_connectors++;
6177         }
6178
6179         /* Enable autotuning of the PLL clock (if permissible) */
6180         factor = 21;
6181         if (is_lvds) {
6182                 if ((intel_panel_use_ssc(dev_priv) &&
6183                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6184                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6185                         factor = 25;
6186         } else if (intel_crtc->config.sdvo_tv_clock)
6187                 factor = 20;
6188
6189         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6190                 *fp |= FP_CB_TUNE;
6191
6192         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6193                 *fp2 |= FP_CB_TUNE;
6194
6195         dpll = 0;
6196
6197         if (is_lvds)
6198                 dpll |= DPLLB_MODE_LVDS;
6199         else
6200                 dpll |= DPLLB_MODE_DAC_SERIAL;
6201
6202         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6203                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6204
6205         if (is_sdvo)
6206                 dpll |= DPLL_SDVO_HIGH_SPEED;
6207         if (intel_crtc->config.has_dp_encoder)
6208                 dpll |= DPLL_SDVO_HIGH_SPEED;
6209
6210         /* compute bitmask from p1 value */
6211         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6212         /* also FPA1 */
6213         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6214
6215         switch (intel_crtc->config.dpll.p2) {
6216         case 5:
6217                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6218                 break;
6219         case 7:
6220                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6221                 break;
6222         case 10:
6223                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6224                 break;
6225         case 14:
6226                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6227                 break;
6228         }
6229
6230         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6231                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6232         else
6233                 dpll |= PLL_REF_INPUT_DREFCLK;
6234
6235         return dpll | DPLL_VCO_ENABLE;
6236 }
6237
6238 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6239                                   int x, int y,
6240                                   struct drm_framebuffer *fb)
6241 {
6242         struct drm_device *dev = crtc->dev;
6243         struct drm_i915_private *dev_priv = dev->dev_private;
6244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6245         int pipe = intel_crtc->pipe;
6246         int plane = intel_crtc->plane;
6247         int num_connectors = 0;
6248         intel_clock_t clock, reduced_clock;
6249         u32 dpll = 0, fp = 0, fp2 = 0;
6250         bool ok, has_reduced_clock = false;
6251         bool is_lvds = false;
6252         struct intel_encoder *encoder;
6253         struct intel_shared_dpll *pll;
6254         int ret;
6255
6256         for_each_encoder_on_crtc(dev, crtc, encoder) {
6257                 switch (encoder->type) {
6258                 case INTEL_OUTPUT_LVDS:
6259                         is_lvds = true;
6260                         break;
6261                 }
6262
6263                 num_connectors++;
6264         }
6265
6266         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6267              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6268
6269         ok = ironlake_compute_clocks(crtc, &clock,
6270                                      &has_reduced_clock, &reduced_clock);
6271         if (!ok && !intel_crtc->config.clock_set) {
6272                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6273                 return -EINVAL;
6274         }
6275         /* Compat-code for transition, will disappear. */
6276         if (!intel_crtc->config.clock_set) {
6277                 intel_crtc->config.dpll.n = clock.n;
6278                 intel_crtc->config.dpll.m1 = clock.m1;
6279                 intel_crtc->config.dpll.m2 = clock.m2;
6280                 intel_crtc->config.dpll.p1 = clock.p1;
6281                 intel_crtc->config.dpll.p2 = clock.p2;
6282         }
6283
6284         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6285         if (intel_crtc->config.has_pch_encoder) {
6286                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6287                 if (has_reduced_clock)
6288                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6289
6290                 dpll = ironlake_compute_dpll(intel_crtc,
6291                                              &fp, &reduced_clock,
6292                                              has_reduced_clock ? &fp2 : NULL);
6293
6294                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6295                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6296                 if (has_reduced_clock)
6297                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6298                 else
6299                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6300
6301                 pll = intel_get_shared_dpll(intel_crtc);
6302                 if (pll == NULL) {
6303                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6304                                          pipe_name(pipe));
6305                         return -EINVAL;
6306                 }
6307         } else
6308                 intel_put_shared_dpll(intel_crtc);
6309
6310         if (intel_crtc->config.has_dp_encoder)
6311                 intel_dp_set_m_n(intel_crtc);
6312
6313         if (is_lvds && has_reduced_clock && i915_powersave)
6314                 intel_crtc->lowfreq_avail = true;
6315         else
6316                 intel_crtc->lowfreq_avail = false;
6317
6318         intel_set_pipe_timings(intel_crtc);
6319
6320         if (intel_crtc->config.has_pch_encoder) {
6321                 intel_cpu_transcoder_set_m_n(intel_crtc,
6322                                              &intel_crtc->config.fdi_m_n);
6323         }
6324
6325         ironlake_set_pipeconf(crtc);
6326
6327         /* Set up the display plane register */
6328         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6329         POSTING_READ(DSPCNTR(plane));
6330
6331         ret = intel_pipe_set_base(crtc, x, y, fb);
6332
6333         return ret;
6334 }
6335
6336 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6337                                          struct intel_link_m_n *m_n)
6338 {
6339         struct drm_device *dev = crtc->base.dev;
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341         enum pipe pipe = crtc->pipe;
6342
6343         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6344         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6345         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6346                 & ~TU_SIZE_MASK;
6347         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6348         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6349                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6350 }
6351
6352 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6353                                          enum transcoder transcoder,
6354                                          struct intel_link_m_n *m_n)
6355 {
6356         struct drm_device *dev = crtc->base.dev;
6357         struct drm_i915_private *dev_priv = dev->dev_private;
6358         enum pipe pipe = crtc->pipe;
6359
6360         if (INTEL_INFO(dev)->gen >= 5) {
6361                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6362                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6363                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6364                         & ~TU_SIZE_MASK;
6365                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6366                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6367                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6368         } else {
6369                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6370                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6371                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6372                         & ~TU_SIZE_MASK;
6373                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6374                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6375                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6376         }
6377 }
6378
6379 void intel_dp_get_m_n(struct intel_crtc *crtc,
6380                       struct intel_crtc_config *pipe_config)
6381 {
6382         if (crtc->config.has_pch_encoder)
6383                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6384         else
6385                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6386                                              &pipe_config->dp_m_n);
6387 }
6388
6389 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6390                                         struct intel_crtc_config *pipe_config)
6391 {
6392         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6393                                      &pipe_config->fdi_m_n);
6394 }
6395
6396 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6397                                      struct intel_crtc_config *pipe_config)
6398 {
6399         struct drm_device *dev = crtc->base.dev;
6400         struct drm_i915_private *dev_priv = dev->dev_private;
6401         uint32_t tmp;
6402
6403         tmp = I915_READ(PF_CTL(crtc->pipe));
6404
6405         if (tmp & PF_ENABLE) {
6406                 pipe_config->pch_pfit.enabled = true;
6407                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6408                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6409
6410                 /* We currently do not free assignements of panel fitters on
6411                  * ivb/hsw (since we don't use the higher upscaling modes which
6412                  * differentiates them) so just WARN about this case for now. */
6413                 if (IS_GEN7(dev)) {
6414                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6415                                 PF_PIPE_SEL_IVB(crtc->pipe));
6416                 }
6417         }
6418 }
6419
6420 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6421                                      struct intel_crtc_config *pipe_config)
6422 {
6423         struct drm_device *dev = crtc->base.dev;
6424         struct drm_i915_private *dev_priv = dev->dev_private;
6425         uint32_t tmp;
6426
6427         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6428         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6429
6430         tmp = I915_READ(PIPECONF(crtc->pipe));
6431         if (!(tmp & PIPECONF_ENABLE))
6432                 return false;
6433
6434         switch (tmp & PIPECONF_BPC_MASK) {
6435         case PIPECONF_6BPC:
6436                 pipe_config->pipe_bpp = 18;
6437                 break;
6438         case PIPECONF_8BPC:
6439                 pipe_config->pipe_bpp = 24;
6440                 break;
6441         case PIPECONF_10BPC:
6442                 pipe_config->pipe_bpp = 30;
6443                 break;
6444         case PIPECONF_12BPC:
6445                 pipe_config->pipe_bpp = 36;
6446                 break;
6447         default:
6448                 break;
6449         }
6450
6451         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6452                 struct intel_shared_dpll *pll;
6453
6454                 pipe_config->has_pch_encoder = true;
6455
6456                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6457                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6458                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6459
6460                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6461
6462                 if (HAS_PCH_IBX(dev_priv->dev)) {
6463                         pipe_config->shared_dpll =
6464                                 (enum intel_dpll_id) crtc->pipe;
6465                 } else {
6466                         tmp = I915_READ(PCH_DPLL_SEL);
6467                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6468                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6469                         else
6470                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6471                 }
6472
6473                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6474
6475                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6476                                            &pipe_config->dpll_hw_state));
6477
6478                 tmp = pipe_config->dpll_hw_state.dpll;
6479                 pipe_config->pixel_multiplier =
6480                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6481                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6482
6483                 ironlake_pch_clock_get(crtc, pipe_config);
6484         } else {
6485                 pipe_config->pixel_multiplier = 1;
6486         }
6487
6488         intel_get_pipe_timings(crtc, pipe_config);
6489
6490         ironlake_get_pfit_config(crtc, pipe_config);
6491
6492         return true;
6493 }
6494
6495 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6496 {
6497         struct drm_device *dev = dev_priv->dev;
6498         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6499         struct intel_crtc *crtc;
6500         unsigned long irqflags;
6501         uint32_t val;
6502
6503         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6504                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6505                      pipe_name(crtc->pipe));
6506
6507         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6508         WARN(plls->spll_refcount, "SPLL enabled\n");
6509         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6510         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6511         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6512         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6513              "CPU PWM1 enabled\n");
6514         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6515              "CPU PWM2 enabled\n");
6516         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6517              "PCH PWM1 enabled\n");
6518         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6519              "Utility pin enabled\n");
6520         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6521
6522         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6523         val = I915_READ(DEIMR);
6524         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6525              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6526         val = I915_READ(SDEIMR);
6527         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6528              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6529         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6530 }
6531
6532 /*
6533  * This function implements pieces of two sequences from BSpec:
6534  * - Sequence for display software to disable LCPLL
6535  * - Sequence for display software to allow package C8+
6536  * The steps implemented here are just the steps that actually touch the LCPLL
6537  * register. Callers should take care of disabling all the display engine
6538  * functions, doing the mode unset, fixing interrupts, etc.
6539  */
6540 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6541                               bool switch_to_fclk, bool allow_power_down)
6542 {
6543         uint32_t val;
6544
6545         assert_can_disable_lcpll(dev_priv);
6546
6547         val = I915_READ(LCPLL_CTL);
6548
6549         if (switch_to_fclk) {
6550                 val |= LCPLL_CD_SOURCE_FCLK;
6551                 I915_WRITE(LCPLL_CTL, val);
6552
6553                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6554                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6555                         DRM_ERROR("Switching to FCLK failed\n");
6556
6557                 val = I915_READ(LCPLL_CTL);
6558         }
6559
6560         val |= LCPLL_PLL_DISABLE;
6561         I915_WRITE(LCPLL_CTL, val);
6562         POSTING_READ(LCPLL_CTL);
6563
6564         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6565                 DRM_ERROR("LCPLL still locked\n");
6566
6567         val = I915_READ(D_COMP);
6568         val |= D_COMP_COMP_DISABLE;
6569         mutex_lock(&dev_priv->rps.hw_lock);
6570         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6571                 DRM_ERROR("Failed to disable D_COMP\n");
6572         mutex_unlock(&dev_priv->rps.hw_lock);
6573         POSTING_READ(D_COMP);
6574         ndelay(100);
6575
6576         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6577                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6578
6579         if (allow_power_down) {
6580                 val = I915_READ(LCPLL_CTL);
6581                 val |= LCPLL_POWER_DOWN_ALLOW;
6582                 I915_WRITE(LCPLL_CTL, val);
6583                 POSTING_READ(LCPLL_CTL);
6584         }
6585 }
6586
6587 /*
6588  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6589  * source.
6590  */
6591 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6592 {
6593         uint32_t val;
6594
6595         val = I915_READ(LCPLL_CTL);
6596
6597         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6598                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6599                 return;
6600
6601         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6602          * we'll hang the machine! */
6603         dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6604
6605         if (val & LCPLL_POWER_DOWN_ALLOW) {
6606                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6607                 I915_WRITE(LCPLL_CTL, val);
6608                 POSTING_READ(LCPLL_CTL);
6609         }
6610
6611         val = I915_READ(D_COMP);
6612         val |= D_COMP_COMP_FORCE;
6613         val &= ~D_COMP_COMP_DISABLE;
6614         mutex_lock(&dev_priv->rps.hw_lock);
6615         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6616                 DRM_ERROR("Failed to enable D_COMP\n");
6617         mutex_unlock(&dev_priv->rps.hw_lock);
6618         POSTING_READ(D_COMP);
6619
6620         val = I915_READ(LCPLL_CTL);
6621         val &= ~LCPLL_PLL_DISABLE;
6622         I915_WRITE(LCPLL_CTL, val);
6623
6624         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6625                 DRM_ERROR("LCPLL not locked yet\n");
6626
6627         if (val & LCPLL_CD_SOURCE_FCLK) {
6628                 val = I915_READ(LCPLL_CTL);
6629                 val &= ~LCPLL_CD_SOURCE_FCLK;
6630                 I915_WRITE(LCPLL_CTL, val);
6631
6632                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6633                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6634                         DRM_ERROR("Switching back to LCPLL failed\n");
6635         }
6636
6637         dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6638 }
6639
6640 void hsw_enable_pc8_work(struct work_struct *__work)
6641 {
6642         struct drm_i915_private *dev_priv =
6643                 container_of(to_delayed_work(__work), struct drm_i915_private,
6644                              pc8.enable_work);
6645         struct drm_device *dev = dev_priv->dev;
6646         uint32_t val;
6647
6648         WARN_ON(!HAS_PC8(dev));
6649
6650         if (dev_priv->pc8.enabled)
6651                 return;
6652
6653         DRM_DEBUG_KMS("Enabling package C8+\n");
6654
6655         dev_priv->pc8.enabled = true;
6656
6657         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6658                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6659                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6660                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6661         }
6662
6663         lpt_disable_clkout_dp(dev);
6664         hsw_pc8_disable_interrupts(dev);
6665         hsw_disable_lcpll(dev_priv, true, true);
6666
6667         intel_runtime_pm_put(dev_priv);
6668 }
6669
6670 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6671 {
6672         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6673         WARN(dev_priv->pc8.disable_count < 1,
6674              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6675
6676         dev_priv->pc8.disable_count--;
6677         if (dev_priv->pc8.disable_count != 0)
6678                 return;
6679
6680         schedule_delayed_work(&dev_priv->pc8.enable_work,
6681                               msecs_to_jiffies(i915_pc8_timeout));
6682 }
6683
6684 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6685 {
6686         struct drm_device *dev = dev_priv->dev;
6687         uint32_t val;
6688
6689         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6690         WARN(dev_priv->pc8.disable_count < 0,
6691              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6692
6693         dev_priv->pc8.disable_count++;
6694         if (dev_priv->pc8.disable_count != 1)
6695                 return;
6696
6697         WARN_ON(!HAS_PC8(dev));
6698
6699         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6700         if (!dev_priv->pc8.enabled)
6701                 return;
6702
6703         DRM_DEBUG_KMS("Disabling package C8+\n");
6704
6705         intel_runtime_pm_get(dev_priv);
6706
6707         hsw_restore_lcpll(dev_priv);
6708         hsw_pc8_restore_interrupts(dev);
6709         lpt_init_pch_refclk(dev);
6710
6711         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6712                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6713                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6714                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6715         }
6716
6717         intel_prepare_ddi(dev);
6718         i915_gem_init_swizzling(dev);
6719         mutex_lock(&dev_priv->rps.hw_lock);
6720         gen6_update_ring_freq(dev);
6721         mutex_unlock(&dev_priv->rps.hw_lock);
6722         dev_priv->pc8.enabled = false;
6723 }
6724
6725 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6726 {
6727         if (!HAS_PC8(dev_priv->dev))
6728                 return;
6729
6730         mutex_lock(&dev_priv->pc8.lock);
6731         __hsw_enable_package_c8(dev_priv);
6732         mutex_unlock(&dev_priv->pc8.lock);
6733 }
6734
6735 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6736 {
6737         if (!HAS_PC8(dev_priv->dev))
6738                 return;
6739
6740         mutex_lock(&dev_priv->pc8.lock);
6741         __hsw_disable_package_c8(dev_priv);
6742         mutex_unlock(&dev_priv->pc8.lock);
6743 }
6744
6745 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6746 {
6747         struct drm_device *dev = dev_priv->dev;
6748         struct intel_crtc *crtc;
6749         uint32_t val;
6750
6751         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6752                 if (crtc->base.enabled)
6753                         return false;
6754
6755         /* This case is still possible since we have the i915.disable_power_well
6756          * parameter and also the KVMr or something else might be requesting the
6757          * power well. */
6758         val = I915_READ(HSW_PWR_WELL_DRIVER);
6759         if (val != 0) {
6760                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6761                 return false;
6762         }
6763
6764         return true;
6765 }
6766
6767 /* Since we're called from modeset_global_resources there's no way to
6768  * symmetrically increase and decrease the refcount, so we use
6769  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6770  * or not.
6771  */
6772 static void hsw_update_package_c8(struct drm_device *dev)
6773 {
6774         struct drm_i915_private *dev_priv = dev->dev_private;
6775         bool allow;
6776
6777         if (!HAS_PC8(dev_priv->dev))
6778                 return;
6779
6780         if (!i915_enable_pc8)
6781                 return;
6782
6783         mutex_lock(&dev_priv->pc8.lock);
6784
6785         allow = hsw_can_enable_package_c8(dev_priv);
6786
6787         if (allow == dev_priv->pc8.requirements_met)
6788                 goto done;
6789
6790         dev_priv->pc8.requirements_met = allow;
6791
6792         if (allow)
6793                 __hsw_enable_package_c8(dev_priv);
6794         else
6795                 __hsw_disable_package_c8(dev_priv);
6796
6797 done:
6798         mutex_unlock(&dev_priv->pc8.lock);
6799 }
6800
6801 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6802 {
6803         if (!HAS_PC8(dev_priv->dev))
6804                 return;
6805
6806         mutex_lock(&dev_priv->pc8.lock);
6807         if (!dev_priv->pc8.gpu_idle) {
6808                 dev_priv->pc8.gpu_idle = true;
6809                 __hsw_enable_package_c8(dev_priv);
6810         }
6811         mutex_unlock(&dev_priv->pc8.lock);
6812 }
6813
6814 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6815 {
6816         if (!HAS_PC8(dev_priv->dev))
6817                 return;
6818
6819         mutex_lock(&dev_priv->pc8.lock);
6820         if (dev_priv->pc8.gpu_idle) {
6821                 dev_priv->pc8.gpu_idle = false;
6822                 __hsw_disable_package_c8(dev_priv);
6823         }
6824         mutex_unlock(&dev_priv->pc8.lock);
6825 }
6826
6827 #define for_each_power_domain(domain, mask)                             \
6828         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6829                 if ((1 << (domain)) & (mask))
6830
6831 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6832                                             enum pipe pipe, bool pfit_enabled)
6833 {
6834         unsigned long mask;
6835         enum transcoder transcoder;
6836
6837         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6838
6839         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6840         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6841         if (pfit_enabled)
6842                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6843
6844         return mask;
6845 }
6846
6847 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6848 {
6849         struct drm_i915_private *dev_priv = dev->dev_private;
6850
6851         if (dev_priv->power_domains.init_power_on == enable)
6852                 return;
6853
6854         if (enable)
6855                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6856         else
6857                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6858
6859         dev_priv->power_domains.init_power_on = enable;
6860 }
6861
6862 static void modeset_update_power_wells(struct drm_device *dev)
6863 {
6864         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6865         struct intel_crtc *crtc;
6866
6867         /*
6868          * First get all needed power domains, then put all unneeded, to avoid
6869          * any unnecessary toggling of the power wells.
6870          */
6871         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6872                 enum intel_display_power_domain domain;
6873
6874                 if (!crtc->base.enabled)
6875                         continue;
6876
6877                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6878                                                 crtc->pipe,
6879                                                 crtc->config.pch_pfit.enabled);
6880
6881                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6882                         intel_display_power_get(dev, domain);
6883         }
6884
6885         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6886                 enum intel_display_power_domain domain;
6887
6888                 for_each_power_domain(domain, crtc->enabled_power_domains)
6889                         intel_display_power_put(dev, domain);
6890
6891                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6892         }
6893
6894         intel_display_set_init_power(dev, false);
6895 }
6896
6897 static void haswell_modeset_global_resources(struct drm_device *dev)
6898 {
6899         modeset_update_power_wells(dev);
6900         hsw_update_package_c8(dev);
6901 }
6902
6903 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6904                                  int x, int y,
6905                                  struct drm_framebuffer *fb)
6906 {
6907         struct drm_device *dev = crtc->dev;
6908         struct drm_i915_private *dev_priv = dev->dev_private;
6909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6910         int plane = intel_crtc->plane;
6911         int ret;
6912
6913         if (!intel_ddi_pll_select(intel_crtc))
6914                 return -EINVAL;
6915         intel_ddi_pll_enable(intel_crtc);
6916
6917         if (intel_crtc->config.has_dp_encoder)
6918                 intel_dp_set_m_n(intel_crtc);
6919
6920         intel_crtc->lowfreq_avail = false;
6921
6922         intel_set_pipe_timings(intel_crtc);
6923
6924         if (intel_crtc->config.has_pch_encoder) {
6925                 intel_cpu_transcoder_set_m_n(intel_crtc,
6926                                              &intel_crtc->config.fdi_m_n);
6927         }
6928
6929         haswell_set_pipeconf(crtc);
6930
6931         intel_set_pipe_csc(crtc);
6932
6933         /* Set up the display plane register */
6934         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6935         POSTING_READ(DSPCNTR(plane));
6936
6937         ret = intel_pipe_set_base(crtc, x, y, fb);
6938
6939         return ret;
6940 }
6941
6942 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6943                                     struct intel_crtc_config *pipe_config)
6944 {
6945         struct drm_device *dev = crtc->base.dev;
6946         struct drm_i915_private *dev_priv = dev->dev_private;
6947         enum intel_display_power_domain pfit_domain;
6948         uint32_t tmp;
6949
6950         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6951         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6952
6953         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6954         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6955                 enum pipe trans_edp_pipe;
6956                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6957                 default:
6958                         WARN(1, "unknown pipe linked to edp transcoder\n");
6959                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6960                 case TRANS_DDI_EDP_INPUT_A_ON:
6961                         trans_edp_pipe = PIPE_A;
6962                         break;
6963                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6964                         trans_edp_pipe = PIPE_B;
6965                         break;
6966                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6967                         trans_edp_pipe = PIPE_C;
6968                         break;
6969                 }
6970
6971                 if (trans_edp_pipe == crtc->pipe)
6972                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6973         }
6974
6975         if (!intel_display_power_enabled(dev,
6976                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6977                 return false;
6978
6979         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6980         if (!(tmp & PIPECONF_ENABLE))
6981                 return false;
6982
6983         /*
6984          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6985          * DDI E. So just check whether this pipe is wired to DDI E and whether
6986          * the PCH transcoder is on.
6987          */
6988         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6989         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6990             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6991                 pipe_config->has_pch_encoder = true;
6992
6993                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6994                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6995                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6996
6997                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6998         }
6999
7000         intel_get_pipe_timings(crtc, pipe_config);
7001
7002         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7003         if (intel_display_power_enabled(dev, pfit_domain))
7004                 ironlake_get_pfit_config(crtc, pipe_config);
7005
7006         if (IS_HASWELL(dev))
7007                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7008                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7009
7010         pipe_config->pixel_multiplier = 1;
7011
7012         return true;
7013 }
7014
7015 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7016                                int x, int y,
7017                                struct drm_framebuffer *fb)
7018 {
7019         struct drm_device *dev = crtc->dev;
7020         struct drm_i915_private *dev_priv = dev->dev_private;
7021         struct intel_encoder *encoder;
7022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7024         int pipe = intel_crtc->pipe;
7025         int ret;
7026
7027         drm_vblank_pre_modeset(dev, pipe);
7028
7029         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7030
7031         drm_vblank_post_modeset(dev, pipe);
7032
7033         if (ret != 0)
7034                 return ret;
7035
7036         for_each_encoder_on_crtc(dev, crtc, encoder) {
7037                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7038                         encoder->base.base.id,
7039                         drm_get_encoder_name(&encoder->base),
7040                         mode->base.id, mode->name);
7041                 encoder->mode_set(encoder);
7042         }
7043
7044         return 0;
7045 }
7046
7047 static struct {
7048         int clock;
7049         u32 config;
7050 } hdmi_audio_clock[] = {
7051         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7052         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7053         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7054         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7055         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7056         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7057         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7058         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7059         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7060         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7061 };
7062
7063 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7064 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7065 {
7066         int i;
7067
7068         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7069                 if (mode->clock == hdmi_audio_clock[i].clock)
7070                         break;
7071         }
7072
7073         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7074                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7075                 i = 1;
7076         }
7077
7078         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7079                       hdmi_audio_clock[i].clock,
7080                       hdmi_audio_clock[i].config);
7081
7082         return hdmi_audio_clock[i].config;
7083 }
7084
7085 static bool intel_eld_uptodate(struct drm_connector *connector,
7086                                int reg_eldv, uint32_t bits_eldv,
7087                                int reg_elda, uint32_t bits_elda,
7088                                int reg_edid)
7089 {
7090         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7091         uint8_t *eld = connector->eld;
7092         uint32_t i;
7093
7094         i = I915_READ(reg_eldv);
7095         i &= bits_eldv;
7096
7097         if (!eld[0])
7098                 return !i;
7099
7100         if (!i)
7101                 return false;
7102
7103         i = I915_READ(reg_elda);
7104         i &= ~bits_elda;
7105         I915_WRITE(reg_elda, i);
7106
7107         for (i = 0; i < eld[2]; i++)
7108                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7109                         return false;
7110
7111         return true;
7112 }
7113
7114 static void g4x_write_eld(struct drm_connector *connector,
7115                           struct drm_crtc *crtc,
7116                           struct drm_display_mode *mode)
7117 {
7118         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7119         uint8_t *eld = connector->eld;
7120         uint32_t eldv;
7121         uint32_t len;
7122         uint32_t i;
7123
7124         i = I915_READ(G4X_AUD_VID_DID);
7125
7126         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7127                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7128         else
7129                 eldv = G4X_ELDV_DEVCTG;
7130
7131         if (intel_eld_uptodate(connector,
7132                                G4X_AUD_CNTL_ST, eldv,
7133                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7134                                G4X_HDMIW_HDMIEDID))
7135                 return;
7136
7137         i = I915_READ(G4X_AUD_CNTL_ST);
7138         i &= ~(eldv | G4X_ELD_ADDR);
7139         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7140         I915_WRITE(G4X_AUD_CNTL_ST, i);
7141
7142         if (!eld[0])
7143                 return;
7144
7145         len = min_t(uint8_t, eld[2], len);
7146         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7147         for (i = 0; i < len; i++)
7148                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7149
7150         i = I915_READ(G4X_AUD_CNTL_ST);
7151         i |= eldv;
7152         I915_WRITE(G4X_AUD_CNTL_ST, i);
7153 }
7154
7155 static void haswell_write_eld(struct drm_connector *connector,
7156                               struct drm_crtc *crtc,
7157                               struct drm_display_mode *mode)
7158 {
7159         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7160         uint8_t *eld = connector->eld;
7161         struct drm_device *dev = crtc->dev;
7162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7163         uint32_t eldv;
7164         uint32_t i;
7165         int len;
7166         int pipe = to_intel_crtc(crtc)->pipe;
7167         int tmp;
7168
7169         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7170         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7171         int aud_config = HSW_AUD_CFG(pipe);
7172         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7173
7174
7175         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7176
7177         /* Audio output enable */
7178         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7179         tmp = I915_READ(aud_cntrl_st2);
7180         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7181         I915_WRITE(aud_cntrl_st2, tmp);
7182
7183         /* Wait for 1 vertical blank */
7184         intel_wait_for_vblank(dev, pipe);
7185
7186         /* Set ELD valid state */
7187         tmp = I915_READ(aud_cntrl_st2);
7188         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7189         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7190         I915_WRITE(aud_cntrl_st2, tmp);
7191         tmp = I915_READ(aud_cntrl_st2);
7192         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7193
7194         /* Enable HDMI mode */
7195         tmp = I915_READ(aud_config);
7196         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7197         /* clear N_programing_enable and N_value_index */
7198         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7199         I915_WRITE(aud_config, tmp);
7200
7201         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7202
7203         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7204         intel_crtc->eld_vld = true;
7205
7206         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7207                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7208                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7209                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7210         } else {
7211                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7212         }
7213
7214         if (intel_eld_uptodate(connector,
7215                                aud_cntrl_st2, eldv,
7216                                aud_cntl_st, IBX_ELD_ADDRESS,
7217                                hdmiw_hdmiedid))
7218                 return;
7219
7220         i = I915_READ(aud_cntrl_st2);
7221         i &= ~eldv;
7222         I915_WRITE(aud_cntrl_st2, i);
7223
7224         if (!eld[0])
7225                 return;
7226
7227         i = I915_READ(aud_cntl_st);
7228         i &= ~IBX_ELD_ADDRESS;
7229         I915_WRITE(aud_cntl_st, i);
7230         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7231         DRM_DEBUG_DRIVER("port num:%d\n", i);
7232
7233         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7234         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7235         for (i = 0; i < len; i++)
7236                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7237
7238         i = I915_READ(aud_cntrl_st2);
7239         i |= eldv;
7240         I915_WRITE(aud_cntrl_st2, i);
7241
7242 }
7243
7244 static void ironlake_write_eld(struct drm_connector *connector,
7245                                struct drm_crtc *crtc,
7246                                struct drm_display_mode *mode)
7247 {
7248         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7249         uint8_t *eld = connector->eld;
7250         uint32_t eldv;
7251         uint32_t i;
7252         int len;
7253         int hdmiw_hdmiedid;
7254         int aud_config;
7255         int aud_cntl_st;
7256         int aud_cntrl_st2;
7257         int pipe = to_intel_crtc(crtc)->pipe;
7258
7259         if (HAS_PCH_IBX(connector->dev)) {
7260                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7261                 aud_config = IBX_AUD_CFG(pipe);
7262                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7263                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7264         } else if (IS_VALLEYVIEW(connector->dev)) {
7265                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7266                 aud_config = VLV_AUD_CFG(pipe);
7267                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7268                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7269         } else {
7270                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7271                 aud_config = CPT_AUD_CFG(pipe);
7272                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7273                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7274         }
7275
7276         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7277
7278         if (IS_VALLEYVIEW(connector->dev))  {
7279                 struct intel_encoder *intel_encoder;
7280                 struct intel_digital_port *intel_dig_port;
7281
7282                 intel_encoder = intel_attached_encoder(connector);
7283                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7284                 i = intel_dig_port->port;
7285         } else {
7286                 i = I915_READ(aud_cntl_st);
7287                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7288                 /* DIP_Port_Select, 0x1 = PortB */
7289         }
7290
7291         if (!i) {
7292                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7293                 /* operate blindly on all ports */
7294                 eldv = IBX_ELD_VALIDB;
7295                 eldv |= IBX_ELD_VALIDB << 4;
7296                 eldv |= IBX_ELD_VALIDB << 8;
7297         } else {
7298                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7299                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7300         }
7301
7302         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7303                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7304                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7305                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7306         } else {
7307                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7308         }
7309
7310         if (intel_eld_uptodate(connector,
7311                                aud_cntrl_st2, eldv,
7312                                aud_cntl_st, IBX_ELD_ADDRESS,
7313                                hdmiw_hdmiedid))
7314                 return;
7315
7316         i = I915_READ(aud_cntrl_st2);
7317         i &= ~eldv;
7318         I915_WRITE(aud_cntrl_st2, i);
7319
7320         if (!eld[0])
7321                 return;
7322
7323         i = I915_READ(aud_cntl_st);
7324         i &= ~IBX_ELD_ADDRESS;
7325         I915_WRITE(aud_cntl_st, i);
7326
7327         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7328         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7329         for (i = 0; i < len; i++)
7330                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7331
7332         i = I915_READ(aud_cntrl_st2);
7333         i |= eldv;
7334         I915_WRITE(aud_cntrl_st2, i);
7335 }
7336
7337 void intel_write_eld(struct drm_encoder *encoder,
7338                      struct drm_display_mode *mode)
7339 {
7340         struct drm_crtc *crtc = encoder->crtc;
7341         struct drm_connector *connector;
7342         struct drm_device *dev = encoder->dev;
7343         struct drm_i915_private *dev_priv = dev->dev_private;
7344
7345         connector = drm_select_eld(encoder, mode);
7346         if (!connector)
7347                 return;
7348
7349         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7350                          connector->base.id,
7351                          drm_get_connector_name(connector),
7352                          connector->encoder->base.id,
7353                          drm_get_encoder_name(connector->encoder));
7354
7355         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7356
7357         if (dev_priv->display.write_eld)
7358                 dev_priv->display.write_eld(connector, crtc, mode);
7359 }
7360
7361 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7362 {
7363         struct drm_device *dev = crtc->dev;
7364         struct drm_i915_private *dev_priv = dev->dev_private;
7365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7366         bool visible = base != 0;
7367         u32 cntl;
7368
7369         if (intel_crtc->cursor_visible == visible)
7370                 return;
7371
7372         cntl = I915_READ(_CURACNTR);
7373         if (visible) {
7374                 /* On these chipsets we can only modify the base whilst
7375                  * the cursor is disabled.
7376                  */
7377                 I915_WRITE(_CURABASE, base);
7378
7379                 cntl &= ~(CURSOR_FORMAT_MASK);
7380                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7381                 cntl |= CURSOR_ENABLE |
7382                         CURSOR_GAMMA_ENABLE |
7383                         CURSOR_FORMAT_ARGB;
7384         } else
7385                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7386         I915_WRITE(_CURACNTR, cntl);
7387
7388         intel_crtc->cursor_visible = visible;
7389 }
7390
7391 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7392 {
7393         struct drm_device *dev = crtc->dev;
7394         struct drm_i915_private *dev_priv = dev->dev_private;
7395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7396         int pipe = intel_crtc->pipe;
7397         bool visible = base != 0;
7398
7399         if (intel_crtc->cursor_visible != visible) {
7400                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7401                 if (base) {
7402                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7403                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7404                         cntl |= pipe << 28; /* Connect to correct pipe */
7405                 } else {
7406                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7407                         cntl |= CURSOR_MODE_DISABLE;
7408                 }
7409                 I915_WRITE(CURCNTR(pipe), cntl);
7410
7411                 intel_crtc->cursor_visible = visible;
7412         }
7413         /* and commit changes on next vblank */
7414         POSTING_READ(CURCNTR(pipe));
7415         I915_WRITE(CURBASE(pipe), base);
7416         POSTING_READ(CURBASE(pipe));
7417 }
7418
7419 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7420 {
7421         struct drm_device *dev = crtc->dev;
7422         struct drm_i915_private *dev_priv = dev->dev_private;
7423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7424         int pipe = intel_crtc->pipe;
7425         bool visible = base != 0;
7426
7427         if (intel_crtc->cursor_visible != visible) {
7428                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7429                 if (base) {
7430                         cntl &= ~CURSOR_MODE;
7431                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7432                 } else {
7433                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7434                         cntl |= CURSOR_MODE_DISABLE;
7435                 }
7436                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7437                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7438                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7439                 }
7440                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7441
7442                 intel_crtc->cursor_visible = visible;
7443         }
7444         /* and commit changes on next vblank */
7445         POSTING_READ(CURCNTR_IVB(pipe));
7446         I915_WRITE(CURBASE_IVB(pipe), base);
7447         POSTING_READ(CURBASE_IVB(pipe));
7448 }
7449
7450 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7451 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7452                                      bool on)
7453 {
7454         struct drm_device *dev = crtc->dev;
7455         struct drm_i915_private *dev_priv = dev->dev_private;
7456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457         int pipe = intel_crtc->pipe;
7458         int x = intel_crtc->cursor_x;
7459         int y = intel_crtc->cursor_y;
7460         u32 base = 0, pos = 0;
7461         bool visible;
7462
7463         if (on)
7464                 base = intel_crtc->cursor_addr;
7465
7466         if (x >= intel_crtc->config.pipe_src_w)
7467                 base = 0;
7468
7469         if (y >= intel_crtc->config.pipe_src_h)
7470                 base = 0;
7471
7472         if (x < 0) {
7473                 if (x + intel_crtc->cursor_width <= 0)
7474                         base = 0;
7475
7476                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7477                 x = -x;
7478         }
7479         pos |= x << CURSOR_X_SHIFT;
7480
7481         if (y < 0) {
7482                 if (y + intel_crtc->cursor_height <= 0)
7483                         base = 0;
7484
7485                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7486                 y = -y;
7487         }
7488         pos |= y << CURSOR_Y_SHIFT;
7489
7490         visible = base != 0;
7491         if (!visible && !intel_crtc->cursor_visible)
7492                 return;
7493
7494         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7495                 I915_WRITE(CURPOS_IVB(pipe), pos);
7496                 ivb_update_cursor(crtc, base);
7497         } else {
7498                 I915_WRITE(CURPOS(pipe), pos);
7499                 if (IS_845G(dev) || IS_I865G(dev))
7500                         i845_update_cursor(crtc, base);
7501                 else
7502                         i9xx_update_cursor(crtc, base);
7503         }
7504 }
7505
7506 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7507                                  struct drm_file *file,
7508                                  uint32_t handle,
7509                                  uint32_t width, uint32_t height)
7510 {
7511         struct drm_device *dev = crtc->dev;
7512         struct drm_i915_private *dev_priv = dev->dev_private;
7513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7514         struct drm_i915_gem_object *obj;
7515         uint32_t addr;
7516         int ret;
7517
7518         /* if we want to turn off the cursor ignore width and height */
7519         if (!handle) {
7520                 DRM_DEBUG_KMS("cursor off\n");
7521                 addr = 0;
7522                 obj = NULL;
7523                 mutex_lock(&dev->struct_mutex);
7524                 goto finish;
7525         }
7526
7527         /* Currently we only support 64x64 cursors */
7528         if (width != 64 || height != 64) {
7529                 DRM_ERROR("we currently only support 64x64 cursors\n");
7530                 return -EINVAL;
7531         }
7532
7533         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7534         if (&obj->base == NULL)
7535                 return -ENOENT;
7536
7537         if (obj->base.size < width * height * 4) {
7538                 DRM_ERROR("buffer is to small\n");
7539                 ret = -ENOMEM;
7540                 goto fail;
7541         }
7542
7543         /* we only need to pin inside GTT if cursor is non-phy */
7544         mutex_lock(&dev->struct_mutex);
7545         if (!dev_priv->info->cursor_needs_physical) {
7546                 unsigned alignment;
7547
7548                 if (obj->tiling_mode) {
7549                         DRM_ERROR("cursor cannot be tiled\n");
7550                         ret = -EINVAL;
7551                         goto fail_locked;
7552                 }
7553
7554                 /* Note that the w/a also requires 2 PTE of padding following
7555                  * the bo. We currently fill all unused PTE with the shadow
7556                  * page and so we should always have valid PTE following the
7557                  * cursor preventing the VT-d warning.
7558                  */
7559                 alignment = 0;
7560                 if (need_vtd_wa(dev))
7561                         alignment = 64*1024;
7562
7563                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7564                 if (ret) {
7565                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7566                         goto fail_locked;
7567                 }
7568
7569                 ret = i915_gem_object_put_fence(obj);
7570                 if (ret) {
7571                         DRM_ERROR("failed to release fence for cursor");
7572                         goto fail_unpin;
7573                 }
7574
7575                 addr = i915_gem_obj_ggtt_offset(obj);
7576         } else {
7577                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7578                 ret = i915_gem_attach_phys_object(dev, obj,
7579                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7580                                                   align);
7581                 if (ret) {
7582                         DRM_ERROR("failed to attach phys object\n");
7583                         goto fail_locked;
7584                 }
7585                 addr = obj->phys_obj->handle->busaddr;
7586         }
7587
7588         if (IS_GEN2(dev))
7589                 I915_WRITE(CURSIZE, (height << 12) | width);
7590
7591  finish:
7592         if (intel_crtc->cursor_bo) {
7593                 if (dev_priv->info->cursor_needs_physical) {
7594                         if (intel_crtc->cursor_bo != obj)
7595                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7596                 } else
7597                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7598                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7599         }
7600
7601         mutex_unlock(&dev->struct_mutex);
7602
7603         intel_crtc->cursor_addr = addr;
7604         intel_crtc->cursor_bo = obj;
7605         intel_crtc->cursor_width = width;
7606         intel_crtc->cursor_height = height;
7607
7608         if (intel_crtc->active)
7609                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7610
7611         return 0;
7612 fail_unpin:
7613         i915_gem_object_unpin_from_display_plane(obj);
7614 fail_locked:
7615         mutex_unlock(&dev->struct_mutex);
7616 fail:
7617         drm_gem_object_unreference_unlocked(&obj->base);
7618         return ret;
7619 }
7620
7621 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7622 {
7623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7624
7625         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7626         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7627
7628         if (intel_crtc->active)
7629                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7630
7631         return 0;
7632 }
7633
7634 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7635                                  u16 *blue, uint32_t start, uint32_t size)
7636 {
7637         int end = (start + size > 256) ? 256 : start + size, i;
7638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7639
7640         for (i = start; i < end; i++) {
7641                 intel_crtc->lut_r[i] = red[i] >> 8;
7642                 intel_crtc->lut_g[i] = green[i] >> 8;
7643                 intel_crtc->lut_b[i] = blue[i] >> 8;
7644         }
7645
7646         intel_crtc_load_lut(crtc);
7647 }
7648
7649 /* VESA 640x480x72Hz mode to set on the pipe */
7650 static struct drm_display_mode load_detect_mode = {
7651         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7652                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7653 };
7654
7655 static struct drm_framebuffer *
7656 intel_framebuffer_create(struct drm_device *dev,
7657                          struct drm_mode_fb_cmd2 *mode_cmd,
7658                          struct drm_i915_gem_object *obj)
7659 {
7660         struct intel_framebuffer *intel_fb;
7661         int ret;
7662
7663         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7664         if (!intel_fb) {
7665                 drm_gem_object_unreference_unlocked(&obj->base);
7666                 return ERR_PTR(-ENOMEM);
7667         }
7668
7669         ret = i915_mutex_lock_interruptible(dev);
7670         if (ret)
7671                 goto err;
7672
7673         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7674         mutex_unlock(&dev->struct_mutex);
7675         if (ret)
7676                 goto err;
7677
7678         return &intel_fb->base;
7679 err:
7680         drm_gem_object_unreference_unlocked(&obj->base);
7681         kfree(intel_fb);
7682
7683         return ERR_PTR(ret);
7684 }
7685
7686 static u32
7687 intel_framebuffer_pitch_for_width(int width, int bpp)
7688 {
7689         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7690         return ALIGN(pitch, 64);
7691 }
7692
7693 static u32
7694 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7695 {
7696         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7697         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7698 }
7699
7700 static struct drm_framebuffer *
7701 intel_framebuffer_create_for_mode(struct drm_device *dev,
7702                                   struct drm_display_mode *mode,
7703                                   int depth, int bpp)
7704 {
7705         struct drm_i915_gem_object *obj;
7706         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7707
7708         obj = i915_gem_alloc_object(dev,
7709                                     intel_framebuffer_size_for_mode(mode, bpp));
7710         if (obj == NULL)
7711                 return ERR_PTR(-ENOMEM);
7712
7713         mode_cmd.width = mode->hdisplay;
7714         mode_cmd.height = mode->vdisplay;
7715         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7716                                                                 bpp);
7717         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7718
7719         return intel_framebuffer_create(dev, &mode_cmd, obj);
7720 }
7721
7722 static struct drm_framebuffer *
7723 mode_fits_in_fbdev(struct drm_device *dev,
7724                    struct drm_display_mode *mode)
7725 {
7726 #ifdef CONFIG_DRM_I915_FBDEV
7727         struct drm_i915_private *dev_priv = dev->dev_private;
7728         struct drm_i915_gem_object *obj;
7729         struct drm_framebuffer *fb;
7730
7731         if (dev_priv->fbdev == NULL)
7732                 return NULL;
7733
7734         obj = dev_priv->fbdev->ifb.obj;
7735         if (obj == NULL)
7736                 return NULL;
7737
7738         fb = &dev_priv->fbdev->ifb.base;
7739         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7740                                                                fb->bits_per_pixel))
7741                 return NULL;
7742
7743         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7744                 return NULL;
7745
7746         return fb;
7747 #else
7748         return NULL;
7749 #endif
7750 }
7751
7752 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7753                                 struct drm_display_mode *mode,
7754                                 struct intel_load_detect_pipe *old)
7755 {
7756         struct intel_crtc *intel_crtc;
7757         struct intel_encoder *intel_encoder =
7758                 intel_attached_encoder(connector);
7759         struct drm_crtc *possible_crtc;
7760         struct drm_encoder *encoder = &intel_encoder->base;
7761         struct drm_crtc *crtc = NULL;
7762         struct drm_device *dev = encoder->dev;
7763         struct drm_framebuffer *fb;
7764         int i = -1;
7765
7766         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7767                       connector->base.id, drm_get_connector_name(connector),
7768                       encoder->base.id, drm_get_encoder_name(encoder));
7769
7770         /*
7771          * Algorithm gets a little messy:
7772          *
7773          *   - if the connector already has an assigned crtc, use it (but make
7774          *     sure it's on first)
7775          *
7776          *   - try to find the first unused crtc that can drive this connector,
7777          *     and use that if we find one
7778          */
7779
7780         /* See if we already have a CRTC for this connector */
7781         if (encoder->crtc) {
7782                 crtc = encoder->crtc;
7783
7784                 mutex_lock(&crtc->mutex);
7785
7786                 old->dpms_mode = connector->dpms;
7787                 old->load_detect_temp = false;
7788
7789                 /* Make sure the crtc and connector are running */
7790                 if (connector->dpms != DRM_MODE_DPMS_ON)
7791                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7792
7793                 return true;
7794         }
7795
7796         /* Find an unused one (if possible) */
7797         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7798                 i++;
7799                 if (!(encoder->possible_crtcs & (1 << i)))
7800                         continue;
7801                 if (!possible_crtc->enabled) {
7802                         crtc = possible_crtc;
7803                         break;
7804                 }
7805         }
7806
7807         /*
7808          * If we didn't find an unused CRTC, don't use any.
7809          */
7810         if (!crtc) {
7811                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7812                 return false;
7813         }
7814
7815         mutex_lock(&crtc->mutex);
7816         intel_encoder->new_crtc = to_intel_crtc(crtc);
7817         to_intel_connector(connector)->new_encoder = intel_encoder;
7818
7819         intel_crtc = to_intel_crtc(crtc);
7820         old->dpms_mode = connector->dpms;
7821         old->load_detect_temp = true;
7822         old->release_fb = NULL;
7823
7824         if (!mode)
7825                 mode = &load_detect_mode;
7826
7827         /* We need a framebuffer large enough to accommodate all accesses
7828          * that the plane may generate whilst we perform load detection.
7829          * We can not rely on the fbcon either being present (we get called
7830          * during its initialisation to detect all boot displays, or it may
7831          * not even exist) or that it is large enough to satisfy the
7832          * requested mode.
7833          */
7834         fb = mode_fits_in_fbdev(dev, mode);
7835         if (fb == NULL) {
7836                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7837                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7838                 old->release_fb = fb;
7839         } else
7840                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7841         if (IS_ERR(fb)) {
7842                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7843                 mutex_unlock(&crtc->mutex);
7844                 return false;
7845         }
7846
7847         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7848                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7849                 if (old->release_fb)
7850                         old->release_fb->funcs->destroy(old->release_fb);
7851                 mutex_unlock(&crtc->mutex);
7852                 return false;
7853         }
7854
7855         /* let the connector get through one full cycle before testing */
7856         intel_wait_for_vblank(dev, intel_crtc->pipe);
7857         return true;
7858 }
7859
7860 void intel_release_load_detect_pipe(struct drm_connector *connector,
7861                                     struct intel_load_detect_pipe *old)
7862 {
7863         struct intel_encoder *intel_encoder =
7864                 intel_attached_encoder(connector);
7865         struct drm_encoder *encoder = &intel_encoder->base;
7866         struct drm_crtc *crtc = encoder->crtc;
7867
7868         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7869                       connector->base.id, drm_get_connector_name(connector),
7870                       encoder->base.id, drm_get_encoder_name(encoder));
7871
7872         if (old->load_detect_temp) {
7873                 to_intel_connector(connector)->new_encoder = NULL;
7874                 intel_encoder->new_crtc = NULL;
7875                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7876
7877                 if (old->release_fb) {
7878                         drm_framebuffer_unregister_private(old->release_fb);
7879                         drm_framebuffer_unreference(old->release_fb);
7880                 }
7881
7882                 mutex_unlock(&crtc->mutex);
7883                 return;
7884         }
7885
7886         /* Switch crtc and encoder back off if necessary */
7887         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7888                 connector->funcs->dpms(connector, old->dpms_mode);
7889
7890         mutex_unlock(&crtc->mutex);
7891 }
7892
7893 static int i9xx_pll_refclk(struct drm_device *dev,
7894                            const struct intel_crtc_config *pipe_config)
7895 {
7896         struct drm_i915_private *dev_priv = dev->dev_private;
7897         u32 dpll = pipe_config->dpll_hw_state.dpll;
7898
7899         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7900                 return dev_priv->vbt.lvds_ssc_freq;
7901         else if (HAS_PCH_SPLIT(dev))
7902                 return 120000;
7903         else if (!IS_GEN2(dev))
7904                 return 96000;
7905         else
7906                 return 48000;
7907 }
7908
7909 /* Returns the clock of the currently programmed mode of the given pipe. */
7910 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7911                                 struct intel_crtc_config *pipe_config)
7912 {
7913         struct drm_device *dev = crtc->base.dev;
7914         struct drm_i915_private *dev_priv = dev->dev_private;
7915         int pipe = pipe_config->cpu_transcoder;
7916         u32 dpll = pipe_config->dpll_hw_state.dpll;
7917         u32 fp;
7918         intel_clock_t clock;
7919         int refclk = i9xx_pll_refclk(dev, pipe_config);
7920
7921         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7922                 fp = pipe_config->dpll_hw_state.fp0;
7923         else
7924                 fp = pipe_config->dpll_hw_state.fp1;
7925
7926         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7927         if (IS_PINEVIEW(dev)) {
7928                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7929                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7930         } else {
7931                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7932                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7933         }
7934
7935         if (!IS_GEN2(dev)) {
7936                 if (IS_PINEVIEW(dev))
7937                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7938                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7939                 else
7940                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7941                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7942
7943                 switch (dpll & DPLL_MODE_MASK) {
7944                 case DPLLB_MODE_DAC_SERIAL:
7945                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7946                                 5 : 10;
7947                         break;
7948                 case DPLLB_MODE_LVDS:
7949                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7950                                 7 : 14;
7951                         break;
7952                 default:
7953                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7954                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7955                         return;
7956                 }
7957
7958                 if (IS_PINEVIEW(dev))
7959                         pineview_clock(refclk, &clock);
7960                 else
7961                         i9xx_clock(refclk, &clock);
7962         } else {
7963                 u32 lvds = I915_READ(LVDS);
7964                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7965
7966                 if (is_lvds) {
7967                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7968                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7969
7970                         if (lvds & LVDS_CLKB_POWER_UP)
7971                                 clock.p2 = 7;
7972                         else
7973                                 clock.p2 = 14;
7974                 } else {
7975                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7976                                 clock.p1 = 2;
7977                         else {
7978                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7979                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7980                         }
7981                         if (dpll & PLL_P2_DIVIDE_BY_4)
7982                                 clock.p2 = 4;
7983                         else
7984                                 clock.p2 = 2;
7985                 }
7986
7987                 i9xx_clock(refclk, &clock);
7988         }
7989
7990         /*
7991          * This value includes pixel_multiplier. We will use
7992          * port_clock to compute adjusted_mode.crtc_clock in the
7993          * encoder's get_config() function.
7994          */
7995         pipe_config->port_clock = clock.dot;
7996 }
7997
7998 int intel_dotclock_calculate(int link_freq,
7999                              const struct intel_link_m_n *m_n)
8000 {
8001         /*
8002          * The calculation for the data clock is:
8003          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8004          * But we want to avoid losing precison if possible, so:
8005          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8006          *
8007          * and the link clock is simpler:
8008          * link_clock = (m * link_clock) / n
8009          */
8010
8011         if (!m_n->link_n)
8012                 return 0;
8013
8014         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8015 }
8016
8017 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8018                                    struct intel_crtc_config *pipe_config)
8019 {
8020         struct drm_device *dev = crtc->base.dev;
8021
8022         /* read out port_clock from the DPLL */
8023         i9xx_crtc_clock_get(crtc, pipe_config);
8024
8025         /*
8026          * This value does not include pixel_multiplier.
8027          * We will check that port_clock and adjusted_mode.crtc_clock
8028          * agree once we know their relationship in the encoder's
8029          * get_config() function.
8030          */
8031         pipe_config->adjusted_mode.crtc_clock =
8032                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8033                                          &pipe_config->fdi_m_n);
8034 }
8035
8036 /** Returns the currently programmed mode of the given pipe. */
8037 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8038                                              struct drm_crtc *crtc)
8039 {
8040         struct drm_i915_private *dev_priv = dev->dev_private;
8041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8042         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8043         struct drm_display_mode *mode;
8044         struct intel_crtc_config pipe_config;
8045         int htot = I915_READ(HTOTAL(cpu_transcoder));
8046         int hsync = I915_READ(HSYNC(cpu_transcoder));
8047         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8048         int vsync = I915_READ(VSYNC(cpu_transcoder));
8049         enum pipe pipe = intel_crtc->pipe;
8050
8051         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8052         if (!mode)
8053                 return NULL;
8054
8055         /*
8056          * Construct a pipe_config sufficient for getting the clock info
8057          * back out of crtc_clock_get.
8058          *
8059          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8060          * to use a real value here instead.
8061          */
8062         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8063         pipe_config.pixel_multiplier = 1;
8064         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8065         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8066         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8067         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8068
8069         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8070         mode->hdisplay = (htot & 0xffff) + 1;
8071         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8072         mode->hsync_start = (hsync & 0xffff) + 1;
8073         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8074         mode->vdisplay = (vtot & 0xffff) + 1;
8075         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8076         mode->vsync_start = (vsync & 0xffff) + 1;
8077         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8078
8079         drm_mode_set_name(mode);
8080
8081         return mode;
8082 }
8083
8084 static void intel_increase_pllclock(struct drm_crtc *crtc)
8085 {
8086         struct drm_device *dev = crtc->dev;
8087         drm_i915_private_t *dev_priv = dev->dev_private;
8088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8089         int pipe = intel_crtc->pipe;
8090         int dpll_reg = DPLL(pipe);
8091         int dpll;
8092
8093         if (HAS_PCH_SPLIT(dev))
8094                 return;
8095
8096         if (!dev_priv->lvds_downclock_avail)
8097                 return;
8098
8099         dpll = I915_READ(dpll_reg);
8100         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8101                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8102
8103                 assert_panel_unlocked(dev_priv, pipe);
8104
8105                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8106                 I915_WRITE(dpll_reg, dpll);
8107                 intel_wait_for_vblank(dev, pipe);
8108
8109                 dpll = I915_READ(dpll_reg);
8110                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8111                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8112         }
8113 }
8114
8115 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8116 {
8117         struct drm_device *dev = crtc->dev;
8118         drm_i915_private_t *dev_priv = dev->dev_private;
8119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8120
8121         if (HAS_PCH_SPLIT(dev))
8122                 return;
8123
8124         if (!dev_priv->lvds_downclock_avail)
8125                 return;
8126
8127         /*
8128          * Since this is called by a timer, we should never get here in
8129          * the manual case.
8130          */
8131         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8132                 int pipe = intel_crtc->pipe;
8133                 int dpll_reg = DPLL(pipe);
8134                 int dpll;
8135
8136                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8137
8138                 assert_panel_unlocked(dev_priv, pipe);
8139
8140                 dpll = I915_READ(dpll_reg);
8141                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8142                 I915_WRITE(dpll_reg, dpll);
8143                 intel_wait_for_vblank(dev, pipe);
8144                 dpll = I915_READ(dpll_reg);
8145                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8146                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8147         }
8148
8149 }
8150
8151 void intel_mark_busy(struct drm_device *dev)
8152 {
8153         struct drm_i915_private *dev_priv = dev->dev_private;
8154
8155         hsw_package_c8_gpu_busy(dev_priv);
8156         i915_update_gfx_val(dev_priv);
8157 }
8158
8159 void intel_mark_idle(struct drm_device *dev)
8160 {
8161         struct drm_i915_private *dev_priv = dev->dev_private;
8162         struct drm_crtc *crtc;
8163
8164         hsw_package_c8_gpu_idle(dev_priv);
8165
8166         if (!i915_powersave)
8167                 return;
8168
8169         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8170                 if (!crtc->fb)
8171                         continue;
8172
8173                 intel_decrease_pllclock(crtc);
8174         }
8175
8176         if (dev_priv->info->gen >= 6)
8177                 gen6_rps_idle(dev->dev_private);
8178 }
8179
8180 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8181                         struct intel_ring_buffer *ring)
8182 {
8183         struct drm_device *dev = obj->base.dev;
8184         struct drm_crtc *crtc;
8185
8186         if (!i915_powersave)
8187                 return;
8188
8189         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8190                 if (!crtc->fb)
8191                         continue;
8192
8193                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8194                         continue;
8195
8196                 intel_increase_pllclock(crtc);
8197                 if (ring && intel_fbc_enabled(dev))
8198                         ring->fbc_dirty = true;
8199         }
8200 }
8201
8202 static void intel_crtc_destroy(struct drm_crtc *crtc)
8203 {
8204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8205         struct drm_device *dev = crtc->dev;
8206         struct intel_unpin_work *work;
8207         unsigned long flags;
8208
8209         spin_lock_irqsave(&dev->event_lock, flags);
8210         work = intel_crtc->unpin_work;
8211         intel_crtc->unpin_work = NULL;
8212         spin_unlock_irqrestore(&dev->event_lock, flags);
8213
8214         if (work) {
8215                 cancel_work_sync(&work->work);
8216                 kfree(work);
8217         }
8218
8219         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8220
8221         drm_crtc_cleanup(crtc);
8222
8223         kfree(intel_crtc);
8224 }
8225
8226 static void intel_unpin_work_fn(struct work_struct *__work)
8227 {
8228         struct intel_unpin_work *work =
8229                 container_of(__work, struct intel_unpin_work, work);
8230         struct drm_device *dev = work->crtc->dev;
8231
8232         mutex_lock(&dev->struct_mutex);
8233         intel_unpin_fb_obj(work->old_fb_obj);
8234         drm_gem_object_unreference(&work->pending_flip_obj->base);
8235         drm_gem_object_unreference(&work->old_fb_obj->base);
8236
8237         intel_update_fbc(dev);
8238         mutex_unlock(&dev->struct_mutex);
8239
8240         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8241         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8242
8243         kfree(work);
8244 }
8245
8246 static void do_intel_finish_page_flip(struct drm_device *dev,
8247                                       struct drm_crtc *crtc)
8248 {
8249         drm_i915_private_t *dev_priv = dev->dev_private;
8250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8251         struct intel_unpin_work *work;
8252         unsigned long flags;
8253
8254         /* Ignore early vblank irqs */
8255         if (intel_crtc == NULL)
8256                 return;
8257
8258         spin_lock_irqsave(&dev->event_lock, flags);
8259         work = intel_crtc->unpin_work;
8260
8261         /* Ensure we don't miss a work->pending update ... */
8262         smp_rmb();
8263
8264         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8265                 spin_unlock_irqrestore(&dev->event_lock, flags);
8266                 return;
8267         }
8268
8269         /* and that the unpin work is consistent wrt ->pending. */
8270         smp_rmb();
8271
8272         intel_crtc->unpin_work = NULL;
8273
8274         if (work->event)
8275                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8276
8277         drm_vblank_put(dev, intel_crtc->pipe);
8278
8279         spin_unlock_irqrestore(&dev->event_lock, flags);
8280
8281         wake_up_all(&dev_priv->pending_flip_queue);
8282
8283         queue_work(dev_priv->wq, &work->work);
8284
8285         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8286 }
8287
8288 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8289 {
8290         drm_i915_private_t *dev_priv = dev->dev_private;
8291         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8292
8293         do_intel_finish_page_flip(dev, crtc);
8294 }
8295
8296 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8297 {
8298         drm_i915_private_t *dev_priv = dev->dev_private;
8299         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8300
8301         do_intel_finish_page_flip(dev, crtc);
8302 }
8303
8304 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8305 {
8306         drm_i915_private_t *dev_priv = dev->dev_private;
8307         struct intel_crtc *intel_crtc =
8308                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8309         unsigned long flags;
8310
8311         /* NB: An MMIO update of the plane base pointer will also
8312          * generate a page-flip completion irq, i.e. every modeset
8313          * is also accompanied by a spurious intel_prepare_page_flip().
8314          */
8315         spin_lock_irqsave(&dev->event_lock, flags);
8316         if (intel_crtc->unpin_work)
8317                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8318         spin_unlock_irqrestore(&dev->event_lock, flags);
8319 }
8320
8321 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8322 {
8323         /* Ensure that the work item is consistent when activating it ... */
8324         smp_wmb();
8325         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8326         /* and that it is marked active as soon as the irq could fire. */
8327         smp_wmb();
8328 }
8329
8330 static int intel_gen2_queue_flip(struct drm_device *dev,
8331                                  struct drm_crtc *crtc,
8332                                  struct drm_framebuffer *fb,
8333                                  struct drm_i915_gem_object *obj,
8334                                  uint32_t flags)
8335 {
8336         struct drm_i915_private *dev_priv = dev->dev_private;
8337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8338         u32 flip_mask;
8339         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8340         int ret;
8341
8342         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8343         if (ret)
8344                 goto err;
8345
8346         ret = intel_ring_begin(ring, 6);
8347         if (ret)
8348                 goto err_unpin;
8349
8350         /* Can't queue multiple flips, so wait for the previous
8351          * one to finish before executing the next.
8352          */
8353         if (intel_crtc->plane)
8354                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8355         else
8356                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8357         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8358         intel_ring_emit(ring, MI_NOOP);
8359         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8360                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8361         intel_ring_emit(ring, fb->pitches[0]);
8362         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8363         intel_ring_emit(ring, 0); /* aux display base address, unused */
8364
8365         intel_mark_page_flip_active(intel_crtc);
8366         __intel_ring_advance(ring);
8367         return 0;
8368
8369 err_unpin:
8370         intel_unpin_fb_obj(obj);
8371 err:
8372         return ret;
8373 }
8374
8375 static int intel_gen3_queue_flip(struct drm_device *dev,
8376                                  struct drm_crtc *crtc,
8377                                  struct drm_framebuffer *fb,
8378                                  struct drm_i915_gem_object *obj,
8379                                  uint32_t flags)
8380 {
8381         struct drm_i915_private *dev_priv = dev->dev_private;
8382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8383         u32 flip_mask;
8384         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8385         int ret;
8386
8387         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8388         if (ret)
8389                 goto err;
8390
8391         ret = intel_ring_begin(ring, 6);
8392         if (ret)
8393                 goto err_unpin;
8394
8395         if (intel_crtc->plane)
8396                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8397         else
8398                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8399         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8400         intel_ring_emit(ring, MI_NOOP);
8401         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8402                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8403         intel_ring_emit(ring, fb->pitches[0]);
8404         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8405         intel_ring_emit(ring, MI_NOOP);
8406
8407         intel_mark_page_flip_active(intel_crtc);
8408         __intel_ring_advance(ring);
8409         return 0;
8410
8411 err_unpin:
8412         intel_unpin_fb_obj(obj);
8413 err:
8414         return ret;
8415 }
8416
8417 static int intel_gen4_queue_flip(struct drm_device *dev,
8418                                  struct drm_crtc *crtc,
8419                                  struct drm_framebuffer *fb,
8420                                  struct drm_i915_gem_object *obj,
8421                                  uint32_t flags)
8422 {
8423         struct drm_i915_private *dev_priv = dev->dev_private;
8424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8425         uint32_t pf, pipesrc;
8426         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8427         int ret;
8428
8429         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8430         if (ret)
8431                 goto err;
8432
8433         ret = intel_ring_begin(ring, 4);
8434         if (ret)
8435                 goto err_unpin;
8436
8437         /* i965+ uses the linear or tiled offsets from the
8438          * Display Registers (which do not change across a page-flip)
8439          * so we need only reprogram the base address.
8440          */
8441         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8442                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8443         intel_ring_emit(ring, fb->pitches[0]);
8444         intel_ring_emit(ring,
8445                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8446                         obj->tiling_mode);
8447
8448         /* XXX Enabling the panel-fitter across page-flip is so far
8449          * untested on non-native modes, so ignore it for now.
8450          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8451          */
8452         pf = 0;
8453         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8454         intel_ring_emit(ring, pf | pipesrc);
8455
8456         intel_mark_page_flip_active(intel_crtc);
8457         __intel_ring_advance(ring);
8458         return 0;
8459
8460 err_unpin:
8461         intel_unpin_fb_obj(obj);
8462 err:
8463         return ret;
8464 }
8465
8466 static int intel_gen6_queue_flip(struct drm_device *dev,
8467                                  struct drm_crtc *crtc,
8468                                  struct drm_framebuffer *fb,
8469                                  struct drm_i915_gem_object *obj,
8470                                  uint32_t flags)
8471 {
8472         struct drm_i915_private *dev_priv = dev->dev_private;
8473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8474         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8475         uint32_t pf, pipesrc;
8476         int ret;
8477
8478         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8479         if (ret)
8480                 goto err;
8481
8482         ret = intel_ring_begin(ring, 4);
8483         if (ret)
8484                 goto err_unpin;
8485
8486         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8487                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8488         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8489         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8490
8491         /* Contrary to the suggestions in the documentation,
8492          * "Enable Panel Fitter" does not seem to be required when page
8493          * flipping with a non-native mode, and worse causes a normal
8494          * modeset to fail.
8495          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8496          */
8497         pf = 0;
8498         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8499         intel_ring_emit(ring, pf | pipesrc);
8500
8501         intel_mark_page_flip_active(intel_crtc);
8502         __intel_ring_advance(ring);
8503         return 0;
8504
8505 err_unpin:
8506         intel_unpin_fb_obj(obj);
8507 err:
8508         return ret;
8509 }
8510
8511 static int intel_gen7_queue_flip(struct drm_device *dev,
8512                                  struct drm_crtc *crtc,
8513                                  struct drm_framebuffer *fb,
8514                                  struct drm_i915_gem_object *obj,
8515                                  uint32_t flags)
8516 {
8517         struct drm_i915_private *dev_priv = dev->dev_private;
8518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8519         struct intel_ring_buffer *ring;
8520         uint32_t plane_bit = 0;
8521         int len, ret;
8522
8523         ring = obj->ring;
8524         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8525                 ring = &dev_priv->ring[BCS];
8526
8527         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8528         if (ret)
8529                 goto err;
8530
8531         switch(intel_crtc->plane) {
8532         case PLANE_A:
8533                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8534                 break;
8535         case PLANE_B:
8536                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8537                 break;
8538         case PLANE_C:
8539                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8540                 break;
8541         default:
8542                 WARN_ONCE(1, "unknown plane in flip command\n");
8543                 ret = -ENODEV;
8544                 goto err_unpin;
8545         }
8546
8547         len = 4;
8548         if (ring->id == RCS)
8549                 len += 6;
8550
8551         ret = intel_ring_begin(ring, len);
8552         if (ret)
8553                 goto err_unpin;
8554
8555         /* Unmask the flip-done completion message. Note that the bspec says that
8556          * we should do this for both the BCS and RCS, and that we must not unmask
8557          * more than one flip event at any time (or ensure that one flip message
8558          * can be sent by waiting for flip-done prior to queueing new flips).
8559          * Experimentation says that BCS works despite DERRMR masking all
8560          * flip-done completion events and that unmasking all planes at once
8561          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8562          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8563          */
8564         if (ring->id == RCS) {
8565                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8566                 intel_ring_emit(ring, DERRMR);
8567                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8568                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8569                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8570                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8571                 intel_ring_emit(ring, DERRMR);
8572                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8573         }
8574
8575         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8576         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8577         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8578         intel_ring_emit(ring, (MI_NOOP));
8579
8580         intel_mark_page_flip_active(intel_crtc);
8581         __intel_ring_advance(ring);
8582         return 0;
8583
8584 err_unpin:
8585         intel_unpin_fb_obj(obj);
8586 err:
8587         return ret;
8588 }
8589
8590 static int intel_default_queue_flip(struct drm_device *dev,
8591                                     struct drm_crtc *crtc,
8592                                     struct drm_framebuffer *fb,
8593                                     struct drm_i915_gem_object *obj,
8594                                     uint32_t flags)
8595 {
8596         return -ENODEV;
8597 }
8598
8599 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8600                                 struct drm_framebuffer *fb,
8601                                 struct drm_pending_vblank_event *event,
8602                                 uint32_t page_flip_flags)
8603 {
8604         struct drm_device *dev = crtc->dev;
8605         struct drm_i915_private *dev_priv = dev->dev_private;
8606         struct drm_framebuffer *old_fb = crtc->fb;
8607         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8609         struct intel_unpin_work *work;
8610         unsigned long flags;
8611         int ret;
8612
8613         /* Can't change pixel format via MI display flips. */
8614         if (fb->pixel_format != crtc->fb->pixel_format)
8615                 return -EINVAL;
8616
8617         /*
8618          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8619          * Note that pitch changes could also affect these register.
8620          */
8621         if (INTEL_INFO(dev)->gen > 3 &&
8622             (fb->offsets[0] != crtc->fb->offsets[0] ||
8623              fb->pitches[0] != crtc->fb->pitches[0]))
8624                 return -EINVAL;
8625
8626         work = kzalloc(sizeof(*work), GFP_KERNEL);
8627         if (work == NULL)
8628                 return -ENOMEM;
8629
8630         work->event = event;
8631         work->crtc = crtc;
8632         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8633         INIT_WORK(&work->work, intel_unpin_work_fn);
8634
8635         ret = drm_vblank_get(dev, intel_crtc->pipe);
8636         if (ret)
8637                 goto free_work;
8638
8639         /* We borrow the event spin lock for protecting unpin_work */
8640         spin_lock_irqsave(&dev->event_lock, flags);
8641         if (intel_crtc->unpin_work) {
8642                 spin_unlock_irqrestore(&dev->event_lock, flags);
8643                 kfree(work);
8644                 drm_vblank_put(dev, intel_crtc->pipe);
8645
8646                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8647                 return -EBUSY;
8648         }
8649         intel_crtc->unpin_work = work;
8650         spin_unlock_irqrestore(&dev->event_lock, flags);
8651
8652         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8653                 flush_workqueue(dev_priv->wq);
8654
8655         ret = i915_mutex_lock_interruptible(dev);
8656         if (ret)
8657                 goto cleanup;
8658
8659         /* Reference the objects for the scheduled work. */
8660         drm_gem_object_reference(&work->old_fb_obj->base);
8661         drm_gem_object_reference(&obj->base);
8662
8663         crtc->fb = fb;
8664
8665         work->pending_flip_obj = obj;
8666
8667         work->enable_stall_check = true;
8668
8669         atomic_inc(&intel_crtc->unpin_work_count);
8670         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8671
8672         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8673         if (ret)
8674                 goto cleanup_pending;
8675
8676         intel_disable_fbc(dev);
8677         intel_mark_fb_busy(obj, NULL);
8678         mutex_unlock(&dev->struct_mutex);
8679
8680         trace_i915_flip_request(intel_crtc->plane, obj);
8681
8682         return 0;
8683
8684 cleanup_pending:
8685         atomic_dec(&intel_crtc->unpin_work_count);
8686         crtc->fb = old_fb;
8687         drm_gem_object_unreference(&work->old_fb_obj->base);
8688         drm_gem_object_unreference(&obj->base);
8689         mutex_unlock(&dev->struct_mutex);
8690
8691 cleanup:
8692         spin_lock_irqsave(&dev->event_lock, flags);
8693         intel_crtc->unpin_work = NULL;
8694         spin_unlock_irqrestore(&dev->event_lock, flags);
8695
8696         drm_vblank_put(dev, intel_crtc->pipe);
8697 free_work:
8698         kfree(work);
8699
8700         return ret;
8701 }
8702
8703 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8704         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8705         .load_lut = intel_crtc_load_lut,
8706 };
8707
8708 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8709                                   struct drm_crtc *crtc)
8710 {
8711         struct drm_device *dev;
8712         struct drm_crtc *tmp;
8713         int crtc_mask = 1;
8714
8715         WARN(!crtc, "checking null crtc?\n");
8716
8717         dev = crtc->dev;
8718
8719         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8720                 if (tmp == crtc)
8721                         break;
8722                 crtc_mask <<= 1;
8723         }
8724
8725         if (encoder->possible_crtcs & crtc_mask)
8726                 return true;
8727         return false;
8728 }
8729
8730 /**
8731  * intel_modeset_update_staged_output_state
8732  *
8733  * Updates the staged output configuration state, e.g. after we've read out the
8734  * current hw state.
8735  */
8736 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8737 {
8738         struct intel_encoder *encoder;
8739         struct intel_connector *connector;
8740
8741         list_for_each_entry(connector, &dev->mode_config.connector_list,
8742                             base.head) {
8743                 connector->new_encoder =
8744                         to_intel_encoder(connector->base.encoder);
8745         }
8746
8747         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8748                             base.head) {
8749                 encoder->new_crtc =
8750                         to_intel_crtc(encoder->base.crtc);
8751         }
8752 }
8753
8754 /**
8755  * intel_modeset_commit_output_state
8756  *
8757  * This function copies the stage display pipe configuration to the real one.
8758  */
8759 static void intel_modeset_commit_output_state(struct drm_device *dev)
8760 {
8761         struct intel_encoder *encoder;
8762         struct intel_connector *connector;
8763
8764         list_for_each_entry(connector, &dev->mode_config.connector_list,
8765                             base.head) {
8766                 connector->base.encoder = &connector->new_encoder->base;
8767         }
8768
8769         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8770                             base.head) {
8771                 encoder->base.crtc = &encoder->new_crtc->base;
8772         }
8773 }
8774
8775 static void
8776 connected_sink_compute_bpp(struct intel_connector * connector,
8777                            struct intel_crtc_config *pipe_config)
8778 {
8779         int bpp = pipe_config->pipe_bpp;
8780
8781         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8782                 connector->base.base.id,
8783                 drm_get_connector_name(&connector->base));
8784
8785         /* Don't use an invalid EDID bpc value */
8786         if (connector->base.display_info.bpc &&
8787             connector->base.display_info.bpc * 3 < bpp) {
8788                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8789                               bpp, connector->base.display_info.bpc*3);
8790                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8791         }
8792
8793         /* Clamp bpp to 8 on screens without EDID 1.4 */
8794         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8795                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8796                               bpp);
8797                 pipe_config->pipe_bpp = 24;
8798         }
8799 }
8800
8801 static int
8802 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8803                           struct drm_framebuffer *fb,
8804                           struct intel_crtc_config *pipe_config)
8805 {
8806         struct drm_device *dev = crtc->base.dev;
8807         struct intel_connector *connector;
8808         int bpp;
8809
8810         switch (fb->pixel_format) {
8811         case DRM_FORMAT_C8:
8812                 bpp = 8*3; /* since we go through a colormap */
8813                 break;
8814         case DRM_FORMAT_XRGB1555:
8815         case DRM_FORMAT_ARGB1555:
8816                 /* checked in intel_framebuffer_init already */
8817                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8818                         return -EINVAL;
8819         case DRM_FORMAT_RGB565:
8820                 bpp = 6*3; /* min is 18bpp */
8821                 break;
8822         case DRM_FORMAT_XBGR8888:
8823         case DRM_FORMAT_ABGR8888:
8824                 /* checked in intel_framebuffer_init already */
8825                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8826                         return -EINVAL;
8827         case DRM_FORMAT_XRGB8888:
8828         case DRM_FORMAT_ARGB8888:
8829                 bpp = 8*3;
8830                 break;
8831         case DRM_FORMAT_XRGB2101010:
8832         case DRM_FORMAT_ARGB2101010:
8833         case DRM_FORMAT_XBGR2101010:
8834         case DRM_FORMAT_ABGR2101010:
8835                 /* checked in intel_framebuffer_init already */
8836                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8837                         return -EINVAL;
8838                 bpp = 10*3;
8839                 break;
8840         /* TODO: gen4+ supports 16 bpc floating point, too. */
8841         default:
8842                 DRM_DEBUG_KMS("unsupported depth\n");
8843                 return -EINVAL;
8844         }
8845
8846         pipe_config->pipe_bpp = bpp;
8847
8848         /* Clamp display bpp to EDID value */
8849         list_for_each_entry(connector, &dev->mode_config.connector_list,
8850                             base.head) {
8851                 if (!connector->new_encoder ||
8852                     connector->new_encoder->new_crtc != crtc)
8853                         continue;
8854
8855                 connected_sink_compute_bpp(connector, pipe_config);
8856         }
8857
8858         return bpp;
8859 }
8860
8861 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8862 {
8863         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8864                         "type: 0x%x flags: 0x%x\n",
8865                 mode->crtc_clock,
8866                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8867                 mode->crtc_hsync_end, mode->crtc_htotal,
8868                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8869                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8870 }
8871
8872 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8873                                    struct intel_crtc_config *pipe_config,
8874                                    const char *context)
8875 {
8876         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8877                       context, pipe_name(crtc->pipe));
8878
8879         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8880         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8881                       pipe_config->pipe_bpp, pipe_config->dither);
8882         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8883                       pipe_config->has_pch_encoder,
8884                       pipe_config->fdi_lanes,
8885                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8886                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8887                       pipe_config->fdi_m_n.tu);
8888         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8889                       pipe_config->has_dp_encoder,
8890                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8891                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8892                       pipe_config->dp_m_n.tu);
8893         DRM_DEBUG_KMS("requested mode:\n");
8894         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8895         DRM_DEBUG_KMS("adjusted mode:\n");
8896         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8897         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8898         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8899         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8900                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8901         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8902                       pipe_config->gmch_pfit.control,
8903                       pipe_config->gmch_pfit.pgm_ratios,
8904                       pipe_config->gmch_pfit.lvds_border_bits);
8905         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8906                       pipe_config->pch_pfit.pos,
8907                       pipe_config->pch_pfit.size,
8908                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8909         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8910         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8911 }
8912
8913 static bool check_encoder_cloning(struct drm_crtc *crtc)
8914 {
8915         int num_encoders = 0;
8916         bool uncloneable_encoders = false;
8917         struct intel_encoder *encoder;
8918
8919         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8920                             base.head) {
8921                 if (&encoder->new_crtc->base != crtc)
8922                         continue;
8923
8924                 num_encoders++;
8925                 if (!encoder->cloneable)
8926                         uncloneable_encoders = true;
8927         }
8928
8929         return !(num_encoders > 1 && uncloneable_encoders);
8930 }
8931
8932 static struct intel_crtc_config *
8933 intel_modeset_pipe_config(struct drm_crtc *crtc,
8934                           struct drm_framebuffer *fb,
8935                           struct drm_display_mode *mode)
8936 {
8937         struct drm_device *dev = crtc->dev;
8938         struct intel_encoder *encoder;
8939         struct intel_crtc_config *pipe_config;
8940         int plane_bpp, ret = -EINVAL;
8941         bool retry = true;
8942
8943         if (!check_encoder_cloning(crtc)) {
8944                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8945                 return ERR_PTR(-EINVAL);
8946         }
8947
8948         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8949         if (!pipe_config)
8950                 return ERR_PTR(-ENOMEM);
8951
8952         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8953         drm_mode_copy(&pipe_config->requested_mode, mode);
8954
8955         pipe_config->cpu_transcoder =
8956                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8957         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8958
8959         /*
8960          * Sanitize sync polarity flags based on requested ones. If neither
8961          * positive or negative polarity is requested, treat this as meaning
8962          * negative polarity.
8963          */
8964         if (!(pipe_config->adjusted_mode.flags &
8965               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8966                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8967
8968         if (!(pipe_config->adjusted_mode.flags &
8969               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8970                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8971
8972         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8973          * plane pixel format and any sink constraints into account. Returns the
8974          * source plane bpp so that dithering can be selected on mismatches
8975          * after encoders and crtc also have had their say. */
8976         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8977                                               fb, pipe_config);
8978         if (plane_bpp < 0)
8979                 goto fail;
8980
8981         /*
8982          * Determine the real pipe dimensions. Note that stereo modes can
8983          * increase the actual pipe size due to the frame doubling and
8984          * insertion of additional space for blanks between the frame. This
8985          * is stored in the crtc timings. We use the requested mode to do this
8986          * computation to clearly distinguish it from the adjusted mode, which
8987          * can be changed by the connectors in the below retry loop.
8988          */
8989         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8990         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8991         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8992
8993 encoder_retry:
8994         /* Ensure the port clock defaults are reset when retrying. */
8995         pipe_config->port_clock = 0;
8996         pipe_config->pixel_multiplier = 1;
8997
8998         /* Fill in default crtc timings, allow encoders to overwrite them. */
8999         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9000
9001         /* Pass our mode to the connectors and the CRTC to give them a chance to
9002          * adjust it according to limitations or connector properties, and also
9003          * a chance to reject the mode entirely.
9004          */
9005         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9006                             base.head) {
9007
9008                 if (&encoder->new_crtc->base != crtc)
9009                         continue;
9010
9011                 if (!(encoder->compute_config(encoder, pipe_config))) {
9012                         DRM_DEBUG_KMS("Encoder config failure\n");
9013                         goto fail;
9014                 }
9015         }
9016
9017         /* Set default port clock if not overwritten by the encoder. Needs to be
9018          * done afterwards in case the encoder adjusts the mode. */
9019         if (!pipe_config->port_clock)
9020                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9021                         * pipe_config->pixel_multiplier;
9022
9023         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9024         if (ret < 0) {
9025                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9026                 goto fail;
9027         }
9028
9029         if (ret == RETRY) {
9030                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9031                         ret = -EINVAL;
9032                         goto fail;
9033                 }
9034
9035                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9036                 retry = false;
9037                 goto encoder_retry;
9038         }
9039
9040         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9041         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9042                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9043
9044         return pipe_config;
9045 fail:
9046         kfree(pipe_config);
9047         return ERR_PTR(ret);
9048 }
9049
9050 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9051  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9052 static void
9053 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9054                              unsigned *prepare_pipes, unsigned *disable_pipes)
9055 {
9056         struct intel_crtc *intel_crtc;
9057         struct drm_device *dev = crtc->dev;
9058         struct intel_encoder *encoder;
9059         struct intel_connector *connector;
9060         struct drm_crtc *tmp_crtc;
9061
9062         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9063
9064         /* Check which crtcs have changed outputs connected to them, these need
9065          * to be part of the prepare_pipes mask. We don't (yet) support global
9066          * modeset across multiple crtcs, so modeset_pipes will only have one
9067          * bit set at most. */
9068         list_for_each_entry(connector, &dev->mode_config.connector_list,
9069                             base.head) {
9070                 if (connector->base.encoder == &connector->new_encoder->base)
9071                         continue;
9072
9073                 if (connector->base.encoder) {
9074                         tmp_crtc = connector->base.encoder->crtc;
9075
9076                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9077                 }
9078
9079                 if (connector->new_encoder)
9080                         *prepare_pipes |=
9081                                 1 << connector->new_encoder->new_crtc->pipe;
9082         }
9083
9084         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9085                             base.head) {
9086                 if (encoder->base.crtc == &encoder->new_crtc->base)
9087                         continue;
9088
9089                 if (encoder->base.crtc) {
9090                         tmp_crtc = encoder->base.crtc;
9091
9092                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9093                 }
9094
9095                 if (encoder->new_crtc)
9096                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9097         }
9098
9099         /* Check for any pipes that will be fully disabled ... */
9100         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9101                             base.head) {
9102                 bool used = false;
9103
9104                 /* Don't try to disable disabled crtcs. */
9105                 if (!intel_crtc->base.enabled)
9106                         continue;
9107
9108                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9109                                     base.head) {
9110                         if (encoder->new_crtc == intel_crtc)
9111                                 used = true;
9112                 }
9113
9114                 if (!used)
9115                         *disable_pipes |= 1 << intel_crtc->pipe;
9116         }
9117
9118
9119         /* set_mode is also used to update properties on life display pipes. */
9120         intel_crtc = to_intel_crtc(crtc);
9121         if (crtc->enabled)
9122                 *prepare_pipes |= 1 << intel_crtc->pipe;
9123
9124         /*
9125          * For simplicity do a full modeset on any pipe where the output routing
9126          * changed. We could be more clever, but that would require us to be
9127          * more careful with calling the relevant encoder->mode_set functions.
9128          */
9129         if (*prepare_pipes)
9130                 *modeset_pipes = *prepare_pipes;
9131
9132         /* ... and mask these out. */
9133         *modeset_pipes &= ~(*disable_pipes);
9134         *prepare_pipes &= ~(*disable_pipes);
9135
9136         /*
9137          * HACK: We don't (yet) fully support global modesets. intel_set_config
9138          * obies this rule, but the modeset restore mode of
9139          * intel_modeset_setup_hw_state does not.
9140          */
9141         *modeset_pipes &= 1 << intel_crtc->pipe;
9142         *prepare_pipes &= 1 << intel_crtc->pipe;
9143
9144         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9145                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9146 }
9147
9148 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9149 {
9150         struct drm_encoder *encoder;
9151         struct drm_device *dev = crtc->dev;
9152
9153         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9154                 if (encoder->crtc == crtc)
9155                         return true;
9156
9157         return false;
9158 }
9159
9160 static void
9161 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9162 {
9163         struct intel_encoder *intel_encoder;
9164         struct intel_crtc *intel_crtc;
9165         struct drm_connector *connector;
9166
9167         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9168                             base.head) {
9169                 if (!intel_encoder->base.crtc)
9170                         continue;
9171
9172                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9173
9174                 if (prepare_pipes & (1 << intel_crtc->pipe))
9175                         intel_encoder->connectors_active = false;
9176         }
9177
9178         intel_modeset_commit_output_state(dev);
9179
9180         /* Update computed state. */
9181         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9182                             base.head) {
9183                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9184         }
9185
9186         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9187                 if (!connector->encoder || !connector->encoder->crtc)
9188                         continue;
9189
9190                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9191
9192                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9193                         struct drm_property *dpms_property =
9194                                 dev->mode_config.dpms_property;
9195
9196                         connector->dpms = DRM_MODE_DPMS_ON;
9197                         drm_object_property_set_value(&connector->base,
9198                                                          dpms_property,
9199                                                          DRM_MODE_DPMS_ON);
9200
9201                         intel_encoder = to_intel_encoder(connector->encoder);
9202                         intel_encoder->connectors_active = true;
9203                 }
9204         }
9205
9206 }
9207
9208 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9209 {
9210         int diff;
9211
9212         if (clock1 == clock2)
9213                 return true;
9214
9215         if (!clock1 || !clock2)
9216                 return false;
9217
9218         diff = abs(clock1 - clock2);
9219
9220         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9221                 return true;
9222
9223         return false;
9224 }
9225
9226 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9227         list_for_each_entry((intel_crtc), \
9228                             &(dev)->mode_config.crtc_list, \
9229                             base.head) \
9230                 if (mask & (1 <<(intel_crtc)->pipe))
9231
9232 static bool
9233 intel_pipe_config_compare(struct drm_device *dev,
9234                           struct intel_crtc_config *current_config,
9235                           struct intel_crtc_config *pipe_config)
9236 {
9237 #define PIPE_CONF_CHECK_X(name) \
9238         if (current_config->name != pipe_config->name) { \
9239                 DRM_ERROR("mismatch in " #name " " \
9240                           "(expected 0x%08x, found 0x%08x)\n", \
9241                           current_config->name, \
9242                           pipe_config->name); \
9243                 return false; \
9244         }
9245
9246 #define PIPE_CONF_CHECK_I(name) \
9247         if (current_config->name != pipe_config->name) { \
9248                 DRM_ERROR("mismatch in " #name " " \
9249                           "(expected %i, found %i)\n", \
9250                           current_config->name, \
9251                           pipe_config->name); \
9252                 return false; \
9253         }
9254
9255 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9256         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9257                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9258                           "(expected %i, found %i)\n", \
9259                           current_config->name & (mask), \
9260                           pipe_config->name & (mask)); \
9261                 return false; \
9262         }
9263
9264 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9265         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9266                 DRM_ERROR("mismatch in " #name " " \
9267                           "(expected %i, found %i)\n", \
9268                           current_config->name, \
9269                           pipe_config->name); \
9270                 return false; \
9271         }
9272
9273 #define PIPE_CONF_QUIRK(quirk)  \
9274         ((current_config->quirks | pipe_config->quirks) & (quirk))
9275
9276         PIPE_CONF_CHECK_I(cpu_transcoder);
9277
9278         PIPE_CONF_CHECK_I(has_pch_encoder);
9279         PIPE_CONF_CHECK_I(fdi_lanes);
9280         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9281         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9282         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9283         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9284         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9285
9286         PIPE_CONF_CHECK_I(has_dp_encoder);
9287         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9288         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9289         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9290         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9291         PIPE_CONF_CHECK_I(dp_m_n.tu);
9292
9293         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9294         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9295         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9296         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9297         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9298         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9299
9300         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9301         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9302         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9303         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9304         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9305         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9306
9307         PIPE_CONF_CHECK_I(pixel_multiplier);
9308
9309         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9310                               DRM_MODE_FLAG_INTERLACE);
9311
9312         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9313                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9314                                       DRM_MODE_FLAG_PHSYNC);
9315                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9316                                       DRM_MODE_FLAG_NHSYNC);
9317                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9318                                       DRM_MODE_FLAG_PVSYNC);
9319                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9320                                       DRM_MODE_FLAG_NVSYNC);
9321         }
9322
9323         PIPE_CONF_CHECK_I(pipe_src_w);
9324         PIPE_CONF_CHECK_I(pipe_src_h);
9325
9326         PIPE_CONF_CHECK_I(gmch_pfit.control);
9327         /* pfit ratios are autocomputed by the hw on gen4+ */
9328         if (INTEL_INFO(dev)->gen < 4)
9329                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9330         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9331         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9332         if (current_config->pch_pfit.enabled) {
9333                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9334                 PIPE_CONF_CHECK_I(pch_pfit.size);
9335         }
9336
9337         /* BDW+ don't expose a synchronous way to read the state */
9338         if (IS_HASWELL(dev))
9339                 PIPE_CONF_CHECK_I(ips_enabled);
9340
9341         PIPE_CONF_CHECK_I(double_wide);
9342
9343         PIPE_CONF_CHECK_I(shared_dpll);
9344         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9345         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9346         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9347         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9348
9349         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9350                 PIPE_CONF_CHECK_I(pipe_bpp);
9351
9352         if (!IS_HASWELL(dev)) {
9353                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9354                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9355         }
9356
9357 #undef PIPE_CONF_CHECK_X
9358 #undef PIPE_CONF_CHECK_I
9359 #undef PIPE_CONF_CHECK_FLAGS
9360 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9361 #undef PIPE_CONF_QUIRK
9362
9363         return true;
9364 }
9365
9366 static void
9367 check_connector_state(struct drm_device *dev)
9368 {
9369         struct intel_connector *connector;
9370
9371         list_for_each_entry(connector, &dev->mode_config.connector_list,
9372                             base.head) {
9373                 /* This also checks the encoder/connector hw state with the
9374                  * ->get_hw_state callbacks. */
9375                 intel_connector_check_state(connector);
9376
9377                 WARN(&connector->new_encoder->base != connector->base.encoder,
9378                      "connector's staged encoder doesn't match current encoder\n");
9379         }
9380 }
9381
9382 static void
9383 check_encoder_state(struct drm_device *dev)
9384 {
9385         struct intel_encoder *encoder;
9386         struct intel_connector *connector;
9387
9388         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9389                             base.head) {
9390                 bool enabled = false;
9391                 bool active = false;
9392                 enum pipe pipe, tracked_pipe;
9393
9394                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9395                               encoder->base.base.id,
9396                               drm_get_encoder_name(&encoder->base));
9397
9398                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9399                      "encoder's stage crtc doesn't match current crtc\n");
9400                 WARN(encoder->connectors_active && !encoder->base.crtc,
9401                      "encoder's active_connectors set, but no crtc\n");
9402
9403                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9404                                     base.head) {
9405                         if (connector->base.encoder != &encoder->base)
9406                                 continue;
9407                         enabled = true;
9408                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9409                                 active = true;
9410                 }
9411                 WARN(!!encoder->base.crtc != enabled,
9412                      "encoder's enabled state mismatch "
9413                      "(expected %i, found %i)\n",
9414                      !!encoder->base.crtc, enabled);
9415                 WARN(active && !encoder->base.crtc,
9416                      "active encoder with no crtc\n");
9417
9418                 WARN(encoder->connectors_active != active,
9419                      "encoder's computed active state doesn't match tracked active state "
9420                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9421
9422                 active = encoder->get_hw_state(encoder, &pipe);
9423                 WARN(active != encoder->connectors_active,
9424                      "encoder's hw state doesn't match sw tracking "
9425                      "(expected %i, found %i)\n",
9426                      encoder->connectors_active, active);
9427
9428                 if (!encoder->base.crtc)
9429                         continue;
9430
9431                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9432                 WARN(active && pipe != tracked_pipe,
9433                      "active encoder's pipe doesn't match"
9434                      "(expected %i, found %i)\n",
9435                      tracked_pipe, pipe);
9436
9437         }
9438 }
9439
9440 static void
9441 check_crtc_state(struct drm_device *dev)
9442 {
9443         drm_i915_private_t *dev_priv = dev->dev_private;
9444         struct intel_crtc *crtc;
9445         struct intel_encoder *encoder;
9446         struct intel_crtc_config pipe_config;
9447
9448         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9449                             base.head) {
9450                 bool enabled = false;
9451                 bool active = false;
9452
9453                 memset(&pipe_config, 0, sizeof(pipe_config));
9454
9455                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9456                               crtc->base.base.id);
9457
9458                 WARN(crtc->active && !crtc->base.enabled,
9459                      "active crtc, but not enabled in sw tracking\n");
9460
9461                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9462                                     base.head) {
9463                         if (encoder->base.crtc != &crtc->base)
9464                                 continue;
9465                         enabled = true;
9466                         if (encoder->connectors_active)
9467                                 active = true;
9468                 }
9469
9470                 WARN(active != crtc->active,
9471                      "crtc's computed active state doesn't match tracked active state "
9472                      "(expected %i, found %i)\n", active, crtc->active);
9473                 WARN(enabled != crtc->base.enabled,
9474                      "crtc's computed enabled state doesn't match tracked enabled state "
9475                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9476
9477                 active = dev_priv->display.get_pipe_config(crtc,
9478                                                            &pipe_config);
9479
9480                 /* hw state is inconsistent with the pipe A quirk */
9481                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9482                         active = crtc->active;
9483
9484                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9485                                     base.head) {
9486                         enum pipe pipe;
9487                         if (encoder->base.crtc != &crtc->base)
9488                                 continue;
9489                         if (encoder->get_hw_state(encoder, &pipe))
9490                                 encoder->get_config(encoder, &pipe_config);
9491                 }
9492
9493                 WARN(crtc->active != active,
9494                      "crtc active state doesn't match with hw state "
9495                      "(expected %i, found %i)\n", crtc->active, active);
9496
9497                 if (active &&
9498                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9499                         WARN(1, "pipe state doesn't match!\n");
9500                         intel_dump_pipe_config(crtc, &pipe_config,
9501                                                "[hw state]");
9502                         intel_dump_pipe_config(crtc, &crtc->config,
9503                                                "[sw state]");
9504                 }
9505         }
9506 }
9507
9508 static void
9509 check_shared_dpll_state(struct drm_device *dev)
9510 {
9511         drm_i915_private_t *dev_priv = dev->dev_private;
9512         struct intel_crtc *crtc;
9513         struct intel_dpll_hw_state dpll_hw_state;
9514         int i;
9515
9516         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9517                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9518                 int enabled_crtcs = 0, active_crtcs = 0;
9519                 bool active;
9520
9521                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9522
9523                 DRM_DEBUG_KMS("%s\n", pll->name);
9524
9525                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9526
9527                 WARN(pll->active > pll->refcount,
9528                      "more active pll users than references: %i vs %i\n",
9529                      pll->active, pll->refcount);
9530                 WARN(pll->active && !pll->on,
9531                      "pll in active use but not on in sw tracking\n");
9532                 WARN(pll->on && !pll->active,
9533                      "pll in on but not on in use in sw tracking\n");
9534                 WARN(pll->on != active,
9535                      "pll on state mismatch (expected %i, found %i)\n",
9536                      pll->on, active);
9537
9538                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9539                                     base.head) {
9540                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9541                                 enabled_crtcs++;
9542                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9543                                 active_crtcs++;
9544                 }
9545                 WARN(pll->active != active_crtcs,
9546                      "pll active crtcs mismatch (expected %i, found %i)\n",
9547                      pll->active, active_crtcs);
9548                 WARN(pll->refcount != enabled_crtcs,
9549                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9550                      pll->refcount, enabled_crtcs);
9551
9552                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9553                                        sizeof(dpll_hw_state)),
9554                      "pll hw state mismatch\n");
9555         }
9556 }
9557
9558 void
9559 intel_modeset_check_state(struct drm_device *dev)
9560 {
9561         check_connector_state(dev);
9562         check_encoder_state(dev);
9563         check_crtc_state(dev);
9564         check_shared_dpll_state(dev);
9565 }
9566
9567 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9568                                      int dotclock)
9569 {
9570         /*
9571          * FDI already provided one idea for the dotclock.
9572          * Yell if the encoder disagrees.
9573          */
9574         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9575              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9576              pipe_config->adjusted_mode.crtc_clock, dotclock);
9577 }
9578
9579 static int __intel_set_mode(struct drm_crtc *crtc,
9580                             struct drm_display_mode *mode,
9581                             int x, int y, struct drm_framebuffer *fb)
9582 {
9583         struct drm_device *dev = crtc->dev;
9584         drm_i915_private_t *dev_priv = dev->dev_private;
9585         struct drm_display_mode *saved_mode, *saved_hwmode;
9586         struct intel_crtc_config *pipe_config = NULL;
9587         struct intel_crtc *intel_crtc;
9588         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9589         int ret = 0;
9590
9591         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9592         if (!saved_mode)
9593                 return -ENOMEM;
9594         saved_hwmode = saved_mode + 1;
9595
9596         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9597                                      &prepare_pipes, &disable_pipes);
9598
9599         *saved_hwmode = crtc->hwmode;
9600         *saved_mode = crtc->mode;
9601
9602         /* Hack: Because we don't (yet) support global modeset on multiple
9603          * crtcs, we don't keep track of the new mode for more than one crtc.
9604          * Hence simply check whether any bit is set in modeset_pipes in all the
9605          * pieces of code that are not yet converted to deal with mutliple crtcs
9606          * changing their mode at the same time. */
9607         if (modeset_pipes) {
9608                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9609                 if (IS_ERR(pipe_config)) {
9610                         ret = PTR_ERR(pipe_config);
9611                         pipe_config = NULL;
9612
9613                         goto out;
9614                 }
9615                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9616                                        "[modeset]");
9617         }
9618
9619         /*
9620          * See if the config requires any additional preparation, e.g.
9621          * to adjust global state with pipes off.  We need to do this
9622          * here so we can get the modeset_pipe updated config for the new
9623          * mode set on this crtc.  For other crtcs we need to use the
9624          * adjusted_mode bits in the crtc directly.
9625          */
9626         if (IS_VALLEYVIEW(dev)) {
9627                 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9628                                                 modeset_pipes, pipe_config);
9629
9630                 /* may have added more to prepare_pipes than we should */
9631                 prepare_pipes &= ~disable_pipes;
9632         }
9633
9634         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9635                 intel_crtc_disable(&intel_crtc->base);
9636
9637         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9638                 if (intel_crtc->base.enabled)
9639                         dev_priv->display.crtc_disable(&intel_crtc->base);
9640         }
9641
9642         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9643          * to set it here already despite that we pass it down the callchain.
9644          */
9645         if (modeset_pipes) {
9646                 crtc->mode = *mode;
9647                 /* mode_set/enable/disable functions rely on a correct pipe
9648                  * config. */
9649                 to_intel_crtc(crtc)->config = *pipe_config;
9650         }
9651
9652         /* Only after disabling all output pipelines that will be changed can we
9653          * update the the output configuration. */
9654         intel_modeset_update_state(dev, prepare_pipes);
9655
9656         if (dev_priv->display.modeset_global_resources)
9657                 dev_priv->display.modeset_global_resources(dev);
9658
9659         /* Set up the DPLL and any encoders state that needs to adjust or depend
9660          * on the DPLL.
9661          */
9662         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9663                 ret = intel_crtc_mode_set(&intel_crtc->base,
9664                                           x, y, fb);
9665                 if (ret)
9666                         goto done;
9667         }
9668
9669         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9670         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9671                 dev_priv->display.crtc_enable(&intel_crtc->base);
9672
9673         if (modeset_pipes) {
9674                 /* Store real post-adjustment hardware mode. */
9675                 crtc->hwmode = pipe_config->adjusted_mode;
9676
9677                 /* Calculate and store various constants which
9678                  * are later needed by vblank and swap-completion
9679                  * timestamping. They are derived from true hwmode.
9680                  */
9681                 drm_calc_timestamping_constants(crtc);
9682         }
9683
9684         /* FIXME: add subpixel order */
9685 done:
9686         if (ret && crtc->enabled) {
9687                 crtc->hwmode = *saved_hwmode;
9688                 crtc->mode = *saved_mode;
9689         }
9690
9691 out:
9692         kfree(pipe_config);
9693         kfree(saved_mode);
9694         return ret;
9695 }
9696
9697 static int intel_set_mode(struct drm_crtc *crtc,
9698                           struct drm_display_mode *mode,
9699                           int x, int y, struct drm_framebuffer *fb)
9700 {
9701         int ret;
9702
9703         ret = __intel_set_mode(crtc, mode, x, y, fb);
9704
9705         if (ret == 0)
9706                 intel_modeset_check_state(crtc->dev);
9707
9708         return ret;
9709 }
9710
9711 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9712 {
9713         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9714 }
9715
9716 #undef for_each_intel_crtc_masked
9717
9718 static void intel_set_config_free(struct intel_set_config *config)
9719 {
9720         if (!config)
9721                 return;
9722
9723         kfree(config->save_connector_encoders);
9724         kfree(config->save_encoder_crtcs);
9725         kfree(config);
9726 }
9727
9728 static int intel_set_config_save_state(struct drm_device *dev,
9729                                        struct intel_set_config *config)
9730 {
9731         struct drm_encoder *encoder;
9732         struct drm_connector *connector;
9733         int count;
9734
9735         config->save_encoder_crtcs =
9736                 kcalloc(dev->mode_config.num_encoder,
9737                         sizeof(struct drm_crtc *), GFP_KERNEL);
9738         if (!config->save_encoder_crtcs)
9739                 return -ENOMEM;
9740
9741         config->save_connector_encoders =
9742                 kcalloc(dev->mode_config.num_connector,
9743                         sizeof(struct drm_encoder *), GFP_KERNEL);
9744         if (!config->save_connector_encoders)
9745                 return -ENOMEM;
9746
9747         /* Copy data. Note that driver private data is not affected.
9748          * Should anything bad happen only the expected state is
9749          * restored, not the drivers personal bookkeeping.
9750          */
9751         count = 0;
9752         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9753                 config->save_encoder_crtcs[count++] = encoder->crtc;
9754         }
9755
9756         count = 0;
9757         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9758                 config->save_connector_encoders[count++] = connector->encoder;
9759         }
9760
9761         return 0;
9762 }
9763
9764 static void intel_set_config_restore_state(struct drm_device *dev,
9765                                            struct intel_set_config *config)
9766 {
9767         struct intel_encoder *encoder;
9768         struct intel_connector *connector;
9769         int count;
9770
9771         count = 0;
9772         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9773                 encoder->new_crtc =
9774                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9775         }
9776
9777         count = 0;
9778         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9779                 connector->new_encoder =
9780                         to_intel_encoder(config->save_connector_encoders[count++]);
9781         }
9782 }
9783
9784 static bool
9785 is_crtc_connector_off(struct drm_mode_set *set)
9786 {
9787         int i;
9788
9789         if (set->num_connectors == 0)
9790                 return false;
9791
9792         if (WARN_ON(set->connectors == NULL))
9793                 return false;
9794
9795         for (i = 0; i < set->num_connectors; i++)
9796                 if (set->connectors[i]->encoder &&
9797                     set->connectors[i]->encoder->crtc == set->crtc &&
9798                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9799                         return true;
9800
9801         return false;
9802 }
9803
9804 static void
9805 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9806                                       struct intel_set_config *config)
9807 {
9808
9809         /* We should be able to check here if the fb has the same properties
9810          * and then just flip_or_move it */
9811         if (is_crtc_connector_off(set)) {
9812                 config->mode_changed = true;
9813         } else if (set->crtc->fb != set->fb) {
9814                 /* If we have no fb then treat it as a full mode set */
9815                 if (set->crtc->fb == NULL) {
9816                         struct intel_crtc *intel_crtc =
9817                                 to_intel_crtc(set->crtc);
9818
9819                         if (intel_crtc->active && i915_fastboot) {
9820                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9821                                 config->fb_changed = true;
9822                         } else {
9823                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9824                                 config->mode_changed = true;
9825                         }
9826                 } else if (set->fb == NULL) {
9827                         config->mode_changed = true;
9828                 } else if (set->fb->pixel_format !=
9829                            set->crtc->fb->pixel_format) {
9830                         config->mode_changed = true;
9831                 } else {
9832                         config->fb_changed = true;
9833                 }
9834         }
9835
9836         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9837                 config->fb_changed = true;
9838
9839         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9840                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9841                 drm_mode_debug_printmodeline(&set->crtc->mode);
9842                 drm_mode_debug_printmodeline(set->mode);
9843                 config->mode_changed = true;
9844         }
9845
9846         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9847                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9848 }
9849
9850 static int
9851 intel_modeset_stage_output_state(struct drm_device *dev,
9852                                  struct drm_mode_set *set,
9853                                  struct intel_set_config *config)
9854 {
9855         struct drm_crtc *new_crtc;
9856         struct intel_connector *connector;
9857         struct intel_encoder *encoder;
9858         int ro;
9859
9860         /* The upper layers ensure that we either disable a crtc or have a list
9861          * of connectors. For paranoia, double-check this. */
9862         WARN_ON(!set->fb && (set->num_connectors != 0));
9863         WARN_ON(set->fb && (set->num_connectors == 0));
9864
9865         list_for_each_entry(connector, &dev->mode_config.connector_list,
9866                             base.head) {
9867                 /* Otherwise traverse passed in connector list and get encoders
9868                  * for them. */
9869                 for (ro = 0; ro < set->num_connectors; ro++) {
9870                         if (set->connectors[ro] == &connector->base) {
9871                                 connector->new_encoder = connector->encoder;
9872                                 break;
9873                         }
9874                 }
9875
9876                 /* If we disable the crtc, disable all its connectors. Also, if
9877                  * the connector is on the changing crtc but not on the new
9878                  * connector list, disable it. */
9879                 if ((!set->fb || ro == set->num_connectors) &&
9880                     connector->base.encoder &&
9881                     connector->base.encoder->crtc == set->crtc) {
9882                         connector->new_encoder = NULL;
9883
9884                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9885                                 connector->base.base.id,
9886                                 drm_get_connector_name(&connector->base));
9887                 }
9888
9889
9890                 if (&connector->new_encoder->base != connector->base.encoder) {
9891                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9892                         config->mode_changed = true;
9893                 }
9894         }
9895         /* connector->new_encoder is now updated for all connectors. */
9896
9897         /* Update crtc of enabled connectors. */
9898         list_for_each_entry(connector, &dev->mode_config.connector_list,
9899                             base.head) {
9900                 if (!connector->new_encoder)
9901                         continue;
9902
9903                 new_crtc = connector->new_encoder->base.crtc;
9904
9905                 for (ro = 0; ro < set->num_connectors; ro++) {
9906                         if (set->connectors[ro] == &connector->base)
9907                                 new_crtc = set->crtc;
9908                 }
9909
9910                 /* Make sure the new CRTC will work with the encoder */
9911                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9912                                            new_crtc)) {
9913                         return -EINVAL;
9914                 }
9915                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9916
9917                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9918                         connector->base.base.id,
9919                         drm_get_connector_name(&connector->base),
9920                         new_crtc->base.id);
9921         }
9922
9923         /* Check for any encoders that needs to be disabled. */
9924         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9925                             base.head) {
9926                 list_for_each_entry(connector,
9927                                     &dev->mode_config.connector_list,
9928                                     base.head) {
9929                         if (connector->new_encoder == encoder) {
9930                                 WARN_ON(!connector->new_encoder->new_crtc);
9931
9932                                 goto next_encoder;
9933                         }
9934                 }
9935                 encoder->new_crtc = NULL;
9936 next_encoder:
9937                 /* Only now check for crtc changes so we don't miss encoders
9938                  * that will be disabled. */
9939                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9940                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9941                         config->mode_changed = true;
9942                 }
9943         }
9944         /* Now we've also updated encoder->new_crtc for all encoders. */
9945
9946         return 0;
9947 }
9948
9949 static int intel_crtc_set_config(struct drm_mode_set *set)
9950 {
9951         struct drm_device *dev;
9952         struct drm_mode_set save_set;
9953         struct intel_set_config *config;
9954         int ret;
9955
9956         BUG_ON(!set);
9957         BUG_ON(!set->crtc);
9958         BUG_ON(!set->crtc->helper_private);
9959
9960         /* Enforce sane interface api - has been abused by the fb helper. */
9961         BUG_ON(!set->mode && set->fb);
9962         BUG_ON(set->fb && set->num_connectors == 0);
9963
9964         if (set->fb) {
9965                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9966                                 set->crtc->base.id, set->fb->base.id,
9967                                 (int)set->num_connectors, set->x, set->y);
9968         } else {
9969                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9970         }
9971
9972         dev = set->crtc->dev;
9973
9974         ret = -ENOMEM;
9975         config = kzalloc(sizeof(*config), GFP_KERNEL);
9976         if (!config)
9977                 goto out_config;
9978
9979         ret = intel_set_config_save_state(dev, config);
9980         if (ret)
9981                 goto out_config;
9982
9983         save_set.crtc = set->crtc;
9984         save_set.mode = &set->crtc->mode;
9985         save_set.x = set->crtc->x;
9986         save_set.y = set->crtc->y;
9987         save_set.fb = set->crtc->fb;
9988
9989         /* Compute whether we need a full modeset, only an fb base update or no
9990          * change at all. In the future we might also check whether only the
9991          * mode changed, e.g. for LVDS where we only change the panel fitter in
9992          * such cases. */
9993         intel_set_config_compute_mode_changes(set, config);
9994
9995         ret = intel_modeset_stage_output_state(dev, set, config);
9996         if (ret)
9997                 goto fail;
9998
9999         if (config->mode_changed) {
10000                 ret = intel_set_mode(set->crtc, set->mode,
10001                                      set->x, set->y, set->fb);
10002         } else if (config->fb_changed) {
10003                 intel_crtc_wait_for_pending_flips(set->crtc);
10004
10005                 ret = intel_pipe_set_base(set->crtc,
10006                                           set->x, set->y, set->fb);
10007                 /*
10008                  * In the fastboot case this may be our only check of the
10009                  * state after boot.  It would be better to only do it on
10010                  * the first update, but we don't have a nice way of doing that
10011                  * (and really, set_config isn't used much for high freq page
10012                  * flipping, so increasing its cost here shouldn't be a big
10013                  * deal).
10014                  */
10015                 if (i915_fastboot && ret == 0)
10016                         intel_modeset_check_state(set->crtc->dev);
10017         }
10018
10019         if (ret) {
10020                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10021                               set->crtc->base.id, ret);
10022 fail:
10023                 intel_set_config_restore_state(dev, config);
10024
10025                 /* Try to restore the config */
10026                 if (config->mode_changed &&
10027                     intel_set_mode(save_set.crtc, save_set.mode,
10028                                    save_set.x, save_set.y, save_set.fb))
10029                         DRM_ERROR("failed to restore config after modeset failure\n");
10030         }
10031
10032 out_config:
10033         intel_set_config_free(config);
10034         return ret;
10035 }
10036
10037 static const struct drm_crtc_funcs intel_crtc_funcs = {
10038         .cursor_set = intel_crtc_cursor_set,
10039         .cursor_move = intel_crtc_cursor_move,
10040         .gamma_set = intel_crtc_gamma_set,
10041         .set_config = intel_crtc_set_config,
10042         .destroy = intel_crtc_destroy,
10043         .page_flip = intel_crtc_page_flip,
10044 };
10045
10046 static void intel_cpu_pll_init(struct drm_device *dev)
10047 {
10048         if (HAS_DDI(dev))
10049                 intel_ddi_pll_init(dev);
10050 }
10051
10052 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10053                                       struct intel_shared_dpll *pll,
10054                                       struct intel_dpll_hw_state *hw_state)
10055 {
10056         uint32_t val;
10057
10058         val = I915_READ(PCH_DPLL(pll->id));
10059         hw_state->dpll = val;
10060         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10061         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10062
10063         return val & DPLL_VCO_ENABLE;
10064 }
10065
10066 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10067                                   struct intel_shared_dpll *pll)
10068 {
10069         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10070         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10071 }
10072
10073 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10074                                 struct intel_shared_dpll *pll)
10075 {
10076         /* PCH refclock must be enabled first */
10077         ibx_assert_pch_refclk_enabled(dev_priv);
10078
10079         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10080
10081         /* Wait for the clocks to stabilize. */
10082         POSTING_READ(PCH_DPLL(pll->id));
10083         udelay(150);
10084
10085         /* The pixel multiplier can only be updated once the
10086          * DPLL is enabled and the clocks are stable.
10087          *
10088          * So write it again.
10089          */
10090         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10091         POSTING_READ(PCH_DPLL(pll->id));
10092         udelay(200);
10093 }
10094
10095 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10096                                  struct intel_shared_dpll *pll)
10097 {
10098         struct drm_device *dev = dev_priv->dev;
10099         struct intel_crtc *crtc;
10100
10101         /* Make sure no transcoder isn't still depending on us. */
10102         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10103                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10104                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10105         }
10106
10107         I915_WRITE(PCH_DPLL(pll->id), 0);
10108         POSTING_READ(PCH_DPLL(pll->id));
10109         udelay(200);
10110 }
10111
10112 static char *ibx_pch_dpll_names[] = {
10113         "PCH DPLL A",
10114         "PCH DPLL B",
10115 };
10116
10117 static void ibx_pch_dpll_init(struct drm_device *dev)
10118 {
10119         struct drm_i915_private *dev_priv = dev->dev_private;
10120         int i;
10121
10122         dev_priv->num_shared_dpll = 2;
10123
10124         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10125                 dev_priv->shared_dplls[i].id = i;
10126                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10127                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10128                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10129                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10130                 dev_priv->shared_dplls[i].get_hw_state =
10131                         ibx_pch_dpll_get_hw_state;
10132         }
10133 }
10134
10135 static void intel_shared_dpll_init(struct drm_device *dev)
10136 {
10137         struct drm_i915_private *dev_priv = dev->dev_private;
10138
10139         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10140                 ibx_pch_dpll_init(dev);
10141         else
10142                 dev_priv->num_shared_dpll = 0;
10143
10144         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10145 }
10146
10147 static void intel_crtc_init(struct drm_device *dev, int pipe)
10148 {
10149         drm_i915_private_t *dev_priv = dev->dev_private;
10150         struct intel_crtc *intel_crtc;
10151         int i;
10152
10153         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10154         if (intel_crtc == NULL)
10155                 return;
10156
10157         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10158
10159         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10160         for (i = 0; i < 256; i++) {
10161                 intel_crtc->lut_r[i] = i;
10162                 intel_crtc->lut_g[i] = i;
10163                 intel_crtc->lut_b[i] = i;
10164         }
10165
10166         /*
10167          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10168          * is hooked to plane B. Hence we want plane A feeding pipe B.
10169          */
10170         intel_crtc->pipe = pipe;
10171         intel_crtc->plane = pipe;
10172         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10173                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10174                 intel_crtc->plane = !pipe;
10175         }
10176
10177         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10178                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10179         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10180         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10181
10182         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10183 }
10184
10185 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10186 {
10187         struct drm_encoder *encoder = connector->base.encoder;
10188
10189         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10190
10191         if (!encoder)
10192                 return INVALID_PIPE;
10193
10194         return to_intel_crtc(encoder->crtc)->pipe;
10195 }
10196
10197 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10198                                 struct drm_file *file)
10199 {
10200         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10201         struct drm_mode_object *drmmode_obj;
10202         struct intel_crtc *crtc;
10203
10204         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10205                 return -ENODEV;
10206
10207         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10208                         DRM_MODE_OBJECT_CRTC);
10209
10210         if (!drmmode_obj) {
10211                 DRM_ERROR("no such CRTC id\n");
10212                 return -ENOENT;
10213         }
10214
10215         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10216         pipe_from_crtc_id->pipe = crtc->pipe;
10217
10218         return 0;
10219 }
10220
10221 static int intel_encoder_clones(struct intel_encoder *encoder)
10222 {
10223         struct drm_device *dev = encoder->base.dev;
10224         struct intel_encoder *source_encoder;
10225         int index_mask = 0;
10226         int entry = 0;
10227
10228         list_for_each_entry(source_encoder,
10229                             &dev->mode_config.encoder_list, base.head) {
10230
10231                 if (encoder == source_encoder)
10232                         index_mask |= (1 << entry);
10233
10234                 /* Intel hw has only one MUX where enocoders could be cloned. */
10235                 if (encoder->cloneable && source_encoder->cloneable)
10236                         index_mask |= (1 << entry);
10237
10238                 entry++;
10239         }
10240
10241         return index_mask;
10242 }
10243
10244 static bool has_edp_a(struct drm_device *dev)
10245 {
10246         struct drm_i915_private *dev_priv = dev->dev_private;
10247
10248         if (!IS_MOBILE(dev))
10249                 return false;
10250
10251         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10252                 return false;
10253
10254         if (IS_GEN5(dev) &&
10255             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10256                 return false;
10257
10258         return true;
10259 }
10260
10261 static void intel_setup_outputs(struct drm_device *dev)
10262 {
10263         struct drm_i915_private *dev_priv = dev->dev_private;
10264         struct intel_encoder *encoder;
10265         bool dpd_is_edp = false;
10266
10267         intel_lvds_init(dev);
10268
10269         if (!IS_ULT(dev))
10270                 intel_crt_init(dev);
10271
10272         if (HAS_DDI(dev)) {
10273                 int found;
10274
10275                 /* Haswell uses DDI functions to detect digital outputs */
10276                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10277                 /* DDI A only supports eDP */
10278                 if (found)
10279                         intel_ddi_init(dev, PORT_A);
10280
10281                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10282                  * register */
10283                 found = I915_READ(SFUSE_STRAP);
10284
10285                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10286                         intel_ddi_init(dev, PORT_B);
10287                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10288                         intel_ddi_init(dev, PORT_C);
10289                 if (found & SFUSE_STRAP_DDID_DETECTED)
10290                         intel_ddi_init(dev, PORT_D);
10291         } else if (HAS_PCH_SPLIT(dev)) {
10292                 int found;
10293                 dpd_is_edp = intel_dpd_is_edp(dev);
10294
10295                 if (has_edp_a(dev))
10296                         intel_dp_init(dev, DP_A, PORT_A);
10297
10298                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10299                         /* PCH SDVOB multiplex with HDMIB */
10300                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10301                         if (!found)
10302                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10303                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10304                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10305                 }
10306
10307                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10308                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10309
10310                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10311                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10312
10313                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10314                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10315
10316                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10317                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10318         } else if (IS_VALLEYVIEW(dev)) {
10319                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10320                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10321                                         PORT_B);
10322                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10323                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10324                 }
10325
10326                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10327                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10328                                         PORT_C);
10329                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10330                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10331                                               PORT_C);
10332                 }
10333
10334                 intel_dsi_init(dev);
10335         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10336                 bool found = false;
10337
10338                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10339                         DRM_DEBUG_KMS("probing SDVOB\n");
10340                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10341                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10342                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10343                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10344                         }
10345
10346                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10347                                 intel_dp_init(dev, DP_B, PORT_B);
10348                 }
10349
10350                 /* Before G4X SDVOC doesn't have its own detect register */
10351
10352                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10353                         DRM_DEBUG_KMS("probing SDVOC\n");
10354                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10355                 }
10356
10357                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10358
10359                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10360                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10361                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10362                         }
10363                         if (SUPPORTS_INTEGRATED_DP(dev))
10364                                 intel_dp_init(dev, DP_C, PORT_C);
10365                 }
10366
10367                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10368                     (I915_READ(DP_D) & DP_DETECTED))
10369                         intel_dp_init(dev, DP_D, PORT_D);
10370         } else if (IS_GEN2(dev))
10371                 intel_dvo_init(dev);
10372
10373         if (SUPPORTS_TV(dev))
10374                 intel_tv_init(dev);
10375
10376         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10377                 encoder->base.possible_crtcs = encoder->crtc_mask;
10378                 encoder->base.possible_clones =
10379                         intel_encoder_clones(encoder);
10380         }
10381
10382         intel_init_pch_refclk(dev);
10383
10384         drm_helper_move_panel_connectors_to_head(dev);
10385 }
10386
10387 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10388 {
10389         drm_framebuffer_cleanup(&fb->base);
10390         WARN_ON(!fb->obj->framebuffer_references--);
10391         drm_gem_object_unreference_unlocked(&fb->obj->base);
10392 }
10393
10394 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10395 {
10396         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10397
10398         intel_framebuffer_fini(intel_fb);
10399         kfree(intel_fb);
10400 }
10401
10402 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10403                                                 struct drm_file *file,
10404                                                 unsigned int *handle)
10405 {
10406         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10407         struct drm_i915_gem_object *obj = intel_fb->obj;
10408
10409         return drm_gem_handle_create(file, &obj->base, handle);
10410 }
10411
10412 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10413         .destroy = intel_user_framebuffer_destroy,
10414         .create_handle = intel_user_framebuffer_create_handle,
10415 };
10416
10417 int intel_framebuffer_init(struct drm_device *dev,
10418                            struct intel_framebuffer *intel_fb,
10419                            struct drm_mode_fb_cmd2 *mode_cmd,
10420                            struct drm_i915_gem_object *obj)
10421 {
10422         int aligned_height, tile_height;
10423         int pitch_limit;
10424         int ret;
10425
10426         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10427
10428         if (obj->tiling_mode == I915_TILING_Y) {
10429                 DRM_DEBUG("hardware does not support tiling Y\n");
10430                 return -EINVAL;
10431         }
10432
10433         if (mode_cmd->pitches[0] & 63) {
10434                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10435                           mode_cmd->pitches[0]);
10436                 return -EINVAL;
10437         }
10438
10439         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10440                 pitch_limit = 32*1024;
10441         } else if (INTEL_INFO(dev)->gen >= 4) {
10442                 if (obj->tiling_mode)
10443                         pitch_limit = 16*1024;
10444                 else
10445                         pitch_limit = 32*1024;
10446         } else if (INTEL_INFO(dev)->gen >= 3) {
10447                 if (obj->tiling_mode)
10448                         pitch_limit = 8*1024;
10449                 else
10450                         pitch_limit = 16*1024;
10451         } else
10452                 /* XXX DSPC is limited to 4k tiled */
10453                 pitch_limit = 8*1024;
10454
10455         if (mode_cmd->pitches[0] > pitch_limit) {
10456                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10457                           obj->tiling_mode ? "tiled" : "linear",
10458                           mode_cmd->pitches[0], pitch_limit);
10459                 return -EINVAL;
10460         }
10461
10462         if (obj->tiling_mode != I915_TILING_NONE &&
10463             mode_cmd->pitches[0] != obj->stride) {
10464                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10465                           mode_cmd->pitches[0], obj->stride);
10466                 return -EINVAL;
10467         }
10468
10469         /* Reject formats not supported by any plane early. */
10470         switch (mode_cmd->pixel_format) {
10471         case DRM_FORMAT_C8:
10472         case DRM_FORMAT_RGB565:
10473         case DRM_FORMAT_XRGB8888:
10474         case DRM_FORMAT_ARGB8888:
10475                 break;
10476         case DRM_FORMAT_XRGB1555:
10477         case DRM_FORMAT_ARGB1555:
10478                 if (INTEL_INFO(dev)->gen > 3) {
10479                         DRM_DEBUG("unsupported pixel format: %s\n",
10480                                   drm_get_format_name(mode_cmd->pixel_format));
10481                         return -EINVAL;
10482                 }
10483                 break;
10484         case DRM_FORMAT_XBGR8888:
10485         case DRM_FORMAT_ABGR8888:
10486         case DRM_FORMAT_XRGB2101010:
10487         case DRM_FORMAT_ARGB2101010:
10488         case DRM_FORMAT_XBGR2101010:
10489         case DRM_FORMAT_ABGR2101010:
10490                 if (INTEL_INFO(dev)->gen < 4) {
10491                         DRM_DEBUG("unsupported pixel format: %s\n",
10492                                   drm_get_format_name(mode_cmd->pixel_format));
10493                         return -EINVAL;
10494                 }
10495                 break;
10496         case DRM_FORMAT_YUYV:
10497         case DRM_FORMAT_UYVY:
10498         case DRM_FORMAT_YVYU:
10499         case DRM_FORMAT_VYUY:
10500                 if (INTEL_INFO(dev)->gen < 5) {
10501                         DRM_DEBUG("unsupported pixel format: %s\n",
10502                                   drm_get_format_name(mode_cmd->pixel_format));
10503                         return -EINVAL;
10504                 }
10505                 break;
10506         default:
10507                 DRM_DEBUG("unsupported pixel format: %s\n",
10508                           drm_get_format_name(mode_cmd->pixel_format));
10509                 return -EINVAL;
10510         }
10511
10512         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10513         if (mode_cmd->offsets[0] != 0)
10514                 return -EINVAL;
10515
10516         tile_height = IS_GEN2(dev) ? 16 : 8;
10517         aligned_height = ALIGN(mode_cmd->height,
10518                                obj->tiling_mode ? tile_height : 1);
10519         /* FIXME drm helper for size checks (especially planar formats)? */
10520         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10521                 return -EINVAL;
10522
10523         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10524         intel_fb->obj = obj;
10525         intel_fb->obj->framebuffer_references++;
10526
10527         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10528         if (ret) {
10529                 DRM_ERROR("framebuffer init failed %d\n", ret);
10530                 return ret;
10531         }
10532
10533         return 0;
10534 }
10535
10536 static struct drm_framebuffer *
10537 intel_user_framebuffer_create(struct drm_device *dev,
10538                               struct drm_file *filp,
10539                               struct drm_mode_fb_cmd2 *mode_cmd)
10540 {
10541         struct drm_i915_gem_object *obj;
10542
10543         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10544                                                 mode_cmd->handles[0]));
10545         if (&obj->base == NULL)
10546                 return ERR_PTR(-ENOENT);
10547
10548         return intel_framebuffer_create(dev, mode_cmd, obj);
10549 }
10550
10551 #ifndef CONFIG_DRM_I915_FBDEV
10552 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10553 {
10554 }
10555 #endif
10556
10557 static const struct drm_mode_config_funcs intel_mode_funcs = {
10558         .fb_create = intel_user_framebuffer_create,
10559         .output_poll_changed = intel_fbdev_output_poll_changed,
10560 };
10561
10562 /* Set up chip specific display functions */
10563 static void intel_init_display(struct drm_device *dev)
10564 {
10565         struct drm_i915_private *dev_priv = dev->dev_private;
10566
10567         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10568                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10569         else if (IS_VALLEYVIEW(dev))
10570                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10571         else if (IS_PINEVIEW(dev))
10572                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10573         else
10574                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10575
10576         if (HAS_DDI(dev)) {
10577                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10578                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10579                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10580                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10581                 dev_priv->display.off = haswell_crtc_off;
10582                 dev_priv->display.update_plane = ironlake_update_plane;
10583         } else if (HAS_PCH_SPLIT(dev)) {
10584                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10585                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10586                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10587                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10588                 dev_priv->display.off = ironlake_crtc_off;
10589                 dev_priv->display.update_plane = ironlake_update_plane;
10590         } else if (IS_VALLEYVIEW(dev)) {
10591                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10592                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10593                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10594                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10595                 dev_priv->display.off = i9xx_crtc_off;
10596                 dev_priv->display.update_plane = i9xx_update_plane;
10597         } else {
10598                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10599                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10600                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10601                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10602                 dev_priv->display.off = i9xx_crtc_off;
10603                 dev_priv->display.update_plane = i9xx_update_plane;
10604         }
10605
10606         /* Returns the core display clock speed */
10607         if (IS_VALLEYVIEW(dev))
10608                 dev_priv->display.get_display_clock_speed =
10609                         valleyview_get_display_clock_speed;
10610         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10611                 dev_priv->display.get_display_clock_speed =
10612                         i945_get_display_clock_speed;
10613         else if (IS_I915G(dev))
10614                 dev_priv->display.get_display_clock_speed =
10615                         i915_get_display_clock_speed;
10616         else if (IS_I945GM(dev) || IS_845G(dev))
10617                 dev_priv->display.get_display_clock_speed =
10618                         i9xx_misc_get_display_clock_speed;
10619         else if (IS_PINEVIEW(dev))
10620                 dev_priv->display.get_display_clock_speed =
10621                         pnv_get_display_clock_speed;
10622         else if (IS_I915GM(dev))
10623                 dev_priv->display.get_display_clock_speed =
10624                         i915gm_get_display_clock_speed;
10625         else if (IS_I865G(dev))
10626                 dev_priv->display.get_display_clock_speed =
10627                         i865_get_display_clock_speed;
10628         else if (IS_I85X(dev))
10629                 dev_priv->display.get_display_clock_speed =
10630                         i855_get_display_clock_speed;
10631         else /* 852, 830 */
10632                 dev_priv->display.get_display_clock_speed =
10633                         i830_get_display_clock_speed;
10634
10635         if (HAS_PCH_SPLIT(dev)) {
10636                 if (IS_GEN5(dev)) {
10637                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10638                         dev_priv->display.write_eld = ironlake_write_eld;
10639                 } else if (IS_GEN6(dev)) {
10640                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10641                         dev_priv->display.write_eld = ironlake_write_eld;
10642                 } else if (IS_IVYBRIDGE(dev)) {
10643                         /* FIXME: detect B0+ stepping and use auto training */
10644                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10645                         dev_priv->display.write_eld = ironlake_write_eld;
10646                         dev_priv->display.modeset_global_resources =
10647                                 ivb_modeset_global_resources;
10648                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10649                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10650                         dev_priv->display.write_eld = haswell_write_eld;
10651                         dev_priv->display.modeset_global_resources =
10652                                 haswell_modeset_global_resources;
10653                 }
10654         } else if (IS_G4X(dev)) {
10655                 dev_priv->display.write_eld = g4x_write_eld;
10656         } else if (IS_VALLEYVIEW(dev)) {
10657                 dev_priv->display.modeset_global_resources =
10658                         valleyview_modeset_global_resources;
10659                 dev_priv->display.write_eld = ironlake_write_eld;
10660         }
10661
10662         /* Default just returns -ENODEV to indicate unsupported */
10663         dev_priv->display.queue_flip = intel_default_queue_flip;
10664
10665         switch (INTEL_INFO(dev)->gen) {
10666         case 2:
10667                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10668                 break;
10669
10670         case 3:
10671                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10672                 break;
10673
10674         case 4:
10675         case 5:
10676                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10677                 break;
10678
10679         case 6:
10680                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10681                 break;
10682         case 7:
10683         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10684                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10685                 break;
10686         }
10687
10688         intel_panel_init_backlight_funcs(dev);
10689 }
10690
10691 /*
10692  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10693  * resume, or other times.  This quirk makes sure that's the case for
10694  * affected systems.
10695  */
10696 static void quirk_pipea_force(struct drm_device *dev)
10697 {
10698         struct drm_i915_private *dev_priv = dev->dev_private;
10699
10700         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10701         DRM_INFO("applying pipe a force quirk\n");
10702 }
10703
10704 /*
10705  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10706  */
10707 static void quirk_ssc_force_disable(struct drm_device *dev)
10708 {
10709         struct drm_i915_private *dev_priv = dev->dev_private;
10710         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10711         DRM_INFO("applying lvds SSC disable quirk\n");
10712 }
10713
10714 /*
10715  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10716  * brightness value
10717  */
10718 static void quirk_invert_brightness(struct drm_device *dev)
10719 {
10720         struct drm_i915_private *dev_priv = dev->dev_private;
10721         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10722         DRM_INFO("applying inverted panel brightness quirk\n");
10723 }
10724
10725 struct intel_quirk {
10726         int device;
10727         int subsystem_vendor;
10728         int subsystem_device;
10729         void (*hook)(struct drm_device *dev);
10730 };
10731
10732 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10733 struct intel_dmi_quirk {
10734         void (*hook)(struct drm_device *dev);
10735         const struct dmi_system_id (*dmi_id_list)[];
10736 };
10737
10738 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10739 {
10740         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10741         return 1;
10742 }
10743
10744 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10745         {
10746                 .dmi_id_list = &(const struct dmi_system_id[]) {
10747                         {
10748                                 .callback = intel_dmi_reverse_brightness,
10749                                 .ident = "NCR Corporation",
10750                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10751                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10752                                 },
10753                         },
10754                         { }  /* terminating entry */
10755                 },
10756                 .hook = quirk_invert_brightness,
10757         },
10758 };
10759
10760 static struct intel_quirk intel_quirks[] = {
10761         /* HP Mini needs pipe A force quirk (LP: #322104) */
10762         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10763
10764         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10765         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10766
10767         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10768         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10769
10770         /* 830 needs to leave pipe A & dpll A up */
10771         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10772
10773         /* Lenovo U160 cannot use SSC on LVDS */
10774         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10775
10776         /* Sony Vaio Y cannot use SSC on LVDS */
10777         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10778
10779         /*
10780          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10781          * seem to use inverted backlight PWM.
10782          */
10783         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10784 };
10785
10786 static void intel_init_quirks(struct drm_device *dev)
10787 {
10788         struct pci_dev *d = dev->pdev;
10789         int i;
10790
10791         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10792                 struct intel_quirk *q = &intel_quirks[i];
10793
10794                 if (d->device == q->device &&
10795                     (d->subsystem_vendor == q->subsystem_vendor ||
10796                      q->subsystem_vendor == PCI_ANY_ID) &&
10797                     (d->subsystem_device == q->subsystem_device ||
10798                      q->subsystem_device == PCI_ANY_ID))
10799                         q->hook(dev);
10800         }
10801         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10802                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10803                         intel_dmi_quirks[i].hook(dev);
10804         }
10805 }
10806
10807 /* Disable the VGA plane that we never use */
10808 static void i915_disable_vga(struct drm_device *dev)
10809 {
10810         struct drm_i915_private *dev_priv = dev->dev_private;
10811         u8 sr1;
10812         u32 vga_reg = i915_vgacntrl_reg(dev);
10813
10814         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10815         outb(SR01, VGA_SR_INDEX);
10816         sr1 = inb(VGA_SR_DATA);
10817         outb(sr1 | 1<<5, VGA_SR_DATA);
10818         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10819         udelay(300);
10820
10821         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10822         POSTING_READ(vga_reg);
10823 }
10824
10825 void intel_modeset_init_hw(struct drm_device *dev)
10826 {
10827         intel_prepare_ddi(dev);
10828
10829         intel_init_clock_gating(dev);
10830
10831         intel_reset_dpio(dev);
10832
10833         mutex_lock(&dev->struct_mutex);
10834         intel_enable_gt_powersave(dev);
10835         mutex_unlock(&dev->struct_mutex);
10836 }
10837
10838 void intel_modeset_suspend_hw(struct drm_device *dev)
10839 {
10840         intel_suspend_hw(dev);
10841 }
10842
10843 void intel_modeset_init(struct drm_device *dev)
10844 {
10845         struct drm_i915_private *dev_priv = dev->dev_private;
10846         int i, j, ret;
10847
10848         drm_mode_config_init(dev);
10849
10850         dev->mode_config.min_width = 0;
10851         dev->mode_config.min_height = 0;
10852
10853         dev->mode_config.preferred_depth = 24;
10854         dev->mode_config.prefer_shadow = 1;
10855
10856         dev->mode_config.funcs = &intel_mode_funcs;
10857
10858         intel_init_quirks(dev);
10859
10860         intel_init_pm(dev);
10861
10862         if (INTEL_INFO(dev)->num_pipes == 0)
10863                 return;
10864
10865         intel_init_display(dev);
10866
10867         if (IS_GEN2(dev)) {
10868                 dev->mode_config.max_width = 2048;
10869                 dev->mode_config.max_height = 2048;
10870         } else if (IS_GEN3(dev)) {
10871                 dev->mode_config.max_width = 4096;
10872                 dev->mode_config.max_height = 4096;
10873         } else {
10874                 dev->mode_config.max_width = 8192;
10875                 dev->mode_config.max_height = 8192;
10876         }
10877         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10878
10879         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10880                       INTEL_INFO(dev)->num_pipes,
10881                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10882
10883         for_each_pipe(i) {
10884                 intel_crtc_init(dev, i);
10885                 for (j = 0; j < dev_priv->num_plane; j++) {
10886                         ret = intel_plane_init(dev, i, j);
10887                         if (ret)
10888                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10889                                               pipe_name(i), sprite_name(i, j), ret);
10890                 }
10891         }
10892
10893         intel_init_dpio(dev);
10894         intel_reset_dpio(dev);
10895
10896         intel_cpu_pll_init(dev);
10897         intel_shared_dpll_init(dev);
10898
10899         /* Just disable it once at startup */
10900         i915_disable_vga(dev);
10901         intel_setup_outputs(dev);
10902
10903         /* Just in case the BIOS is doing something questionable. */
10904         intel_disable_fbc(dev);
10905 }
10906
10907 static void
10908 intel_connector_break_all_links(struct intel_connector *connector)
10909 {
10910         connector->base.dpms = DRM_MODE_DPMS_OFF;
10911         connector->base.encoder = NULL;
10912         connector->encoder->connectors_active = false;
10913         connector->encoder->base.crtc = NULL;
10914 }
10915
10916 static void intel_enable_pipe_a(struct drm_device *dev)
10917 {
10918         struct intel_connector *connector;
10919         struct drm_connector *crt = NULL;
10920         struct intel_load_detect_pipe load_detect_temp;
10921
10922         /* We can't just switch on the pipe A, we need to set things up with a
10923          * proper mode and output configuration. As a gross hack, enable pipe A
10924          * by enabling the load detect pipe once. */
10925         list_for_each_entry(connector,
10926                             &dev->mode_config.connector_list,
10927                             base.head) {
10928                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10929                         crt = &connector->base;
10930                         break;
10931                 }
10932         }
10933
10934         if (!crt)
10935                 return;
10936
10937         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10938                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10939
10940
10941 }
10942
10943 static bool
10944 intel_check_plane_mapping(struct intel_crtc *crtc)
10945 {
10946         struct drm_device *dev = crtc->base.dev;
10947         struct drm_i915_private *dev_priv = dev->dev_private;
10948         u32 reg, val;
10949
10950         if (INTEL_INFO(dev)->num_pipes == 1)
10951                 return true;
10952
10953         reg = DSPCNTR(!crtc->plane);
10954         val = I915_READ(reg);
10955
10956         if ((val & DISPLAY_PLANE_ENABLE) &&
10957             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10958                 return false;
10959
10960         return true;
10961 }
10962
10963 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10964 {
10965         struct drm_device *dev = crtc->base.dev;
10966         struct drm_i915_private *dev_priv = dev->dev_private;
10967         u32 reg;
10968
10969         /* Clear any frame start delays used for debugging left by the BIOS */
10970         reg = PIPECONF(crtc->config.cpu_transcoder);
10971         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10972
10973         /* We need to sanitize the plane -> pipe mapping first because this will
10974          * disable the crtc (and hence change the state) if it is wrong. Note
10975          * that gen4+ has a fixed plane -> pipe mapping.  */
10976         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10977                 struct intel_connector *connector;
10978                 bool plane;
10979
10980                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10981                               crtc->base.base.id);
10982
10983                 /* Pipe has the wrong plane attached and the plane is active.
10984                  * Temporarily change the plane mapping and disable everything
10985                  * ...  */
10986                 plane = crtc->plane;
10987                 crtc->plane = !plane;
10988                 dev_priv->display.crtc_disable(&crtc->base);
10989                 crtc->plane = plane;
10990
10991                 /* ... and break all links. */
10992                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10993                                     base.head) {
10994                         if (connector->encoder->base.crtc != &crtc->base)
10995                                 continue;
10996
10997                         intel_connector_break_all_links(connector);
10998                 }
10999
11000                 WARN_ON(crtc->active);
11001                 crtc->base.enabled = false;
11002         }
11003
11004         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11005             crtc->pipe == PIPE_A && !crtc->active) {
11006                 /* BIOS forgot to enable pipe A, this mostly happens after
11007                  * resume. Force-enable the pipe to fix this, the update_dpms
11008                  * call below we restore the pipe to the right state, but leave
11009                  * the required bits on. */
11010                 intel_enable_pipe_a(dev);
11011         }
11012
11013         /* Adjust the state of the output pipe according to whether we
11014          * have active connectors/encoders. */
11015         intel_crtc_update_dpms(&crtc->base);
11016
11017         if (crtc->active != crtc->base.enabled) {
11018                 struct intel_encoder *encoder;
11019
11020                 /* This can happen either due to bugs in the get_hw_state
11021                  * functions or because the pipe is force-enabled due to the
11022                  * pipe A quirk. */
11023                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11024                               crtc->base.base.id,
11025                               crtc->base.enabled ? "enabled" : "disabled",
11026                               crtc->active ? "enabled" : "disabled");
11027
11028                 crtc->base.enabled = crtc->active;
11029
11030                 /* Because we only establish the connector -> encoder ->
11031                  * crtc links if something is active, this means the
11032                  * crtc is now deactivated. Break the links. connector
11033                  * -> encoder links are only establish when things are
11034                  *  actually up, hence no need to break them. */
11035                 WARN_ON(crtc->active);
11036
11037                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11038                         WARN_ON(encoder->connectors_active);
11039                         encoder->base.crtc = NULL;
11040                 }
11041         }
11042 }
11043
11044 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11045 {
11046         struct intel_connector *connector;
11047         struct drm_device *dev = encoder->base.dev;
11048
11049         /* We need to check both for a crtc link (meaning that the
11050          * encoder is active and trying to read from a pipe) and the
11051          * pipe itself being active. */
11052         bool has_active_crtc = encoder->base.crtc &&
11053                 to_intel_crtc(encoder->base.crtc)->active;
11054
11055         if (encoder->connectors_active && !has_active_crtc) {
11056                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11057                               encoder->base.base.id,
11058                               drm_get_encoder_name(&encoder->base));
11059
11060                 /* Connector is active, but has no active pipe. This is
11061                  * fallout from our resume register restoring. Disable
11062                  * the encoder manually again. */
11063                 if (encoder->base.crtc) {
11064                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11065                                       encoder->base.base.id,
11066                                       drm_get_encoder_name(&encoder->base));
11067                         encoder->disable(encoder);
11068                 }
11069
11070                 /* Inconsistent output/port/pipe state happens presumably due to
11071                  * a bug in one of the get_hw_state functions. Or someplace else
11072                  * in our code, like the register restore mess on resume. Clamp
11073                  * things to off as a safer default. */
11074                 list_for_each_entry(connector,
11075                                     &dev->mode_config.connector_list,
11076                                     base.head) {
11077                         if (connector->encoder != encoder)
11078                                 continue;
11079
11080                         intel_connector_break_all_links(connector);
11081                 }
11082         }
11083         /* Enabled encoders without active connectors will be fixed in
11084          * the crtc fixup. */
11085 }
11086
11087 void i915_redisable_vga(struct drm_device *dev)
11088 {
11089         struct drm_i915_private *dev_priv = dev->dev_private;
11090         u32 vga_reg = i915_vgacntrl_reg(dev);
11091
11092         /* This function can be called both from intel_modeset_setup_hw_state or
11093          * at a very early point in our resume sequence, where the power well
11094          * structures are not yet restored. Since this function is at a very
11095          * paranoid "someone might have enabled VGA while we were not looking"
11096          * level, just check if the power well is enabled instead of trying to
11097          * follow the "don't touch the power well if we don't need it" policy
11098          * the rest of the driver uses. */
11099         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11100             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11101                 return;
11102
11103         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11104                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11105                 i915_disable_vga(dev);
11106         }
11107 }
11108
11109 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11110 {
11111         struct drm_i915_private *dev_priv = dev->dev_private;
11112         enum pipe pipe;
11113         struct intel_crtc *crtc;
11114         struct intel_encoder *encoder;
11115         struct intel_connector *connector;
11116         int i;
11117
11118         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11119                             base.head) {
11120                 memset(&crtc->config, 0, sizeof(crtc->config));
11121
11122                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11123                                                                  &crtc->config);
11124
11125                 crtc->base.enabled = crtc->active;
11126                 crtc->primary_enabled = crtc->active;
11127
11128                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11129                               crtc->base.base.id,
11130                               crtc->active ? "enabled" : "disabled");
11131         }
11132
11133         /* FIXME: Smash this into the new shared dpll infrastructure. */
11134         if (HAS_DDI(dev))
11135                 intel_ddi_setup_hw_pll_state(dev);
11136
11137         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11138                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11139
11140                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11141                 pll->active = 0;
11142                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11143                                     base.head) {
11144                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11145                                 pll->active++;
11146                 }
11147                 pll->refcount = pll->active;
11148
11149                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11150                               pll->name, pll->refcount, pll->on);
11151         }
11152
11153         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11154                             base.head) {
11155                 pipe = 0;
11156
11157                 if (encoder->get_hw_state(encoder, &pipe)) {
11158                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11159                         encoder->base.crtc = &crtc->base;
11160                         encoder->get_config(encoder, &crtc->config);
11161                 } else {
11162                         encoder->base.crtc = NULL;
11163                 }
11164
11165                 encoder->connectors_active = false;
11166                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11167                               encoder->base.base.id,
11168                               drm_get_encoder_name(&encoder->base),
11169                               encoder->base.crtc ? "enabled" : "disabled",
11170                               pipe_name(pipe));
11171         }
11172
11173         list_for_each_entry(connector, &dev->mode_config.connector_list,
11174                             base.head) {
11175                 if (connector->get_hw_state(connector)) {
11176                         connector->base.dpms = DRM_MODE_DPMS_ON;
11177                         connector->encoder->connectors_active = true;
11178                         connector->base.encoder = &connector->encoder->base;
11179                 } else {
11180                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11181                         connector->base.encoder = NULL;
11182                 }
11183                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11184                               connector->base.base.id,
11185                               drm_get_connector_name(&connector->base),
11186                               connector->base.encoder ? "enabled" : "disabled");
11187         }
11188 }
11189
11190 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11191  * and i915 state tracking structures. */
11192 void intel_modeset_setup_hw_state(struct drm_device *dev,
11193                                   bool force_restore)
11194 {
11195         struct drm_i915_private *dev_priv = dev->dev_private;
11196         enum pipe pipe;
11197         struct intel_crtc *crtc;
11198         struct intel_encoder *encoder;
11199         int i;
11200
11201         intel_modeset_readout_hw_state(dev);
11202
11203         /*
11204          * Now that we have the config, copy it to each CRTC struct
11205          * Note that this could go away if we move to using crtc_config
11206          * checking everywhere.
11207          */
11208         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11209                             base.head) {
11210                 if (crtc->active && i915_fastboot) {
11211                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11212
11213                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11214                                       crtc->base.base.id);
11215                         drm_mode_debug_printmodeline(&crtc->base.mode);
11216                 }
11217         }
11218
11219         /* HW state is read out, now we need to sanitize this mess. */
11220         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11221                             base.head) {
11222                 intel_sanitize_encoder(encoder);
11223         }
11224
11225         for_each_pipe(pipe) {
11226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11227                 intel_sanitize_crtc(crtc);
11228                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11229         }
11230
11231         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11232                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11233
11234                 if (!pll->on || pll->active)
11235                         continue;
11236
11237                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11238
11239                 pll->disable(dev_priv, pll);
11240                 pll->on = false;
11241         }
11242
11243         if (HAS_PCH_SPLIT(dev))
11244                 ilk_wm_get_hw_state(dev);
11245
11246         if (force_restore) {
11247                 i915_redisable_vga(dev);
11248
11249                 /*
11250                  * We need to use raw interfaces for restoring state to avoid
11251                  * checking (bogus) intermediate states.
11252                  */
11253                 for_each_pipe(pipe) {
11254                         struct drm_crtc *crtc =
11255                                 dev_priv->pipe_to_crtc_mapping[pipe];
11256
11257                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11258                                          crtc->fb);
11259                 }
11260         } else {
11261                 intel_modeset_update_staged_output_state(dev);
11262         }
11263
11264         intel_modeset_check_state(dev);
11265
11266         drm_mode_config_reset(dev);
11267 }
11268
11269 void intel_modeset_gem_init(struct drm_device *dev)
11270 {
11271         intel_modeset_init_hw(dev);
11272
11273         intel_setup_overlay(dev);
11274
11275         intel_modeset_setup_hw_state(dev, false);
11276 }
11277
11278 void intel_modeset_cleanup(struct drm_device *dev)
11279 {
11280         struct drm_i915_private *dev_priv = dev->dev_private;
11281         struct drm_crtc *crtc;
11282         struct drm_connector *connector;
11283
11284         /*
11285          * Interrupts and polling as the first thing to avoid creating havoc.
11286          * Too much stuff here (turning of rps, connectors, ...) would
11287          * experience fancy races otherwise.
11288          */
11289         drm_irq_uninstall(dev);
11290         cancel_work_sync(&dev_priv->hotplug_work);
11291         /*
11292          * Due to the hpd irq storm handling the hotplug work can re-arm the
11293          * poll handlers. Hence disable polling after hpd handling is shut down.
11294          */
11295         drm_kms_helper_poll_fini(dev);
11296
11297         mutex_lock(&dev->struct_mutex);
11298
11299         intel_unregister_dsm_handler();
11300
11301         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11302                 /* Skip inactive CRTCs */
11303                 if (!crtc->fb)
11304                         continue;
11305
11306                 intel_increase_pllclock(crtc);
11307         }
11308
11309         intel_disable_fbc(dev);
11310
11311         intel_disable_gt_powersave(dev);
11312
11313         ironlake_teardown_rc6(dev);
11314
11315         mutex_unlock(&dev->struct_mutex);
11316
11317         /* flush any delayed tasks or pending work */
11318         flush_scheduled_work();
11319
11320         /* destroy the backlight and sysfs files before encoders/connectors */
11321         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11322                 intel_panel_destroy_backlight(connector);
11323                 drm_sysfs_connector_remove(connector);
11324         }
11325
11326         drm_mode_config_cleanup(dev);
11327
11328         intel_cleanup_overlay(dev);
11329 }
11330
11331 /*
11332  * Return which encoder is currently attached for connector.
11333  */
11334 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11335 {
11336         return &intel_attached_encoder(connector)->base;
11337 }
11338
11339 void intel_connector_attach_encoder(struct intel_connector *connector,
11340                                     struct intel_encoder *encoder)
11341 {
11342         connector->encoder = encoder;
11343         drm_mode_connector_attach_encoder(&connector->base,
11344                                           &encoder->base);
11345 }
11346
11347 /*
11348  * set vga decode state - true == enable VGA decode
11349  */
11350 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11351 {
11352         struct drm_i915_private *dev_priv = dev->dev_private;
11353         u16 gmch_ctrl;
11354
11355         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11356         if (state)
11357                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11358         else
11359                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11360         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11361         return 0;
11362 }
11363
11364 struct intel_display_error_state {
11365
11366         u32 power_well_driver;
11367
11368         int num_transcoders;
11369
11370         struct intel_cursor_error_state {
11371                 u32 control;
11372                 u32 position;
11373                 u32 base;
11374                 u32 size;
11375         } cursor[I915_MAX_PIPES];
11376
11377         struct intel_pipe_error_state {
11378                 bool power_domain_on;
11379                 u32 source;
11380         } pipe[I915_MAX_PIPES];
11381
11382         struct intel_plane_error_state {
11383                 u32 control;
11384                 u32 stride;
11385                 u32 size;
11386                 u32 pos;
11387                 u32 addr;
11388                 u32 surface;
11389                 u32 tile_offset;
11390         } plane[I915_MAX_PIPES];
11391
11392         struct intel_transcoder_error_state {
11393                 bool power_domain_on;
11394                 enum transcoder cpu_transcoder;
11395
11396                 u32 conf;
11397
11398                 u32 htotal;
11399                 u32 hblank;
11400                 u32 hsync;
11401                 u32 vtotal;
11402                 u32 vblank;
11403                 u32 vsync;
11404         } transcoder[4];
11405 };
11406
11407 struct intel_display_error_state *
11408 intel_display_capture_error_state(struct drm_device *dev)
11409 {
11410         drm_i915_private_t *dev_priv = dev->dev_private;
11411         struct intel_display_error_state *error;
11412         int transcoders[] = {
11413                 TRANSCODER_A,
11414                 TRANSCODER_B,
11415                 TRANSCODER_C,
11416                 TRANSCODER_EDP,
11417         };
11418         int i;
11419
11420         if (INTEL_INFO(dev)->num_pipes == 0)
11421                 return NULL;
11422
11423         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11424         if (error == NULL)
11425                 return NULL;
11426
11427         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11428                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11429
11430         for_each_pipe(i) {
11431                 error->pipe[i].power_domain_on =
11432                         intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11433                 if (!error->pipe[i].power_domain_on)
11434                         continue;
11435
11436                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11437                         error->cursor[i].control = I915_READ(CURCNTR(i));
11438                         error->cursor[i].position = I915_READ(CURPOS(i));
11439                         error->cursor[i].base = I915_READ(CURBASE(i));
11440                 } else {
11441                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11442                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11443                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11444                 }
11445
11446                 error->plane[i].control = I915_READ(DSPCNTR(i));
11447                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11448                 if (INTEL_INFO(dev)->gen <= 3) {
11449                         error->plane[i].size = I915_READ(DSPSIZE(i));
11450                         error->plane[i].pos = I915_READ(DSPPOS(i));
11451                 }
11452                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11453                         error->plane[i].addr = I915_READ(DSPADDR(i));
11454                 if (INTEL_INFO(dev)->gen >= 4) {
11455                         error->plane[i].surface = I915_READ(DSPSURF(i));
11456                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11457                 }
11458
11459                 error->pipe[i].source = I915_READ(PIPESRC(i));
11460         }
11461
11462         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11463         if (HAS_DDI(dev_priv->dev))
11464                 error->num_transcoders++; /* Account for eDP. */
11465
11466         for (i = 0; i < error->num_transcoders; i++) {
11467                 enum transcoder cpu_transcoder = transcoders[i];
11468
11469                 error->transcoder[i].power_domain_on =
11470                         intel_display_power_enabled_sw(dev,
11471                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11472                 if (!error->transcoder[i].power_domain_on)
11473                         continue;
11474
11475                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11476
11477                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11478                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11479                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11480                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11481                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11482                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11483                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11484         }
11485
11486         return error;
11487 }
11488
11489 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11490
11491 void
11492 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11493                                 struct drm_device *dev,
11494                                 struct intel_display_error_state *error)
11495 {
11496         int i;
11497
11498         if (!error)
11499                 return;
11500
11501         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11502         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11503                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11504                            error->power_well_driver);
11505         for_each_pipe(i) {
11506                 err_printf(m, "Pipe [%d]:\n", i);
11507                 err_printf(m, "  Power: %s\n",
11508                            error->pipe[i].power_domain_on ? "on" : "off");
11509                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11510
11511                 err_printf(m, "Plane [%d]:\n", i);
11512                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11513                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11514                 if (INTEL_INFO(dev)->gen <= 3) {
11515                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11516                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11517                 }
11518                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11519                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11520                 if (INTEL_INFO(dev)->gen >= 4) {
11521                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11522                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11523                 }
11524
11525                 err_printf(m, "Cursor [%d]:\n", i);
11526                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11527                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11528                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11529         }
11530
11531         for (i = 0; i < error->num_transcoders; i++) {
11532                 err_printf(m, "CPU transcoder: %c\n",
11533                            transcoder_name(error->transcoder[i].cpu_transcoder));
11534                 err_printf(m, "  Power: %s\n",
11535                            error->transcoder[i].power_domain_on ? "on" : "off");
11536                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11537                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11538                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11539                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11540                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11541                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11542                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11543         }
11544 }