2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_pch_rawclk(struct drm_device *dev)
84 struct drm_i915_private *dev_priv = dev->dev_private;
86 WARN_ON(!HAS_PCH_SPLIT(dev));
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 8, .max = 18 },
158 .m2 = { .min = 3, .max = 7 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
194 .find_pll = intel_g4x_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
223 .find_pll = intel_g4x_find_best_PLL,
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
238 .find_pll = intel_g4x_find_best_PLL,
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
285 /* Ironlake / Sandybridge
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
435 val = I915_READ(DPIO_DATA);
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464 static void vlv_init_dpio(struct drm_device *dev)
466 struct drm_i915_private *dev_priv = dev->dev_private;
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 { } /* terminating entry */
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
502 if (dmi_check_system(intel_dual_link_lvds))
505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
513 val = I915_READ(reg);
514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 const intel_limit_t *limit;
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530 /* LVDS dual channel */
531 if (refclk == 100000)
532 limit = &intel_limits_ironlake_dual_lvds_100m;
534 limit = &intel_limits_ironlake_dual_lvds;
536 if (refclk == 100000)
537 limit = &intel_limits_ironlake_single_lvds_100m;
539 limit = &intel_limits_ironlake_single_lvds;
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543 limit = &intel_limits_ironlake_display_port;
545 limit = &intel_limits_ironlake_dac;
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 if (is_dual_link_lvds(dev_priv, LVDS))
558 /* LVDS with dual channel */
559 limit = &intel_limits_g4x_dual_channel_lvds;
561 /* LVDS with dual channel */
562 limit = &intel_limits_g4x_single_channel_lvds;
563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565 limit = &intel_limits_g4x_hdmi;
566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567 limit = &intel_limits_g4x_sdvo;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569 limit = &intel_limits_g4x_display_port;
570 } else /* The option is for other outputs */
571 limit = &intel_limits_i9xx_sdvo;
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
581 if (HAS_PCH_SPLIT(dev))
582 limit = intel_ironlake_limit(crtc, refclk);
583 else if (IS_G4X(dev)) {
584 limit = intel_g4x_limit(crtc);
585 } else if (IS_PINEVIEW(dev)) {
586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587 limit = &intel_limits_pineview_lvds;
589 limit = &intel_limits_pineview_sdvo;
590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
596 limit = &intel_limits_vlv_dp;
597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
601 limit = &intel_limits_i9xx_sdvo;
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604 limit = &intel_limits_i8xx_lvds;
606 limit = &intel_limits_i8xx_dvo;
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
633 * Returns whether any output on the specified pipe is of the specified type
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
637 struct drm_device *dev = crtc->dev;
638 struct intel_encoder *encoder;
640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
647 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
658 INTELPllInvalid("p1 out of range\n");
659 if (clock->p < limit->p.min || limit->p.max < clock->p)
660 INTELPllInvalid("p out of range\n");
661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
662 INTELPllInvalid("m2 out of range\n");
663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
664 INTELPllInvalid("m1 out of range\n");
665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666 INTELPllInvalid("m1 <= m2\n");
667 if (clock->m < limit->m.min || limit->m.max < clock->m)
668 INTELPllInvalid("m out of range\n");
669 if (clock->n < limit->n.min || limit->n.max < clock->n)
670 INTELPllInvalid("n out of range\n");
671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672 INTELPllInvalid("vco out of range\n");
673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677 INTELPllInvalid("dot out of range\n");
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694 (I915_READ(LVDS)) != 0) {
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
701 if (is_dual_link_lvds(dev_priv, LVDS))
702 clock.p2 = limit->p2.p2_fast;
704 clock.p2 = limit->p2.p2_slow;
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
709 clock.p2 = limit->p2.p2_fast;
712 memset(best_clock, 0, sizeof(*best_clock));
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
727 intel_clock(dev, refclk, &clock);
728 if (!intel_PLL_is_valid(dev, limit,
732 clock.p != match_clock->p)
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
745 return (err != target);
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
765 if (HAS_PCH_SPLIT(dev))
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
771 clock.p2 = limit->p2.p2_fast;
773 clock.p2 = limit->p2.p2_slow;
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
778 clock.p2 = limit->p2.p2_fast;
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
783 /* based on hardware requirement, prefer smaller n to precision */
784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785 /* based on hardware requirement, prefere larger m1,m2 */
786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
794 intel_clock(dev, refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
799 clock.p != match_clock->p)
802 this_err = abs(clock.dot - target);
803 if (this_err < err_most) {
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
821 struct drm_device *dev = crtc->dev;
824 if (target < 200000) {
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
849 if (target < 200000) {
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
881 dotclk = target * 1000;
884 fastclk = dotclk / (2*100);
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
912 if (absppm < bestppm - 10) {
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
944 return intel_crtc->cpu_transcoder;
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
952 frame = I915_READ(frame_reg);
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
959 * intel_wait_for_vblank - wait for vblank on a given pipe
961 * @pipe: pipe to wait for
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 int pipestat_reg = PIPESTAT(pipe);
971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
992 /* Wait for vblank interrupt bit to set */
993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
996 DRM_DEBUG_KMS("vblank wait timed out\n");
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
1002 * @pipe: pipe to wait for
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 if (INTEL_INFO(dev)->gen >= 4) {
1023 int reg = PIPECONF(cpu_transcoder);
1025 /* Wait for the Pipe State to go off */
1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1028 WARN(1, "pipe_off wait timed out\n");
1030 u32 last_line, line_mask;
1031 int reg = PIPEDSL(pipe);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035 line_mask = DSL_LINEMASK_GEN2;
1037 line_mask = DSL_LINEMASK_GEN3;
1039 /* Wait for the display line to settle */
1041 last_line = I915_READ(reg) & line_mask;
1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
1046 WARN(1, "pipe_off wait timed out\n");
1050 static const char *state_string(bool enabled)
1052 return enabled ? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_ENABLE);
1155 WARN(cur_state != state,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv->info->gen == 5)
1172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv->dev))
1176 reg = FDI_TX_CTL(pipe);
1177 val = I915_READ(reg);
1178 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1195 int pp_reg, lvds_reg;
1197 enum pipe panel_pipe = PIPE_A;
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1204 pp_reg = PP_CONTROL;
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
1221 void assert_pipe(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1227 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 WARN(cur_state != state,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
1239 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 static void assert_plane(struct drm_i915_private *dev_priv,
1243 enum plane plane, bool state)
1249 reg = DSPCNTR(plane);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252 WARN(cur_state != state,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane), state_string(state), state_string(cur_state));
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1260 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1267 /* Planes are fixed to pipes on ILK+ */
1268 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269 reg = DSPCNTR(pipe);
1270 val = I915_READ(reg);
1271 WARN((val & DISPLAY_PLANE_ENABLE),
1272 "plane %c assertion failure, should be disabled but not\n",
1277 /* Need to check both planes against the pipe */
1278 for (i = 0; i < 2; i++) {
1280 val = I915_READ(reg);
1281 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282 DISPPLANE_SEL_PIPE_SHIFT;
1283 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i), pipe_name(pipe));
1289 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1294 if (HAS_PCH_LPT(dev_priv->dev)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1299 val = I915_READ(PCH_DREF_CONTROL);
1300 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301 DREF_SUPERSPREAD_SOURCE_MASK));
1302 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1312 reg = TRANSCONF(pipe);
1313 val = I915_READ(reg);
1314 enabled = !!(val & TRANS_ENABLE);
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1320 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 port_sel, u32 val)
1323 if ((val & DP_PORT_EN) == 0)
1326 if (HAS_PCH_CPT(dev_priv->dev)) {
1327 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 if ((val & DP_PIPE_MASK) != (pipe << 30))
1338 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, u32 val)
1341 if ((val & PORT_ENABLE) == 0)
1344 if (HAS_PCH_CPT(dev_priv->dev)) {
1345 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1354 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe, u32 val)
1357 if ((val & LVDS_PORT_EN) == 0)
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1370 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1373 if ((val & ADPA_DAC_ENABLE) == 0)
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1385 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, int reg, u32 port_sel)
1388 u32 val = I915_READ(reg);
1389 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391 reg, pipe_name(pipe));
1393 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394 && (val & DP_PIPEB_SELECT),
1395 "IBX PCH dp port still using transcoder B\n");
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe, int reg)
1401 u32 val = I915_READ(reg);
1402 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404 reg, pipe_name(pipe));
1406 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407 && (val & SDVO_PIPE_B_SELECT),
1408 "IBX PCH hdmi port still using transcoder B\n");
1411 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1417 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1422 val = I915_READ(reg);
1423 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424 "PCH VGA enabled on transcoder %c, should be disabled\n",
1428 val = I915_READ(reg);
1429 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1433 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1447 * Note! This is for pre-ILK only.
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1451 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1456 /* No really, not for ILK+ */
1457 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461 assert_panel_unlocked(dev_priv, pipe);
1464 val = I915_READ(reg);
1465 val |= DPLL_VCO_ENABLE;
1467 /* We do this three times for luck */
1468 I915_WRITE(reg, val);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, val);
1476 udelay(150); /* wait for warmup */
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1486 * Note! This is for pre-ILK only.
1488 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1501 val = I915_READ(reg);
1502 val &= ~DPLL_VCO_ENABLE;
1503 I915_WRITE(reg, val);
1509 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1510 enum intel_sbi_destination destination)
1512 unsigned long flags;
1515 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1516 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1517 DRM_ERROR("timeout waiting for SBI to become ready\n");
1521 I915_WRITE(SBI_ADDR, (reg << 16));
1522 I915_WRITE(SBI_DATA, value);
1524 if (destination == SBI_ICLK)
1525 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1527 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1528 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1530 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1532 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1537 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1541 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
1544 unsigned long flags;
1547 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1548 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1553 I915_WRITE(SBI_ADDR, (reg << 16));
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567 value = I915_READ(SBI_DATA);
1570 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1575 * ironlake_enable_pch_pll - enable PCH PLL
1576 * @dev_priv: i915 private structure
1577 * @pipe: pipe PLL to enable
1579 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1580 * drives the transcoder clock.
1582 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1584 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1585 struct intel_pch_pll *pll;
1589 /* PCH PLLs only available on ILK, SNB and IVB */
1590 BUG_ON(dev_priv->info->gen < 5);
1591 pll = intel_crtc->pch_pll;
1595 if (WARN_ON(pll->refcount == 0))
1598 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1599 pll->pll_reg, pll->active, pll->on,
1600 intel_crtc->base.base.id);
1602 /* PCH refclock must be enabled first */
1603 assert_pch_refclk_enabled(dev_priv);
1605 if (pll->active++ && pll->on) {
1606 assert_pch_pll_enabled(dev_priv, pll, NULL);
1610 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1613 val = I915_READ(reg);
1614 val |= DPLL_VCO_ENABLE;
1615 I915_WRITE(reg, val);
1622 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1624 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1625 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1629 /* PCH only available on ILK+ */
1630 BUG_ON(dev_priv->info->gen < 5);
1634 if (WARN_ON(pll->refcount == 0))
1637 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1638 pll->pll_reg, pll->active, pll->on,
1639 intel_crtc->base.base.id);
1641 if (WARN_ON(pll->active == 0)) {
1642 assert_pch_pll_disabled(dev_priv, pll, NULL);
1646 if (--pll->active) {
1647 assert_pch_pll_enabled(dev_priv, pll, NULL);
1651 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1653 /* Make sure transcoder isn't still depending on us */
1654 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1657 val = I915_READ(reg);
1658 val &= ~DPLL_VCO_ENABLE;
1659 I915_WRITE(reg, val);
1666 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1669 struct drm_device *dev = dev_priv->dev;
1670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1671 uint32_t reg, val, pipeconf_val;
1673 /* PCH only available on ILK+ */
1674 BUG_ON(dev_priv->info->gen < 5);
1676 /* Make sure PCH DPLL is enabled */
1677 assert_pch_pll_enabled(dev_priv,
1678 to_intel_crtc(crtc)->pch_pll,
1679 to_intel_crtc(crtc));
1681 /* FDI must be feeding us bits for PCH ports */
1682 assert_fdi_tx_enabled(dev_priv, pipe);
1683 assert_fdi_rx_enabled(dev_priv, pipe);
1685 if (HAS_PCH_CPT(dev)) {
1686 /* Workaround: Set the timing override bit before enabling the
1687 * pch transcoder. */
1688 reg = TRANS_CHICKEN2(pipe);
1689 val = I915_READ(reg);
1690 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1691 I915_WRITE(reg, val);
1694 reg = TRANSCONF(pipe);
1695 val = I915_READ(reg);
1696 pipeconf_val = I915_READ(PIPECONF(pipe));
1698 if (HAS_PCH_IBX(dev_priv->dev)) {
1700 * make the BPC in transcoder be consistent with
1701 * that in pipeconf reg.
1703 val &= ~PIPE_BPC_MASK;
1704 val |= pipeconf_val & PIPE_BPC_MASK;
1707 val &= ~TRANS_INTERLACE_MASK;
1708 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1709 if (HAS_PCH_IBX(dev_priv->dev) &&
1710 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1711 val |= TRANS_LEGACY_INTERLACED_ILK;
1713 val |= TRANS_INTERLACED;
1715 val |= TRANS_PROGRESSIVE;
1717 I915_WRITE(reg, val | TRANS_ENABLE);
1718 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1719 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1723 enum transcoder cpu_transcoder)
1725 u32 val, pipeconf_val;
1727 /* PCH only available on ILK+ */
1728 BUG_ON(dev_priv->info->gen < 5);
1730 /* FDI must be feeding us bits for PCH ports */
1731 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1732 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1734 /* Workaround: set timing override bit. */
1735 val = I915_READ(_TRANSA_CHICKEN2);
1736 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1737 I915_WRITE(_TRANSA_CHICKEN2, val);
1740 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1742 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1743 PIPECONF_INTERLACED_ILK)
1744 val |= TRANS_INTERLACED;
1746 val |= TRANS_PROGRESSIVE;
1748 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1749 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1750 DRM_ERROR("Failed to enable PCH transcoder\n");
1753 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1756 struct drm_device *dev = dev_priv->dev;
1759 /* FDI relies on the transcoder */
1760 assert_fdi_tx_disabled(dev_priv, pipe);
1761 assert_fdi_rx_disabled(dev_priv, pipe);
1763 /* Ports must be off as well */
1764 assert_pch_ports_disabled(dev_priv, pipe);
1766 reg = TRANSCONF(pipe);
1767 val = I915_READ(reg);
1768 val &= ~TRANS_ENABLE;
1769 I915_WRITE(reg, val);
1770 /* wait for PCH transcoder off, transcoder state */
1771 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1772 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1774 if (!HAS_PCH_IBX(dev)) {
1775 /* Workaround: Clear the timing override chicken bit again. */
1776 reg = TRANS_CHICKEN2(pipe);
1777 val = I915_READ(reg);
1778 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1779 I915_WRITE(reg, val);
1783 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1787 val = I915_READ(_TRANSACONF);
1788 val &= ~TRANS_ENABLE;
1789 I915_WRITE(_TRANSACONF, val);
1790 /* wait for PCH transcoder off, transcoder state */
1791 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1792 DRM_ERROR("Failed to disable PCH transcoder\n");
1794 /* Workaround: clear timing override bit. */
1795 val = I915_READ(_TRANSA_CHICKEN2);
1796 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1797 I915_WRITE(_TRANSA_CHICKEN2, val);
1801 * intel_enable_pipe - enable a pipe, asserting requirements
1802 * @dev_priv: i915 private structure
1803 * @pipe: pipe to enable
1804 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1806 * Enable @pipe, making sure that various hardware specific requirements
1807 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1809 * @pipe should be %PIPE_A or %PIPE_B.
1811 * Will wait until the pipe is actually running (i.e. first vblank) before
1814 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1819 enum transcoder pch_transcoder;
1823 if (IS_HASWELL(dev_priv->dev))
1824 pch_transcoder = TRANSCODER_A;
1826 pch_transcoder = pipe;
1829 * A pipe without a PLL won't actually be able to drive bits from
1830 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1833 if (!HAS_PCH_SPLIT(dev_priv->dev))
1834 assert_pll_enabled(dev_priv, pipe);
1837 /* if driving the PCH, we need FDI enabled */
1838 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1839 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1841 /* FIXME: assert CPU port conditions for SNB+ */
1844 reg = PIPECONF(cpu_transcoder);
1845 val = I915_READ(reg);
1846 if (val & PIPECONF_ENABLE)
1849 I915_WRITE(reg, val | PIPECONF_ENABLE);
1850 intel_wait_for_vblank(dev_priv->dev, pipe);
1854 * intel_disable_pipe - disable a pipe, asserting requirements
1855 * @dev_priv: i915 private structure
1856 * @pipe: pipe to disable
1858 * Disable @pipe, making sure that various hardware specific requirements
1859 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1861 * @pipe should be %PIPE_A or %PIPE_B.
1863 * Will wait until the pipe has shut down before returning.
1865 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1868 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1874 * Make sure planes won't keep trying to pump pixels to us,
1875 * or we might hang the display.
1877 assert_planes_disabled(dev_priv, pipe);
1879 /* Don't disable pipe A or pipe A PLLs if needed */
1880 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1883 reg = PIPECONF(cpu_transcoder);
1884 val = I915_READ(reg);
1885 if ((val & PIPECONF_ENABLE) == 0)
1888 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1889 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1893 * Plane regs are double buffered, going from enabled->disabled needs a
1894 * trigger in order to latch. The display address reg provides this.
1896 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1899 if (dev_priv->info->gen >= 4)
1900 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1902 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1906 * intel_enable_plane - enable a display plane on a given pipe
1907 * @dev_priv: i915 private structure
1908 * @plane: plane to enable
1909 * @pipe: pipe being fed
1911 * Enable @plane on @pipe, making sure that @pipe is running first.
1913 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane, enum pipe pipe)
1919 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1920 assert_pipe_enabled(dev_priv, pipe);
1922 reg = DSPCNTR(plane);
1923 val = I915_READ(reg);
1924 if (val & DISPLAY_PLANE_ENABLE)
1927 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1928 intel_flush_display_plane(dev_priv, plane);
1929 intel_wait_for_vblank(dev_priv->dev, pipe);
1933 * intel_disable_plane - disable a display plane
1934 * @dev_priv: i915 private structure
1935 * @plane: plane to disable
1936 * @pipe: pipe consuming the data
1938 * Disable @plane; should be an independent operation.
1940 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941 enum plane plane, enum pipe pipe)
1946 reg = DSPCNTR(plane);
1947 val = I915_READ(reg);
1948 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1951 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1952 intel_flush_display_plane(dev_priv, plane);
1953 intel_wait_for_vblank(dev_priv->dev, pipe);
1957 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1958 struct drm_i915_gem_object *obj,
1959 struct intel_ring_buffer *pipelined)
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1965 switch (obj->tiling_mode) {
1966 case I915_TILING_NONE:
1967 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968 alignment = 128 * 1024;
1969 else if (INTEL_INFO(dev)->gen >= 4)
1970 alignment = 4 * 1024;
1972 alignment = 64 * 1024;
1975 /* pin() will align the object as required by fence */
1979 /* FIXME: Is this true? */
1980 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1986 dev_priv->mm.interruptible = false;
1987 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1989 goto err_interruptible;
1991 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1992 * fence, whereas 965+ only requires a fence if using
1993 * framebuffer compression. For simplicity, we always install
1994 * a fence as the cost is not that onerous.
1996 ret = i915_gem_object_get_fence(obj);
2000 i915_gem_object_pin_fence(obj);
2002 dev_priv->mm.interruptible = true;
2006 i915_gem_object_unpin(obj);
2008 dev_priv->mm.interruptible = true;
2012 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2014 i915_gem_object_unpin_fence(obj);
2015 i915_gem_object_unpin(obj);
2018 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019 * is assumed to be a power-of-two. */
2020 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2024 int tile_rows, tiles;
2028 tiles = *x / (512/bpp);
2031 return tile_rows * pitch * 8 + tiles * 4096;
2034 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2037 struct drm_device *dev = crtc->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040 struct intel_framebuffer *intel_fb;
2041 struct drm_i915_gem_object *obj;
2042 int plane = intel_crtc->plane;
2043 unsigned long linear_offset;
2052 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056 intel_fb = to_intel_framebuffer(fb);
2057 obj = intel_fb->obj;
2059 reg = DSPCNTR(plane);
2060 dspcntr = I915_READ(reg);
2061 /* Mask out pixel format bits in case we change it */
2062 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2063 switch (fb->pixel_format) {
2065 dspcntr |= DISPPLANE_8BPP;
2067 case DRM_FORMAT_XRGB1555:
2068 case DRM_FORMAT_ARGB1555:
2069 dspcntr |= DISPPLANE_BGRX555;
2071 case DRM_FORMAT_RGB565:
2072 dspcntr |= DISPPLANE_BGRX565;
2074 case DRM_FORMAT_XRGB8888:
2075 case DRM_FORMAT_ARGB8888:
2076 dspcntr |= DISPPLANE_BGRX888;
2078 case DRM_FORMAT_XBGR8888:
2079 case DRM_FORMAT_ABGR8888:
2080 dspcntr |= DISPPLANE_RGBX888;
2082 case DRM_FORMAT_XRGB2101010:
2083 case DRM_FORMAT_ARGB2101010:
2084 dspcntr |= DISPPLANE_BGRX101010;
2086 case DRM_FORMAT_XBGR2101010:
2087 case DRM_FORMAT_ABGR2101010:
2088 dspcntr |= DISPPLANE_RGBX101010;
2091 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2095 if (INTEL_INFO(dev)->gen >= 4) {
2096 if (obj->tiling_mode != I915_TILING_NONE)
2097 dspcntr |= DISPPLANE_TILED;
2099 dspcntr &= ~DISPPLANE_TILED;
2102 I915_WRITE(reg, dspcntr);
2104 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2106 if (INTEL_INFO(dev)->gen >= 4) {
2107 intel_crtc->dspaddr_offset =
2108 intel_gen4_compute_offset_xtiled(&x, &y,
2109 fb->bits_per_pixel / 8,
2111 linear_offset -= intel_crtc->dspaddr_offset;
2113 intel_crtc->dspaddr_offset = linear_offset;
2116 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119 if (INTEL_INFO(dev)->gen >= 4) {
2120 I915_MODIFY_DISPBASE(DSPSURF(plane),
2121 obj->gtt_offset + intel_crtc->dspaddr_offset);
2122 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2123 I915_WRITE(DSPLINOFF(plane), linear_offset);
2125 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2131 static int ironlake_update_plane(struct drm_crtc *crtc,
2132 struct drm_framebuffer *fb, int x, int y)
2134 struct drm_device *dev = crtc->dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 struct intel_framebuffer *intel_fb;
2138 struct drm_i915_gem_object *obj;
2139 int plane = intel_crtc->plane;
2140 unsigned long linear_offset;
2150 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2154 intel_fb = to_intel_framebuffer(fb);
2155 obj = intel_fb->obj;
2157 reg = DSPCNTR(plane);
2158 dspcntr = I915_READ(reg);
2159 /* Mask out pixel format bits in case we change it */
2160 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2161 switch (fb->pixel_format) {
2163 dspcntr |= DISPPLANE_8BPP;
2165 case DRM_FORMAT_RGB565:
2166 dspcntr |= DISPPLANE_BGRX565;
2168 case DRM_FORMAT_XRGB8888:
2169 case DRM_FORMAT_ARGB8888:
2170 dspcntr |= DISPPLANE_BGRX888;
2172 case DRM_FORMAT_XBGR8888:
2173 case DRM_FORMAT_ABGR8888:
2174 dspcntr |= DISPPLANE_RGBX888;
2176 case DRM_FORMAT_XRGB2101010:
2177 case DRM_FORMAT_ARGB2101010:
2178 dspcntr |= DISPPLANE_BGRX101010;
2180 case DRM_FORMAT_XBGR2101010:
2181 case DRM_FORMAT_ABGR2101010:
2182 dspcntr |= DISPPLANE_RGBX101010;
2185 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2189 if (obj->tiling_mode != I915_TILING_NONE)
2190 dspcntr |= DISPPLANE_TILED;
2192 dspcntr &= ~DISPPLANE_TILED;
2195 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2197 I915_WRITE(reg, dspcntr);
2199 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2200 intel_crtc->dspaddr_offset =
2201 intel_gen4_compute_offset_xtiled(&x, &y,
2202 fb->bits_per_pixel / 8,
2204 linear_offset -= intel_crtc->dspaddr_offset;
2206 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2208 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2209 I915_MODIFY_DISPBASE(DSPSURF(plane),
2210 obj->gtt_offset + intel_crtc->dspaddr_offset);
2211 if (IS_HASWELL(dev)) {
2212 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2214 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215 I915_WRITE(DSPLINOFF(plane), linear_offset);
2222 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2224 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225 int x, int y, enum mode_set_atomic state)
2227 struct drm_device *dev = crtc->dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2230 if (dev_priv->display.disable_fbc)
2231 dev_priv->display.disable_fbc(dev);
2232 intel_increase_pllclock(crtc);
2234 return dev_priv->display.update_plane(crtc, fb, x, y);
2238 intel_finish_fb(struct drm_framebuffer *old_fb)
2240 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2241 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2242 bool was_interruptible = dev_priv->mm.interruptible;
2245 wait_event(dev_priv->pending_flip_queue,
2246 atomic_read(&dev_priv->mm.wedged) ||
2247 atomic_read(&obj->pending_flip) == 0);
2249 /* Big Hammer, we also need to ensure that any pending
2250 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251 * current scanout is retired before unpinning the old
2254 * This should only fail upon a hung GPU, in which case we
2255 * can safely continue.
2257 dev_priv->mm.interruptible = false;
2258 ret = i915_gem_object_finish_gpu(obj);
2259 dev_priv->mm.interruptible = was_interruptible;
2264 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_master_private *master_priv;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270 if (!dev->primary->master)
2273 master_priv = dev->primary->master->driver_priv;
2274 if (!master_priv->sarea_priv)
2277 switch (intel_crtc->pipe) {
2279 master_priv->sarea_priv->pipeA_x = x;
2280 master_priv->sarea_priv->pipeA_y = y;
2283 master_priv->sarea_priv->pipeB_x = x;
2284 master_priv->sarea_priv->pipeB_y = y;
2292 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2293 struct drm_framebuffer *fb)
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 struct drm_framebuffer *old_fb;
2303 DRM_ERROR("No FB bound\n");
2307 if(intel_crtc->plane > dev_priv->num_pipe) {
2308 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2310 dev_priv->num_pipe);
2314 mutex_lock(&dev->struct_mutex);
2315 ret = intel_pin_and_fence_fb_obj(dev,
2316 to_intel_framebuffer(fb)->obj,
2319 mutex_unlock(&dev->struct_mutex);
2320 DRM_ERROR("pin & fence failed\n");
2325 intel_finish_fb(crtc->fb);
2327 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2329 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2330 mutex_unlock(&dev->struct_mutex);
2331 DRM_ERROR("failed to update base address\n");
2341 intel_wait_for_vblank(dev, intel_crtc->pipe);
2342 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2345 intel_update_fbc(dev);
2346 mutex_unlock(&dev->struct_mutex);
2348 intel_crtc_update_sarea_pos(crtc, x, y);
2353 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2355 struct drm_device *dev = crtc->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2359 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2360 dpa_ctl = I915_READ(DP_A);
2361 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2363 if (clock < 200000) {
2365 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2366 /* workaround for 160Mhz:
2367 1) program 0x4600c bits 15:0 = 0x8124
2368 2) program 0x46010 bit 0 = 1
2369 3) program 0x46034 bit 24 = 1
2370 4) program 0x64000 bit 14 = 1
2372 temp = I915_READ(0x4600c);
2374 I915_WRITE(0x4600c, temp | 0x8124);
2376 temp = I915_READ(0x46010);
2377 I915_WRITE(0x46010, temp | 1);
2379 temp = I915_READ(0x46034);
2380 I915_WRITE(0x46034, temp | (1 << 24));
2382 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2384 I915_WRITE(DP_A, dpa_ctl);
2390 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2392 struct drm_device *dev = crtc->dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2395 int pipe = intel_crtc->pipe;
2398 /* enable normal train */
2399 reg = FDI_TX_CTL(pipe);
2400 temp = I915_READ(reg);
2401 if (IS_IVYBRIDGE(dev)) {
2402 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2403 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2405 temp &= ~FDI_LINK_TRAIN_NONE;
2406 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2408 I915_WRITE(reg, temp);
2410 reg = FDI_RX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 if (HAS_PCH_CPT(dev)) {
2413 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2416 temp &= ~FDI_LINK_TRAIN_NONE;
2417 temp |= FDI_LINK_TRAIN_NONE;
2419 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2421 /* wait one idle pattern time */
2425 /* IVB wants error correction enabled */
2426 if (IS_IVYBRIDGE(dev))
2427 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2428 FDI_FE_ERRC_ENABLE);
2431 static void ivb_modeset_global_resources(struct drm_device *dev)
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_crtc *pipe_B_crtc =
2435 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2436 struct intel_crtc *pipe_C_crtc =
2437 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2440 /* When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. XXX: This misses the case where a pipe is not using
2442 * any pch resources and so doesn't need any fdi lanes. */
2443 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2444 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2445 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2447 temp = I915_READ(SOUTH_CHICKEN1);
2448 temp &= ~FDI_BC_BIFURCATION_SELECT;
2449 DRM_DEBUG_KMS("disabling fdi C rx\n");
2450 I915_WRITE(SOUTH_CHICKEN1, temp);
2454 /* The FDI link training functions for ILK/Ibexpeak. */
2455 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2457 struct drm_device *dev = crtc->dev;
2458 struct drm_i915_private *dev_priv = dev->dev_private;
2459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2460 int pipe = intel_crtc->pipe;
2461 int plane = intel_crtc->plane;
2462 u32 reg, temp, tries;
2464 /* FDI needs bits from pipe & plane first */
2465 assert_pipe_enabled(dev_priv, pipe);
2466 assert_plane_enabled(dev_priv, plane);
2468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2470 reg = FDI_RX_IMR(pipe);
2471 temp = I915_READ(reg);
2472 temp &= ~FDI_RX_SYMBOL_LOCK;
2473 temp &= ~FDI_RX_BIT_LOCK;
2474 I915_WRITE(reg, temp);
2478 /* enable CPU FDI TX and PCH FDI RX */
2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
2482 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_1;
2485 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2487 reg = FDI_RX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2496 /* Ironlake workaround, enable clock pointer after FDI enable*/
2497 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2499 FDI_RX_PHASE_SYNC_POINTER_EN);
2501 reg = FDI_RX_IIR(pipe);
2502 for (tries = 0; tries < 5; tries++) {
2503 temp = I915_READ(reg);
2504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2506 if ((temp & FDI_RX_BIT_LOCK)) {
2507 DRM_DEBUG_KMS("FDI train 1 done.\n");
2508 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2513 DRM_ERROR("FDI train 1 fail!\n");
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
2520 I915_WRITE(reg, temp);
2522 reg = FDI_RX_CTL(pipe);
2523 temp = I915_READ(reg);
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_2;
2526 I915_WRITE(reg, temp);
2531 reg = FDI_RX_IIR(pipe);
2532 for (tries = 0; tries < 5; tries++) {
2533 temp = I915_READ(reg);
2534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2543 DRM_ERROR("FDI train 2 fail!\n");
2545 DRM_DEBUG_KMS("FDI train done\n");
2549 static const int snb_b_fdi_train_param[] = {
2550 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2551 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2552 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2553 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556 /* The FDI link training functions for SNB/Cougarpoint. */
2557 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2559 struct drm_device *dev = crtc->dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562 int pipe = intel_crtc->pipe;
2563 u32 reg, temp, i, retry;
2565 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2567 reg = FDI_RX_IMR(pipe);
2568 temp = I915_READ(reg);
2569 temp &= ~FDI_RX_SYMBOL_LOCK;
2570 temp &= ~FDI_RX_BIT_LOCK;
2571 I915_WRITE(reg, temp);
2576 /* enable CPU FDI TX and PCH FDI RX */
2577 reg = FDI_TX_CTL(pipe);
2578 temp = I915_READ(reg);
2580 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2581 temp &= ~FDI_LINK_TRAIN_NONE;
2582 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2586 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2588 I915_WRITE(FDI_RX_MISC(pipe),
2589 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2591 reg = FDI_RX_CTL(pipe);
2592 temp = I915_READ(reg);
2593 if (HAS_PCH_CPT(dev)) {
2594 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2595 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2605 for (i = 0; i < 4; i++) {
2606 reg = FDI_TX_CTL(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2609 temp |= snb_b_fdi_train_param[i];
2610 I915_WRITE(reg, temp);
2615 for (retry = 0; retry < 5; retry++) {
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619 if (temp & FDI_RX_BIT_LOCK) {
2620 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2621 DRM_DEBUG_KMS("FDI train 1 done.\n");
2630 DRM_ERROR("FDI train 1 fail!\n");
2633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
2635 temp &= ~FDI_LINK_TRAIN_NONE;
2636 temp |= FDI_LINK_TRAIN_PATTERN_2;
2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642 I915_WRITE(reg, temp);
2644 reg = FDI_RX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 if (HAS_PCH_CPT(dev)) {
2647 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2650 temp &= ~FDI_LINK_TRAIN_NONE;
2651 temp |= FDI_LINK_TRAIN_PATTERN_2;
2653 I915_WRITE(reg, temp);
2658 for (i = 0; i < 4; i++) {
2659 reg = FDI_TX_CTL(pipe);
2660 temp = I915_READ(reg);
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= snb_b_fdi_train_param[i];
2663 I915_WRITE(reg, temp);
2668 for (retry = 0; retry < 5; retry++) {
2669 reg = FDI_RX_IIR(pipe);
2670 temp = I915_READ(reg);
2671 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2672 if (temp & FDI_RX_SYMBOL_LOCK) {
2673 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2674 DRM_DEBUG_KMS("FDI train 2 done.\n");
2683 DRM_ERROR("FDI train 2 fail!\n");
2685 DRM_DEBUG_KMS("FDI train done.\n");
2688 /* Manual link training for Ivy Bridge A0 parts */
2689 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2691 struct drm_device *dev = crtc->dev;
2692 struct drm_i915_private *dev_priv = dev->dev_private;
2693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694 int pipe = intel_crtc->pipe;
2697 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2699 reg = FDI_RX_IMR(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_RX_SYMBOL_LOCK;
2702 temp &= ~FDI_RX_BIT_LOCK;
2703 I915_WRITE(reg, temp);
2708 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2709 I915_READ(FDI_RX_IIR(pipe)));
2711 /* enable CPU FDI TX and PCH FDI RX */
2712 reg = FDI_TX_CTL(pipe);
2713 temp = I915_READ(reg);
2715 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2716 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2717 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2718 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2720 temp |= FDI_COMPOSITE_SYNC;
2721 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2723 I915_WRITE(FDI_RX_MISC(pipe),
2724 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~FDI_LINK_TRAIN_AUTO;
2729 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2731 temp |= FDI_COMPOSITE_SYNC;
2732 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2737 for (i = 0; i < 4; i++) {
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741 temp |= snb_b_fdi_train_param[i];
2742 I915_WRITE(reg, temp);
2747 reg = FDI_RX_IIR(pipe);
2748 temp = I915_READ(reg);
2749 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2751 if (temp & FDI_RX_BIT_LOCK ||
2752 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2754 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2759 DRM_ERROR("FDI train 1 fail!\n");
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768 I915_WRITE(reg, temp);
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774 I915_WRITE(reg, temp);
2779 for (i = 0; i < 4; i++) {
2780 reg = FDI_TX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783 temp |= snb_b_fdi_train_param[i];
2784 I915_WRITE(reg, temp);
2789 reg = FDI_RX_IIR(pipe);
2790 temp = I915_READ(reg);
2791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2793 if (temp & FDI_RX_SYMBOL_LOCK) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2800 DRM_ERROR("FDI train 2 fail!\n");
2802 DRM_DEBUG_KMS("FDI train done.\n");
2805 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2807 struct drm_device *dev = intel_crtc->base.dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 int pipe = intel_crtc->pipe;
2813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~((0x7 << 19) | (0x7 << 16));
2817 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824 /* Switch from Rawclk to PCDclk */
2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp | FDI_PCDCLK);
2831 /* On Haswell, the PLL configuration for ports and pipes is handled
2832 * separately, as part of DDI setup */
2833 if (!IS_HASWELL(dev)) {
2834 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835 reg = FDI_TX_CTL(pipe);
2836 temp = I915_READ(reg);
2837 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2870 /* Wait for the clocks to turn off. */
2875 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
2899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2922 I915_WRITE(reg, temp);
2928 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 unsigned long flags;
2935 if (atomic_read(&dev_priv->mm.wedged))
2938 spin_lock_irqsave(&dev->event_lock, flags);
2939 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2940 spin_unlock_irqrestore(&dev->event_lock, flags);
2945 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2950 if (crtc->fb == NULL)
2953 wait_event(dev_priv->pending_flip_queue,
2954 !intel_crtc_has_pending_flip(crtc));
2956 mutex_lock(&dev->struct_mutex);
2957 intel_finish_fb(crtc->fb);
2958 mutex_unlock(&dev->struct_mutex);
2961 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2963 struct drm_device *dev = crtc->dev;
2964 struct intel_encoder *intel_encoder;
2967 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2968 * must be driven by its own crtc; no sharing is possible.
2970 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2971 switch (intel_encoder->type) {
2972 case INTEL_OUTPUT_EDP:
2973 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2982 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2984 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2987 /* Program iCLKIP clock to the desired frequency */
2988 static void lpt_program_iclkip(struct drm_crtc *crtc)
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3002 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (crtc->mode.clock == 20000) {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the crtc->mode.clock in in KHz. To get the divisors,
3014 * it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3018 u32 iclk_virtual_root_freq = 172800 * 1000;
3019 u32 iclk_pi_range = 64;
3020 u32 desired_divisor, msb_divisor_value, pi_value;
3022 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3023 msb_divisor_value = desired_divisor / iclk_pi_range;
3024 pi_value = desired_divisor % iclk_pi_range;
3027 divsel = msb_divisor_value - 2;
3028 phaseinc = pi_value;
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3044 /* Program SSCDIVINTPHASE6 */
3045 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3046 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3054 /* Program SSCAUXDIV */
3055 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3056 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3058 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3060 /* Enable modulator and associated divider */
3061 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3062 temp &= ~SBI_SSCCTL_DISABLE;
3063 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3065 /* Wait for initialization time */
3068 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3072 * Enable PCH resources required for PCH ports:
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3079 static void ironlake_pch_enable(struct drm_crtc *crtc)
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
3087 assert_transcoder_disabled(dev_priv, pipe);
3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3094 /* For PCH output, training FDI link */
3095 dev_priv->display.fdi_link_train(crtc);
3097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
3104 ironlake_enable_pch_pll(intel_crtc);
3106 if (HAS_PCH_CPT(dev)) {
3109 temp = I915_READ(PCH_DPLL_SEL);
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3129 I915_WRITE(PCH_DPLL_SEL, temp);
3132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
3134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3143 intel_fdi_normal_train(crtc);
3145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
3147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3153 TRANS_DP_SYNC_MASK |
3155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
3157 temp |= bpc << 9; /* same format but at 11:9 */
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3164 switch (intel_trans_dp_port_sel(crtc)) {
3166 temp |= TRANS_DP_PORT_SEL_B;
3169 temp |= TRANS_DP_PORT_SEL_C;
3172 temp |= TRANS_DP_PORT_SEL_D;
3178 I915_WRITE(reg, temp);
3181 ironlake_enable_pch_transcoder(dev_priv, pipe);
3184 static void lpt_pch_enable(struct drm_crtc *crtc)
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3193 lpt_program_iclkip(crtc);
3195 /* Set transcoder timing. */
3196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3208 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3221 intel_crtc->pch_pll = NULL;
3224 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3230 pll = intel_crtc->pch_pll;
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3278 intel_crtc->pch_pll = pll;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281 prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3286 POSTING_READ(pll->pll_reg);
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3295 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 int dslreg = PIPEDSL(pipe);
3301 temp = I915_READ(dslreg);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3309 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314 struct intel_encoder *encoder;
3315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3320 WARN_ON(!crtc->enabled);
3322 if (intel_crtc->active)
3325 intel_crtc->active = true;
3326 intel_update_watermarks(dev);
3328 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3329 temp = I915_READ(PCH_LVDS);
3330 if ((temp & LVDS_PORT_EN) == 0)
3331 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3334 is_pch_port = ironlake_crtc_driving_pch(crtc);
3337 /* Note: FDI PLL enabling _must_ be done before we enable the
3338 * cpu pipes, hence this is separate from all the other fdi/pch
3340 ironlake_fdi_pll_enable(intel_crtc);
3342 assert_fdi_tx_disabled(dev_priv, pipe);
3343 assert_fdi_rx_disabled(dev_priv, pipe);
3346 for_each_encoder_on_crtc(dev, crtc, encoder)
3347 if (encoder->pre_enable)
3348 encoder->pre_enable(encoder);
3350 /* Enable panel fitting for LVDS */
3351 if (dev_priv->pch_pf_size &&
3352 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3353 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3354 /* Force use of hard-coded filter coefficients
3355 * as some pre-programmed values are broken,
3358 if (IS_IVYBRIDGE(dev))
3359 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3360 PF_PIPE_SEL_IVB(pipe));
3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3371 intel_crtc_load_lut(crtc);
3373 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3374 intel_enable_plane(dev_priv, plane, pipe);
3377 ironlake_pch_enable(crtc);
3379 mutex_lock(&dev->struct_mutex);
3380 intel_update_fbc(dev);
3381 mutex_unlock(&dev->struct_mutex);
3383 intel_crtc_update_cursor(crtc, true);
3385 for_each_encoder_on_crtc(dev, crtc, encoder)
3386 encoder->enable(encoder);
3388 if (HAS_PCH_CPT(dev))
3389 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
3402 static void haswell_crtc_enable(struct drm_crtc *crtc)
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 struct intel_encoder *encoder;
3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
3412 WARN_ON(!crtc->enabled);
3414 if (intel_crtc->active)
3417 intel_crtc->active = true;
3418 intel_update_watermarks(dev);
3420 is_pch_port = haswell_crtc_driving_pch(crtc);
3423 dev_priv->display.fdi_link_train(crtc);
3425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 if (encoder->pre_enable)
3427 encoder->pre_enable(encoder);
3429 intel_ddi_enable_pipe_clock(intel_crtc);
3431 /* Enable panel fitting for eDP */
3432 if (dev_priv->pch_pf_size &&
3433 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3434 /* Force use of hard-coded filter coefficients
3435 * as some pre-programmed values are broken,
3438 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3439 PF_PIPE_SEL_IVB(pipe));
3440 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3441 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3445 * On ILK+ LUT must be loaded before the pipe is running but with
3448 intel_crtc_load_lut(crtc);
3450 intel_ddi_set_pipe_settings(crtc);
3451 intel_ddi_enable_pipe_func(crtc);
3453 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3454 intel_enable_plane(dev_priv, plane, pipe);
3457 lpt_pch_enable(crtc);
3459 mutex_lock(&dev->struct_mutex);
3460 intel_update_fbc(dev);
3461 mutex_unlock(&dev->struct_mutex);
3463 intel_crtc_update_cursor(crtc, true);
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->enable(encoder);
3469 * There seems to be a race in PCH platform hw (at least on some
3470 * outputs) where an enabled pipe still completes any pageflip right
3471 * away (as if the pipe is off) instead of waiting for vblank. As soon
3472 * as the first vblank happend, everything works as expected. Hence just
3473 * wait for one vblank before returning to avoid strange things
3476 intel_wait_for_vblank(dev, intel_crtc->pipe);
3479 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484 struct intel_encoder *encoder;
3485 int pipe = intel_crtc->pipe;
3486 int plane = intel_crtc->plane;
3490 if (!intel_crtc->active)
3493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 encoder->disable(encoder);
3496 intel_crtc_wait_for_pending_flips(crtc);
3497 drm_vblank_off(dev, pipe);
3498 intel_crtc_update_cursor(crtc, false);
3500 intel_disable_plane(dev_priv, plane, pipe);
3502 if (dev_priv->cfb_plane == plane)
3503 intel_disable_fbc(dev);
3505 intel_disable_pipe(dev_priv, pipe);
3508 I915_WRITE(PF_CTL(pipe), 0);
3509 I915_WRITE(PF_WIN_SZ(pipe), 0);
3511 for_each_encoder_on_crtc(dev, crtc, encoder)
3512 if (encoder->post_disable)
3513 encoder->post_disable(encoder);
3515 ironlake_fdi_disable(crtc);
3517 ironlake_disable_pch_transcoder(dev_priv, pipe);
3519 if (HAS_PCH_CPT(dev)) {
3520 /* disable TRANS_DP_CTL */
3521 reg = TRANS_DP_CTL(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3524 temp |= TRANS_DP_PORT_SEL_NONE;
3525 I915_WRITE(reg, temp);
3527 /* disable DPLL_SEL */
3528 temp = I915_READ(PCH_DPLL_SEL);
3531 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3534 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3537 /* C shares PLL A or B */
3538 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3543 I915_WRITE(PCH_DPLL_SEL, temp);
3546 /* disable PCH DPLL */
3547 intel_disable_pch_pll(intel_crtc);
3549 ironlake_fdi_pll_disable(intel_crtc);
3551 intel_crtc->active = false;
3552 intel_update_watermarks(dev);
3554 mutex_lock(&dev->struct_mutex);
3555 intel_update_fbc(dev);
3556 mutex_unlock(&dev->struct_mutex);
3559 static void haswell_crtc_disable(struct drm_crtc *crtc)
3561 struct drm_device *dev = crtc->dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564 struct intel_encoder *encoder;
3565 int pipe = intel_crtc->pipe;
3566 int plane = intel_crtc->plane;
3567 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3570 if (!intel_crtc->active)
3573 is_pch_port = haswell_crtc_driving_pch(crtc);
3575 for_each_encoder_on_crtc(dev, crtc, encoder)
3576 encoder->disable(encoder);
3578 intel_crtc_wait_for_pending_flips(crtc);
3579 drm_vblank_off(dev, pipe);
3580 intel_crtc_update_cursor(crtc, false);
3582 intel_disable_plane(dev_priv, plane, pipe);
3584 if (dev_priv->cfb_plane == plane)
3585 intel_disable_fbc(dev);
3587 intel_disable_pipe(dev_priv, pipe);
3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3592 I915_WRITE(PF_CTL(pipe), 0);
3593 I915_WRITE(PF_WIN_SZ(pipe), 0);
3595 intel_ddi_disable_pipe_clock(intel_crtc);
3597 for_each_encoder_on_crtc(dev, crtc, encoder)
3598 if (encoder->post_disable)
3599 encoder->post_disable(encoder);
3602 lpt_disable_pch_transcoder(dev_priv);
3603 intel_ddi_fdi_disable(crtc);
3606 intel_crtc->active = false;
3607 intel_update_watermarks(dev);
3609 mutex_lock(&dev->struct_mutex);
3610 intel_update_fbc(dev);
3611 mutex_unlock(&dev->struct_mutex);
3614 static void ironlake_crtc_off(struct drm_crtc *crtc)
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 intel_put_pch_pll(intel_crtc);
3620 static void haswell_crtc_off(struct drm_crtc *crtc)
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3625 * start using it. */
3626 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3628 intel_ddi_put_crtc_pll(crtc);
3631 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3633 if (!enable && intel_crtc->overlay) {
3634 struct drm_device *dev = intel_crtc->base.dev;
3635 struct drm_i915_private *dev_priv = dev->dev_private;
3637 mutex_lock(&dev->struct_mutex);
3638 dev_priv->mm.interruptible = false;
3639 (void) intel_overlay_switch_off(intel_crtc->overlay);
3640 dev_priv->mm.interruptible = true;
3641 mutex_unlock(&dev->struct_mutex);
3644 /* Let userspace switch the overlay on again. In most cases userspace
3645 * has to recompute where to put it anyway.
3649 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3651 struct drm_device *dev = crtc->dev;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654 struct intel_encoder *encoder;
3655 int pipe = intel_crtc->pipe;
3656 int plane = intel_crtc->plane;
3658 WARN_ON(!crtc->enabled);
3660 if (intel_crtc->active)
3663 intel_crtc->active = true;
3664 intel_update_watermarks(dev);
3666 intel_enable_pll(dev_priv, pipe);
3667 intel_enable_pipe(dev_priv, pipe, false);
3668 intel_enable_plane(dev_priv, plane, pipe);
3670 intel_crtc_load_lut(crtc);
3671 intel_update_fbc(dev);
3673 /* Give the overlay scaler a chance to enable if it's on this pipe */
3674 intel_crtc_dpms_overlay(intel_crtc, true);
3675 intel_crtc_update_cursor(crtc, true);
3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 encoder->enable(encoder);
3681 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3686 struct intel_encoder *encoder;
3687 int pipe = intel_crtc->pipe;
3688 int plane = intel_crtc->plane;
3692 if (!intel_crtc->active)
3695 for_each_encoder_on_crtc(dev, crtc, encoder)
3696 encoder->disable(encoder);
3698 /* Give the overlay scaler a chance to disable if it's on this pipe */
3699 intel_crtc_wait_for_pending_flips(crtc);
3700 drm_vblank_off(dev, pipe);
3701 intel_crtc_dpms_overlay(intel_crtc, false);
3702 intel_crtc_update_cursor(crtc, false);
3704 if (dev_priv->cfb_plane == plane)
3705 intel_disable_fbc(dev);
3707 intel_disable_plane(dev_priv, plane, pipe);
3708 intel_disable_pipe(dev_priv, pipe);
3710 /* Disable pannel fitter if it is on this pipe. */
3711 pctl = I915_READ(PFIT_CONTROL);
3712 if ((pctl & PFIT_ENABLE) &&
3713 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3714 I915_WRITE(PFIT_CONTROL, 0);
3716 intel_disable_pll(dev_priv, pipe);
3718 intel_crtc->active = false;
3719 intel_update_fbc(dev);
3720 intel_update_watermarks(dev);
3723 static void i9xx_crtc_off(struct drm_crtc *crtc)
3727 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3730 struct drm_device *dev = crtc->dev;
3731 struct drm_i915_master_private *master_priv;
3732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3733 int pipe = intel_crtc->pipe;
3735 if (!dev->primary->master)
3738 master_priv = dev->primary->master->driver_priv;
3739 if (!master_priv->sarea_priv)
3744 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3745 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3748 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3749 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3752 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3758 * Sets the power management mode of the pipe and plane.
3760 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3762 struct drm_device *dev = crtc->dev;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 struct intel_encoder *intel_encoder;
3765 bool enable = false;
3767 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3768 enable |= intel_encoder->connectors_active;
3771 dev_priv->display.crtc_enable(crtc);
3773 dev_priv->display.crtc_disable(crtc);
3775 intel_crtc_update_sarea(crtc, enable);
3778 static void intel_crtc_noop(struct drm_crtc *crtc)
3782 static void intel_crtc_disable(struct drm_crtc *crtc)
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_connector *connector;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3788 /* crtc should still be enabled when we disable it. */
3789 WARN_ON(!crtc->enabled);
3791 dev_priv->display.crtc_disable(crtc);
3792 intel_crtc_update_sarea(crtc, false);
3793 dev_priv->display.off(crtc);
3795 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3796 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3799 mutex_lock(&dev->struct_mutex);
3800 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3801 mutex_unlock(&dev->struct_mutex);
3805 /* Update computed state. */
3806 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3807 if (!connector->encoder || !connector->encoder->crtc)
3810 if (connector->encoder->crtc != crtc)
3813 connector->dpms = DRM_MODE_DPMS_OFF;
3814 to_intel_encoder(connector->encoder)->connectors_active = false;
3818 void intel_modeset_disable(struct drm_device *dev)
3820 struct drm_crtc *crtc;
3822 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3824 intel_crtc_disable(crtc);
3828 void intel_encoder_noop(struct drm_encoder *encoder)
3832 void intel_encoder_destroy(struct drm_encoder *encoder)
3834 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3836 drm_encoder_cleanup(encoder);
3837 kfree(intel_encoder);
3840 /* Simple dpms helper for encodres with just one connector, no cloning and only
3841 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3842 * state of the entire output pipe. */
3843 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3845 if (mode == DRM_MODE_DPMS_ON) {
3846 encoder->connectors_active = true;
3848 intel_crtc_update_dpms(encoder->base.crtc);
3850 encoder->connectors_active = false;
3852 intel_crtc_update_dpms(encoder->base.crtc);
3856 /* Cross check the actual hw state with our own modeset state tracking (and it's
3857 * internal consistency). */
3858 static void intel_connector_check_state(struct intel_connector *connector)
3860 if (connector->get_hw_state(connector)) {
3861 struct intel_encoder *encoder = connector->encoder;
3862 struct drm_crtc *crtc;
3863 bool encoder_enabled;
3866 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3867 connector->base.base.id,
3868 drm_get_connector_name(&connector->base));
3870 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3871 "wrong connector dpms state\n");
3872 WARN(connector->base.encoder != &encoder->base,
3873 "active connector not linked to encoder\n");
3874 WARN(!encoder->connectors_active,
3875 "encoder->connectors_active not set\n");
3877 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3878 WARN(!encoder_enabled, "encoder not enabled\n");
3879 if (WARN_ON(!encoder->base.crtc))
3882 crtc = encoder->base.crtc;
3884 WARN(!crtc->enabled, "crtc not enabled\n");
3885 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3886 WARN(pipe != to_intel_crtc(crtc)->pipe,
3887 "encoder active on the wrong pipe\n");
3891 /* Even simpler default implementation, if there's really no special case to
3893 void intel_connector_dpms(struct drm_connector *connector, int mode)
3895 struct intel_encoder *encoder = intel_attached_encoder(connector);
3897 /* All the simple cases only support two dpms states. */
3898 if (mode != DRM_MODE_DPMS_ON)
3899 mode = DRM_MODE_DPMS_OFF;
3901 if (mode == connector->dpms)
3904 connector->dpms = mode;
3906 /* Only need to change hw state when actually enabled */
3907 if (encoder->base.crtc)
3908 intel_encoder_dpms(encoder, mode);
3910 WARN_ON(encoder->connectors_active != false);
3912 intel_modeset_check_state(connector->dev);
3915 /* Simple connector->get_hw_state implementation for encoders that support only
3916 * one connector and no cloning and hence the encoder state determines the state
3917 * of the connector. */
3918 bool intel_connector_get_hw_state(struct intel_connector *connector)
3921 struct intel_encoder *encoder = connector->encoder;
3923 return encoder->get_hw_state(encoder, &pipe);
3926 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3927 const struct drm_display_mode *mode,
3928 struct drm_display_mode *adjusted_mode)
3930 struct drm_device *dev = crtc->dev;
3932 if (HAS_PCH_SPLIT(dev)) {
3933 /* FDI link clock is fixed at 2.7G */
3934 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3938 /* All interlaced capable intel hw wants timings in frames. Note though
3939 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3940 * timings, so we need to be careful not to clobber these.*/
3941 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3942 drm_mode_set_crtcinfo(adjusted_mode, 0);
3944 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3945 * with a hsync front porch of 0.
3947 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3948 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3954 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3956 return 400000; /* FIXME */
3959 static int i945_get_display_clock_speed(struct drm_device *dev)
3964 static int i915_get_display_clock_speed(struct drm_device *dev)
3969 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3974 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3978 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3980 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3983 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3984 case GC_DISPLAY_CLOCK_333_MHZ:
3987 case GC_DISPLAY_CLOCK_190_200_MHZ:
3993 static int i865_get_display_clock_speed(struct drm_device *dev)
3998 static int i855_get_display_clock_speed(struct drm_device *dev)
4001 /* Assume that the hardware is in the high speed state. This
4002 * should be the default.
4004 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4005 case GC_CLOCK_133_200:
4006 case GC_CLOCK_100_200:
4008 case GC_CLOCK_166_250:
4010 case GC_CLOCK_100_133:
4014 /* Shouldn't happen */
4018 static int i830_get_display_clock_speed(struct drm_device *dev)
4032 fdi_reduce_ratio(u32 *num, u32 *den)
4034 while (*num > 0xffffff || *den > 0xffffff) {
4041 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4042 int link_clock, struct fdi_m_n *m_n)
4044 m_n->tu = 64; /* default size */
4046 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4047 m_n->gmch_m = bits_per_pixel * pixel_clock;
4048 m_n->gmch_n = link_clock * nlanes * 8;
4049 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4051 m_n->link_m = pixel_clock;
4052 m_n->link_n = link_clock;
4053 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4056 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4058 if (i915_panel_use_ssc >= 0)
4059 return i915_panel_use_ssc != 0;
4060 return dev_priv->lvds_use_ssc
4061 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4065 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4066 * @crtc: CRTC structure
4067 * @mode: requested mode
4069 * A pipe may be connected to one or more outputs. Based on the depth of the
4070 * attached framebuffer, choose a good color depth to use on the pipe.
4072 * If possible, match the pipe depth to the fb depth. In some cases, this
4073 * isn't ideal, because the connected output supports a lesser or restricted
4074 * set of depths. Resolve that here:
4075 * LVDS typically supports only 6bpc, so clamp down in that case
4076 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4077 * Displays may support a restricted set as well, check EDID and clamp as
4079 * DP may want to dither down to 6bpc to fit larger modes
4082 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4083 * true if they don't match).
4085 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4086 struct drm_framebuffer *fb,
4087 unsigned int *pipe_bpp,
4088 struct drm_display_mode *mode)
4090 struct drm_device *dev = crtc->dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 struct drm_connector *connector;
4093 struct intel_encoder *intel_encoder;
4094 unsigned int display_bpc = UINT_MAX, bpc;
4096 /* Walk the encoders & connectors on this crtc, get min bpc */
4097 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4099 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4100 unsigned int lvds_bpc;
4102 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4108 if (lvds_bpc < display_bpc) {
4109 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4110 display_bpc = lvds_bpc;
4115 /* Not one of the known troublemakers, check the EDID */
4116 list_for_each_entry(connector, &dev->mode_config.connector_list,
4118 if (connector->encoder != &intel_encoder->base)
4121 /* Don't use an invalid EDID bpc value */
4122 if (connector->display_info.bpc &&
4123 connector->display_info.bpc < display_bpc) {
4124 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4125 display_bpc = connector->display_info.bpc;
4129 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4130 /* Use VBT settings if we have an eDP panel */
4131 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4133 if (edp_bpc && edp_bpc < display_bpc) {
4134 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4135 display_bpc = edp_bpc;
4141 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4142 * through, clamp it down. (Note: >12bpc will be caught below.)
4144 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4145 if (display_bpc > 8 && display_bpc < 12) {
4146 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4149 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4155 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4156 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4161 * We could just drive the pipe at the highest bpc all the time and
4162 * enable dithering as needed, but that costs bandwidth. So choose
4163 * the minimum value that expresses the full color range of the fb but
4164 * also stays within the max display bpc discovered above.
4167 switch (fb->depth) {
4169 bpc = 8; /* since we go through a colormap */
4173 bpc = 6; /* min is 18bpp */
4185 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4186 bpc = min((unsigned int)8, display_bpc);
4190 display_bpc = min(display_bpc, bpc);
4192 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4195 *pipe_bpp = display_bpc * 3;
4197 return display_bpc != bpc;
4200 static int vlv_get_refclk(struct drm_crtc *crtc)
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 int refclk = 27000; /* for DP & HDMI */
4206 return 100000; /* only one validated so far */
4208 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4210 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4211 if (intel_panel_use_ssc(dev_priv))
4215 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4222 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4224 struct drm_device *dev = crtc->dev;
4225 struct drm_i915_private *dev_priv = dev->dev_private;
4228 if (IS_VALLEYVIEW(dev)) {
4229 refclk = vlv_get_refclk(crtc);
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4231 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4232 refclk = dev_priv->lvds_ssc_freq * 1000;
4233 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4235 } else if (!IS_GEN2(dev)) {
4244 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4245 intel_clock_t *clock)
4247 /* SDVO TV has fixed PLL values depend on its clock range,
4248 this mirrors vbios setting. */
4249 if (adjusted_mode->clock >= 100000
4250 && adjusted_mode->clock < 140500) {
4256 } else if (adjusted_mode->clock >= 140500
4257 && adjusted_mode->clock <= 200000) {
4266 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4267 intel_clock_t *clock,
4268 intel_clock_t *reduced_clock)
4270 struct drm_device *dev = crtc->dev;
4271 struct drm_i915_private *dev_priv = dev->dev_private;
4272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273 int pipe = intel_crtc->pipe;
4276 if (IS_PINEVIEW(dev)) {
4277 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4279 fp2 = (1 << reduced_clock->n) << 16 |
4280 reduced_clock->m1 << 8 | reduced_clock->m2;
4282 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4284 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4288 I915_WRITE(FP0(pipe), fp);
4290 intel_crtc->lowfreq_avail = false;
4291 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4292 reduced_clock && i915_powersave) {
4293 I915_WRITE(FP1(pipe), fp2);
4294 intel_crtc->lowfreq_avail = true;
4296 I915_WRITE(FP1(pipe), fp);
4300 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4301 struct drm_display_mode *adjusted_mode)
4303 struct drm_device *dev = crtc->dev;
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4306 int pipe = intel_crtc->pipe;
4309 temp = I915_READ(LVDS);
4310 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4312 temp |= LVDS_PIPEB_SELECT;
4314 temp &= ~LVDS_PIPEB_SELECT;
4316 /* set the corresponsding LVDS_BORDER bit */
4317 temp |= dev_priv->lvds_border_bits;
4318 /* Set the B0-B3 data pairs corresponding to whether we're going to
4319 * set the DPLLs for dual-channel mode or not.
4322 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4324 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4326 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4327 * appropriately here, but we need to look more thoroughly into how
4328 * panels behave in the two modes.
4330 /* set the dithering flag on LVDS as needed */
4331 if (INTEL_INFO(dev)->gen >= 4) {
4332 if (dev_priv->lvds_dither)
4333 temp |= LVDS_ENABLE_DITHER;
4335 temp &= ~LVDS_ENABLE_DITHER;
4337 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4338 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4339 temp |= LVDS_HSYNC_POLARITY;
4340 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4341 temp |= LVDS_VSYNC_POLARITY;
4342 I915_WRITE(LVDS, temp);
4345 static void vlv_update_pll(struct drm_crtc *crtc,
4346 struct drm_display_mode *mode,
4347 struct drm_display_mode *adjusted_mode,
4348 intel_clock_t *clock, intel_clock_t *reduced_clock,
4351 struct drm_device *dev = crtc->dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4354 int pipe = intel_crtc->pipe;
4355 u32 dpll, mdiv, pdiv;
4356 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4360 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4361 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4363 dpll = DPLL_VGA_MODE_DIS;
4364 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4365 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4366 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4368 I915_WRITE(DPLL(pipe), dpll);
4369 POSTING_READ(DPLL(pipe));
4378 * In Valleyview PLL and program lane counter registers are exposed
4379 * through DPIO interface
4381 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4382 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4383 mdiv |= ((bestn << DPIO_N_SHIFT));
4384 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4385 mdiv |= (1 << DPIO_K_SHIFT);
4386 mdiv |= DPIO_ENABLE_CALIBRATION;
4387 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4389 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4391 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4392 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4393 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4394 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4395 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4397 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4399 dpll |= DPLL_VCO_ENABLE;
4400 I915_WRITE(DPLL(pipe), dpll);
4401 POSTING_READ(DPLL(pipe));
4402 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4403 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4405 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4408 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4410 I915_WRITE(DPLL(pipe), dpll);
4412 /* Wait for the clocks to stabilize. */
4413 POSTING_READ(DPLL(pipe));
4418 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4420 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4424 I915_WRITE(DPLL_MD(pipe), temp);
4425 POSTING_READ(DPLL_MD(pipe));
4427 /* Now program lane control registers */
4428 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4429 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4434 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4436 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4441 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4445 static void i9xx_update_pll(struct drm_crtc *crtc,
4446 struct drm_display_mode *mode,
4447 struct drm_display_mode *adjusted_mode,
4448 intel_clock_t *clock, intel_clock_t *reduced_clock,
4451 struct drm_device *dev = crtc->dev;
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4454 int pipe = intel_crtc->pipe;
4458 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4460 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4461 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4463 dpll = DPLL_VGA_MODE_DIS;
4465 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4466 dpll |= DPLLB_MODE_LVDS;
4468 dpll |= DPLLB_MODE_DAC_SERIAL;
4470 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4471 if (pixel_multiplier > 1) {
4472 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4473 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4475 dpll |= DPLL_DVO_HIGH_SPEED;
4477 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4478 dpll |= DPLL_DVO_HIGH_SPEED;
4480 /* compute bitmask from p1 value */
4481 if (IS_PINEVIEW(dev))
4482 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4484 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4485 if (IS_G4X(dev) && reduced_clock)
4486 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4488 switch (clock->p2) {
4490 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4493 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4502 if (INTEL_INFO(dev)->gen >= 4)
4503 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4505 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4506 dpll |= PLL_REF_INPUT_TVCLKINBC;
4507 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4508 /* XXX: just matching BIOS for now */
4509 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4511 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4512 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4513 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4515 dpll |= PLL_REF_INPUT_DREFCLK;
4517 dpll |= DPLL_VCO_ENABLE;
4518 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4519 POSTING_READ(DPLL(pipe));
4522 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4523 * This is an exception to the general rule that mode_set doesn't turn
4526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4527 intel_update_lvds(crtc, clock, adjusted_mode);
4529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4530 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4532 I915_WRITE(DPLL(pipe), dpll);
4534 /* Wait for the clocks to stabilize. */
4535 POSTING_READ(DPLL(pipe));
4538 if (INTEL_INFO(dev)->gen >= 4) {
4541 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4543 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4547 I915_WRITE(DPLL_MD(pipe), temp);
4549 /* The pixel multiplier can only be updated once the
4550 * DPLL is enabled and the clocks are stable.
4552 * So write it again.
4554 I915_WRITE(DPLL(pipe), dpll);
4558 static void i8xx_update_pll(struct drm_crtc *crtc,
4559 struct drm_display_mode *adjusted_mode,
4560 intel_clock_t *clock, intel_clock_t *reduced_clock,
4563 struct drm_device *dev = crtc->dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566 int pipe = intel_crtc->pipe;
4569 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4571 dpll = DPLL_VGA_MODE_DIS;
4573 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4574 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4577 dpll |= PLL_P1_DIVIDE_BY_TWO;
4579 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4581 dpll |= PLL_P2_DIVIDE_BY_4;
4584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4585 /* XXX: just matching BIOS for now */
4586 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4588 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4592 dpll |= PLL_REF_INPUT_DREFCLK;
4594 dpll |= DPLL_VCO_ENABLE;
4595 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4596 POSTING_READ(DPLL(pipe));
4599 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4600 * This is an exception to the general rule that mode_set doesn't turn
4603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4604 intel_update_lvds(crtc, clock, adjusted_mode);
4606 I915_WRITE(DPLL(pipe), dpll);
4608 /* Wait for the clocks to stabilize. */
4609 POSTING_READ(DPLL(pipe));
4612 /* The pixel multiplier can only be updated once the
4613 * DPLL is enabled and the clocks are stable.
4615 * So write it again.
4617 I915_WRITE(DPLL(pipe), dpll);
4620 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4621 struct drm_display_mode *mode,
4622 struct drm_display_mode *adjusted_mode)
4624 struct drm_device *dev = intel_crtc->base.dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626 enum pipe pipe = intel_crtc->pipe;
4627 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4628 uint32_t vsyncshift;
4630 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4631 /* the chip adds 2 halflines automatically */
4632 adjusted_mode->crtc_vtotal -= 1;
4633 adjusted_mode->crtc_vblank_end -= 1;
4634 vsyncshift = adjusted_mode->crtc_hsync_start
4635 - adjusted_mode->crtc_htotal / 2;
4640 if (INTEL_INFO(dev)->gen > 3)
4641 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4643 I915_WRITE(HTOTAL(cpu_transcoder),
4644 (adjusted_mode->crtc_hdisplay - 1) |
4645 ((adjusted_mode->crtc_htotal - 1) << 16));
4646 I915_WRITE(HBLANK(cpu_transcoder),
4647 (adjusted_mode->crtc_hblank_start - 1) |
4648 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4649 I915_WRITE(HSYNC(cpu_transcoder),
4650 (adjusted_mode->crtc_hsync_start - 1) |
4651 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4653 I915_WRITE(VTOTAL(cpu_transcoder),
4654 (adjusted_mode->crtc_vdisplay - 1) |
4655 ((adjusted_mode->crtc_vtotal - 1) << 16));
4656 I915_WRITE(VBLANK(cpu_transcoder),
4657 (adjusted_mode->crtc_vblank_start - 1) |
4658 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4659 I915_WRITE(VSYNC(cpu_transcoder),
4660 (adjusted_mode->crtc_vsync_start - 1) |
4661 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4663 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4664 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4665 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4667 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4668 (pipe == PIPE_B || pipe == PIPE_C))
4669 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4671 /* pipesrc controls the size that is scaled from, which should
4672 * always be the user's requested size.
4674 I915_WRITE(PIPESRC(pipe),
4675 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4678 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4679 struct drm_display_mode *mode,
4680 struct drm_display_mode *adjusted_mode,
4682 struct drm_framebuffer *fb)
4684 struct drm_device *dev = crtc->dev;
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4687 int pipe = intel_crtc->pipe;
4688 int plane = intel_crtc->plane;
4689 int refclk, num_connectors = 0;
4690 intel_clock_t clock, reduced_clock;
4691 u32 dspcntr, pipeconf;
4692 bool ok, has_reduced_clock = false, is_sdvo = false;
4693 bool is_lvds = false, is_tv = false, is_dp = false;
4694 struct intel_encoder *encoder;
4695 const intel_limit_t *limit;
4698 for_each_encoder_on_crtc(dev, crtc, encoder) {
4699 switch (encoder->type) {
4700 case INTEL_OUTPUT_LVDS:
4703 case INTEL_OUTPUT_SDVO:
4704 case INTEL_OUTPUT_HDMI:
4706 if (encoder->needs_tv_clock)
4709 case INTEL_OUTPUT_TVOUT:
4712 case INTEL_OUTPUT_DISPLAYPORT:
4720 refclk = i9xx_get_refclk(crtc, num_connectors);
4723 * Returns a set of divisors for the desired target clock with the given
4724 * refclk, or FALSE. The returned values represent the clock equation:
4725 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4727 limit = intel_limit(crtc, refclk);
4728 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4731 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4735 /* Ensure that the cursor is valid for the new mode before changing... */
4736 intel_crtc_update_cursor(crtc, true);
4738 if (is_lvds && dev_priv->lvds_downclock_avail) {
4740 * Ensure we match the reduced clock's P to the target clock.
4741 * If the clocks don't match, we can't switch the display clock
4742 * by using the FP0/FP1. In such case we will disable the LVDS
4743 * downclock feature.
4745 has_reduced_clock = limit->find_pll(limit, crtc,
4746 dev_priv->lvds_downclock,
4752 if (is_sdvo && is_tv)
4753 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4756 i8xx_update_pll(crtc, adjusted_mode, &clock,
4757 has_reduced_clock ? &reduced_clock : NULL,
4759 else if (IS_VALLEYVIEW(dev))
4760 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4761 has_reduced_clock ? &reduced_clock : NULL,
4764 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4765 has_reduced_clock ? &reduced_clock : NULL,
4768 /* setup pipeconf */
4769 pipeconf = I915_READ(PIPECONF(pipe));
4771 /* Set up the display plane register */
4772 dspcntr = DISPPLANE_GAMMA_ENABLE;
4775 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4777 dspcntr |= DISPPLANE_SEL_PIPE_B;
4779 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4780 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4783 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4787 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4788 pipeconf |= PIPECONF_DOUBLE_WIDE;
4790 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4793 /* default to 8bpc */
4794 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4796 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4797 pipeconf |= PIPECONF_BPP_6 |
4798 PIPECONF_DITHER_EN |
4799 PIPECONF_DITHER_TYPE_SP;
4803 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4804 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4805 pipeconf |= PIPECONF_BPP_6 |
4807 I965_PIPECONF_ACTIVE;
4811 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4812 drm_mode_debug_printmodeline(mode);
4814 if (HAS_PIPE_CXSR(dev)) {
4815 if (intel_crtc->lowfreq_avail) {
4816 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4817 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4819 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4820 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4824 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4825 if (!IS_GEN2(dev) &&
4826 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4827 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4829 pipeconf |= PIPECONF_PROGRESSIVE;
4831 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4833 /* pipesrc and dspsize control the size that is scaled from,
4834 * which should always be the user's requested size.
4836 I915_WRITE(DSPSIZE(plane),
4837 ((mode->vdisplay - 1) << 16) |
4838 (mode->hdisplay - 1));
4839 I915_WRITE(DSPPOS(plane), 0);
4841 I915_WRITE(PIPECONF(pipe), pipeconf);
4842 POSTING_READ(PIPECONF(pipe));
4843 intel_enable_pipe(dev_priv, pipe, false);
4845 intel_wait_for_vblank(dev, pipe);
4847 I915_WRITE(DSPCNTR(plane), dspcntr);
4848 POSTING_READ(DSPCNTR(plane));
4850 ret = intel_pipe_set_base(crtc, x, y, fb);
4852 intel_update_watermarks(dev);
4857 static void ironlake_init_pch_refclk(struct drm_device *dev)
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 struct drm_mode_config *mode_config = &dev->mode_config;
4861 struct intel_encoder *encoder;
4863 bool has_lvds = false;
4864 bool has_cpu_edp = false;
4865 bool has_pch_edp = false;
4866 bool has_panel = false;
4867 bool has_ck505 = false;
4868 bool can_ssc = false;
4870 /* We need to take the global config into account */
4871 list_for_each_entry(encoder, &mode_config->encoder_list,
4873 switch (encoder->type) {
4874 case INTEL_OUTPUT_LVDS:
4878 case INTEL_OUTPUT_EDP:
4880 if (intel_encoder_is_pch_edp(&encoder->base))
4888 if (HAS_PCH_IBX(dev)) {
4889 has_ck505 = dev_priv->display_clock_mode;
4890 can_ssc = has_ck505;
4896 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4897 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4900 /* Ironlake: try to setup display ref clock before DPLL
4901 * enabling. This is only under driver's control after
4902 * PCH B stepping, previous chipset stepping should be
4903 * ignoring this setting.
4905 temp = I915_READ(PCH_DREF_CONTROL);
4906 /* Always enable nonspread source */
4907 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4910 temp |= DREF_NONSPREAD_CK505_ENABLE;
4912 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4915 temp &= ~DREF_SSC_SOURCE_MASK;
4916 temp |= DREF_SSC_SOURCE_ENABLE;
4918 /* SSC must be turned on before enabling the CPU output */
4919 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4920 DRM_DEBUG_KMS("Using SSC on panel\n");
4921 temp |= DREF_SSC1_ENABLE;
4923 temp &= ~DREF_SSC1_ENABLE;
4925 /* Get SSC going before enabling the outputs */
4926 I915_WRITE(PCH_DREF_CONTROL, temp);
4927 POSTING_READ(PCH_DREF_CONTROL);
4930 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4932 /* Enable CPU source on CPU attached eDP */
4934 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4935 DRM_DEBUG_KMS("Using SSC on eDP\n");
4936 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4939 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4941 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4943 I915_WRITE(PCH_DREF_CONTROL, temp);
4944 POSTING_READ(PCH_DREF_CONTROL);
4947 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4949 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4951 /* Turn off CPU output */
4952 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4954 I915_WRITE(PCH_DREF_CONTROL, temp);
4955 POSTING_READ(PCH_DREF_CONTROL);
4958 /* Turn off the SSC source */
4959 temp &= ~DREF_SSC_SOURCE_MASK;
4960 temp |= DREF_SSC_SOURCE_DISABLE;
4963 temp &= ~ DREF_SSC1_ENABLE;
4965 I915_WRITE(PCH_DREF_CONTROL, temp);
4966 POSTING_READ(PCH_DREF_CONTROL);
4971 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4972 static void lpt_init_pch_refclk(struct drm_device *dev)
4974 struct drm_i915_private *dev_priv = dev->dev_private;
4975 struct drm_mode_config *mode_config = &dev->mode_config;
4976 struct intel_encoder *encoder;
4977 bool has_vga = false;
4978 bool is_sdv = false;
4981 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4982 switch (encoder->type) {
4983 case INTEL_OUTPUT_ANALOG:
4992 /* XXX: Rip out SDV support once Haswell ships for real. */
4993 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4996 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4997 tmp &= ~SBI_SSCCTL_DISABLE;
4998 tmp |= SBI_SSCCTL_PATHALT;
4999 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5003 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5004 tmp &= ~SBI_SSCCTL_PATHALT;
5005 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5008 tmp = I915_READ(SOUTH_CHICKEN2);
5009 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5010 I915_WRITE(SOUTH_CHICKEN2, tmp);
5012 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5013 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5014 DRM_ERROR("FDI mPHY reset assert timeout\n");
5016 tmp = I915_READ(SOUTH_CHICKEN2);
5017 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5018 I915_WRITE(SOUTH_CHICKEN2, tmp);
5020 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5021 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5023 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5026 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5027 tmp &= ~(0xFF << 24);
5028 tmp |= (0x12 << 24);
5029 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5032 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5034 tmp |= (1 << 6) | (1 << 0);
5035 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5039 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5041 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5044 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5046 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5048 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5050 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5053 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5054 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5055 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5057 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5058 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5059 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5061 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5063 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5065 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5067 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5070 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5071 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5072 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5074 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5075 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5076 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5079 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5082 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5084 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5087 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5090 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5093 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5095 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5098 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5100 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5101 tmp &= ~(0xFF << 16);
5102 tmp |= (0x1C << 16);
5103 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5105 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5106 tmp &= ~(0xFF << 16);
5107 tmp |= (0x1C << 16);
5108 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5111 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5113 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5115 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5117 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5119 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5120 tmp &= ~(0xF << 28);
5122 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5124 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5125 tmp &= ~(0xF << 28);
5127 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5130 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5131 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5132 tmp |= SBI_DBUFF0_ENABLE;
5133 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5137 * Initialize reference clocks when the driver loads
5139 void intel_init_pch_refclk(struct drm_device *dev)
5141 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5142 ironlake_init_pch_refclk(dev);
5143 else if (HAS_PCH_LPT(dev))
5144 lpt_init_pch_refclk(dev);
5147 static int ironlake_get_refclk(struct drm_crtc *crtc)
5149 struct drm_device *dev = crtc->dev;
5150 struct drm_i915_private *dev_priv = dev->dev_private;
5151 struct intel_encoder *encoder;
5152 struct intel_encoder *edp_encoder = NULL;
5153 int num_connectors = 0;
5154 bool is_lvds = false;
5156 for_each_encoder_on_crtc(dev, crtc, encoder) {
5157 switch (encoder->type) {
5158 case INTEL_OUTPUT_LVDS:
5161 case INTEL_OUTPUT_EDP:
5162 edp_encoder = encoder;
5168 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5169 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5170 dev_priv->lvds_ssc_freq);
5171 return dev_priv->lvds_ssc_freq * 1000;
5177 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5178 struct drm_display_mode *adjusted_mode,
5181 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5183 int pipe = intel_crtc->pipe;
5186 val = I915_READ(PIPECONF(pipe));
5188 val &= ~PIPE_BPC_MASK;
5189 switch (intel_crtc->bpp) {
5203 /* Case prevented by intel_choose_pipe_bpp_dither. */
5207 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5209 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5211 val &= ~PIPECONF_INTERLACE_MASK;
5212 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5213 val |= PIPECONF_INTERLACED_ILK;
5215 val |= PIPECONF_PROGRESSIVE;
5217 I915_WRITE(PIPECONF(pipe), val);
5218 POSTING_READ(PIPECONF(pipe));
5221 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5222 struct drm_display_mode *adjusted_mode,
5225 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5227 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5230 val = I915_READ(PIPECONF(cpu_transcoder));
5232 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5234 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5236 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5237 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5238 val |= PIPECONF_INTERLACED_ILK;
5240 val |= PIPECONF_PROGRESSIVE;
5242 I915_WRITE(PIPECONF(cpu_transcoder), val);
5243 POSTING_READ(PIPECONF(cpu_transcoder));
5246 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5247 struct drm_display_mode *adjusted_mode,
5248 intel_clock_t *clock,
5249 bool *has_reduced_clock,
5250 intel_clock_t *reduced_clock)
5252 struct drm_device *dev = crtc->dev;
5253 struct drm_i915_private *dev_priv = dev->dev_private;
5254 struct intel_encoder *intel_encoder;
5256 const intel_limit_t *limit;
5257 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5259 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5260 switch (intel_encoder->type) {
5261 case INTEL_OUTPUT_LVDS:
5264 case INTEL_OUTPUT_SDVO:
5265 case INTEL_OUTPUT_HDMI:
5267 if (intel_encoder->needs_tv_clock)
5270 case INTEL_OUTPUT_TVOUT:
5276 refclk = ironlake_get_refclk(crtc);
5279 * Returns a set of divisors for the desired target clock with the given
5280 * refclk, or FALSE. The returned values represent the clock equation:
5281 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5283 limit = intel_limit(crtc, refclk);
5284 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5289 if (is_lvds && dev_priv->lvds_downclock_avail) {
5291 * Ensure we match the reduced clock's P to the target clock.
5292 * If the clocks don't match, we can't switch the display clock
5293 * by using the FP0/FP1. In such case we will disable the LVDS
5294 * downclock feature.
5296 *has_reduced_clock = limit->find_pll(limit, crtc,
5297 dev_priv->lvds_downclock,
5303 if (is_sdvo && is_tv)
5304 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5309 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5314 temp = I915_READ(SOUTH_CHICKEN1);
5315 if (temp & FDI_BC_BIFURCATION_SELECT)
5318 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5319 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5321 temp |= FDI_BC_BIFURCATION_SELECT;
5322 DRM_DEBUG_KMS("enabling fdi C rx\n");
5323 I915_WRITE(SOUTH_CHICKEN1, temp);
5324 POSTING_READ(SOUTH_CHICKEN1);
5327 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5329 struct drm_device *dev = intel_crtc->base.dev;
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 struct intel_crtc *pipe_B_crtc =
5332 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5334 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5335 intel_crtc->pipe, intel_crtc->fdi_lanes);
5336 if (intel_crtc->fdi_lanes > 4) {
5337 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5338 intel_crtc->pipe, intel_crtc->fdi_lanes);
5339 /* Clamp lanes to avoid programming the hw with bogus values. */
5340 intel_crtc->fdi_lanes = 4;
5345 if (dev_priv->num_pipe == 2)
5348 switch (intel_crtc->pipe) {
5352 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5353 intel_crtc->fdi_lanes > 2) {
5354 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5355 intel_crtc->pipe, intel_crtc->fdi_lanes);
5356 /* Clamp lanes to avoid programming the hw with bogus values. */
5357 intel_crtc->fdi_lanes = 2;
5362 if (intel_crtc->fdi_lanes > 2)
5363 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5365 cpt_enable_fdi_bc_bifurcation(dev);
5369 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5370 if (intel_crtc->fdi_lanes > 2) {
5371 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5372 intel_crtc->pipe, intel_crtc->fdi_lanes);
5373 /* Clamp lanes to avoid programming the hw with bogus values. */
5374 intel_crtc->fdi_lanes = 2;
5379 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5383 cpt_enable_fdi_bc_bifurcation(dev);
5391 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5394 * Account for spread spectrum to avoid
5395 * oversubscribing the link. Max center spread
5396 * is 2.5%; use 5% for safety's sake.
5398 u32 bps = target_clock * bpp * 21 / 20;
5399 return bps / (link_bw * 8) + 1;
5402 static void ironlake_set_m_n(struct drm_crtc *crtc,
5403 struct drm_display_mode *mode,
5404 struct drm_display_mode *adjusted_mode)
5406 struct drm_device *dev = crtc->dev;
5407 struct drm_i915_private *dev_priv = dev->dev_private;
5408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5409 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5410 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5411 struct fdi_m_n m_n = {0};
5412 int target_clock, pixel_multiplier, lane, link_bw;
5413 bool is_dp = false, is_cpu_edp = false;
5415 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5416 switch (intel_encoder->type) {
5417 case INTEL_OUTPUT_DISPLAYPORT:
5420 case INTEL_OUTPUT_EDP:
5422 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5424 edp_encoder = intel_encoder;
5430 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5432 /* CPU eDP doesn't require FDI link, so just set DP M/N
5433 according to current link config */
5435 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5437 /* FDI is a binary signal running at ~2.7GHz, encoding
5438 * each output octet as 10 bits. The actual frequency
5439 * is stored as a divider into a 100MHz clock, and the
5440 * mode pixel clock is stored in units of 1KHz.
5441 * Hence the bw of each lane in terms of the mode signal
5444 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5447 /* [e]DP over FDI requires target mode clock instead of link clock. */
5449 target_clock = intel_edp_target_clock(edp_encoder, mode);
5451 target_clock = mode->clock;
5453 target_clock = adjusted_mode->clock;
5456 lane = ironlake_get_lanes_required(target_clock, link_bw,
5459 intel_crtc->fdi_lanes = lane;
5461 if (pixel_multiplier > 1)
5462 link_bw *= pixel_multiplier;
5463 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5466 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5467 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5468 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5469 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5472 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5473 struct drm_display_mode *adjusted_mode,
5474 intel_clock_t *clock, u32 fp)
5476 struct drm_crtc *crtc = &intel_crtc->base;
5477 struct drm_device *dev = crtc->dev;
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479 struct intel_encoder *intel_encoder;
5481 int factor, pixel_multiplier, num_connectors = 0;
5482 bool is_lvds = false, is_sdvo = false, is_tv = false;
5483 bool is_dp = false, is_cpu_edp = false;
5485 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5486 switch (intel_encoder->type) {
5487 case INTEL_OUTPUT_LVDS:
5490 case INTEL_OUTPUT_SDVO:
5491 case INTEL_OUTPUT_HDMI:
5493 if (intel_encoder->needs_tv_clock)
5496 case INTEL_OUTPUT_TVOUT:
5499 case INTEL_OUTPUT_DISPLAYPORT:
5502 case INTEL_OUTPUT_EDP:
5504 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5512 /* Enable autotuning of the PLL clock (if permissible) */
5515 if ((intel_panel_use_ssc(dev_priv) &&
5516 dev_priv->lvds_ssc_freq == 100) ||
5517 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5519 } else if (is_sdvo && is_tv)
5522 if (clock->m < factor * clock->n)
5528 dpll |= DPLLB_MODE_LVDS;
5530 dpll |= DPLLB_MODE_DAC_SERIAL;
5532 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5533 if (pixel_multiplier > 1) {
5534 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5536 dpll |= DPLL_DVO_HIGH_SPEED;
5538 if (is_dp && !is_cpu_edp)
5539 dpll |= DPLL_DVO_HIGH_SPEED;
5541 /* compute bitmask from p1 value */
5542 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5544 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5546 switch (clock->p2) {
5548 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5551 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5554 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5557 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5561 if (is_sdvo && is_tv)
5562 dpll |= PLL_REF_INPUT_TVCLKINBC;
5564 /* XXX: just matching BIOS for now */
5565 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5567 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5568 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5570 dpll |= PLL_REF_INPUT_DREFCLK;
5575 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5576 struct drm_display_mode *mode,
5577 struct drm_display_mode *adjusted_mode,
5579 struct drm_framebuffer *fb)
5581 struct drm_device *dev = crtc->dev;
5582 struct drm_i915_private *dev_priv = dev->dev_private;
5583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5584 int pipe = intel_crtc->pipe;
5585 int plane = intel_crtc->plane;
5586 int num_connectors = 0;
5587 intel_clock_t clock, reduced_clock;
5588 u32 dpll, fp = 0, fp2 = 0;
5589 bool ok, has_reduced_clock = false;
5590 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5591 struct intel_encoder *encoder;
5594 bool dither, fdi_config_ok;
5596 for_each_encoder_on_crtc(dev, crtc, encoder) {
5597 switch (encoder->type) {
5598 case INTEL_OUTPUT_LVDS:
5601 case INTEL_OUTPUT_DISPLAYPORT:
5604 case INTEL_OUTPUT_EDP:
5606 if (!intel_encoder_is_pch_edp(&encoder->base))
5614 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5615 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5617 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5618 &has_reduced_clock, &reduced_clock);
5620 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5624 /* Ensure that the cursor is valid for the new mode before changing... */
5625 intel_crtc_update_cursor(crtc, true);
5627 /* determine panel color depth */
5628 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5630 if (is_lvds && dev_priv->lvds_dither)
5633 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5634 if (has_reduced_clock)
5635 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5638 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5640 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5641 drm_mode_debug_printmodeline(mode);
5643 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5645 struct intel_pch_pll *pll;
5647 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5649 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5654 intel_put_pch_pll(intel_crtc);
5656 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5657 * This is an exception to the general rule that mode_set doesn't turn
5661 temp = I915_READ(PCH_LVDS);
5662 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5663 if (HAS_PCH_CPT(dev)) {
5664 temp &= ~PORT_TRANS_SEL_MASK;
5665 temp |= PORT_TRANS_SEL_CPT(pipe);
5668 temp |= LVDS_PIPEB_SELECT;
5670 temp &= ~LVDS_PIPEB_SELECT;
5673 /* set the corresponsding LVDS_BORDER bit */
5674 temp |= dev_priv->lvds_border_bits;
5675 /* Set the B0-B3 data pairs corresponding to whether we're going to
5676 * set the DPLLs for dual-channel mode or not.
5679 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5681 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5683 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5684 * appropriately here, but we need to look more thoroughly into how
5685 * panels behave in the two modes.
5687 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5688 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5689 temp |= LVDS_HSYNC_POLARITY;
5690 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5691 temp |= LVDS_VSYNC_POLARITY;
5692 I915_WRITE(PCH_LVDS, temp);
5695 if (is_dp && !is_cpu_edp) {
5696 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5698 /* For non-DP output, clear any trans DP clock recovery setting.*/
5699 I915_WRITE(TRANSDATA_M1(pipe), 0);
5700 I915_WRITE(TRANSDATA_N1(pipe), 0);
5701 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5702 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5705 if (intel_crtc->pch_pll) {
5706 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5708 /* Wait for the clocks to stabilize. */
5709 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5712 /* The pixel multiplier can only be updated once the
5713 * DPLL is enabled and the clocks are stable.
5715 * So write it again.
5717 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5720 intel_crtc->lowfreq_avail = false;
5721 if (intel_crtc->pch_pll) {
5722 if (is_lvds && has_reduced_clock && i915_powersave) {
5723 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5724 intel_crtc->lowfreq_avail = true;
5726 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5730 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5732 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5733 * ironlake_check_fdi_lanes. */
5734 ironlake_set_m_n(crtc, mode, adjusted_mode);
5736 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5739 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5741 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5743 intel_wait_for_vblank(dev, pipe);
5745 /* Set up the display plane register */
5746 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5747 POSTING_READ(DSPCNTR(plane));
5749 ret = intel_pipe_set_base(crtc, x, y, fb);
5751 intel_update_watermarks(dev);
5753 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5755 return fdi_config_ok ? ret : -EINVAL;
5758 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5759 struct drm_display_mode *mode,
5760 struct drm_display_mode *adjusted_mode,
5762 struct drm_framebuffer *fb)
5764 struct drm_device *dev = crtc->dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767 int pipe = intel_crtc->pipe;
5768 int plane = intel_crtc->plane;
5769 int num_connectors = 0;
5770 intel_clock_t clock, reduced_clock;
5771 u32 dpll = 0, fp = 0, fp2 = 0;
5772 bool ok, has_reduced_clock = false;
5773 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5774 struct intel_encoder *encoder;
5779 for_each_encoder_on_crtc(dev, crtc, encoder) {
5780 switch (encoder->type) {
5781 case INTEL_OUTPUT_LVDS:
5784 case INTEL_OUTPUT_DISPLAYPORT:
5787 case INTEL_OUTPUT_EDP:
5789 if (!intel_encoder_is_pch_edp(&encoder->base))
5798 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5800 intel_crtc->cpu_transcoder = pipe;
5802 /* We are not sure yet this won't happen. */
5803 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5804 INTEL_PCH_TYPE(dev));
5806 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5807 num_connectors, pipe_name(pipe));
5809 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5810 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5812 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5814 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5817 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5818 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5822 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5827 /* Ensure that the cursor is valid for the new mode before changing... */
5828 intel_crtc_update_cursor(crtc, true);
5830 /* determine panel color depth */
5831 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5833 if (is_lvds && dev_priv->lvds_dither)
5836 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5837 drm_mode_debug_printmodeline(mode);
5839 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5840 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5841 if (has_reduced_clock)
5842 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5845 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5848 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5849 * own on pre-Haswell/LPT generation */
5851 struct intel_pch_pll *pll;
5853 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5855 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5860 intel_put_pch_pll(intel_crtc);
5862 /* The LVDS pin pair needs to be on before the DPLLs are
5863 * enabled. This is an exception to the general rule that
5864 * mode_set doesn't turn things on.
5867 temp = I915_READ(PCH_LVDS);
5868 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5869 if (HAS_PCH_CPT(dev)) {
5870 temp &= ~PORT_TRANS_SEL_MASK;
5871 temp |= PORT_TRANS_SEL_CPT(pipe);
5874 temp |= LVDS_PIPEB_SELECT;
5876 temp &= ~LVDS_PIPEB_SELECT;
5879 /* set the corresponsding LVDS_BORDER bit */
5880 temp |= dev_priv->lvds_border_bits;
5881 /* Set the B0-B3 data pairs corresponding to whether
5882 * we're going to set the DPLLs for dual-channel mode or
5886 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5888 temp &= ~(LVDS_B0B3_POWER_UP |
5889 LVDS_CLKB_POWER_UP);
5891 /* It would be nice to set 24 vs 18-bit mode
5892 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5893 * look more thoroughly into how panels behave in the
5896 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5897 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5898 temp |= LVDS_HSYNC_POLARITY;
5899 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5900 temp |= LVDS_VSYNC_POLARITY;
5901 I915_WRITE(PCH_LVDS, temp);
5905 if (is_dp && !is_cpu_edp) {
5906 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5908 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5909 /* For non-DP output, clear any trans DP clock recovery
5911 I915_WRITE(TRANSDATA_M1(pipe), 0);
5912 I915_WRITE(TRANSDATA_N1(pipe), 0);
5913 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5914 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5918 intel_crtc->lowfreq_avail = false;
5919 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5920 if (intel_crtc->pch_pll) {
5921 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5923 /* Wait for the clocks to stabilize. */
5924 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5927 /* The pixel multiplier can only be updated once the
5928 * DPLL is enabled and the clocks are stable.
5930 * So write it again.
5932 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5935 if (intel_crtc->pch_pll) {
5936 if (is_lvds && has_reduced_clock && i915_powersave) {
5937 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5938 intel_crtc->lowfreq_avail = true;
5940 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5945 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5947 if (!is_dp || is_cpu_edp)
5948 ironlake_set_m_n(crtc, mode, adjusted_mode);
5950 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5952 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5954 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5956 /* Set up the display plane register */
5957 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5958 POSTING_READ(DSPCNTR(plane));
5960 ret = intel_pipe_set_base(crtc, x, y, fb);
5962 intel_update_watermarks(dev);
5964 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5969 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5970 struct drm_display_mode *mode,
5971 struct drm_display_mode *adjusted_mode,
5973 struct drm_framebuffer *fb)
5975 struct drm_device *dev = crtc->dev;
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977 struct drm_encoder_helper_funcs *encoder_funcs;
5978 struct intel_encoder *encoder;
5979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5980 int pipe = intel_crtc->pipe;
5983 drm_vblank_pre_modeset(dev, pipe);
5985 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5987 drm_vblank_post_modeset(dev, pipe);
5992 for_each_encoder_on_crtc(dev, crtc, encoder) {
5993 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5994 encoder->base.base.id,
5995 drm_get_encoder_name(&encoder->base),
5996 mode->base.id, mode->name);
5997 encoder_funcs = encoder->base.helper_private;
5998 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6004 static bool intel_eld_uptodate(struct drm_connector *connector,
6005 int reg_eldv, uint32_t bits_eldv,
6006 int reg_elda, uint32_t bits_elda,
6009 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6010 uint8_t *eld = connector->eld;
6013 i = I915_READ(reg_eldv);
6022 i = I915_READ(reg_elda);
6024 I915_WRITE(reg_elda, i);
6026 for (i = 0; i < eld[2]; i++)
6027 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6033 static void g4x_write_eld(struct drm_connector *connector,
6034 struct drm_crtc *crtc)
6036 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6037 uint8_t *eld = connector->eld;
6042 i = I915_READ(G4X_AUD_VID_DID);
6044 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6045 eldv = G4X_ELDV_DEVCL_DEVBLC;
6047 eldv = G4X_ELDV_DEVCTG;
6049 if (intel_eld_uptodate(connector,
6050 G4X_AUD_CNTL_ST, eldv,
6051 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6052 G4X_HDMIW_HDMIEDID))
6055 i = I915_READ(G4X_AUD_CNTL_ST);
6056 i &= ~(eldv | G4X_ELD_ADDR);
6057 len = (i >> 9) & 0x1f; /* ELD buffer size */
6058 I915_WRITE(G4X_AUD_CNTL_ST, i);
6063 len = min_t(uint8_t, eld[2], len);
6064 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6065 for (i = 0; i < len; i++)
6066 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6068 i = I915_READ(G4X_AUD_CNTL_ST);
6070 I915_WRITE(G4X_AUD_CNTL_ST, i);
6073 static void haswell_write_eld(struct drm_connector *connector,
6074 struct drm_crtc *crtc)
6076 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6077 uint8_t *eld = connector->eld;
6078 struct drm_device *dev = crtc->dev;
6082 int pipe = to_intel_crtc(crtc)->pipe;
6085 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6086 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6087 int aud_config = HSW_AUD_CFG(pipe);
6088 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6091 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6093 /* Audio output enable */
6094 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6095 tmp = I915_READ(aud_cntrl_st2);
6096 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6097 I915_WRITE(aud_cntrl_st2, tmp);
6099 /* Wait for 1 vertical blank */
6100 intel_wait_for_vblank(dev, pipe);
6102 /* Set ELD valid state */
6103 tmp = I915_READ(aud_cntrl_st2);
6104 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6105 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6106 I915_WRITE(aud_cntrl_st2, tmp);
6107 tmp = I915_READ(aud_cntrl_st2);
6108 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6110 /* Enable HDMI mode */
6111 tmp = I915_READ(aud_config);
6112 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6113 /* clear N_programing_enable and N_value_index */
6114 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6115 I915_WRITE(aud_config, tmp);
6117 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6119 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6121 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6122 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6123 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6124 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6126 I915_WRITE(aud_config, 0);
6128 if (intel_eld_uptodate(connector,
6129 aud_cntrl_st2, eldv,
6130 aud_cntl_st, IBX_ELD_ADDRESS,
6134 i = I915_READ(aud_cntrl_st2);
6136 I915_WRITE(aud_cntrl_st2, i);
6141 i = I915_READ(aud_cntl_st);
6142 i &= ~IBX_ELD_ADDRESS;
6143 I915_WRITE(aud_cntl_st, i);
6144 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6145 DRM_DEBUG_DRIVER("port num:%d\n", i);
6147 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6148 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6149 for (i = 0; i < len; i++)
6150 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6152 i = I915_READ(aud_cntrl_st2);
6154 I915_WRITE(aud_cntrl_st2, i);
6158 static void ironlake_write_eld(struct drm_connector *connector,
6159 struct drm_crtc *crtc)
6161 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6162 uint8_t *eld = connector->eld;
6170 int pipe = to_intel_crtc(crtc)->pipe;
6172 if (HAS_PCH_IBX(connector->dev)) {
6173 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6174 aud_config = IBX_AUD_CFG(pipe);
6175 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6176 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6178 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6179 aud_config = CPT_AUD_CFG(pipe);
6180 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6181 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6184 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6186 i = I915_READ(aud_cntl_st);
6187 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6189 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6190 /* operate blindly on all ports */
6191 eldv = IBX_ELD_VALIDB;
6192 eldv |= IBX_ELD_VALIDB << 4;
6193 eldv |= IBX_ELD_VALIDB << 8;
6195 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6196 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6199 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6200 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6201 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6202 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6204 I915_WRITE(aud_config, 0);
6206 if (intel_eld_uptodate(connector,
6207 aud_cntrl_st2, eldv,
6208 aud_cntl_st, IBX_ELD_ADDRESS,
6212 i = I915_READ(aud_cntrl_st2);
6214 I915_WRITE(aud_cntrl_st2, i);
6219 i = I915_READ(aud_cntl_st);
6220 i &= ~IBX_ELD_ADDRESS;
6221 I915_WRITE(aud_cntl_st, i);
6223 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6224 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6225 for (i = 0; i < len; i++)
6226 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6228 i = I915_READ(aud_cntrl_st2);
6230 I915_WRITE(aud_cntrl_st2, i);
6233 void intel_write_eld(struct drm_encoder *encoder,
6234 struct drm_display_mode *mode)
6236 struct drm_crtc *crtc = encoder->crtc;
6237 struct drm_connector *connector;
6238 struct drm_device *dev = encoder->dev;
6239 struct drm_i915_private *dev_priv = dev->dev_private;
6241 connector = drm_select_eld(encoder, mode);
6245 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6247 drm_get_connector_name(connector),
6248 connector->encoder->base.id,
6249 drm_get_encoder_name(connector->encoder));
6251 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6253 if (dev_priv->display.write_eld)
6254 dev_priv->display.write_eld(connector, crtc);
6257 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6258 void intel_crtc_load_lut(struct drm_crtc *crtc)
6260 struct drm_device *dev = crtc->dev;
6261 struct drm_i915_private *dev_priv = dev->dev_private;
6262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6263 int palreg = PALETTE(intel_crtc->pipe);
6266 /* The clocks have to be on to load the palette. */
6267 if (!crtc->enabled || !intel_crtc->active)
6270 /* use legacy palette for Ironlake */
6271 if (HAS_PCH_SPLIT(dev))
6272 palreg = LGC_PALETTE(intel_crtc->pipe);
6274 for (i = 0; i < 256; i++) {
6275 I915_WRITE(palreg + 4 * i,
6276 (intel_crtc->lut_r[i] << 16) |
6277 (intel_crtc->lut_g[i] << 8) |
6278 intel_crtc->lut_b[i]);
6282 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6284 struct drm_device *dev = crtc->dev;
6285 struct drm_i915_private *dev_priv = dev->dev_private;
6286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6287 bool visible = base != 0;
6290 if (intel_crtc->cursor_visible == visible)
6293 cntl = I915_READ(_CURACNTR);
6295 /* On these chipsets we can only modify the base whilst
6296 * the cursor is disabled.
6298 I915_WRITE(_CURABASE, base);
6300 cntl &= ~(CURSOR_FORMAT_MASK);
6301 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6302 cntl |= CURSOR_ENABLE |
6303 CURSOR_GAMMA_ENABLE |
6306 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6307 I915_WRITE(_CURACNTR, cntl);
6309 intel_crtc->cursor_visible = visible;
6312 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6314 struct drm_device *dev = crtc->dev;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6317 int pipe = intel_crtc->pipe;
6318 bool visible = base != 0;
6320 if (intel_crtc->cursor_visible != visible) {
6321 uint32_t cntl = I915_READ(CURCNTR(pipe));
6323 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6324 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6325 cntl |= pipe << 28; /* Connect to correct pipe */
6327 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6328 cntl |= CURSOR_MODE_DISABLE;
6330 I915_WRITE(CURCNTR(pipe), cntl);
6332 intel_crtc->cursor_visible = visible;
6334 /* and commit changes on next vblank */
6335 I915_WRITE(CURBASE(pipe), base);
6338 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6340 struct drm_device *dev = crtc->dev;
6341 struct drm_i915_private *dev_priv = dev->dev_private;
6342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6343 int pipe = intel_crtc->pipe;
6344 bool visible = base != 0;
6346 if (intel_crtc->cursor_visible != visible) {
6347 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6349 cntl &= ~CURSOR_MODE;
6350 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6352 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6353 cntl |= CURSOR_MODE_DISABLE;
6355 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6357 intel_crtc->cursor_visible = visible;
6359 /* and commit changes on next vblank */
6360 I915_WRITE(CURBASE_IVB(pipe), base);
6363 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6364 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6367 struct drm_device *dev = crtc->dev;
6368 struct drm_i915_private *dev_priv = dev->dev_private;
6369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6370 int pipe = intel_crtc->pipe;
6371 int x = intel_crtc->cursor_x;
6372 int y = intel_crtc->cursor_y;
6378 if (on && crtc->enabled && crtc->fb) {
6379 base = intel_crtc->cursor_addr;
6380 if (x > (int) crtc->fb->width)
6383 if (y > (int) crtc->fb->height)
6389 if (x + intel_crtc->cursor_width < 0)
6392 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6395 pos |= x << CURSOR_X_SHIFT;
6398 if (y + intel_crtc->cursor_height < 0)
6401 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6404 pos |= y << CURSOR_Y_SHIFT;
6406 visible = base != 0;
6407 if (!visible && !intel_crtc->cursor_visible)
6410 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6411 I915_WRITE(CURPOS_IVB(pipe), pos);
6412 ivb_update_cursor(crtc, base);
6414 I915_WRITE(CURPOS(pipe), pos);
6415 if (IS_845G(dev) || IS_I865G(dev))
6416 i845_update_cursor(crtc, base);
6418 i9xx_update_cursor(crtc, base);
6422 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6423 struct drm_file *file,
6425 uint32_t width, uint32_t height)
6427 struct drm_device *dev = crtc->dev;
6428 struct drm_i915_private *dev_priv = dev->dev_private;
6429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6430 struct drm_i915_gem_object *obj;
6434 /* if we want to turn off the cursor ignore width and height */
6436 DRM_DEBUG_KMS("cursor off\n");
6439 mutex_lock(&dev->struct_mutex);
6443 /* Currently we only support 64x64 cursors */
6444 if (width != 64 || height != 64) {
6445 DRM_ERROR("we currently only support 64x64 cursors\n");
6449 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6450 if (&obj->base == NULL)
6453 if (obj->base.size < width * height * 4) {
6454 DRM_ERROR("buffer is to small\n");
6459 /* we only need to pin inside GTT if cursor is non-phy */
6460 mutex_lock(&dev->struct_mutex);
6461 if (!dev_priv->info->cursor_needs_physical) {
6462 if (obj->tiling_mode) {
6463 DRM_ERROR("cursor cannot be tiled\n");
6468 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6470 DRM_ERROR("failed to move cursor bo into the GTT\n");
6474 ret = i915_gem_object_put_fence(obj);
6476 DRM_ERROR("failed to release fence for cursor");
6480 addr = obj->gtt_offset;
6482 int align = IS_I830(dev) ? 16 * 1024 : 256;
6483 ret = i915_gem_attach_phys_object(dev, obj,
6484 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6487 DRM_ERROR("failed to attach phys object\n");
6490 addr = obj->phys_obj->handle->busaddr;
6494 I915_WRITE(CURSIZE, (height << 12) | width);
6497 if (intel_crtc->cursor_bo) {
6498 if (dev_priv->info->cursor_needs_physical) {
6499 if (intel_crtc->cursor_bo != obj)
6500 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6502 i915_gem_object_unpin(intel_crtc->cursor_bo);
6503 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6506 mutex_unlock(&dev->struct_mutex);
6508 intel_crtc->cursor_addr = addr;
6509 intel_crtc->cursor_bo = obj;
6510 intel_crtc->cursor_width = width;
6511 intel_crtc->cursor_height = height;
6513 intel_crtc_update_cursor(crtc, true);
6517 i915_gem_object_unpin(obj);
6519 mutex_unlock(&dev->struct_mutex);
6521 drm_gem_object_unreference_unlocked(&obj->base);
6525 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6529 intel_crtc->cursor_x = x;
6530 intel_crtc->cursor_y = y;
6532 intel_crtc_update_cursor(crtc, true);
6537 /** Sets the color ramps on behalf of RandR */
6538 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6539 u16 blue, int regno)
6541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6543 intel_crtc->lut_r[regno] = red >> 8;
6544 intel_crtc->lut_g[regno] = green >> 8;
6545 intel_crtc->lut_b[regno] = blue >> 8;
6548 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6549 u16 *blue, int regno)
6551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6553 *red = intel_crtc->lut_r[regno] << 8;
6554 *green = intel_crtc->lut_g[regno] << 8;
6555 *blue = intel_crtc->lut_b[regno] << 8;
6558 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6559 u16 *blue, uint32_t start, uint32_t size)
6561 int end = (start + size > 256) ? 256 : start + size, i;
6562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6564 for (i = start; i < end; i++) {
6565 intel_crtc->lut_r[i] = red[i] >> 8;
6566 intel_crtc->lut_g[i] = green[i] >> 8;
6567 intel_crtc->lut_b[i] = blue[i] >> 8;
6570 intel_crtc_load_lut(crtc);
6574 * Get a pipe with a simple mode set on it for doing load-based monitor
6577 * It will be up to the load-detect code to adjust the pipe as appropriate for
6578 * its requirements. The pipe will be connected to no other encoders.
6580 * Currently this code will only succeed if there is a pipe with no encoders
6581 * configured for it. In the future, it could choose to temporarily disable
6582 * some outputs to free up a pipe for its use.
6584 * \return crtc, or NULL if no pipes are available.
6587 /* VESA 640x480x72Hz mode to set on the pipe */
6588 static struct drm_display_mode load_detect_mode = {
6589 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6590 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6593 static struct drm_framebuffer *
6594 intel_framebuffer_create(struct drm_device *dev,
6595 struct drm_mode_fb_cmd2 *mode_cmd,
6596 struct drm_i915_gem_object *obj)
6598 struct intel_framebuffer *intel_fb;
6601 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6603 drm_gem_object_unreference_unlocked(&obj->base);
6604 return ERR_PTR(-ENOMEM);
6607 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6609 drm_gem_object_unreference_unlocked(&obj->base);
6611 return ERR_PTR(ret);
6614 return &intel_fb->base;
6618 intel_framebuffer_pitch_for_width(int width, int bpp)
6620 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6621 return ALIGN(pitch, 64);
6625 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6627 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6628 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6631 static struct drm_framebuffer *
6632 intel_framebuffer_create_for_mode(struct drm_device *dev,
6633 struct drm_display_mode *mode,
6636 struct drm_i915_gem_object *obj;
6637 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6639 obj = i915_gem_alloc_object(dev,
6640 intel_framebuffer_size_for_mode(mode, bpp));
6642 return ERR_PTR(-ENOMEM);
6644 mode_cmd.width = mode->hdisplay;
6645 mode_cmd.height = mode->vdisplay;
6646 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6648 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6650 return intel_framebuffer_create(dev, &mode_cmd, obj);
6653 static struct drm_framebuffer *
6654 mode_fits_in_fbdev(struct drm_device *dev,
6655 struct drm_display_mode *mode)
6657 struct drm_i915_private *dev_priv = dev->dev_private;
6658 struct drm_i915_gem_object *obj;
6659 struct drm_framebuffer *fb;
6661 if (dev_priv->fbdev == NULL)
6664 obj = dev_priv->fbdev->ifb.obj;
6668 fb = &dev_priv->fbdev->ifb.base;
6669 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6670 fb->bits_per_pixel))
6673 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6679 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6680 struct drm_display_mode *mode,
6681 struct intel_load_detect_pipe *old)
6683 struct intel_crtc *intel_crtc;
6684 struct intel_encoder *intel_encoder =
6685 intel_attached_encoder(connector);
6686 struct drm_crtc *possible_crtc;
6687 struct drm_encoder *encoder = &intel_encoder->base;
6688 struct drm_crtc *crtc = NULL;
6689 struct drm_device *dev = encoder->dev;
6690 struct drm_framebuffer *fb;
6693 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6694 connector->base.id, drm_get_connector_name(connector),
6695 encoder->base.id, drm_get_encoder_name(encoder));
6698 * Algorithm gets a little messy:
6700 * - if the connector already has an assigned crtc, use it (but make
6701 * sure it's on first)
6703 * - try to find the first unused crtc that can drive this connector,
6704 * and use that if we find one
6707 /* See if we already have a CRTC for this connector */
6708 if (encoder->crtc) {
6709 crtc = encoder->crtc;
6711 old->dpms_mode = connector->dpms;
6712 old->load_detect_temp = false;
6714 /* Make sure the crtc and connector are running */
6715 if (connector->dpms != DRM_MODE_DPMS_ON)
6716 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6721 /* Find an unused one (if possible) */
6722 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6724 if (!(encoder->possible_crtcs & (1 << i)))
6726 if (!possible_crtc->enabled) {
6727 crtc = possible_crtc;
6733 * If we didn't find an unused CRTC, don't use any.
6736 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6740 intel_encoder->new_crtc = to_intel_crtc(crtc);
6741 to_intel_connector(connector)->new_encoder = intel_encoder;
6743 intel_crtc = to_intel_crtc(crtc);
6744 old->dpms_mode = connector->dpms;
6745 old->load_detect_temp = true;
6746 old->release_fb = NULL;
6749 mode = &load_detect_mode;
6751 /* We need a framebuffer large enough to accommodate all accesses
6752 * that the plane may generate whilst we perform load detection.
6753 * We can not rely on the fbcon either being present (we get called
6754 * during its initialisation to detect all boot displays, or it may
6755 * not even exist) or that it is large enough to satisfy the
6758 fb = mode_fits_in_fbdev(dev, mode);
6760 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6761 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6762 old->release_fb = fb;
6764 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6766 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6770 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6771 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6772 if (old->release_fb)
6773 old->release_fb->funcs->destroy(old->release_fb);
6777 /* let the connector get through one full cycle before testing */
6778 intel_wait_for_vblank(dev, intel_crtc->pipe);
6782 void intel_release_load_detect_pipe(struct drm_connector *connector,
6783 struct intel_load_detect_pipe *old)
6785 struct intel_encoder *intel_encoder =
6786 intel_attached_encoder(connector);
6787 struct drm_encoder *encoder = &intel_encoder->base;
6789 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6790 connector->base.id, drm_get_connector_name(connector),
6791 encoder->base.id, drm_get_encoder_name(encoder));
6793 if (old->load_detect_temp) {
6794 struct drm_crtc *crtc = encoder->crtc;
6796 to_intel_connector(connector)->new_encoder = NULL;
6797 intel_encoder->new_crtc = NULL;
6798 intel_set_mode(crtc, NULL, 0, 0, NULL);
6800 if (old->release_fb)
6801 old->release_fb->funcs->destroy(old->release_fb);
6806 /* Switch crtc and encoder back off if necessary */
6807 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6808 connector->funcs->dpms(connector, old->dpms_mode);
6811 /* Returns the clock of the currently programmed mode of the given pipe. */
6812 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6814 struct drm_i915_private *dev_priv = dev->dev_private;
6815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6816 int pipe = intel_crtc->pipe;
6817 u32 dpll = I915_READ(DPLL(pipe));
6819 intel_clock_t clock;
6821 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6822 fp = I915_READ(FP0(pipe));
6824 fp = I915_READ(FP1(pipe));
6826 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6827 if (IS_PINEVIEW(dev)) {
6828 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6829 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6831 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6832 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6835 if (!IS_GEN2(dev)) {
6836 if (IS_PINEVIEW(dev))
6837 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6838 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6840 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6841 DPLL_FPA01_P1_POST_DIV_SHIFT);
6843 switch (dpll & DPLL_MODE_MASK) {
6844 case DPLLB_MODE_DAC_SERIAL:
6845 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6848 case DPLLB_MODE_LVDS:
6849 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6853 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6854 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6858 /* XXX: Handle the 100Mhz refclk */
6859 intel_clock(dev, 96000, &clock);
6861 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6864 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6865 DPLL_FPA01_P1_POST_DIV_SHIFT);
6868 if ((dpll & PLL_REF_INPUT_MASK) ==
6869 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6870 /* XXX: might not be 66MHz */
6871 intel_clock(dev, 66000, &clock);
6873 intel_clock(dev, 48000, &clock);
6875 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6878 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6879 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6881 if (dpll & PLL_P2_DIVIDE_BY_4)
6886 intel_clock(dev, 48000, &clock);
6890 /* XXX: It would be nice to validate the clocks, but we can't reuse
6891 * i830PllIsValid() because it relies on the xf86_config connector
6892 * configuration being accurate, which it isn't necessarily.
6898 /** Returns the currently programmed mode of the given pipe. */
6899 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6900 struct drm_crtc *crtc)
6902 struct drm_i915_private *dev_priv = dev->dev_private;
6903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6904 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6905 struct drm_display_mode *mode;
6906 int htot = I915_READ(HTOTAL(cpu_transcoder));
6907 int hsync = I915_READ(HSYNC(cpu_transcoder));
6908 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6909 int vsync = I915_READ(VSYNC(cpu_transcoder));
6911 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6915 mode->clock = intel_crtc_clock_get(dev, crtc);
6916 mode->hdisplay = (htot & 0xffff) + 1;
6917 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6918 mode->hsync_start = (hsync & 0xffff) + 1;
6919 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6920 mode->vdisplay = (vtot & 0xffff) + 1;
6921 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6922 mode->vsync_start = (vsync & 0xffff) + 1;
6923 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6925 drm_mode_set_name(mode);
6930 static void intel_increase_pllclock(struct drm_crtc *crtc)
6932 struct drm_device *dev = crtc->dev;
6933 drm_i915_private_t *dev_priv = dev->dev_private;
6934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6935 int pipe = intel_crtc->pipe;
6936 int dpll_reg = DPLL(pipe);
6939 if (HAS_PCH_SPLIT(dev))
6942 if (!dev_priv->lvds_downclock_avail)
6945 dpll = I915_READ(dpll_reg);
6946 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6947 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6949 assert_panel_unlocked(dev_priv, pipe);
6951 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6952 I915_WRITE(dpll_reg, dpll);
6953 intel_wait_for_vblank(dev, pipe);
6955 dpll = I915_READ(dpll_reg);
6956 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6957 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6961 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6963 struct drm_device *dev = crtc->dev;
6964 drm_i915_private_t *dev_priv = dev->dev_private;
6965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6967 if (HAS_PCH_SPLIT(dev))
6970 if (!dev_priv->lvds_downclock_avail)
6974 * Since this is called by a timer, we should never get here in
6977 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6978 int pipe = intel_crtc->pipe;
6979 int dpll_reg = DPLL(pipe);
6982 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6984 assert_panel_unlocked(dev_priv, pipe);
6986 dpll = I915_READ(dpll_reg);
6987 dpll |= DISPLAY_RATE_SELECT_FPA1;
6988 I915_WRITE(dpll_reg, dpll);
6989 intel_wait_for_vblank(dev, pipe);
6990 dpll = I915_READ(dpll_reg);
6991 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6992 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6997 void intel_mark_busy(struct drm_device *dev)
6999 i915_update_gfx_val(dev->dev_private);
7002 void intel_mark_idle(struct drm_device *dev)
7004 struct drm_crtc *crtc;
7006 if (!i915_powersave)
7009 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7013 intel_decrease_pllclock(crtc);
7017 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7019 struct drm_device *dev = obj->base.dev;
7020 struct drm_crtc *crtc;
7022 if (!i915_powersave)
7025 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7029 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7030 intel_increase_pllclock(crtc);
7034 static void intel_crtc_destroy(struct drm_crtc *crtc)
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037 struct drm_device *dev = crtc->dev;
7038 struct intel_unpin_work *work;
7039 unsigned long flags;
7041 spin_lock_irqsave(&dev->event_lock, flags);
7042 work = intel_crtc->unpin_work;
7043 intel_crtc->unpin_work = NULL;
7044 spin_unlock_irqrestore(&dev->event_lock, flags);
7047 cancel_work_sync(&work->work);
7051 drm_crtc_cleanup(crtc);
7056 static void intel_unpin_work_fn(struct work_struct *__work)
7058 struct intel_unpin_work *work =
7059 container_of(__work, struct intel_unpin_work, work);
7060 struct drm_device *dev = work->crtc->dev;
7062 mutex_lock(&dev->struct_mutex);
7063 intel_unpin_fb_obj(work->old_fb_obj);
7064 drm_gem_object_unreference(&work->pending_flip_obj->base);
7065 drm_gem_object_unreference(&work->old_fb_obj->base);
7067 intel_update_fbc(dev);
7068 mutex_unlock(&dev->struct_mutex);
7070 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7071 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7076 static void do_intel_finish_page_flip(struct drm_device *dev,
7077 struct drm_crtc *crtc)
7079 drm_i915_private_t *dev_priv = dev->dev_private;
7080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7081 struct intel_unpin_work *work;
7082 struct drm_i915_gem_object *obj;
7083 unsigned long flags;
7085 /* Ignore early vblank irqs */
7086 if (intel_crtc == NULL)
7089 spin_lock_irqsave(&dev->event_lock, flags);
7090 work = intel_crtc->unpin_work;
7092 /* Ensure we don't miss a work->pending update ... */
7095 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7096 spin_unlock_irqrestore(&dev->event_lock, flags);
7100 /* and that the unpin work is consistent wrt ->pending. */
7103 intel_crtc->unpin_work = NULL;
7106 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7108 drm_vblank_put(dev, intel_crtc->pipe);
7110 spin_unlock_irqrestore(&dev->event_lock, flags);
7112 obj = work->old_fb_obj;
7114 atomic_clear_mask(1 << intel_crtc->plane,
7115 &obj->pending_flip.counter);
7116 wake_up(&dev_priv->pending_flip_queue);
7118 queue_work(dev_priv->wq, &work->work);
7120 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7123 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7125 drm_i915_private_t *dev_priv = dev->dev_private;
7126 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7128 do_intel_finish_page_flip(dev, crtc);
7131 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7133 drm_i915_private_t *dev_priv = dev->dev_private;
7134 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7136 do_intel_finish_page_flip(dev, crtc);
7139 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7141 drm_i915_private_t *dev_priv = dev->dev_private;
7142 struct intel_crtc *intel_crtc =
7143 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7144 unsigned long flags;
7146 /* NB: An MMIO update of the plane base pointer will also
7147 * generate a page-flip completion irq, i.e. every modeset
7148 * is also accompanied by a spurious intel_prepare_page_flip().
7150 spin_lock_irqsave(&dev->event_lock, flags);
7151 if (intel_crtc->unpin_work)
7152 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7153 spin_unlock_irqrestore(&dev->event_lock, flags);
7156 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7158 /* Ensure that the work item is consistent when activating it ... */
7160 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7161 /* and that it is marked active as soon as the irq could fire. */
7165 static int intel_gen2_queue_flip(struct drm_device *dev,
7166 struct drm_crtc *crtc,
7167 struct drm_framebuffer *fb,
7168 struct drm_i915_gem_object *obj)
7170 struct drm_i915_private *dev_priv = dev->dev_private;
7171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7173 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7176 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7180 ret = intel_ring_begin(ring, 6);
7184 /* Can't queue multiple flips, so wait for the previous
7185 * one to finish before executing the next.
7187 if (intel_crtc->plane)
7188 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7190 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7191 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7192 intel_ring_emit(ring, MI_NOOP);
7193 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7194 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7195 intel_ring_emit(ring, fb->pitches[0]);
7196 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7197 intel_ring_emit(ring, 0); /* aux display base address, unused */
7199 intel_mark_page_flip_active(intel_crtc);
7200 intel_ring_advance(ring);
7204 intel_unpin_fb_obj(obj);
7209 static int intel_gen3_queue_flip(struct drm_device *dev,
7210 struct drm_crtc *crtc,
7211 struct drm_framebuffer *fb,
7212 struct drm_i915_gem_object *obj)
7214 struct drm_i915_private *dev_priv = dev->dev_private;
7215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7217 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7220 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7224 ret = intel_ring_begin(ring, 6);
7228 if (intel_crtc->plane)
7229 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7231 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7232 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7233 intel_ring_emit(ring, MI_NOOP);
7234 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7235 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7236 intel_ring_emit(ring, fb->pitches[0]);
7237 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7238 intel_ring_emit(ring, MI_NOOP);
7240 intel_mark_page_flip_active(intel_crtc);
7241 intel_ring_advance(ring);
7245 intel_unpin_fb_obj(obj);
7250 static int intel_gen4_queue_flip(struct drm_device *dev,
7251 struct drm_crtc *crtc,
7252 struct drm_framebuffer *fb,
7253 struct drm_i915_gem_object *obj)
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7257 uint32_t pf, pipesrc;
7258 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7261 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7265 ret = intel_ring_begin(ring, 4);
7269 /* i965+ uses the linear or tiled offsets from the
7270 * Display Registers (which do not change across a page-flip)
7271 * so we need only reprogram the base address.
7273 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7274 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7275 intel_ring_emit(ring, fb->pitches[0]);
7276 intel_ring_emit(ring,
7277 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7280 /* XXX Enabling the panel-fitter across page-flip is so far
7281 * untested on non-native modes, so ignore it for now.
7282 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7285 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7286 intel_ring_emit(ring, pf | pipesrc);
7288 intel_mark_page_flip_active(intel_crtc);
7289 intel_ring_advance(ring);
7293 intel_unpin_fb_obj(obj);
7298 static int intel_gen6_queue_flip(struct drm_device *dev,
7299 struct drm_crtc *crtc,
7300 struct drm_framebuffer *fb,
7301 struct drm_i915_gem_object *obj)
7303 struct drm_i915_private *dev_priv = dev->dev_private;
7304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7305 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7306 uint32_t pf, pipesrc;
7309 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7313 ret = intel_ring_begin(ring, 4);
7317 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7318 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7319 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7320 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7322 /* Contrary to the suggestions in the documentation,
7323 * "Enable Panel Fitter" does not seem to be required when page
7324 * flipping with a non-native mode, and worse causes a normal
7326 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7329 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7330 intel_ring_emit(ring, pf | pipesrc);
7332 intel_mark_page_flip_active(intel_crtc);
7333 intel_ring_advance(ring);
7337 intel_unpin_fb_obj(obj);
7343 * On gen7 we currently use the blit ring because (in early silicon at least)
7344 * the render ring doesn't give us interrpts for page flip completion, which
7345 * means clients will hang after the first flip is queued. Fortunately the
7346 * blit ring generates interrupts properly, so use it instead.
7348 static int intel_gen7_queue_flip(struct drm_device *dev,
7349 struct drm_crtc *crtc,
7350 struct drm_framebuffer *fb,
7351 struct drm_i915_gem_object *obj)
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7355 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7356 uint32_t plane_bit = 0;
7359 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7363 switch(intel_crtc->plane) {
7365 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7368 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7371 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7374 WARN_ONCE(1, "unknown plane in flip command\n");
7379 ret = intel_ring_begin(ring, 4);
7383 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7384 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7385 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7386 intel_ring_emit(ring, (MI_NOOP));
7388 intel_mark_page_flip_active(intel_crtc);
7389 intel_ring_advance(ring);
7393 intel_unpin_fb_obj(obj);
7398 static int intel_default_queue_flip(struct drm_device *dev,
7399 struct drm_crtc *crtc,
7400 struct drm_framebuffer *fb,
7401 struct drm_i915_gem_object *obj)
7406 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7407 struct drm_framebuffer *fb,
7408 struct drm_pending_vblank_event *event)
7410 struct drm_device *dev = crtc->dev;
7411 struct drm_i915_private *dev_priv = dev->dev_private;
7412 struct intel_framebuffer *intel_fb;
7413 struct drm_i915_gem_object *obj;
7414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415 struct intel_unpin_work *work;
7416 unsigned long flags;
7419 /* Can't change pixel format via MI display flips. */
7420 if (fb->pixel_format != crtc->fb->pixel_format)
7424 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7425 * Note that pitch changes could also affect these register.
7427 if (INTEL_INFO(dev)->gen > 3 &&
7428 (fb->offsets[0] != crtc->fb->offsets[0] ||
7429 fb->pitches[0] != crtc->fb->pitches[0]))
7432 work = kzalloc(sizeof *work, GFP_KERNEL);
7436 work->event = event;
7438 intel_fb = to_intel_framebuffer(crtc->fb);
7439 work->old_fb_obj = intel_fb->obj;
7440 INIT_WORK(&work->work, intel_unpin_work_fn);
7442 ret = drm_vblank_get(dev, intel_crtc->pipe);
7446 /* We borrow the event spin lock for protecting unpin_work */
7447 spin_lock_irqsave(&dev->event_lock, flags);
7448 if (intel_crtc->unpin_work) {
7449 spin_unlock_irqrestore(&dev->event_lock, flags);
7451 drm_vblank_put(dev, intel_crtc->pipe);
7453 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7456 intel_crtc->unpin_work = work;
7457 spin_unlock_irqrestore(&dev->event_lock, flags);
7459 intel_fb = to_intel_framebuffer(fb);
7460 obj = intel_fb->obj;
7462 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7463 flush_workqueue(dev_priv->wq);
7465 ret = i915_mutex_lock_interruptible(dev);
7469 /* Reference the objects for the scheduled work. */
7470 drm_gem_object_reference(&work->old_fb_obj->base);
7471 drm_gem_object_reference(&obj->base);
7475 work->pending_flip_obj = obj;
7477 work->enable_stall_check = true;
7479 /* Block clients from rendering to the new back buffer until
7480 * the flip occurs and the object is no longer visible.
7482 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7483 atomic_inc(&intel_crtc->unpin_work_count);
7485 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7487 goto cleanup_pending;
7489 intel_disable_fbc(dev);
7490 intel_mark_fb_busy(obj);
7491 mutex_unlock(&dev->struct_mutex);
7493 trace_i915_flip_request(intel_crtc->plane, obj);
7498 atomic_dec(&intel_crtc->unpin_work_count);
7499 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7500 drm_gem_object_unreference(&work->old_fb_obj->base);
7501 drm_gem_object_unreference(&obj->base);
7502 mutex_unlock(&dev->struct_mutex);
7505 spin_lock_irqsave(&dev->event_lock, flags);
7506 intel_crtc->unpin_work = NULL;
7507 spin_unlock_irqrestore(&dev->event_lock, flags);
7509 drm_vblank_put(dev, intel_crtc->pipe);
7516 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7517 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7518 .load_lut = intel_crtc_load_lut,
7519 .disable = intel_crtc_noop,
7522 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7524 struct intel_encoder *other_encoder;
7525 struct drm_crtc *crtc = &encoder->new_crtc->base;
7530 list_for_each_entry(other_encoder,
7531 &crtc->dev->mode_config.encoder_list,
7534 if (&other_encoder->new_crtc->base != crtc ||
7535 encoder == other_encoder)
7544 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7545 struct drm_crtc *crtc)
7547 struct drm_device *dev;
7548 struct drm_crtc *tmp;
7551 WARN(!crtc, "checking null crtc?\n");
7555 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7561 if (encoder->possible_crtcs & crtc_mask)
7567 * intel_modeset_update_staged_output_state
7569 * Updates the staged output configuration state, e.g. after we've read out the
7572 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7574 struct intel_encoder *encoder;
7575 struct intel_connector *connector;
7577 list_for_each_entry(connector, &dev->mode_config.connector_list,
7579 connector->new_encoder =
7580 to_intel_encoder(connector->base.encoder);
7583 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7586 to_intel_crtc(encoder->base.crtc);
7591 * intel_modeset_commit_output_state
7593 * This function copies the stage display pipe configuration to the real one.
7595 static void intel_modeset_commit_output_state(struct drm_device *dev)
7597 struct intel_encoder *encoder;
7598 struct intel_connector *connector;
7600 list_for_each_entry(connector, &dev->mode_config.connector_list,
7602 connector->base.encoder = &connector->new_encoder->base;
7605 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7607 encoder->base.crtc = &encoder->new_crtc->base;
7611 static struct drm_display_mode *
7612 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7613 struct drm_display_mode *mode)
7615 struct drm_device *dev = crtc->dev;
7616 struct drm_display_mode *adjusted_mode;
7617 struct drm_encoder_helper_funcs *encoder_funcs;
7618 struct intel_encoder *encoder;
7620 adjusted_mode = drm_mode_duplicate(dev, mode);
7622 return ERR_PTR(-ENOMEM);
7624 /* Pass our mode to the connectors and the CRTC to give them a chance to
7625 * adjust it according to limitations or connector properties, and also
7626 * a chance to reject the mode entirely.
7628 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7631 if (&encoder->new_crtc->base != crtc)
7633 encoder_funcs = encoder->base.helper_private;
7634 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7636 DRM_DEBUG_KMS("Encoder fixup failed\n");
7641 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7642 DRM_DEBUG_KMS("CRTC fixup failed\n");
7645 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7647 return adjusted_mode;
7649 drm_mode_destroy(dev, adjusted_mode);
7650 return ERR_PTR(-EINVAL);
7653 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7654 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7656 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7657 unsigned *prepare_pipes, unsigned *disable_pipes)
7659 struct intel_crtc *intel_crtc;
7660 struct drm_device *dev = crtc->dev;
7661 struct intel_encoder *encoder;
7662 struct intel_connector *connector;
7663 struct drm_crtc *tmp_crtc;
7665 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7667 /* Check which crtcs have changed outputs connected to them, these need
7668 * to be part of the prepare_pipes mask. We don't (yet) support global
7669 * modeset across multiple crtcs, so modeset_pipes will only have one
7670 * bit set at most. */
7671 list_for_each_entry(connector, &dev->mode_config.connector_list,
7673 if (connector->base.encoder == &connector->new_encoder->base)
7676 if (connector->base.encoder) {
7677 tmp_crtc = connector->base.encoder->crtc;
7679 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7682 if (connector->new_encoder)
7684 1 << connector->new_encoder->new_crtc->pipe;
7687 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7689 if (encoder->base.crtc == &encoder->new_crtc->base)
7692 if (encoder->base.crtc) {
7693 tmp_crtc = encoder->base.crtc;
7695 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7698 if (encoder->new_crtc)
7699 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7702 /* Check for any pipes that will be fully disabled ... */
7703 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7707 /* Don't try to disable disabled crtcs. */
7708 if (!intel_crtc->base.enabled)
7711 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7713 if (encoder->new_crtc == intel_crtc)
7718 *disable_pipes |= 1 << intel_crtc->pipe;
7722 /* set_mode is also used to update properties on life display pipes. */
7723 intel_crtc = to_intel_crtc(crtc);
7725 *prepare_pipes |= 1 << intel_crtc->pipe;
7727 /* We only support modeset on one single crtc, hence we need to do that
7728 * only for the passed in crtc iff we change anything else than just
7731 * This is actually not true, to be fully compatible with the old crtc
7732 * helper we automatically disable _any_ output (i.e. doesn't need to be
7733 * connected to the crtc we're modesetting on) if it's disconnected.
7734 * Which is a rather nutty api (since changed the output configuration
7735 * without userspace's explicit request can lead to confusion), but
7736 * alas. Hence we currently need to modeset on all pipes we prepare. */
7738 *modeset_pipes = *prepare_pipes;
7740 /* ... and mask these out. */
7741 *modeset_pipes &= ~(*disable_pipes);
7742 *prepare_pipes &= ~(*disable_pipes);
7745 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7747 struct drm_encoder *encoder;
7748 struct drm_device *dev = crtc->dev;
7750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7751 if (encoder->crtc == crtc)
7758 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7760 struct intel_encoder *intel_encoder;
7761 struct intel_crtc *intel_crtc;
7762 struct drm_connector *connector;
7764 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7766 if (!intel_encoder->base.crtc)
7769 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7771 if (prepare_pipes & (1 << intel_crtc->pipe))
7772 intel_encoder->connectors_active = false;
7775 intel_modeset_commit_output_state(dev);
7777 /* Update computed state. */
7778 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7780 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7783 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7784 if (!connector->encoder || !connector->encoder->crtc)
7787 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7789 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7790 struct drm_property *dpms_property =
7791 dev->mode_config.dpms_property;
7793 connector->dpms = DRM_MODE_DPMS_ON;
7794 drm_object_property_set_value(&connector->base,
7798 intel_encoder = to_intel_encoder(connector->encoder);
7799 intel_encoder->connectors_active = true;
7805 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7806 list_for_each_entry((intel_crtc), \
7807 &(dev)->mode_config.crtc_list, \
7809 if (mask & (1 <<(intel_crtc)->pipe)) \
7812 intel_modeset_check_state(struct drm_device *dev)
7814 struct intel_crtc *crtc;
7815 struct intel_encoder *encoder;
7816 struct intel_connector *connector;
7818 list_for_each_entry(connector, &dev->mode_config.connector_list,
7820 /* This also checks the encoder/connector hw state with the
7821 * ->get_hw_state callbacks. */
7822 intel_connector_check_state(connector);
7824 WARN(&connector->new_encoder->base != connector->base.encoder,
7825 "connector's staged encoder doesn't match current encoder\n");
7828 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7830 bool enabled = false;
7831 bool active = false;
7832 enum pipe pipe, tracked_pipe;
7834 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7835 encoder->base.base.id,
7836 drm_get_encoder_name(&encoder->base));
7838 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7839 "encoder's stage crtc doesn't match current crtc\n");
7840 WARN(encoder->connectors_active && !encoder->base.crtc,
7841 "encoder's active_connectors set, but no crtc\n");
7843 list_for_each_entry(connector, &dev->mode_config.connector_list,
7845 if (connector->base.encoder != &encoder->base)
7848 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7851 WARN(!!encoder->base.crtc != enabled,
7852 "encoder's enabled state mismatch "
7853 "(expected %i, found %i)\n",
7854 !!encoder->base.crtc, enabled);
7855 WARN(active && !encoder->base.crtc,
7856 "active encoder with no crtc\n");
7858 WARN(encoder->connectors_active != active,
7859 "encoder's computed active state doesn't match tracked active state "
7860 "(expected %i, found %i)\n", active, encoder->connectors_active);
7862 active = encoder->get_hw_state(encoder, &pipe);
7863 WARN(active != encoder->connectors_active,
7864 "encoder's hw state doesn't match sw tracking "
7865 "(expected %i, found %i)\n",
7866 encoder->connectors_active, active);
7868 if (!encoder->base.crtc)
7871 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7872 WARN(active && pipe != tracked_pipe,
7873 "active encoder's pipe doesn't match"
7874 "(expected %i, found %i)\n",
7875 tracked_pipe, pipe);
7879 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7881 bool enabled = false;
7882 bool active = false;
7884 DRM_DEBUG_KMS("[CRTC:%d]\n",
7885 crtc->base.base.id);
7887 WARN(crtc->active && !crtc->base.enabled,
7888 "active crtc, but not enabled in sw tracking\n");
7890 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7892 if (encoder->base.crtc != &crtc->base)
7895 if (encoder->connectors_active)
7898 WARN(active != crtc->active,
7899 "crtc's computed active state doesn't match tracked active state "
7900 "(expected %i, found %i)\n", active, crtc->active);
7901 WARN(enabled != crtc->base.enabled,
7902 "crtc's computed enabled state doesn't match tracked enabled state "
7903 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7905 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7909 bool intel_set_mode(struct drm_crtc *crtc,
7910 struct drm_display_mode *mode,
7911 int x, int y, struct drm_framebuffer *fb)
7913 struct drm_device *dev = crtc->dev;
7914 drm_i915_private_t *dev_priv = dev->dev_private;
7915 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7916 struct intel_crtc *intel_crtc;
7917 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7920 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7921 &prepare_pipes, &disable_pipes);
7923 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7924 modeset_pipes, prepare_pipes, disable_pipes);
7926 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7927 intel_crtc_disable(&intel_crtc->base);
7929 saved_hwmode = crtc->hwmode;
7930 saved_mode = crtc->mode;
7932 /* Hack: Because we don't (yet) support global modeset on multiple
7933 * crtcs, we don't keep track of the new mode for more than one crtc.
7934 * Hence simply check whether any bit is set in modeset_pipes in all the
7935 * pieces of code that are not yet converted to deal with mutliple crtcs
7936 * changing their mode at the same time. */
7937 adjusted_mode = NULL;
7938 if (modeset_pipes) {
7939 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7940 if (IS_ERR(adjusted_mode)) {
7945 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7946 if (intel_crtc->base.enabled)
7947 dev_priv->display.crtc_disable(&intel_crtc->base);
7950 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7951 * to set it here already despite that we pass it down the callchain.
7956 /* Only after disabling all output pipelines that will be changed can we
7957 * update the the output configuration. */
7958 intel_modeset_update_state(dev, prepare_pipes);
7960 if (dev_priv->display.modeset_global_resources)
7961 dev_priv->display.modeset_global_resources(dev);
7963 /* Set up the DPLL and any encoders state that needs to adjust or depend
7966 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7967 ret = !intel_crtc_mode_set(&intel_crtc->base,
7968 mode, adjusted_mode,
7974 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7975 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7976 dev_priv->display.crtc_enable(&intel_crtc->base);
7978 if (modeset_pipes) {
7979 /* Store real post-adjustment hardware mode. */
7980 crtc->hwmode = *adjusted_mode;
7982 /* Calculate and store various constants which
7983 * are later needed by vblank and swap-completion
7984 * timestamping. They are derived from true hwmode.
7986 drm_calc_timestamping_constants(crtc);
7989 /* FIXME: add subpixel order */
7991 drm_mode_destroy(dev, adjusted_mode);
7992 if (!ret && crtc->enabled) {
7993 crtc->hwmode = saved_hwmode;
7994 crtc->mode = saved_mode;
7996 intel_modeset_check_state(dev);
8002 #undef for_each_intel_crtc_masked
8004 static void intel_set_config_free(struct intel_set_config *config)
8009 kfree(config->save_connector_encoders);
8010 kfree(config->save_encoder_crtcs);
8014 static int intel_set_config_save_state(struct drm_device *dev,
8015 struct intel_set_config *config)
8017 struct drm_encoder *encoder;
8018 struct drm_connector *connector;
8021 config->save_encoder_crtcs =
8022 kcalloc(dev->mode_config.num_encoder,
8023 sizeof(struct drm_crtc *), GFP_KERNEL);
8024 if (!config->save_encoder_crtcs)
8027 config->save_connector_encoders =
8028 kcalloc(dev->mode_config.num_connector,
8029 sizeof(struct drm_encoder *), GFP_KERNEL);
8030 if (!config->save_connector_encoders)
8033 /* Copy data. Note that driver private data is not affected.
8034 * Should anything bad happen only the expected state is
8035 * restored, not the drivers personal bookkeeping.
8038 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8039 config->save_encoder_crtcs[count++] = encoder->crtc;
8043 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8044 config->save_connector_encoders[count++] = connector->encoder;
8050 static void intel_set_config_restore_state(struct drm_device *dev,
8051 struct intel_set_config *config)
8053 struct intel_encoder *encoder;
8054 struct intel_connector *connector;
8058 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8060 to_intel_crtc(config->save_encoder_crtcs[count++]);
8064 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8065 connector->new_encoder =
8066 to_intel_encoder(config->save_connector_encoders[count++]);
8071 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8072 struct intel_set_config *config)
8075 /* We should be able to check here if the fb has the same properties
8076 * and then just flip_or_move it */
8077 if (set->crtc->fb != set->fb) {
8078 /* If we have no fb then treat it as a full mode set */
8079 if (set->crtc->fb == NULL) {
8080 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8081 config->mode_changed = true;
8082 } else if (set->fb == NULL) {
8083 config->mode_changed = true;
8084 } else if (set->fb->depth != set->crtc->fb->depth) {
8085 config->mode_changed = true;
8086 } else if (set->fb->bits_per_pixel !=
8087 set->crtc->fb->bits_per_pixel) {
8088 config->mode_changed = true;
8090 config->fb_changed = true;
8093 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8094 config->fb_changed = true;
8096 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8097 DRM_DEBUG_KMS("modes are different, full mode set\n");
8098 drm_mode_debug_printmodeline(&set->crtc->mode);
8099 drm_mode_debug_printmodeline(set->mode);
8100 config->mode_changed = true;
8105 intel_modeset_stage_output_state(struct drm_device *dev,
8106 struct drm_mode_set *set,
8107 struct intel_set_config *config)
8109 struct drm_crtc *new_crtc;
8110 struct intel_connector *connector;
8111 struct intel_encoder *encoder;
8114 /* The upper layers ensure that we either disabl a crtc or have a list
8115 * of connectors. For paranoia, double-check this. */
8116 WARN_ON(!set->fb && (set->num_connectors != 0));
8117 WARN_ON(set->fb && (set->num_connectors == 0));
8120 list_for_each_entry(connector, &dev->mode_config.connector_list,
8122 /* Otherwise traverse passed in connector list and get encoders
8124 for (ro = 0; ro < set->num_connectors; ro++) {
8125 if (set->connectors[ro] == &connector->base) {
8126 connector->new_encoder = connector->encoder;
8131 /* If we disable the crtc, disable all its connectors. Also, if
8132 * the connector is on the changing crtc but not on the new
8133 * connector list, disable it. */
8134 if ((!set->fb || ro == set->num_connectors) &&
8135 connector->base.encoder &&
8136 connector->base.encoder->crtc == set->crtc) {
8137 connector->new_encoder = NULL;
8139 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8140 connector->base.base.id,
8141 drm_get_connector_name(&connector->base));
8145 if (&connector->new_encoder->base != connector->base.encoder) {
8146 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8147 config->mode_changed = true;
8150 /* connector->new_encoder is now updated for all connectors. */
8152 /* Update crtc of enabled connectors. */
8154 list_for_each_entry(connector, &dev->mode_config.connector_list,
8156 if (!connector->new_encoder)
8159 new_crtc = connector->new_encoder->base.crtc;
8161 for (ro = 0; ro < set->num_connectors; ro++) {
8162 if (set->connectors[ro] == &connector->base)
8163 new_crtc = set->crtc;
8166 /* Make sure the new CRTC will work with the encoder */
8167 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8171 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8173 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8174 connector->base.base.id,
8175 drm_get_connector_name(&connector->base),
8179 /* Check for any encoders that needs to be disabled. */
8180 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8182 list_for_each_entry(connector,
8183 &dev->mode_config.connector_list,
8185 if (connector->new_encoder == encoder) {
8186 WARN_ON(!connector->new_encoder->new_crtc);
8191 encoder->new_crtc = NULL;
8193 /* Only now check for crtc changes so we don't miss encoders
8194 * that will be disabled. */
8195 if (&encoder->new_crtc->base != encoder->base.crtc) {
8196 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8197 config->mode_changed = true;
8200 /* Now we've also updated encoder->new_crtc for all encoders. */
8205 static int intel_crtc_set_config(struct drm_mode_set *set)
8207 struct drm_device *dev;
8208 struct drm_mode_set save_set;
8209 struct intel_set_config *config;
8214 BUG_ON(!set->crtc->helper_private);
8219 /* The fb helper likes to play gross jokes with ->mode_set_config.
8220 * Unfortunately the crtc helper doesn't do much at all for this case,
8221 * so we have to cope with this madness until the fb helper is fixed up. */
8222 if (set->fb && set->num_connectors == 0)
8226 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8227 set->crtc->base.id, set->fb->base.id,
8228 (int)set->num_connectors, set->x, set->y);
8230 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8233 dev = set->crtc->dev;
8236 config = kzalloc(sizeof(*config), GFP_KERNEL);
8240 ret = intel_set_config_save_state(dev, config);
8244 save_set.crtc = set->crtc;
8245 save_set.mode = &set->crtc->mode;
8246 save_set.x = set->crtc->x;
8247 save_set.y = set->crtc->y;
8248 save_set.fb = set->crtc->fb;
8250 /* Compute whether we need a full modeset, only an fb base update or no
8251 * change at all. In the future we might also check whether only the
8252 * mode changed, e.g. for LVDS where we only change the panel fitter in
8254 intel_set_config_compute_mode_changes(set, config);
8256 ret = intel_modeset_stage_output_state(dev, set, config);
8260 if (config->mode_changed) {
8262 DRM_DEBUG_KMS("attempting to set mode from"
8264 drm_mode_debug_printmodeline(set->mode);
8267 if (!intel_set_mode(set->crtc, set->mode,
8268 set->x, set->y, set->fb)) {
8269 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8270 set->crtc->base.id);
8274 } else if (config->fb_changed) {
8275 ret = intel_pipe_set_base(set->crtc,
8276 set->x, set->y, set->fb);
8279 intel_set_config_free(config);
8284 intel_set_config_restore_state(dev, config);
8286 /* Try to restore the config */
8287 if (config->mode_changed &&
8288 !intel_set_mode(save_set.crtc, save_set.mode,
8289 save_set.x, save_set.y, save_set.fb))
8290 DRM_ERROR("failed to restore config after modeset failure\n");
8293 intel_set_config_free(config);
8297 static const struct drm_crtc_funcs intel_crtc_funcs = {
8298 .cursor_set = intel_crtc_cursor_set,
8299 .cursor_move = intel_crtc_cursor_move,
8300 .gamma_set = intel_crtc_gamma_set,
8301 .set_config = intel_crtc_set_config,
8302 .destroy = intel_crtc_destroy,
8303 .page_flip = intel_crtc_page_flip,
8306 static void intel_cpu_pll_init(struct drm_device *dev)
8308 if (IS_HASWELL(dev))
8309 intel_ddi_pll_init(dev);
8312 static void intel_pch_pll_init(struct drm_device *dev)
8314 drm_i915_private_t *dev_priv = dev->dev_private;
8317 if (dev_priv->num_pch_pll == 0) {
8318 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8322 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8323 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8324 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8325 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8329 static void intel_crtc_init(struct drm_device *dev, int pipe)
8331 drm_i915_private_t *dev_priv = dev->dev_private;
8332 struct intel_crtc *intel_crtc;
8335 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8336 if (intel_crtc == NULL)
8339 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8341 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8342 for (i = 0; i < 256; i++) {
8343 intel_crtc->lut_r[i] = i;
8344 intel_crtc->lut_g[i] = i;
8345 intel_crtc->lut_b[i] = i;
8348 /* Swap pipes & planes for FBC on pre-965 */
8349 intel_crtc->pipe = pipe;
8350 intel_crtc->plane = pipe;
8351 intel_crtc->cpu_transcoder = pipe;
8352 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8353 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8354 intel_crtc->plane = !pipe;
8357 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8358 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8359 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8360 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8362 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8364 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8367 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8368 struct drm_file *file)
8370 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8371 struct drm_mode_object *drmmode_obj;
8372 struct intel_crtc *crtc;
8374 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8377 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8378 DRM_MODE_OBJECT_CRTC);
8381 DRM_ERROR("no such CRTC id\n");
8385 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8386 pipe_from_crtc_id->pipe = crtc->pipe;
8391 static int intel_encoder_clones(struct intel_encoder *encoder)
8393 struct drm_device *dev = encoder->base.dev;
8394 struct intel_encoder *source_encoder;
8398 list_for_each_entry(source_encoder,
8399 &dev->mode_config.encoder_list, base.head) {
8401 if (encoder == source_encoder)
8402 index_mask |= (1 << entry);
8404 /* Intel hw has only one MUX where enocoders could be cloned. */
8405 if (encoder->cloneable && source_encoder->cloneable)
8406 index_mask |= (1 << entry);
8414 static bool has_edp_a(struct drm_device *dev)
8416 struct drm_i915_private *dev_priv = dev->dev_private;
8418 if (!IS_MOBILE(dev))
8421 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8425 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8431 static void intel_setup_outputs(struct drm_device *dev)
8433 struct drm_i915_private *dev_priv = dev->dev_private;
8434 struct intel_encoder *encoder;
8435 bool dpd_is_edp = false;
8438 has_lvds = intel_lvds_init(dev);
8439 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8440 /* disable the panel fitter on everything but LVDS */
8441 I915_WRITE(PFIT_CONTROL, 0);
8444 if (!(IS_HASWELL(dev) &&
8445 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8446 intel_crt_init(dev);
8448 if (IS_HASWELL(dev)) {
8451 /* Haswell uses DDI functions to detect digital outputs */
8452 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8453 /* DDI A only supports eDP */
8455 intel_ddi_init(dev, PORT_A);
8457 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8459 found = I915_READ(SFUSE_STRAP);
8461 if (found & SFUSE_STRAP_DDIB_DETECTED)
8462 intel_ddi_init(dev, PORT_B);
8463 if (found & SFUSE_STRAP_DDIC_DETECTED)
8464 intel_ddi_init(dev, PORT_C);
8465 if (found & SFUSE_STRAP_DDID_DETECTED)
8466 intel_ddi_init(dev, PORT_D);
8467 } else if (HAS_PCH_SPLIT(dev)) {
8469 dpd_is_edp = intel_dpd_is_edp(dev);
8472 intel_dp_init(dev, DP_A, PORT_A);
8474 if (I915_READ(HDMIB) & PORT_DETECTED) {
8475 /* PCH SDVOB multiplex with HDMIB */
8476 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8478 intel_hdmi_init(dev, HDMIB, PORT_B);
8479 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8480 intel_dp_init(dev, PCH_DP_B, PORT_B);
8483 if (I915_READ(HDMIC) & PORT_DETECTED)
8484 intel_hdmi_init(dev, HDMIC, PORT_C);
8486 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8487 intel_hdmi_init(dev, HDMID, PORT_D);
8489 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8490 intel_dp_init(dev, PCH_DP_C, PORT_C);
8492 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8493 intel_dp_init(dev, PCH_DP_D, PORT_D);
8494 } else if (IS_VALLEYVIEW(dev)) {
8497 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8498 if (I915_READ(DP_C) & DP_DETECTED)
8499 intel_dp_init(dev, DP_C, PORT_C);
8501 if (I915_READ(SDVOB) & PORT_DETECTED) {
8502 /* SDVOB multiplex with HDMIB */
8503 found = intel_sdvo_init(dev, SDVOB, true);
8505 intel_hdmi_init(dev, SDVOB, PORT_B);
8506 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8507 intel_dp_init(dev, DP_B, PORT_B);
8510 if (I915_READ(SDVOC) & PORT_DETECTED)
8511 intel_hdmi_init(dev, SDVOC, PORT_C);
8513 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8516 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8517 DRM_DEBUG_KMS("probing SDVOB\n");
8518 found = intel_sdvo_init(dev, SDVOB, true);
8519 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8520 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8521 intel_hdmi_init(dev, SDVOB, PORT_B);
8524 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8525 DRM_DEBUG_KMS("probing DP_B\n");
8526 intel_dp_init(dev, DP_B, PORT_B);
8530 /* Before G4X SDVOC doesn't have its own detect register */
8532 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8533 DRM_DEBUG_KMS("probing SDVOC\n");
8534 found = intel_sdvo_init(dev, SDVOC, false);
8537 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8539 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8540 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8541 intel_hdmi_init(dev, SDVOC, PORT_C);
8543 if (SUPPORTS_INTEGRATED_DP(dev)) {
8544 DRM_DEBUG_KMS("probing DP_C\n");
8545 intel_dp_init(dev, DP_C, PORT_C);
8549 if (SUPPORTS_INTEGRATED_DP(dev) &&
8550 (I915_READ(DP_D) & DP_DETECTED)) {
8551 DRM_DEBUG_KMS("probing DP_D\n");
8552 intel_dp_init(dev, DP_D, PORT_D);
8554 } else if (IS_GEN2(dev))
8555 intel_dvo_init(dev);
8557 if (SUPPORTS_TV(dev))
8560 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8561 encoder->base.possible_crtcs = encoder->crtc_mask;
8562 encoder->base.possible_clones =
8563 intel_encoder_clones(encoder);
8566 intel_init_pch_refclk(dev);
8568 drm_helper_move_panel_connectors_to_head(dev);
8571 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8573 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8575 drm_framebuffer_cleanup(fb);
8576 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8581 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8582 struct drm_file *file,
8583 unsigned int *handle)
8585 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8586 struct drm_i915_gem_object *obj = intel_fb->obj;
8588 return drm_gem_handle_create(file, &obj->base, handle);
8591 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8592 .destroy = intel_user_framebuffer_destroy,
8593 .create_handle = intel_user_framebuffer_create_handle,
8596 int intel_framebuffer_init(struct drm_device *dev,
8597 struct intel_framebuffer *intel_fb,
8598 struct drm_mode_fb_cmd2 *mode_cmd,
8599 struct drm_i915_gem_object *obj)
8603 if (obj->tiling_mode == I915_TILING_Y) {
8604 DRM_DEBUG("hardware does not support tiling Y\n");
8608 if (mode_cmd->pitches[0] & 63) {
8609 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8610 mode_cmd->pitches[0]);
8614 /* FIXME <= Gen4 stride limits are bit unclear */
8615 if (mode_cmd->pitches[0] > 32768) {
8616 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8617 mode_cmd->pitches[0]);
8621 if (obj->tiling_mode != I915_TILING_NONE &&
8622 mode_cmd->pitches[0] != obj->stride) {
8623 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8624 mode_cmd->pitches[0], obj->stride);
8628 /* Reject formats not supported by any plane early. */
8629 switch (mode_cmd->pixel_format) {
8631 case DRM_FORMAT_RGB565:
8632 case DRM_FORMAT_XRGB8888:
8633 case DRM_FORMAT_ARGB8888:
8635 case DRM_FORMAT_XRGB1555:
8636 case DRM_FORMAT_ARGB1555:
8637 if (INTEL_INFO(dev)->gen > 3) {
8638 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8642 case DRM_FORMAT_XBGR8888:
8643 case DRM_FORMAT_ABGR8888:
8644 case DRM_FORMAT_XRGB2101010:
8645 case DRM_FORMAT_ARGB2101010:
8646 case DRM_FORMAT_XBGR2101010:
8647 case DRM_FORMAT_ABGR2101010:
8648 if (INTEL_INFO(dev)->gen < 4) {
8649 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8653 case DRM_FORMAT_YUYV:
8654 case DRM_FORMAT_UYVY:
8655 case DRM_FORMAT_YVYU:
8656 case DRM_FORMAT_VYUY:
8657 if (INTEL_INFO(dev)->gen < 5) {
8658 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8663 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8667 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8668 if (mode_cmd->offsets[0] != 0)
8671 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8673 DRM_ERROR("framebuffer init failed %d\n", ret);
8677 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8678 intel_fb->obj = obj;
8682 static struct drm_framebuffer *
8683 intel_user_framebuffer_create(struct drm_device *dev,
8684 struct drm_file *filp,
8685 struct drm_mode_fb_cmd2 *mode_cmd)
8687 struct drm_i915_gem_object *obj;
8689 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8690 mode_cmd->handles[0]));
8691 if (&obj->base == NULL)
8692 return ERR_PTR(-ENOENT);
8694 return intel_framebuffer_create(dev, mode_cmd, obj);
8697 static const struct drm_mode_config_funcs intel_mode_funcs = {
8698 .fb_create = intel_user_framebuffer_create,
8699 .output_poll_changed = intel_fb_output_poll_changed,
8702 /* Set up chip specific display functions */
8703 static void intel_init_display(struct drm_device *dev)
8705 struct drm_i915_private *dev_priv = dev->dev_private;
8707 /* We always want a DPMS function */
8708 if (IS_HASWELL(dev)) {
8709 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8710 dev_priv->display.crtc_enable = haswell_crtc_enable;
8711 dev_priv->display.crtc_disable = haswell_crtc_disable;
8712 dev_priv->display.off = haswell_crtc_off;
8713 dev_priv->display.update_plane = ironlake_update_plane;
8714 } else if (HAS_PCH_SPLIT(dev)) {
8715 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8716 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8717 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8718 dev_priv->display.off = ironlake_crtc_off;
8719 dev_priv->display.update_plane = ironlake_update_plane;
8721 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8722 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8723 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8724 dev_priv->display.off = i9xx_crtc_off;
8725 dev_priv->display.update_plane = i9xx_update_plane;
8728 /* Returns the core display clock speed */
8729 if (IS_VALLEYVIEW(dev))
8730 dev_priv->display.get_display_clock_speed =
8731 valleyview_get_display_clock_speed;
8732 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8733 dev_priv->display.get_display_clock_speed =
8734 i945_get_display_clock_speed;
8735 else if (IS_I915G(dev))
8736 dev_priv->display.get_display_clock_speed =
8737 i915_get_display_clock_speed;
8738 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8739 dev_priv->display.get_display_clock_speed =
8740 i9xx_misc_get_display_clock_speed;
8741 else if (IS_I915GM(dev))
8742 dev_priv->display.get_display_clock_speed =
8743 i915gm_get_display_clock_speed;
8744 else if (IS_I865G(dev))
8745 dev_priv->display.get_display_clock_speed =
8746 i865_get_display_clock_speed;
8747 else if (IS_I85X(dev))
8748 dev_priv->display.get_display_clock_speed =
8749 i855_get_display_clock_speed;
8751 dev_priv->display.get_display_clock_speed =
8752 i830_get_display_clock_speed;
8754 if (HAS_PCH_SPLIT(dev)) {
8756 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8757 dev_priv->display.write_eld = ironlake_write_eld;
8758 } else if (IS_GEN6(dev)) {
8759 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8760 dev_priv->display.write_eld = ironlake_write_eld;
8761 } else if (IS_IVYBRIDGE(dev)) {
8762 /* FIXME: detect B0+ stepping and use auto training */
8763 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8764 dev_priv->display.write_eld = ironlake_write_eld;
8765 dev_priv->display.modeset_global_resources =
8766 ivb_modeset_global_resources;
8767 } else if (IS_HASWELL(dev)) {
8768 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8769 dev_priv->display.write_eld = haswell_write_eld;
8771 dev_priv->display.update_wm = NULL;
8772 } else if (IS_G4X(dev)) {
8773 dev_priv->display.write_eld = g4x_write_eld;
8776 /* Default just returns -ENODEV to indicate unsupported */
8777 dev_priv->display.queue_flip = intel_default_queue_flip;
8779 switch (INTEL_INFO(dev)->gen) {
8781 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8785 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8790 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8794 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8797 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8803 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8804 * resume, or other times. This quirk makes sure that's the case for
8807 static void quirk_pipea_force(struct drm_device *dev)
8809 struct drm_i915_private *dev_priv = dev->dev_private;
8811 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8812 DRM_INFO("applying pipe a force quirk\n");
8816 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8818 static void quirk_ssc_force_disable(struct drm_device *dev)
8820 struct drm_i915_private *dev_priv = dev->dev_private;
8821 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8822 DRM_INFO("applying lvds SSC disable quirk\n");
8826 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8829 static void quirk_invert_brightness(struct drm_device *dev)
8831 struct drm_i915_private *dev_priv = dev->dev_private;
8832 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8833 DRM_INFO("applying inverted panel brightness quirk\n");
8836 struct intel_quirk {
8838 int subsystem_vendor;
8839 int subsystem_device;
8840 void (*hook)(struct drm_device *dev);
8843 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8844 struct intel_dmi_quirk {
8845 void (*hook)(struct drm_device *dev);
8846 const struct dmi_system_id (*dmi_id_list)[];
8849 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8851 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8855 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8857 .dmi_id_list = &(const struct dmi_system_id[]) {
8859 .callback = intel_dmi_reverse_brightness,
8860 .ident = "NCR Corporation",
8861 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8862 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8865 { } /* terminating entry */
8867 .hook = quirk_invert_brightness,
8871 static struct intel_quirk intel_quirks[] = {
8872 /* HP Mini needs pipe A force quirk (LP: #322104) */
8873 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8875 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8876 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8878 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8879 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8881 /* 830/845 need to leave pipe A & dpll A up */
8882 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8883 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8885 /* Lenovo U160 cannot use SSC on LVDS */
8886 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8888 /* Sony Vaio Y cannot use SSC on LVDS */
8889 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8891 /* Acer Aspire 5734Z must invert backlight brightness */
8892 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8895 static void intel_init_quirks(struct drm_device *dev)
8897 struct pci_dev *d = dev->pdev;
8900 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8901 struct intel_quirk *q = &intel_quirks[i];
8903 if (d->device == q->device &&
8904 (d->subsystem_vendor == q->subsystem_vendor ||
8905 q->subsystem_vendor == PCI_ANY_ID) &&
8906 (d->subsystem_device == q->subsystem_device ||
8907 q->subsystem_device == PCI_ANY_ID))
8910 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8911 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8912 intel_dmi_quirks[i].hook(dev);
8916 /* Disable the VGA plane that we never use */
8917 static void i915_disable_vga(struct drm_device *dev)
8919 struct drm_i915_private *dev_priv = dev->dev_private;
8923 if (HAS_PCH_SPLIT(dev))
8924 vga_reg = CPU_VGACNTRL;
8928 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8929 outb(SR01, VGA_SR_INDEX);
8930 sr1 = inb(VGA_SR_DATA);
8931 outb(sr1 | 1<<5, VGA_SR_DATA);
8932 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8935 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8936 POSTING_READ(vga_reg);
8939 void intel_modeset_init_hw(struct drm_device *dev)
8941 /* We attempt to init the necessary power wells early in the initialization
8942 * time, so the subsystems that expect power to be enabled can work.
8944 intel_init_power_wells(dev);
8946 intel_prepare_ddi(dev);
8948 intel_init_clock_gating(dev);
8950 mutex_lock(&dev->struct_mutex);
8951 intel_enable_gt_powersave(dev);
8952 mutex_unlock(&dev->struct_mutex);
8955 void intel_modeset_init(struct drm_device *dev)
8957 struct drm_i915_private *dev_priv = dev->dev_private;
8960 drm_mode_config_init(dev);
8962 dev->mode_config.min_width = 0;
8963 dev->mode_config.min_height = 0;
8965 dev->mode_config.preferred_depth = 24;
8966 dev->mode_config.prefer_shadow = 1;
8968 dev->mode_config.funcs = &intel_mode_funcs;
8970 intel_init_quirks(dev);
8974 intel_init_display(dev);
8977 dev->mode_config.max_width = 2048;
8978 dev->mode_config.max_height = 2048;
8979 } else if (IS_GEN3(dev)) {
8980 dev->mode_config.max_width = 4096;
8981 dev->mode_config.max_height = 4096;
8983 dev->mode_config.max_width = 8192;
8984 dev->mode_config.max_height = 8192;
8986 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8988 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8989 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8991 for (i = 0; i < dev_priv->num_pipe; i++) {
8992 intel_crtc_init(dev, i);
8993 ret = intel_plane_init(dev, i);
8995 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8998 intel_cpu_pll_init(dev);
8999 intel_pch_pll_init(dev);
9001 /* Just disable it once at startup */
9002 i915_disable_vga(dev);
9003 intel_setup_outputs(dev);
9007 intel_connector_break_all_links(struct intel_connector *connector)
9009 connector->base.dpms = DRM_MODE_DPMS_OFF;
9010 connector->base.encoder = NULL;
9011 connector->encoder->connectors_active = false;
9012 connector->encoder->base.crtc = NULL;
9015 static void intel_enable_pipe_a(struct drm_device *dev)
9017 struct intel_connector *connector;
9018 struct drm_connector *crt = NULL;
9019 struct intel_load_detect_pipe load_detect_temp;
9021 /* We can't just switch on the pipe A, we need to set things up with a
9022 * proper mode and output configuration. As a gross hack, enable pipe A
9023 * by enabling the load detect pipe once. */
9024 list_for_each_entry(connector,
9025 &dev->mode_config.connector_list,
9027 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9028 crt = &connector->base;
9036 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9037 intel_release_load_detect_pipe(crt, &load_detect_temp);
9043 intel_check_plane_mapping(struct intel_crtc *crtc)
9045 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
9048 if (dev_priv->num_pipe == 1)
9051 reg = DSPCNTR(!crtc->plane);
9052 val = I915_READ(reg);
9054 if ((val & DISPLAY_PLANE_ENABLE) &&
9055 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9061 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9063 struct drm_device *dev = crtc->base.dev;
9064 struct drm_i915_private *dev_priv = dev->dev_private;
9067 /* Clear any frame start delays used for debugging left by the BIOS */
9068 reg = PIPECONF(crtc->cpu_transcoder);
9069 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9071 /* We need to sanitize the plane -> pipe mapping first because this will
9072 * disable the crtc (and hence change the state) if it is wrong. Note
9073 * that gen4+ has a fixed plane -> pipe mapping. */
9074 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9075 struct intel_connector *connector;
9078 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9079 crtc->base.base.id);
9081 /* Pipe has the wrong plane attached and the plane is active.
9082 * Temporarily change the plane mapping and disable everything
9084 plane = crtc->plane;
9085 crtc->plane = !plane;
9086 dev_priv->display.crtc_disable(&crtc->base);
9087 crtc->plane = plane;
9089 /* ... and break all links. */
9090 list_for_each_entry(connector, &dev->mode_config.connector_list,
9092 if (connector->encoder->base.crtc != &crtc->base)
9095 intel_connector_break_all_links(connector);
9098 WARN_ON(crtc->active);
9099 crtc->base.enabled = false;
9102 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9103 crtc->pipe == PIPE_A && !crtc->active) {
9104 /* BIOS forgot to enable pipe A, this mostly happens after
9105 * resume. Force-enable the pipe to fix this, the update_dpms
9106 * call below we restore the pipe to the right state, but leave
9107 * the required bits on. */
9108 intel_enable_pipe_a(dev);
9111 /* Adjust the state of the output pipe according to whether we
9112 * have active connectors/encoders. */
9113 intel_crtc_update_dpms(&crtc->base);
9115 if (crtc->active != crtc->base.enabled) {
9116 struct intel_encoder *encoder;
9118 /* This can happen either due to bugs in the get_hw_state
9119 * functions or because the pipe is force-enabled due to the
9121 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9123 crtc->base.enabled ? "enabled" : "disabled",
9124 crtc->active ? "enabled" : "disabled");
9126 crtc->base.enabled = crtc->active;
9128 /* Because we only establish the connector -> encoder ->
9129 * crtc links if something is active, this means the
9130 * crtc is now deactivated. Break the links. connector
9131 * -> encoder links are only establish when things are
9132 * actually up, hence no need to break them. */
9133 WARN_ON(crtc->active);
9135 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9136 WARN_ON(encoder->connectors_active);
9137 encoder->base.crtc = NULL;
9142 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9144 struct intel_connector *connector;
9145 struct drm_device *dev = encoder->base.dev;
9147 /* We need to check both for a crtc link (meaning that the
9148 * encoder is active and trying to read from a pipe) and the
9149 * pipe itself being active. */
9150 bool has_active_crtc = encoder->base.crtc &&
9151 to_intel_crtc(encoder->base.crtc)->active;
9153 if (encoder->connectors_active && !has_active_crtc) {
9154 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9155 encoder->base.base.id,
9156 drm_get_encoder_name(&encoder->base));
9158 /* Connector is active, but has no active pipe. This is
9159 * fallout from our resume register restoring. Disable
9160 * the encoder manually again. */
9161 if (encoder->base.crtc) {
9162 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9163 encoder->base.base.id,
9164 drm_get_encoder_name(&encoder->base));
9165 encoder->disable(encoder);
9168 /* Inconsistent output/port/pipe state happens presumably due to
9169 * a bug in one of the get_hw_state functions. Or someplace else
9170 * in our code, like the register restore mess on resume. Clamp
9171 * things to off as a safer default. */
9172 list_for_each_entry(connector,
9173 &dev->mode_config.connector_list,
9175 if (connector->encoder != encoder)
9178 intel_connector_break_all_links(connector);
9181 /* Enabled encoders without active connectors will be fixed in
9182 * the crtc fixup. */
9185 static void i915_redisable_vga(struct drm_device *dev)
9187 struct drm_i915_private *dev_priv = dev->dev_private;
9190 if (HAS_PCH_SPLIT(dev))
9191 vga_reg = CPU_VGACNTRL;
9195 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9196 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9197 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9198 POSTING_READ(vga_reg);
9202 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9203 * and i915 state tracking structures. */
9204 void intel_modeset_setup_hw_state(struct drm_device *dev,
9207 struct drm_i915_private *dev_priv = dev->dev_private;
9210 struct intel_crtc *crtc;
9211 struct intel_encoder *encoder;
9212 struct intel_connector *connector;
9214 if (IS_HASWELL(dev)) {
9215 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9217 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9218 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9219 case TRANS_DDI_EDP_INPUT_A_ON:
9220 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9223 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9226 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9231 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9232 crtc->cpu_transcoder = TRANSCODER_EDP;
9234 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9239 for_each_pipe(pipe) {
9240 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9242 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9243 if (tmp & PIPECONF_ENABLE)
9244 crtc->active = true;
9246 crtc->active = false;
9248 crtc->base.enabled = crtc->active;
9250 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9252 crtc->active ? "enabled" : "disabled");
9255 if (IS_HASWELL(dev))
9256 intel_ddi_setup_hw_pll_state(dev);
9258 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9262 if (encoder->get_hw_state(encoder, &pipe)) {
9263 encoder->base.crtc =
9264 dev_priv->pipe_to_crtc_mapping[pipe];
9266 encoder->base.crtc = NULL;
9269 encoder->connectors_active = false;
9270 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9271 encoder->base.base.id,
9272 drm_get_encoder_name(&encoder->base),
9273 encoder->base.crtc ? "enabled" : "disabled",
9277 list_for_each_entry(connector, &dev->mode_config.connector_list,
9279 if (connector->get_hw_state(connector)) {
9280 connector->base.dpms = DRM_MODE_DPMS_ON;
9281 connector->encoder->connectors_active = true;
9282 connector->base.encoder = &connector->encoder->base;
9284 connector->base.dpms = DRM_MODE_DPMS_OFF;
9285 connector->base.encoder = NULL;
9287 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9288 connector->base.base.id,
9289 drm_get_connector_name(&connector->base),
9290 connector->base.encoder ? "enabled" : "disabled");
9293 /* HW state is read out, now we need to sanitize this mess. */
9294 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9296 intel_sanitize_encoder(encoder);
9299 for_each_pipe(pipe) {
9300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9301 intel_sanitize_crtc(crtc);
9304 if (force_restore) {
9305 for_each_pipe(pipe) {
9306 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9307 intel_set_mode(&crtc->base, &crtc->base.mode,
9308 crtc->base.x, crtc->base.y, crtc->base.fb);
9311 i915_redisable_vga(dev);
9313 intel_modeset_update_staged_output_state(dev);
9316 intel_modeset_check_state(dev);
9318 drm_mode_config_reset(dev);
9321 void intel_modeset_gem_init(struct drm_device *dev)
9323 intel_modeset_init_hw(dev);
9325 intel_setup_overlay(dev);
9327 intel_modeset_setup_hw_state(dev, false);
9330 void intel_modeset_cleanup(struct drm_device *dev)
9332 struct drm_i915_private *dev_priv = dev->dev_private;
9333 struct drm_crtc *crtc;
9334 struct intel_crtc *intel_crtc;
9336 drm_kms_helper_poll_fini(dev);
9337 mutex_lock(&dev->struct_mutex);
9339 intel_unregister_dsm_handler();
9342 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9343 /* Skip inactive CRTCs */
9347 intel_crtc = to_intel_crtc(crtc);
9348 intel_increase_pllclock(crtc);
9351 intel_disable_fbc(dev);
9353 intel_disable_gt_powersave(dev);
9355 ironlake_teardown_rc6(dev);
9357 if (IS_VALLEYVIEW(dev))
9360 mutex_unlock(&dev->struct_mutex);
9362 /* Disable the irq before mode object teardown, for the irq might
9363 * enqueue unpin/hotplug work. */
9364 drm_irq_uninstall(dev);
9365 cancel_work_sync(&dev_priv->hotplug_work);
9366 cancel_work_sync(&dev_priv->rps.work);
9368 /* flush any delayed tasks or pending work */
9369 flush_scheduled_work();
9371 drm_mode_config_cleanup(dev);
9375 * Return which encoder is currently attached for connector.
9377 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9379 return &intel_attached_encoder(connector)->base;
9382 void intel_connector_attach_encoder(struct intel_connector *connector,
9383 struct intel_encoder *encoder)
9385 connector->encoder = encoder;
9386 drm_mode_connector_attach_encoder(&connector->base,
9391 * set vga decode state - true == enable VGA decode
9393 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9395 struct drm_i915_private *dev_priv = dev->dev_private;
9398 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9400 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9402 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9403 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9407 #ifdef CONFIG_DEBUG_FS
9408 #include <linux/seq_file.h>
9410 struct intel_display_error_state {
9411 struct intel_cursor_error_state {
9416 } cursor[I915_MAX_PIPES];
9418 struct intel_pipe_error_state {
9428 } pipe[I915_MAX_PIPES];
9430 struct intel_plane_error_state {
9438 } plane[I915_MAX_PIPES];
9441 struct intel_display_error_state *
9442 intel_display_capture_error_state(struct drm_device *dev)
9444 drm_i915_private_t *dev_priv = dev->dev_private;
9445 struct intel_display_error_state *error;
9446 enum transcoder cpu_transcoder;
9449 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9454 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9456 error->cursor[i].control = I915_READ(CURCNTR(i));
9457 error->cursor[i].position = I915_READ(CURPOS(i));
9458 error->cursor[i].base = I915_READ(CURBASE(i));
9460 error->plane[i].control = I915_READ(DSPCNTR(i));
9461 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9462 error->plane[i].size = I915_READ(DSPSIZE(i));
9463 error->plane[i].pos = I915_READ(DSPPOS(i));
9464 error->plane[i].addr = I915_READ(DSPADDR(i));
9465 if (INTEL_INFO(dev)->gen >= 4) {
9466 error->plane[i].surface = I915_READ(DSPSURF(i));
9467 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9470 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9471 error->pipe[i].source = I915_READ(PIPESRC(i));
9472 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9473 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9474 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9475 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9476 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9477 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9484 intel_display_print_error_state(struct seq_file *m,
9485 struct drm_device *dev,
9486 struct intel_display_error_state *error)
9488 drm_i915_private_t *dev_priv = dev->dev_private;
9491 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9493 seq_printf(m, "Pipe [%d]:\n", i);
9494 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9495 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9496 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9497 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9498 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9499 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9500 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9501 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9503 seq_printf(m, "Plane [%d]:\n", i);
9504 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9505 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9506 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9507 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9508 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9509 if (INTEL_INFO(dev)->gen >= 4) {
9510 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9511 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9514 seq_printf(m, "Cursor [%d]:\n", i);
9515 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9516 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9517 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);