drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/cpufreq.h>
  29 #include <linux/module.h>
  30 #include <linux/input.h>
  31 #include <linux/i2c.h>
  32 #include <linux/kernel.h>
  33 #include <linux/slab.h>
  34 #include <linux/vgaarb.h>
  35 #include <drm/drm_edid.h>
  36 #include "drmP.h"
  37 #include "intel_drv.h"
  38 #include "i915_drm.h"
  39 #include "i915_drv.h"
  40 #include "i915_trace.h"
  41 #include "drm_dp_helper.h"
  42 #include "drm_crtc_helper.h"
  43 #include <linux/dma_remapping.h>
  44
  45 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  46
  47 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  48 static void intel_update_watermarks(struct drm_device *dev);
  49 static void intel_increase_pllclock(struct drm_crtc *crtc);
  50 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  51
  52 typedef struct {
  53         /* given values */
  54         int n;
  55         int m1, m2;
  56         int p1, p2;
  57         /* derived values */
  58         int     dot;
  59         int     vco;
  60         int     m;
  61         int     p;
  62 } intel_clock_t;
  63
  64 typedef struct {
  65         int     min, max;
  66 } intel_range_t;
  67
  68 typedef struct {
  69         int     dot_limit;
  70         int     p2_slow, p2_fast;
  71 } intel_p2_t;
  72
  73 #define INTEL_P2_NUM                  2
  74 typedef struct intel_limit intel_limit_t;
  75 struct intel_limit {
  76         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  77         intel_p2_t          p2;
  78         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  79                         int, int, intel_clock_t *, intel_clock_t *);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 static bool
  86 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  87                     int target, int refclk, intel_clock_t *match_clock,
  88                     intel_clock_t *best_clock);
  89 static bool
  90 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  91                         int target, int refclk, intel_clock_t *match_clock,
  92                         intel_clock_t *best_clock);
  93
  94 static bool
  95 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  96                       int target, int refclk, intel_clock_t *match_clock,
  97                       intel_clock_t *best_clock);
  98 static bool
  99 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 100                            int target, int refclk, intel_clock_t *match_clock,
 101                            intel_clock_t *best_clock);
 102
 103 static inline u32 /* units of 100MHz */
 104 intel_fdi_link_freq(struct drm_device *dev)
 105 {
 106         if (IS_GEN5(dev)) {
 107                 struct drm_i915_private *dev_priv = dev->dev_private;
 108                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 109         } else
 110                 return 27;
 111 }
 112
 113 static const intel_limit_t intel_limits_i8xx_dvo = {
 114         .dot = { .min = 25000, .max = 350000 },
 115         .vco = { .min = 930000, .max = 1400000 },
 116         .n = { .min = 3, .max = 16 },
 117         .m = { .min = 96, .max = 140 },
 118         .m1 = { .min = 18, .max = 26 },
 119         .m2 = { .min = 6, .max = 16 },
 120         .p = { .min = 4, .max = 128 },
 121         .p1 = { .min = 2, .max = 33 },
 122         .p2 = { .dot_limit = 165000,
 123                 .p2_slow = 4, .p2_fast = 2 },
 124         .find_pll = intel_find_best_PLL,
 125 };
 126
 127 static const intel_limit_t intel_limits_i8xx_lvds = {
 128         .dot = { .min = 25000, .max = 350000 },
 129         .vco = { .min = 930000, .max = 1400000 },
 130         .n = { .min = 3, .max = 16 },
 131         .m = { .min = 96, .max = 140 },
 132         .m1 = { .min = 18, .max = 26 },
 133         .m2 = { .min = 6, .max = 16 },
 134         .p = { .min = 4, .max = 128 },
 135         .p1 = { .min = 1, .max = 6 },
 136         .p2 = { .dot_limit = 165000,
 137                 .p2_slow = 14, .p2_fast = 7 },
 138         .find_pll = intel_find_best_PLL,
 139 };
 140
 141 static const intel_limit_t intel_limits_i9xx_sdvo = {
 142         .dot = { .min = 20000, .max = 400000 },
 143         .vco = { .min = 1400000, .max = 2800000 },
 144         .n = { .min = 1, .max = 6 },
 145         .m = { .min = 70, .max = 120 },
 146         .m1 = { .min = 10, .max = 22 },
 147         .m2 = { .min = 5, .max = 9 },
 148         .p = { .min = 5, .max = 80 },
 149         .p1 = { .min = 1, .max = 8 },
 150         .p2 = { .dot_limit = 200000,
 151                 .p2_slow = 10, .p2_fast = 5 },
 152         .find_pll = intel_find_best_PLL,
 153 };
 154
 155 static const intel_limit_t intel_limits_i9xx_lvds = {
 156         .dot = { .min = 20000, .max = 400000 },
 157         .vco = { .min = 1400000, .max = 2800000 },
 158         .n = { .min = 1, .max = 6 },
 159         .m = { .min = 70, .max = 120 },
 160         .m1 = { .min = 10, .max = 22 },
 161         .m2 = { .min = 5, .max = 9 },
 162         .p = { .min = 7, .max = 98 },
 163         .p1 = { .min = 1, .max = 8 },
 164         .p2 = { .dot_limit = 112000,
 165                 .p2_slow = 14, .p2_fast = 7 },
 166         .find_pll = intel_find_best_PLL,
 167 };
 168
 169
 170 static const intel_limit_t intel_limits_g4x_sdvo = {
 171         .dot = { .min = 25000, .max = 270000 },
 172         .vco = { .min = 1750000, .max = 3500000},
 173         .n = { .min = 1, .max = 4 },
 174         .m = { .min = 104, .max = 138 },
 175         .m1 = { .min = 17, .max = 23 },
 176         .m2 = { .min = 5, .max = 11 },
 177         .p = { .min = 10, .max = 30 },
 178         .p1 = { .min = 1, .max = 3},
 179         .p2 = { .dot_limit = 270000,
 180                 .p2_slow = 10,
 181                 .p2_fast = 10
 182         },
 183         .find_pll = intel_g4x_find_best_PLL,
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_hdmi = {
 187         .dot = { .min = 22000, .max = 400000 },
 188         .vco = { .min = 1750000, .max = 3500000},
 189         .n = { .min = 1, .max = 4 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 16, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 5, .max = 80 },
 194         .p1 = { .min = 1, .max = 8},
 195         .p2 = { .dot_limit = 165000,
 196                 .p2_slow = 10, .p2_fast = 5 },
 197         .find_pll = intel_g4x_find_best_PLL,
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 201         .dot = { .min = 20000, .max = 115000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 28, .max = 112 },
 208         .p1 = { .min = 2, .max = 8 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 14, .p2_fast = 14
 211         },
 212         .find_pll = intel_g4x_find_best_PLL,
 213 };
 214
 215 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 216         .dot = { .min = 80000, .max = 224000 },
 217         .vco = { .min = 1750000, .max = 3500000 },
 218         .n = { .min = 1, .max = 3 },
 219         .m = { .min = 104, .max = 138 },
 220         .m1 = { .min = 17, .max = 23 },
 221         .m2 = { .min = 5, .max = 11 },
 222         .p = { .min = 14, .max = 42 },
 223         .p1 = { .min = 2, .max = 6 },
 224         .p2 = { .dot_limit = 0,
 225                 .p2_slow = 7, .p2_fast = 7
 226         },
 227         .find_pll = intel_g4x_find_best_PLL,
 228 };
 229
 230 static const intel_limit_t intel_limits_g4x_display_port = {
 231         .dot = { .min = 161670, .max = 227000 },
 232         .vco = { .min = 1750000, .max = 3500000},
 233         .n = { .min = 1, .max = 2 },
 234         .m = { .min = 97, .max = 108 },
 235         .m1 = { .min = 0x10, .max = 0x12 },
 236         .m2 = { .min = 0x05, .max = 0x06 },
 237         .p = { .min = 10, .max = 20 },
 238         .p1 = { .min = 1, .max = 2},
 239         .p2 = { .dot_limit = 0,
 240                 .p2_slow = 10, .p2_fast = 10 },
 241         .find_pll = intel_find_pll_g4x_dp,
 242 };
 243
 244 static const intel_limit_t intel_limits_pineview_sdvo = {
 245         .dot = { .min = 20000, .max = 400000},
 246         .vco = { .min = 1700000, .max = 3500000 },
 247         /* Pineview's Ncounter is a ring counter */
 248         .n = { .min = 3, .max = 6 },
 249         .m = { .min = 2, .max = 256 },
 250         /* Pineview only has one combined m divider, which we treat as m2. */
 251         .m1 = { .min = 0, .max = 0 },
 252         .m2 = { .min = 0, .max = 254 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 200000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257         .find_pll = intel_find_best_PLL,
 258 };
 259
 260 static const intel_limit_t intel_limits_pineview_lvds = {
 261         .dot = { .min = 20000, .max = 400000 },
 262         .vco = { .min = 1700000, .max = 3500000 },
 263         .n = { .min = 3, .max = 6 },
 264         .m = { .min = 2, .max = 256 },
 265         .m1 = { .min = 0, .max = 0 },
 266         .m2 = { .min = 0, .max = 254 },
 267         .p = { .min = 7, .max = 112 },
 268         .p1 = { .min = 1, .max = 8 },
 269         .p2 = { .dot_limit = 112000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271         .find_pll = intel_find_best_PLL,
 272 };
 273
 274 /* Ironlake / Sandybridge
 275  *
 276  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 277  * the range value for them is (actual_value - 2).
 278  */
 279 static const intel_limit_t intel_limits_ironlake_dac = {
 280         .dot = { .min = 25000, .max = 350000 },
 281         .vco = { .min = 1760000, .max = 3510000 },
 282         .n = { .min = 1, .max = 5 },
 283         .m = { .min = 79, .max = 127 },
 284         .m1 = { .min = 12, .max = 22 },
 285         .m2 = { .min = 5, .max = 9 },
 286         .p = { .min = 5, .max = 80 },
 287         .p1 = { .min = 1, .max = 8 },
 288         .p2 = { .dot_limit = 225000,
 289                 .p2_slow = 10, .p2_fast = 5 },
 290         .find_pll = intel_g4x_find_best_PLL,
 291 };
 292
 293 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 294         .dot = { .min = 25000, .max = 350000 },
 295         .vco = { .min = 1760000, .max = 3510000 },
 296         .n = { .min = 1, .max = 3 },
 297         .m = { .min = 79, .max = 118 },
 298         .m1 = { .min = 12, .max = 22 },
 299         .m2 = { .min = 5, .max = 9 },
 300         .p = { .min = 28, .max = 112 },
 301         .p1 = { .min = 2, .max = 8 },
 302         .p2 = { .dot_limit = 225000,
 303                 .p2_slow = 14, .p2_fast = 14 },
 304         .find_pll = intel_g4x_find_best_PLL,
 305 };
 306
 307 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 308         .dot = { .min = 25000, .max = 350000 },
 309         .vco = { .min = 1760000, .max = 3510000 },
 310         .n = { .min = 1, .max = 3 },
 311         .m = { .min = 79, .max = 127 },
 312         .m1 = { .min = 12, .max = 22 },
 313         .m2 = { .min = 5, .max = 9 },
 314         .p = { .min = 14, .max = 56 },
 315         .p1 = { .min = 2, .max = 8 },
 316         .p2 = { .dot_limit = 225000,
 317                 .p2_slow = 7, .p2_fast = 7 },
 318         .find_pll = intel_g4x_find_best_PLL,
 319 };
 320
 321 /* LVDS 100mhz refclk limits. */
 322 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 323         .dot = { .min = 25000, .max = 350000 },
 324         .vco = { .min = 1760000, .max = 3510000 },
 325         .n = { .min = 1, .max = 2 },
 326         .m = { .min = 79, .max = 126 },
 327         .m1 = { .min = 12, .max = 22 },
 328         .m2 = { .min = 5, .max = 9 },
 329         .p = { .min = 28, .max = 112 },
 330         .p1 = { .min = 2, .max = 8 },
 331         .p2 = { .dot_limit = 225000,
 332                 .p2_slow = 14, .p2_fast = 14 },
 333         .find_pll = intel_g4x_find_best_PLL,
 334 };
 335
 336 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 337         .dot = { .min = 25000, .max = 350000 },
 338         .vco = { .min = 1760000, .max = 3510000 },
 339         .n = { .min = 1, .max = 3 },
 340         .m = { .min = 79, .max = 126 },
 341         .m1 = { .min = 12, .max = 22 },
 342         .m2 = { .min = 5, .max = 9 },
 343         .p = { .min = 14, .max = 42 },
 344         .p1 = { .min = 2, .max = 6 },
 345         .p2 = { .dot_limit = 225000,
 346                 .p2_slow = 7, .p2_fast = 7 },
 347         .find_pll = intel_g4x_find_best_PLL,
 348 };
 349
 350 static const intel_limit_t intel_limits_ironlake_display_port = {
 351         .dot = { .min = 25000, .max = 350000 },
 352         .vco = { .min = 1760000, .max = 3510000},
 353         .n = { .min = 1, .max = 2 },
 354         .m = { .min = 81, .max = 90 },
 355         .m1 = { .min = 12, .max = 22 },
 356         .m2 = { .min = 5, .max = 9 },
 357         .p = { .min = 10, .max = 20 },
 358         .p1 = { .min = 1, .max = 2},
 359         .p2 = { .dot_limit = 0,
 360                 .p2_slow = 10, .p2_fast = 10 },
 361         .find_pll = intel_find_pll_ironlake_dp,
 362 };
 363
 364 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 365 {
 366         unsigned long flags;
 367         u32 val = 0;
 368
 369         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 370         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 371                 DRM_ERROR("DPIO idle wait timed out\n");
 372                 goto out_unlock;
 373         }
 374
 375         I915_WRITE(DPIO_REG, reg);
 376         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 377                    DPIO_BYTE);
 378         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 379                 DRM_ERROR("DPIO read wait timed out\n");
 380                 goto out_unlock;
 381         }
 382         val = I915_READ(DPIO_DATA);
 383
 384 out_unlock:
 385         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 386         return val;
 387 }
 388
 389 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 390                              u32 val)
 391 {
 392         unsigned long flags;
 393
 394         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 395         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 396                 DRM_ERROR("DPIO idle wait timed out\n");
 397                 goto out_unlock;
 398         }
 399
 400         I915_WRITE(DPIO_DATA, val);
 401         I915_WRITE(DPIO_REG, reg);
 402         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 403                    DPIO_BYTE);
 404         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 405                 DRM_ERROR("DPIO write wait timed out\n");
 406
 407 out_unlock:
 408         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 409 }
 410
 411 static void vlv_init_dpio(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         /* Reset the DPIO config */
 416         I915_WRITE(DPIO_CTL, 0);
 417         POSTING_READ(DPIO_CTL);
 418         I915_WRITE(DPIO_CTL, 1);
 419         POSTING_READ(DPIO_CTL);
 420 }
 421
 422 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 423 {
 424         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 425         return 1;
 426 }
 427
 428 static const struct dmi_system_id intel_dual_link_lvds[] = {
 429         {
 430                 .callback = intel_dual_link_lvds_callback,
 431                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 432                 .matches = {
 433                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 434                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 435                 },
 436         },
 437         { }     /* terminating entry */
 438 };
 439
 440 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 441                               unsigned int reg)
 442 {
 443         unsigned int val;
 444
 445         /* use the module option value if specified */
 446         if (i915_lvds_channel_mode > 0)
 447                 return i915_lvds_channel_mode == 2;
 448
 449         if (dmi_check_system(intel_dual_link_lvds))
 450                 return true;
 451
 452         if (dev_priv->lvds_val)
 453                 val = dev_priv->lvds_val;
 454         else {
 455                 /* BIOS should set the proper LVDS register value at boot, but
 456                  * in reality, it doesn't set the value when the lid is closed;
 457                  * we need to check "the value to be set" in VBT when LVDS
 458                  * register is uninitialized.
 459                  */
 460                 val = I915_READ(reg);
 461                 if (!(val & ~LVDS_DETECTED))
 462                         val = dev_priv->bios_lvds_val;
 463                 dev_priv->lvds_val = val;
 464         }
 465         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 466 }
 467
 468 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 469                                                 int refclk)
 470 {
 471         struct drm_device *dev = crtc->dev;
 472         struct drm_i915_private *dev_priv = dev->dev_private;
 473         const intel_limit_t *limit;
 474
 475         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 476                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 477                         /* LVDS dual channel */
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_dual_lvds;
 482                 } else {
 483                         if (refclk == 100000)
 484                                 limit = &intel_limits_ironlake_single_lvds_100m;
 485                         else
 486                                 limit = &intel_limits_ironlake_single_lvds;
 487                 }
 488         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 489                         HAS_eDP)
 490                 limit = &intel_limits_ironlake_display_port;
 491         else
 492                 limit = &intel_limits_ironlake_dac;
 493
 494         return limit;
 495 }
 496
 497 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 498 {
 499         struct drm_device *dev = crtc->dev;
 500         struct drm_i915_private *dev_priv = dev->dev_private;
 501         const intel_limit_t *limit;
 502
 503         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 504                 if (is_dual_link_lvds(dev_priv, LVDS))
 505                         /* LVDS with dual channel */
 506                         limit = &intel_limits_g4x_dual_channel_lvds;
 507                 else
 508                         /* LVDS with dual channel */
 509                         limit = &intel_limits_g4x_single_channel_lvds;
 510         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 511                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 512                 limit = &intel_limits_g4x_hdmi;
 513         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 514                 limit = &intel_limits_g4x_sdvo;
 515         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 516                 limit = &intel_limits_g4x_display_port;
 517         } else /* The option is for other outputs */
 518                 limit = &intel_limits_i9xx_sdvo;
 519
 520         return limit;
 521 }
 522
 523 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 524 {
 525         struct drm_device *dev = crtc->dev;
 526         const intel_limit_t *limit;
 527
 528         if (HAS_PCH_SPLIT(dev))
 529                 limit = intel_ironlake_limit(crtc, refclk);
 530         else if (IS_G4X(dev)) {
 531                 limit = intel_g4x_limit(crtc);
 532         } else if (IS_PINEVIEW(dev)) {
 533                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_pineview_lvds;
 535                 else
 536                         limit = &intel_limits_pineview_sdvo;
 537         } else if (!IS_GEN2(dev)) {
 538                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_i9xx_lvds;
 540                 else
 541                         limit = &intel_limits_i9xx_sdvo;
 542         } else {
 543                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 544                         limit = &intel_limits_i8xx_lvds;
 545                 else
 546                         limit = &intel_limits_i8xx_dvo;
 547         }
 548         return limit;
 549 }
 550
 551 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 552 static void pineview_clock(int refclk, intel_clock_t *clock)
 553 {
 554         clock->m = clock->m2 + 2;
 555         clock->p = clock->p1 * clock->p2;
 556         clock->vco = refclk * clock->m / clock->n;
 557         clock->dot = clock->vco / clock->p;
 558 }
 559
 560 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 561 {
 562         if (IS_PINEVIEW(dev)) {
 563                 pineview_clock(refclk, clock);
 564                 return;
 565         }
 566         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 567         clock->p = clock->p1 * clock->p2;
 568         clock->vco = refclk * clock->m / (clock->n + 2);
 569         clock->dot = clock->vco / clock->p;
 570 }
 571
 572 /**
 573  * Returns whether any output on the specified pipe is of the specified type
 574  */
 575 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 576 {
 577         struct drm_device *dev = crtc->dev;
 578         struct drm_mode_config *mode_config = &dev->mode_config;
 579         struct intel_encoder *encoder;
 580
 581         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 582                 if (encoder->base.crtc == crtc && encoder->type == type)
 583                         return true;
 584
 585         return false;
 586 }
 587
 588 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 589 /**
 590  * Returns whether the given set of divisors are valid for a given refclk with
 591  * the given connectors.
 592  */
 593
 594 static bool intel_PLL_is_valid(struct drm_device *dev,
 595                                const intel_limit_t *limit,
 596                                const intel_clock_t *clock)
 597 {
 598         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 599                 INTELPllInvalid("p1 out of range\n");
 600         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 601                 INTELPllInvalid("p out of range\n");
 602         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 603                 INTELPllInvalid("m2 out of range\n");
 604         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 605                 INTELPllInvalid("m1 out of range\n");
 606         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 607                 INTELPllInvalid("m1 <= m2\n");
 608         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 609                 INTELPllInvalid("m out of range\n");
 610         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 611                 INTELPllInvalid("n out of range\n");
 612         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 613                 INTELPllInvalid("vco out of range\n");
 614         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 615          * connector, etc., rather than just a single range.
 616          */
 617         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 618                 INTELPllInvalid("dot out of range\n");
 619
 620         return true;
 621 }
 622
 623 static bool
 624 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 625                     int target, int refclk, intel_clock_t *match_clock,
 626                     intel_clock_t *best_clock)
 627
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct drm_i915_private *dev_priv = dev->dev_private;
 631         intel_clock_t clock;
 632         int err = target;
 633
 634         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 635             (I915_READ(LVDS)) != 0) {
 636                 /*
 637                  * For LVDS, if the panel is on, just rely on its current
 638                  * settings for dual-channel.  We haven't figured out how to
 639                  * reliably set up different single/dual channel state, if we
 640                  * even can.
 641                  */
 642                 if (is_dual_link_lvds(dev_priv, LVDS))
 643                         clock.p2 = limit->p2.p2_fast;
 644                 else
 645                         clock.p2 = limit->p2.p2_slow;
 646         } else {
 647                 if (target < limit->p2.dot_limit)
 648                         clock.p2 = limit->p2.p2_slow;
 649                 else
 650                         clock.p2 = limit->p2.p2_fast;
 651         }
 652
 653         memset(best_clock, 0, sizeof(*best_clock));
 654
 655         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 656              clock.m1++) {
 657                 for (clock.m2 = limit->m2.min;
 658                      clock.m2 <= limit->m2.max; clock.m2++) {
 659                         /* m1 is always 0 in Pineview */
 660                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 661                                 break;
 662                         for (clock.n = limit->n.min;
 663                              clock.n <= limit->n.max; clock.n++) {
 664                                 for (clock.p1 = limit->p1.min;
 665                                         clock.p1 <= limit->p1.max; clock.p1++) {
 666                                         int this_err;
 667
 668                                         intel_clock(dev, refclk, &clock);
 669                                         if (!intel_PLL_is_valid(dev, limit,
 670                                                                 &clock))
 671                                                 continue;
 672                                         if (match_clock &&
 673                                             clock.p != match_clock->p)
 674                                                 continue;
 675
 676                                         this_err = abs(clock.dot - target);
 677                                         if (this_err < err) {
 678                                                 *best_clock = clock;
 679                                                 err = this_err;
 680                                         }
 681                                 }
 682                         }
 683                 }
 684         }
 685
 686         return (err != target);
 687 }
 688
 689 static bool
 690 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 691                         int target, int refclk, intel_clock_t *match_clock,
 692                         intel_clock_t *best_clock)
 693 {
 694         struct drm_device *dev = crtc->dev;
 695         struct drm_i915_private *dev_priv = dev->dev_private;
 696         intel_clock_t clock;
 697         int max_n;
 698         bool found;
 699         /* approximately equals target * 0.00585 */
 700         int err_most = (target >> 8) + (target >> 9);
 701         found = false;
 702
 703         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 704                 int lvds_reg;
 705
 706                 if (HAS_PCH_SPLIT(dev))
 707                         lvds_reg = PCH_LVDS;
 708                 else
 709                         lvds_reg = LVDS;
 710                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 711                     LVDS_CLKB_POWER_UP)
 712                         clock.p2 = limit->p2.p2_fast;
 713                 else
 714                         clock.p2 = limit->p2.p2_slow;
 715         } else {
 716                 if (target < limit->p2.dot_limit)
 717                         clock.p2 = limit->p2.p2_slow;
 718                 else
 719                         clock.p2 = limit->p2.p2_fast;
 720         }
 721
 722         memset(best_clock, 0, sizeof(*best_clock));
 723         max_n = limit->n.max;
 724         /* based on hardware requirement, prefer smaller n to precision */
 725         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 726                 /* based on hardware requirement, prefere larger m1,m2 */
 727                 for (clock.m1 = limit->m1.max;
 728                      clock.m1 >= limit->m1.min; clock.m1--) {
 729                         for (clock.m2 = limit->m2.max;
 730                              clock.m2 >= limit->m2.min; clock.m2--) {
 731                                 for (clock.p1 = limit->p1.max;
 732                                      clock.p1 >= limit->p1.min; clock.p1--) {
 733                                         int this_err;
 734
 735                                         intel_clock(dev, refclk, &clock);
 736                                         if (!intel_PLL_is_valid(dev, limit,
 737                                                                 &clock))
 738                                                 continue;
 739                                         if (match_clock &&
 740                                             clock.p != match_clock->p)
 741                                                 continue;
 742
 743                                         this_err = abs(clock.dot - target);
 744                                         if (this_err < err_most) {
 745                                                 *best_clock = clock;
 746                                                 err_most = this_err;
 747                                                 max_n = clock.n;
 748                                                 found = true;
 749                                         }
 750                                 }
 751                         }
 752                 }
 753         }
 754         return found;
 755 }
 756
 757 static bool
 758 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 759                            int target, int refclk, intel_clock_t *match_clock,
 760                            intel_clock_t *best_clock)
 761 {
 762         struct drm_device *dev = crtc->dev;
 763         intel_clock_t clock;
 764
 765         if (target < 200000) {
 766                 clock.n = 1;
 767                 clock.p1 = 2;
 768                 clock.p2 = 10;
 769                 clock.m1 = 12;
 770                 clock.m2 = 9;
 771         } else {
 772                 clock.n = 2;
 773                 clock.p1 = 1;
 774                 clock.p2 = 10;
 775                 clock.m1 = 14;
 776                 clock.m2 = 8;
 777         }
 778         intel_clock(dev, refclk, &clock);
 779         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 780         return true;
 781 }
 782
 783 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 784 static bool
 785 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 786                       int target, int refclk, intel_clock_t *match_clock,
 787                       intel_clock_t *best_clock)
 788 {
 789         intel_clock_t clock;
 790         if (target < 200000) {
 791                 clock.p1 = 2;
 792                 clock.p2 = 10;
 793                 clock.n = 2;
 794                 clock.m1 = 23;
 795                 clock.m2 = 8;
 796         } else {
 797                 clock.p1 = 1;
 798                 clock.p2 = 10;
 799                 clock.n = 1;
 800                 clock.m1 = 14;
 801                 clock.m2 = 2;
 802         }
 803         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 804         clock.p = (clock.p1 * clock.p2);
 805         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 806         clock.vco = 0;
 807         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 808         return true;
 809 }
 810
 811 /**
 812  * intel_wait_for_vblank - wait for vblank on a given pipe
 813  * @dev: drm device
 814  * @pipe: pipe to wait for
 815  *
 816  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 817  * mode setting code.
 818  */
 819 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 820 {
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822         int pipestat_reg = PIPESTAT(pipe);
 823
 824         /* Clear existing vblank status. Note this will clear any other
 825          * sticky status fields as well.
 826          *
 827          * This races with i915_driver_irq_handler() with the result
 828          * that either function could miss a vblank event.  Here it is not
 829          * fatal, as we will either wait upon the next vblank interrupt or
 830          * timeout.  Generally speaking intel_wait_for_vblank() is only
 831          * called during modeset at which time the GPU should be idle and
 832          * should *not* be performing page flips and thus not waiting on
 833          * vblanks...
 834          * Currently, the result of us stealing a vblank from the irq
 835          * handler is that a single frame will be skipped during swapbuffers.
 836          */
 837         I915_WRITE(pipestat_reg,
 838                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 839
 840         /* Wait for vblank interrupt bit to set */
 841         if (wait_for(I915_READ(pipestat_reg) &
 842                      PIPE_VBLANK_INTERRUPT_STATUS,
 843                      50))
 844                 DRM_DEBUG_KMS("vblank wait timed out\n");
 845 }
 846
 847 /*
 848  * intel_wait_for_pipe_off - wait for pipe to turn off
 849  * @dev: drm device
 850  * @pipe: pipe to wait for
 851  *
 852  * After disabling a pipe, we can't wait for vblank in the usual way,
 853  * spinning on the vblank interrupt status bit, since we won't actually
 854  * see an interrupt when the pipe is disabled.
 855  *
 856  * On Gen4 and above:
 857  *   wait for the pipe register state bit to turn off
 858  *
 859  * Otherwise:
 860  *   wait for the display line value to settle (it usually
 861  *   ends up stopping at the start of the next frame).
 862  *
 863  */
 864 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 865 {
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867
 868         if (INTEL_INFO(dev)->gen >= 4) {
 869                 int reg = PIPECONF(pipe);
 870
 871                 /* Wait for the Pipe State to go off */
 872                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 873                              100))
 874                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 875         } else {
 876                 u32 last_line;
 877                 int reg = PIPEDSL(pipe);
 878                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 879
 880                 /* Wait for the display line to settle */
 881                 do {
 882                         last_line = I915_READ(reg) & DSL_LINEMASK;
 883                         mdelay(5);
 884                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 885                          time_after(timeout, jiffies));
 886                 if (time_after(jiffies, timeout))
 887                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 888         }
 889 }
 890
 891 static const char *state_string(bool enabled)
 892 {
 893         return enabled ? "on" : "off";
 894 }
 895
 896 /* Only for pre-ILK configs */
 897 static void assert_pll(struct drm_i915_private *dev_priv,
 898                        enum pipe pipe, bool state)
 899 {
 900         int reg;
 901         u32 val;
 902         bool cur_state;
 903
 904         reg = DPLL(pipe);
 905         val = I915_READ(reg);
 906         cur_state = !!(val & DPLL_VCO_ENABLE);
 907         WARN(cur_state != state,
 908              "PLL state assertion failure (expected %s, current %s)\n",
 909              state_string(state), state_string(cur_state));
 910 }
 911 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 912 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 913
 914 /* For ILK+ */
 915 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 916                            enum pipe pipe, bool state)
 917 {
 918         int reg;
 919         u32 val;
 920         bool cur_state;
 921
 922         if (HAS_PCH_CPT(dev_priv->dev)) {
 923                 u32 pch_dpll;
 924
 925                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 926
 927                 /* Make sure the selected PLL is enabled to the transcoder */
 928                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 929                      "transcoder %d PLL not enabled\n", pipe);
 930
 931                 /* Convert the transcoder pipe number to a pll pipe number */
 932                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 933         }
 934
 935         reg = PCH_DPLL(pipe);
 936         val = I915_READ(reg);
 937         cur_state = !!(val & DPLL_VCO_ENABLE);
 938         WARN(cur_state != state,
 939              "PCH PLL state assertion failure (expected %s, current %s)\n",
 940              state_string(state), state_string(cur_state));
 941 }
 942 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 943 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 944
 945 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 946                           enum pipe pipe, bool state)
 947 {
 948         int reg;
 949         u32 val;
 950         bool cur_state;
 951
 952         reg = FDI_TX_CTL(pipe);
 953         val = I915_READ(reg);
 954         cur_state = !!(val & FDI_TX_ENABLE);
 955         WARN(cur_state != state,
 956              "FDI TX state assertion failure (expected %s, current %s)\n",
 957              state_string(state), state_string(cur_state));
 958 }
 959 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 960 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 961
 962 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 963                           enum pipe pipe, bool state)
 964 {
 965         int reg;
 966         u32 val;
 967         bool cur_state;
 968
 969         reg = FDI_RX_CTL(pipe);
 970         val = I915_READ(reg);
 971         cur_state = !!(val & FDI_RX_ENABLE);
 972         WARN(cur_state != state,
 973              "FDI RX state assertion failure (expected %s, current %s)\n",
 974              state_string(state), state_string(cur_state));
 975 }
 976 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 977 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 978
 979 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 980                                       enum pipe pipe)
 981 {
 982         int reg;
 983         u32 val;
 984
 985         /* ILK FDI PLL is always enabled */
 986         if (dev_priv->info->gen == 5)
 987                 return;
 988
 989         reg = FDI_TX_CTL(pipe);
 990         val = I915_READ(reg);
 991         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 992 }
 993
 994 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 995                                       enum pipe pipe)
 996 {
 997         int reg;
 998         u32 val;
 999
1000         reg = FDI_RX_CTL(pipe);
1001         val = I915_READ(reg);
1002         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1003 }
1004
1005 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1006                                   enum pipe pipe)
1007 {
1008         int pp_reg, lvds_reg;
1009         u32 val;
1010         enum pipe panel_pipe = PIPE_A;
1011         bool locked = true;
1012
1013         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1014                 pp_reg = PCH_PP_CONTROL;
1015                 lvds_reg = PCH_LVDS;
1016         } else {
1017                 pp_reg = PP_CONTROL;
1018                 lvds_reg = LVDS;
1019         }
1020
1021         val = I915_READ(pp_reg);
1022         if (!(val & PANEL_POWER_ON) ||
1023             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1024                 locked = false;
1025
1026         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1027                 panel_pipe = PIPE_B;
1028
1029         WARN(panel_pipe == pipe && locked,
1030              "panel assertion failure, pipe %c regs locked\n",
1031              pipe_name(pipe));
1032 }
1033
1034 void assert_pipe(struct drm_i915_private *dev_priv,
1035                  enum pipe pipe, bool state)
1036 {
1037         int reg;
1038         u32 val;
1039         bool cur_state;
1040
1041         /* if we need the pipe A quirk it must be always on */
1042         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1043                 state = true;
1044
1045         reg = PIPECONF(pipe);
1046         val = I915_READ(reg);
1047         cur_state = !!(val & PIPECONF_ENABLE);
1048         WARN(cur_state != state,
1049              "pipe %c assertion failure (expected %s, current %s)\n",
1050              pipe_name(pipe), state_string(state), state_string(cur_state));
1051 }
1052
1053 static void assert_plane(struct drm_i915_private *dev_priv,
1054                          enum plane plane, bool state)
1055 {
1056         int reg;
1057         u32 val;
1058         bool cur_state;
1059
1060         reg = DSPCNTR(plane);
1061         val = I915_READ(reg);
1062         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1063         WARN(cur_state != state,
1064              "plane %c assertion failure (expected %s, current %s)\n",
1065              plane_name(plane), state_string(state), state_string(cur_state));
1066 }
1067
1068 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1069 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1070
1071 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1072                                    enum pipe pipe)
1073 {
1074         int reg, i;
1075         u32 val;
1076         int cur_pipe;
1077
1078         /* Planes are fixed to pipes on ILK+ */
1079         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080                 reg = DSPCNTR(pipe);
1081                 val = I915_READ(reg);
1082                 WARN((val & DISPLAY_PLANE_ENABLE),
1083                      "plane %c assertion failure, should be disabled but not\n",
1084                      plane_name(pipe));
1085                 return;
1086         }
1087
1088         /* Need to check both planes against the pipe */
1089         for (i = 0; i < 2; i++) {
1090                 reg = DSPCNTR(i);
1091                 val = I915_READ(reg);
1092                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1093                         DISPPLANE_SEL_PIPE_SHIFT;
1094                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1095                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1096                      plane_name(i), pipe_name(pipe));
1097         }
1098 }
1099
1100 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1101 {
1102         u32 val;
1103         bool enabled;
1104
1105         val = I915_READ(PCH_DREF_CONTROL);
1106         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1107                             DREF_SUPERSPREAD_SOURCE_MASK));
1108         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1109 }
1110
1111 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1112                                        enum pipe pipe)
1113 {
1114         int reg;
1115         u32 val;
1116         bool enabled;
1117
1118         reg = TRANSCONF(pipe);
1119         val = I915_READ(reg);
1120         enabled = !!(val & TRANS_ENABLE);
1121         WARN(enabled,
1122              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1123              pipe_name(pipe));
1124 }
1125
1126 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1127                             enum pipe pipe, u32 port_sel, u32 val)
1128 {
1129         if ((val & DP_PORT_EN) == 0)
1130                 return false;
1131
1132         if (HAS_PCH_CPT(dev_priv->dev)) {
1133                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1134                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1135                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1136                         return false;
1137         } else {
1138                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1139                         return false;
1140         }
1141         return true;
1142 }
1143
1144 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1145                               enum pipe pipe, u32 val)
1146 {
1147         if ((val & PORT_ENABLE) == 0)
1148                 return false;
1149
1150         if (HAS_PCH_CPT(dev_priv->dev)) {
1151                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1152                         return false;
1153         } else {
1154                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1155                         return false;
1156         }
1157         return true;
1158 }
1159
1160 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1161                               enum pipe pipe, u32 val)
1162 {
1163         if ((val & LVDS_PORT_EN) == 0)
1164                 return false;
1165
1166         if (HAS_PCH_CPT(dev_priv->dev)) {
1167                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1168                         return false;
1169         } else {
1170                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1171                         return false;
1172         }
1173         return true;
1174 }
1175
1176 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1177                               enum pipe pipe, u32 val)
1178 {
1179         if ((val & ADPA_DAC_ENABLE) == 0)
1180                 return false;
1181         if (HAS_PCH_CPT(dev_priv->dev)) {
1182                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1183                         return false;
1184         } else {
1185                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1186                         return false;
1187         }
1188         return true;
1189 }
1190
1191 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1192                                    enum pipe pipe, int reg, u32 port_sel)
1193 {
1194         u32 val = I915_READ(reg);
1195         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1196              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1197              reg, pipe_name(pipe));
1198 }
1199
1200 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1201                                      enum pipe pipe, int reg)
1202 {
1203         u32 val = I915_READ(reg);
1204         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1205              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1206              reg, pipe_name(pipe));
1207 }
1208
1209 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1210                                       enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214
1215         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1216         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1217         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1218
1219         reg = PCH_ADPA;
1220         val = I915_READ(reg);
1221         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1222              "PCH VGA enabled on transcoder %c, should be disabled\n",
1223              pipe_name(pipe));
1224
1225         reg = PCH_LVDS;
1226         val = I915_READ(reg);
1227         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1228              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1229              pipe_name(pipe));
1230
1231         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1232         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1233         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1234 }
1235
1236 /**
1237  * intel_enable_pll - enable a PLL
1238  * @dev_priv: i915 private structure
1239  * @pipe: pipe PLL to enable
1240  *
1241  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1242  * make sure the PLL reg is writable first though, since the panel write
1243  * protect mechanism may be enabled.
1244  *
1245  * Note!  This is for pre-ILK only.
1246  */
1247 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1248 {
1249         int reg;
1250         u32 val;
1251
1252         /* No really, not for ILK+ */
1253         BUG_ON(dev_priv->info->gen >= 5);
1254
1255         /* PLL is protected by panel, make sure we can write it */
1256         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1257                 assert_panel_unlocked(dev_priv, pipe);
1258
1259         reg = DPLL(pipe);
1260         val = I915_READ(reg);
1261         val |= DPLL_VCO_ENABLE;
1262
1263         /* We do this three times for luck */
1264         I915_WRITE(reg, val);
1265         POSTING_READ(reg);
1266         udelay(150); /* wait for warmup */
1267         I915_WRITE(reg, val);
1268         POSTING_READ(reg);
1269         udelay(150); /* wait for warmup */
1270         I915_WRITE(reg, val);
1271         POSTING_READ(reg);
1272         udelay(150); /* wait for warmup */
1273 }
1274
1275 /**
1276  * intel_disable_pll - disable a PLL
1277  * @dev_priv: i915 private structure
1278  * @pipe: pipe PLL to disable
1279  *
1280  * Disable the PLL for @pipe, making sure the pipe is off first.
1281  *
1282  * Note!  This is for pre-ILK only.
1283  */
1284 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1285 {
1286         int reg;
1287         u32 val;
1288
1289         /* Don't disable pipe A or pipe A PLLs if needed */
1290         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1291                 return;
1292
1293         /* Make sure the pipe isn't still relying on us */
1294         assert_pipe_disabled(dev_priv, pipe);
1295
1296         reg = DPLL(pipe);
1297         val = I915_READ(reg);
1298         val &= ~DPLL_VCO_ENABLE;
1299         I915_WRITE(reg, val);
1300         POSTING_READ(reg);
1301 }
1302
1303 /**
1304  * intel_enable_pch_pll - enable PCH PLL
1305  * @dev_priv: i915 private structure
1306  * @pipe: pipe PLL to enable
1307  *
1308  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1309  * drives the transcoder clock.
1310  */
1311 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1312                                  enum pipe pipe)
1313 {
1314         int reg;
1315         u32 val;
1316
1317         if (pipe > 1)
1318                 return;
1319
1320         /* PCH only available on ILK+ */
1321         BUG_ON(dev_priv->info->gen < 5);
1322
1323         /* PCH refclock must be enabled first */
1324         assert_pch_refclk_enabled(dev_priv);
1325
1326         reg = PCH_DPLL(pipe);
1327         val = I915_READ(reg);
1328         val |= DPLL_VCO_ENABLE;
1329         I915_WRITE(reg, val);
1330         POSTING_READ(reg);
1331         udelay(200);
1332 }
1333
1334 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1335                                   enum pipe pipe)
1336 {
1337         int reg;
1338         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1339                 pll_sel = TRANSC_DPLL_ENABLE;
1340
1341         if (pipe > 1)
1342                 return;
1343
1344         /* PCH only available on ILK+ */
1345         BUG_ON(dev_priv->info->gen < 5);
1346
1347         /* Make sure transcoder isn't still depending on us */
1348         assert_transcoder_disabled(dev_priv, pipe);
1349
1350         if (pipe == 0)
1351                 pll_sel |= TRANSC_DPLLA_SEL;
1352         else if (pipe == 1)
1353                 pll_sel |= TRANSC_DPLLB_SEL;
1354
1355
1356         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1357                 return;
1358
1359         reg = PCH_DPLL(pipe);
1360         val = I915_READ(reg);
1361         val &= ~DPLL_VCO_ENABLE;
1362         I915_WRITE(reg, val);
1363         POSTING_READ(reg);
1364         udelay(200);
1365 }
1366
1367 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1368                                     enum pipe pipe)
1369 {
1370         int reg;
1371         u32 val, pipeconf_val;
1372         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1373
1374         /* PCH only available on ILK+ */
1375         BUG_ON(dev_priv->info->gen < 5);
1376
1377         /* Make sure PCH DPLL is enabled */
1378         assert_pch_pll_enabled(dev_priv, pipe);
1379
1380         /* FDI must be feeding us bits for PCH ports */
1381         assert_fdi_tx_enabled(dev_priv, pipe);
1382         assert_fdi_rx_enabled(dev_priv, pipe);
1383
1384         reg = TRANSCONF(pipe);
1385         val = I915_READ(reg);
1386         pipeconf_val = I915_READ(PIPECONF(pipe));
1387
1388         if (HAS_PCH_IBX(dev_priv->dev)) {
1389                 /*
1390                  * make the BPC in transcoder be consistent with
1391                  * that in pipeconf reg.
1392                  */
1393                 val &= ~PIPE_BPC_MASK;
1394                 val |= pipeconf_val & PIPE_BPC_MASK;
1395         }
1396
1397         val &= ~TRANS_INTERLACE_MASK;
1398         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1399                 if (HAS_PCH_IBX(dev_priv->dev) &&
1400                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1401                         val |= TRANS_LEGACY_INTERLACED_ILK;
1402                 else
1403                         val |= TRANS_INTERLACED;
1404         else
1405                 val |= TRANS_PROGRESSIVE;
1406
1407         I915_WRITE(reg, val | TRANS_ENABLE);
1408         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1409                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1410 }
1411
1412 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1413                                      enum pipe pipe)
1414 {
1415         int reg;
1416         u32 val;
1417
1418         /* FDI relies on the transcoder */
1419         assert_fdi_tx_disabled(dev_priv, pipe);
1420         assert_fdi_rx_disabled(dev_priv, pipe);
1421
1422         /* Ports must be off as well */
1423         assert_pch_ports_disabled(dev_priv, pipe);
1424
1425         reg = TRANSCONF(pipe);
1426         val = I915_READ(reg);
1427         val &= ~TRANS_ENABLE;
1428         I915_WRITE(reg, val);
1429         /* wait for PCH transcoder off, transcoder state */
1430         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1431                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1432 }
1433
1434 /**
1435  * intel_enable_pipe - enable a pipe, asserting requirements
1436  * @dev_priv: i915 private structure
1437  * @pipe: pipe to enable
1438  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1439  *
1440  * Enable @pipe, making sure that various hardware specific requirements
1441  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1442  *
1443  * @pipe should be %PIPE_A or %PIPE_B.
1444  *
1445  * Will wait until the pipe is actually running (i.e. first vblank) before
1446  * returning.
1447  */
1448 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1449                               bool pch_port)
1450 {
1451         int reg;
1452         u32 val;
1453
1454         /*
1455          * A pipe without a PLL won't actually be able to drive bits from
1456          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1457          * need the check.
1458          */
1459         if (!HAS_PCH_SPLIT(dev_priv->dev))
1460                 assert_pll_enabled(dev_priv, pipe);
1461         else {
1462                 if (pch_port) {
1463                         /* if driving the PCH, we need FDI enabled */
1464                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1465                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1466                 }
1467                 /* FIXME: assert CPU port conditions for SNB+ */
1468         }
1469
1470         reg = PIPECONF(pipe);
1471         val = I915_READ(reg);
1472         if (val & PIPECONF_ENABLE)
1473                 return;
1474
1475         I915_WRITE(reg, val | PIPECONF_ENABLE);
1476         intel_wait_for_vblank(dev_priv->dev, pipe);
1477 }
1478
1479 /**
1480  * intel_disable_pipe - disable a pipe, asserting requirements
1481  * @dev_priv: i915 private structure
1482  * @pipe: pipe to disable
1483  *
1484  * Disable @pipe, making sure that various hardware specific requirements
1485  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1486  *
1487  * @pipe should be %PIPE_A or %PIPE_B.
1488  *
1489  * Will wait until the pipe has shut down before returning.
1490  */
1491 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1492                                enum pipe pipe)
1493 {
1494         int reg;
1495         u32 val;
1496
1497         /*
1498          * Make sure planes won't keep trying to pump pixels to us,
1499          * or we might hang the display.
1500          */
1501         assert_planes_disabled(dev_priv, pipe);
1502
1503         /* Don't disable pipe A or pipe A PLLs if needed */
1504         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1505                 return;
1506
1507         reg = PIPECONF(pipe);
1508         val = I915_READ(reg);
1509         if ((val & PIPECONF_ENABLE) == 0)
1510                 return;
1511
1512         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1513         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1514 }
1515
1516 /*
1517  * Plane regs are double buffered, going from enabled->disabled needs a
1518  * trigger in order to latch.  The display address reg provides this.
1519  */
1520 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1521                                       enum plane plane)
1522 {
1523         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1524         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1525 }
1526
1527 /**
1528  * intel_enable_plane - enable a display plane on a given pipe
1529  * @dev_priv: i915 private structure
1530  * @plane: plane to enable
1531  * @pipe: pipe being fed
1532  *
1533  * Enable @plane on @pipe, making sure that @pipe is running first.
1534  */
1535 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1536                                enum plane plane, enum pipe pipe)
1537 {
1538         int reg;
1539         u32 val;
1540
1541         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1542         assert_pipe_enabled(dev_priv, pipe);
1543
1544         reg = DSPCNTR(plane);
1545         val = I915_READ(reg);
1546         if (val & DISPLAY_PLANE_ENABLE)
1547                 return;
1548
1549         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1550         intel_flush_display_plane(dev_priv, plane);
1551         intel_wait_for_vblank(dev_priv->dev, pipe);
1552 }
1553
1554 /**
1555  * intel_disable_plane - disable a display plane
1556  * @dev_priv: i915 private structure
1557  * @plane: plane to disable
1558  * @pipe: pipe consuming the data
1559  *
1560  * Disable @plane; should be an independent operation.
1561  */
1562 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1563                                 enum plane plane, enum pipe pipe)
1564 {
1565         int reg;
1566         u32 val;
1567
1568         reg = DSPCNTR(plane);
1569         val = I915_READ(reg);
1570         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1571                 return;
1572
1573         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1574         intel_flush_display_plane(dev_priv, plane);
1575         intel_wait_for_vblank(dev_priv->dev, pipe);
1576 }
1577
1578 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1579                            enum pipe pipe, int reg, u32 port_sel)
1580 {
1581         u32 val = I915_READ(reg);
1582         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1583                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1584                 I915_WRITE(reg, val & ~DP_PORT_EN);
1585         }
1586 }
1587
1588 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1589                              enum pipe pipe, int reg)
1590 {
1591         u32 val = I915_READ(reg);
1592         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1593                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1594                               reg, pipe);
1595                 I915_WRITE(reg, val & ~PORT_ENABLE);
1596         }
1597 }
1598
1599 /* Disable any ports connected to this transcoder */
1600 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1601                                     enum pipe pipe)
1602 {
1603         u32 reg, val;
1604
1605         val = I915_READ(PCH_PP_CONTROL);
1606         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1607
1608         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1609         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1610         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1611
1612         reg = PCH_ADPA;
1613         val = I915_READ(reg);
1614         if (adpa_pipe_enabled(dev_priv, val, pipe))
1615                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1616
1617         reg = PCH_LVDS;
1618         val = I915_READ(reg);
1619         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1620                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1621                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1622                 POSTING_READ(reg);
1623                 udelay(100);
1624         }
1625
1626         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1627         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1628         disable_pch_hdmi(dev_priv, pipe, HDMID);
1629 }
1630
1631 static void i8xx_disable_fbc(struct drm_device *dev)
1632 {
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634         u32 fbc_ctl;
1635
1636         /* Disable compression */
1637         fbc_ctl = I915_READ(FBC_CONTROL);
1638         if ((fbc_ctl & FBC_CTL_EN) == 0)
1639                 return;
1640
1641         fbc_ctl &= ~FBC_CTL_EN;
1642         I915_WRITE(FBC_CONTROL, fbc_ctl);
1643
1644         /* Wait for compressing bit to clear */
1645         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1646                 DRM_DEBUG_KMS("FBC idle timed out\n");
1647                 return;
1648         }
1649
1650         DRM_DEBUG_KMS("disabled FBC\n");
1651 }
1652
1653 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1654 {
1655         struct drm_device *dev = crtc->dev;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         struct drm_framebuffer *fb = crtc->fb;
1658         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1659         struct drm_i915_gem_object *obj = intel_fb->obj;
1660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1661         int cfb_pitch;
1662         int plane, i;
1663         u32 fbc_ctl, fbc_ctl2;
1664
1665         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1666         if (fb->pitches[0] < cfb_pitch)
1667                 cfb_pitch = fb->pitches[0];
1668
1669         /* FBC_CTL wants 64B units */
1670         cfb_pitch = (cfb_pitch / 64) - 1;
1671         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1672
1673         /* Clear old tags */
1674         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1675                 I915_WRITE(FBC_TAG + (i * 4), 0);
1676
1677         /* Set it up... */
1678         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1679         fbc_ctl2 |= plane;
1680         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1681         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1682
1683         /* enable it... */
1684         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1685         if (IS_I945GM(dev))
1686                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1687         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1688         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1689         fbc_ctl |= obj->fence_reg;
1690         I915_WRITE(FBC_CONTROL, fbc_ctl);
1691
1692         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1693                       cfb_pitch, crtc->y, intel_crtc->plane);
1694 }
1695
1696 static bool i8xx_fbc_enabled(struct drm_device *dev)
1697 {
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699
1700         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1701 }
1702
1703 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1704 {
1705         struct drm_device *dev = crtc->dev;
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707         struct drm_framebuffer *fb = crtc->fb;
1708         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1709         struct drm_i915_gem_object *obj = intel_fb->obj;
1710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1711         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1712         unsigned long stall_watermark = 200;
1713         u32 dpfc_ctl;
1714
1715         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1716         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1717         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1718
1719         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1720                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1721                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1722         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1723
1724         /* enable it... */
1725         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1726
1727         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1728 }
1729
1730 static void g4x_disable_fbc(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         u32 dpfc_ctl;
1734
1735         /* Disable compression */
1736         dpfc_ctl = I915_READ(DPFC_CONTROL);
1737         if (dpfc_ctl & DPFC_CTL_EN) {
1738                 dpfc_ctl &= ~DPFC_CTL_EN;
1739                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1740
1741                 DRM_DEBUG_KMS("disabled FBC\n");
1742         }
1743 }
1744
1745 static bool g4x_fbc_enabled(struct drm_device *dev)
1746 {
1747         struct drm_i915_private *dev_priv = dev->dev_private;
1748
1749         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1750 }
1751
1752 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1753 {
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         u32 blt_ecoskpd;
1756
1757         /* Make sure blitter notifies FBC of writes */
1758         gen6_gt_force_wake_get(dev_priv);
1759         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1760         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1761                 GEN6_BLITTER_LOCK_SHIFT;
1762         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1763         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1764         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1765         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1766                          GEN6_BLITTER_LOCK_SHIFT);
1767         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1768         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1769         gen6_gt_force_wake_put(dev_priv);
1770 }
1771
1772 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1773 {
1774         struct drm_device *dev = crtc->dev;
1775         struct drm_i915_private *dev_priv = dev->dev_private;
1776         struct drm_framebuffer *fb = crtc->fb;
1777         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1778         struct drm_i915_gem_object *obj = intel_fb->obj;
1779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1781         unsigned long stall_watermark = 200;
1782         u32 dpfc_ctl;
1783
1784         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1785         dpfc_ctl &= DPFC_RESERVED;
1786         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1787         /* Set persistent mode for front-buffer rendering, ala X. */
1788         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1789         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1790         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1791
1792         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1793                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1794                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1795         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1796         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1797         /* enable it... */
1798         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1799
1800         if (IS_GEN6(dev)) {
1801                 I915_WRITE(SNB_DPFC_CTL_SA,
1802                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1803                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1804                 sandybridge_blit_fbc_update(dev);
1805         }
1806
1807         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1808 }
1809
1810 static void ironlake_disable_fbc(struct drm_device *dev)
1811 {
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         u32 dpfc_ctl;
1814
1815         /* Disable compression */
1816         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1817         if (dpfc_ctl & DPFC_CTL_EN) {
1818                 dpfc_ctl &= ~DPFC_CTL_EN;
1819                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1820
1821                 DRM_DEBUG_KMS("disabled FBC\n");
1822         }
1823 }
1824
1825 static bool ironlake_fbc_enabled(struct drm_device *dev)
1826 {
1827         struct drm_i915_private *dev_priv = dev->dev_private;
1828
1829         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1830 }
1831
1832 bool intel_fbc_enabled(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836         if (!dev_priv->display.fbc_enabled)
1837                 return false;
1838
1839         return dev_priv->display.fbc_enabled(dev);
1840 }
1841
1842 static void intel_fbc_work_fn(struct work_struct *__work)
1843 {
1844         struct intel_fbc_work *work =
1845                 container_of(to_delayed_work(__work),
1846                              struct intel_fbc_work, work);
1847         struct drm_device *dev = work->crtc->dev;
1848         struct drm_i915_private *dev_priv = dev->dev_private;
1849
1850         mutex_lock(&dev->struct_mutex);
1851         if (work == dev_priv->fbc_work) {
1852                 /* Double check that we haven't switched fb without cancelling
1853                  * the prior work.
1854                  */
1855                 if (work->crtc->fb == work->fb) {
1856                         dev_priv->display.enable_fbc(work->crtc,
1857                                                      work->interval);
1858
1859                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1860                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1861                         dev_priv->cfb_y = work->crtc->y;
1862                 }
1863
1864                 dev_priv->fbc_work = NULL;
1865         }
1866         mutex_unlock(&dev->struct_mutex);
1867
1868         kfree(work);
1869 }
1870
1871 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1872 {
1873         if (dev_priv->fbc_work == NULL)
1874                 return;
1875
1876         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1877
1878         /* Synchronisation is provided by struct_mutex and checking of
1879          * dev_priv->fbc_work, so we can perform the cancellation
1880          * entirely asynchronously.
1881          */
1882         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1883                 /* tasklet was killed before being run, clean up */
1884                 kfree(dev_priv->fbc_work);
1885
1886         /* Mark the work as no longer wanted so that if it does
1887          * wake-up (because the work was already running and waiting
1888          * for our mutex), it will discover that is no longer
1889          * necessary to run.
1890          */
1891         dev_priv->fbc_work = NULL;
1892 }
1893
1894 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1895 {
1896         struct intel_fbc_work *work;
1897         struct drm_device *dev = crtc->dev;
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899
1900         if (!dev_priv->display.enable_fbc)
1901                 return;
1902
1903         intel_cancel_fbc_work(dev_priv);
1904
1905         work = kzalloc(sizeof *work, GFP_KERNEL);
1906         if (work == NULL) {
1907                 dev_priv->display.enable_fbc(crtc, interval);
1908                 return;
1909         }
1910
1911         work->crtc = crtc;
1912         work->fb = crtc->fb;
1913         work->interval = interval;
1914         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1915
1916         dev_priv->fbc_work = work;
1917
1918         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1919
1920         /* Delay the actual enabling to let pageflipping cease and the
1921          * display to settle before starting the compression. Note that
1922          * this delay also serves a second purpose: it allows for a
1923          * vblank to pass after disabling the FBC before we attempt
1924          * to modify the control registers.
1925          *
1926          * A more complicated solution would involve tracking vblanks
1927          * following the termination of the page-flipping sequence
1928          * and indeed performing the enable as a co-routine and not
1929          * waiting synchronously upon the vblank.
1930          */
1931         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1932 }
1933
1934 void intel_disable_fbc(struct drm_device *dev)
1935 {
1936         struct drm_i915_private *dev_priv = dev->dev_private;
1937
1938         intel_cancel_fbc_work(dev_priv);
1939
1940         if (!dev_priv->display.disable_fbc)
1941                 return;
1942
1943         dev_priv->display.disable_fbc(dev);
1944         dev_priv->cfb_plane = -1;
1945 }
1946
1947 /**
1948  * intel_update_fbc - enable/disable FBC as needed
1949  * @dev: the drm_device
1950  *
1951  * Set up the framebuffer compression hardware at mode set time.  We
1952  * enable it if possible:
1953  *   - plane A only (on pre-965)
1954  *   - no pixel mulitply/line duplication
1955  *   - no alpha buffer discard
1956  *   - no dual wide
1957  *   - framebuffer <= 2048 in width, 1536 in height
1958  *
1959  * We can't assume that any compression will take place (worst case),
1960  * so the compressed buffer has to be the same size as the uncompressed
1961  * one.  It also must reside (along with the line length buffer) in
1962  * stolen memory.
1963  *
1964  * We need to enable/disable FBC on a global basis.
1965  */
1966 static void intel_update_fbc(struct drm_device *dev)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         struct drm_crtc *crtc = NULL, *tmp_crtc;
1970         struct intel_crtc *intel_crtc;
1971         struct drm_framebuffer *fb;
1972         struct intel_framebuffer *intel_fb;
1973         struct drm_i915_gem_object *obj;
1974         int enable_fbc;
1975
1976         DRM_DEBUG_KMS("\n");
1977
1978         if (!i915_powersave)
1979                 return;
1980
1981         if (!I915_HAS_FBC(dev))
1982                 return;
1983
1984         /*
1985          * If FBC is already on, we just have to verify that we can
1986          * keep it that way...
1987          * Need to disable if:
1988          *   - more than one pipe is active
1989          *   - changing FBC params (stride, fence, mode)
1990          *   - new fb is too large to fit in compressed buffer
1991          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1992          */
1993         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1994                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1995                         if (crtc) {
1996                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1997                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1998                                 goto out_disable;
1999                         }
2000                         crtc = tmp_crtc;
2001                 }
2002         }
2003
2004         if (!crtc || crtc->fb == NULL) {
2005                 DRM_DEBUG_KMS("no output, disabling\n");
2006                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2007                 goto out_disable;
2008         }
2009
2010         intel_crtc = to_intel_crtc(crtc);
2011         fb = crtc->fb;
2012         intel_fb = to_intel_framebuffer(fb);
2013         obj = intel_fb->obj;
2014
2015         enable_fbc = i915_enable_fbc;
2016         if (enable_fbc < 0) {
2017                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
2018                 enable_fbc = 1;
2019                 if (INTEL_INFO(dev)->gen <= 6)
2020                         enable_fbc = 0;
2021         }
2022         if (!enable_fbc) {
2023                 DRM_DEBUG_KMS("fbc disabled per module param\n");
2024                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
2025                 goto out_disable;
2026         }
2027         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2028                 DRM_DEBUG_KMS("framebuffer too large, disabling "
2029                               "compression\n");
2030                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2031                 goto out_disable;
2032         }
2033         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2034             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2035                 DRM_DEBUG_KMS("mode incompatible with compression, "
2036                               "disabling\n");
2037                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2038                 goto out_disable;
2039         }
2040         if ((crtc->mode.hdisplay > 2048) ||
2041             (crtc->mode.vdisplay > 1536)) {
2042                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2043                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2044                 goto out_disable;
2045         }
2046         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
2047                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2048                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2049                 goto out_disable;
2050         }
2051
2052         /* The use of a CPU fence is mandatory in order to detect writes
2053          * by the CPU to the scanout and trigger updates to the FBC.
2054          */
2055         if (obj->tiling_mode != I915_TILING_X ||
2056             obj->fence_reg == I915_FENCE_REG_NONE) {
2057                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
2058                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
2059                 goto out_disable;
2060         }
2061
2062         /* If the kernel debugger is active, always disable compression */
2063         if (in_dbg_master())
2064                 goto out_disable;
2065
2066         /* If the scanout has not changed, don't modify the FBC settings.
2067          * Note that we make the fundamental assumption that the fb->obj
2068          * cannot be unpinned (and have its GTT offset and fence revoked)
2069          * without first being decoupled from the scanout and FBC disabled.
2070          */
2071         if (dev_priv->cfb_plane == intel_crtc->plane &&
2072             dev_priv->cfb_fb == fb->base.id &&
2073             dev_priv->cfb_y == crtc->y)
2074                 return;
2075
2076         if (intel_fbc_enabled(dev)) {
2077                 /* We update FBC along two paths, after changing fb/crtc
2078                  * configuration (modeswitching) and after page-flipping
2079                  * finishes. For the latter, we know that not only did
2080                  * we disable the FBC at the start of the page-flip
2081                  * sequence, but also more than one vblank has passed.
2082                  *
2083                  * For the former case of modeswitching, it is possible
2084                  * to switch between two FBC valid configurations
2085                  * instantaneously so we do need to disable the FBC
2086                  * before we can modify its control registers. We also
2087                  * have to wait for the next vblank for that to take
2088                  * effect. However, since we delay enabling FBC we can
2089                  * assume that a vblank has passed since disabling and
2090                  * that we can safely alter the registers in the deferred
2091                  * callback.
2092                  *
2093                  * In the scenario that we go from a valid to invalid
2094                  * and then back to valid FBC configuration we have
2095                  * no strict enforcement that a vblank occurred since
2096                  * disabling the FBC. However, along all current pipe
2097                  * disabling paths we do need to wait for a vblank at
2098                  * some point. And we wait before enabling FBC anyway.
2099                  */
2100                 DRM_DEBUG_KMS("disabling active FBC for update\n");
2101                 intel_disable_fbc(dev);
2102         }
2103
2104         intel_enable_fbc(crtc, 500);
2105         return;
2106
2107 out_disable:
2108         /* Multiple disables should be harmless */
2109         if (intel_fbc_enabled(dev)) {
2110                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2111                 intel_disable_fbc(dev);
2112         }
2113 }
2114
2115 int
2116 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2117                            struct drm_i915_gem_object *obj,
2118                            struct intel_ring_buffer *pipelined)
2119 {
2120         struct drm_i915_private *dev_priv = dev->dev_private;
2121         u32 alignment;
2122         int ret;
2123
2124         switch (obj->tiling_mode) {
2125         case I915_TILING_NONE:
2126                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2127                         alignment = 128 * 1024;
2128                 else if (INTEL_INFO(dev)->gen >= 4)
2129                         alignment = 4 * 1024;
2130                 else
2131                         alignment = 64 * 1024;
2132                 break;
2133         case I915_TILING_X:
2134                 /* pin() will align the object as required by fence */
2135                 alignment = 0;
2136                 break;
2137         case I915_TILING_Y:
2138                 /* FIXME: Is this true? */
2139                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2140                 return -EINVAL;
2141         default:
2142                 BUG();
2143         }
2144
2145         dev_priv->mm.interruptible = false;
2146         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2147         if (ret)
2148                 goto err_interruptible;
2149
2150         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2151          * fence, whereas 965+ only requires a fence if using
2152          * framebuffer compression.  For simplicity, we always install
2153          * a fence as the cost is not that onerous.
2154          */
2155         ret = i915_gem_object_get_fence(obj, pipelined);
2156         if (ret)
2157                 goto err_unpin;
2158
2159         i915_gem_object_pin_fence(obj);
2160
2161         dev_priv->mm.interruptible = true;
2162         return 0;
2163
2164 err_unpin:
2165         i915_gem_object_unpin(obj);
2166 err_interruptible:
2167         dev_priv->mm.interruptible = true;
2168         return ret;
2169 }
2170
2171 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2172 {
2173         i915_gem_object_unpin_fence(obj);
2174         i915_gem_object_unpin(obj);
2175 }
2176
2177 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2178                              int x, int y)
2179 {
2180         struct drm_device *dev = crtc->dev;
2181         struct drm_i915_private *dev_priv = dev->dev_private;
2182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183         struct intel_framebuffer *intel_fb;
2184         struct drm_i915_gem_object *obj;
2185         int plane = intel_crtc->plane;
2186         unsigned long Start, Offset;
2187         u32 dspcntr;
2188         u32 reg;
2189
2190         switch (plane) {
2191         case 0:
2192         case 1:
2193                 break;
2194         default:
2195                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2196                 return -EINVAL;
2197         }
2198
2199         intel_fb = to_intel_framebuffer(fb);
2200         obj = intel_fb->obj;
2201
2202         reg = DSPCNTR(plane);
2203         dspcntr = I915_READ(reg);
2204         /* Mask out pixel format bits in case we change it */
2205         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2206         switch (fb->bits_per_pixel) {
2207         case 8:
2208                 dspcntr |= DISPPLANE_8BPP;
2209                 break;
2210         case 16:
2211                 if (fb->depth == 15)
2212                         dspcntr |= DISPPLANE_15_16BPP;
2213                 else
2214                         dspcntr |= DISPPLANE_16BPP;
2215                 break;
2216         case 24:
2217         case 32:
2218                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2219                 break;
2220         default:
2221                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2222                 return -EINVAL;
2223         }
2224         if (INTEL_INFO(dev)->gen >= 4) {
2225                 if (obj->tiling_mode != I915_TILING_NONE)
2226                         dspcntr |= DISPPLANE_TILED;
2227                 else
2228                         dspcntr &= ~DISPPLANE_TILED;
2229         }
2230
2231         I915_WRITE(reg, dspcntr);
2232
2233         Start = obj->gtt_offset;
2234         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2235
2236         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2237                       Start, Offset, x, y, fb->pitches[0]);
2238         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2239         if (INTEL_INFO(dev)->gen >= 4) {
2240                 I915_WRITE(DSPSURF(plane), Start);
2241                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2242                 I915_WRITE(DSPADDR(plane), Offset);
2243         } else
2244                 I915_WRITE(DSPADDR(plane), Start + Offset);
2245         POSTING_READ(reg);
2246
2247         return 0;
2248 }
2249
2250 static int ironlake_update_plane(struct drm_crtc *crtc,
2251                                  struct drm_framebuffer *fb, int x, int y)
2252 {
2253         struct drm_device *dev = crtc->dev;
2254         struct drm_i915_private *dev_priv = dev->dev_private;
2255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2256         struct intel_framebuffer *intel_fb;
2257         struct drm_i915_gem_object *obj;
2258         int plane = intel_crtc->plane;
2259         unsigned long Start, Offset;
2260         u32 dspcntr;
2261         u32 reg;
2262
2263         switch (plane) {
2264         case 0:
2265         case 1:
2266         case 2:
2267                 break;
2268         default:
2269                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2270                 return -EINVAL;
2271         }
2272
2273         intel_fb = to_intel_framebuffer(fb);
2274         obj = intel_fb->obj;
2275
2276         reg = DSPCNTR(plane);
2277         dspcntr = I915_READ(reg);
2278         /* Mask out pixel format bits in case we change it */
2279         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2280         switch (fb->bits_per_pixel) {
2281         case 8:
2282                 dspcntr |= DISPPLANE_8BPP;
2283                 break;
2284         case 16:
2285                 if (fb->depth != 16)
2286                         return -EINVAL;
2287
2288                 dspcntr |= DISPPLANE_16BPP;
2289                 break;
2290         case 24:
2291         case 32:
2292                 if (fb->depth == 24)
2293                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2294                 else if (fb->depth == 30)
2295                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2296                 else
2297                         return -EINVAL;
2298                 break;
2299         default:
2300                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2301                 return -EINVAL;
2302         }
2303
2304         if (obj->tiling_mode != I915_TILING_NONE)
2305                 dspcntr |= DISPPLANE_TILED;
2306         else
2307                 dspcntr &= ~DISPPLANE_TILED;
2308
2309         /* must disable */
2310         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2311
2312         I915_WRITE(reg, dspcntr);
2313
2314         Start = obj->gtt_offset;
2315         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2316
2317         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2318                       Start, Offset, x, y, fb->pitches[0]);
2319         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2320         I915_WRITE(DSPSURF(plane), Start);
2321         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2322         I915_WRITE(DSPADDR(plane), Offset);
2323         POSTING_READ(reg);
2324
2325         return 0;
2326 }
2327
2328 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2329 static int
2330 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2331                            int x, int y, enum mode_set_atomic state)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         int ret;
2336
2337         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2338         if (ret)
2339                 return ret;
2340
2341         intel_update_fbc(dev);
2342         intel_increase_pllclock(crtc);
2343
2344         return 0;
2345 }
2346
2347 static int
2348 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2349                     struct drm_framebuffer *old_fb)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_master_private *master_priv;
2353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2354         int ret;
2355
2356         /* no fb bound */
2357         if (!crtc->fb) {
2358                 DRM_ERROR("No FB bound\n");
2359                 return 0;
2360         }
2361
2362         switch (intel_crtc->plane) {
2363         case 0:
2364         case 1:
2365                 break;
2366         case 2:
2367                 if (IS_IVYBRIDGE(dev))
2368                         break;
2369                 /* fall through otherwise */
2370         default:
2371                 DRM_ERROR("no plane for crtc\n");
2372                 return -EINVAL;
2373         }
2374
2375         mutex_lock(&dev->struct_mutex);
2376         ret = intel_pin_and_fence_fb_obj(dev,
2377                                          to_intel_framebuffer(crtc->fb)->obj,
2378                                          NULL);
2379         if (ret != 0) {
2380                 mutex_unlock(&dev->struct_mutex);
2381                 DRM_ERROR("pin & fence failed\n");
2382                 return ret;
2383         }
2384
2385         if (old_fb) {
2386                 struct drm_i915_private *dev_priv = dev->dev_private;
2387                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2388
2389                 wait_event(dev_priv->pending_flip_queue,
2390                            atomic_read(&dev_priv->mm.wedged) ||
2391                            atomic_read(&obj->pending_flip) == 0);
2392
2393                 /* Big Hammer, we also need to ensure that any pending
2394                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2395                  * current scanout is retired before unpinning the old
2396                  * framebuffer.
2397                  *
2398                  * This should only fail upon a hung GPU, in which case we
2399                  * can safely continue.
2400                  */
2401                 ret = i915_gem_object_finish_gpu(obj);
2402                 (void) ret;
2403         }
2404
2405         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2406                                          LEAVE_ATOMIC_MODE_SET);
2407         if (ret) {
2408                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2409                 mutex_unlock(&dev->struct_mutex);
2410                 DRM_ERROR("failed to update base address\n");
2411                 return ret;
2412         }
2413
2414         if (old_fb) {
2415                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2416                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2417         }
2418
2419         mutex_unlock(&dev->struct_mutex);
2420
2421         if (!dev->primary->master)
2422                 return 0;
2423
2424         master_priv = dev->primary->master->driver_priv;
2425         if (!master_priv->sarea_priv)
2426                 return 0;
2427
2428         if (intel_crtc->pipe) {
2429                 master_priv->sarea_priv->pipeB_x = x;
2430                 master_priv->sarea_priv->pipeB_y = y;
2431         } else {
2432                 master_priv->sarea_priv->pipeA_x = x;
2433                 master_priv->sarea_priv->pipeA_y = y;
2434         }
2435
2436         return 0;
2437 }
2438
2439 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2440 {
2441         struct drm_device *dev = crtc->dev;
2442         struct drm_i915_private *dev_priv = dev->dev_private;
2443         u32 dpa_ctl;
2444
2445         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2446         dpa_ctl = I915_READ(DP_A);
2447         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2448
2449         if (clock < 200000) {
2450                 u32 temp;
2451                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2452                 /* workaround for 160Mhz:
2453                    1) program 0x4600c bits 15:0 = 0x8124
2454                    2) program 0x46010 bit 0 = 1
2455                    3) program 0x46034 bit 24 = 1
2456                    4) program 0x64000 bit 14 = 1
2457                    */
2458                 temp = I915_READ(0x4600c);
2459                 temp &= 0xffff0000;
2460                 I915_WRITE(0x4600c, temp | 0x8124);
2461
2462                 temp = I915_READ(0x46010);
2463                 I915_WRITE(0x46010, temp | 1);
2464
2465                 temp = I915_READ(0x46034);
2466                 I915_WRITE(0x46034, temp | (1 << 24));
2467         } else {
2468                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2469         }
2470         I915_WRITE(DP_A, dpa_ctl);
2471
2472         POSTING_READ(DP_A);
2473         udelay(500);
2474 }
2475
2476 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2477 {
2478         struct drm_device *dev = crtc->dev;
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481         int pipe = intel_crtc->pipe;
2482         u32 reg, temp;
2483
2484         /* enable normal train */
2485         reg = FDI_TX_CTL(pipe);
2486         temp = I915_READ(reg);
2487         if (IS_IVYBRIDGE(dev)) {
2488                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2489                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2490         } else {
2491                 temp &= ~FDI_LINK_TRAIN_NONE;
2492                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2493         }
2494         I915_WRITE(reg, temp);
2495
2496         reg = FDI_RX_CTL(pipe);
2497         temp = I915_READ(reg);
2498         if (HAS_PCH_CPT(dev)) {
2499                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2501         } else {
2502                 temp &= ~FDI_LINK_TRAIN_NONE;
2503                 temp |= FDI_LINK_TRAIN_NONE;
2504         }
2505         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2506
2507         /* wait one idle pattern time */
2508         POSTING_READ(reg);
2509         udelay(1000);
2510
2511         /* IVB wants error correction enabled */
2512         if (IS_IVYBRIDGE(dev))
2513                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2514                            FDI_FE_ERRC_ENABLE);
2515 }
2516
2517 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2518 {
2519         struct drm_i915_private *dev_priv = dev->dev_private;
2520         u32 flags = I915_READ(SOUTH_CHICKEN1);
2521
2522         flags |= FDI_PHASE_SYNC_OVR(pipe);
2523         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2524         flags |= FDI_PHASE_SYNC_EN(pipe);
2525         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2526         POSTING_READ(SOUTH_CHICKEN1);
2527 }
2528
2529 /* The FDI link training functions for ILK/Ibexpeak. */
2530 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2531 {
2532         struct drm_device *dev = crtc->dev;
2533         struct drm_i915_private *dev_priv = dev->dev_private;
2534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2535         int pipe = intel_crtc->pipe;
2536         int plane = intel_crtc->plane;
2537         u32 reg, temp, tries;
2538
2539         /* FDI needs bits from pipe & plane first */
2540         assert_pipe_enabled(dev_priv, pipe);
2541         assert_plane_enabled(dev_priv, plane);
2542
2543         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2544            for train result */
2545         reg = FDI_RX_IMR(pipe);
2546         temp = I915_READ(reg);
2547         temp &= ~FDI_RX_SYMBOL_LOCK;
2548         temp &= ~FDI_RX_BIT_LOCK;
2549         I915_WRITE(reg, temp);
2550         I915_READ(reg);
2551         udelay(150);
2552
2553         /* enable CPU FDI TX and PCH FDI RX */
2554         reg = FDI_TX_CTL(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~(7 << 19);
2557         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_1;
2560         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2561
2562         reg = FDI_RX_CTL(pipe);
2563         temp = I915_READ(reg);
2564         temp &= ~FDI_LINK_TRAIN_NONE;
2565         temp |= FDI_LINK_TRAIN_PATTERN_1;
2566         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2567
2568         POSTING_READ(reg);
2569         udelay(150);
2570
2571         /* Ironlake workaround, enable clock pointer after FDI enable*/
2572         if (HAS_PCH_IBX(dev)) {
2573                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2574                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2575                            FDI_RX_PHASE_SYNC_POINTER_EN);
2576         }
2577
2578         reg = FDI_RX_IIR(pipe);
2579         for (tries = 0; tries < 5; tries++) {
2580                 temp = I915_READ(reg);
2581                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582
2583                 if ((temp & FDI_RX_BIT_LOCK)) {
2584                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2585                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2586                         break;
2587                 }
2588         }
2589         if (tries == 5)
2590                 DRM_ERROR("FDI train 1 fail!\n");
2591
2592         /* Train 2 */
2593         reg = FDI_TX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         temp &= ~FDI_LINK_TRAIN_NONE;
2596         temp |= FDI_LINK_TRAIN_PATTERN_2;
2597         I915_WRITE(reg, temp);
2598
2599         reg = FDI_RX_CTL(pipe);
2600         temp = I915_READ(reg);
2601         temp &= ~FDI_LINK_TRAIN_NONE;
2602         temp |= FDI_LINK_TRAIN_PATTERN_2;
2603         I915_WRITE(reg, temp);
2604
2605         POSTING_READ(reg);
2606         udelay(150);
2607
2608         reg = FDI_RX_IIR(pipe);
2609         for (tries = 0; tries < 5; tries++) {
2610                 temp = I915_READ(reg);
2611                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613                 if (temp & FDI_RX_SYMBOL_LOCK) {
2614                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2615                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2616                         break;
2617                 }
2618         }
2619         if (tries == 5)
2620                 DRM_ERROR("FDI train 2 fail!\n");
2621
2622         DRM_DEBUG_KMS("FDI train done\n");
2623
2624 }
2625
2626 static const int snb_b_fdi_train_param[] = {
2627         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2628         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2629         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2630         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2631 };
2632
2633 /* The FDI link training functions for SNB/Cougarpoint. */
2634 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2635 {
2636         struct drm_device *dev = crtc->dev;
2637         struct drm_i915_private *dev_priv = dev->dev_private;
2638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2639         int pipe = intel_crtc->pipe;
2640         u32 reg, temp, i, retry;
2641
2642         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2643            for train result */
2644         reg = FDI_RX_IMR(pipe);
2645         temp = I915_READ(reg);
2646         temp &= ~FDI_RX_SYMBOL_LOCK;
2647         temp &= ~FDI_RX_BIT_LOCK;
2648         I915_WRITE(reg, temp);
2649
2650         POSTING_READ(reg);
2651         udelay(150);
2652
2653         /* enable CPU FDI TX and PCH FDI RX */
2654         reg = FDI_TX_CTL(pipe);
2655         temp = I915_READ(reg);
2656         temp &= ~(7 << 19);
2657         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2658         temp &= ~FDI_LINK_TRAIN_NONE;
2659         temp |= FDI_LINK_TRAIN_PATTERN_1;
2660         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661         /* SNB-B */
2662         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2664
2665         reg = FDI_RX_CTL(pipe);
2666         temp = I915_READ(reg);
2667         if (HAS_PCH_CPT(dev)) {
2668                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2669                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2670         } else {
2671                 temp &= ~FDI_LINK_TRAIN_NONE;
2672                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2673         }
2674         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2675
2676         POSTING_READ(reg);
2677         udelay(150);
2678
2679         if (HAS_PCH_CPT(dev))
2680                 cpt_phase_pointer_enable(dev, pipe);
2681
2682         for (i = 0; i < 4; i++) {
2683                 reg = FDI_TX_CTL(pipe);
2684                 temp = I915_READ(reg);
2685                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2686                 temp |= snb_b_fdi_train_param[i];
2687                 I915_WRITE(reg, temp);
2688
2689                 POSTING_READ(reg);
2690                 udelay(500);
2691
2692                 for (retry = 0; retry < 5; retry++) {
2693                         reg = FDI_RX_IIR(pipe);
2694                         temp = I915_READ(reg);
2695                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2696                         if (temp & FDI_RX_BIT_LOCK) {
2697                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2698                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2699                                 break;
2700                         }
2701                         udelay(50);
2702                 }
2703                 if (retry < 5)
2704                         break;
2705         }
2706         if (i == 4)
2707                 DRM_ERROR("FDI train 1 fail!\n");
2708
2709         /* Train 2 */
2710         reg = FDI_TX_CTL(pipe);
2711         temp = I915_READ(reg);
2712         temp &= ~FDI_LINK_TRAIN_NONE;
2713         temp |= FDI_LINK_TRAIN_PATTERN_2;
2714         if (IS_GEN6(dev)) {
2715                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716                 /* SNB-B */
2717                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2718         }
2719         I915_WRITE(reg, temp);
2720
2721         reg = FDI_RX_CTL(pipe);
2722         temp = I915_READ(reg);
2723         if (HAS_PCH_CPT(dev)) {
2724                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2725                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2726         } else {
2727                 temp &= ~FDI_LINK_TRAIN_NONE;
2728                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2729         }
2730         I915_WRITE(reg, temp);
2731
2732         POSTING_READ(reg);
2733         udelay(150);
2734
2735         for (i = 0; i < 4; i++) {
2736                 reg = FDI_TX_CTL(pipe);
2737                 temp = I915_READ(reg);
2738                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2739                 temp |= snb_b_fdi_train_param[i];
2740                 I915_WRITE(reg, temp);
2741
2742                 POSTING_READ(reg);
2743                 udelay(500);
2744
2745                 for (retry = 0; retry < 5; retry++) {
2746                         reg = FDI_RX_IIR(pipe);
2747                         temp = I915_READ(reg);
2748                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2749                         if (temp & FDI_RX_SYMBOL_LOCK) {
2750                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2751                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2752                                 break;
2753                         }
2754                         udelay(50);
2755                 }
2756                 if (retry < 5)
2757                         break;
2758         }
2759         if (i == 4)
2760                 DRM_ERROR("FDI train 2 fail!\n");
2761
2762         DRM_DEBUG_KMS("FDI train done.\n");
2763 }
2764
2765 /* Manual link training for Ivy Bridge A0 parts */
2766 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2767 {
2768         struct drm_device *dev = crtc->dev;
2769         struct drm_i915_private *dev_priv = dev->dev_private;
2770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2771         int pipe = intel_crtc->pipe;
2772         u32 reg, temp, i;
2773
2774         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2775            for train result */
2776         reg = FDI_RX_IMR(pipe);
2777         temp = I915_READ(reg);
2778         temp &= ~FDI_RX_SYMBOL_LOCK;
2779         temp &= ~FDI_RX_BIT_LOCK;
2780         I915_WRITE(reg, temp);
2781
2782         POSTING_READ(reg);
2783         udelay(150);
2784
2785         /* enable CPU FDI TX and PCH FDI RX */
2786         reg = FDI_TX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         temp &= ~(7 << 19);
2789         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2790         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2791         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2792         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2793         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2794         temp |= FDI_COMPOSITE_SYNC;
2795         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2796
2797         reg = FDI_RX_CTL(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~FDI_LINK_TRAIN_AUTO;
2800         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2801         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2802         temp |= FDI_COMPOSITE_SYNC;
2803         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2804
2805         POSTING_READ(reg);
2806         udelay(150);
2807
2808         if (HAS_PCH_CPT(dev))
2809                 cpt_phase_pointer_enable(dev, pipe);
2810
2811         for (i = 0; i < 4; i++) {
2812                 reg = FDI_TX_CTL(pipe);
2813                 temp = I915_READ(reg);
2814                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2815                 temp |= snb_b_fdi_train_param[i];
2816                 I915_WRITE(reg, temp);
2817
2818                 POSTING_READ(reg);
2819                 udelay(500);
2820
2821                 reg = FDI_RX_IIR(pipe);
2822                 temp = I915_READ(reg);
2823                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2824
2825                 if (temp & FDI_RX_BIT_LOCK ||
2826                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2827                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2828                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2829                         break;
2830                 }
2831         }
2832         if (i == 4)
2833                 DRM_ERROR("FDI train 1 fail!\n");
2834
2835         /* Train 2 */
2836         reg = FDI_TX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2839         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2840         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2841         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2842         I915_WRITE(reg, temp);
2843
2844         reg = FDI_RX_CTL(pipe);
2845         temp = I915_READ(reg);
2846         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2847         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2848         I915_WRITE(reg, temp);
2849
2850         POSTING_READ(reg);
2851         udelay(150);
2852
2853         for (i = 0; i < 4; i++) {
2854                 reg = FDI_TX_CTL(pipe);
2855                 temp = I915_READ(reg);
2856                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2857                 temp |= snb_b_fdi_train_param[i];
2858                 I915_WRITE(reg, temp);
2859
2860                 POSTING_READ(reg);
2861                 udelay(500);
2862
2863                 reg = FDI_RX_IIR(pipe);
2864                 temp = I915_READ(reg);
2865                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2866
2867                 if (temp & FDI_RX_SYMBOL_LOCK) {
2868                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2869                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2870                         break;
2871                 }
2872         }
2873         if (i == 4)
2874                 DRM_ERROR("FDI train 2 fail!\n");
2875
2876         DRM_DEBUG_KMS("FDI train done.\n");
2877 }
2878
2879 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2880 {
2881         struct drm_device *dev = crtc->dev;
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2884         int pipe = intel_crtc->pipe;
2885         u32 reg, temp;
2886
2887         /* Write the TU size bits so error detection works */
2888         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2889                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2890
2891         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2892         reg = FDI_RX_CTL(pipe);
2893         temp = I915_READ(reg);
2894         temp &= ~((0x7 << 19) | (0x7 << 16));
2895         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2896         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2897         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2898
2899         POSTING_READ(reg);
2900         udelay(200);
2901
2902         /* Switch from Rawclk to PCDclk */
2903         temp = I915_READ(reg);
2904         I915_WRITE(reg, temp | FDI_PCDCLK);
2905
2906         POSTING_READ(reg);
2907         udelay(200);
2908
2909         /* Enable CPU FDI TX PLL, always on for Ironlake */
2910         reg = FDI_TX_CTL(pipe);
2911         temp = I915_READ(reg);
2912         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2913                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2914
2915                 POSTING_READ(reg);
2916                 udelay(100);
2917         }
2918 }
2919
2920 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2921 {
2922         struct drm_i915_private *dev_priv = dev->dev_private;
2923         u32 flags = I915_READ(SOUTH_CHICKEN1);
2924
2925         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2926         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2927         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2928         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2929         POSTING_READ(SOUTH_CHICKEN1);
2930 }
2931 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2932 {
2933         struct drm_device *dev = crtc->dev;
2934         struct drm_i915_private *dev_priv = dev->dev_private;
2935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936         int pipe = intel_crtc->pipe;
2937         u32 reg, temp;
2938
2939         /* disable CPU FDI tx and PCH FDI rx */
2940         reg = FDI_TX_CTL(pipe);
2941         temp = I915_READ(reg);
2942         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2943         POSTING_READ(reg);
2944
2945         reg = FDI_RX_CTL(pipe);
2946         temp = I915_READ(reg);
2947         temp &= ~(0x7 << 16);
2948         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2949         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2950
2951         POSTING_READ(reg);
2952         udelay(100);
2953
2954         /* Ironlake workaround, disable clock pointer after downing FDI */
2955         if (HAS_PCH_IBX(dev)) {
2956                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2957                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2958                            I915_READ(FDI_RX_CHICKEN(pipe) &
2959                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2960         } else if (HAS_PCH_CPT(dev)) {
2961                 cpt_phase_pointer_disable(dev, pipe);
2962         }
2963
2964         /* still set train pattern 1 */
2965         reg = FDI_TX_CTL(pipe);
2966         temp = I915_READ(reg);
2967         temp &= ~FDI_LINK_TRAIN_NONE;
2968         temp |= FDI_LINK_TRAIN_PATTERN_1;
2969         I915_WRITE(reg, temp);
2970
2971         reg = FDI_RX_CTL(pipe);
2972         temp = I915_READ(reg);
2973         if (HAS_PCH_CPT(dev)) {
2974                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2975                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2976         } else {
2977                 temp &= ~FDI_LINK_TRAIN_NONE;
2978                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2979         }
2980         /* BPC in FDI rx is consistent with that in PIPECONF */
2981         temp &= ~(0x07 << 16);
2982         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2983         I915_WRITE(reg, temp);
2984
2985         POSTING_READ(reg);
2986         udelay(100);
2987 }
2988
2989 /*
2990  * When we disable a pipe, we need to clear any pending scanline wait events
2991  * to avoid hanging the ring, which we assume we are waiting on.
2992  */
2993 static void intel_clear_scanline_wait(struct drm_device *dev)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         struct intel_ring_buffer *ring;
2997         u32 tmp;
2998
2999         if (IS_GEN2(dev))
3000                 /* Can't break the hang on i8xx */
3001                 return;
3002
3003         ring = LP_RING(dev_priv);
3004         tmp = I915_READ_CTL(ring);
3005         if (tmp & RING_WAIT)
3006                 I915_WRITE_CTL(ring, tmp);
3007 }
3008
3009 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3010 {
3011         struct drm_i915_gem_object *obj;
3012         struct drm_i915_private *dev_priv;
3013
3014         if (crtc->fb == NULL)
3015                 return;
3016
3017         obj = to_intel_framebuffer(crtc->fb)->obj;
3018         dev_priv = crtc->dev->dev_private;
3019         wait_event(dev_priv->pending_flip_queue,
3020                    atomic_read(&obj->pending_flip) == 0);
3021 }
3022
3023 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
3024 {
3025         struct drm_device *dev = crtc->dev;
3026         struct drm_mode_config *mode_config = &dev->mode_config;
3027         struct intel_encoder *encoder;
3028
3029         /*
3030          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3031          * must be driven by its own crtc; no sharing is possible.
3032          */
3033         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3034                 if (encoder->base.crtc != crtc)
3035                         continue;
3036
3037                 switch (encoder->type) {
3038                 case INTEL_OUTPUT_EDP:
3039                         if (!intel_encoder_is_pch_edp(&encoder->base))
3040                                 return false;
3041                         continue;
3042                 }
3043         }
3044
3045         return true;
3046 }
3047
3048 /*
3049  * Enable PCH resources required for PCH ports:
3050  *   - PCH PLLs
3051  *   - FDI training & RX/TX
3052  *   - update transcoder timings
3053  *   - DP transcoding bits
3054  *   - transcoder
3055  */
3056 static void ironlake_pch_enable(struct drm_crtc *crtc)
3057 {
3058         struct drm_device *dev = crtc->dev;
3059         struct drm_i915_private *dev_priv = dev->dev_private;
3060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3061         int pipe = intel_crtc->pipe;
3062         u32 reg, temp, transc_sel;
3063
3064         /* For PCH output, training FDI link */
3065         dev_priv->display.fdi_link_train(crtc);
3066
3067         intel_enable_pch_pll(dev_priv, pipe);
3068
3069         if (HAS_PCH_CPT(dev)) {
3070                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
3071                         TRANSC_DPLLB_SEL;
3072
3073                 /* Be sure PCH DPLL SEL is set */
3074                 temp = I915_READ(PCH_DPLL_SEL);
3075                 if (pipe == 0) {
3076                         temp &= ~(TRANSA_DPLLB_SEL);
3077                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3078                 } else if (pipe == 1) {
3079                         temp &= ~(TRANSB_DPLLB_SEL);
3080                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3081                 } else if (pipe == 2) {
3082                         temp &= ~(TRANSC_DPLLB_SEL);
3083                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3084                 }
3085                 I915_WRITE(PCH_DPLL_SEL, temp);
3086         }
3087
3088         /* set transcoder timing, panel must allow it */
3089         assert_panel_unlocked(dev_priv, pipe);
3090         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3091         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3092         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3093
3094         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3095         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3096         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3097         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3098
3099         intel_fdi_normal_train(crtc);
3100
3101         /* For PCH DP, enable TRANS_DP_CTL */
3102         if (HAS_PCH_CPT(dev) &&
3103             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3104              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3105                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3106                 reg = TRANS_DP_CTL(pipe);
3107                 temp = I915_READ(reg);
3108                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3109                           TRANS_DP_SYNC_MASK |
3110                           TRANS_DP_BPC_MASK);
3111                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3112                          TRANS_DP_ENH_FRAMING);
3113                 temp |= bpc << 9; /* same format but at 11:9 */
3114
3115                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3116                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3117                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3118                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3119
3120                 switch (intel_trans_dp_port_sel(crtc)) {
3121                 case PCH_DP_B:
3122                         temp |= TRANS_DP_PORT_SEL_B;
3123                         break;
3124                 case PCH_DP_C:
3125                         temp |= TRANS_DP_PORT_SEL_C;
3126                         break;
3127                 case PCH_DP_D:
3128                         temp |= TRANS_DP_PORT_SEL_D;
3129                         break;
3130                 default:
3131                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3132                         temp |= TRANS_DP_PORT_SEL_B;
3133                         break;
3134                 }
3135
3136                 I915_WRITE(reg, temp);
3137         }
3138
3139         intel_enable_transcoder(dev_priv, pipe);
3140 }
3141
3142 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3143 {
3144         struct drm_i915_private *dev_priv = dev->dev_private;
3145         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3146         u32 temp;
3147
3148         temp = I915_READ(dslreg);
3149         udelay(500);
3150         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3151                 /* Without this, mode sets may fail silently on FDI */
3152                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3153                 udelay(250);
3154                 I915_WRITE(tc2reg, 0);
3155                 if (wait_for(I915_READ(dslreg) != temp, 5))
3156                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3157         }
3158 }
3159
3160 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3161 {
3162         struct drm_device *dev = crtc->dev;
3163         struct drm_i915_private *dev_priv = dev->dev_private;
3164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165         int pipe = intel_crtc->pipe;
3166         int plane = intel_crtc->plane;
3167         u32 temp;
3168         bool is_pch_port;
3169
3170         if (intel_crtc->active)
3171                 return;
3172
3173         intel_crtc->active = true;
3174         intel_update_watermarks(dev);
3175
3176         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3177                 temp = I915_READ(PCH_LVDS);
3178                 if ((temp & LVDS_PORT_EN) == 0)
3179                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3180         }
3181
3182         is_pch_port = intel_crtc_driving_pch(crtc);
3183
3184         if (is_pch_port)
3185                 ironlake_fdi_pll_enable(crtc);
3186         else
3187                 ironlake_fdi_disable(crtc);
3188
3189         /* Enable panel fitting for LVDS */
3190         if (dev_priv->pch_pf_size &&
3191             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3192                 /* Force use of hard-coded filter coefficients
3193                  * as some pre-programmed values are broken,
3194                  * e.g. x201.
3195                  */
3196                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3197                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3198                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3199         }
3200
3201         /*
3202          * On ILK+ LUT must be loaded before the pipe is running but with
3203          * clocks enabled
3204          */
3205         intel_crtc_load_lut(crtc);
3206
3207         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3208         intel_enable_plane(dev_priv, plane, pipe);
3209
3210         if (is_pch_port)
3211                 ironlake_pch_enable(crtc);
3212
3213         mutex_lock(&dev->struct_mutex);
3214         intel_update_fbc(dev);
3215         mutex_unlock(&dev->struct_mutex);
3216
3217         intel_crtc_update_cursor(crtc, true);
3218 }
3219
3220 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3221 {
3222         struct drm_device *dev = crtc->dev;
3223         struct drm_i915_private *dev_priv = dev->dev_private;
3224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3225         int pipe = intel_crtc->pipe;
3226         int plane = intel_crtc->plane;
3227         u32 reg, temp;
3228
3229         if (!intel_crtc->active)
3230                 return;
3231
3232         intel_crtc_wait_for_pending_flips(crtc);
3233         drm_vblank_off(dev, pipe);
3234         intel_crtc_update_cursor(crtc, false);
3235
3236         intel_disable_plane(dev_priv, plane, pipe);
3237
3238         if (dev_priv->cfb_plane == plane)
3239                 intel_disable_fbc(dev);
3240
3241         intel_disable_pipe(dev_priv, pipe);
3242
3243         /* Disable PF */
3244         I915_WRITE(PF_CTL(pipe), 0);
3245         I915_WRITE(PF_WIN_SZ(pipe), 0);
3246
3247         ironlake_fdi_disable(crtc);
3248
3249         /* This is a horrible layering violation; we should be doing this in
3250          * the connector/encoder ->prepare instead, but we don't always have
3251          * enough information there about the config to know whether it will
3252          * actually be necessary or just cause undesired flicker.
3253          */
3254         intel_disable_pch_ports(dev_priv, pipe);
3255
3256         intel_disable_transcoder(dev_priv, pipe);
3257
3258         if (HAS_PCH_CPT(dev)) {
3259                 /* disable TRANS_DP_CTL */
3260                 reg = TRANS_DP_CTL(pipe);
3261                 temp = I915_READ(reg);
3262                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3263                 temp |= TRANS_DP_PORT_SEL_NONE;
3264                 I915_WRITE(reg, temp);
3265
3266                 /* disable DPLL_SEL */
3267                 temp = I915_READ(PCH_DPLL_SEL);
3268                 switch (pipe) {
3269                 case 0:
3270                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3271                         break;
3272                 case 1:
3273                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3274                         break;
3275                 case 2:
3276                         /* C shares PLL A or B */
3277                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3278                         break;
3279                 default:
3280                         BUG(); /* wtf */
3281                 }
3282                 I915_WRITE(PCH_DPLL_SEL, temp);
3283         }
3284
3285         /* disable PCH DPLL */
3286         if (!intel_crtc->no_pll)
3287                 intel_disable_pch_pll(dev_priv, pipe);
3288
3289         /* Switch from PCDclk to Rawclk */
3290         reg = FDI_RX_CTL(pipe);
3291         temp = I915_READ(reg);
3292         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3293
3294         /* Disable CPU FDI TX PLL */
3295         reg = FDI_TX_CTL(pipe);
3296         temp = I915_READ(reg);
3297         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3298
3299         POSTING_READ(reg);
3300         udelay(100);
3301
3302         reg = FDI_RX_CTL(pipe);
3303         temp = I915_READ(reg);
3304         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3305
3306         /* Wait for the clocks to turn off. */
3307         POSTING_READ(reg);
3308         udelay(100);
3309
3310         intel_crtc->active = false;
3311         intel_update_watermarks(dev);
3312
3313         mutex_lock(&dev->struct_mutex);
3314         intel_update_fbc(dev);
3315         intel_clear_scanline_wait(dev);
3316         mutex_unlock(&dev->struct_mutex);
3317 }
3318
3319 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3320 {
3321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3322         int pipe = intel_crtc->pipe;
3323         int plane = intel_crtc->plane;
3324
3325         /* XXX: When our outputs are all unaware of DPMS modes other than off
3326          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3327          */
3328         switch (mode) {
3329         case DRM_MODE_DPMS_ON:
3330         case DRM_MODE_DPMS_STANDBY:
3331         case DRM_MODE_DPMS_SUSPEND:
3332                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3333                 ironlake_crtc_enable(crtc);
3334                 break;
3335
3336         case DRM_MODE_DPMS_OFF:
3337                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3338                 ironlake_crtc_disable(crtc);
3339                 break;
3340         }
3341 }
3342
3343 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3344 {
3345         if (!enable && intel_crtc->overlay) {
3346                 struct drm_device *dev = intel_crtc->base.dev;
3347                 struct drm_i915_private *dev_priv = dev->dev_private;
3348
3349                 mutex_lock(&dev->struct_mutex);
3350                 dev_priv->mm.interruptible = false;
3351                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3352                 dev_priv->mm.interruptible = true;
3353                 mutex_unlock(&dev->struct_mutex);
3354         }
3355
3356         /* Let userspace switch the overlay on again. In most cases userspace
3357          * has to recompute where to put it anyway.
3358          */
3359 }
3360
3361 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3362 {
3363         struct drm_device *dev = crtc->dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366         int pipe = intel_crtc->pipe;
3367         int plane = intel_crtc->plane;
3368
3369         if (intel_crtc->active)
3370                 return;
3371
3372         intel_crtc->active = true;
3373         intel_update_watermarks(dev);
3374
3375         intel_enable_pll(dev_priv, pipe);
3376         intel_enable_pipe(dev_priv, pipe, false);
3377         intel_enable_plane(dev_priv, plane, pipe);
3378
3379         intel_crtc_load_lut(crtc);
3380         intel_update_fbc(dev);
3381
3382         /* Give the overlay scaler a chance to enable if it's on this pipe */
3383         intel_crtc_dpms_overlay(intel_crtc, true);
3384         intel_crtc_update_cursor(crtc, true);
3385 }
3386
3387 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3388 {
3389         struct drm_device *dev = crtc->dev;
3390         struct drm_i915_private *dev_priv = dev->dev_private;
3391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392         int pipe = intel_crtc->pipe;
3393         int plane = intel_crtc->plane;
3394
3395         if (!intel_crtc->active)
3396                 return;
3397
3398         /* Give the overlay scaler a chance to disable if it's on this pipe */
3399         intel_crtc_wait_for_pending_flips(crtc);
3400         drm_vblank_off(dev, pipe);
3401         intel_crtc_dpms_overlay(intel_crtc, false);
3402         intel_crtc_update_cursor(crtc, false);
3403
3404         if (dev_priv->cfb_plane == plane)
3405                 intel_disable_fbc(dev);
3406
3407         intel_disable_plane(dev_priv, plane, pipe);
3408         intel_disable_pipe(dev_priv, pipe);
3409         intel_disable_pll(dev_priv, pipe);
3410
3411         intel_crtc->active = false;
3412         intel_update_fbc(dev);
3413         intel_update_watermarks(dev);
3414         intel_clear_scanline_wait(dev);
3415 }
3416
3417 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3418 {
3419         /* XXX: When our outputs are all unaware of DPMS modes other than off
3420          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3421          */
3422         switch (mode) {
3423         case DRM_MODE_DPMS_ON:
3424         case DRM_MODE_DPMS_STANDBY:
3425         case DRM_MODE_DPMS_SUSPEND:
3426                 i9xx_crtc_enable(crtc);
3427                 break;
3428         case DRM_MODE_DPMS_OFF:
3429                 i9xx_crtc_disable(crtc);
3430                 break;
3431         }
3432 }
3433
3434 /**
3435  * Sets the power management mode of the pipe and plane.
3436  */
3437 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3438 {
3439         struct drm_device *dev = crtc->dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct drm_i915_master_private *master_priv;
3442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3443         int pipe = intel_crtc->pipe;
3444         bool enabled;
3445
3446         if (intel_crtc->dpms_mode == mode)
3447                 return;
3448
3449         intel_crtc->dpms_mode = mode;
3450
3451         dev_priv->display.dpms(crtc, mode);
3452
3453         if (!dev->primary->master)
3454                 return;
3455
3456         master_priv = dev->primary->master->driver_priv;
3457         if (!master_priv->sarea_priv)
3458                 return;
3459
3460         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3461
3462         switch (pipe) {
3463         case 0:
3464                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3465                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3466                 break;
3467         case 1:
3468                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3469                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3470                 break;
3471         default:
3472                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3473                 break;
3474         }
3475 }
3476
3477 static void intel_crtc_disable(struct drm_crtc *crtc)
3478 {
3479         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3480         struct drm_device *dev = crtc->dev;
3481
3482         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3483         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3484         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3485
3486         if (crtc->fb) {
3487                 mutex_lock(&dev->struct_mutex);
3488                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3489                 mutex_unlock(&dev->struct_mutex);
3490         }
3491 }
3492
3493 /* Prepare for a mode set.
3494  *
3495  * Note we could be a lot smarter here.  We need to figure out which outputs
3496  * will be enabled, which disabled (in short, how the config will changes)
3497  * and perform the minimum necessary steps to accomplish that, e.g. updating
3498  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3499  * panel fitting is in the proper state, etc.
3500  */
3501 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3502 {
3503         i9xx_crtc_disable(crtc);
3504 }
3505
3506 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3507 {
3508         i9xx_crtc_enable(crtc);
3509 }
3510
3511 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3512 {
3513         ironlake_crtc_disable(crtc);
3514 }
3515
3516 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3517 {
3518         ironlake_crtc_enable(crtc);
3519 }
3520
3521 void intel_encoder_prepare(struct drm_encoder *encoder)
3522 {
3523         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3524         /* lvds has its own version of prepare see intel_lvds_prepare */
3525         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3526 }
3527
3528 void intel_encoder_commit(struct drm_encoder *encoder)
3529 {
3530         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3531         struct drm_device *dev = encoder->dev;
3532         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3533         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3534
3535         /* lvds has its own version of commit see intel_lvds_commit */
3536         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3537
3538         if (HAS_PCH_CPT(dev))
3539                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3540 }
3541
3542 void intel_encoder_destroy(struct drm_encoder *encoder)
3543 {
3544         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3545
3546         drm_encoder_cleanup(encoder);
3547         kfree(intel_encoder);
3548 }
3549
3550 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3551                                   struct drm_display_mode *mode,
3552                                   struct drm_display_mode *adjusted_mode)
3553 {
3554         struct drm_device *dev = crtc->dev;
3555
3556         if (HAS_PCH_SPLIT(dev)) {
3557                 /* FDI link clock is fixed at 2.7G */
3558                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3559                         return false;
3560         }
3561
3562         /* All interlaced capable intel hw wants timings in frames. */
3563         drm_mode_set_crtcinfo(adjusted_mode, 0);
3564
3565         return true;
3566 }
3567
3568 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3569 {
3570         return 400000; /* FIXME */
3571 }
3572
3573 static int i945_get_display_clock_speed(struct drm_device *dev)
3574 {
3575         return 400000;
3576 }
3577
3578 static int i915_get_display_clock_speed(struct drm_device *dev)
3579 {
3580         return 333000;
3581 }
3582
3583 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3584 {
3585         return 200000;
3586 }
3587
3588 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3589 {
3590         u16 gcfgc = 0;
3591
3592         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3593
3594         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3595                 return 133000;
3596         else {
3597                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3598                 case GC_DISPLAY_CLOCK_333_MHZ:
3599                         return 333000;
3600                 default:
3601                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3602                         return 190000;
3603                 }
3604         }
3605 }
3606
3607 static int i865_get_display_clock_speed(struct drm_device *dev)
3608 {
3609         return 266000;
3610 }
3611
3612 static int i855_get_display_clock_speed(struct drm_device *dev)
3613 {
3614         u16 hpllcc = 0;
3615         /* Assume that the hardware is in the high speed state.  This
3616          * should be the default.
3617          */
3618         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3619         case GC_CLOCK_133_200:
3620         case GC_CLOCK_100_200:
3621                 return 200000;
3622         case GC_CLOCK_166_250:
3623                 return 250000;
3624         case GC_CLOCK_100_133:
3625                 return 133000;
3626         }
3627
3628         /* Shouldn't happen */
3629         return 0;
3630 }
3631
3632 static int i830_get_display_clock_speed(struct drm_device *dev)
3633 {
3634         return 133000;
3635 }
3636
3637 struct fdi_m_n {
3638         u32        tu;
3639         u32        gmch_m;
3640         u32        gmch_n;
3641         u32        link_m;
3642         u32        link_n;
3643 };
3644
3645 static void
3646 fdi_reduce_ratio(u32 *num, u32 *den)
3647 {
3648         while (*num > 0xffffff || *den > 0xffffff) {
3649                 *num >>= 1;
3650                 *den >>= 1;
3651         }
3652 }
3653
3654 static void
3655 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3656                      int link_clock, struct fdi_m_n *m_n)
3657 {
3658         m_n->tu = 64; /* default size */
3659
3660         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3661         m_n->gmch_m = bits_per_pixel * pixel_clock;
3662         m_n->gmch_n = link_clock * nlanes * 8;
3663         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3664
3665         m_n->link_m = pixel_clock;
3666         m_n->link_n = link_clock;
3667         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3668 }
3669
3670
3671 struct intel_watermark_params {
3672         unsigned long fifo_size;
3673         unsigned long max_wm;
3674         unsigned long default_wm;
3675         unsigned long guard_size;
3676         unsigned long cacheline_size;
3677 };
3678
3679 /* Pineview has different values for various configs */
3680 static const struct intel_watermark_params pineview_display_wm = {
3681         PINEVIEW_DISPLAY_FIFO,
3682         PINEVIEW_MAX_WM,
3683         PINEVIEW_DFT_WM,
3684         PINEVIEW_GUARD_WM,
3685         PINEVIEW_FIFO_LINE_SIZE
3686 };
3687 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3688         PINEVIEW_DISPLAY_FIFO,
3689         PINEVIEW_MAX_WM,
3690         PINEVIEW_DFT_HPLLOFF_WM,
3691         PINEVIEW_GUARD_WM,
3692         PINEVIEW_FIFO_LINE_SIZE
3693 };
3694 static const struct intel_watermark_params pineview_cursor_wm = {
3695         PINEVIEW_CURSOR_FIFO,
3696         PINEVIEW_CURSOR_MAX_WM,
3697         PINEVIEW_CURSOR_DFT_WM,
3698         PINEVIEW_CURSOR_GUARD_WM,
3699         PINEVIEW_FIFO_LINE_SIZE,
3700 };
3701 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3702         PINEVIEW_CURSOR_FIFO,
3703         PINEVIEW_CURSOR_MAX_WM,
3704         PINEVIEW_CURSOR_DFT_WM,
3705         PINEVIEW_CURSOR_GUARD_WM,
3706         PINEVIEW_FIFO_LINE_SIZE
3707 };
3708 static const struct intel_watermark_params g4x_wm_info = {
3709         G4X_FIFO_SIZE,
3710         G4X_MAX_WM,
3711         G4X_MAX_WM,
3712         2,
3713         G4X_FIFO_LINE_SIZE,
3714 };
3715 static const struct intel_watermark_params g4x_cursor_wm_info = {
3716         I965_CURSOR_FIFO,
3717         I965_CURSOR_MAX_WM,
3718         I965_CURSOR_DFT_WM,
3719         2,
3720         G4X_FIFO_LINE_SIZE,
3721 };
3722 static const struct intel_watermark_params valleyview_wm_info = {
3723         VALLEYVIEW_FIFO_SIZE,
3724         VALLEYVIEW_MAX_WM,
3725         VALLEYVIEW_MAX_WM,
3726         2,
3727         G4X_FIFO_LINE_SIZE,
3728 };
3729 static const struct intel_watermark_params valleyview_cursor_wm_info = {
3730         I965_CURSOR_FIFO,
3731         VALLEYVIEW_CURSOR_MAX_WM,
3732         I965_CURSOR_DFT_WM,
3733         2,
3734         G4X_FIFO_LINE_SIZE,
3735 };
3736 static const struct intel_watermark_params i965_cursor_wm_info = {
3737         I965_CURSOR_FIFO,
3738         I965_CURSOR_MAX_WM,
3739         I965_CURSOR_DFT_WM,
3740         2,
3741         I915_FIFO_LINE_SIZE,
3742 };
3743 static const struct intel_watermark_params i945_wm_info = {
3744         I945_FIFO_SIZE,
3745         I915_MAX_WM,
3746         1,
3747         2,
3748         I915_FIFO_LINE_SIZE
3749 };
3750 static const struct intel_watermark_params i915_wm_info = {
3751         I915_FIFO_SIZE,
3752         I915_MAX_WM,
3753         1,
3754         2,
3755         I915_FIFO_LINE_SIZE
3756 };
3757 static const struct intel_watermark_params i855_wm_info = {
3758         I855GM_FIFO_SIZE,
3759         I915_MAX_WM,
3760         1,
3761         2,
3762         I830_FIFO_LINE_SIZE
3763 };
3764 static const struct intel_watermark_params i830_wm_info = {
3765         I830_FIFO_SIZE,
3766         I915_MAX_WM,
3767         1,
3768         2,
3769         I830_FIFO_LINE_SIZE
3770 };
3771
3772 static const struct intel_watermark_params ironlake_display_wm_info = {
3773         ILK_DISPLAY_FIFO,
3774         ILK_DISPLAY_MAXWM,
3775         ILK_DISPLAY_DFTWM,
3776         2,
3777         ILK_FIFO_LINE_SIZE
3778 };
3779 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3780         ILK_CURSOR_FIFO,
3781         ILK_CURSOR_MAXWM,
3782         ILK_CURSOR_DFTWM,
3783         2,
3784         ILK_FIFO_LINE_SIZE
3785 };
3786 static const struct intel_watermark_params ironlake_display_srwm_info = {
3787         ILK_DISPLAY_SR_FIFO,
3788         ILK_DISPLAY_MAX_SRWM,
3789         ILK_DISPLAY_DFT_SRWM,
3790         2,
3791         ILK_FIFO_LINE_SIZE
3792 };
3793 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3794         ILK_CURSOR_SR_FIFO,
3795         ILK_CURSOR_MAX_SRWM,
3796         ILK_CURSOR_DFT_SRWM,
3797         2,
3798         ILK_FIFO_LINE_SIZE
3799 };
3800
3801 static const struct intel_watermark_params sandybridge_display_wm_info = {
3802         SNB_DISPLAY_FIFO,
3803         SNB_DISPLAY_MAXWM,
3804         SNB_DISPLAY_DFTWM,
3805         2,
3806         SNB_FIFO_LINE_SIZE
3807 };
3808 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3809         SNB_CURSOR_FIFO,
3810         SNB_CURSOR_MAXWM,
3811         SNB_CURSOR_DFTWM,
3812         2,
3813         SNB_FIFO_LINE_SIZE
3814 };
3815 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3816         SNB_DISPLAY_SR_FIFO,
3817         SNB_DISPLAY_MAX_SRWM,
3818         SNB_DISPLAY_DFT_SRWM,
3819         2,
3820         SNB_FIFO_LINE_SIZE
3821 };
3822 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3823         SNB_CURSOR_SR_FIFO,
3824         SNB_CURSOR_MAX_SRWM,
3825         SNB_CURSOR_DFT_SRWM,
3826         2,
3827         SNB_FIFO_LINE_SIZE
3828 };
3829
3830
3831 /**
3832  * intel_calculate_wm - calculate watermark level
3833  * @clock_in_khz: pixel clock
3834  * @wm: chip FIFO params
3835  * @pixel_size: display pixel size
3836  * @latency_ns: memory latency for the platform
3837  *
3838  * Calculate the watermark level (the level at which the display plane will
3839  * start fetching from memory again).  Each chip has a different display
3840  * FIFO size and allocation, so the caller needs to figure that out and pass
3841  * in the correct intel_watermark_params structure.
3842  *
3843  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3844  * on the pixel size.  When it reaches the watermark level, it'll start
3845  * fetching FIFO line sized based chunks from memory until the FIFO fills
3846  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3847  * will occur, and a display engine hang could result.
3848  */
3849 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3850                                         const struct intel_watermark_params *wm,
3851                                         int fifo_size,
3852                                         int pixel_size,
3853                                         unsigned long latency_ns)
3854 {
3855         long entries_required, wm_size;
3856
3857         /*
3858          * Note: we need to make sure we don't overflow for various clock &
3859          * latency values.
3860          * clocks go from a few thousand to several hundred thousand.
3861          * latency is usually a few thousand
3862          */
3863         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3864                 1000;
3865         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3866
3867         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3868
3869         wm_size = fifo_size - (entries_required + wm->guard_size);
3870
3871         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3872
3873         /* Don't promote wm_size to unsigned... */
3874         if (wm_size > (long)wm->max_wm)
3875                 wm_size = wm->max_wm;
3876         if (wm_size <= 0)
3877                 wm_size = wm->default_wm;
3878         return wm_size;
3879 }
3880
3881 struct cxsr_latency {
3882         int is_desktop;
3883         int is_ddr3;
3884         unsigned long fsb_freq;
3885         unsigned long mem_freq;
3886         unsigned long display_sr;
3887         unsigned long display_hpll_disable;
3888         unsigned long cursor_sr;
3889         unsigned long cursor_hpll_disable;
3890 };
3891
3892 static const struct cxsr_latency cxsr_latency_table[] = {
3893         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3894         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3895         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3896         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3897         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3898
3899         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3900         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3901         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3902         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3903         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3904
3905         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3906         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3907         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3908         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3909         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3910
3911         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3912         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3913         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3914         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3915         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3916
3917         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3918         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3919         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3920         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3921         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3922
3923         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3924         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3925         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3926         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3927         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3928 };
3929
3930 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3931                                                          int is_ddr3,
3932                                                          int fsb,
3933                                                          int mem)
3934 {
3935         const struct cxsr_latency *latency;
3936         int i;
3937
3938         if (fsb == 0 || mem == 0)
3939                 return NULL;
3940
3941         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3942                 latency = &cxsr_latency_table[i];
3943                 if (is_desktop == latency->is_desktop &&
3944                     is_ddr3 == latency->is_ddr3 &&
3945                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3946                         return latency;
3947         }
3948
3949         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3950
3951         return NULL;
3952 }
3953
3954 static void pineview_disable_cxsr(struct drm_device *dev)
3955 {
3956         struct drm_i915_private *dev_priv = dev->dev_private;
3957
3958         /* deactivate cxsr */
3959         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3960 }
3961
3962 /*
3963  * Latency for FIFO fetches is dependent on several factors:
3964  *   - memory configuration (speed, channels)
3965  *   - chipset
3966  *   - current MCH state
3967  * It can be fairly high in some situations, so here we assume a fairly
3968  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3969  * set this value too high, the FIFO will fetch frequently to stay full)
3970  * and power consumption (set it too low to save power and we might see
3971  * FIFO underruns and display "flicker").
3972  *
3973  * A value of 5us seems to be a good balance; safe for very low end
3974  * platforms but not overly aggressive on lower latency configs.
3975  */
3976 static const int latency_ns = 5000;
3977
3978 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3979 {
3980         struct drm_i915_private *dev_priv = dev->dev_private;
3981         uint32_t dsparb = I915_READ(DSPARB);
3982         int size;
3983
3984         size = dsparb & 0x7f;
3985         if (plane)
3986                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3987
3988         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3989                       plane ? "B" : "A", size);
3990
3991         return size;
3992 }
3993
3994 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3995 {
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997         uint32_t dsparb = I915_READ(DSPARB);
3998         int size;
3999
4000         size = dsparb & 0x1ff;
4001         if (plane)
4002                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
4003         size >>= 1; /* Convert to cachelines */
4004
4005         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4006                       plane ? "B" : "A", size);
4007
4008         return size;
4009 }
4010
4011 static int i845_get_fifo_size(struct drm_device *dev, int plane)
4012 {
4013         struct drm_i915_private *dev_priv = dev->dev_private;
4014         uint32_t dsparb = I915_READ(DSPARB);
4015         int size;
4016
4017         size = dsparb & 0x7f;
4018         size >>= 2; /* Convert to cachelines */
4019
4020         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4021                       plane ? "B" : "A",
4022                       size);
4023
4024         return size;
4025 }
4026
4027 static int i830_get_fifo_size(struct drm_device *dev, int plane)
4028 {
4029         struct drm_i915_private *dev_priv = dev->dev_private;
4030         uint32_t dsparb = I915_READ(DSPARB);
4031         int size;
4032
4033         size = dsparb & 0x7f;
4034         size >>= 1; /* Convert to cachelines */
4035
4036         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4037                       plane ? "B" : "A", size);
4038
4039         return size;
4040 }
4041
4042 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
4043 {
4044         struct drm_crtc *crtc, *enabled = NULL;
4045
4046         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4047                 if (crtc->enabled && crtc->fb) {
4048                         if (enabled)
4049                                 return NULL;
4050                         enabled = crtc;
4051                 }
4052         }
4053
4054         return enabled;
4055 }
4056
4057 static void pineview_update_wm(struct drm_device *dev)
4058 {
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         struct drm_crtc *crtc;
4061         const struct cxsr_latency *latency;
4062         u32 reg;
4063         unsigned long wm;
4064
4065         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
4066                                          dev_priv->fsb_freq, dev_priv->mem_freq);
4067         if (!latency) {
4068                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
4069                 pineview_disable_cxsr(dev);
4070                 return;
4071         }
4072
4073         crtc = single_enabled_crtc(dev);
4074         if (crtc) {
4075                 int clock = crtc->mode.clock;
4076                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4077
4078                 /* Display SR */
4079                 wm = intel_calculate_wm(clock, &pineview_display_wm,
4080                                         pineview_display_wm.fifo_size,
4081                                         pixel_size, latency->display_sr);
4082                 reg = I915_READ(DSPFW1);
4083                 reg &= ~DSPFW_SR_MASK;
4084                 reg |= wm << DSPFW_SR_SHIFT;
4085                 I915_WRITE(DSPFW1, reg);
4086                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4087
4088                 /* cursor SR */
4089                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4090                                         pineview_display_wm.fifo_size,
4091                                         pixel_size, latency->cursor_sr);
4092                 reg = I915_READ(DSPFW3);
4093                 reg &= ~DSPFW_CURSOR_SR_MASK;
4094                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4095                 I915_WRITE(DSPFW3, reg);
4096
4097                 /* Display HPLL off SR */
4098                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4099                                         pineview_display_hplloff_wm.fifo_size,
4100                                         pixel_size, latency->display_hpll_disable);
4101                 reg = I915_READ(DSPFW3);
4102                 reg &= ~DSPFW_HPLL_SR_MASK;
4103                 reg |= wm & DSPFW_HPLL_SR_MASK;
4104                 I915_WRITE(DSPFW3, reg);
4105
4106                 /* cursor HPLL off SR */
4107                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4108                                         pineview_display_hplloff_wm.fifo_size,
4109                                         pixel_size, latency->cursor_hpll_disable);
4110                 reg = I915_READ(DSPFW3);
4111                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4112                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4113                 I915_WRITE(DSPFW3, reg);
4114                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4115
4116                 /* activate cxsr */
4117                 I915_WRITE(DSPFW3,
4118                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4119                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4120         } else {
4121                 pineview_disable_cxsr(dev);
4122                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4123         }
4124 }
4125
4126 static bool g4x_compute_wm0(struct drm_device *dev,
4127                             int plane,
4128                             const struct intel_watermark_params *display,
4129                             int display_latency_ns,
4130                             const struct intel_watermark_params *cursor,
4131                             int cursor_latency_ns,
4132                             int *plane_wm,
4133                             int *cursor_wm)
4134 {
4135         struct drm_crtc *crtc;
4136         int htotal, hdisplay, clock, pixel_size;
4137         int line_time_us, line_count;
4138         int entries, tlb_miss;
4139
4140         crtc = intel_get_crtc_for_plane(dev, plane);
4141         if (crtc->fb == NULL || !crtc->enabled) {
4142                 *cursor_wm = cursor->guard_size;
4143                 *plane_wm = display->guard_size;
4144                 return false;
4145         }
4146
4147         htotal = crtc->mode.htotal;
4148         hdisplay = crtc->mode.hdisplay;
4149         clock = crtc->mode.clock;
4150         pixel_size = crtc->fb->bits_per_pixel / 8;
4151
4152         /* Use the small buffer method to calculate plane watermark */
4153         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4154         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4155         if (tlb_miss > 0)
4156                 entries += tlb_miss;
4157         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4158         *plane_wm = entries + display->guard_size;
4159         if (*plane_wm > (int)display->max_wm)
4160                 *plane_wm = display->max_wm;
4161
4162         /* Use the large buffer method to calculate cursor watermark */
4163         line_time_us = ((htotal * 1000) / clock);
4164         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4165         entries = line_count * 64 * pixel_size;
4166         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4167         if (tlb_miss > 0)
4168                 entries += tlb_miss;
4169         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4170         *cursor_wm = entries + cursor->guard_size;
4171         if (*cursor_wm > (int)cursor->max_wm)
4172                 *cursor_wm = (int)cursor->max_wm;
4173
4174         return true;
4175 }
4176
4177 /*
4178  * Check the wm result.
4179  *
4180  * If any calculated watermark values is larger than the maximum value that
4181  * can be programmed into the associated watermark register, that watermark
4182  * must be disabled.
4183  */
4184 static bool g4x_check_srwm(struct drm_device *dev,
4185                            int display_wm, int cursor_wm,
4186                            const struct intel_watermark_params *display,
4187                            const struct intel_watermark_params *cursor)
4188 {
4189         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4190                       display_wm, cursor_wm);
4191
4192         if (display_wm > display->max_wm) {
4193                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4194                               display_wm, display->max_wm);
4195                 return false;
4196         }
4197
4198         if (cursor_wm > cursor->max_wm) {
4199                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4200                               cursor_wm, cursor->max_wm);
4201                 return false;
4202         }
4203
4204         if (!(display_wm || cursor_wm)) {
4205                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4206                 return false;
4207         }
4208
4209         return true;
4210 }
4211
4212 static bool g4x_compute_srwm(struct drm_device *dev,
4213                              int plane,
4214                              int latency_ns,
4215                              const struct intel_watermark_params *display,
4216                              const struct intel_watermark_params *cursor,
4217                              int *display_wm, int *cursor_wm)
4218 {
4219         struct drm_crtc *crtc;
4220         int hdisplay, htotal, pixel_size, clock;
4221         unsigned long line_time_us;
4222         int line_count, line_size;
4223         int small, large;
4224         int entries;
4225
4226         if (!latency_ns) {
4227                 *display_wm = *cursor_wm = 0;
4228                 return false;
4229         }
4230
4231         crtc = intel_get_crtc_for_plane(dev, plane);
4232         hdisplay = crtc->mode.hdisplay;
4233         htotal = crtc->mode.htotal;
4234         clock = crtc->mode.clock;
4235         pixel_size = crtc->fb->bits_per_pixel / 8;
4236
4237         line_time_us = (htotal * 1000) / clock;
4238         line_count = (latency_ns / line_time_us + 1000) / 1000;
4239         line_size = hdisplay * pixel_size;
4240
4241         /* Use the minimum of the small and large buffer method for primary */
4242         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4243         large = line_count * line_size;
4244
4245         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4246         *display_wm = entries + display->guard_size;
4247
4248         /* calculate the self-refresh watermark for display cursor */
4249         entries = line_count * pixel_size * 64;
4250         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4251         *cursor_wm = entries + cursor->guard_size;
4252
4253         return g4x_check_srwm(dev,
4254                               *display_wm, *cursor_wm,
4255                               display, cursor);
4256 }
4257
4258 static bool vlv_compute_drain_latency(struct drm_device *dev,
4259                                      int plane,
4260                                      int *plane_prec_mult,
4261                                      int *plane_dl,
4262                                      int *cursor_prec_mult,
4263                                      int *cursor_dl)
4264 {
4265         struct drm_crtc *crtc;
4266         int clock, pixel_size;
4267         int entries;
4268
4269         crtc = intel_get_crtc_for_plane(dev, plane);
4270         if (crtc->fb == NULL || !crtc->enabled)
4271                 return false;
4272
4273         clock = crtc->mode.clock;       /* VESA DOT Clock */
4274         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
4275
4276         entries = (clock / 1000) * pixel_size;
4277         *plane_prec_mult = (entries > 256) ?
4278                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4279         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
4280                                                      pixel_size);
4281
4282         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
4283         *cursor_prec_mult = (entries > 256) ?
4284                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4285         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
4286
4287         return true;
4288 }
4289
4290 /*
4291  * Update drain latency registers of memory arbiter
4292  *
4293  * Valleyview SoC has a new memory arbiter and needs drain latency registers
4294  * to be programmed. Each plane has a drain latency multiplier and a drain
4295  * latency value.
4296  */
4297
4298 static void vlv_update_drain_latency(struct drm_device *dev)
4299 {
4300         struct drm_i915_private *dev_priv = dev->dev_private;
4301         int planea_prec, planea_dl, planeb_prec, planeb_dl;
4302         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
4303         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
4304                                                         either 16 or 32 */
4305
4306         /* For plane A, Cursor A */
4307         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
4308                                       &cursor_prec_mult, &cursora_dl)) {
4309                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4310                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
4311                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4312                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
4313
4314                 I915_WRITE(VLV_DDL1, cursora_prec |
4315                                 (cursora_dl << DDL_CURSORA_SHIFT) |
4316                                 planea_prec | planea_dl);
4317         }
4318
4319         /* For plane B, Cursor B */
4320         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
4321                                       &cursor_prec_mult, &cursorb_dl)) {
4322                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4323                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
4324                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4325                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
4326
4327                 I915_WRITE(VLV_DDL2, cursorb_prec |
4328                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
4329                                 planeb_prec | planeb_dl);
4330         }
4331 }
4332
4333 #define single_plane_enabled(mask) is_power_of_2(mask)
4334
4335 static void valleyview_update_wm(struct drm_device *dev)
4336 {
4337         static const int sr_latency_ns = 12000;
4338         struct drm_i915_private *dev_priv = dev->dev_private;
4339         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4340         int plane_sr, cursor_sr;
4341         unsigned int enabled = 0;
4342
4343         vlv_update_drain_latency(dev);
4344
4345         if (g4x_compute_wm0(dev, 0,
4346                             &valleyview_wm_info, latency_ns,
4347                             &valleyview_cursor_wm_info, latency_ns,
4348                             &planea_wm, &cursora_wm))
4349                 enabled |= 1;
4350
4351         if (g4x_compute_wm0(dev, 1,
4352                             &valleyview_wm_info, latency_ns,
4353                             &valleyview_cursor_wm_info, latency_ns,
4354                             &planeb_wm, &cursorb_wm))
4355                 enabled |= 2;
4356
4357         plane_sr = cursor_sr = 0;
4358         if (single_plane_enabled(enabled) &&
4359             g4x_compute_srwm(dev, ffs(enabled) - 1,
4360                              sr_latency_ns,
4361                              &valleyview_wm_info,
4362                              &valleyview_cursor_wm_info,
4363                              &plane_sr, &cursor_sr))
4364                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
4365         else
4366                 I915_WRITE(FW_BLC_SELF_VLV,
4367                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
4368
4369         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4370                       planea_wm, cursora_wm,
4371                       planeb_wm, cursorb_wm,
4372                       plane_sr, cursor_sr);
4373
4374         I915_WRITE(DSPFW1,
4375                    (plane_sr << DSPFW_SR_SHIFT) |
4376                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4377                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4378                    planea_wm);
4379         I915_WRITE(DSPFW2,
4380                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4381                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4382         I915_WRITE(DSPFW3,
4383                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
4384 }
4385
4386 static void g4x_update_wm(struct drm_device *dev)
4387 {
4388         static const int sr_latency_ns = 12000;
4389         struct drm_i915_private *dev_priv = dev->dev_private;
4390         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4391         int plane_sr, cursor_sr;
4392         unsigned int enabled = 0;
4393
4394         if (g4x_compute_wm0(dev, 0,
4395                             &g4x_wm_info, latency_ns,
4396                             &g4x_cursor_wm_info, latency_ns,
4397                             &planea_wm, &cursora_wm))
4398                 enabled |= 1;
4399
4400         if (g4x_compute_wm0(dev, 1,
4401                             &g4x_wm_info, latency_ns,
4402                             &g4x_cursor_wm_info, latency_ns,
4403                             &planeb_wm, &cursorb_wm))
4404                 enabled |= 2;
4405
4406         plane_sr = cursor_sr = 0;
4407         if (single_plane_enabled(enabled) &&
4408             g4x_compute_srwm(dev, ffs(enabled) - 1,
4409                              sr_latency_ns,
4410                              &g4x_wm_info,
4411                              &g4x_cursor_wm_info,
4412                              &plane_sr, &cursor_sr))
4413                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4414         else
4415                 I915_WRITE(FW_BLC_SELF,
4416                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4417
4418         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4419                       planea_wm, cursora_wm,
4420                       planeb_wm, cursorb_wm,
4421                       plane_sr, cursor_sr);
4422
4423         I915_WRITE(DSPFW1,
4424                    (plane_sr << DSPFW_SR_SHIFT) |
4425                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4426                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4427                    planea_wm);
4428         I915_WRITE(DSPFW2,
4429                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4430                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4431         /* HPLL off in SR has some issues on G4x... disable it */
4432         I915_WRITE(DSPFW3,
4433                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4434                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4435 }
4436
4437 static void i965_update_wm(struct drm_device *dev)
4438 {
4439         struct drm_i915_private *dev_priv = dev->dev_private;
4440         struct drm_crtc *crtc;
4441         int srwm = 1;
4442         int cursor_sr = 16;
4443
4444         /* Calc sr entries for one plane configs */
4445         crtc = single_enabled_crtc(dev);
4446         if (crtc) {
4447                 /* self-refresh has much higher latency */
4448                 static const int sr_latency_ns = 12000;
4449                 int clock = crtc->mode.clock;
4450                 int htotal = crtc->mode.htotal;
4451                 int hdisplay = crtc->mode.hdisplay;
4452                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4453                 unsigned long line_time_us;
4454                 int entries;
4455
4456                 line_time_us = ((htotal * 1000) / clock);
4457
4458                 /* Use ns/us then divide to preserve precision */
4459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4460                         pixel_size * hdisplay;
4461                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4462                 srwm = I965_FIFO_SIZE - entries;
4463                 if (srwm < 0)
4464                         srwm = 1;
4465                 srwm &= 0x1ff;
4466                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4467                               entries, srwm);
4468
4469                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4470                         pixel_size * 64;
4471                 entries = DIV_ROUND_UP(entries,
4472                                           i965_cursor_wm_info.cacheline_size);
4473                 cursor_sr = i965_cursor_wm_info.fifo_size -
4474                         (entries + i965_cursor_wm_info.guard_size);
4475
4476                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4477                         cursor_sr = i965_cursor_wm_info.max_wm;
4478
4479                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4480                               "cursor %d\n", srwm, cursor_sr);
4481
4482                 if (IS_CRESTLINE(dev))
4483                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4484         } else {
4485                 /* Turn off self refresh if both pipes are enabled */
4486                 if (IS_CRESTLINE(dev))
4487                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4488                                    & ~FW_BLC_SELF_EN);
4489         }
4490
4491         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4492                       srwm);
4493
4494         /* 965 has limitations... */
4495         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4496                    (8 << 16) | (8 << 8) | (8 << 0));
4497         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4498         /* update cursor SR watermark */
4499         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4500 }
4501
4502 static void i9xx_update_wm(struct drm_device *dev)
4503 {
4504         struct drm_i915_private *dev_priv = dev->dev_private;
4505         const struct intel_watermark_params *wm_info;
4506         uint32_t fwater_lo;
4507         uint32_t fwater_hi;
4508         int cwm, srwm = 1;
4509         int fifo_size;
4510         int planea_wm, planeb_wm;
4511         struct drm_crtc *crtc, *enabled = NULL;
4512
4513         if (IS_I945GM(dev))
4514                 wm_info = &i945_wm_info;
4515         else if (!IS_GEN2(dev))
4516                 wm_info = &i915_wm_info;
4517         else
4518                 wm_info = &i855_wm_info;
4519
4520         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4521         crtc = intel_get_crtc_for_plane(dev, 0);
4522         if (crtc->enabled && crtc->fb) {
4523                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4524                                                wm_info, fifo_size,
4525                                                crtc->fb->bits_per_pixel / 8,
4526                                                latency_ns);
4527                 enabled = crtc;
4528         } else
4529                 planea_wm = fifo_size - wm_info->guard_size;
4530
4531         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4532         crtc = intel_get_crtc_for_plane(dev, 1);
4533         if (crtc->enabled && crtc->fb) {
4534                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4535                                                wm_info, fifo_size,
4536                                                crtc->fb->bits_per_pixel / 8,
4537                                                latency_ns);
4538                 if (enabled == NULL)
4539                         enabled = crtc;
4540                 else
4541                         enabled = NULL;
4542         } else
4543                 planeb_wm = fifo_size - wm_info->guard_size;
4544
4545         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4546
4547         /*
4548          * Overlay gets an aggressive default since video jitter is bad.
4549          */
4550         cwm = 2;
4551
4552         /* Play safe and disable self-refresh before adjusting watermarks. */
4553         if (IS_I945G(dev) || IS_I945GM(dev))
4554                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4555         else if (IS_I915GM(dev))
4556                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4557
4558         /* Calc sr entries for one plane configs */
4559         if (HAS_FW_BLC(dev) && enabled) {
4560                 /* self-refresh has much higher latency */
4561                 static const int sr_latency_ns = 6000;
4562                 int clock = enabled->mode.clock;
4563                 int htotal = enabled->mode.htotal;
4564                 int hdisplay = enabled->mode.hdisplay;
4565                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4566                 unsigned long line_time_us;
4567                 int entries;
4568
4569                 line_time_us = (htotal * 1000) / clock;
4570
4571                 /* Use ns/us then divide to preserve precision */
4572                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4573                         pixel_size * hdisplay;
4574                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4575                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4576                 srwm = wm_info->fifo_size - entries;
4577                 if (srwm < 0)
4578                         srwm = 1;
4579
4580                 if (IS_I945G(dev) || IS_I945GM(dev))
4581                         I915_WRITE(FW_BLC_SELF,
4582                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4583                 else if (IS_I915GM(dev))
4584                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4585         }
4586
4587         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4588                       planea_wm, planeb_wm, cwm, srwm);
4589
4590         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4591         fwater_hi = (cwm & 0x1f);
4592
4593         /* Set request length to 8 cachelines per fetch */
4594         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4595         fwater_hi = fwater_hi | (1 << 8);
4596
4597         I915_WRITE(FW_BLC, fwater_lo);
4598         I915_WRITE(FW_BLC2, fwater_hi);
4599
4600         if (HAS_FW_BLC(dev)) {
4601                 if (enabled) {
4602                         if (IS_I945G(dev) || IS_I945GM(dev))
4603                                 I915_WRITE(FW_BLC_SELF,
4604                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4605                         else if (IS_I915GM(dev))
4606                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4607                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4608                 } else
4609                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4610         }
4611 }
4612
4613 static void i830_update_wm(struct drm_device *dev)
4614 {
4615         struct drm_i915_private *dev_priv = dev->dev_private;
4616         struct drm_crtc *crtc;
4617         uint32_t fwater_lo;
4618         int planea_wm;
4619
4620         crtc = single_enabled_crtc(dev);
4621         if (crtc == NULL)
4622                 return;
4623
4624         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4625                                        dev_priv->display.get_fifo_size(dev, 0),
4626                                        crtc->fb->bits_per_pixel / 8,
4627                                        latency_ns);
4628         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4629         fwater_lo |= (3<<8) | planea_wm;
4630
4631         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4632
4633         I915_WRITE(FW_BLC, fwater_lo);
4634 }
4635
4636 #define ILK_LP0_PLANE_LATENCY           700
4637 #define ILK_LP0_CURSOR_LATENCY          1300
4638
4639 /*
4640  * Check the wm result.
4641  *
4642  * If any calculated watermark values is larger than the maximum value that
4643  * can be programmed into the associated watermark register, that watermark
4644  * must be disabled.
4645  */
4646 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4647                                 int fbc_wm, int display_wm, int cursor_wm,
4648                                 const struct intel_watermark_params *display,
4649                                 const struct intel_watermark_params *cursor)
4650 {
4651         struct drm_i915_private *dev_priv = dev->dev_private;
4652
4653         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4654                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4655
4656         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4657                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4658                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4659
4660                 /* fbc has it's own way to disable FBC WM */
4661                 I915_WRITE(DISP_ARB_CTL,
4662                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4663                 return false;
4664         }
4665
4666         if (display_wm > display->max_wm) {
4667                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4668                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4669                 return false;
4670         }
4671
4672         if (cursor_wm > cursor->max_wm) {
4673                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4674                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4675                 return false;
4676         }
4677
4678         if (!(fbc_wm || display_wm || cursor_wm)) {
4679                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4680                 return false;
4681         }
4682
4683         return true;
4684 }
4685
4686 /*
4687  * Compute watermark values of WM[1-3],
4688  */
4689 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4690                                   int latency_ns,
4691                                   const struct intel_watermark_params *display,
4692                                   const struct intel_watermark_params *cursor,
4693                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4694 {
4695         struct drm_crtc *crtc;
4696         unsigned long line_time_us;
4697         int hdisplay, htotal, pixel_size, clock;
4698         int line_count, line_size;
4699         int small, large;
4700         int entries;
4701
4702         if (!latency_ns) {
4703                 *fbc_wm = *display_wm = *cursor_wm = 0;
4704                 return false;
4705         }
4706
4707         crtc = intel_get_crtc_for_plane(dev, plane);
4708         hdisplay = crtc->mode.hdisplay;
4709         htotal = crtc->mode.htotal;
4710         clock = crtc->mode.clock;
4711         pixel_size = crtc->fb->bits_per_pixel / 8;
4712
4713         line_time_us = (htotal * 1000) / clock;
4714         line_count = (latency_ns / line_time_us + 1000) / 1000;
4715         line_size = hdisplay * pixel_size;
4716
4717         /* Use the minimum of the small and large buffer method for primary */
4718         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4719         large = line_count * line_size;
4720
4721         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4722         *display_wm = entries + display->guard_size;
4723
4724         /*
4725          * Spec says:
4726          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4727          */
4728         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4729
4730         /* calculate the self-refresh watermark for display cursor */
4731         entries = line_count * pixel_size * 64;
4732         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4733         *cursor_wm = entries + cursor->guard_size;
4734
4735         return ironlake_check_srwm(dev, level,
4736                                    *fbc_wm, *display_wm, *cursor_wm,
4737                                    display, cursor);
4738 }
4739
4740 static void ironlake_update_wm(struct drm_device *dev)
4741 {
4742         struct drm_i915_private *dev_priv = dev->dev_private;
4743         int fbc_wm, plane_wm, cursor_wm;
4744         unsigned int enabled;
4745
4746         enabled = 0;
4747         if (g4x_compute_wm0(dev, 0,
4748                             &ironlake_display_wm_info,
4749                             ILK_LP0_PLANE_LATENCY,
4750                             &ironlake_cursor_wm_info,
4751                             ILK_LP0_CURSOR_LATENCY,
4752                             &plane_wm, &cursor_wm)) {
4753                 I915_WRITE(WM0_PIPEA_ILK,
4754                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4755                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4756                               " plane %d, " "cursor: %d\n",
4757                               plane_wm, cursor_wm);
4758                 enabled |= 1;
4759         }
4760
4761         if (g4x_compute_wm0(dev, 1,
4762                             &ironlake_display_wm_info,
4763                             ILK_LP0_PLANE_LATENCY,
4764                             &ironlake_cursor_wm_info,
4765                             ILK_LP0_CURSOR_LATENCY,
4766                             &plane_wm, &cursor_wm)) {
4767                 I915_WRITE(WM0_PIPEB_ILK,
4768                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4769                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4770                               " plane %d, cursor: %d\n",
4771                               plane_wm, cursor_wm);
4772                 enabled |= 2;
4773         }
4774
4775         /*
4776          * Calculate and update the self-refresh watermark only when one
4777          * display plane is used.
4778          */
4779         I915_WRITE(WM3_LP_ILK, 0);
4780         I915_WRITE(WM2_LP_ILK, 0);
4781         I915_WRITE(WM1_LP_ILK, 0);
4782
4783         if (!single_plane_enabled(enabled))
4784                 return;
4785         enabled = ffs(enabled) - 1;
4786
4787         /* WM1 */
4788         if (!ironlake_compute_srwm(dev, 1, enabled,
4789                                    ILK_READ_WM1_LATENCY() * 500,
4790                                    &ironlake_display_srwm_info,
4791                                    &ironlake_cursor_srwm_info,
4792                                    &fbc_wm, &plane_wm, &cursor_wm))
4793                 return;
4794
4795         I915_WRITE(WM1_LP_ILK,
4796                    WM1_LP_SR_EN |
4797                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4798                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4799                    (plane_wm << WM1_LP_SR_SHIFT) |
4800                    cursor_wm);
4801
4802         /* WM2 */
4803         if (!ironlake_compute_srwm(dev, 2, enabled,
4804                                    ILK_READ_WM2_LATENCY() * 500,
4805                                    &ironlake_display_srwm_info,
4806                                    &ironlake_cursor_srwm_info,
4807                                    &fbc_wm, &plane_wm, &cursor_wm))
4808                 return;
4809
4810         I915_WRITE(WM2_LP_ILK,
4811                    WM2_LP_EN |
4812                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4813                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4814                    (plane_wm << WM1_LP_SR_SHIFT) |
4815                    cursor_wm);
4816
4817         /*
4818          * WM3 is unsupported on ILK, probably because we don't have latency
4819          * data for that power state
4820          */
4821 }
4822
4823 void sandybridge_update_wm(struct drm_device *dev)
4824 {
4825         struct drm_i915_private *dev_priv = dev->dev_private;
4826         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4827         u32 val;
4828         int fbc_wm, plane_wm, cursor_wm;
4829         unsigned int enabled;
4830
4831         enabled = 0;
4832         if (g4x_compute_wm0(dev, 0,
4833                             &sandybridge_display_wm_info, latency,
4834                             &sandybridge_cursor_wm_info, latency,
4835                             &plane_wm, &cursor_wm)) {
4836                 val = I915_READ(WM0_PIPEA_ILK);
4837                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4838                 I915_WRITE(WM0_PIPEA_ILK, val |
4839                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4840                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4841                               " plane %d, " "cursor: %d\n",
4842                               plane_wm, cursor_wm);
4843                 enabled |= 1;
4844         }
4845
4846         if (g4x_compute_wm0(dev, 1,
4847                             &sandybridge_display_wm_info, latency,
4848                             &sandybridge_cursor_wm_info, latency,
4849                             &plane_wm, &cursor_wm)) {
4850                 val = I915_READ(WM0_PIPEB_ILK);
4851                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4852                 I915_WRITE(WM0_PIPEB_ILK, val |
4853                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4854                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4855                               " plane %d, cursor: %d\n",
4856                               plane_wm, cursor_wm);
4857                 enabled |= 2;
4858         }
4859
4860         /* IVB has 3 pipes */
4861         if (IS_IVYBRIDGE(dev) &&
4862             g4x_compute_wm0(dev, 2,
4863                             &sandybridge_display_wm_info, latency,
4864                             &sandybridge_cursor_wm_info, latency,
4865                             &plane_wm, &cursor_wm)) {
4866                 val = I915_READ(WM0_PIPEC_IVB);
4867                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4868                 I915_WRITE(WM0_PIPEC_IVB, val |
4869                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4870                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4871                               " plane %d, cursor: %d\n",
4872                               plane_wm, cursor_wm);
4873                 enabled |= 3;
4874         }
4875
4876         /*
4877          * Calculate and update the self-refresh watermark only when one
4878          * display plane is used.
4879          *
4880          * SNB support 3 levels of watermark.
4881          *
4882          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4883          * and disabled in the descending order
4884          *
4885          */
4886         I915_WRITE(WM3_LP_ILK, 0);
4887         I915_WRITE(WM2_LP_ILK, 0);
4888         I915_WRITE(WM1_LP_ILK, 0);
4889
4890         if (!single_plane_enabled(enabled) ||
4891             dev_priv->sprite_scaling_enabled)
4892                 return;
4893         enabled = ffs(enabled) - 1;
4894
4895         /* WM1 */
4896         if (!ironlake_compute_srwm(dev, 1, enabled,
4897                                    SNB_READ_WM1_LATENCY() * 500,
4898                                    &sandybridge_display_srwm_info,
4899                                    &sandybridge_cursor_srwm_info,
4900                                    &fbc_wm, &plane_wm, &cursor_wm))
4901                 return;
4902
4903         I915_WRITE(WM1_LP_ILK,
4904                    WM1_LP_SR_EN |
4905                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4906                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4907                    (plane_wm << WM1_LP_SR_SHIFT) |
4908                    cursor_wm);
4909
4910         /* WM2 */
4911         if (!ironlake_compute_srwm(dev, 2, enabled,
4912                                    SNB_READ_WM2_LATENCY() * 500,
4913                                    &sandybridge_display_srwm_info,
4914                                    &sandybridge_cursor_srwm_info,
4915                                    &fbc_wm, &plane_wm, &cursor_wm))
4916                 return;
4917
4918         I915_WRITE(WM2_LP_ILK,
4919                    WM2_LP_EN |
4920                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4921                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4922                    (plane_wm << WM1_LP_SR_SHIFT) |
4923                    cursor_wm);
4924
4925         /* WM3 */
4926         if (!ironlake_compute_srwm(dev, 3, enabled,
4927                                    SNB_READ_WM3_LATENCY() * 500,
4928                                    &sandybridge_display_srwm_info,
4929                                    &sandybridge_cursor_srwm_info,
4930                                    &fbc_wm, &plane_wm, &cursor_wm))
4931                 return;
4932
4933         I915_WRITE(WM3_LP_ILK,
4934                    WM3_LP_EN |
4935                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4936                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4937                    (plane_wm << WM1_LP_SR_SHIFT) |
4938                    cursor_wm);
4939 }
4940
4941 static bool
4942 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4943                               uint32_t sprite_width, int pixel_size,
4944                               const struct intel_watermark_params *display,
4945                               int display_latency_ns, int *sprite_wm)
4946 {
4947         struct drm_crtc *crtc;
4948         int clock;
4949         int entries, tlb_miss;
4950
4951         crtc = intel_get_crtc_for_plane(dev, plane);
4952         if (crtc->fb == NULL || !crtc->enabled) {
4953                 *sprite_wm = display->guard_size;
4954                 return false;
4955         }
4956
4957         clock = crtc->mode.clock;
4958
4959         /* Use the small buffer method to calculate the sprite watermark */
4960         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4961         tlb_miss = display->fifo_size*display->cacheline_size -
4962                 sprite_width * 8;
4963         if (tlb_miss > 0)
4964                 entries += tlb_miss;
4965         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4966         *sprite_wm = entries + display->guard_size;
4967         if (*sprite_wm > (int)display->max_wm)
4968                 *sprite_wm = display->max_wm;
4969
4970         return true;
4971 }
4972
4973 static bool
4974 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4975                                 uint32_t sprite_width, int pixel_size,
4976                                 const struct intel_watermark_params *display,
4977                                 int latency_ns, int *sprite_wm)
4978 {
4979         struct drm_crtc *crtc;
4980         unsigned long line_time_us;
4981         int clock;
4982         int line_count, line_size;
4983         int small, large;
4984         int entries;
4985
4986         if (!latency_ns) {
4987                 *sprite_wm = 0;
4988                 return false;
4989         }
4990
4991         crtc = intel_get_crtc_for_plane(dev, plane);
4992         clock = crtc->mode.clock;
4993         if (!clock) {
4994                 *sprite_wm = 0;
4995                 return false;
4996         }
4997
4998         line_time_us = (sprite_width * 1000) / clock;
4999         if (!line_time_us) {
5000                 *sprite_wm = 0;
5001                 return false;
5002         }
5003
5004         line_count = (latency_ns / line_time_us + 1000) / 1000;
5005         line_size = sprite_width * pixel_size;
5006
5007         /* Use the minimum of the small and large buffer method for primary */
5008         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
5009         large = line_count * line_size;
5010
5011         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
5012         *sprite_wm = entries + display->guard_size;
5013
5014         return *sprite_wm > 0x3ff ? false : true;
5015 }
5016
5017 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
5018                                          uint32_t sprite_width, int pixel_size)
5019 {
5020         struct drm_i915_private *dev_priv = dev->dev_private;
5021         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
5022         u32 val;
5023         int sprite_wm, reg;
5024         int ret;
5025
5026         switch (pipe) {
5027         case 0:
5028                 reg = WM0_PIPEA_ILK;
5029                 break;
5030         case 1:
5031                 reg = WM0_PIPEB_ILK;
5032                 break;
5033         case 2:
5034                 reg = WM0_PIPEC_IVB;
5035                 break;
5036         default:
5037                 return; /* bad pipe */
5038         }
5039
5040         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
5041                                             &sandybridge_display_wm_info,
5042                                             latency, &sprite_wm);
5043         if (!ret) {
5044                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
5045                               pipe);
5046                 return;
5047         }
5048
5049         val = I915_READ(reg);
5050         val &= ~WM0_PIPE_SPRITE_MASK;
5051         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
5052         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
5053
5054
5055         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5056                                               pixel_size,
5057                                               &sandybridge_display_srwm_info,
5058                                               SNB_READ_WM1_LATENCY() * 500,
5059                                               &sprite_wm);
5060         if (!ret) {
5061                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
5062                               pipe);
5063                 return;
5064         }
5065         I915_WRITE(WM1S_LP_ILK, sprite_wm);
5066
5067         /* Only IVB has two more LP watermarks for sprite */
5068         if (!IS_IVYBRIDGE(dev))
5069                 return;
5070
5071         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5072                                               pixel_size,
5073                                               &sandybridge_display_srwm_info,
5074                                               SNB_READ_WM2_LATENCY() * 500,
5075                                               &sprite_wm);
5076         if (!ret) {
5077                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
5078                               pipe);
5079                 return;
5080         }
5081         I915_WRITE(WM2S_LP_IVB, sprite_wm);
5082
5083         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5084                                               pixel_size,
5085                                               &sandybridge_display_srwm_info,
5086                                               SNB_READ_WM3_LATENCY() * 500,
5087                                               &sprite_wm);
5088         if (!ret) {
5089                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
5090                               pipe);
5091                 return;
5092         }
5093         I915_WRITE(WM3S_LP_IVB, sprite_wm);
5094 }
5095
5096 /**
5097  * intel_update_watermarks - update FIFO watermark values based on current modes
5098  *
5099  * Calculate watermark values for the various WM regs based on current mode
5100  * and plane configuration.
5101  *
5102  * There are several cases to deal with here:
5103  *   - normal (i.e. non-self-refresh)
5104  *   - self-refresh (SR) mode
5105  *   - lines are large relative to FIFO size (buffer can hold up to 2)
5106  *   - lines are small relative to FIFO size (buffer can hold more than 2
5107  *     lines), so need to account for TLB latency
5108  *
5109  *   The normal calculation is:
5110  *     watermark = dotclock * bytes per pixel * latency
5111  *   where latency is platform & configuration dependent (we assume pessimal
5112  *   values here).
5113  *
5114  *   The SR calculation is:
5115  *     watermark = (trunc(latency/line time)+1) * surface width *
5116  *       bytes per pixel
5117  *   where
5118  *     line time = htotal / dotclock
5119  *     surface width = hdisplay for normal plane and 64 for cursor
5120  *   and latency is assumed to be high, as above.
5121  *
5122  * The final value programmed to the register should always be rounded up,
5123  * and include an extra 2 entries to account for clock crossings.
5124  *
5125  * We don't use the sprite, so we can ignore that.  And on Crestline we have
5126  * to set the non-SR watermarks to 8.
5127  */
5128 static void intel_update_watermarks(struct drm_device *dev)
5129 {
5130         struct drm_i915_private *dev_priv = dev->dev_private;
5131
5132         if (dev_priv->display.update_wm)
5133                 dev_priv->display.update_wm(dev);
5134 }
5135
5136 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
5137                                     uint32_t sprite_width, int pixel_size)
5138 {
5139         struct drm_i915_private *dev_priv = dev->dev_private;
5140
5141         if (dev_priv->display.update_sprite_wm)
5142                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
5143                                                    pixel_size);
5144 }
5145
5146 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5147 {
5148         if (i915_panel_use_ssc >= 0)
5149                 return i915_panel_use_ssc != 0;
5150         return dev_priv->lvds_use_ssc
5151                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5152 }
5153
5154 /**
5155  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
5156  * @crtc: CRTC structure
5157  * @mode: requested mode
5158  *
5159  * A pipe may be connected to one or more outputs.  Based on the depth of the
5160  * attached framebuffer, choose a good color depth to use on the pipe.
5161  *
5162  * If possible, match the pipe depth to the fb depth.  In some cases, this
5163  * isn't ideal, because the connected output supports a lesser or restricted
5164  * set of depths.  Resolve that here:
5165  *    LVDS typically supports only 6bpc, so clamp down in that case
5166  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
5167  *    Displays may support a restricted set as well, check EDID and clamp as
5168  *      appropriate.
5169  *    DP may want to dither down to 6bpc to fit larger modes
5170  *
5171  * RETURNS:
5172  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
5173  * true if they don't match).
5174  */
5175 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
5176                                          unsigned int *pipe_bpp,
5177                                          struct drm_display_mode *mode)
5178 {
5179         struct drm_device *dev = crtc->dev;
5180         struct drm_i915_private *dev_priv = dev->dev_private;
5181         struct drm_encoder *encoder;
5182         struct drm_connector *connector;
5183         unsigned int display_bpc = UINT_MAX, bpc;
5184
5185         /* Walk the encoders & connectors on this crtc, get min bpc */
5186         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5187                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5188
5189                 if (encoder->crtc != crtc)
5190                         continue;
5191
5192                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5193                         unsigned int lvds_bpc;
5194
5195                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5196                             LVDS_A3_POWER_UP)
5197                                 lvds_bpc = 8;
5198                         else
5199                                 lvds_bpc = 6;
5200
5201                         if (lvds_bpc < display_bpc) {
5202                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5203                                 display_bpc = lvds_bpc;
5204                         }
5205                         continue;
5206                 }
5207
5208                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5209                         /* Use VBT settings if we have an eDP panel */
5210                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5211
5212                         if (edp_bpc < display_bpc) {
5213                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5214                                 display_bpc = edp_bpc;
5215                         }
5216                         continue;
5217                 }
5218
5219                 /* Not one of the known troublemakers, check the EDID */
5220                 list_for_each_entry(connector, &dev->mode_config.connector_list,
5221                                     head) {
5222                         if (connector->encoder != encoder)
5223                                 continue;
5224
5225                         /* Don't use an invalid EDID bpc value */
5226                         if (connector->display_info.bpc &&
5227                             connector->display_info.bpc < display_bpc) {
5228                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5229                                 display_bpc = connector->display_info.bpc;
5230                         }
5231                 }
5232
5233                 /*
5234                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5235                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5236                  */
5237                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5238                         if (display_bpc > 8 && display_bpc < 12) {
5239                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5240                                 display_bpc = 12;
5241                         } else {
5242                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5243                                 display_bpc = 8;
5244                         }
5245                 }
5246         }
5247
5248         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5249                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5250                 display_bpc = 6;
5251         }
5252
5253         /*
5254          * We could just drive the pipe at the highest bpc all the time and
5255          * enable dithering as needed, but that costs bandwidth.  So choose
5256          * the minimum value that expresses the full color range of the fb but
5257          * also stays within the max display bpc discovered above.
5258          */
5259
5260         switch (crtc->fb->depth) {
5261         case 8:
5262                 bpc = 8; /* since we go through a colormap */
5263                 break;
5264         case 15:
5265         case 16:
5266                 bpc = 6; /* min is 18bpp */
5267                 break;
5268         case 24:
5269                 bpc = 8;
5270                 break;
5271         case 30:
5272                 bpc = 10;
5273                 break;
5274         case 48:
5275                 bpc = 12;
5276                 break;
5277         default:
5278                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5279                 bpc = min((unsigned int)8, display_bpc);
5280                 break;
5281         }
5282
5283         display_bpc = min(display_bpc, bpc);
5284
5285         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5286                       bpc, display_bpc);
5287
5288         *pipe_bpp = display_bpc * 3;
5289
5290         return display_bpc != bpc;
5291 }
5292
5293 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5294 {
5295         struct drm_device *dev = crtc->dev;
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297         int refclk;
5298
5299         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5300             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5301                 refclk = dev_priv->lvds_ssc_freq * 1000;
5302                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5303                               refclk / 1000);
5304         } else if (!IS_GEN2(dev)) {
5305                 refclk = 96000;
5306         } else {
5307                 refclk = 48000;
5308         }
5309
5310         return refclk;
5311 }
5312
5313 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5314                                       intel_clock_t *clock)
5315 {
5316         /* SDVO TV has fixed PLL values depend on its clock range,
5317            this mirrors vbios setting. */
5318         if (adjusted_mode->clock >= 100000
5319             && adjusted_mode->clock < 140500) {
5320                 clock->p1 = 2;
5321                 clock->p2 = 10;
5322                 clock->n = 3;
5323                 clock->m1 = 16;
5324                 clock->m2 = 8;
5325         } else if (adjusted_mode->clock >= 140500
5326                    && adjusted_mode->clock <= 200000) {
5327                 clock->p1 = 1;
5328                 clock->p2 = 10;
5329                 clock->n = 6;
5330                 clock->m1 = 12;
5331                 clock->m2 = 8;
5332         }
5333 }
5334
5335 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5336                                      intel_clock_t *clock,
5337                                      intel_clock_t *reduced_clock)
5338 {
5339         struct drm_device *dev = crtc->dev;
5340         struct drm_i915_private *dev_priv = dev->dev_private;
5341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5342         int pipe = intel_crtc->pipe;
5343         u32 fp, fp2 = 0;
5344
5345         if (IS_PINEVIEW(dev)) {
5346                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5347                 if (reduced_clock)
5348                         fp2 = (1 << reduced_clock->n) << 16 |
5349                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5350         } else {
5351                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5352                 if (reduced_clock)
5353                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5354                                 reduced_clock->m2;
5355         }
5356
5357         I915_WRITE(FP0(pipe), fp);
5358
5359         intel_crtc->lowfreq_avail = false;
5360         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5361             reduced_clock && i915_powersave) {
5362                 I915_WRITE(FP1(pipe), fp2);
5363                 intel_crtc->lowfreq_avail = true;
5364         } else {
5365                 I915_WRITE(FP1(pipe), fp);
5366         }
5367 }
5368
5369 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5370                               struct drm_display_mode *adjusted_mode)
5371 {
5372         struct drm_device *dev = crtc->dev;
5373         struct drm_i915_private *dev_priv = dev->dev_private;
5374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375         int pipe = intel_crtc->pipe;
5376         u32 temp, lvds_sync = 0;
5377
5378         temp = I915_READ(LVDS);
5379         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5380         if (pipe == 1) {
5381                 temp |= LVDS_PIPEB_SELECT;
5382         } else {
5383                 temp &= ~LVDS_PIPEB_SELECT;
5384         }
5385         /* set the corresponsding LVDS_BORDER bit */
5386         temp |= dev_priv->lvds_border_bits;
5387         /* Set the B0-B3 data pairs corresponding to whether we're going to
5388          * set the DPLLs for dual-channel mode or not.
5389          */
5390         if (clock->p2 == 7)
5391                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5392         else
5393                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5394
5395         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5396          * appropriately here, but we need to look more thoroughly into how
5397          * panels behave in the two modes.
5398          */
5399         /* set the dithering flag on LVDS as needed */
5400         if (INTEL_INFO(dev)->gen >= 4) {
5401                 if (dev_priv->lvds_dither)
5402                         temp |= LVDS_ENABLE_DITHER;
5403                 else
5404                         temp &= ~LVDS_ENABLE_DITHER;
5405         }
5406         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5407                 lvds_sync |= LVDS_HSYNC_POLARITY;
5408         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5409                 lvds_sync |= LVDS_VSYNC_POLARITY;
5410         if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5411             != lvds_sync) {
5412                 char flags[2] = "-+";
5413                 DRM_INFO("Changing LVDS panel from "
5414                          "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5415                          flags[!(temp & LVDS_HSYNC_POLARITY)],
5416                          flags[!(temp & LVDS_VSYNC_POLARITY)],
5417                          flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5418                          flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5419                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5420                 temp |= lvds_sync;
5421         }
5422         I915_WRITE(LVDS, temp);
5423 }
5424
5425 static void i9xx_update_pll(struct drm_crtc *crtc,
5426                             struct drm_display_mode *mode,
5427                             struct drm_display_mode *adjusted_mode,
5428                             intel_clock_t *clock, intel_clock_t *reduced_clock,
5429                             int num_connectors)
5430 {
5431         struct drm_device *dev = crtc->dev;
5432         struct drm_i915_private *dev_priv = dev->dev_private;
5433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5434         int pipe = intel_crtc->pipe;
5435         u32 dpll;
5436         bool is_sdvo;
5437
5438         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5439                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5440
5441         dpll = DPLL_VGA_MODE_DIS;
5442
5443         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5444                 dpll |= DPLLB_MODE_LVDS;
5445         else
5446                 dpll |= DPLLB_MODE_DAC_SERIAL;
5447         if (is_sdvo) {
5448                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5449                 if (pixel_multiplier > 1) {
5450                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5451                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5452                 }
5453                 dpll |= DPLL_DVO_HIGH_SPEED;
5454         }
5455         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5456                 dpll |= DPLL_DVO_HIGH_SPEED;
5457
5458         /* compute bitmask from p1 value */
5459         if (IS_PINEVIEW(dev))
5460                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5461         else {
5462                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5463                 if (IS_G4X(dev) && reduced_clock)
5464                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5465         }
5466         switch (clock->p2) {
5467         case 5:
5468                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5469                 break;
5470         case 7:
5471                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5472                 break;
5473         case 10:
5474                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5475                 break;
5476         case 14:
5477                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5478                 break;
5479         }
5480         if (INTEL_INFO(dev)->gen >= 4)
5481                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5482
5483         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5484                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5485         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5486                 /* XXX: just matching BIOS for now */
5487                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5488                 dpll |= 3;
5489         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5490                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5491                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5492         else
5493                 dpll |= PLL_REF_INPUT_DREFCLK;
5494
5495         dpll |= DPLL_VCO_ENABLE;
5496         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5497         POSTING_READ(DPLL(pipe));
5498         udelay(150);
5499
5500         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5501          * This is an exception to the general rule that mode_set doesn't turn
5502          * things on.
5503          */
5504         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5505                 intel_update_lvds(crtc, clock, adjusted_mode);
5506
5507         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5508                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5509
5510         I915_WRITE(DPLL(pipe), dpll);
5511
5512         /* Wait for the clocks to stabilize. */
5513         POSTING_READ(DPLL(pipe));
5514         udelay(150);
5515
5516         if (INTEL_INFO(dev)->gen >= 4) {
5517                 u32 temp = 0;
5518                 if (is_sdvo) {
5519                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5520                         if (temp > 1)
5521                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5522                         else
5523                                 temp = 0;
5524                 }
5525                 I915_WRITE(DPLL_MD(pipe), temp);
5526         } else {
5527                 /* The pixel multiplier can only be updated once the
5528                  * DPLL is enabled and the clocks are stable.
5529                  *
5530                  * So write it again.
5531                  */
5532                 I915_WRITE(DPLL(pipe), dpll);
5533         }
5534 }
5535
5536 static void i8xx_update_pll(struct drm_crtc *crtc,
5537                             struct drm_display_mode *adjusted_mode,
5538                             intel_clock_t *clock,
5539                             int num_connectors)
5540 {
5541         struct drm_device *dev = crtc->dev;
5542         struct drm_i915_private *dev_priv = dev->dev_private;
5543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5544         int pipe = intel_crtc->pipe;
5545         u32 dpll;
5546
5547         dpll = DPLL_VGA_MODE_DIS;
5548
5549         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
5550                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5551         } else {
5552                 if (clock->p1 == 2)
5553                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5554                 else
5555                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5556                 if (clock->p2 == 4)
5557                         dpll |= PLL_P2_DIVIDE_BY_4;
5558         }
5559
5560         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5561                 /* XXX: just matching BIOS for now */
5562                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5563                 dpll |= 3;
5564         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5565                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5566                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5567         else
5568                 dpll |= PLL_REF_INPUT_DREFCLK;
5569
5570         dpll |= DPLL_VCO_ENABLE;
5571         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5572         POSTING_READ(DPLL(pipe));
5573         udelay(150);
5574
5575         I915_WRITE(DPLL(pipe), dpll);
5576
5577         /* Wait for the clocks to stabilize. */
5578         POSTING_READ(DPLL(pipe));
5579         udelay(150);
5580
5581         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5582          * This is an exception to the general rule that mode_set doesn't turn
5583          * things on.
5584          */
5585         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5586                 intel_update_lvds(crtc, clock, adjusted_mode);
5587
5588         /* The pixel multiplier can only be updated once the
5589          * DPLL is enabled and the clocks are stable.
5590          *
5591          * So write it again.
5592          */
5593         I915_WRITE(DPLL(pipe), dpll);
5594 }
5595
5596 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5597                               struct drm_display_mode *mode,
5598                               struct drm_display_mode *adjusted_mode,
5599                               int x, int y,
5600                               struct drm_framebuffer *old_fb)
5601 {
5602         struct drm_device *dev = crtc->dev;
5603         struct drm_i915_private *dev_priv = dev->dev_private;
5604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5605         int pipe = intel_crtc->pipe;
5606         int plane = intel_crtc->plane;
5607         int refclk, num_connectors = 0;
5608         intel_clock_t clock, reduced_clock;
5609         u32 dspcntr, pipeconf, vsyncshift;
5610         bool ok, has_reduced_clock = false, is_sdvo = false;
5611         bool is_lvds = false, is_tv = false, is_dp = false;
5612         struct drm_mode_config *mode_config = &dev->mode_config;
5613         struct intel_encoder *encoder;
5614         const intel_limit_t *limit;
5615         int ret;
5616
5617         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5618                 if (encoder->base.crtc != crtc)
5619                         continue;
5620
5621                 switch (encoder->type) {
5622                 case INTEL_OUTPUT_LVDS:
5623                         is_lvds = true;
5624                         break;
5625                 case INTEL_OUTPUT_SDVO:
5626                 case INTEL_OUTPUT_HDMI:
5627                         is_sdvo = true;
5628                         if (encoder->needs_tv_clock)
5629                                 is_tv = true;
5630                         break;
5631                 case INTEL_OUTPUT_TVOUT:
5632                         is_tv = true;
5633                         break;
5634                 case INTEL_OUTPUT_DISPLAYPORT:
5635                         is_dp = true;
5636                         break;
5637                 }
5638
5639                 num_connectors++;
5640         }
5641
5642         refclk = i9xx_get_refclk(crtc, num_connectors);
5643
5644         /*
5645          * Returns a set of divisors for the desired target clock with the given
5646          * refclk, or FALSE.  The returned values represent the clock equation:
5647          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5648          */
5649         limit = intel_limit(crtc, refclk);
5650         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5651                              &clock);
5652         if (!ok) {
5653                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5654                 return -EINVAL;
5655         }
5656
5657         /* Ensure that the cursor is valid for the new mode before changing... */
5658         intel_crtc_update_cursor(crtc, true);
5659
5660         if (is_lvds && dev_priv->lvds_downclock_avail) {
5661                 /*
5662                  * Ensure we match the reduced clock's P to the target clock.
5663                  * If the clocks don't match, we can't switch the display clock
5664                  * by using the FP0/FP1. In such case we will disable the LVDS
5665                  * downclock feature.
5666                 */
5667                 has_reduced_clock = limit->find_pll(limit, crtc,
5668                                                     dev_priv->lvds_downclock,
5669                                                     refclk,
5670                                                     &clock,
5671                                                     &reduced_clock);
5672         }
5673
5674         if (is_sdvo && is_tv)
5675                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5676
5677         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5678                                  &reduced_clock : NULL);
5679
5680         if (IS_GEN2(dev))
5681                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
5682         else
5683                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
5684                                 has_reduced_clock ? &reduced_clock : NULL,
5685                                 num_connectors);
5686
5687         /* setup pipeconf */
5688         pipeconf = I915_READ(PIPECONF(pipe));
5689
5690         /* Set up the display plane register */
5691         dspcntr = DISPPLANE_GAMMA_ENABLE;
5692
5693         if (pipe == 0)
5694                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5695         else
5696                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5697
5698         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5699                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5700                  * core speed.
5701                  *
5702                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5703                  * pipe == 0 check?
5704                  */
5705                 if (mode->clock >
5706                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5707                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5708                 else
5709                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5710         }
5711
5712         /* default to 8bpc */
5713         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5714         if (is_dp) {
5715                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5716                         pipeconf |= PIPECONF_BPP_6 |
5717                                     PIPECONF_DITHER_EN |
5718                                     PIPECONF_DITHER_TYPE_SP;
5719                 }
5720         }
5721
5722         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5723         drm_mode_debug_printmodeline(mode);
5724
5725         if (HAS_PIPE_CXSR(dev)) {
5726                 if (intel_crtc->lowfreq_avail) {
5727                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5728                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5729                 } else {
5730                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5731                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5732                 }
5733         }
5734
5735         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5736         if (!IS_GEN2(dev) &&
5737             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5738                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5739                 /* the chip adds 2 halflines automatically */
5740                 adjusted_mode->crtc_vtotal -= 1;
5741                 adjusted_mode->crtc_vblank_end -= 1;
5742                 vsyncshift = adjusted_mode->crtc_hsync_start
5743                              - adjusted_mode->crtc_htotal/2;
5744         } else {
5745                 pipeconf |= PIPECONF_PROGRESSIVE;
5746                 vsyncshift = 0;
5747         }
5748
5749         if (!IS_GEN3(dev))
5750                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5751
5752         I915_WRITE(HTOTAL(pipe),
5753                    (adjusted_mode->crtc_hdisplay - 1) |
5754                    ((adjusted_mode->crtc_htotal - 1) << 16));
5755         I915_WRITE(HBLANK(pipe),
5756                    (adjusted_mode->crtc_hblank_start - 1) |
5757                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5758         I915_WRITE(HSYNC(pipe),
5759                    (adjusted_mode->crtc_hsync_start - 1) |
5760                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5761
5762         I915_WRITE(VTOTAL(pipe),
5763                    (adjusted_mode->crtc_vdisplay - 1) |
5764                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5765         I915_WRITE(VBLANK(pipe),
5766                    (adjusted_mode->crtc_vblank_start - 1) |
5767                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5768         I915_WRITE(VSYNC(pipe),
5769                    (adjusted_mode->crtc_vsync_start - 1) |
5770                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5771
5772         /* pipesrc and dspsize control the size that is scaled from,
5773          * which should always be the user's requested size.
5774          */
5775         I915_WRITE(DSPSIZE(plane),
5776                    ((mode->vdisplay - 1) << 16) |
5777                    (mode->hdisplay - 1));
5778         I915_WRITE(DSPPOS(plane), 0);
5779         I915_WRITE(PIPESRC(pipe),
5780                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5781
5782         I915_WRITE(PIPECONF(pipe), pipeconf);
5783         POSTING_READ(PIPECONF(pipe));
5784         intel_enable_pipe(dev_priv, pipe, false);
5785
5786         intel_wait_for_vblank(dev, pipe);
5787
5788         I915_WRITE(DSPCNTR(plane), dspcntr);
5789         POSTING_READ(DSPCNTR(plane));
5790         intel_enable_plane(dev_priv, plane, pipe);
5791
5792         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5793
5794         intel_update_watermarks(dev);
5795
5796         return ret;
5797 }
5798
5799 /*
5800  * Initialize reference clocks when the driver loads
5801  */
5802 void ironlake_init_pch_refclk(struct drm_device *dev)
5803 {
5804         struct drm_i915_private *dev_priv = dev->dev_private;
5805         struct drm_mode_config *mode_config = &dev->mode_config;
5806         struct intel_encoder *encoder;
5807         u32 temp;
5808         bool has_lvds = false;
5809         bool has_cpu_edp = false;
5810         bool has_pch_edp = false;
5811         bool has_panel = false;
5812         bool has_ck505 = false;
5813         bool can_ssc = false;
5814
5815         /* We need to take the global config into account */
5816         list_for_each_entry(encoder, &mode_config->encoder_list,
5817                             base.head) {
5818                 switch (encoder->type) {
5819                 case INTEL_OUTPUT_LVDS:
5820                         has_panel = true;
5821                         has_lvds = true;
5822                         break;
5823                 case INTEL_OUTPUT_EDP:
5824                         has_panel = true;
5825                         if (intel_encoder_is_pch_edp(&encoder->base))
5826                                 has_pch_edp = true;
5827                         else
5828                                 has_cpu_edp = true;
5829                         break;
5830                 }
5831         }
5832
5833         if (HAS_PCH_IBX(dev)) {
5834                 has_ck505 = dev_priv->display_clock_mode;
5835                 can_ssc = has_ck505;
5836         } else {
5837                 has_ck505 = false;
5838                 can_ssc = true;
5839         }
5840
5841         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5842                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5843                       has_ck505);
5844
5845         /* Ironlake: try to setup display ref clock before DPLL
5846          * enabling. This is only under driver's control after
5847          * PCH B stepping, previous chipset stepping should be
5848          * ignoring this setting.
5849          */
5850         temp = I915_READ(PCH_DREF_CONTROL);
5851         /* Always enable nonspread source */
5852         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5853
5854         if (has_ck505)
5855                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5856         else
5857                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5858
5859         if (has_panel) {
5860                 temp &= ~DREF_SSC_SOURCE_MASK;
5861                 temp |= DREF_SSC_SOURCE_ENABLE;
5862
5863                 /* SSC must be turned on before enabling the CPU output  */
5864                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5865                         DRM_DEBUG_KMS("Using SSC on panel\n");
5866                         temp |= DREF_SSC1_ENABLE;
5867                 } else
5868                         temp &= ~DREF_SSC1_ENABLE;
5869
5870                 /* Get SSC going before enabling the outputs */
5871                 I915_WRITE(PCH_DREF_CONTROL, temp);
5872                 POSTING_READ(PCH_DREF_CONTROL);
5873                 udelay(200);
5874
5875                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5876
5877                 /* Enable CPU source on CPU attached eDP */
5878                 if (has_cpu_edp) {
5879                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5880                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5881                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5882                         }
5883                         else
5884                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5885                 } else
5886                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5887
5888                 I915_WRITE(PCH_DREF_CONTROL, temp);
5889                 POSTING_READ(PCH_DREF_CONTROL);
5890                 udelay(200);
5891         } else {
5892                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5893
5894                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5895
5896                 /* Turn off CPU output */
5897                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5898
5899                 I915_WRITE(PCH_DREF_CONTROL, temp);
5900                 POSTING_READ(PCH_DREF_CONTROL);
5901                 udelay(200);
5902
5903                 /* Turn off the SSC source */
5904                 temp &= ~DREF_SSC_SOURCE_MASK;
5905                 temp |= DREF_SSC_SOURCE_DISABLE;
5906
5907                 /* Turn off SSC1 */
5908                 temp &= ~ DREF_SSC1_ENABLE;
5909
5910                 I915_WRITE(PCH_DREF_CONTROL, temp);
5911                 POSTING_READ(PCH_DREF_CONTROL);
5912                 udelay(200);
5913         }
5914 }
5915
5916 static int ironlake_get_refclk(struct drm_crtc *crtc)
5917 {
5918         struct drm_device *dev = crtc->dev;
5919         struct drm_i915_private *dev_priv = dev->dev_private;
5920         struct intel_encoder *encoder;
5921         struct drm_mode_config *mode_config = &dev->mode_config;
5922         struct intel_encoder *edp_encoder = NULL;
5923         int num_connectors = 0;
5924         bool is_lvds = false;
5925
5926         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5927                 if (encoder->base.crtc != crtc)
5928                         continue;
5929
5930                 switch (encoder->type) {
5931                 case INTEL_OUTPUT_LVDS:
5932                         is_lvds = true;
5933                         break;
5934                 case INTEL_OUTPUT_EDP:
5935                         edp_encoder = encoder;
5936                         break;
5937                 }
5938                 num_connectors++;
5939         }
5940
5941         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5942                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5943                               dev_priv->lvds_ssc_freq);
5944                 return dev_priv->lvds_ssc_freq * 1000;
5945         }
5946
5947         return 120000;
5948 }
5949
5950 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5951                                   struct drm_display_mode *mode,
5952                                   struct drm_display_mode *adjusted_mode,
5953                                   int x, int y,
5954                                   struct drm_framebuffer *old_fb)
5955 {
5956         struct drm_device *dev = crtc->dev;
5957         struct drm_i915_private *dev_priv = dev->dev_private;
5958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5959         int pipe = intel_crtc->pipe;
5960         int plane = intel_crtc->plane;
5961         int refclk, num_connectors = 0;
5962         intel_clock_t clock, reduced_clock;
5963         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5964         bool ok, has_reduced_clock = false, is_sdvo = false;
5965         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5966         struct intel_encoder *has_edp_encoder = NULL;
5967         struct drm_mode_config *mode_config = &dev->mode_config;
5968         struct intel_encoder *encoder;
5969         const intel_limit_t *limit;
5970         int ret;
5971         struct fdi_m_n m_n = {0};
5972         u32 temp;
5973         u32 lvds_sync = 0;
5974         int target_clock, pixel_multiplier, lane, link_bw, factor;
5975         unsigned int pipe_bpp;
5976         bool dither;
5977
5978         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5979                 if (encoder->base.crtc != crtc)
5980                         continue;
5981
5982                 switch (encoder->type) {
5983                 case INTEL_OUTPUT_LVDS:
5984                         is_lvds = true;
5985                         break;
5986                 case INTEL_OUTPUT_SDVO:
5987                 case INTEL_OUTPUT_HDMI:
5988                         is_sdvo = true;
5989                         if (encoder->needs_tv_clock)
5990                                 is_tv = true;
5991                         break;
5992                 case INTEL_OUTPUT_TVOUT:
5993                         is_tv = true;
5994                         break;
5995                 case INTEL_OUTPUT_ANALOG:
5996                         is_crt = true;
5997                         break;
5998                 case INTEL_OUTPUT_DISPLAYPORT:
5999                         is_dp = true;
6000                         break;
6001                 case INTEL_OUTPUT_EDP:
6002                         has_edp_encoder = encoder;
6003                         break;
6004                 }
6005
6006                 num_connectors++;
6007         }
6008
6009         refclk = ironlake_get_refclk(crtc);
6010
6011         /*
6012          * Returns a set of divisors for the desired target clock with the given
6013          * refclk, or FALSE.  The returned values represent the clock equation:
6014          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6015          */
6016         limit = intel_limit(crtc, refclk);
6017         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
6018                              &clock);
6019         if (!ok) {
6020                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6021                 return -EINVAL;
6022         }
6023
6024         /* Ensure that the cursor is valid for the new mode before changing... */
6025         intel_crtc_update_cursor(crtc, true);
6026
6027         if (is_lvds && dev_priv->lvds_downclock_avail) {
6028                 /*
6029                  * Ensure we match the reduced clock's P to the target clock.
6030                  * If the clocks don't match, we can't switch the display clock
6031                  * by using the FP0/FP1. In such case we will disable the LVDS
6032                  * downclock feature.
6033                 */
6034                 has_reduced_clock = limit->find_pll(limit, crtc,
6035                                                     dev_priv->lvds_downclock,
6036                                                     refclk,
6037                                                     &clock,
6038                                                     &reduced_clock);
6039         }
6040         /* SDVO TV has fixed PLL values depend on its clock range,
6041            this mirrors vbios setting. */
6042         if (is_sdvo && is_tv) {
6043                 if (adjusted_mode->clock >= 100000
6044                     && adjusted_mode->clock < 140500) {
6045                         clock.p1 = 2;
6046                         clock.p2 = 10;
6047                         clock.n = 3;
6048                         clock.m1 = 16;
6049                         clock.m2 = 8;
6050                 } else if (adjusted_mode->clock >= 140500
6051                            && adjusted_mode->clock <= 200000) {
6052                         clock.p1 = 1;
6053                         clock.p2 = 10;
6054                         clock.n = 6;
6055                         clock.m1 = 12;
6056                         clock.m2 = 8;
6057                 }
6058         }
6059
6060         /* FDI link */
6061         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
6062         lane = 0;
6063         /* CPU eDP doesn't require FDI link, so just set DP M/N
6064            according to current link config */
6065         if (has_edp_encoder &&
6066             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6067                 target_clock = mode->clock;
6068                 intel_edp_link_config(has_edp_encoder,
6069                                       &lane, &link_bw);
6070         } else {
6071                 /* [e]DP over FDI requires target mode clock
6072                    instead of link clock */
6073                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
6074                         target_clock = mode->clock;
6075                 else
6076                         target_clock = adjusted_mode->clock;
6077
6078                 /* FDI is a binary signal running at ~2.7GHz, encoding
6079                  * each output octet as 10 bits. The actual frequency
6080                  * is stored as a divider into a 100MHz clock, and the
6081                  * mode pixel clock is stored in units of 1KHz.
6082                  * Hence the bw of each lane in terms of the mode signal
6083                  * is:
6084                  */
6085                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6086         }
6087
6088         /* determine panel color depth */
6089         temp = I915_READ(PIPECONF(pipe));
6090         temp &= ~PIPE_BPC_MASK;
6091         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
6092         switch (pipe_bpp) {
6093         case 18:
6094                 temp |= PIPE_6BPC;
6095                 break;
6096         case 24:
6097                 temp |= PIPE_8BPC;
6098                 break;
6099         case 30:
6100                 temp |= PIPE_10BPC;
6101                 break;
6102         case 36:
6103                 temp |= PIPE_12BPC;
6104                 break;
6105         default:
6106                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
6107                         pipe_bpp);
6108                 temp |= PIPE_8BPC;
6109                 pipe_bpp = 24;
6110                 break;
6111         }
6112
6113         intel_crtc->bpp = pipe_bpp;
6114         I915_WRITE(PIPECONF(pipe), temp);
6115
6116         if (!lane) {
6117                 /*
6118                  * Account for spread spectrum to avoid
6119                  * oversubscribing the link. Max center spread
6120                  * is 2.5%; use 5% for safety's sake.
6121                  */
6122                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
6123                 lane = bps / (link_bw * 8) + 1;
6124         }
6125
6126         intel_crtc->fdi_lanes = lane;
6127
6128         if (pixel_multiplier > 1)
6129                 link_bw *= pixel_multiplier;
6130         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
6131                              &m_n);
6132
6133         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
6134         if (has_reduced_clock)
6135                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
6136                         reduced_clock.m2;
6137
6138         /* Enable autotuning of the PLL clock (if permissible) */
6139         factor = 21;
6140         if (is_lvds) {
6141                 if ((intel_panel_use_ssc(dev_priv) &&
6142                      dev_priv->lvds_ssc_freq == 100) ||
6143                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
6144                         factor = 25;
6145         } else if (is_sdvo && is_tv)
6146                 factor = 20;
6147
6148         if (clock.m < factor * clock.n)
6149                 fp |= FP_CB_TUNE;
6150
6151         dpll = 0;
6152
6153         if (is_lvds)
6154                 dpll |= DPLLB_MODE_LVDS;
6155         else
6156                 dpll |= DPLLB_MODE_DAC_SERIAL;
6157         if (is_sdvo) {
6158                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
6159                 if (pixel_multiplier > 1) {
6160                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6161                 }
6162                 dpll |= DPLL_DVO_HIGH_SPEED;
6163         }
6164         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
6165                 dpll |= DPLL_DVO_HIGH_SPEED;
6166
6167         /* compute bitmask from p1 value */
6168         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6169         /* also FPA1 */
6170         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6171
6172         switch (clock.p2) {
6173         case 5:
6174                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6175                 break;
6176         case 7:
6177                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6178                 break;
6179         case 10:
6180                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6181                 break;
6182         case 14:
6183                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6184                 break;
6185         }
6186
6187         if (is_sdvo && is_tv)
6188                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6189         else if (is_tv)
6190                 /* XXX: just matching BIOS for now */
6191                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
6192                 dpll |= 3;
6193         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6194                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6195         else
6196                 dpll |= PLL_REF_INPUT_DREFCLK;
6197
6198         /* setup pipeconf */
6199         pipeconf = I915_READ(PIPECONF(pipe));
6200
6201         /* Set up the display plane register */
6202         dspcntr = DISPPLANE_GAMMA_ENABLE;
6203
6204         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
6205         drm_mode_debug_printmodeline(mode);
6206
6207         /* PCH eDP needs FDI, but CPU eDP does not */
6208         if (!intel_crtc->no_pll) {
6209                 if (!has_edp_encoder ||
6210                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6211                         I915_WRITE(PCH_FP0(pipe), fp);
6212                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
6213
6214                         POSTING_READ(PCH_DPLL(pipe));
6215                         udelay(150);
6216                 }
6217         } else {
6218                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
6219                     fp == I915_READ(PCH_FP0(0))) {
6220                         intel_crtc->use_pll_a = true;
6221                         DRM_DEBUG_KMS("using pipe a dpll\n");
6222                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
6223                            fp == I915_READ(PCH_FP0(1))) {
6224                         intel_crtc->use_pll_a = false;
6225                         DRM_DEBUG_KMS("using pipe b dpll\n");
6226                 } else {
6227                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
6228                         return -EINVAL;
6229                 }
6230         }
6231
6232         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
6233          * This is an exception to the general rule that mode_set doesn't turn
6234          * things on.
6235          */
6236         if (is_lvds) {
6237                 temp = I915_READ(PCH_LVDS);
6238                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
6239                 if (HAS_PCH_CPT(dev)) {
6240                         temp &= ~PORT_TRANS_SEL_MASK;
6241                         temp |= PORT_TRANS_SEL_CPT(pipe);
6242                 } else {
6243                         if (pipe == 1)
6244                                 temp |= LVDS_PIPEB_SELECT;
6245                         else
6246                                 temp &= ~LVDS_PIPEB_SELECT;
6247                 }
6248
6249                 /* set the corresponsding LVDS_BORDER bit */
6250                 temp |= dev_priv->lvds_border_bits;
6251                 /* Set the B0-B3 data pairs corresponding to whether we're going to
6252                  * set the DPLLs for dual-channel mode or not.
6253                  */
6254                 if (clock.p2 == 7)
6255                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6256                 else
6257                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6258
6259                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6260                  * appropriately here, but we need to look more thoroughly into how
6261                  * panels behave in the two modes.
6262                  */
6263                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6264                         lvds_sync |= LVDS_HSYNC_POLARITY;
6265                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6266                         lvds_sync |= LVDS_VSYNC_POLARITY;
6267                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6268                     != lvds_sync) {
6269                         char flags[2] = "-+";
6270                         DRM_INFO("Changing LVDS panel from "
6271                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6272                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
6273                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
6274                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6275                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6276                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6277                         temp |= lvds_sync;
6278                 }
6279                 I915_WRITE(PCH_LVDS, temp);
6280         }
6281
6282         pipeconf &= ~PIPECONF_DITHER_EN;
6283         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
6284         if ((is_lvds && dev_priv->lvds_dither) || dither) {
6285                 pipeconf |= PIPECONF_DITHER_EN;
6286                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6287         }
6288         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6289                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6290         } else {
6291                 /* For non-DP output, clear any trans DP clock recovery setting.*/
6292                 I915_WRITE(TRANSDATA_M1(pipe), 0);
6293                 I915_WRITE(TRANSDATA_N1(pipe), 0);
6294                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6295                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6296         }
6297
6298         if (!intel_crtc->no_pll &&
6299             (!has_edp_encoder ||
6300              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6301                 I915_WRITE(PCH_DPLL(pipe), dpll);
6302
6303                 /* Wait for the clocks to stabilize. */
6304                 POSTING_READ(PCH_DPLL(pipe));
6305                 udelay(150);
6306
6307                 /* The pixel multiplier can only be updated once the
6308                  * DPLL is enabled and the clocks are stable.
6309                  *
6310                  * So write it again.
6311                  */
6312                 I915_WRITE(PCH_DPLL(pipe), dpll);
6313         }
6314
6315         intel_crtc->lowfreq_avail = false;
6316         if (!intel_crtc->no_pll) {
6317                 if (is_lvds && has_reduced_clock && i915_powersave) {
6318                         I915_WRITE(PCH_FP1(pipe), fp2);
6319                         intel_crtc->lowfreq_avail = true;
6320                         if (HAS_PIPE_CXSR(dev)) {
6321                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6322                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6323                         }
6324                 } else {
6325                         I915_WRITE(PCH_FP1(pipe), fp);
6326                         if (HAS_PIPE_CXSR(dev)) {
6327                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6328                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6329                         }
6330                 }
6331         }
6332
6333         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6334         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6335                 pipeconf |= PIPECONF_INTERLACED_ILK;
6336                 /* the chip adds 2 halflines automatically */
6337                 adjusted_mode->crtc_vtotal -= 1;
6338                 adjusted_mode->crtc_vblank_end -= 1;
6339                 I915_WRITE(VSYNCSHIFT(pipe),
6340                            adjusted_mode->crtc_hsync_start
6341                            - adjusted_mode->crtc_htotal/2);
6342         } else {
6343                 pipeconf |= PIPECONF_PROGRESSIVE;
6344                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6345         }
6346
6347         I915_WRITE(HTOTAL(pipe),
6348                    (adjusted_mode->crtc_hdisplay - 1) |
6349                    ((adjusted_mode->crtc_htotal - 1) << 16));
6350         I915_WRITE(HBLANK(pipe),
6351                    (adjusted_mode->crtc_hblank_start - 1) |
6352                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6353         I915_WRITE(HSYNC(pipe),
6354                    (adjusted_mode->crtc_hsync_start - 1) |
6355                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6356
6357         I915_WRITE(VTOTAL(pipe),
6358                    (adjusted_mode->crtc_vdisplay - 1) |
6359                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6360         I915_WRITE(VBLANK(pipe),
6361                    (adjusted_mode->crtc_vblank_start - 1) |
6362                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6363         I915_WRITE(VSYNC(pipe),
6364                    (adjusted_mode->crtc_vsync_start - 1) |
6365                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6366
6367         /* pipesrc controls the size that is scaled from, which should
6368          * always be the user's requested size.
6369          */
6370         I915_WRITE(PIPESRC(pipe),
6371                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6372
6373         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6374         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6375         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6376         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6377
6378         if (has_edp_encoder &&
6379             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6380                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6381         }
6382
6383         I915_WRITE(PIPECONF(pipe), pipeconf);
6384         POSTING_READ(PIPECONF(pipe));
6385
6386         intel_wait_for_vblank(dev, pipe);
6387
6388         I915_WRITE(DSPCNTR(plane), dspcntr);
6389         POSTING_READ(DSPCNTR(plane));
6390
6391         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6392
6393         intel_update_watermarks(dev);
6394
6395         return ret;
6396 }
6397
6398 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6399                                struct drm_display_mode *mode,
6400                                struct drm_display_mode *adjusted_mode,
6401                                int x, int y,
6402                                struct drm_framebuffer *old_fb)
6403 {
6404         struct drm_device *dev = crtc->dev;
6405         struct drm_i915_private *dev_priv = dev->dev_private;
6406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6407         int pipe = intel_crtc->pipe;
6408         int ret;
6409
6410         drm_vblank_pre_modeset(dev, pipe);
6411
6412         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6413                                               x, y, old_fb);
6414         drm_vblank_post_modeset(dev, pipe);
6415
6416         if (ret)
6417                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6418         else
6419                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6420
6421         return ret;
6422 }
6423
6424 static bool intel_eld_uptodate(struct drm_connector *connector,
6425                                int reg_eldv, uint32_t bits_eldv,
6426                                int reg_elda, uint32_t bits_elda,
6427                                int reg_edid)
6428 {
6429         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6430         uint8_t *eld = connector->eld;
6431         uint32_t i;
6432
6433         i = I915_READ(reg_eldv);
6434         i &= bits_eldv;
6435
6436         if (!eld[0])
6437                 return !i;
6438
6439         if (!i)
6440                 return false;
6441
6442         i = I915_READ(reg_elda);
6443         i &= ~bits_elda;
6444         I915_WRITE(reg_elda, i);
6445
6446         for (i = 0; i < eld[2]; i++)
6447                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6448                         return false;
6449
6450         return true;
6451 }
6452
6453 static void g4x_write_eld(struct drm_connector *connector,
6454                           struct drm_crtc *crtc)
6455 {
6456         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6457         uint8_t *eld = connector->eld;
6458         uint32_t eldv;
6459         uint32_t len;
6460         uint32_t i;
6461
6462         i = I915_READ(G4X_AUD_VID_DID);
6463
6464         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6465                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6466         else
6467                 eldv = G4X_ELDV_DEVCTG;
6468
6469         if (intel_eld_uptodate(connector,
6470                                G4X_AUD_CNTL_ST, eldv,
6471                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6472                                G4X_HDMIW_HDMIEDID))
6473                 return;
6474
6475         i = I915_READ(G4X_AUD_CNTL_ST);
6476         i &= ~(eldv | G4X_ELD_ADDR);
6477         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6478         I915_WRITE(G4X_AUD_CNTL_ST, i);
6479
6480         if (!eld[0])
6481                 return;
6482
6483         len = min_t(uint8_t, eld[2], len);
6484         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6485         for (i = 0; i < len; i++)
6486                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6487
6488         i = I915_READ(G4X_AUD_CNTL_ST);
6489         i |= eldv;
6490         I915_WRITE(G4X_AUD_CNTL_ST, i);
6491 }
6492
6493 static void ironlake_write_eld(struct drm_connector *connector,
6494                                      struct drm_crtc *crtc)
6495 {
6496         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6497         uint8_t *eld = connector->eld;
6498         uint32_t eldv;
6499         uint32_t i;
6500         int len;
6501         int hdmiw_hdmiedid;
6502         int aud_config;
6503         int aud_cntl_st;
6504         int aud_cntrl_st2;
6505
6506         if (HAS_PCH_IBX(connector->dev)) {
6507                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6508                 aud_config = IBX_AUD_CONFIG_A;
6509                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6510                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6511         } else {
6512                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6513                 aud_config = CPT_AUD_CONFIG_A;
6514                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6515                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6516         }
6517
6518         i = to_intel_crtc(crtc)->pipe;
6519         hdmiw_hdmiedid += i * 0x100;
6520         aud_cntl_st += i * 0x100;
6521         aud_config += i * 0x100;
6522
6523         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6524
6525         i = I915_READ(aud_cntl_st);
6526         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6527         if (!i) {
6528                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6529                 /* operate blindly on all ports */
6530                 eldv = IBX_ELD_VALIDB;
6531                 eldv |= IBX_ELD_VALIDB << 4;
6532                 eldv |= IBX_ELD_VALIDB << 8;
6533         } else {
6534                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6535                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6536         }
6537
6538         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6539                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6540                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6541                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6542         } else
6543                 I915_WRITE(aud_config, 0);
6544
6545         if (intel_eld_uptodate(connector,
6546                                aud_cntrl_st2, eldv,
6547                                aud_cntl_st, IBX_ELD_ADDRESS,
6548                                hdmiw_hdmiedid))
6549                 return;
6550
6551         i = I915_READ(aud_cntrl_st2);
6552         i &= ~eldv;
6553         I915_WRITE(aud_cntrl_st2, i);
6554
6555         if (!eld[0])
6556                 return;
6557
6558         i = I915_READ(aud_cntl_st);
6559         i &= ~IBX_ELD_ADDRESS;
6560         I915_WRITE(aud_cntl_st, i);
6561
6562         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6563         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6564         for (i = 0; i < len; i++)
6565                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6566
6567         i = I915_READ(aud_cntrl_st2);
6568         i |= eldv;
6569         I915_WRITE(aud_cntrl_st2, i);
6570 }
6571
6572 void intel_write_eld(struct drm_encoder *encoder,
6573                      struct drm_display_mode *mode)
6574 {
6575         struct drm_crtc *crtc = encoder->crtc;
6576         struct drm_connector *connector;
6577         struct drm_device *dev = encoder->dev;
6578         struct drm_i915_private *dev_priv = dev->dev_private;
6579
6580         connector = drm_select_eld(encoder, mode);
6581         if (!connector)
6582                 return;
6583
6584         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6585                          connector->base.id,
6586                          drm_get_connector_name(connector),
6587                          connector->encoder->base.id,
6588                          drm_get_encoder_name(connector->encoder));
6589
6590         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6591
6592         if (dev_priv->display.write_eld)
6593                 dev_priv->display.write_eld(connector, crtc);
6594 }
6595
6596 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6597 void intel_crtc_load_lut(struct drm_crtc *crtc)
6598 {
6599         struct drm_device *dev = crtc->dev;
6600         struct drm_i915_private *dev_priv = dev->dev_private;
6601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602         int palreg = PALETTE(intel_crtc->pipe);
6603         int i;
6604
6605         /* The clocks have to be on to load the palette. */
6606         if (!crtc->enabled || !intel_crtc->active)
6607                 return;
6608
6609         /* use legacy palette for Ironlake */
6610         if (HAS_PCH_SPLIT(dev))
6611                 palreg = LGC_PALETTE(intel_crtc->pipe);
6612
6613         for (i = 0; i < 256; i++) {
6614                 I915_WRITE(palreg + 4 * i,
6615                            (intel_crtc->lut_r[i] << 16) |
6616                            (intel_crtc->lut_g[i] << 8) |
6617                            intel_crtc->lut_b[i]);
6618         }
6619 }
6620
6621 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6622 {
6623         struct drm_device *dev = crtc->dev;
6624         struct drm_i915_private *dev_priv = dev->dev_private;
6625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6626         bool visible = base != 0;
6627         u32 cntl;
6628
6629         if (intel_crtc->cursor_visible == visible)
6630                 return;
6631
6632         cntl = I915_READ(_CURACNTR);
6633         if (visible) {
6634                 /* On these chipsets we can only modify the base whilst
6635                  * the cursor is disabled.
6636                  */
6637                 I915_WRITE(_CURABASE, base);
6638
6639                 cntl &= ~(CURSOR_FORMAT_MASK);
6640                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6641                 cntl |= CURSOR_ENABLE |
6642                         CURSOR_GAMMA_ENABLE |
6643                         CURSOR_FORMAT_ARGB;
6644         } else
6645                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6646         I915_WRITE(_CURACNTR, cntl);
6647
6648         intel_crtc->cursor_visible = visible;
6649 }
6650
6651 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6652 {
6653         struct drm_device *dev = crtc->dev;
6654         struct drm_i915_private *dev_priv = dev->dev_private;
6655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6656         int pipe = intel_crtc->pipe;
6657         bool visible = base != 0;
6658
6659         if (intel_crtc->cursor_visible != visible) {
6660                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6661                 if (base) {
6662                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6663                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6664                         cntl |= pipe << 28; /* Connect to correct pipe */
6665                 } else {
6666                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6667                         cntl |= CURSOR_MODE_DISABLE;
6668                 }
6669                 I915_WRITE(CURCNTR(pipe), cntl);
6670
6671                 intel_crtc->cursor_visible = visible;
6672         }
6673         /* and commit changes on next vblank */
6674         I915_WRITE(CURBASE(pipe), base);
6675 }
6676
6677 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6678 {
6679         struct drm_device *dev = crtc->dev;
6680         struct drm_i915_private *dev_priv = dev->dev_private;
6681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6682         int pipe = intel_crtc->pipe;
6683         bool visible = base != 0;
6684
6685         if (intel_crtc->cursor_visible != visible) {
6686                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6687                 if (base) {
6688                         cntl &= ~CURSOR_MODE;
6689                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6690                 } else {
6691                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6692                         cntl |= CURSOR_MODE_DISABLE;
6693                 }
6694                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6695
6696                 intel_crtc->cursor_visible = visible;
6697         }
6698         /* and commit changes on next vblank */
6699         I915_WRITE(CURBASE_IVB(pipe), base);
6700 }
6701
6702 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6703 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6704                                      bool on)
6705 {
6706         struct drm_device *dev = crtc->dev;
6707         struct drm_i915_private *dev_priv = dev->dev_private;
6708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6709         int pipe = intel_crtc->pipe;
6710         int x = intel_crtc->cursor_x;
6711         int y = intel_crtc->cursor_y;
6712         u32 base, pos;
6713         bool visible;
6714
6715         pos = 0;
6716
6717         if (on && crtc->enabled && crtc->fb) {
6718                 base = intel_crtc->cursor_addr;
6719                 if (x > (int) crtc->fb->width)
6720                         base = 0;
6721
6722                 if (y > (int) crtc->fb->height)
6723                         base = 0;
6724         } else
6725                 base = 0;
6726
6727         if (x < 0) {
6728                 if (x + intel_crtc->cursor_width < 0)
6729                         base = 0;
6730
6731                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6732                 x = -x;
6733         }
6734         pos |= x << CURSOR_X_SHIFT;
6735
6736         if (y < 0) {
6737                 if (y + intel_crtc->cursor_height < 0)
6738                         base = 0;
6739
6740                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6741                 y = -y;
6742         }
6743         pos |= y << CURSOR_Y_SHIFT;
6744
6745         visible = base != 0;
6746         if (!visible && !intel_crtc->cursor_visible)
6747                 return;
6748
6749         if (IS_IVYBRIDGE(dev)) {
6750                 I915_WRITE(CURPOS_IVB(pipe), pos);
6751                 ivb_update_cursor(crtc, base);
6752         } else {
6753                 I915_WRITE(CURPOS(pipe), pos);
6754                 if (IS_845G(dev) || IS_I865G(dev))
6755                         i845_update_cursor(crtc, base);
6756                 else
6757                         i9xx_update_cursor(crtc, base);
6758         }
6759
6760         if (visible)
6761                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6762 }
6763
6764 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6765                                  struct drm_file *file,
6766                                  uint32_t handle,
6767                                  uint32_t width, uint32_t height)
6768 {
6769         struct drm_device *dev = crtc->dev;
6770         struct drm_i915_private *dev_priv = dev->dev_private;
6771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6772         struct drm_i915_gem_object *obj;
6773         uint32_t addr;
6774         int ret;
6775
6776         DRM_DEBUG_KMS("\n");
6777
6778         /* if we want to turn off the cursor ignore width and height */
6779         if (!handle) {
6780                 DRM_DEBUG_KMS("cursor off\n");
6781                 addr = 0;
6782                 obj = NULL;
6783                 mutex_lock(&dev->struct_mutex);
6784                 goto finish;
6785         }
6786
6787         /* Currently we only support 64x64 cursors */
6788         if (width != 64 || height != 64) {
6789                 DRM_ERROR("we currently only support 64x64 cursors\n");
6790                 return -EINVAL;
6791         }
6792
6793         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6794         if (&obj->base == NULL)
6795                 return -ENOENT;
6796
6797         if (obj->base.size < width * height * 4) {
6798                 DRM_ERROR("buffer is to small\n");
6799                 ret = -ENOMEM;
6800                 goto fail;
6801         }
6802
6803         /* we only need to pin inside GTT if cursor is non-phy */
6804         mutex_lock(&dev->struct_mutex);
6805         if (!dev_priv->info->cursor_needs_physical) {
6806                 if (obj->tiling_mode) {
6807                         DRM_ERROR("cursor cannot be tiled\n");
6808                         ret = -EINVAL;
6809                         goto fail_locked;
6810                 }
6811
6812                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6813                 if (ret) {
6814                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6815                         goto fail_locked;
6816                 }
6817
6818                 ret = i915_gem_object_put_fence(obj);
6819                 if (ret) {
6820                         DRM_ERROR("failed to release fence for cursor");
6821                         goto fail_unpin;
6822                 }
6823
6824                 addr = obj->gtt_offset;
6825         } else {
6826                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6827                 ret = i915_gem_attach_phys_object(dev, obj,
6828                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6829                                                   align);
6830                 if (ret) {
6831                         DRM_ERROR("failed to attach phys object\n");
6832                         goto fail_locked;
6833                 }
6834                 addr = obj->phys_obj->handle->busaddr;
6835         }
6836
6837         if (IS_GEN2(dev))
6838                 I915_WRITE(CURSIZE, (height << 12) | width);
6839
6840  finish:
6841         if (intel_crtc->cursor_bo) {
6842                 if (dev_priv->info->cursor_needs_physical) {
6843                         if (intel_crtc->cursor_bo != obj)
6844                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6845                 } else
6846                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6847                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6848         }
6849
6850         mutex_unlock(&dev->struct_mutex);
6851
6852         intel_crtc->cursor_addr = addr;
6853         intel_crtc->cursor_bo = obj;
6854         intel_crtc->cursor_width = width;
6855         intel_crtc->cursor_height = height;
6856
6857         intel_crtc_update_cursor(crtc, true);
6858
6859         return 0;
6860 fail_unpin:
6861         i915_gem_object_unpin(obj);
6862 fail_locked:
6863         mutex_unlock(&dev->struct_mutex);
6864 fail:
6865         drm_gem_object_unreference_unlocked(&obj->base);
6866         return ret;
6867 }
6868
6869 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6870 {
6871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6872
6873         intel_crtc->cursor_x = x;
6874         intel_crtc->cursor_y = y;
6875
6876         intel_crtc_update_cursor(crtc, true);
6877
6878         return 0;
6879 }
6880
6881 /** Sets the color ramps on behalf of RandR */
6882 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6883                                  u16 blue, int regno)
6884 {
6885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6886
6887         intel_crtc->lut_r[regno] = red >> 8;
6888         intel_crtc->lut_g[regno] = green >> 8;
6889         intel_crtc->lut_b[regno] = blue >> 8;
6890 }
6891
6892 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6893                              u16 *blue, int regno)
6894 {
6895         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6896
6897         *red = intel_crtc->lut_r[regno] << 8;
6898         *green = intel_crtc->lut_g[regno] << 8;
6899         *blue = intel_crtc->lut_b[regno] << 8;
6900 }
6901
6902 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6903                                  u16 *blue, uint32_t start, uint32_t size)
6904 {
6905         int end = (start + size > 256) ? 256 : start + size, i;
6906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6907
6908         for (i = start; i < end; i++) {
6909                 intel_crtc->lut_r[i] = red[i] >> 8;
6910                 intel_crtc->lut_g[i] = green[i] >> 8;
6911                 intel_crtc->lut_b[i] = blue[i] >> 8;
6912         }
6913
6914         intel_crtc_load_lut(crtc);
6915 }
6916
6917 /**
6918  * Get a pipe with a simple mode set on it for doing load-based monitor
6919  * detection.
6920  *
6921  * It will be up to the load-detect code to adjust the pipe as appropriate for
6922  * its requirements.  The pipe will be connected to no other encoders.
6923  *
6924  * Currently this code will only succeed if there is a pipe with no encoders
6925  * configured for it.  In the future, it could choose to temporarily disable
6926  * some outputs to free up a pipe for its use.
6927  *
6928  * \return crtc, or NULL if no pipes are available.
6929  */
6930
6931 /* VESA 640x480x72Hz mode to set on the pipe */
6932 static struct drm_display_mode load_detect_mode = {
6933         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6934                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6935 };
6936
6937 static struct drm_framebuffer *
6938 intel_framebuffer_create(struct drm_device *dev,
6939                          struct drm_mode_fb_cmd2 *mode_cmd,
6940                          struct drm_i915_gem_object *obj)
6941 {
6942         struct intel_framebuffer *intel_fb;
6943         int ret;
6944
6945         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6946         if (!intel_fb) {
6947                 drm_gem_object_unreference_unlocked(&obj->base);
6948                 return ERR_PTR(-ENOMEM);
6949         }
6950
6951         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6952         if (ret) {
6953                 drm_gem_object_unreference_unlocked(&obj->base);
6954                 kfree(intel_fb);
6955                 return ERR_PTR(ret);
6956         }
6957
6958         return &intel_fb->base;
6959 }
6960
6961 static u32
6962 intel_framebuffer_pitch_for_width(int width, int bpp)
6963 {
6964         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6965         return ALIGN(pitch, 64);
6966 }
6967
6968 static u32
6969 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6970 {
6971         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6972         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6973 }
6974
6975 static struct drm_framebuffer *
6976 intel_framebuffer_create_for_mode(struct drm_device *dev,
6977                                   struct drm_display_mode *mode,
6978                                   int depth, int bpp)
6979 {
6980         struct drm_i915_gem_object *obj;
6981         struct drm_mode_fb_cmd2 mode_cmd;
6982
6983         obj = i915_gem_alloc_object(dev,
6984                                     intel_framebuffer_size_for_mode(mode, bpp));
6985         if (obj == NULL)
6986                 return ERR_PTR(-ENOMEM);
6987
6988         mode_cmd.width = mode->hdisplay;
6989         mode_cmd.height = mode->vdisplay;
6990         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6991                                                                 bpp);
6992         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6993
6994         return intel_framebuffer_create(dev, &mode_cmd, obj);
6995 }
6996
6997 static struct drm_framebuffer *
6998 mode_fits_in_fbdev(struct drm_device *dev,
6999                    struct drm_display_mode *mode)
7000 {
7001         struct drm_i915_private *dev_priv = dev->dev_private;
7002         struct drm_i915_gem_object *obj;
7003         struct drm_framebuffer *fb;
7004
7005         if (dev_priv->fbdev == NULL)
7006                 return NULL;
7007
7008         obj = dev_priv->fbdev->ifb.obj;
7009         if (obj == NULL)
7010                 return NULL;
7011
7012         fb = &dev_priv->fbdev->ifb.base;
7013         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7014                                                                fb->bits_per_pixel))
7015                 return NULL;
7016
7017         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7018                 return NULL;
7019
7020         return fb;
7021 }
7022
7023 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
7024                                 struct drm_connector *connector,
7025                                 struct drm_display_mode *mode,
7026                                 struct intel_load_detect_pipe *old)
7027 {
7028         struct intel_crtc *intel_crtc;
7029         struct drm_crtc *possible_crtc;
7030         struct drm_encoder *encoder = &intel_encoder->base;
7031         struct drm_crtc *crtc = NULL;
7032         struct drm_device *dev = encoder->dev;
7033         struct drm_framebuffer *old_fb;
7034         int i = -1;
7035
7036         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7037                       connector->base.id, drm_get_connector_name(connector),
7038                       encoder->base.id, drm_get_encoder_name(encoder));
7039
7040         /*
7041          * Algorithm gets a little messy:
7042          *
7043          *   - if the connector already has an assigned crtc, use it (but make
7044          *     sure it's on first)
7045          *
7046          *   - try to find the first unused crtc that can drive this connector,
7047          *     and use that if we find one
7048          */
7049
7050         /* See if we already have a CRTC for this connector */
7051         if (encoder->crtc) {
7052                 crtc = encoder->crtc;
7053
7054                 intel_crtc = to_intel_crtc(crtc);
7055                 old->dpms_mode = intel_crtc->dpms_mode;
7056                 old->load_detect_temp = false;
7057
7058                 /* Make sure the crtc and connector are running */
7059                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
7060                         struct drm_encoder_helper_funcs *encoder_funcs;
7061                         struct drm_crtc_helper_funcs *crtc_funcs;
7062
7063                         crtc_funcs = crtc->helper_private;
7064                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
7065
7066                         encoder_funcs = encoder->helper_private;
7067                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
7068                 }
7069
7070                 return true;
7071         }
7072
7073         /* Find an unused one (if possible) */
7074         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7075                 i++;
7076                 if (!(encoder->possible_crtcs & (1 << i)))
7077                         continue;
7078                 if (!possible_crtc->enabled) {
7079                         crtc = possible_crtc;
7080                         break;
7081                 }
7082         }
7083
7084         /*
7085          * If we didn't find an unused CRTC, don't use any.
7086          */
7087         if (!crtc) {
7088                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7089                 return false;
7090         }
7091
7092         encoder->crtc = crtc;
7093         connector->encoder = encoder;
7094
7095         intel_crtc = to_intel_crtc(crtc);
7096         old->dpms_mode = intel_crtc->dpms_mode;
7097         old->load_detect_temp = true;
7098         old->release_fb = NULL;
7099
7100         if (!mode)
7101                 mode = &load_detect_mode;
7102
7103         old_fb = crtc->fb;
7104
7105         /* We need a framebuffer large enough to accommodate all accesses
7106          * that the plane may generate whilst we perform load detection.
7107          * We can not rely on the fbcon either being present (we get called
7108          * during its initialisation to detect all boot displays, or it may
7109          * not even exist) or that it is large enough to satisfy the
7110          * requested mode.
7111          */
7112         crtc->fb = mode_fits_in_fbdev(dev, mode);
7113         if (crtc->fb == NULL) {
7114                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7115                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7116                 old->release_fb = crtc->fb;
7117         } else
7118                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7119         if (IS_ERR(crtc->fb)) {
7120                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7121                 crtc->fb = old_fb;
7122                 return false;
7123         }
7124
7125         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
7126                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7127                 if (old->release_fb)
7128                         old->release_fb->funcs->destroy(old->release_fb);
7129                 crtc->fb = old_fb;
7130                 return false;
7131         }
7132
7133         /* let the connector get through one full cycle before testing */
7134         intel_wait_for_vblank(dev, intel_crtc->pipe);
7135
7136         return true;
7137 }
7138
7139 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
7140                                     struct drm_connector *connector,
7141                                     struct intel_load_detect_pipe *old)
7142 {
7143         struct drm_encoder *encoder = &intel_encoder->base;
7144         struct drm_device *dev = encoder->dev;
7145         struct drm_crtc *crtc = encoder->crtc;
7146         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
7147         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
7148
7149         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7150                       connector->base.id, drm_get_connector_name(connector),
7151                       encoder->base.id, drm_get_encoder_name(encoder));
7152
7153         if (old->load_detect_temp) {
7154                 connector->encoder = NULL;
7155                 drm_helper_disable_unused_functions(dev);
7156
7157                 if (old->release_fb)
7158                         old->release_fb->funcs->destroy(old->release_fb);
7159
7160                 return;
7161         }
7162
7163         /* Switch crtc and encoder back off if necessary */
7164         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
7165                 encoder_funcs->dpms(encoder, old->dpms_mode);
7166                 crtc_funcs->dpms(crtc, old->dpms_mode);
7167         }
7168 }
7169
7170 /* Returns the clock of the currently programmed mode of the given pipe. */
7171 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
7172 {
7173         struct drm_i915_private *dev_priv = dev->dev_private;
7174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7175         int pipe = intel_crtc->pipe;
7176         u32 dpll = I915_READ(DPLL(pipe));
7177         u32 fp;
7178         intel_clock_t clock;
7179
7180         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7181                 fp = I915_READ(FP0(pipe));
7182         else
7183                 fp = I915_READ(FP1(pipe));
7184
7185         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7186         if (IS_PINEVIEW(dev)) {
7187                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7188                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7189         } else {
7190                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7191                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7192         }
7193
7194         if (!IS_GEN2(dev)) {
7195                 if (IS_PINEVIEW(dev))
7196                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7197                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7198                 else
7199                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7200                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7201
7202                 switch (dpll & DPLL_MODE_MASK) {
7203                 case DPLLB_MODE_DAC_SERIAL:
7204                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7205                                 5 : 10;
7206                         break;
7207                 case DPLLB_MODE_LVDS:
7208                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7209                                 7 : 14;
7210                         break;
7211                 default:
7212                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7213                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7214                         return 0;
7215                 }
7216
7217                 /* XXX: Handle the 100Mhz refclk */
7218                 intel_clock(dev, 96000, &clock);
7219         } else {
7220                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7221
7222                 if (is_lvds) {
7223                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7224                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7225                         clock.p2 = 14;
7226
7227                         if ((dpll & PLL_REF_INPUT_MASK) ==
7228                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7229                                 /* XXX: might not be 66MHz */
7230                                 intel_clock(dev, 66000, &clock);
7231                         } else
7232                                 intel_clock(dev, 48000, &clock);
7233                 } else {
7234                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7235                                 clock.p1 = 2;
7236                         else {
7237                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7238                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7239                         }
7240                         if (dpll & PLL_P2_DIVIDE_BY_4)
7241                                 clock.p2 = 4;
7242                         else
7243                                 clock.p2 = 2;
7244
7245                         intel_clock(dev, 48000, &clock);
7246                 }
7247         }
7248
7249         /* XXX: It would be nice to validate the clocks, but we can't reuse
7250          * i830PllIsValid() because it relies on the xf86_config connector
7251          * configuration being accurate, which it isn't necessarily.
7252          */
7253
7254         return clock.dot;
7255 }
7256
7257 /** Returns the currently programmed mode of the given pipe. */
7258 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7259                                              struct drm_crtc *crtc)
7260 {
7261         struct drm_i915_private *dev_priv = dev->dev_private;
7262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7263         int pipe = intel_crtc->pipe;
7264         struct drm_display_mode *mode;
7265         int htot = I915_READ(HTOTAL(pipe));
7266         int hsync = I915_READ(HSYNC(pipe));
7267         int vtot = I915_READ(VTOTAL(pipe));
7268         int vsync = I915_READ(VSYNC(pipe));
7269
7270         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7271         if (!mode)
7272                 return NULL;
7273
7274         mode->clock = intel_crtc_clock_get(dev, crtc);
7275         mode->hdisplay = (htot & 0xffff) + 1;
7276         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7277         mode->hsync_start = (hsync & 0xffff) + 1;
7278         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7279         mode->vdisplay = (vtot & 0xffff) + 1;
7280         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7281         mode->vsync_start = (vsync & 0xffff) + 1;
7282         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7283
7284         drm_mode_set_name(mode);
7285         drm_mode_set_crtcinfo(mode, 0);
7286
7287         return mode;
7288 }
7289
7290 #define GPU_IDLE_TIMEOUT 500 /* ms */
7291
7292 /* When this timer fires, we've been idle for awhile */
7293 static void intel_gpu_idle_timer(unsigned long arg)
7294 {
7295         struct drm_device *dev = (struct drm_device *)arg;
7296         drm_i915_private_t *dev_priv = dev->dev_private;
7297
7298         if (!list_empty(&dev_priv->mm.active_list)) {
7299                 /* Still processing requests, so just re-arm the timer. */
7300                 mod_timer(&dev_priv->idle_timer, jiffies +
7301                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7302                 return;
7303         }
7304
7305         dev_priv->busy = false;
7306         queue_work(dev_priv->wq, &dev_priv->idle_work);
7307 }
7308
7309 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7310
7311 static void intel_crtc_idle_timer(unsigned long arg)
7312 {
7313         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7314         struct drm_crtc *crtc = &intel_crtc->base;
7315         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7316         struct intel_framebuffer *intel_fb;
7317
7318         intel_fb = to_intel_framebuffer(crtc->fb);
7319         if (intel_fb && intel_fb->obj->active) {
7320                 /* The framebuffer is still being accessed by the GPU. */
7321                 mod_timer(&intel_crtc->idle_timer, jiffies +
7322                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7323                 return;
7324         }
7325
7326         intel_crtc->busy = false;
7327         queue_work(dev_priv->wq, &dev_priv->idle_work);
7328 }
7329
7330 static void intel_increase_pllclock(struct drm_crtc *crtc)
7331 {
7332         struct drm_device *dev = crtc->dev;
7333         drm_i915_private_t *dev_priv = dev->dev_private;
7334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7335         int pipe = intel_crtc->pipe;
7336         int dpll_reg = DPLL(pipe);
7337         int dpll;
7338
7339         if (HAS_PCH_SPLIT(dev))
7340                 return;
7341
7342         if (!dev_priv->lvds_downclock_avail)
7343                 return;
7344
7345         dpll = I915_READ(dpll_reg);
7346         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7347                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7348
7349                 assert_panel_unlocked(dev_priv, pipe);
7350
7351                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7352                 I915_WRITE(dpll_reg, dpll);
7353                 intel_wait_for_vblank(dev, pipe);
7354
7355                 dpll = I915_READ(dpll_reg);
7356                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7357                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7358         }
7359
7360         /* Schedule downclock */
7361         mod_timer(&intel_crtc->idle_timer, jiffies +
7362                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7363 }
7364
7365 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7366 {
7367         struct drm_device *dev = crtc->dev;
7368         drm_i915_private_t *dev_priv = dev->dev_private;
7369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7370         int pipe = intel_crtc->pipe;
7371         int dpll_reg = DPLL(pipe);
7372         int dpll = I915_READ(dpll_reg);
7373
7374         if (HAS_PCH_SPLIT(dev))
7375                 return;
7376
7377         if (!dev_priv->lvds_downclock_avail)
7378                 return;
7379
7380         /*
7381          * Since this is called by a timer, we should never get here in
7382          * the manual case.
7383          */
7384         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7385                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7386
7387                 assert_panel_unlocked(dev_priv, pipe);
7388
7389                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7390                 I915_WRITE(dpll_reg, dpll);
7391                 intel_wait_for_vblank(dev, pipe);
7392                 dpll = I915_READ(dpll_reg);
7393                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7394                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7395         }
7396
7397 }
7398
7399 /**
7400  * intel_idle_update - adjust clocks for idleness
7401  * @work: work struct
7402  *
7403  * Either the GPU or display (or both) went idle.  Check the busy status
7404  * here and adjust the CRTC and GPU clocks as necessary.
7405  */
7406 static void intel_idle_update(struct work_struct *work)
7407 {
7408         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7409                                                     idle_work);
7410         struct drm_device *dev = dev_priv->dev;
7411         struct drm_crtc *crtc;
7412         struct intel_crtc *intel_crtc;
7413
7414         if (!i915_powersave)
7415                 return;
7416
7417         mutex_lock(&dev->struct_mutex);
7418
7419         i915_update_gfx_val(dev_priv);
7420
7421         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7422                 /* Skip inactive CRTCs */
7423                 if (!crtc->fb)
7424                         continue;
7425
7426                 intel_crtc = to_intel_crtc(crtc);
7427                 if (!intel_crtc->busy)
7428                         intel_decrease_pllclock(crtc);
7429         }
7430
7431
7432         mutex_unlock(&dev->struct_mutex);
7433 }
7434
7435 /**
7436  * intel_mark_busy - mark the GPU and possibly the display busy
7437  * @dev: drm device
7438  * @obj: object we're operating on
7439  *
7440  * Callers can use this function to indicate that the GPU is busy processing
7441  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7442  * buffer), we'll also mark the display as busy, so we know to increase its
7443  * clock frequency.
7444  */
7445 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7446 {
7447         drm_i915_private_t *dev_priv = dev->dev_private;
7448         struct drm_crtc *crtc = NULL;
7449         struct intel_framebuffer *intel_fb;
7450         struct intel_crtc *intel_crtc;
7451
7452         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7453                 return;
7454
7455         if (!dev_priv->busy)
7456                 dev_priv->busy = true;
7457         else
7458                 mod_timer(&dev_priv->idle_timer, jiffies +
7459                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7460
7461         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7462                 if (!crtc->fb)
7463                         continue;
7464
7465                 intel_crtc = to_intel_crtc(crtc);
7466                 intel_fb = to_intel_framebuffer(crtc->fb);
7467                 if (intel_fb->obj == obj) {
7468                         if (!intel_crtc->busy) {
7469                                 /* Non-busy -> busy, upclock */
7470                                 intel_increase_pllclock(crtc);
7471                                 intel_crtc->busy = true;
7472                         } else {
7473                                 /* Busy -> busy, put off timer */
7474                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7475                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7476                         }
7477                 }
7478         }
7479 }
7480
7481 static void intel_crtc_destroy(struct drm_crtc *crtc)
7482 {
7483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7484         struct drm_device *dev = crtc->dev;
7485         struct intel_unpin_work *work;
7486         unsigned long flags;
7487
7488         spin_lock_irqsave(&dev->event_lock, flags);
7489         work = intel_crtc->unpin_work;
7490         intel_crtc->unpin_work = NULL;
7491         spin_unlock_irqrestore(&dev->event_lock, flags);
7492
7493         if (work) {
7494                 cancel_work_sync(&work->work);
7495                 kfree(work);
7496         }
7497
7498         drm_crtc_cleanup(crtc);
7499
7500         kfree(intel_crtc);
7501 }
7502
7503 static void intel_unpin_work_fn(struct work_struct *__work)
7504 {
7505         struct intel_unpin_work *work =
7506                 container_of(__work, struct intel_unpin_work, work);
7507
7508         mutex_lock(&work->dev->struct_mutex);
7509         intel_unpin_fb_obj(work->old_fb_obj);
7510         drm_gem_object_unreference(&work->pending_flip_obj->base);
7511         drm_gem_object_unreference(&work->old_fb_obj->base);
7512
7513         intel_update_fbc(work->dev);
7514         mutex_unlock(&work->dev->struct_mutex);
7515         kfree(work);
7516 }
7517
7518 static void do_intel_finish_page_flip(struct drm_device *dev,
7519                                       struct drm_crtc *crtc)
7520 {
7521         drm_i915_private_t *dev_priv = dev->dev_private;
7522         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7523         struct intel_unpin_work *work;
7524         struct drm_i915_gem_object *obj;
7525         struct drm_pending_vblank_event *e;
7526         struct timeval tnow, tvbl;
7527         unsigned long flags;
7528
7529         /* Ignore early vblank irqs */
7530         if (intel_crtc == NULL)
7531                 return;
7532
7533         do_gettimeofday(&tnow);
7534
7535         spin_lock_irqsave(&dev->event_lock, flags);
7536         work = intel_crtc->unpin_work;
7537         if (work == NULL || !work->pending) {
7538                 spin_unlock_irqrestore(&dev->event_lock, flags);
7539                 return;
7540         }
7541
7542         intel_crtc->unpin_work = NULL;
7543
7544         if (work->event) {
7545                 e = work->event;
7546                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7547
7548                 /* Called before vblank count and timestamps have
7549                  * been updated for the vblank interval of flip
7550                  * completion? Need to increment vblank count and
7551                  * add one videorefresh duration to returned timestamp
7552                  * to account for this. We assume this happened if we
7553                  * get called over 0.9 frame durations after the last
7554                  * timestamped vblank.
7555                  *
7556                  * This calculation can not be used with vrefresh rates
7557                  * below 5Hz (10Hz to be on the safe side) without
7558                  * promoting to 64 integers.
7559                  */
7560                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7561                     9 * crtc->framedur_ns) {
7562                         e->event.sequence++;
7563                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7564                                              crtc->framedur_ns);
7565                 }
7566
7567                 e->event.tv_sec = tvbl.tv_sec;
7568                 e->event.tv_usec = tvbl.tv_usec;
7569
7570                 list_add_tail(&e->base.link,
7571                               &e->base.file_priv->event_list);
7572                 wake_up_interruptible(&e->base.file_priv->event_wait);
7573         }
7574
7575         drm_vblank_put(dev, intel_crtc->pipe);
7576
7577         spin_unlock_irqrestore(&dev->event_lock, flags);
7578
7579         obj = work->old_fb_obj;
7580
7581         atomic_clear_mask(1 << intel_crtc->plane,
7582                           &obj->pending_flip.counter);
7583         if (atomic_read(&obj->pending_flip) == 0)
7584                 wake_up(&dev_priv->pending_flip_queue);
7585
7586         schedule_work(&work->work);
7587
7588         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7589 }
7590
7591 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7592 {
7593         drm_i915_private_t *dev_priv = dev->dev_private;
7594         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7595
7596         do_intel_finish_page_flip(dev, crtc);
7597 }
7598
7599 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7600 {
7601         drm_i915_private_t *dev_priv = dev->dev_private;
7602         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7603
7604         do_intel_finish_page_flip(dev, crtc);
7605 }
7606
7607 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7608 {
7609         drm_i915_private_t *dev_priv = dev->dev_private;
7610         struct intel_crtc *intel_crtc =
7611                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7612         unsigned long flags;
7613
7614         spin_lock_irqsave(&dev->event_lock, flags);
7615         if (intel_crtc->unpin_work) {
7616                 if ((++intel_crtc->unpin_work->pending) > 1)
7617                         DRM_ERROR("Prepared flip multiple times\n");
7618         } else {
7619                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7620         }
7621         spin_unlock_irqrestore(&dev->event_lock, flags);
7622 }
7623
7624 static int intel_gen2_queue_flip(struct drm_device *dev,
7625                                  struct drm_crtc *crtc,
7626                                  struct drm_framebuffer *fb,
7627                                  struct drm_i915_gem_object *obj)
7628 {
7629         struct drm_i915_private *dev_priv = dev->dev_private;
7630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7631         unsigned long offset;
7632         u32 flip_mask;
7633         int ret;
7634
7635         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7636         if (ret)
7637                 goto out;
7638
7639         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7640         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7641
7642         ret = BEGIN_LP_RING(6);
7643         if (ret)
7644                 goto out;
7645
7646         /* Can't queue multiple flips, so wait for the previous
7647          * one to finish before executing the next.
7648          */
7649         if (intel_crtc->plane)
7650                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7651         else
7652                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7653         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7654         OUT_RING(MI_NOOP);
7655         OUT_RING(MI_DISPLAY_FLIP |
7656                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7657         OUT_RING(fb->pitches[0]);
7658         OUT_RING(obj->gtt_offset + offset);
7659         OUT_RING(0); /* aux display base address, unused */
7660         ADVANCE_LP_RING();
7661 out:
7662         return ret;
7663 }
7664
7665 static int intel_gen3_queue_flip(struct drm_device *dev,
7666                                  struct drm_crtc *crtc,
7667                                  struct drm_framebuffer *fb,
7668                                  struct drm_i915_gem_object *obj)
7669 {
7670         struct drm_i915_private *dev_priv = dev->dev_private;
7671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7672         unsigned long offset;
7673         u32 flip_mask;
7674         int ret;
7675
7676         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7677         if (ret)
7678                 goto out;
7679
7680         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7681         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7682
7683         ret = BEGIN_LP_RING(6);
7684         if (ret)
7685                 goto out;
7686
7687         if (intel_crtc->plane)
7688                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7689         else
7690                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7691         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7692         OUT_RING(MI_NOOP);
7693         OUT_RING(MI_DISPLAY_FLIP_I915 |
7694                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7695         OUT_RING(fb->pitches[0]);
7696         OUT_RING(obj->gtt_offset + offset);
7697         OUT_RING(MI_NOOP);
7698
7699         ADVANCE_LP_RING();
7700 out:
7701         return ret;
7702 }
7703
7704 static int intel_gen4_queue_flip(struct drm_device *dev,
7705                                  struct drm_crtc *crtc,
7706                                  struct drm_framebuffer *fb,
7707                                  struct drm_i915_gem_object *obj)
7708 {
7709         struct drm_i915_private *dev_priv = dev->dev_private;
7710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7711         uint32_t pf, pipesrc;
7712         int ret;
7713
7714         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7715         if (ret)
7716                 goto out;
7717
7718         ret = BEGIN_LP_RING(4);
7719         if (ret)
7720                 goto out;
7721
7722         /* i965+ uses the linear or tiled offsets from the
7723          * Display Registers (which do not change across a page-flip)
7724          * so we need only reprogram the base address.
7725          */
7726         OUT_RING(MI_DISPLAY_FLIP |
7727                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7728         OUT_RING(fb->pitches[0]);
7729         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7730
7731         /* XXX Enabling the panel-fitter across page-flip is so far
7732          * untested on non-native modes, so ignore it for now.
7733          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7734          */
7735         pf = 0;
7736         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7737         OUT_RING(pf | pipesrc);
7738         ADVANCE_LP_RING();
7739 out:
7740         return ret;
7741 }
7742
7743 static int intel_gen6_queue_flip(struct drm_device *dev,
7744                                  struct drm_crtc *crtc,
7745                                  struct drm_framebuffer *fb,
7746                                  struct drm_i915_gem_object *obj)
7747 {
7748         struct drm_i915_private *dev_priv = dev->dev_private;
7749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7750         uint32_t pf, pipesrc;
7751         int ret;
7752
7753         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7754         if (ret)
7755                 goto out;
7756
7757         ret = BEGIN_LP_RING(4);
7758         if (ret)
7759                 goto out;
7760
7761         OUT_RING(MI_DISPLAY_FLIP |
7762                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7763         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7764         OUT_RING(obj->gtt_offset);
7765
7766         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7767         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7768         OUT_RING(pf | pipesrc);
7769         ADVANCE_LP_RING();
7770 out:
7771         return ret;
7772 }
7773
7774 /*
7775  * On gen7 we currently use the blit ring because (in early silicon at least)
7776  * the render ring doesn't give us interrpts for page flip completion, which
7777  * means clients will hang after the first flip is queued.  Fortunately the
7778  * blit ring generates interrupts properly, so use it instead.
7779  */
7780 static int intel_gen7_queue_flip(struct drm_device *dev,
7781                                  struct drm_crtc *crtc,
7782                                  struct drm_framebuffer *fb,
7783                                  struct drm_i915_gem_object *obj)
7784 {
7785         struct drm_i915_private *dev_priv = dev->dev_private;
7786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7787         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7788         int ret;
7789
7790         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7791         if (ret)
7792                 goto out;
7793
7794         ret = intel_ring_begin(ring, 4);
7795         if (ret)
7796                 goto out;
7797
7798         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7799         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7800         intel_ring_emit(ring, (obj->gtt_offset));
7801         intel_ring_emit(ring, (MI_NOOP));
7802         intel_ring_advance(ring);
7803 out:
7804         return ret;
7805 }
7806
7807 static int intel_default_queue_flip(struct drm_device *dev,
7808                                     struct drm_crtc *crtc,
7809                                     struct drm_framebuffer *fb,
7810                                     struct drm_i915_gem_object *obj)
7811 {
7812         return -ENODEV;
7813 }
7814
7815 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7816                                 struct drm_framebuffer *fb,
7817                                 struct drm_pending_vblank_event *event)
7818 {
7819         struct drm_device *dev = crtc->dev;
7820         struct drm_i915_private *dev_priv = dev->dev_private;
7821         struct intel_framebuffer *intel_fb;
7822         struct drm_i915_gem_object *obj;
7823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7824         struct intel_unpin_work *work;
7825         unsigned long flags;
7826         int ret;
7827
7828         work = kzalloc(sizeof *work, GFP_KERNEL);
7829         if (work == NULL)
7830                 return -ENOMEM;
7831
7832         work->event = event;
7833         work->dev = crtc->dev;
7834         intel_fb = to_intel_framebuffer(crtc->fb);
7835         work->old_fb_obj = intel_fb->obj;
7836         INIT_WORK(&work->work, intel_unpin_work_fn);
7837
7838         ret = drm_vblank_get(dev, intel_crtc->pipe);
7839         if (ret)
7840                 goto free_work;
7841
7842         /* We borrow the event spin lock for protecting unpin_work */
7843         spin_lock_irqsave(&dev->event_lock, flags);
7844         if (intel_crtc->unpin_work) {
7845                 spin_unlock_irqrestore(&dev->event_lock, flags);
7846                 kfree(work);
7847                 drm_vblank_put(dev, intel_crtc->pipe);
7848
7849                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7850                 return -EBUSY;
7851         }
7852         intel_crtc->unpin_work = work;
7853         spin_unlock_irqrestore(&dev->event_lock, flags);
7854
7855         intel_fb = to_intel_framebuffer(fb);
7856         obj = intel_fb->obj;
7857
7858         mutex_lock(&dev->struct_mutex);
7859
7860         /* Reference the objects for the scheduled work. */
7861         drm_gem_object_reference(&work->old_fb_obj->base);
7862         drm_gem_object_reference(&obj->base);
7863
7864         crtc->fb = fb;
7865
7866         work->pending_flip_obj = obj;
7867
7868         work->enable_stall_check = true;
7869
7870         /* Block clients from rendering to the new back buffer until
7871          * the flip occurs and the object is no longer visible.
7872          */
7873         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7874
7875         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7876         if (ret)
7877                 goto cleanup_pending;
7878
7879         intel_disable_fbc(dev);
7880         mutex_unlock(&dev->struct_mutex);
7881
7882         trace_i915_flip_request(intel_crtc->plane, obj);
7883
7884         return 0;
7885
7886 cleanup_pending:
7887         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7888         drm_gem_object_unreference(&work->old_fb_obj->base);
7889         drm_gem_object_unreference(&obj->base);
7890         mutex_unlock(&dev->struct_mutex);
7891
7892         spin_lock_irqsave(&dev->event_lock, flags);
7893         intel_crtc->unpin_work = NULL;
7894         spin_unlock_irqrestore(&dev->event_lock, flags);
7895
7896         drm_vblank_put(dev, intel_crtc->pipe);
7897 free_work:
7898         kfree(work);
7899
7900         return ret;
7901 }
7902
7903 static void intel_sanitize_modesetting(struct drm_device *dev,
7904                                        int pipe, int plane)
7905 {
7906         struct drm_i915_private *dev_priv = dev->dev_private;
7907         u32 reg, val;
7908
7909         /* Clear any frame start delays used for debugging left by the BIOS */
7910         for_each_pipe(pipe) {
7911                 reg = PIPECONF(pipe);
7912                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7913         }
7914
7915         if (HAS_PCH_SPLIT(dev))
7916                 return;
7917
7918         /* Who knows what state these registers were left in by the BIOS or
7919          * grub?
7920          *
7921          * If we leave the registers in a conflicting state (e.g. with the
7922          * display plane reading from the other pipe than the one we intend
7923          * to use) then when we attempt to teardown the active mode, we will
7924          * not disable the pipes and planes in the correct order -- leaving
7925          * a plane reading from a disabled pipe and possibly leading to
7926          * undefined behaviour.
7927          */
7928
7929         reg = DSPCNTR(plane);
7930         val = I915_READ(reg);
7931
7932         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7933                 return;
7934         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7935                 return;
7936
7937         /* This display plane is active and attached to the other CPU pipe. */
7938         pipe = !pipe;
7939
7940         /* Disable the plane and wait for it to stop reading from the pipe. */
7941         intel_disable_plane(dev_priv, plane, pipe);
7942         intel_disable_pipe(dev_priv, pipe);
7943 }
7944
7945 static void intel_crtc_reset(struct drm_crtc *crtc)
7946 {
7947         struct drm_device *dev = crtc->dev;
7948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7949
7950         /* Reset flags back to the 'unknown' status so that they
7951          * will be correctly set on the initial modeset.
7952          */
7953         intel_crtc->dpms_mode = -1;
7954
7955         /* We need to fix up any BIOS configuration that conflicts with
7956          * our expectations.
7957          */
7958         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7959 }
7960
7961 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7962         .dpms = intel_crtc_dpms,
7963         .mode_fixup = intel_crtc_mode_fixup,
7964         .mode_set = intel_crtc_mode_set,
7965         .mode_set_base = intel_pipe_set_base,
7966         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7967         .load_lut = intel_crtc_load_lut,
7968         .disable = intel_crtc_disable,
7969 };
7970
7971 static const struct drm_crtc_funcs intel_crtc_funcs = {
7972         .reset = intel_crtc_reset,
7973         .cursor_set = intel_crtc_cursor_set,
7974         .cursor_move = intel_crtc_cursor_move,
7975         .gamma_set = intel_crtc_gamma_set,
7976         .set_config = drm_crtc_helper_set_config,
7977         .destroy = intel_crtc_destroy,
7978         .page_flip = intel_crtc_page_flip,
7979 };
7980
7981 static void intel_crtc_init(struct drm_device *dev, int pipe)
7982 {
7983         drm_i915_private_t *dev_priv = dev->dev_private;
7984         struct intel_crtc *intel_crtc;
7985         int i;
7986
7987         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7988         if (intel_crtc == NULL)
7989                 return;
7990
7991         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7992
7993         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7994         for (i = 0; i < 256; i++) {
7995                 intel_crtc->lut_r[i] = i;
7996                 intel_crtc->lut_g[i] = i;
7997                 intel_crtc->lut_b[i] = i;
7998         }
7999
8000         /* Swap pipes & planes for FBC on pre-965 */
8001         intel_crtc->pipe = pipe;
8002         intel_crtc->plane = pipe;
8003         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8004                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8005                 intel_crtc->plane = !pipe;
8006         }
8007
8008         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8009                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8010         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8011         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8012
8013         intel_crtc_reset(&intel_crtc->base);
8014         intel_crtc->active = true; /* force the pipe off on setup_init_config */
8015         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8016
8017         if (HAS_PCH_SPLIT(dev)) {
8018                 if (pipe == 2 && IS_IVYBRIDGE(dev))
8019                         intel_crtc->no_pll = true;
8020                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
8021                 intel_helper_funcs.commit = ironlake_crtc_commit;
8022         } else {
8023                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
8024                 intel_helper_funcs.commit = i9xx_crtc_commit;
8025         }
8026
8027         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8028
8029         intel_crtc->busy = false;
8030
8031         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
8032                     (unsigned long)intel_crtc);
8033 }
8034
8035 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8036                                 struct drm_file *file)
8037 {
8038         drm_i915_private_t *dev_priv = dev->dev_private;
8039         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8040         struct drm_mode_object *drmmode_obj;
8041         struct intel_crtc *crtc;
8042
8043         if (!dev_priv) {
8044                 DRM_ERROR("called with no initialization\n");
8045                 return -EINVAL;
8046         }
8047
8048         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8049                         DRM_MODE_OBJECT_CRTC);
8050
8051         if (!drmmode_obj) {
8052                 DRM_ERROR("no such CRTC id\n");
8053                 return -EINVAL;
8054         }
8055
8056         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8057         pipe_from_crtc_id->pipe = crtc->pipe;
8058
8059         return 0;
8060 }
8061
8062 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
8063 {
8064         struct intel_encoder *encoder;
8065         int index_mask = 0;
8066         int entry = 0;
8067
8068         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8069                 if (type_mask & encoder->clone_mask)
8070                         index_mask |= (1 << entry);
8071                 entry++;
8072         }
8073
8074         return index_mask;
8075 }
8076
8077 static bool has_edp_a(struct drm_device *dev)
8078 {
8079         struct drm_i915_private *dev_priv = dev->dev_private;
8080
8081         if (!IS_MOBILE(dev))
8082                 return false;
8083
8084         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8085                 return false;
8086
8087         if (IS_GEN5(dev) &&
8088             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8089                 return false;
8090
8091         return true;
8092 }
8093
8094 static void intel_setup_outputs(struct drm_device *dev)
8095 {
8096         struct drm_i915_private *dev_priv = dev->dev_private;
8097         struct intel_encoder *encoder;
8098         bool dpd_is_edp = false;
8099         bool has_lvds;
8100
8101         has_lvds = intel_lvds_init(dev);
8102         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8103                 /* disable the panel fitter on everything but LVDS */
8104                 I915_WRITE(PFIT_CONTROL, 0);
8105         }
8106
8107         if (HAS_PCH_SPLIT(dev)) {
8108                 dpd_is_edp = intel_dpd_is_edp(dev);
8109
8110                 if (has_edp_a(dev))
8111                         intel_dp_init(dev, DP_A);
8112
8113                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8114                         intel_dp_init(dev, PCH_DP_D);
8115         }
8116
8117         intel_crt_init(dev);
8118
8119         if (HAS_PCH_SPLIT(dev)) {
8120                 int found;
8121
8122                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8123                         /* PCH SDVOB multiplex with HDMIB */
8124                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8125                         if (!found)
8126                                 intel_hdmi_init(dev, HDMIB);
8127                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8128                                 intel_dp_init(dev, PCH_DP_B);
8129                 }
8130
8131                 if (I915_READ(HDMIC) & PORT_DETECTED)
8132                         intel_hdmi_init(dev, HDMIC);
8133
8134                 if (I915_READ(HDMID) & PORT_DETECTED)
8135                         intel_hdmi_init(dev, HDMID);
8136
8137                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8138                         intel_dp_init(dev, PCH_DP_C);
8139
8140                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8141                         intel_dp_init(dev, PCH_DP_D);
8142
8143         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8144                 bool found = false;
8145
8146                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8147                         DRM_DEBUG_KMS("probing SDVOB\n");
8148                         found = intel_sdvo_init(dev, SDVOB, true);
8149                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8150                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8151                                 intel_hdmi_init(dev, SDVOB);
8152                         }
8153
8154                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8155                                 DRM_DEBUG_KMS("probing DP_B\n");
8156                                 intel_dp_init(dev, DP_B);
8157                         }
8158                 }
8159
8160                 /* Before G4X SDVOC doesn't have its own detect register */
8161
8162                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8163                         DRM_DEBUG_KMS("probing SDVOC\n");
8164                         found = intel_sdvo_init(dev, SDVOC, false);
8165                 }
8166
8167                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8168
8169                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8170                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8171                                 intel_hdmi_init(dev, SDVOC);
8172                         }
8173                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8174                                 DRM_DEBUG_KMS("probing DP_C\n");
8175                                 intel_dp_init(dev, DP_C);
8176                         }
8177                 }
8178
8179                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8180                     (I915_READ(DP_D) & DP_DETECTED)) {
8181                         DRM_DEBUG_KMS("probing DP_D\n");
8182                         intel_dp_init(dev, DP_D);
8183                 }
8184         } else if (IS_GEN2(dev))
8185                 intel_dvo_init(dev);
8186
8187         if (SUPPORTS_TV(dev))
8188                 intel_tv_init(dev);
8189
8190         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8191                 encoder->base.possible_crtcs = encoder->crtc_mask;
8192                 encoder->base.possible_clones =
8193                         intel_encoder_clones(dev, encoder->clone_mask);
8194         }
8195
8196         /* disable all the possible outputs/crtcs before entering KMS mode */
8197         drm_helper_disable_unused_functions(dev);
8198
8199         if (HAS_PCH_SPLIT(dev))
8200                 ironlake_init_pch_refclk(dev);
8201 }
8202
8203 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8204 {
8205         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8206
8207         drm_framebuffer_cleanup(fb);
8208         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8209
8210         kfree(intel_fb);
8211 }
8212
8213 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8214                                                 struct drm_file *file,
8215                                                 unsigned int *handle)
8216 {
8217         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8218         struct drm_i915_gem_object *obj = intel_fb->obj;
8219
8220         return drm_gem_handle_create(file, &obj->base, handle);
8221 }
8222
8223 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8224         .destroy = intel_user_framebuffer_destroy,
8225         .create_handle = intel_user_framebuffer_create_handle,
8226 };
8227
8228 int intel_framebuffer_init(struct drm_device *dev,
8229                            struct intel_framebuffer *intel_fb,
8230                            struct drm_mode_fb_cmd2 *mode_cmd,
8231                            struct drm_i915_gem_object *obj)
8232 {
8233         int ret;
8234
8235         if (obj->tiling_mode == I915_TILING_Y)
8236                 return -EINVAL;
8237
8238         if (mode_cmd->pitches[0] & 63)
8239                 return -EINVAL;
8240
8241         switch (mode_cmd->pixel_format) {
8242         case DRM_FORMAT_RGB332:
8243         case DRM_FORMAT_RGB565:
8244         case DRM_FORMAT_XRGB8888:
8245         case DRM_FORMAT_XBGR8888:
8246         case DRM_FORMAT_ARGB8888:
8247         case DRM_FORMAT_XRGB2101010:
8248         case DRM_FORMAT_ARGB2101010:
8249                 /* RGB formats are common across chipsets */
8250                 break;
8251         case DRM_FORMAT_YUYV:
8252         case DRM_FORMAT_UYVY:
8253         case DRM_FORMAT_YVYU:
8254         case DRM_FORMAT_VYUY:
8255                 break;
8256         default:
8257                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8258                                 mode_cmd->pixel_format);
8259                 return -EINVAL;
8260         }
8261
8262         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8263         if (ret) {
8264                 DRM_ERROR("framebuffer init failed %d\n", ret);
8265                 return ret;
8266         }
8267
8268         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8269         intel_fb->obj = obj;
8270         return 0;
8271 }
8272
8273 static struct drm_framebuffer *
8274 intel_user_framebuffer_create(struct drm_device *dev,
8275                               struct drm_file *filp,
8276                               struct drm_mode_fb_cmd2 *mode_cmd)
8277 {
8278         struct drm_i915_gem_object *obj;
8279
8280         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8281                                                 mode_cmd->handles[0]));
8282         if (&obj->base == NULL)
8283                 return ERR_PTR(-ENOENT);
8284
8285         return intel_framebuffer_create(dev, mode_cmd, obj);
8286 }
8287
8288 static const struct drm_mode_config_funcs intel_mode_funcs = {
8289         .fb_create = intel_user_framebuffer_create,
8290         .output_poll_changed = intel_fb_output_poll_changed,
8291 };
8292
8293 static struct drm_i915_gem_object *
8294 intel_alloc_context_page(struct drm_device *dev)
8295 {
8296         struct drm_i915_gem_object *ctx;
8297         int ret;
8298
8299         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8300
8301         ctx = i915_gem_alloc_object(dev, 4096);
8302         if (!ctx) {
8303                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8304                 return NULL;
8305         }
8306
8307         ret = i915_gem_object_pin(ctx, 4096, true);
8308         if (ret) {
8309                 DRM_ERROR("failed to pin power context: %d\n", ret);
8310                 goto err_unref;
8311         }
8312
8313         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8314         if (ret) {
8315                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8316                 goto err_unpin;
8317         }
8318
8319         return ctx;
8320
8321 err_unpin:
8322         i915_gem_object_unpin(ctx);
8323 err_unref:
8324         drm_gem_object_unreference(&ctx->base);
8325         mutex_unlock(&dev->struct_mutex);
8326         return NULL;
8327 }
8328
8329 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8330 {
8331         struct drm_i915_private *dev_priv = dev->dev_private;
8332         u16 rgvswctl;
8333
8334         rgvswctl = I915_READ16(MEMSWCTL);
8335         if (rgvswctl & MEMCTL_CMD_STS) {
8336                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8337                 return false; /* still busy with another command */
8338         }
8339
8340         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8341                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8342         I915_WRITE16(MEMSWCTL, rgvswctl);
8343         POSTING_READ16(MEMSWCTL);
8344
8345         rgvswctl |= MEMCTL_CMD_STS;
8346         I915_WRITE16(MEMSWCTL, rgvswctl);
8347
8348         return true;
8349 }
8350
8351 void ironlake_enable_drps(struct drm_device *dev)
8352 {
8353         struct drm_i915_private *dev_priv = dev->dev_private;
8354         u32 rgvmodectl = I915_READ(MEMMODECTL);
8355         u8 fmax, fmin, fstart, vstart;
8356
8357         /* Enable temp reporting */
8358         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8359         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8360
8361         /* 100ms RC evaluation intervals */
8362         I915_WRITE(RCUPEI, 100000);
8363         I915_WRITE(RCDNEI, 100000);
8364
8365         /* Set max/min thresholds to 90ms and 80ms respectively */
8366         I915_WRITE(RCBMAXAVG, 90000);
8367         I915_WRITE(RCBMINAVG, 80000);
8368
8369         I915_WRITE(MEMIHYST, 1);
8370
8371         /* Set up min, max, and cur for interrupt handling */
8372         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8373         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8374         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8375                 MEMMODE_FSTART_SHIFT;
8376
8377         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8378                 PXVFREQ_PX_SHIFT;
8379
8380         dev_priv->fmax = fmax; /* IPS callback will increase this */
8381         dev_priv->fstart = fstart;
8382
8383         dev_priv->max_delay = fstart;
8384         dev_priv->min_delay = fmin;
8385         dev_priv->cur_delay = fstart;
8386
8387         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8388                          fmax, fmin, fstart);
8389
8390         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8391
8392         /*
8393          * Interrupts will be enabled in ironlake_irq_postinstall
8394          */
8395
8396         I915_WRITE(VIDSTART, vstart);
8397         POSTING_READ(VIDSTART);
8398
8399         rgvmodectl |= MEMMODE_SWMODE_EN;
8400         I915_WRITE(MEMMODECTL, rgvmodectl);
8401
8402         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8403                 DRM_ERROR("stuck trying to change perf mode\n");
8404         msleep(1);
8405
8406         ironlake_set_drps(dev, fstart);
8407
8408         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8409                 I915_READ(0x112e0);
8410         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8411         dev_priv->last_count2 = I915_READ(0x112f4);
8412         getrawmonotonic(&dev_priv->last_time2);
8413 }
8414
8415 void ironlake_disable_drps(struct drm_device *dev)
8416 {
8417         struct drm_i915_private *dev_priv = dev->dev_private;
8418         u16 rgvswctl = I915_READ16(MEMSWCTL);
8419
8420         /* Ack interrupts, disable EFC interrupt */
8421         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8422         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8423         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8424         I915_WRITE(DEIIR, DE_PCU_EVENT);
8425         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8426
8427         /* Go back to the starting frequency */
8428         ironlake_set_drps(dev, dev_priv->fstart);
8429         msleep(1);
8430         rgvswctl |= MEMCTL_CMD_STS;
8431         I915_WRITE(MEMSWCTL, rgvswctl);
8432         msleep(1);
8433
8434 }
8435
8436 void gen6_set_rps(struct drm_device *dev, u8 val)
8437 {
8438         struct drm_i915_private *dev_priv = dev->dev_private;
8439         u32 swreq;
8440
8441         swreq = (val & 0x3ff) << 25;
8442         I915_WRITE(GEN6_RPNSWREQ, swreq);
8443 }
8444
8445 void gen6_disable_rps(struct drm_device *dev)
8446 {
8447         struct drm_i915_private *dev_priv = dev->dev_private;
8448
8449         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8450         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8451         I915_WRITE(GEN6_PMIER, 0);
8452         /* Complete PM interrupt masking here doesn't race with the rps work
8453          * item again unmasking PM interrupts because that is using a different
8454          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8455          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8456
8457         spin_lock_irq(&dev_priv->rps_lock);
8458         dev_priv->pm_iir = 0;
8459         spin_unlock_irq(&dev_priv->rps_lock);
8460
8461         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8462 }
8463
8464 static unsigned long intel_pxfreq(u32 vidfreq)
8465 {
8466         unsigned long freq;
8467         int div = (vidfreq & 0x3f0000) >> 16;
8468         int post = (vidfreq & 0x3000) >> 12;
8469         int pre = (vidfreq & 0x7);
8470
8471         if (!pre)
8472                 return 0;
8473
8474         freq = ((div * 133333) / ((1<<post) * pre));
8475
8476         return freq;
8477 }
8478
8479 void intel_init_emon(struct drm_device *dev)
8480 {
8481         struct drm_i915_private *dev_priv = dev->dev_private;
8482         u32 lcfuse;
8483         u8 pxw[16];
8484         int i;
8485
8486         /* Disable to program */
8487         I915_WRITE(ECR, 0);
8488         POSTING_READ(ECR);
8489
8490         /* Program energy weights for various events */
8491         I915_WRITE(SDEW, 0x15040d00);
8492         I915_WRITE(CSIEW0, 0x007f0000);
8493         I915_WRITE(CSIEW1, 0x1e220004);
8494         I915_WRITE(CSIEW2, 0x04000004);
8495
8496         for (i = 0; i < 5; i++)
8497                 I915_WRITE(PEW + (i * 4), 0);
8498         for (i = 0; i < 3; i++)
8499                 I915_WRITE(DEW + (i * 4), 0);
8500
8501         /* Program P-state weights to account for frequency power adjustment */
8502         for (i = 0; i < 16; i++) {
8503                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8504                 unsigned long freq = intel_pxfreq(pxvidfreq);
8505                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8506                         PXVFREQ_PX_SHIFT;
8507                 unsigned long val;
8508
8509                 val = vid * vid;
8510                 val *= (freq / 1000);
8511                 val *= 255;
8512                 val /= (127*127*900);
8513                 if (val > 0xff)
8514                         DRM_ERROR("bad pxval: %ld\n", val);
8515                 pxw[i] = val;
8516         }
8517         /* Render standby states get 0 weight */
8518         pxw[14] = 0;
8519         pxw[15] = 0;
8520
8521         for (i = 0; i < 4; i++) {
8522                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8523                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8524                 I915_WRITE(PXW + (i * 4), val);
8525         }
8526
8527         /* Adjust magic regs to magic values (more experimental results) */
8528         I915_WRITE(OGW0, 0);
8529         I915_WRITE(OGW1, 0);
8530         I915_WRITE(EG0, 0x00007f00);
8531         I915_WRITE(EG1, 0x0000000e);
8532         I915_WRITE(EG2, 0x000e0000);
8533         I915_WRITE(EG3, 0x68000300);
8534         I915_WRITE(EG4, 0x42000000);
8535         I915_WRITE(EG5, 0x00140031);
8536         I915_WRITE(EG6, 0);
8537         I915_WRITE(EG7, 0);
8538
8539         for (i = 0; i < 8; i++)
8540                 I915_WRITE(PXWL + (i * 4), 0);
8541
8542         /* Enable PMON + select events */
8543         I915_WRITE(ECR, 0x80000019);
8544
8545         lcfuse = I915_READ(LCFUSE02);
8546
8547         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8548 }
8549
8550 static int intel_enable_rc6(struct drm_device *dev)
8551 {
8552         /*
8553          * Respect the kernel parameter if it is set
8554          */
8555         if (i915_enable_rc6 >= 0)
8556                 return i915_enable_rc6;
8557
8558         /*
8559          * Disable RC6 on Ironlake
8560          */
8561         if (INTEL_INFO(dev)->gen == 5)
8562                 return 0;
8563
8564         /*
8565          * Disable rc6 on Sandybridge
8566          */
8567         if (INTEL_INFO(dev)->gen == 6) {
8568                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8569                 return INTEL_RC6_ENABLE;
8570         }
8571         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8572         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8573 }
8574
8575 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8576 {
8577         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8578         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8579         u32 pcu_mbox, rc6_mask = 0;
8580         u32 gtfifodbg;
8581         int cur_freq, min_freq, max_freq;
8582         int rc6_mode;
8583         int i;
8584
8585         /* Here begins a magic sequence of register writes to enable
8586          * auto-downclocking.
8587          *
8588          * Perhaps there might be some value in exposing these to
8589          * userspace...
8590          */
8591         I915_WRITE(GEN6_RC_STATE, 0);
8592         mutex_lock(&dev_priv->dev->struct_mutex);
8593
8594         /* Clear the DBG now so we don't confuse earlier errors */
8595         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8596                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8597                 I915_WRITE(GTFIFODBG, gtfifodbg);
8598         }
8599
8600         gen6_gt_force_wake_get(dev_priv);
8601
8602         /* disable the counters and set deterministic thresholds */
8603         I915_WRITE(GEN6_RC_CONTROL, 0);
8604
8605         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8606         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8607         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8608         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8609         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8610
8611         for (i = 0; i < I915_NUM_RINGS; i++)
8612                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8613
8614         I915_WRITE(GEN6_RC_SLEEP, 0);
8615         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8616         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8617         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8618         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8619
8620         rc6_mode = intel_enable_rc6(dev_priv->dev);
8621         if (rc6_mode & INTEL_RC6_ENABLE)
8622                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8623
8624         if (rc6_mode & INTEL_RC6p_ENABLE)
8625                 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8626
8627         if (rc6_mode & INTEL_RC6pp_ENABLE)
8628                 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8629
8630         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8631                         (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8632                         (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8633                         (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
8634
8635         I915_WRITE(GEN6_RC_CONTROL,
8636                    rc6_mask |
8637                    GEN6_RC_CTL_EI_MODE(1) |
8638                    GEN6_RC_CTL_HW_ENABLE);
8639
8640         I915_WRITE(GEN6_RPNSWREQ,
8641                    GEN6_FREQUENCY(10) |
8642                    GEN6_OFFSET(0) |
8643                    GEN6_AGGRESSIVE_TURBO);
8644         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8645                    GEN6_FREQUENCY(12));
8646
8647         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8648         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8649                    18 << 24 |
8650                    6 << 16);
8651         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8652         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8653         I915_WRITE(GEN6_RP_UP_EI, 100000);
8654         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8655         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8656         I915_WRITE(GEN6_RP_CONTROL,
8657                    GEN6_RP_MEDIA_TURBO |
8658                    GEN6_RP_MEDIA_HW_MODE |
8659                    GEN6_RP_MEDIA_IS_GFX |
8660                    GEN6_RP_ENABLE |
8661                    GEN6_RP_UP_BUSY_AVG |
8662                    GEN6_RP_DOWN_IDLE_CONT);
8663
8664         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8665                      500))
8666                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8667
8668         I915_WRITE(GEN6_PCODE_DATA, 0);
8669         I915_WRITE(GEN6_PCODE_MAILBOX,
8670                    GEN6_PCODE_READY |
8671                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8672         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8673                      500))
8674                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8675
8676         min_freq = (rp_state_cap & 0xff0000) >> 16;
8677         max_freq = rp_state_cap & 0xff;
8678         cur_freq = (gt_perf_status & 0xff00) >> 8;
8679
8680         /* Check for overclock support */
8681         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8682                      500))
8683                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8684         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8685         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8686         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8687                      500))
8688                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8689         if (pcu_mbox & (1<<31)) { /* OC supported */
8690                 max_freq = pcu_mbox & 0xff;
8691                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8692         }
8693
8694         /* In units of 100MHz */
8695         dev_priv->max_delay = max_freq;
8696         dev_priv->min_delay = min_freq;
8697         dev_priv->cur_delay = cur_freq;
8698
8699         /* requires MSI enabled */
8700         I915_WRITE(GEN6_PMIER,
8701                    GEN6_PM_MBOX_EVENT |
8702                    GEN6_PM_THERMAL_EVENT |
8703                    GEN6_PM_RP_DOWN_TIMEOUT |
8704                    GEN6_PM_RP_UP_THRESHOLD |
8705                    GEN6_PM_RP_DOWN_THRESHOLD |
8706                    GEN6_PM_RP_UP_EI_EXPIRED |
8707                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8708         spin_lock_irq(&dev_priv->rps_lock);
8709         WARN_ON(dev_priv->pm_iir != 0);
8710         I915_WRITE(GEN6_PMIMR, 0);
8711         spin_unlock_irq(&dev_priv->rps_lock);
8712         /* enable all PM interrupts */
8713         I915_WRITE(GEN6_PMINTRMSK, 0);
8714
8715         gen6_gt_force_wake_put(dev_priv);
8716         mutex_unlock(&dev_priv->dev->struct_mutex);
8717 }
8718
8719 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8720 {
8721         int min_freq = 15;
8722         int gpu_freq, ia_freq, max_ia_freq;
8723         int scaling_factor = 180;
8724
8725         max_ia_freq = cpufreq_quick_get_max(0);
8726         /*
8727          * Default to measured freq if none found, PCU will ensure we don't go
8728          * over
8729          */
8730         if (!max_ia_freq)
8731                 max_ia_freq = tsc_khz;
8732
8733         /* Convert from kHz to MHz */
8734         max_ia_freq /= 1000;
8735
8736         mutex_lock(&dev_priv->dev->struct_mutex);
8737
8738         /*
8739          * For each potential GPU frequency, load a ring frequency we'd like
8740          * to use for memory access.  We do this by specifying the IA frequency
8741          * the PCU should use as a reference to determine the ring frequency.
8742          */
8743         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8744              gpu_freq--) {
8745                 int diff = dev_priv->max_delay - gpu_freq;
8746
8747                 /*
8748                  * For GPU frequencies less than 750MHz, just use the lowest
8749                  * ring freq.
8750                  */
8751                 if (gpu_freq < min_freq)
8752                         ia_freq = 800;
8753                 else
8754                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8755                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8756
8757                 I915_WRITE(GEN6_PCODE_DATA,
8758                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8759                            gpu_freq);
8760                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8761                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8762                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8763                               GEN6_PCODE_READY) == 0, 10)) {
8764                         DRM_ERROR("pcode write of freq table timed out\n");
8765                         continue;
8766                 }
8767         }
8768
8769         mutex_unlock(&dev_priv->dev->struct_mutex);
8770 }
8771
8772 static void ironlake_init_clock_gating(struct drm_device *dev)
8773 {
8774         struct drm_i915_private *dev_priv = dev->dev_private;
8775         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8776
8777         /* Required for FBC */
8778         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8779                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8780                 DPFDUNIT_CLOCK_GATE_DISABLE;
8781         /* Required for CxSR */
8782         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8783
8784         I915_WRITE(PCH_3DCGDIS0,
8785                    MARIUNIT_CLOCK_GATE_DISABLE |
8786                    SVSMUNIT_CLOCK_GATE_DISABLE);
8787         I915_WRITE(PCH_3DCGDIS1,
8788                    VFMUNIT_CLOCK_GATE_DISABLE);
8789
8790         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8791
8792         /*
8793          * According to the spec the following bits should be set in
8794          * order to enable memory self-refresh
8795          * The bit 22/21 of 0x42004
8796          * The bit 5 of 0x42020
8797          * The bit 15 of 0x45000
8798          */
8799         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8800                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8801                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8802         I915_WRITE(ILK_DSPCLK_GATE,
8803                    (I915_READ(ILK_DSPCLK_GATE) |
8804                     ILK_DPARB_CLK_GATE));
8805         I915_WRITE(DISP_ARB_CTL,
8806                    (I915_READ(DISP_ARB_CTL) |
8807                     DISP_FBC_WM_DIS));
8808         I915_WRITE(WM3_LP_ILK, 0);
8809         I915_WRITE(WM2_LP_ILK, 0);
8810         I915_WRITE(WM1_LP_ILK, 0);
8811
8812         /*
8813          * Based on the document from hardware guys the following bits
8814          * should be set unconditionally in order to enable FBC.
8815          * The bit 22 of 0x42000
8816          * The bit 22 of 0x42004
8817          * The bit 7,8,9 of 0x42020.
8818          */
8819         if (IS_IRONLAKE_M(dev)) {
8820                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8821                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8822                            ILK_FBCQ_DIS);
8823                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8824                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8825                            ILK_DPARB_GATE);
8826                 I915_WRITE(ILK_DSPCLK_GATE,
8827                            I915_READ(ILK_DSPCLK_GATE) |
8828                            ILK_DPFC_DIS1 |
8829                            ILK_DPFC_DIS2 |
8830                            ILK_CLK_FBC);
8831         }
8832
8833         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8834                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8835                    ILK_ELPIN_409_SELECT);
8836         I915_WRITE(_3D_CHICKEN2,
8837                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8838                    _3D_CHICKEN2_WM_READ_PIPELINED);
8839 }
8840
8841 static void gen6_init_clock_gating(struct drm_device *dev)
8842 {
8843         struct drm_i915_private *dev_priv = dev->dev_private;
8844         int pipe;
8845         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8846
8847         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8848
8849         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8850                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8851                    ILK_ELPIN_409_SELECT);
8852
8853         I915_WRITE(WM3_LP_ILK, 0);
8854         I915_WRITE(WM2_LP_ILK, 0);
8855         I915_WRITE(WM1_LP_ILK, 0);
8856
8857         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8858          * gating disable must be set.  Failure to set it results in
8859          * flickering pixels due to Z write ordering failures after
8860          * some amount of runtime in the Mesa "fire" demo, and Unigine
8861          * Sanctuary and Tropics, and apparently anything else with
8862          * alpha test or pixel discard.
8863          *
8864          * According to the spec, bit 11 (RCCUNIT) must also be set,
8865          * but we didn't debug actual testcases to find it out.
8866          */
8867         I915_WRITE(GEN6_UCGCTL2,
8868                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8869                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8870
8871         /*
8872          * According to the spec the following bits should be
8873          * set in order to enable memory self-refresh and fbc:
8874          * The bit21 and bit22 of 0x42000
8875          * The bit21 and bit22 of 0x42004
8876          * The bit5 and bit7 of 0x42020
8877          * The bit14 of 0x70180
8878          * The bit14 of 0x71180
8879          */
8880         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8881                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8882                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8883         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8884                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8885                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8886         I915_WRITE(ILK_DSPCLK_GATE,
8887                    I915_READ(ILK_DSPCLK_GATE) |
8888                    ILK_DPARB_CLK_GATE  |
8889                    ILK_DPFD_CLK_GATE);
8890
8891         for_each_pipe(pipe) {
8892                 I915_WRITE(DSPCNTR(pipe),
8893                            I915_READ(DSPCNTR(pipe)) |
8894                            DISPPLANE_TRICKLE_FEED_DISABLE);
8895                 intel_flush_display_plane(dev_priv, pipe);
8896         }
8897 }
8898
8899 static void ivybridge_init_clock_gating(struct drm_device *dev)
8900 {
8901         struct drm_i915_private *dev_priv = dev->dev_private;
8902         int pipe;
8903         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8904
8905         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8906
8907         I915_WRITE(WM3_LP_ILK, 0);
8908         I915_WRITE(WM2_LP_ILK, 0);
8909         I915_WRITE(WM1_LP_ILK, 0);
8910
8911         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8912          * This implements the WaDisableRCZUnitClockGating workaround.
8913          */
8914         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8915
8916         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8917
8918         I915_WRITE(IVB_CHICKEN3,
8919                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8920                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8921
8922         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8923         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8924                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8925
8926         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8927         I915_WRITE(GEN7_L3CNTLREG1,
8928                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8929         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8930                         GEN7_WA_L3_CHICKEN_MODE);
8931
8932         /* This is required by WaCatErrorRejectionIssue */
8933         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8934                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8935                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8936
8937         for_each_pipe(pipe) {
8938                 I915_WRITE(DSPCNTR(pipe),
8939                            I915_READ(DSPCNTR(pipe)) |
8940                            DISPPLANE_TRICKLE_FEED_DISABLE);
8941                 intel_flush_display_plane(dev_priv, pipe);
8942         }
8943 }
8944
8945 static void valleyview_init_clock_gating(struct drm_device *dev)
8946 {
8947         struct drm_i915_private *dev_priv = dev->dev_private;
8948         int pipe;
8949         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8950
8951         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8952
8953         I915_WRITE(WM3_LP_ILK, 0);
8954         I915_WRITE(WM2_LP_ILK, 0);
8955         I915_WRITE(WM1_LP_ILK, 0);
8956
8957         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8958          * This implements the WaDisableRCZUnitClockGating workaround.
8959          */
8960         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8961
8962         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8963
8964         I915_WRITE(IVB_CHICKEN3,
8965                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8966                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8967
8968         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8969         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8970                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8971
8972         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8973         I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
8974         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
8975
8976         /* This is required by WaCatErrorRejectionIssue */
8977         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8978                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8979                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8980
8981         for_each_pipe(pipe) {
8982                 I915_WRITE(DSPCNTR(pipe),
8983                            I915_READ(DSPCNTR(pipe)) |
8984                            DISPPLANE_TRICKLE_FEED_DISABLE);
8985                 intel_flush_display_plane(dev_priv, pipe);
8986         }
8987
8988         I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
8989                    (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
8990                    PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
8991 }
8992
8993 static void g4x_init_clock_gating(struct drm_device *dev)
8994 {
8995         struct drm_i915_private *dev_priv = dev->dev_private;
8996         uint32_t dspclk_gate;
8997
8998         I915_WRITE(RENCLK_GATE_D1, 0);
8999         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
9000                    GS_UNIT_CLOCK_GATE_DISABLE |
9001                    CL_UNIT_CLOCK_GATE_DISABLE);
9002         I915_WRITE(RAMCLK_GATE_D, 0);
9003         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
9004                 OVRUNIT_CLOCK_GATE_DISABLE |
9005                 OVCUNIT_CLOCK_GATE_DISABLE;
9006         if (IS_GM45(dev))
9007                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
9008         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
9009 }
9010
9011 static void crestline_init_clock_gating(struct drm_device *dev)
9012 {
9013         struct drm_i915_private *dev_priv = dev->dev_private;
9014
9015         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
9016         I915_WRITE(RENCLK_GATE_D2, 0);
9017         I915_WRITE(DSPCLK_GATE_D, 0);
9018         I915_WRITE(RAMCLK_GATE_D, 0);
9019         I915_WRITE16(DEUC, 0);
9020 }
9021
9022 static void broadwater_init_clock_gating(struct drm_device *dev)
9023 {
9024         struct drm_i915_private *dev_priv = dev->dev_private;
9025
9026         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
9027                    I965_RCC_CLOCK_GATE_DISABLE |
9028                    I965_RCPB_CLOCK_GATE_DISABLE |
9029                    I965_ISC_CLOCK_GATE_DISABLE |
9030                    I965_FBC_CLOCK_GATE_DISABLE);
9031         I915_WRITE(RENCLK_GATE_D2, 0);
9032 }
9033
9034 static void gen3_init_clock_gating(struct drm_device *dev)
9035 {
9036         struct drm_i915_private *dev_priv = dev->dev_private;
9037         u32 dstate = I915_READ(D_STATE);
9038
9039         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
9040                 DSTATE_DOT_CLOCK_GATING;
9041         I915_WRITE(D_STATE, dstate);
9042 }
9043
9044 static void i85x_init_clock_gating(struct drm_device *dev)
9045 {
9046         struct drm_i915_private *dev_priv = dev->dev_private;
9047
9048         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
9049 }
9050
9051 static void i830_init_clock_gating(struct drm_device *dev)
9052 {
9053         struct drm_i915_private *dev_priv = dev->dev_private;
9054
9055         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
9056 }
9057
9058 static void ibx_init_clock_gating(struct drm_device *dev)
9059 {
9060         struct drm_i915_private *dev_priv = dev->dev_private;
9061
9062         /*
9063          * On Ibex Peak and Cougar Point, we need to disable clock
9064          * gating for the panel power sequencer or it will fail to
9065          * start up when no ports are active.
9066          */
9067         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
9068 }
9069
9070 static void cpt_init_clock_gating(struct drm_device *dev)
9071 {
9072         struct drm_i915_private *dev_priv = dev->dev_private;
9073         int pipe;
9074
9075         /*
9076          * On Ibex Peak and Cougar Point, we need to disable clock
9077          * gating for the panel power sequencer or it will fail to
9078          * start up when no ports are active.
9079          */
9080         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
9081         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
9082                    DPLS_EDP_PPS_FIX_DIS);
9083         /* Without this, mode sets may fail silently on FDI */
9084         for_each_pipe(pipe)
9085                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
9086 }
9087
9088 static void ironlake_teardown_rc6(struct drm_device *dev)
9089 {
9090         struct drm_i915_private *dev_priv = dev->dev_private;
9091
9092         if (dev_priv->renderctx) {
9093                 i915_gem_object_unpin(dev_priv->renderctx);
9094                 drm_gem_object_unreference(&dev_priv->renderctx->base);
9095                 dev_priv->renderctx = NULL;
9096         }
9097
9098         if (dev_priv->pwrctx) {
9099                 i915_gem_object_unpin(dev_priv->pwrctx);
9100                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
9101                 dev_priv->pwrctx = NULL;
9102         }
9103 }
9104
9105 static void ironlake_disable_rc6(struct drm_device *dev)
9106 {
9107         struct drm_i915_private *dev_priv = dev->dev_private;
9108
9109         if (I915_READ(PWRCTXA)) {
9110                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
9111                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
9112                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
9113                          50);
9114
9115                 I915_WRITE(PWRCTXA, 0);
9116                 POSTING_READ(PWRCTXA);
9117
9118                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
9119                 POSTING_READ(RSTDBYCTL);
9120         }
9121
9122         ironlake_teardown_rc6(dev);
9123 }
9124
9125 static int ironlake_setup_rc6(struct drm_device *dev)
9126 {
9127         struct drm_i915_private *dev_priv = dev->dev_private;
9128
9129         if (dev_priv->renderctx == NULL)
9130                 dev_priv->renderctx = intel_alloc_context_page(dev);
9131         if (!dev_priv->renderctx)
9132                 return -ENOMEM;
9133
9134         if (dev_priv->pwrctx == NULL)
9135                 dev_priv->pwrctx = intel_alloc_context_page(dev);
9136         if (!dev_priv->pwrctx) {
9137                 ironlake_teardown_rc6(dev);
9138                 return -ENOMEM;
9139         }
9140
9141         return 0;
9142 }
9143
9144 void ironlake_enable_rc6(struct drm_device *dev)
9145 {
9146         struct drm_i915_private *dev_priv = dev->dev_private;
9147         int ret;
9148
9149         /* rc6 disabled by default due to repeated reports of hanging during
9150          * boot and resume.
9151          */
9152         if (!intel_enable_rc6(dev))
9153                 return;
9154
9155         mutex_lock(&dev->struct_mutex);
9156         ret = ironlake_setup_rc6(dev);
9157         if (ret) {
9158                 mutex_unlock(&dev->struct_mutex);
9159                 return;
9160         }
9161
9162         /*
9163          * GPU can automatically power down the render unit if given a page
9164          * to save state.
9165          */
9166         ret = BEGIN_LP_RING(6);
9167         if (ret) {
9168                 ironlake_teardown_rc6(dev);
9169                 mutex_unlock(&dev->struct_mutex);
9170                 return;
9171         }
9172
9173         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
9174         OUT_RING(MI_SET_CONTEXT);
9175         OUT_RING(dev_priv->renderctx->gtt_offset |
9176                  MI_MM_SPACE_GTT |
9177                  MI_SAVE_EXT_STATE_EN |
9178                  MI_RESTORE_EXT_STATE_EN |
9179                  MI_RESTORE_INHIBIT);
9180         OUT_RING(MI_SUSPEND_FLUSH);
9181         OUT_RING(MI_NOOP);
9182         OUT_RING(MI_FLUSH);
9183         ADVANCE_LP_RING();
9184
9185         /*
9186          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
9187          * does an implicit flush, combined with MI_FLUSH above, it should be
9188          * safe to assume that renderctx is valid
9189          */
9190         ret = intel_wait_ring_idle(LP_RING(dev_priv));
9191         if (ret) {
9192                 DRM_ERROR("failed to enable ironlake power power savings\n");
9193                 ironlake_teardown_rc6(dev);
9194                 mutex_unlock(&dev->struct_mutex);
9195                 return;
9196         }
9197
9198         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
9199         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
9200         mutex_unlock(&dev->struct_mutex);
9201 }
9202
9203 void intel_init_clock_gating(struct drm_device *dev)
9204 {
9205         struct drm_i915_private *dev_priv = dev->dev_private;
9206
9207         dev_priv->display.init_clock_gating(dev);
9208
9209         if (dev_priv->display.init_pch_clock_gating)
9210                 dev_priv->display.init_pch_clock_gating(dev);
9211 }
9212
9213 /* Set up chip specific display functions */
9214 static void intel_init_display(struct drm_device *dev)
9215 {
9216         struct drm_i915_private *dev_priv = dev->dev_private;
9217
9218         /* We always want a DPMS function */
9219         if (HAS_PCH_SPLIT(dev)) {
9220                 dev_priv->display.dpms = ironlake_crtc_dpms;
9221                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9222                 dev_priv->display.update_plane = ironlake_update_plane;
9223         } else {
9224                 dev_priv->display.dpms = i9xx_crtc_dpms;
9225                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9226                 dev_priv->display.update_plane = i9xx_update_plane;
9227         }
9228
9229         if (I915_HAS_FBC(dev)) {
9230                 if (HAS_PCH_SPLIT(dev)) {
9231                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
9232                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
9233                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
9234                 } else if (IS_GM45(dev)) {
9235                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
9236                         dev_priv->display.enable_fbc = g4x_enable_fbc;
9237                         dev_priv->display.disable_fbc = g4x_disable_fbc;
9238                 } else if (IS_CRESTLINE(dev)) {
9239                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
9240                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
9241                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
9242                 }
9243                 /* 855GM needs testing */
9244         }
9245
9246         /* Returns the core display clock speed */
9247         if (IS_VALLEYVIEW(dev))
9248                 dev_priv->display.get_display_clock_speed =
9249                         valleyview_get_display_clock_speed;
9250         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9251                 dev_priv->display.get_display_clock_speed =
9252                         i945_get_display_clock_speed;
9253         else if (IS_I915G(dev))
9254                 dev_priv->display.get_display_clock_speed =
9255                         i915_get_display_clock_speed;
9256         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9257                 dev_priv->display.get_display_clock_speed =
9258                         i9xx_misc_get_display_clock_speed;
9259         else if (IS_I915GM(dev))
9260                 dev_priv->display.get_display_clock_speed =
9261                         i915gm_get_display_clock_speed;
9262         else if (IS_I865G(dev))
9263                 dev_priv->display.get_display_clock_speed =
9264                         i865_get_display_clock_speed;
9265         else if (IS_I85X(dev))
9266                 dev_priv->display.get_display_clock_speed =
9267                         i855_get_display_clock_speed;
9268         else /* 852, 830 */
9269                 dev_priv->display.get_display_clock_speed =
9270                         i830_get_display_clock_speed;
9271
9272         /* For FIFO watermark updates */
9273         if (HAS_PCH_SPLIT(dev)) {
9274                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9275                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9276
9277                 /* IVB configs may use multi-threaded forcewake */
9278                 if (IS_IVYBRIDGE(dev)) {
9279                         u32     ecobus;
9280
9281                         /* A small trick here - if the bios hasn't configured MT forcewake,
9282                          * and if the device is in RC6, then force_wake_mt_get will not wake
9283                          * the device and the ECOBUS read will return zero. Which will be
9284                          * (correctly) interpreted by the test below as MT forcewake being
9285                          * disabled.
9286                          */
9287                         mutex_lock(&dev->struct_mutex);
9288                         __gen6_gt_force_wake_mt_get(dev_priv);
9289                         ecobus = I915_READ_NOTRACE(ECOBUS);
9290                         __gen6_gt_force_wake_mt_put(dev_priv);
9291                         mutex_unlock(&dev->struct_mutex);
9292
9293                         if (ecobus & FORCEWAKE_MT_ENABLE) {
9294                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9295                                 dev_priv->display.force_wake_get =
9296                                         __gen6_gt_force_wake_mt_get;
9297                                 dev_priv->display.force_wake_put =
9298                                         __gen6_gt_force_wake_mt_put;
9299                         }
9300                 }
9301
9302                 if (HAS_PCH_IBX(dev))
9303                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9304                 else if (HAS_PCH_CPT(dev))
9305                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9306
9307                 if (IS_GEN5(dev)) {
9308                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9309                                 dev_priv->display.update_wm = ironlake_update_wm;
9310                         else {
9311                                 DRM_DEBUG_KMS("Failed to get proper latency. "
9312                                               "Disable CxSR\n");
9313                                 dev_priv->display.update_wm = NULL;
9314                         }
9315                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9316                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
9317                         dev_priv->display.write_eld = ironlake_write_eld;
9318                 } else if (IS_GEN6(dev)) {
9319                         if (SNB_READ_WM0_LATENCY()) {
9320                                 dev_priv->display.update_wm = sandybridge_update_wm;
9321                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9322                         } else {
9323                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9324                                               "Disable CxSR\n");
9325                                 dev_priv->display.update_wm = NULL;
9326                         }
9327                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9328                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9329                         dev_priv->display.write_eld = ironlake_write_eld;
9330                 } else if (IS_IVYBRIDGE(dev)) {
9331                         /* FIXME: detect B0+ stepping and use auto training */
9332                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9333                         if (SNB_READ_WM0_LATENCY()) {
9334                                 dev_priv->display.update_wm = sandybridge_update_wm;
9335                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9336                         } else {
9337                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9338                                               "Disable CxSR\n");
9339                                 dev_priv->display.update_wm = NULL;
9340                         }
9341                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9342                         dev_priv->display.write_eld = ironlake_write_eld;
9343                 } else
9344                         dev_priv->display.update_wm = NULL;
9345         } else if (IS_VALLEYVIEW(dev)) {
9346                 dev_priv->display.update_wm = valleyview_update_wm;
9347                 dev_priv->display.init_clock_gating =
9348                         valleyview_init_clock_gating;
9349                 dev_priv->display.force_wake_get = vlv_force_wake_get;
9350                 dev_priv->display.force_wake_put = vlv_force_wake_put;
9351         } else if (IS_PINEVIEW(dev)) {
9352                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9353                                             dev_priv->is_ddr3,
9354                                             dev_priv->fsb_freq,
9355                                             dev_priv->mem_freq)) {
9356                         DRM_INFO("failed to find known CxSR latency "
9357                                  "(found ddr%s fsb freq %d, mem freq %d), "
9358                                  "disabling CxSR\n",
9359                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9360                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9361                         /* Disable CxSR and never update its watermark again */
9362                         pineview_disable_cxsr(dev);
9363                         dev_priv->display.update_wm = NULL;
9364                 } else
9365                         dev_priv->display.update_wm = pineview_update_wm;
9366                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9367         } else if (IS_G4X(dev)) {
9368                 dev_priv->display.write_eld = g4x_write_eld;
9369                 dev_priv->display.update_wm = g4x_update_wm;
9370                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9371         } else if (IS_GEN4(dev)) {
9372                 dev_priv->display.update_wm = i965_update_wm;
9373                 if (IS_CRESTLINE(dev))
9374                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9375                 else if (IS_BROADWATER(dev))
9376                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9377         } else if (IS_GEN3(dev)) {
9378                 dev_priv->display.update_wm = i9xx_update_wm;
9379                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9380                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9381         } else if (IS_I865G(dev)) {
9382                 dev_priv->display.update_wm = i830_update_wm;
9383                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9384                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9385         } else if (IS_I85X(dev)) {
9386                 dev_priv->display.update_wm = i9xx_update_wm;
9387                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9388                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9389         } else {
9390                 dev_priv->display.update_wm = i830_update_wm;
9391                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9392                 if (IS_845G(dev))
9393                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9394                 else
9395                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9396         }
9397
9398         /* Default just returns -ENODEV to indicate unsupported */
9399         dev_priv->display.queue_flip = intel_default_queue_flip;
9400
9401         switch (INTEL_INFO(dev)->gen) {
9402         case 2:
9403                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9404                 break;
9405
9406         case 3:
9407                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9408                 break;
9409
9410         case 4:
9411         case 5:
9412                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9413                 break;
9414
9415         case 6:
9416                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9417                 break;
9418         case 7:
9419                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9420                 break;
9421         }
9422 }
9423
9424 /*
9425  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9426  * resume, or other times.  This quirk makes sure that's the case for
9427  * affected systems.
9428  */
9429 static void quirk_pipea_force(struct drm_device *dev)
9430 {
9431         struct drm_i915_private *dev_priv = dev->dev_private;
9432
9433         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9434         DRM_INFO("applying pipe a force quirk\n");
9435 }
9436
9437 /*
9438  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9439  */
9440 static void quirk_ssc_force_disable(struct drm_device *dev)
9441 {
9442         struct drm_i915_private *dev_priv = dev->dev_private;
9443         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9444         DRM_INFO("applying lvds SSC disable quirk\n");
9445 }
9446
9447 /*
9448  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9449  * brightness value
9450  */
9451 static void quirk_invert_brightness(struct drm_device *dev)
9452 {
9453         struct drm_i915_private *dev_priv = dev->dev_private;
9454         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9455         DRM_INFO("applying inverted panel brightness quirk\n");
9456 }
9457
9458 struct intel_quirk {
9459         int device;
9460         int subsystem_vendor;
9461         int subsystem_device;
9462         void (*hook)(struct drm_device *dev);
9463 };
9464
9465 struct intel_quirk intel_quirks[] = {
9466         /* HP Mini needs pipe A force quirk (LP: #322104) */
9467         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9468
9469         /* Thinkpad R31 needs pipe A force quirk */
9470         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9471         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9472         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9473
9474         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9475         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9476         /* ThinkPad X40 needs pipe A force quirk */
9477
9478         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9479         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9480
9481         /* 855 & before need to leave pipe A & dpll A up */
9482         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9483         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9484
9485         /* Lenovo U160 cannot use SSC on LVDS */
9486         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9487
9488         /* Sony Vaio Y cannot use SSC on LVDS */
9489         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9490
9491         /* Acer Aspire 5734Z must invert backlight brightness */
9492         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9493 };
9494
9495 static void intel_init_quirks(struct drm_device *dev)
9496 {
9497         struct pci_dev *d = dev->pdev;
9498         int i;
9499
9500         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9501                 struct intel_quirk *q = &intel_quirks[i];
9502
9503                 if (d->device == q->device &&
9504                     (d->subsystem_vendor == q->subsystem_vendor ||
9505                      q->subsystem_vendor == PCI_ANY_ID) &&
9506                     (d->subsystem_device == q->subsystem_device ||
9507                      q->subsystem_device == PCI_ANY_ID))
9508                         q->hook(dev);
9509         }
9510 }
9511
9512 /* Disable the VGA plane that we never use */
9513 static void i915_disable_vga(struct drm_device *dev)
9514 {
9515         struct drm_i915_private *dev_priv = dev->dev_private;
9516         u8 sr1;
9517         u32 vga_reg;
9518
9519         if (HAS_PCH_SPLIT(dev))
9520                 vga_reg = CPU_VGACNTRL;
9521         else
9522                 vga_reg = VGACNTRL;
9523
9524         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9525         outb(1, VGA_SR_INDEX);
9526         sr1 = inb(VGA_SR_DATA);
9527         outb(sr1 | 1<<5, VGA_SR_DATA);
9528         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9529         udelay(300);
9530
9531         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9532         POSTING_READ(vga_reg);
9533 }
9534
9535 void intel_modeset_init(struct drm_device *dev)
9536 {
9537         struct drm_i915_private *dev_priv = dev->dev_private;
9538         int i, ret;
9539
9540         drm_mode_config_init(dev);
9541
9542         dev->mode_config.min_width = 0;
9543         dev->mode_config.min_height = 0;
9544
9545         dev->mode_config.preferred_depth = 24;
9546         dev->mode_config.prefer_shadow = 1;
9547
9548         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9549
9550         intel_init_quirks(dev);
9551
9552         intel_init_display(dev);
9553
9554         if (IS_GEN2(dev)) {
9555                 dev->mode_config.max_width = 2048;
9556                 dev->mode_config.max_height = 2048;
9557         } else if (IS_GEN3(dev)) {
9558                 dev->mode_config.max_width = 4096;
9559                 dev->mode_config.max_height = 4096;
9560         } else {
9561                 dev->mode_config.max_width = 8192;
9562                 dev->mode_config.max_height = 8192;
9563         }
9564         dev->mode_config.fb_base = dev->agp->base;
9565
9566         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9567                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9568
9569         for (i = 0; i < dev_priv->num_pipe; i++) {
9570                 intel_crtc_init(dev, i);
9571                 ret = intel_plane_init(dev, i);
9572                 if (ret)
9573                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9574         }
9575
9576         /* Just disable it once at startup */
9577         i915_disable_vga(dev);
9578         intel_setup_outputs(dev);
9579
9580         intel_init_clock_gating(dev);
9581
9582         if (IS_IRONLAKE_M(dev)) {
9583                 ironlake_enable_drps(dev);
9584                 intel_init_emon(dev);
9585         }
9586
9587         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9588                 gen6_enable_rps(dev_priv);
9589                 gen6_update_ring_freq(dev_priv);
9590         }
9591
9592         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9593         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9594                     (unsigned long)dev);
9595 }
9596
9597 void intel_modeset_gem_init(struct drm_device *dev)
9598 {
9599         if (IS_IRONLAKE_M(dev))
9600                 ironlake_enable_rc6(dev);
9601
9602         intel_setup_overlay(dev);
9603 }
9604
9605 void intel_modeset_cleanup(struct drm_device *dev)
9606 {
9607         struct drm_i915_private *dev_priv = dev->dev_private;
9608         struct drm_crtc *crtc;
9609         struct intel_crtc *intel_crtc;
9610
9611         drm_kms_helper_poll_fini(dev);
9612         mutex_lock(&dev->struct_mutex);
9613
9614         intel_unregister_dsm_handler();
9615
9616
9617         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9618                 /* Skip inactive CRTCs */
9619                 if (!crtc->fb)
9620                         continue;
9621
9622                 intel_crtc = to_intel_crtc(crtc);
9623                 intel_increase_pllclock(crtc);
9624         }
9625
9626         intel_disable_fbc(dev);
9627
9628         if (IS_IRONLAKE_M(dev))
9629                 ironlake_disable_drps(dev);
9630         if (IS_GEN6(dev) || IS_GEN7(dev))
9631                 gen6_disable_rps(dev);
9632
9633         if (IS_IRONLAKE_M(dev))
9634                 ironlake_disable_rc6(dev);
9635
9636         if (IS_VALLEYVIEW(dev))
9637                 vlv_init_dpio(dev);
9638
9639         mutex_unlock(&dev->struct_mutex);
9640
9641         /* Disable the irq before mode object teardown, for the irq might
9642          * enqueue unpin/hotplug work. */
9643         drm_irq_uninstall(dev);
9644         cancel_work_sync(&dev_priv->hotplug_work);
9645         cancel_work_sync(&dev_priv->rps_work);
9646
9647         /* flush any delayed tasks or pending work */
9648         flush_scheduled_work();
9649
9650         /* Shut off idle work before the crtcs get freed. */
9651         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9652                 intel_crtc = to_intel_crtc(crtc);
9653                 del_timer_sync(&intel_crtc->idle_timer);
9654         }
9655         del_timer_sync(&dev_priv->idle_timer);
9656         cancel_work_sync(&dev_priv->idle_work);
9657
9658         drm_mode_config_cleanup(dev);
9659 }
9660
9661 /*
9662  * Return which encoder is currently attached for connector.
9663  */
9664 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9665 {
9666         return &intel_attached_encoder(connector)->base;
9667 }
9668
9669 void intel_connector_attach_encoder(struct intel_connector *connector,
9670                                     struct intel_encoder *encoder)
9671 {
9672         connector->encoder = encoder;
9673         drm_mode_connector_attach_encoder(&connector->base,
9674                                           &encoder->base);
9675 }
9676
9677 /*
9678  * set vga decode state - true == enable VGA decode
9679  */
9680 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9681 {
9682         struct drm_i915_private *dev_priv = dev->dev_private;
9683         u16 gmch_ctrl;
9684
9685         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9686         if (state)
9687                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9688         else
9689                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9690         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9691         return 0;
9692 }
9693
9694 #ifdef CONFIG_DEBUG_FS
9695 #include <linux/seq_file.h>
9696
9697 struct intel_display_error_state {
9698         struct intel_cursor_error_state {
9699                 u32 control;
9700                 u32 position;
9701                 u32 base;
9702                 u32 size;
9703         } cursor[2];
9704
9705         struct intel_pipe_error_state {
9706                 u32 conf;
9707                 u32 source;
9708
9709                 u32 htotal;
9710                 u32 hblank;
9711                 u32 hsync;
9712                 u32 vtotal;
9713                 u32 vblank;
9714                 u32 vsync;
9715         } pipe[2];
9716
9717         struct intel_plane_error_state {
9718                 u32 control;
9719                 u32 stride;
9720                 u32 size;
9721                 u32 pos;
9722                 u32 addr;
9723                 u32 surface;
9724                 u32 tile_offset;
9725         } plane[2];
9726 };
9727
9728 struct intel_display_error_state *
9729 intel_display_capture_error_state(struct drm_device *dev)
9730 {
9731         drm_i915_private_t *dev_priv = dev->dev_private;
9732         struct intel_display_error_state *error;
9733         int i;
9734
9735         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9736         if (error == NULL)
9737                 return NULL;
9738
9739         for (i = 0; i < 2; i++) {
9740                 error->cursor[i].control = I915_READ(CURCNTR(i));
9741                 error->cursor[i].position = I915_READ(CURPOS(i));
9742                 error->cursor[i].base = I915_READ(CURBASE(i));
9743
9744                 error->plane[i].control = I915_READ(DSPCNTR(i));
9745                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9746                 error->plane[i].size = I915_READ(DSPSIZE(i));
9747                 error->plane[i].pos = I915_READ(DSPPOS(i));
9748                 error->plane[i].addr = I915_READ(DSPADDR(i));
9749                 if (INTEL_INFO(dev)->gen >= 4) {
9750                         error->plane[i].surface = I915_READ(DSPSURF(i));
9751                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9752                 }
9753
9754                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9755                 error->pipe[i].source = I915_READ(PIPESRC(i));
9756                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9757                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9758                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9759                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9760                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9761                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9762         }
9763
9764         return error;
9765 }
9766
9767 void
9768 intel_display_print_error_state(struct seq_file *m,
9769                                 struct drm_device *dev,
9770                                 struct intel_display_error_state *error)
9771 {
9772         int i;
9773
9774         for (i = 0; i < 2; i++) {
9775                 seq_printf(m, "Pipe [%d]:\n", i);
9776                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9777                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9778                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9779                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9780                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9781                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9782                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9783                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9784
9785                 seq_printf(m, "Plane [%d]:\n", i);
9786                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9787                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9788                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9789                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9790                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9791                 if (INTEL_INFO(dev)->gen >= 4) {
9792                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9793                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9794                 }
9795
9796                 seq_printf(m, "Cursor [%d]:\n", i);
9797                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9798                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9799                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9800         }
9801 }
9802 #endif