drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  51                                    struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dac = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_dvo = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 2, .max = 33 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 4, .p2_fast = 4 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i8xx_lvds = {
 119         .dot = { .min = 25000, .max = 350000 },
 120         .vco = { .min = 930000, .max = 1400000 },
 121         .n = { .min = 3, .max = 16 },
 122         .m = { .min = 96, .max = 140 },
 123         .m1 = { .min = 18, .max = 26 },
 124         .m2 = { .min = 6, .max = 16 },
 125         .p = { .min = 4, .max = 128 },
 126         .p1 = { .min = 1, .max = 6 },
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 14, .p2_fast = 7 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_sdvo = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 5, .max = 80 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 200000,
 141                 .p2_slow = 10, .p2_fast = 5 },
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_lvds = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 8, .max = 18 },
 150         .m2 = { .min = 3, .max = 7 },
 151         .p = { .min = 7, .max = 98 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 112000,
 154                 .p2_slow = 14, .p2_fast = 7 },
 155 };
 156
 157
 158 static const intel_limit_t intel_limits_g4x_sdvo = {
 159         .dot = { .min = 25000, .max = 270000 },
 160         .vco = { .min = 1750000, .max = 3500000},
 161         .n = { .min = 1, .max = 4 },
 162         .m = { .min = 104, .max = 138 },
 163         .m1 = { .min = 17, .max = 23 },
 164         .m2 = { .min = 5, .max = 11 },
 165         .p = { .min = 10, .max = 30 },
 166         .p1 = { .min = 1, .max = 3},
 167         .p2 = { .dot_limit = 270000,
 168                 .p2_slow = 10,
 169                 .p2_fast = 10
 170         },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_hdmi = {
 174         .dot = { .min = 22000, .max = 400000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 16, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 5, .max = 80 },
 181         .p1 = { .min = 1, .max = 8},
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 10, .p2_fast = 5 },
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 187         .dot = { .min = 20000, .max = 115000 },
 188         .vco = { .min = 1750000, .max = 3500000 },
 189         .n = { .min = 1, .max = 3 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 17, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 28, .max = 112 },
 194         .p1 = { .min = 2, .max = 8 },
 195         .p2 = { .dot_limit = 0,
 196                 .p2_slow = 14, .p2_fast = 14
 197         },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 201         .dot = { .min = 80000, .max = 224000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 14, .max = 42 },
 208         .p1 = { .min = 2, .max = 6 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 7, .p2_fast = 7
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_pineview_sdvo = {
 215         .dot = { .min = 20000, .max = 400000},
 216         .vco = { .min = 1700000, .max = 3500000 },
 217         /* Pineview's Ncounter is a ring counter */
 218         .n = { .min = 3, .max = 6 },
 219         .m = { .min = 2, .max = 256 },
 220         /* Pineview only has one combined m divider, which we treat as m2. */
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 5, .max = 80 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 200000,
 226                 .p2_slow = 10, .p2_fast = 5 },
 227 };
 228
 229 static const intel_limit_t intel_limits_pineview_lvds = {
 230         .dot = { .min = 20000, .max = 400000 },
 231         .vco = { .min = 1700000, .max = 3500000 },
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         .m1 = { .min = 0, .max = 0 },
 235         .m2 = { .min = 0, .max = 254 },
 236         .p = { .min = 7, .max = 112 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 112000,
 239                 .p2_slow = 14, .p2_fast = 14 },
 240 };
 241
 242 /* Ironlake / Sandybridge
 243  *
 244  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 245  * the range value for them is (actual_value - 2).
 246  */
 247 static const intel_limit_t intel_limits_ironlake_dac = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 5 },
 251         .m = { .min = 79, .max = 127 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 5, .max = 80 },
 255         .p1 = { .min = 1, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 10, .p2_fast = 5 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 118 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 28, .max = 112 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271 };
 272
 273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 3 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 14, .max = 56 },
 281         .p1 = { .min = 2, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 7, .p2_fast = 7 },
 284 };
 285
 286 /* LVDS 100mhz refclk limits. */
 287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 2 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 126 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 42 },
 308         .p1 = { .min = 2, .max = 6 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_dac = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 22, .max = 450 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 1, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_hdmi = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 60, .max = 300 }, /* guess */
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 2, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 340                                                 int refclk)
 341 {
 342         struct drm_device *dev = crtc->dev;
 343         const intel_limit_t *limit;
 344
 345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 346                 if (intel_is_dual_link_lvds(dev)) {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_dual_lvds;
 351                 } else {
 352                         if (refclk == 100000)
 353                                 limit = &intel_limits_ironlake_single_lvds_100m;
 354                         else
 355                                 limit = &intel_limits_ironlake_single_lvds;
 356                 }
 357         } else
 358                 limit = &intel_limits_ironlake_dac;
 359
 360         return limit;
 361 }
 362
 363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         const intel_limit_t *limit;
 367
 368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 369                 if (intel_is_dual_link_lvds(dev))
 370                         limit = &intel_limits_g4x_dual_channel_lvds;
 371                 else
 372                         limit = &intel_limits_g4x_single_channel_lvds;
 373         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 374                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 375                 limit = &intel_limits_g4x_hdmi;
 376         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 377                 limit = &intel_limits_g4x_sdvo;
 378         } else /* The option is for other outputs */
 379                 limit = &intel_limits_i9xx_sdvo;
 380
 381         return limit;
 382 }
 383
 384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 385 {
 386         struct drm_device *dev = crtc->dev;
 387         const intel_limit_t *limit;
 388
 389         if (HAS_PCH_SPLIT(dev))
 390                 limit = intel_ironlake_limit(crtc, refclk);
 391         else if (IS_G4X(dev)) {
 392                 limit = intel_g4x_limit(crtc);
 393         } else if (IS_PINEVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 395                         limit = &intel_limits_pineview_lvds;
 396                 else
 397                         limit = &intel_limits_pineview_sdvo;
 398         } else if (IS_VALLEYVIEW(dev)) {
 399                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 400                         limit = &intel_limits_vlv_dac;
 401                 else
 402                         limit = &intel_limits_vlv_hdmi;
 403         } else if (!IS_GEN2(dev)) {
 404                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 405                         limit = &intel_limits_i9xx_lvds;
 406                 else
 407                         limit = &intel_limits_i9xx_sdvo;
 408         } else {
 409                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 410                         limit = &intel_limits_i8xx_lvds;
 411                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 412                         limit = &intel_limits_i8xx_dvo;
 413                 else
 414                         limit = &intel_limits_i8xx_dac;
 415         }
 416         return limit;
 417 }
 418
 419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 420 static void pineview_clock(int refclk, intel_clock_t *clock)
 421 {
 422         clock->m = clock->m2 + 2;
 423         clock->p = clock->p1 * clock->p2;
 424         clock->vco = refclk * clock->m / clock->n;
 425         clock->dot = clock->vco / clock->p;
 426 }
 427
 428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 429 {
 430         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 431 }
 432
 433 static void i9xx_clock(int refclk, intel_clock_t *clock)
 434 {
 435         clock->m = i9xx_dpll_compute_m(clock);
 436         clock->p = clock->p1 * clock->p2;
 437         clock->vco = refclk * clock->m / (clock->n + 2);
 438         clock->dot = clock->vco / clock->p;
 439 }
 440
 441 /**
 442  * Returns whether any output on the specified pipe is of the specified type
 443  */
 444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 445 {
 446         struct drm_device *dev = crtc->dev;
 447         struct intel_encoder *encoder;
 448
 449         for_each_encoder_on_crtc(dev, crtc, encoder)
 450                 if (encoder->type == type)
 451                         return true;
 452
 453         return false;
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 467                 INTELPllInvalid("p1 out of range\n");
 468         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 469                 INTELPllInvalid("p out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 475                 INTELPllInvalid("m1 <= m2\n");
 476         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 477                 INTELPllInvalid("m out of range\n");
 478         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 479                 INTELPllInvalid("n out of range\n");
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 674         u32 m, n, fastclk;
 675         u32 updrate, minupdate, p;
 676         unsigned long bestppm, ppm, absppm;
 677         int dotclk, flag;
 678
 679         flag = 0;
 680         dotclk = target * 1000;
 681         bestppm = 1000000;
 682         ppm = absppm = 0;
 683         fastclk = dotclk / (2*100);
 684         updrate = 0;
 685         minupdate = 19200;
 686         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 687         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 688
 689         /* based on hardware requirement, prefer smaller n to precision */
 690         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 691                 updrate = refclk / n;
 692                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 693                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 694                                 if (p2 > 10)
 695                                         p2 = p2 - 1;
 696                                 p = p1 * p2;
 697                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 698                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 699                                         m2 = (((2*(fastclk * p * n / m1 )) +
 700                                                refclk) / (2*refclk));
 701                                         m = m1 * m2;
 702                                         vco = updrate * m;
 703                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 704                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 705                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 706                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 707                                                         bestppm = 0;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (absppm < bestppm - 10) {
 711                                                         bestppm = absppm;
 712                                                         flag = 1;
 713                                                 }
 714                                                 if (flag) {
 715                                                         bestn = n;
 716                                                         bestm1 = m1;
 717                                                         bestm2 = m2;
 718                                                         bestp1 = p1;
 719                                                         bestp2 = p2;
 720                                                         flag = 0;
 721                                                 }
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727         best_clock->n = bestn;
 728         best_clock->m1 = bestm1;
 729         best_clock->m2 = bestm2;
 730         best_clock->p1 = bestp1;
 731         best_clock->p2 = bestp2;
 732
 733         return true;
 734 }
 735
 736 bool intel_crtc_active(struct drm_crtc *crtc)
 737 {
 738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 739
 740         /* Be paranoid as we can arrive here with only partial
 741          * state retrieved from the hardware during setup.
 742          *
 743          * We can ditch the adjusted_mode.clock check as soon
 744          * as Haswell has gained clock readout/fastboot support.
 745          *
 746          * We can ditch the crtc->fb check as soon as we can
 747          * properly reconstruct framebuffers.
 748          */
 749         return intel_crtc->active && crtc->fb &&
 750                 intel_crtc->config.adjusted_mode.clock;
 751 }
 752
 753 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 754                                              enum pipe pipe)
 755 {
 756         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 758
 759         return intel_crtc->config.cpu_transcoder;
 760 }
 761
 762 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         u32 frame, frame_reg = PIPEFRAME(pipe);
 766
 767         frame = I915_READ(frame_reg);
 768
 769         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 770                 DRM_DEBUG_KMS("vblank wait timed out\n");
 771 }
 772
 773 /**
 774  * intel_wait_for_vblank - wait for vblank on a given pipe
 775  * @dev: drm device
 776  * @pipe: pipe to wait for
 777  *
 778  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 779  * mode setting code.
 780  */
 781 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         int pipestat_reg = PIPESTAT(pipe);
 785
 786         if (INTEL_INFO(dev)->gen >= 5) {
 787                 ironlake_wait_for_vblank(dev, pipe);
 788                 return;
 789         }
 790
 791         /* Clear existing vblank status. Note this will clear any other
 792          * sticky status fields as well.
 793          *
 794          * This races with i915_driver_irq_handler() with the result
 795          * that either function could miss a vblank event.  Here it is not
 796          * fatal, as we will either wait upon the next vblank interrupt or
 797          * timeout.  Generally speaking intel_wait_for_vblank() is only
 798          * called during modeset at which time the GPU should be idle and
 799          * should *not* be performing page flips and thus not waiting on
 800          * vblanks...
 801          * Currently, the result of us stealing a vblank from the irq
 802          * handler is that a single frame will be skipped during swapbuffers.
 803          */
 804         I915_WRITE(pipestat_reg,
 805                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 806
 807         /* Wait for vblank interrupt bit to set */
 808         if (wait_for(I915_READ(pipestat_reg) &
 809                      PIPE_VBLANK_INTERRUPT_STATUS,
 810                      50))
 811                 DRM_DEBUG_KMS("vblank wait timed out\n");
 812 }
 813
 814 /*
 815  * intel_wait_for_pipe_off - wait for pipe to turn off
 816  * @dev: drm device
 817  * @pipe: pipe to wait for
 818  *
 819  * After disabling a pipe, we can't wait for vblank in the usual way,
 820  * spinning on the vblank interrupt status bit, since we won't actually
 821  * see an interrupt when the pipe is disabled.
 822  *
 823  * On Gen4 and above:
 824  *   wait for the pipe register state bit to turn off
 825  *
 826  * Otherwise:
 827  *   wait for the display line value to settle (it usually
 828  *   ends up stopping at the start of the next frame).
 829  *
 830  */
 831 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 832 {
 833         struct drm_i915_private *dev_priv = dev->dev_private;
 834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 835                                                                       pipe);
 836
 837         if (INTEL_INFO(dev)->gen >= 4) {
 838                 int reg = PIPECONF(cpu_transcoder);
 839
 840                 /* Wait for the Pipe State to go off */
 841                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 842                              100))
 843                         WARN(1, "pipe_off wait timed out\n");
 844         } else {
 845                 u32 last_line, line_mask;
 846                 int reg = PIPEDSL(pipe);
 847                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 848
 849                 if (IS_GEN2(dev))
 850                         line_mask = DSL_LINEMASK_GEN2;
 851                 else
 852                         line_mask = DSL_LINEMASK_GEN3;
 853
 854                 /* Wait for the display line to settle */
 855                 do {
 856                         last_line = I915_READ(reg) & line_mask;
 857                         mdelay(5);
 858                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 859                          time_after(timeout, jiffies));
 860                 if (time_after(jiffies, timeout))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         if (HAS_PCH_LPT(dev_priv->dev)) {
1220                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221                 return;
1222         }
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void vlv_enable_pll(struct intel_crtc *crtc)
1364 {
1365         struct drm_device *dev = crtc->base.dev;
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         int reg = DPLL(crtc->pipe);
1368         u32 dpll = crtc->config.dpll_hw_state.dpll;
1369
1370         assert_pipe_disabled(dev_priv, crtc->pipe);
1371
1372         /* No really, not for ILK+ */
1373         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375         /* PLL is protected by panel, make sure we can write it */
1376         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1377                 assert_panel_unlocked(dev_priv, crtc->pipe);
1378
1379         I915_WRITE(reg, dpll);
1380         POSTING_READ(reg);
1381         udelay(150);
1382
1383         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387         POSTING_READ(DPLL_MD(crtc->pipe));
1388
1389         /* We do this three times for luck */
1390         I915_WRITE(reg, dpll);
1391         POSTING_READ(reg);
1392         udelay(150); /* wait for warmup */
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150); /* wait for warmup */
1396         I915_WRITE(reg, dpll);
1397         POSTING_READ(reg);
1398         udelay(150); /* wait for warmup */
1399 }
1400
1401 static void i9xx_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(dev_priv->info->gen >= 5);
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev) && !IS_I830(dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418
1419         /* Wait for the clocks to stabilize. */
1420         POSTING_READ(reg);
1421         udelay(150);
1422
1423         if (INTEL_INFO(dev)->gen >= 4) {
1424                 I915_WRITE(DPLL_MD(crtc->pipe),
1425                            crtc->config.dpll_hw_state.dpll_md);
1426         } else {
1427                 /* The pixel multiplier can only be updated once the
1428                  * DPLL is enabled and the clocks are stable.
1429                  *
1430                  * So write it again.
1431                  */
1432                 I915_WRITE(reg, dpll);
1433         }
1434
1435         /* We do this three times for luck */
1436         I915_WRITE(reg, dpll);
1437         POSTING_READ(reg);
1438         udelay(150); /* wait for warmup */
1439         I915_WRITE(reg, dpll);
1440         POSTING_READ(reg);
1441         udelay(150); /* wait for warmup */
1442         I915_WRITE(reg, dpll);
1443         POSTING_READ(reg);
1444         udelay(150); /* wait for warmup */
1445 }
1446
1447 /**
1448  * i9xx_disable_pll - disable a PLL
1449  * @dev_priv: i915 private structure
1450  * @pipe: pipe PLL to disable
1451  *
1452  * Disable the PLL for @pipe, making sure the pipe is off first.
1453  *
1454  * Note!  This is for pre-ILK only.
1455  */
1456 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1457 {
1458         /* Don't disable pipe A or pipe A PLLs if needed */
1459         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460                 return;
1461
1462         /* Make sure the pipe isn't still relying on us */
1463         assert_pipe_disabled(dev_priv, pipe);
1464
1465         I915_WRITE(DPLL(pipe), 0);
1466         POSTING_READ(DPLL(pipe));
1467 }
1468
1469 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470 {
1471         u32 port_mask;
1472
1473         if (!port)
1474                 port_mask = DPLL_PORTB_READY_MASK;
1475         else
1476                 port_mask = DPLL_PORTC_READY_MASK;
1477
1478         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480                      'B' + port, I915_READ(DPLL(0)));
1481 }
1482
1483 /**
1484  * ironlake_enable_shared_dpll - enable PCH PLL
1485  * @dev_priv: i915 private structure
1486  * @pipe: pipe PLL to enable
1487  *
1488  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489  * drives the transcoder clock.
1490  */
1491 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1492 {
1493         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1495
1496         /* PCH PLLs only available on ILK, SNB and IVB */
1497         BUG_ON(dev_priv->info->gen < 5);
1498         if (WARN_ON(pll == NULL))
1499                 return;
1500
1501         if (WARN_ON(pll->refcount == 0))
1502                 return;
1503
1504         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505                       pll->name, pll->active, pll->on,
1506                       crtc->base.base.id);
1507
1508         if (pll->active++) {
1509                 WARN_ON(!pll->on);
1510                 assert_shared_dpll_enabled(dev_priv, pll);
1511                 return;
1512         }
1513         WARN_ON(pll->on);
1514
1515         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1516         pll->enable(dev_priv, pll);
1517         pll->on = true;
1518 }
1519
1520 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1521 {
1522         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1524
1525         /* PCH only available on ILK+ */
1526         BUG_ON(dev_priv->info->gen < 5);
1527         if (WARN_ON(pll == NULL))
1528                return;
1529
1530         if (WARN_ON(pll->refcount == 0))
1531                 return;
1532
1533         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534                       pll->name, pll->active, pll->on,
1535                       crtc->base.base.id);
1536
1537         if (WARN_ON(pll->active == 0)) {
1538                 assert_shared_dpll_disabled(dev_priv, pll);
1539                 return;
1540         }
1541
1542         assert_shared_dpll_enabled(dev_priv, pll);
1543         WARN_ON(!pll->on);
1544         if (--pll->active)
1545                 return;
1546
1547         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1548         pll->disable(dev_priv, pll);
1549         pll->on = false;
1550 }
1551
1552 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553                                            enum pipe pipe)
1554 {
1555         struct drm_device *dev = dev_priv->dev;
1556         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1558         uint32_t reg, val, pipeconf_val;
1559
1560         /* PCH only available on ILK+ */
1561         BUG_ON(dev_priv->info->gen < 5);
1562
1563         /* Make sure PCH DPLL is enabled */
1564         assert_shared_dpll_enabled(dev_priv,
1565                                    intel_crtc_to_shared_dpll(intel_crtc));
1566
1567         /* FDI must be feeding us bits for PCH ports */
1568         assert_fdi_tx_enabled(dev_priv, pipe);
1569         assert_fdi_rx_enabled(dev_priv, pipe);
1570
1571         if (HAS_PCH_CPT(dev)) {
1572                 /* Workaround: Set the timing override bit before enabling the
1573                  * pch transcoder. */
1574                 reg = TRANS_CHICKEN2(pipe);
1575                 val = I915_READ(reg);
1576                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577                 I915_WRITE(reg, val);
1578         }
1579
1580         reg = PCH_TRANSCONF(pipe);
1581         val = I915_READ(reg);
1582         pipeconf_val = I915_READ(PIPECONF(pipe));
1583
1584         if (HAS_PCH_IBX(dev_priv->dev)) {
1585                 /*
1586                  * make the BPC in transcoder be consistent with
1587                  * that in pipeconf reg.
1588                  */
1589                 val &= ~PIPECONF_BPC_MASK;
1590                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1591         }
1592
1593         val &= ~TRANS_INTERLACE_MASK;
1594         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1595                 if (HAS_PCH_IBX(dev_priv->dev) &&
1596                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597                         val |= TRANS_LEGACY_INTERLACED_ILK;
1598                 else
1599                         val |= TRANS_INTERLACED;
1600         else
1601                 val |= TRANS_PROGRESSIVE;
1602
1603         I915_WRITE(reg, val | TRANS_ENABLE);
1604         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1605                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1606 }
1607
1608 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1609                                       enum transcoder cpu_transcoder)
1610 {
1611         u32 val, pipeconf_val;
1612
1613         /* PCH only available on ILK+ */
1614         BUG_ON(dev_priv->info->gen < 5);
1615
1616         /* FDI must be feeding us bits for PCH ports */
1617         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1618         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1619
1620         /* Workaround: set timing override bit. */
1621         val = I915_READ(_TRANSA_CHICKEN2);
1622         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623         I915_WRITE(_TRANSA_CHICKEN2, val);
1624
1625         val = TRANS_ENABLE;
1626         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1627
1628         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629             PIPECONF_INTERLACED_ILK)
1630                 val |= TRANS_INTERLACED;
1631         else
1632                 val |= TRANS_PROGRESSIVE;
1633
1634         I915_WRITE(LPT_TRANSCONF, val);
1635         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1636                 DRM_ERROR("Failed to enable PCH transcoder\n");
1637 }
1638
1639 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640                                             enum pipe pipe)
1641 {
1642         struct drm_device *dev = dev_priv->dev;
1643         uint32_t reg, val;
1644
1645         /* FDI relies on the transcoder */
1646         assert_fdi_tx_disabled(dev_priv, pipe);
1647         assert_fdi_rx_disabled(dev_priv, pipe);
1648
1649         /* Ports must be off as well */
1650         assert_pch_ports_disabled(dev_priv, pipe);
1651
1652         reg = PCH_TRANSCONF(pipe);
1653         val = I915_READ(reg);
1654         val &= ~TRANS_ENABLE;
1655         I915_WRITE(reg, val);
1656         /* wait for PCH transcoder off, transcoder state */
1657         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1658                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1659
1660         if (!HAS_PCH_IBX(dev)) {
1661                 /* Workaround: Clear the timing override chicken bit again. */
1662                 reg = TRANS_CHICKEN2(pipe);
1663                 val = I915_READ(reg);
1664                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665                 I915_WRITE(reg, val);
1666         }
1667 }
1668
1669 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1670 {
1671         u32 val;
1672
1673         val = I915_READ(LPT_TRANSCONF);
1674         val &= ~TRANS_ENABLE;
1675         I915_WRITE(LPT_TRANSCONF, val);
1676         /* wait for PCH transcoder off, transcoder state */
1677         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1678                 DRM_ERROR("Failed to disable PCH transcoder\n");
1679
1680         /* Workaround: clear timing override bit. */
1681         val = I915_READ(_TRANSA_CHICKEN2);
1682         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1683         I915_WRITE(_TRANSA_CHICKEN2, val);
1684 }
1685
1686 /**
1687  * intel_enable_pipe - enable a pipe, asserting requirements
1688  * @dev_priv: i915 private structure
1689  * @pipe: pipe to enable
1690  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1691  *
1692  * Enable @pipe, making sure that various hardware specific requirements
1693  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694  *
1695  * @pipe should be %PIPE_A or %PIPE_B.
1696  *
1697  * Will wait until the pipe is actually running (i.e. first vblank) before
1698  * returning.
1699  */
1700 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1701                               bool pch_port, bool dsi)
1702 {
1703         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704                                                                       pipe);
1705         enum pipe pch_transcoder;
1706         int reg;
1707         u32 val;
1708
1709         assert_planes_disabled(dev_priv, pipe);
1710         assert_cursor_disabled(dev_priv, pipe);
1711         assert_sprites_disabled(dev_priv, pipe);
1712
1713         if (HAS_PCH_LPT(dev_priv->dev))
1714                 pch_transcoder = TRANSCODER_A;
1715         else
1716                 pch_transcoder = pipe;
1717
1718         /*
1719          * A pipe without a PLL won't actually be able to drive bits from
1720          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1721          * need the check.
1722          */
1723         if (!HAS_PCH_SPLIT(dev_priv->dev))
1724                 if (dsi)
1725                         assert_dsi_pll_enabled(dev_priv);
1726                 else
1727                         assert_pll_enabled(dev_priv, pipe);
1728         else {
1729                 if (pch_port) {
1730                         /* if driving the PCH, we need FDI enabled */
1731                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1732                         assert_fdi_tx_pll_enabled(dev_priv,
1733                                                   (enum pipe) cpu_transcoder);
1734                 }
1735                 /* FIXME: assert CPU port conditions for SNB+ */
1736         }
1737
1738         reg = PIPECONF(cpu_transcoder);
1739         val = I915_READ(reg);
1740         if (val & PIPECONF_ENABLE)
1741                 return;
1742
1743         I915_WRITE(reg, val | PIPECONF_ENABLE);
1744         intel_wait_for_vblank(dev_priv->dev, pipe);
1745 }
1746
1747 /**
1748  * intel_disable_pipe - disable a pipe, asserting requirements
1749  * @dev_priv: i915 private structure
1750  * @pipe: pipe to disable
1751  *
1752  * Disable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe has shut down before returning.
1758  */
1759 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760                                enum pipe pipe)
1761 {
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         int reg;
1765         u32 val;
1766
1767         /*
1768          * Make sure planes won't keep trying to pump pixels to us,
1769          * or we might hang the display.
1770          */
1771         assert_planes_disabled(dev_priv, pipe);
1772         assert_cursor_disabled(dev_priv, pipe);
1773         assert_sprites_disabled(dev_priv, pipe);
1774
1775         /* Don't disable pipe A or pipe A PLLs if needed */
1776         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777                 return;
1778
1779         reg = PIPECONF(cpu_transcoder);
1780         val = I915_READ(reg);
1781         if ((val & PIPECONF_ENABLE) == 0)
1782                 return;
1783
1784         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1785         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786 }
1787
1788 /*
1789  * Plane regs are double buffered, going from enabled->disabled needs a
1790  * trigger in order to latch.  The display address reg provides this.
1791  */
1792 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1793                                       enum plane plane)
1794 {
1795         if (dev_priv->info->gen >= 4)
1796                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797         else
1798                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1799 }
1800
1801 /**
1802  * intel_enable_plane - enable a display plane on a given pipe
1803  * @dev_priv: i915 private structure
1804  * @plane: plane to enable
1805  * @pipe: pipe being fed
1806  *
1807  * Enable @plane on @pipe, making sure that @pipe is running first.
1808  */
1809 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810                                enum plane plane, enum pipe pipe)
1811 {
1812         int reg;
1813         u32 val;
1814
1815         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816         assert_pipe_enabled(dev_priv, pipe);
1817
1818         reg = DSPCNTR(plane);
1819         val = I915_READ(reg);
1820         if (val & DISPLAY_PLANE_ENABLE)
1821                 return;
1822
1823         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1824         intel_flush_display_plane(dev_priv, plane);
1825         intel_wait_for_vblank(dev_priv->dev, pipe);
1826 }
1827
1828 /**
1829  * intel_disable_plane - disable a display plane
1830  * @dev_priv: i915 private structure
1831  * @plane: plane to disable
1832  * @pipe: pipe consuming the data
1833  *
1834  * Disable @plane; should be an independent operation.
1835  */
1836 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837                                 enum plane plane, enum pipe pipe)
1838 {
1839         int reg;
1840         u32 val;
1841
1842         reg = DSPCNTR(plane);
1843         val = I915_READ(reg);
1844         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845                 return;
1846
1847         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1848         intel_flush_display_plane(dev_priv, plane);
1849         intel_wait_for_vblank(dev_priv->dev, pipe);
1850 }
1851
1852 static bool need_vtd_wa(struct drm_device *dev)
1853 {
1854 #ifdef CONFIG_INTEL_IOMMU
1855         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856                 return true;
1857 #endif
1858         return false;
1859 }
1860
1861 int
1862 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1863                            struct drm_i915_gem_object *obj,
1864                            struct intel_ring_buffer *pipelined)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         u32 alignment;
1868         int ret;
1869
1870         switch (obj->tiling_mode) {
1871         case I915_TILING_NONE:
1872                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873                         alignment = 128 * 1024;
1874                 else if (INTEL_INFO(dev)->gen >= 4)
1875                         alignment = 4 * 1024;
1876                 else
1877                         alignment = 64 * 1024;
1878                 break;
1879         case I915_TILING_X:
1880                 /* pin() will align the object as required by fence */
1881                 alignment = 0;
1882                 break;
1883         case I915_TILING_Y:
1884                 /* Despite that we check this in framebuffer_init userspace can
1885                  * screw us over and change the tiling after the fact. Only
1886                  * pinned buffers can't change their tiling. */
1887                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1888                 return -EINVAL;
1889         default:
1890                 BUG();
1891         }
1892
1893         /* Note that the w/a also requires 64 PTE of padding following the
1894          * bo. We currently fill all unused PTE with the shadow page and so
1895          * we should always have valid PTE following the scanout preventing
1896          * the VT-d warning.
1897          */
1898         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899                 alignment = 256 * 1024;
1900
1901         dev_priv->mm.interruptible = false;
1902         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1903         if (ret)
1904                 goto err_interruptible;
1905
1906         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907          * fence, whereas 965+ only requires a fence if using
1908          * framebuffer compression.  For simplicity, we always install
1909          * a fence as the cost is not that onerous.
1910          */
1911         ret = i915_gem_object_get_fence(obj);
1912         if (ret)
1913                 goto err_unpin;
1914
1915         i915_gem_object_pin_fence(obj);
1916
1917         dev_priv->mm.interruptible = true;
1918         return 0;
1919
1920 err_unpin:
1921         i915_gem_object_unpin_from_display_plane(obj);
1922 err_interruptible:
1923         dev_priv->mm.interruptible = true;
1924         return ret;
1925 }
1926
1927 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928 {
1929         i915_gem_object_unpin_fence(obj);
1930         i915_gem_object_unpin_from_display_plane(obj);
1931 }
1932
1933 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934  * is assumed to be a power-of-two. */
1935 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936                                              unsigned int tiling_mode,
1937                                              unsigned int cpp,
1938                                              unsigned int pitch)
1939 {
1940         if (tiling_mode != I915_TILING_NONE) {
1941                 unsigned int tile_rows, tiles;
1942
1943                 tile_rows = *y / 8;
1944                 *y %= 8;
1945
1946                 tiles = *x / (512/cpp);
1947                 *x %= 512/cpp;
1948
1949                 return tile_rows * pitch * 8 + tiles * 4096;
1950         } else {
1951                 unsigned int offset;
1952
1953                 offset = *y * pitch + *x * cpp;
1954                 *y = 0;
1955                 *x = (offset & 4095) / cpp;
1956                 return offset & -4096;
1957         }
1958 }
1959
1960 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961                              int x, int y)
1962 {
1963         struct drm_device *dev = crtc->dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966         struct intel_framebuffer *intel_fb;
1967         struct drm_i915_gem_object *obj;
1968         int plane = intel_crtc->plane;
1969         unsigned long linear_offset;
1970         u32 dspcntr;
1971         u32 reg;
1972
1973         switch (plane) {
1974         case 0:
1975         case 1:
1976                 break;
1977         default:
1978                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1979                 return -EINVAL;
1980         }
1981
1982         intel_fb = to_intel_framebuffer(fb);
1983         obj = intel_fb->obj;
1984
1985         reg = DSPCNTR(plane);
1986         dspcntr = I915_READ(reg);
1987         /* Mask out pixel format bits in case we change it */
1988         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1989         switch (fb->pixel_format) {
1990         case DRM_FORMAT_C8:
1991                 dspcntr |= DISPPLANE_8BPP;
1992                 break;
1993         case DRM_FORMAT_XRGB1555:
1994         case DRM_FORMAT_ARGB1555:
1995                 dspcntr |= DISPPLANE_BGRX555;
1996                 break;
1997         case DRM_FORMAT_RGB565:
1998                 dspcntr |= DISPPLANE_BGRX565;
1999                 break;
2000         case DRM_FORMAT_XRGB8888:
2001         case DRM_FORMAT_ARGB8888:
2002                 dspcntr |= DISPPLANE_BGRX888;
2003                 break;
2004         case DRM_FORMAT_XBGR8888:
2005         case DRM_FORMAT_ABGR8888:
2006                 dspcntr |= DISPPLANE_RGBX888;
2007                 break;
2008         case DRM_FORMAT_XRGB2101010:
2009         case DRM_FORMAT_ARGB2101010:
2010                 dspcntr |= DISPPLANE_BGRX101010;
2011                 break;
2012         case DRM_FORMAT_XBGR2101010:
2013         case DRM_FORMAT_ABGR2101010:
2014                 dspcntr |= DISPPLANE_RGBX101010;
2015                 break;
2016         default:
2017                 BUG();
2018         }
2019
2020         if (INTEL_INFO(dev)->gen >= 4) {
2021                 if (obj->tiling_mode != I915_TILING_NONE)
2022                         dspcntr |= DISPPLANE_TILED;
2023                 else
2024                         dspcntr &= ~DISPPLANE_TILED;
2025         }
2026
2027         if (IS_G4X(dev))
2028                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
2030         I915_WRITE(reg, dspcntr);
2031
2032         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2033
2034         if (INTEL_INFO(dev)->gen >= 4) {
2035                 intel_crtc->dspaddr_offset =
2036                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037                                                        fb->bits_per_pixel / 8,
2038                                                        fb->pitches[0]);
2039                 linear_offset -= intel_crtc->dspaddr_offset;
2040         } else {
2041                 intel_crtc->dspaddr_offset = linear_offset;
2042         }
2043
2044         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046                       fb->pitches[0]);
2047         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2048         if (INTEL_INFO(dev)->gen >= 4) {
2049                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2050                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2051                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2052                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2053         } else
2054                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2055         POSTING_READ(reg);
2056
2057         return 0;
2058 }
2059
2060 static int ironlake_update_plane(struct drm_crtc *crtc,
2061                                  struct drm_framebuffer *fb, int x, int y)
2062 {
2063         struct drm_device *dev = crtc->dev;
2064         struct drm_i915_private *dev_priv = dev->dev_private;
2065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066         struct intel_framebuffer *intel_fb;
2067         struct drm_i915_gem_object *obj;
2068         int plane = intel_crtc->plane;
2069         unsigned long linear_offset;
2070         u32 dspcntr;
2071         u32 reg;
2072
2073         switch (plane) {
2074         case 0:
2075         case 1:
2076         case 2:
2077                 break;
2078         default:
2079                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2080                 return -EINVAL;
2081         }
2082
2083         intel_fb = to_intel_framebuffer(fb);
2084         obj = intel_fb->obj;
2085
2086         reg = DSPCNTR(plane);
2087         dspcntr = I915_READ(reg);
2088         /* Mask out pixel format bits in case we change it */
2089         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2090         switch (fb->pixel_format) {
2091         case DRM_FORMAT_C8:
2092                 dspcntr |= DISPPLANE_8BPP;
2093                 break;
2094         case DRM_FORMAT_RGB565:
2095                 dspcntr |= DISPPLANE_BGRX565;
2096                 break;
2097         case DRM_FORMAT_XRGB8888:
2098         case DRM_FORMAT_ARGB8888:
2099                 dspcntr |= DISPPLANE_BGRX888;
2100                 break;
2101         case DRM_FORMAT_XBGR8888:
2102         case DRM_FORMAT_ABGR8888:
2103                 dspcntr |= DISPPLANE_RGBX888;
2104                 break;
2105         case DRM_FORMAT_XRGB2101010:
2106         case DRM_FORMAT_ARGB2101010:
2107                 dspcntr |= DISPPLANE_BGRX101010;
2108                 break;
2109         case DRM_FORMAT_XBGR2101010:
2110         case DRM_FORMAT_ABGR2101010:
2111                 dspcntr |= DISPPLANE_RGBX101010;
2112                 break;
2113         default:
2114                 BUG();
2115         }
2116
2117         if (obj->tiling_mode != I915_TILING_NONE)
2118                 dspcntr |= DISPPLANE_TILED;
2119         else
2120                 dspcntr &= ~DISPPLANE_TILED;
2121
2122         if (IS_HASWELL(dev))
2123                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124         else
2125                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2126
2127         I915_WRITE(reg, dspcntr);
2128
2129         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2130         intel_crtc->dspaddr_offset =
2131                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132                                                fb->bits_per_pixel / 8,
2133                                                fb->pitches[0]);
2134         linear_offset -= intel_crtc->dspaddr_offset;
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138                       fb->pitches[0]);
2139         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2140         I915_MODIFY_DISPBASE(DSPSURF(plane),
2141                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2142         if (IS_HASWELL(dev)) {
2143                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144         } else {
2145                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147         }
2148         POSTING_READ(reg);
2149
2150         return 0;
2151 }
2152
2153 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2154 static int
2155 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156                            int x, int y, enum mode_set_atomic state)
2157 {
2158         struct drm_device *dev = crtc->dev;
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160
2161         if (dev_priv->display.disable_fbc)
2162                 dev_priv->display.disable_fbc(dev);
2163         intel_increase_pllclock(crtc);
2164
2165         return dev_priv->display.update_plane(crtc, fb, x, y);
2166 }
2167
2168 void intel_display_handle_reset(struct drm_device *dev)
2169 {
2170         struct drm_i915_private *dev_priv = dev->dev_private;
2171         struct drm_crtc *crtc;
2172
2173         /*
2174          * Flips in the rings have been nuked by the reset,
2175          * so complete all pending flips so that user space
2176          * will get its events and not get stuck.
2177          *
2178          * Also update the base address of all primary
2179          * planes to the the last fb to make sure we're
2180          * showing the correct fb after a reset.
2181          *
2182          * Need to make two loops over the crtcs so that we
2183          * don't try to grab a crtc mutex before the
2184          * pending_flip_queue really got woken up.
2185          */
2186
2187         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189                 enum plane plane = intel_crtc->plane;
2190
2191                 intel_prepare_page_flip(dev, plane);
2192                 intel_finish_page_flip_plane(dev, plane);
2193         }
2194
2195         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198                 mutex_lock(&crtc->mutex);
2199                 if (intel_crtc->active)
2200                         dev_priv->display.update_plane(crtc, crtc->fb,
2201                                                        crtc->x, crtc->y);
2202                 mutex_unlock(&crtc->mutex);
2203         }
2204 }
2205
2206 static int
2207 intel_finish_fb(struct drm_framebuffer *old_fb)
2208 {
2209         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211         bool was_interruptible = dev_priv->mm.interruptible;
2212         int ret;
2213
2214         /* Big Hammer, we also need to ensure that any pending
2215          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216          * current scanout is retired before unpinning the old
2217          * framebuffer.
2218          *
2219          * This should only fail upon a hung GPU, in which case we
2220          * can safely continue.
2221          */
2222         dev_priv->mm.interruptible = false;
2223         ret = i915_gem_object_finish_gpu(obj);
2224         dev_priv->mm.interruptible = was_interruptible;
2225
2226         return ret;
2227 }
2228
2229 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230 {
2231         struct drm_device *dev = crtc->dev;
2232         struct drm_i915_master_private *master_priv;
2233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235         if (!dev->primary->master)
2236                 return;
2237
2238         master_priv = dev->primary->master->driver_priv;
2239         if (!master_priv->sarea_priv)
2240                 return;
2241
2242         switch (intel_crtc->pipe) {
2243         case 0:
2244                 master_priv->sarea_priv->pipeA_x = x;
2245                 master_priv->sarea_priv->pipeA_y = y;
2246                 break;
2247         case 1:
2248                 master_priv->sarea_priv->pipeB_x = x;
2249                 master_priv->sarea_priv->pipeB_y = y;
2250                 break;
2251         default:
2252                 break;
2253         }
2254 }
2255
2256 static int
2257 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2258                     struct drm_framebuffer *fb)
2259 {
2260         struct drm_device *dev = crtc->dev;
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263         struct drm_framebuffer *old_fb;
2264         int ret;
2265
2266         /* no fb bound */
2267         if (!fb) {
2268                 DRM_ERROR("No FB bound\n");
2269                 return 0;
2270         }
2271
2272         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2273                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274                           plane_name(intel_crtc->plane),
2275                           INTEL_INFO(dev)->num_pipes);
2276                 return -EINVAL;
2277         }
2278
2279         mutex_lock(&dev->struct_mutex);
2280         ret = intel_pin_and_fence_fb_obj(dev,
2281                                          to_intel_framebuffer(fb)->obj,
2282                                          NULL);
2283         if (ret != 0) {
2284                 mutex_unlock(&dev->struct_mutex);
2285                 DRM_ERROR("pin & fence failed\n");
2286                 return ret;
2287         }
2288
2289         /* Update pipe size and adjust fitter if needed */
2290         if (i915_fastboot) {
2291                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292                            ((crtc->mode.hdisplay - 1) << 16) |
2293                            (crtc->mode.vdisplay - 1));
2294                 if (!intel_crtc->config.pch_pfit.enabled &&
2295                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300                 }
2301         }
2302
2303         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2304         if (ret) {
2305                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2306                 mutex_unlock(&dev->struct_mutex);
2307                 DRM_ERROR("failed to update base address\n");
2308                 return ret;
2309         }
2310
2311         old_fb = crtc->fb;
2312         crtc->fb = fb;
2313         crtc->x = x;
2314         crtc->y = y;
2315
2316         if (old_fb) {
2317                 if (intel_crtc->active && old_fb != fb)
2318                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2319                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2320         }
2321
2322         intel_update_fbc(dev);
2323         intel_edp_psr_update(dev);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328         return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         if (IS_IVYBRIDGE(dev)) {
2343                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         } else {
2346                 temp &= ~FDI_LINK_TRAIN_NONE;
2347                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         }
2349         I915_WRITE(reg, temp);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         if (HAS_PCH_CPT(dev)) {
2354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356         } else {
2357                 temp &= ~FDI_LINK_TRAIN_NONE;
2358                 temp |= FDI_LINK_TRAIN_NONE;
2359         }
2360         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362         /* wait one idle pattern time */
2363         POSTING_READ(reg);
2364         udelay(1000);
2365
2366         /* IVB wants error correction enabled */
2367         if (IS_IVYBRIDGE(dev))
2368                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369                            FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373 {
2374         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375 }
2376
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *pipe_B_crtc =
2381                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382         struct intel_crtc *pipe_C_crtc =
2383                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384         uint32_t temp;
2385
2386         /*
2387          * When everything is off disable fdi C so that we could enable fdi B
2388          * with all lanes. Note that we don't care about enabled pipes without
2389          * an enabled pch encoder.
2390          */
2391         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392             !pipe_has_enabled_pch(pipe_C_crtc)) {
2393                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396                 temp = I915_READ(SOUTH_CHICKEN1);
2397                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399                 I915_WRITE(SOUTH_CHICKEN1, temp);
2400         }
2401 }
2402
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         int pipe = intel_crtc->pipe;
2410         int plane = intel_crtc->plane;
2411         u32 reg, temp, tries;
2412
2413         /* FDI needs bits from pipe & plane first */
2414         assert_pipe_enabled(dev_priv, pipe);
2415         assert_plane_enabled(dev_priv, plane);
2416
2417         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418            for train result */
2419         reg = FDI_RX_IMR(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_RX_SYMBOL_LOCK;
2422         temp &= ~FDI_RX_BIT_LOCK;
2423         I915_WRITE(reg, temp);
2424         I915_READ(reg);
2425         udelay(150);
2426
2427         /* enable CPU FDI TX and PCH FDI RX */
2428         reg = FDI_TX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         /* Ironlake workaround, enable clock pointer after FDI enable*/
2446         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448                    FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if ((temp & FDI_RX_BIT_LOCK)) {
2456                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2457                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 1 fail!\n");
2463
2464         /* Train 2 */
2465         reg = FDI_TX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         reg = FDI_RX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         POSTING_READ(reg);
2478         udelay(150);
2479
2480         reg = FDI_RX_IIR(pipe);
2481         for (tries = 0; tries < 5; tries++) {
2482                 temp = I915_READ(reg);
2483                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485                 if (temp & FDI_RX_SYMBOL_LOCK) {
2486                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2488                         break;
2489                 }
2490         }
2491         if (tries == 5)
2492                 DRM_ERROR("FDI train 2 fail!\n");
2493
2494         DRM_DEBUG_KMS("FDI train done\n");
2495
2496 }
2497
2498 static const int snb_b_fdi_train_param[] = {
2499         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503 };
2504
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         int pipe = intel_crtc->pipe;
2512         u32 reg, temp, i, retry;
2513
2514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515            for train result */
2516         reg = FDI_RX_IMR(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_RX_SYMBOL_LOCK;
2519         temp &= ~FDI_RX_BIT_LOCK;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         /* enable CPU FDI TX and PCH FDI RX */
2526         reg = FDI_TX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530         temp &= ~FDI_LINK_TRAIN_NONE;
2531         temp |= FDI_LINK_TRAIN_PATTERN_1;
2532         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533         /* SNB-B */
2534         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537         I915_WRITE(FDI_RX_MISC(pipe),
2538                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540         reg = FDI_RX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         if (HAS_PCH_CPT(dev)) {
2543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545         } else {
2546                 temp &= ~FDI_LINK_TRAIN_NONE;
2547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548         }
2549         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551         POSTING_READ(reg);
2552         udelay(150);
2553
2554         for (i = 0; i < 4; i++) {
2555                 reg = FDI_TX_CTL(pipe);
2556                 temp = I915_READ(reg);
2557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558                 temp |= snb_b_fdi_train_param[i];
2559                 I915_WRITE(reg, temp);
2560
2561                 POSTING_READ(reg);
2562                 udelay(500);
2563
2564                 for (retry = 0; retry < 5; retry++) {
2565                         reg = FDI_RX_IIR(pipe);
2566                         temp = I915_READ(reg);
2567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568                         if (temp & FDI_RX_BIT_LOCK) {
2569                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571                                 break;
2572                         }
2573                         udelay(50);
2574                 }
2575                 if (retry < 5)
2576                         break;
2577         }
2578         if (i == 4)
2579                 DRM_ERROR("FDI train 1 fail!\n");
2580
2581         /* Train 2 */
2582         reg = FDI_TX_CTL(pipe);
2583         temp = I915_READ(reg);
2584         temp &= ~FDI_LINK_TRAIN_NONE;
2585         temp |= FDI_LINK_TRAIN_PATTERN_2;
2586         if (IS_GEN6(dev)) {
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 /* SNB-B */
2589                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590         }
2591         I915_WRITE(reg, temp);
2592
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         if (HAS_PCH_CPT(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598         } else {
2599                 temp &= ~FDI_LINK_TRAIN_NONE;
2600                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601         }
2602         I915_WRITE(reg, temp);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         for (i = 0; i < 4; i++) {
2608                 reg = FDI_TX_CTL(pipe);
2609                 temp = I915_READ(reg);
2610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611                 temp |= snb_b_fdi_train_param[i];
2612                 I915_WRITE(reg, temp);
2613
2614                 POSTING_READ(reg);
2615                 udelay(500);
2616
2617                 for (retry = 0; retry < 5; retry++) {
2618                         reg = FDI_RX_IIR(pipe);
2619                         temp = I915_READ(reg);
2620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621                         if (temp & FDI_RX_SYMBOL_LOCK) {
2622                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624                                 break;
2625                         }
2626                         udelay(50);
2627                 }
2628                 if (retry < 5)
2629                         break;
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 2 fail!\n");
2633
2634         DRM_DEBUG_KMS("FDI train done.\n");
2635 }
2636
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         int pipe = intel_crtc->pipe;
2644         u32 reg, temp, i, j;
2645
2646         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647            for train result */
2648         reg = FDI_RX_IMR(pipe);
2649         temp = I915_READ(reg);
2650         temp &= ~FDI_RX_SYMBOL_LOCK;
2651         temp &= ~FDI_RX_BIT_LOCK;
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658                       I915_READ(FDI_RX_IIR(pipe)));
2659
2660         /* Try each vswing and preemphasis setting twice before moving on */
2661         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662                 /* disable first in case we need to retry */
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666                 temp &= ~FDI_TX_ENABLE;
2667                 I915_WRITE(reg, temp);
2668
2669                 reg = FDI_RX_CTL(pipe);
2670                 temp = I915_READ(reg);
2671                 temp &= ~FDI_LINK_TRAIN_AUTO;
2672                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673                 temp &= ~FDI_RX_ENABLE;
2674                 I915_WRITE(reg, temp);
2675
2676                 /* enable CPU FDI TX and PCH FDI RX */
2677                 reg = FDI_TX_CTL(pipe);
2678                 temp = I915_READ(reg);
2679                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2682                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683                 temp |= snb_b_fdi_train_param[j/2];
2684                 temp |= FDI_COMPOSITE_SYNC;
2685                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2686
2687                 I915_WRITE(FDI_RX_MISC(pipe),
2688                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2689
2690                 reg = FDI_RX_CTL(pipe);
2691                 temp = I915_READ(reg);
2692                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693                 temp |= FDI_COMPOSITE_SYNC;
2694                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2695
2696                 POSTING_READ(reg);
2697                 udelay(1); /* should be 0.5us */
2698
2699                 for (i = 0; i < 4; i++) {
2700                         reg = FDI_RX_IIR(pipe);
2701                         temp = I915_READ(reg);
2702                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704                         if (temp & FDI_RX_BIT_LOCK ||
2705                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708                                               i);
2709                                 break;
2710                         }
2711                         udelay(1); /* should be 0.5us */
2712                 }
2713                 if (i == 4) {
2714                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715                         continue;
2716                 }
2717
2718                 /* Train 2 */
2719                 reg = FDI_TX_CTL(pipe);
2720                 temp = I915_READ(reg);
2721                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723                 I915_WRITE(reg, temp);
2724
2725                 reg = FDI_RX_CTL(pipe);
2726                 temp = I915_READ(reg);
2727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2729                 I915_WRITE(reg, temp);
2730
2731                 POSTING_READ(reg);
2732                 udelay(2); /* should be 1.5us */
2733
2734                 for (i = 0; i < 4; i++) {
2735                         reg = FDI_RX_IIR(pipe);
2736                         temp = I915_READ(reg);
2737                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2738
2739                         if (temp & FDI_RX_SYMBOL_LOCK ||
2740                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743                                               i);
2744                                 goto train_done;
2745                         }
2746                         udelay(2); /* should be 1.5us */
2747                 }
2748                 if (i == 4)
2749                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2750         }
2751
2752 train_done:
2753         DRM_DEBUG_KMS("FDI train done.\n");
2754 }
2755
2756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2757 {
2758         struct drm_device *dev = intel_crtc->base.dev;
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         int pipe = intel_crtc->pipe;
2761         u32 reg, temp;
2762
2763
2764         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2769         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2770         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772         POSTING_READ(reg);
2773         udelay(200);
2774
2775         /* Switch from Rawclk to PCDclk */
2776         temp = I915_READ(reg);
2777         I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779         POSTING_READ(reg);
2780         udelay(200);
2781
2782         /* Enable CPU FDI TX PLL, always on for Ironlake */
2783         reg = FDI_TX_CTL(pipe);
2784         temp = I915_READ(reg);
2785         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2787
2788                 POSTING_READ(reg);
2789                 udelay(100);
2790         }
2791 }
2792
2793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794 {
2795         struct drm_device *dev = intel_crtc->base.dev;
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         int pipe = intel_crtc->pipe;
2798         u32 reg, temp;
2799
2800         /* Switch from PCDclk to Rawclk */
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805         /* Disable CPU FDI TX PLL */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810         POSTING_READ(reg);
2811         udelay(100);
2812
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817         /* Wait for the clocks to turn off. */
2818         POSTING_READ(reg);
2819         udelay(100);
2820 }
2821
2822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823 {
2824         struct drm_device *dev = crtc->dev;
2825         struct drm_i915_private *dev_priv = dev->dev_private;
2826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827         int pipe = intel_crtc->pipe;
2828         u32 reg, temp;
2829
2830         /* disable CPU FDI tx and PCH FDI rx */
2831         reg = FDI_TX_CTL(pipe);
2832         temp = I915_READ(reg);
2833         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834         POSTING_READ(reg);
2835
2836         reg = FDI_RX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         temp &= ~(0x7 << 16);
2839         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2840         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842         POSTING_READ(reg);
2843         udelay(100);
2844
2845         /* Ironlake workaround, disable clock pointer after downing FDI */
2846         if (HAS_PCH_IBX(dev)) {
2847                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2848         }
2849
2850         /* still set train pattern 1 */
2851         reg = FDI_TX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         temp &= ~FDI_LINK_TRAIN_NONE;
2854         temp |= FDI_LINK_TRAIN_PATTERN_1;
2855         I915_WRITE(reg, temp);
2856
2857         reg = FDI_RX_CTL(pipe);
2858         temp = I915_READ(reg);
2859         if (HAS_PCH_CPT(dev)) {
2860                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862         } else {
2863                 temp &= ~FDI_LINK_TRAIN_NONE;
2864                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865         }
2866         /* BPC in FDI rx is consistent with that in PIPECONF */
2867         temp &= ~(0x07 << 16);
2868         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2869         I915_WRITE(reg, temp);
2870
2871         POSTING_READ(reg);
2872         udelay(100);
2873 }
2874
2875 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880         unsigned long flags;
2881         bool pending;
2882
2883         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2885                 return false;
2886
2887         spin_lock_irqsave(&dev->event_lock, flags);
2888         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889         spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891         return pending;
2892 }
2893
2894 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895 {
2896         struct drm_device *dev = crtc->dev;
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898
2899         if (crtc->fb == NULL)
2900                 return;
2901
2902         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
2904         wait_event(dev_priv->pending_flip_queue,
2905                    !intel_crtc_has_pending_flip(crtc));
2906
2907         mutex_lock(&dev->struct_mutex);
2908         intel_finish_fb(crtc->fb);
2909         mutex_unlock(&dev->struct_mutex);
2910 }
2911
2912 /* Program iCLKIP clock to the desired frequency */
2913 static void lpt_program_iclkip(struct drm_crtc *crtc)
2914 {
2915         struct drm_device *dev = crtc->dev;
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
2918         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919         u32 temp;
2920
2921         mutex_lock(&dev_priv->dpio_lock);
2922
2923         /* It is necessary to ungate the pixclk gate prior to programming
2924          * the divisors, and gate it back when it is done.
2925          */
2926         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928         /* Disable SSCCTL */
2929         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2930                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931                                 SBI_SSCCTL_DISABLE,
2932                         SBI_ICLK);
2933
2934         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2935         if (clock == 20000) {
2936                 auxdiv = 1;
2937                 divsel = 0x41;
2938                 phaseinc = 0x20;
2939         } else {
2940                 /* The iCLK virtual clock root frequency is in MHz,
2941                  * but the adjusted_mode->clock in in KHz. To get the divisors,
2942                  * it is necessary to divide one by another, so we
2943                  * convert the virtual clock precision to KHz here for higher
2944                  * precision.
2945                  */
2946                 u32 iclk_virtual_root_freq = 172800 * 1000;
2947                 u32 iclk_pi_range = 64;
2948                 u32 desired_divisor, msb_divisor_value, pi_value;
2949
2950                 desired_divisor = (iclk_virtual_root_freq / clock);
2951                 msb_divisor_value = desired_divisor / iclk_pi_range;
2952                 pi_value = desired_divisor % iclk_pi_range;
2953
2954                 auxdiv = 0;
2955                 divsel = msb_divisor_value - 2;
2956                 phaseinc = pi_value;
2957         }
2958
2959         /* This should not happen with any sane values */
2960         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2966                         clock,
2967                         auxdiv,
2968                         divsel,
2969                         phasedir,
2970                         phaseinc);
2971
2972         /* Program SSCDIVINTPHASE6 */
2973         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2974         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2980         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2981
2982         /* Program SSCAUXDIV */
2983         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2984         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2986         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2987
2988         /* Enable modulator and associated divider */
2989         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2990         temp &= ~SBI_SSCCTL_DISABLE;
2991         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2992
2993         /* Wait for initialization time */
2994         udelay(24);
2995
2996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997
2998         mutex_unlock(&dev_priv->dpio_lock);
2999 }
3000
3001 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002                                                 enum pipe pch_transcoder)
3003 {
3004         struct drm_device *dev = crtc->base.dev;
3005         struct drm_i915_private *dev_priv = dev->dev_private;
3006         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009                    I915_READ(HTOTAL(cpu_transcoder)));
3010         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011                    I915_READ(HBLANK(cpu_transcoder)));
3012         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013                    I915_READ(HSYNC(cpu_transcoder)));
3014
3015         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016                    I915_READ(VTOTAL(cpu_transcoder)));
3017         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018                    I915_READ(VBLANK(cpu_transcoder)));
3019         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020                    I915_READ(VSYNC(cpu_transcoder)));
3021         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023 }
3024
3025 /*
3026  * Enable PCH resources required for PCH ports:
3027  *   - PCH PLLs
3028  *   - FDI training & RX/TX
3029  *   - update transcoder timings
3030  *   - DP transcoding bits
3031  *   - transcoder
3032  */
3033 static void ironlake_pch_enable(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp;
3040
3041         assert_pch_transcoder_disabled(dev_priv, pipe);
3042
3043         /* Write the TU size bits before fdi link training, so that error
3044          * detection works. */
3045         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
3048         /* For PCH output, training FDI link */
3049         dev_priv->display.fdi_link_train(crtc);
3050
3051         /* We need to program the right clock selection before writing the pixel
3052          * mutliplier into the DPLL. */
3053         if (HAS_PCH_CPT(dev)) {
3054                 u32 sel;
3055
3056                 temp = I915_READ(PCH_DPLL_SEL);
3057                 temp |= TRANS_DPLL_ENABLE(pipe);
3058                 sel = TRANS_DPLLB_SEL(pipe);
3059                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3060                         temp |= sel;
3061                 else
3062                         temp &= ~sel;
3063                 I915_WRITE(PCH_DPLL_SEL, temp);
3064         }
3065
3066         /* XXX: pch pll's can be enabled any time before we enable the PCH
3067          * transcoder, and we actually should do this to not upset any PCH
3068          * transcoder that already use the clock when we share it.
3069          *
3070          * Note that enable_shared_dpll tries to do the right thing, but
3071          * get_shared_dpll unconditionally resets the pll - we need that to have
3072          * the right LVDS enable sequence. */
3073         ironlake_enable_shared_dpll(intel_crtc);
3074
3075         /* set transcoder timing, panel must allow it */
3076         assert_panel_unlocked(dev_priv, pipe);
3077         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3078
3079         intel_fdi_normal_train(crtc);
3080
3081         /* For PCH DP, enable TRANS_DP_CTL */
3082         if (HAS_PCH_CPT(dev) &&
3083             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3085                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3086                 reg = TRANS_DP_CTL(pipe);
3087                 temp = I915_READ(reg);
3088                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3089                           TRANS_DP_SYNC_MASK |
3090                           TRANS_DP_BPC_MASK);
3091                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092                          TRANS_DP_ENH_FRAMING);
3093                 temp |= bpc << 9; /* same format but at 11:9 */
3094
3095                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3096                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3097                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3098                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3099
3100                 switch (intel_trans_dp_port_sel(crtc)) {
3101                 case PCH_DP_B:
3102                         temp |= TRANS_DP_PORT_SEL_B;
3103                         break;
3104                 case PCH_DP_C:
3105                         temp |= TRANS_DP_PORT_SEL_C;
3106                         break;
3107                 case PCH_DP_D:
3108                         temp |= TRANS_DP_PORT_SEL_D;
3109                         break;
3110                 default:
3111                         BUG();
3112                 }
3113
3114                 I915_WRITE(reg, temp);
3115         }
3116
3117         ironlake_enable_pch_transcoder(dev_priv, pipe);
3118 }
3119
3120 static void lpt_pch_enable(struct drm_crtc *crtc)
3121 {
3122         struct drm_device *dev = crtc->dev;
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3126
3127         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3128
3129         lpt_program_iclkip(crtc);
3130
3131         /* Set transcoder timing. */
3132         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3133
3134         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3135 }
3136
3137 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3138 {
3139         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3140
3141         if (pll == NULL)
3142                 return;
3143
3144         if (pll->refcount == 0) {
3145                 WARN(1, "bad %s refcount\n", pll->name);
3146                 return;
3147         }
3148
3149         if (--pll->refcount == 0) {
3150                 WARN_ON(pll->on);
3151                 WARN_ON(pll->active);
3152         }
3153
3154         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3155 }
3156
3157 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3158 {
3159         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161         enum intel_dpll_id i;
3162
3163         if (pll) {
3164                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165                               crtc->base.base.id, pll->name);
3166                 intel_put_shared_dpll(crtc);
3167         }
3168
3169         if (HAS_PCH_IBX(dev_priv->dev)) {
3170                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171                 i = (enum intel_dpll_id) crtc->pipe;
3172                 pll = &dev_priv->shared_dplls[i];
3173
3174                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175                               crtc->base.base.id, pll->name);
3176
3177                 goto found;
3178         }
3179
3180         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181                 pll = &dev_priv->shared_dplls[i];
3182
3183                 /* Only want to check enabled timings first */
3184                 if (pll->refcount == 0)
3185                         continue;
3186
3187                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188                            sizeof(pll->hw_state)) == 0) {
3189                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3190                                       crtc->base.base.id,
3191                                       pll->name, pll->refcount, pll->active);
3192
3193                         goto found;
3194                 }
3195         }
3196
3197         /* Ok no matching timings, maybe there's a free one? */
3198         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199                 pll = &dev_priv->shared_dplls[i];
3200                 if (pll->refcount == 0) {
3201                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202                                       crtc->base.base.id, pll->name);
3203                         goto found;
3204                 }
3205         }
3206
3207         return NULL;
3208
3209 found:
3210         crtc->config.shared_dpll = i;
3211         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212                          pipe_name(crtc->pipe));
3213
3214         if (pll->active == 0) {
3215                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216                        sizeof(pll->hw_state));
3217
3218                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3219                 WARN_ON(pll->on);
3220                 assert_shared_dpll_disabled(dev_priv, pll);
3221
3222                 pll->mode_set(dev_priv, pll);
3223         }
3224         pll->refcount++;
3225
3226         return pll;
3227 }
3228
3229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3230 {
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         int dslreg = PIPEDSL(pipe);
3233         u32 temp;
3234
3235         temp = I915_READ(dslreg);
3236         udelay(500);
3237         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3238                 if (wait_for(I915_READ(dslreg) != temp, 5))
3239                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3240         }
3241 }
3242
3243 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244 {
3245         struct drm_device *dev = crtc->base.dev;
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         int pipe = crtc->pipe;
3248
3249         if (crtc->config.pch_pfit.enabled) {
3250                 /* Force use of hard-coded filter coefficients
3251                  * as some pre-programmed values are broken,
3252                  * e.g. x201.
3253                  */
3254                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256                                                  PF_PIPE_SEL_IVB(pipe));
3257                 else
3258                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3261         }
3262 }
3263
3264 static void intel_enable_planes(struct drm_crtc *crtc)
3265 {
3266         struct drm_device *dev = crtc->dev;
3267         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268         struct intel_plane *intel_plane;
3269
3270         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271                 if (intel_plane->pipe == pipe)
3272                         intel_plane_restore(&intel_plane->base);
3273 }
3274
3275 static void intel_disable_planes(struct drm_crtc *crtc)
3276 {
3277         struct drm_device *dev = crtc->dev;
3278         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279         struct intel_plane *intel_plane;
3280
3281         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282                 if (intel_plane->pipe == pipe)
3283                         intel_plane_disable(&intel_plane->base);
3284 }
3285
3286 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287 {
3288         struct drm_device *dev = crtc->dev;
3289         struct drm_i915_private *dev_priv = dev->dev_private;
3290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291         struct intel_encoder *encoder;
3292         int pipe = intel_crtc->pipe;
3293         int plane = intel_crtc->plane;
3294
3295         WARN_ON(!crtc->enabled);
3296
3297         if (intel_crtc->active)
3298                 return;
3299
3300         intel_crtc->active = true;
3301
3302         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
3305         for_each_encoder_on_crtc(dev, crtc, encoder)
3306                 if (encoder->pre_enable)
3307                         encoder->pre_enable(encoder);
3308
3309         if (intel_crtc->config.has_pch_encoder) {
3310                 /* Note: FDI PLL enabling _must_ be done before we enable the
3311                  * cpu pipes, hence this is separate from all the other fdi/pch
3312                  * enabling. */
3313                 ironlake_fdi_pll_enable(intel_crtc);
3314         } else {
3315                 assert_fdi_tx_disabled(dev_priv, pipe);
3316                 assert_fdi_rx_disabled(dev_priv, pipe);
3317         }
3318
3319         ironlake_pfit_enable(intel_crtc);
3320
3321         /*
3322          * On ILK+ LUT must be loaded before the pipe is running but with
3323          * clocks enabled
3324          */
3325         intel_crtc_load_lut(crtc);
3326
3327         intel_update_watermarks(crtc);
3328         intel_enable_pipe(dev_priv, pipe,
3329                           intel_crtc->config.has_pch_encoder, false);
3330         intel_enable_plane(dev_priv, plane, pipe);
3331         intel_enable_planes(crtc);
3332         intel_crtc_update_cursor(crtc, true);
3333
3334         if (intel_crtc->config.has_pch_encoder)
3335                 ironlake_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         for_each_encoder_on_crtc(dev, crtc, encoder)
3342                 encoder->enable(encoder);
3343
3344         if (HAS_PCH_CPT(dev))
3345                 cpt_verify_modeset(dev, intel_crtc->pipe);
3346
3347         /*
3348          * There seems to be a race in PCH platform hw (at least on some
3349          * outputs) where an enabled pipe still completes any pageflip right
3350          * away (as if the pipe is off) instead of waiting for vblank. As soon
3351          * as the first vblank happend, everything works as expected. Hence just
3352          * wait for one vblank before returning to avoid strange things
3353          * happening.
3354          */
3355         intel_wait_for_vblank(dev, intel_crtc->pipe);
3356 }
3357
3358 /* IPS only exists on ULT machines and is tied to pipe A. */
3359 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360 {
3361         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3362 }
3363
3364 static void hsw_enable_ips(struct intel_crtc *crtc)
3365 {
3366         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368         if (!crtc->config.ips_enabled)
3369                 return;
3370
3371         /* We can only enable IPS after we enable a plane and wait for a vblank.
3372          * We guarantee that the plane is enabled by calling intel_enable_ips
3373          * only after intel_enable_plane. And intel_enable_plane already waits
3374          * for a vblank, so all we need to do here is to enable the IPS bit. */
3375         assert_plane_enabled(dev_priv, crtc->plane);
3376         I915_WRITE(IPS_CTL, IPS_ENABLE);
3377 }
3378
3379 static void hsw_disable_ips(struct intel_crtc *crtc)
3380 {
3381         struct drm_device *dev = crtc->base.dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384         if (!crtc->config.ips_enabled)
3385                 return;
3386
3387         assert_plane_enabled(dev_priv, crtc->plane);
3388         I915_WRITE(IPS_CTL, 0);
3389         POSTING_READ(IPS_CTL);
3390
3391         /* We need to wait for a vblank before we can disable the plane. */
3392         intel_wait_for_vblank(dev, crtc->pipe);
3393 }
3394
3395 static void haswell_crtc_enable(struct drm_crtc *crtc)
3396 {
3397         struct drm_device *dev = crtc->dev;
3398         struct drm_i915_private *dev_priv = dev->dev_private;
3399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3400         struct intel_encoder *encoder;
3401         int pipe = intel_crtc->pipe;
3402         int plane = intel_crtc->plane;
3403
3404         WARN_ON(!crtc->enabled);
3405
3406         if (intel_crtc->active)
3407                 return;
3408
3409         intel_crtc->active = true;
3410
3411         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3412         if (intel_crtc->config.has_pch_encoder)
3413                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3414
3415         if (intel_crtc->config.has_pch_encoder)
3416                 dev_priv->display.fdi_link_train(crtc);
3417
3418         for_each_encoder_on_crtc(dev, crtc, encoder)
3419                 if (encoder->pre_enable)
3420                         encoder->pre_enable(encoder);
3421
3422         intel_ddi_enable_pipe_clock(intel_crtc);
3423
3424         ironlake_pfit_enable(intel_crtc);
3425
3426         /*
3427          * On ILK+ LUT must be loaded before the pipe is running but with
3428          * clocks enabled
3429          */
3430         intel_crtc_load_lut(crtc);
3431
3432         intel_ddi_set_pipe_settings(crtc);
3433         intel_ddi_enable_transcoder_func(crtc);
3434
3435         intel_update_watermarks(crtc);
3436         intel_enable_pipe(dev_priv, pipe,
3437                           intel_crtc->config.has_pch_encoder, false);
3438         intel_enable_plane(dev_priv, plane, pipe);
3439         intel_enable_planes(crtc);
3440         intel_crtc_update_cursor(crtc, true);
3441
3442         hsw_enable_ips(intel_crtc);
3443
3444         if (intel_crtc->config.has_pch_encoder)
3445                 lpt_pch_enable(crtc);
3446
3447         mutex_lock(&dev->struct_mutex);
3448         intel_update_fbc(dev);
3449         mutex_unlock(&dev->struct_mutex);
3450
3451         for_each_encoder_on_crtc(dev, crtc, encoder) {
3452                 encoder->enable(encoder);
3453                 intel_opregion_notify_encoder(encoder, true);
3454         }
3455
3456         /*
3457          * There seems to be a race in PCH platform hw (at least on some
3458          * outputs) where an enabled pipe still completes any pageflip right
3459          * away (as if the pipe is off) instead of waiting for vblank. As soon
3460          * as the first vblank happend, everything works as expected. Hence just
3461          * wait for one vblank before returning to avoid strange things
3462          * happening.
3463          */
3464         intel_wait_for_vblank(dev, intel_crtc->pipe);
3465 }
3466
3467 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3468 {
3469         struct drm_device *dev = crtc->base.dev;
3470         struct drm_i915_private *dev_priv = dev->dev_private;
3471         int pipe = crtc->pipe;
3472
3473         /* To avoid upsetting the power well on haswell only disable the pfit if
3474          * it's in use. The hw state code will make sure we get this right. */
3475         if (crtc->config.pch_pfit.enabled) {
3476                 I915_WRITE(PF_CTL(pipe), 0);
3477                 I915_WRITE(PF_WIN_POS(pipe), 0);
3478                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3479         }
3480 }
3481
3482 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3483 {
3484         struct drm_device *dev = crtc->dev;
3485         struct drm_i915_private *dev_priv = dev->dev_private;
3486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3487         struct intel_encoder *encoder;
3488         int pipe = intel_crtc->pipe;
3489         int plane = intel_crtc->plane;
3490         u32 reg, temp;
3491
3492
3493         if (!intel_crtc->active)
3494                 return;
3495
3496         for_each_encoder_on_crtc(dev, crtc, encoder)
3497                 encoder->disable(encoder);
3498
3499         intel_crtc_wait_for_pending_flips(crtc);
3500         drm_vblank_off(dev, pipe);
3501
3502         if (dev_priv->fbc.plane == plane)
3503                 intel_disable_fbc(dev);
3504
3505         intel_crtc_update_cursor(crtc, false);
3506         intel_disable_planes(crtc);
3507         intel_disable_plane(dev_priv, plane, pipe);
3508
3509         if (intel_crtc->config.has_pch_encoder)
3510                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3511
3512         intel_disable_pipe(dev_priv, pipe);
3513
3514         ironlake_pfit_disable(intel_crtc);
3515
3516         for_each_encoder_on_crtc(dev, crtc, encoder)
3517                 if (encoder->post_disable)
3518                         encoder->post_disable(encoder);
3519
3520         if (intel_crtc->config.has_pch_encoder) {
3521                 ironlake_fdi_disable(crtc);
3522
3523                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3524                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3525
3526                 if (HAS_PCH_CPT(dev)) {
3527                         /* disable TRANS_DP_CTL */
3528                         reg = TRANS_DP_CTL(pipe);
3529                         temp = I915_READ(reg);
3530                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3531                                   TRANS_DP_PORT_SEL_MASK);
3532                         temp |= TRANS_DP_PORT_SEL_NONE;
3533                         I915_WRITE(reg, temp);
3534
3535                         /* disable DPLL_SEL */
3536                         temp = I915_READ(PCH_DPLL_SEL);
3537                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3538                         I915_WRITE(PCH_DPLL_SEL, temp);
3539                 }
3540
3541                 /* disable PCH DPLL */
3542                 intel_disable_shared_dpll(intel_crtc);
3543
3544                 ironlake_fdi_pll_disable(intel_crtc);
3545         }
3546
3547         intel_crtc->active = false;
3548         intel_update_watermarks(crtc);
3549
3550         mutex_lock(&dev->struct_mutex);
3551         intel_update_fbc(dev);
3552         mutex_unlock(&dev->struct_mutex);
3553 }
3554
3555 static void haswell_crtc_disable(struct drm_crtc *crtc)
3556 {
3557         struct drm_device *dev = crtc->dev;
3558         struct drm_i915_private *dev_priv = dev->dev_private;
3559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3560         struct intel_encoder *encoder;
3561         int pipe = intel_crtc->pipe;
3562         int plane = intel_crtc->plane;
3563         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3564
3565         if (!intel_crtc->active)
3566                 return;
3567
3568         for_each_encoder_on_crtc(dev, crtc, encoder) {
3569                 intel_opregion_notify_encoder(encoder, false);
3570                 encoder->disable(encoder);
3571         }
3572
3573         intel_crtc_wait_for_pending_flips(crtc);
3574         drm_vblank_off(dev, pipe);
3575
3576         /* FBC must be disabled before disabling the plane on HSW. */
3577         if (dev_priv->fbc.plane == plane)
3578                 intel_disable_fbc(dev);
3579
3580         hsw_disable_ips(intel_crtc);
3581
3582         intel_crtc_update_cursor(crtc, false);
3583         intel_disable_planes(crtc);
3584         intel_disable_plane(dev_priv, plane, pipe);
3585
3586         if (intel_crtc->config.has_pch_encoder)
3587                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3588         intel_disable_pipe(dev_priv, pipe);
3589
3590         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3591
3592         ironlake_pfit_disable(intel_crtc);
3593
3594         intel_ddi_disable_pipe_clock(intel_crtc);
3595
3596         for_each_encoder_on_crtc(dev, crtc, encoder)
3597                 if (encoder->post_disable)
3598                         encoder->post_disable(encoder);
3599
3600         if (intel_crtc->config.has_pch_encoder) {
3601                 lpt_disable_pch_transcoder(dev_priv);
3602                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3603                 intel_ddi_fdi_disable(crtc);
3604         }
3605
3606         intel_crtc->active = false;
3607         intel_update_watermarks(crtc);
3608
3609         mutex_lock(&dev->struct_mutex);
3610         intel_update_fbc(dev);
3611         mutex_unlock(&dev->struct_mutex);
3612 }
3613
3614 static void ironlake_crtc_off(struct drm_crtc *crtc)
3615 {
3616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617         intel_put_shared_dpll(intel_crtc);
3618 }
3619
3620 static void haswell_crtc_off(struct drm_crtc *crtc)
3621 {
3622         intel_ddi_put_crtc_pll(crtc);
3623 }
3624
3625 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3626 {
3627         if (!enable && intel_crtc->overlay) {
3628                 struct drm_device *dev = intel_crtc->base.dev;
3629                 struct drm_i915_private *dev_priv = dev->dev_private;
3630
3631                 mutex_lock(&dev->struct_mutex);
3632                 dev_priv->mm.interruptible = false;
3633                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3634                 dev_priv->mm.interruptible = true;
3635                 mutex_unlock(&dev->struct_mutex);
3636         }
3637
3638         /* Let userspace switch the overlay on again. In most cases userspace
3639          * has to recompute where to put it anyway.
3640          */
3641 }
3642
3643 /**
3644  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3645  * cursor plane briefly if not already running after enabling the display
3646  * plane.
3647  * This workaround avoids occasional blank screens when self refresh is
3648  * enabled.
3649  */
3650 static void
3651 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3652 {
3653         u32 cntl = I915_READ(CURCNTR(pipe));
3654
3655         if ((cntl & CURSOR_MODE) == 0) {
3656                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3657
3658                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3659                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3660                 intel_wait_for_vblank(dev_priv->dev, pipe);
3661                 I915_WRITE(CURCNTR(pipe), cntl);
3662                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3663                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3664         }
3665 }
3666
3667 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3668 {
3669         struct drm_device *dev = crtc->base.dev;
3670         struct drm_i915_private *dev_priv = dev->dev_private;
3671         struct intel_crtc_config *pipe_config = &crtc->config;
3672
3673         if (!crtc->config.gmch_pfit.control)
3674                 return;
3675
3676         /*
3677          * The panel fitter should only be adjusted whilst the pipe is disabled,
3678          * according to register description and PRM.
3679          */
3680         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3681         assert_pipe_disabled(dev_priv, crtc->pipe);
3682
3683         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3684         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3685
3686         /* Border color in case we don't scale up to the full screen. Black by
3687          * default, change to something else for debugging. */
3688         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3689 }
3690
3691 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3692 {
3693         struct drm_device *dev = crtc->dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696         struct intel_encoder *encoder;
3697         int pipe = intel_crtc->pipe;
3698         int plane = intel_crtc->plane;
3699         bool is_dsi;
3700
3701         WARN_ON(!crtc->enabled);
3702
3703         if (intel_crtc->active)
3704                 return;
3705
3706         intel_crtc->active = true;
3707
3708         for_each_encoder_on_crtc(dev, crtc, encoder)
3709                 if (encoder->pre_pll_enable)
3710                         encoder->pre_pll_enable(encoder);
3711
3712         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3713
3714         if (!is_dsi)
3715                 vlv_enable_pll(intel_crtc);
3716
3717         for_each_encoder_on_crtc(dev, crtc, encoder)
3718                 if (encoder->pre_enable)
3719                         encoder->pre_enable(encoder);
3720
3721         i9xx_pfit_enable(intel_crtc);
3722
3723         intel_crtc_load_lut(crtc);
3724
3725         intel_update_watermarks(crtc);
3726         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3727         intel_enable_plane(dev_priv, plane, pipe);
3728         intel_enable_planes(crtc);
3729         intel_crtc_update_cursor(crtc, true);
3730
3731         intel_update_fbc(dev);
3732
3733         for_each_encoder_on_crtc(dev, crtc, encoder)
3734                 encoder->enable(encoder);
3735 }
3736
3737 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         struct intel_encoder *encoder;
3743         int pipe = intel_crtc->pipe;
3744         int plane = intel_crtc->plane;
3745
3746         WARN_ON(!crtc->enabled);
3747
3748         if (intel_crtc->active)
3749                 return;
3750
3751         intel_crtc->active = true;
3752
3753         for_each_encoder_on_crtc(dev, crtc, encoder)
3754                 if (encoder->pre_enable)
3755                         encoder->pre_enable(encoder);
3756
3757         i9xx_enable_pll(intel_crtc);
3758
3759         i9xx_pfit_enable(intel_crtc);
3760
3761         intel_crtc_load_lut(crtc);
3762
3763         intel_update_watermarks(crtc);
3764         intel_enable_pipe(dev_priv, pipe, false, false);
3765         intel_enable_plane(dev_priv, plane, pipe);
3766         intel_enable_planes(crtc);
3767         /* The fixup needs to happen before cursor is enabled */
3768         if (IS_G4X(dev))
3769                 g4x_fixup_plane(dev_priv, pipe);
3770         intel_crtc_update_cursor(crtc, true);
3771
3772         /* Give the overlay scaler a chance to enable if it's on this pipe */
3773         intel_crtc_dpms_overlay(intel_crtc, true);
3774
3775         intel_update_fbc(dev);
3776
3777         for_each_encoder_on_crtc(dev, crtc, encoder)
3778                 encoder->enable(encoder);
3779 }
3780
3781 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3782 {
3783         struct drm_device *dev = crtc->base.dev;
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785
3786         if (!crtc->config.gmch_pfit.control)
3787                 return;
3788
3789         assert_pipe_disabled(dev_priv, crtc->pipe);
3790
3791         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3792                          I915_READ(PFIT_CONTROL));
3793         I915_WRITE(PFIT_CONTROL, 0);
3794 }
3795
3796 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3797 {
3798         struct drm_device *dev = crtc->dev;
3799         struct drm_i915_private *dev_priv = dev->dev_private;
3800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3801         struct intel_encoder *encoder;
3802         int pipe = intel_crtc->pipe;
3803         int plane = intel_crtc->plane;
3804
3805         if (!intel_crtc->active)
3806                 return;
3807
3808         for_each_encoder_on_crtc(dev, crtc, encoder)
3809                 encoder->disable(encoder);
3810
3811         /* Give the overlay scaler a chance to disable if it's on this pipe */
3812         intel_crtc_wait_for_pending_flips(crtc);
3813         drm_vblank_off(dev, pipe);
3814
3815         if (dev_priv->fbc.plane == plane)
3816                 intel_disable_fbc(dev);
3817
3818         intel_crtc_dpms_overlay(intel_crtc, false);
3819         intel_crtc_update_cursor(crtc, false);
3820         intel_disable_planes(crtc);
3821         intel_disable_plane(dev_priv, plane, pipe);
3822
3823         intel_disable_pipe(dev_priv, pipe);
3824
3825         i9xx_pfit_disable(intel_crtc);
3826
3827         for_each_encoder_on_crtc(dev, crtc, encoder)
3828                 if (encoder->post_disable)
3829                         encoder->post_disable(encoder);
3830
3831         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3832                 i9xx_disable_pll(dev_priv, pipe);
3833
3834         intel_crtc->active = false;
3835         intel_update_watermarks(crtc);
3836
3837         intel_update_fbc(dev);
3838 }
3839
3840 static void i9xx_crtc_off(struct drm_crtc *crtc)
3841 {
3842 }
3843
3844 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3845                                     bool enabled)
3846 {
3847         struct drm_device *dev = crtc->dev;
3848         struct drm_i915_master_private *master_priv;
3849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3850         int pipe = intel_crtc->pipe;
3851
3852         if (!dev->primary->master)
3853                 return;
3854
3855         master_priv = dev->primary->master->driver_priv;
3856         if (!master_priv->sarea_priv)
3857                 return;
3858
3859         switch (pipe) {
3860         case 0:
3861                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3862                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3863                 break;
3864         case 1:
3865                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3866                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3867                 break;
3868         default:
3869                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3870                 break;
3871         }
3872 }
3873
3874 /**
3875  * Sets the power management mode of the pipe and plane.
3876  */
3877 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3878 {
3879         struct drm_device *dev = crtc->dev;
3880         struct drm_i915_private *dev_priv = dev->dev_private;
3881         struct intel_encoder *intel_encoder;
3882         bool enable = false;
3883
3884         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3885                 enable |= intel_encoder->connectors_active;
3886
3887         if (enable)
3888                 dev_priv->display.crtc_enable(crtc);
3889         else
3890                 dev_priv->display.crtc_disable(crtc);
3891
3892         intel_crtc_update_sarea(crtc, enable);
3893 }
3894
3895 static void intel_crtc_disable(struct drm_crtc *crtc)
3896 {
3897         struct drm_device *dev = crtc->dev;
3898         struct drm_connector *connector;
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3901
3902         /* crtc should still be enabled when we disable it. */
3903         WARN_ON(!crtc->enabled);
3904
3905         dev_priv->display.crtc_disable(crtc);
3906         intel_crtc->eld_vld = false;
3907         intel_crtc_update_sarea(crtc, false);
3908         dev_priv->display.off(crtc);
3909
3910         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3911         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
3912         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3913
3914         if (crtc->fb) {
3915                 mutex_lock(&dev->struct_mutex);
3916                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3917                 mutex_unlock(&dev->struct_mutex);
3918                 crtc->fb = NULL;
3919         }
3920
3921         /* Update computed state. */
3922         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3923                 if (!connector->encoder || !connector->encoder->crtc)
3924                         continue;
3925
3926                 if (connector->encoder->crtc != crtc)
3927                         continue;
3928
3929                 connector->dpms = DRM_MODE_DPMS_OFF;
3930                 to_intel_encoder(connector->encoder)->connectors_active = false;
3931         }
3932 }
3933
3934 void intel_encoder_destroy(struct drm_encoder *encoder)
3935 {
3936         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3937
3938         drm_encoder_cleanup(encoder);
3939         kfree(intel_encoder);
3940 }
3941
3942 /* Simple dpms helper for encoders with just one connector, no cloning and only
3943  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3944  * state of the entire output pipe. */
3945 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3946 {
3947         if (mode == DRM_MODE_DPMS_ON) {
3948                 encoder->connectors_active = true;
3949
3950                 intel_crtc_update_dpms(encoder->base.crtc);
3951         } else {
3952                 encoder->connectors_active = false;
3953
3954                 intel_crtc_update_dpms(encoder->base.crtc);
3955         }
3956 }
3957
3958 /* Cross check the actual hw state with our own modeset state tracking (and it's
3959  * internal consistency). */
3960 static void intel_connector_check_state(struct intel_connector *connector)
3961 {
3962         if (connector->get_hw_state(connector)) {
3963                 struct intel_encoder *encoder = connector->encoder;
3964                 struct drm_crtc *crtc;
3965                 bool encoder_enabled;
3966                 enum pipe pipe;
3967
3968                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3969                               connector->base.base.id,
3970                               drm_get_connector_name(&connector->base));
3971
3972                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3973                      "wrong connector dpms state\n");
3974                 WARN(connector->base.encoder != &encoder->base,
3975                      "active connector not linked to encoder\n");
3976                 WARN(!encoder->connectors_active,
3977                      "encoder->connectors_active not set\n");
3978
3979                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3980                 WARN(!encoder_enabled, "encoder not enabled\n");
3981                 if (WARN_ON(!encoder->base.crtc))
3982                         return;
3983
3984                 crtc = encoder->base.crtc;
3985
3986                 WARN(!crtc->enabled, "crtc not enabled\n");
3987                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3988                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3989                      "encoder active on the wrong pipe\n");
3990         }
3991 }
3992
3993 /* Even simpler default implementation, if there's really no special case to
3994  * consider. */
3995 void intel_connector_dpms(struct drm_connector *connector, int mode)
3996 {
3997         struct intel_encoder *encoder = intel_attached_encoder(connector);
3998
3999         /* All the simple cases only support two dpms states. */
4000         if (mode != DRM_MODE_DPMS_ON)
4001                 mode = DRM_MODE_DPMS_OFF;
4002
4003         if (mode == connector->dpms)
4004                 return;
4005
4006         connector->dpms = mode;
4007
4008         /* Only need to change hw state when actually enabled */
4009         if (encoder->base.crtc)
4010                 intel_encoder_dpms(encoder, mode);
4011         else
4012                 WARN_ON(encoder->connectors_active != false);
4013
4014         intel_modeset_check_state(connector->dev);
4015 }
4016
4017 /* Simple connector->get_hw_state implementation for encoders that support only
4018  * one connector and no cloning and hence the encoder state determines the state
4019  * of the connector. */
4020 bool intel_connector_get_hw_state(struct intel_connector *connector)
4021 {
4022         enum pipe pipe = 0;
4023         struct intel_encoder *encoder = connector->encoder;
4024
4025         return encoder->get_hw_state(encoder, &pipe);
4026 }
4027
4028 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4029                                      struct intel_crtc_config *pipe_config)
4030 {
4031         struct drm_i915_private *dev_priv = dev->dev_private;
4032         struct intel_crtc *pipe_B_crtc =
4033                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4034
4035         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4036                       pipe_name(pipe), pipe_config->fdi_lanes);
4037         if (pipe_config->fdi_lanes > 4) {
4038                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4039                               pipe_name(pipe), pipe_config->fdi_lanes);
4040                 return false;
4041         }
4042
4043         if (IS_HASWELL(dev)) {
4044                 if (pipe_config->fdi_lanes > 2) {
4045                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4046                                       pipe_config->fdi_lanes);
4047                         return false;
4048                 } else {
4049                         return true;
4050                 }
4051         }
4052
4053         if (INTEL_INFO(dev)->num_pipes == 2)
4054                 return true;
4055
4056         /* Ivybridge 3 pipe is really complicated */
4057         switch (pipe) {
4058         case PIPE_A:
4059                 return true;
4060         case PIPE_B:
4061                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4062                     pipe_config->fdi_lanes > 2) {
4063                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4064                                       pipe_name(pipe), pipe_config->fdi_lanes);
4065                         return false;
4066                 }
4067                 return true;
4068         case PIPE_C:
4069                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4070                     pipe_B_crtc->config.fdi_lanes <= 2) {
4071                         if (pipe_config->fdi_lanes > 2) {
4072                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4073                                               pipe_name(pipe), pipe_config->fdi_lanes);
4074                                 return false;
4075                         }
4076                 } else {
4077                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4078                         return false;
4079                 }
4080                 return true;
4081         default:
4082                 BUG();
4083         }
4084 }
4085
4086 #define RETRY 1
4087 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4088                                        struct intel_crtc_config *pipe_config)
4089 {
4090         struct drm_device *dev = intel_crtc->base.dev;
4091         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4092         int lane, link_bw, fdi_dotclock;
4093         bool setup_ok, needs_recompute = false;
4094
4095 retry:
4096         /* FDI is a binary signal running at ~2.7GHz, encoding
4097          * each output octet as 10 bits. The actual frequency
4098          * is stored as a divider into a 100MHz clock, and the
4099          * mode pixel clock is stored in units of 1KHz.
4100          * Hence the bw of each lane in terms of the mode signal
4101          * is:
4102          */
4103         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4104
4105         fdi_dotclock = adjusted_mode->clock;
4106
4107         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4108                                            pipe_config->pipe_bpp);
4109
4110         pipe_config->fdi_lanes = lane;
4111
4112         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4113                                link_bw, &pipe_config->fdi_m_n);
4114
4115         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4116                                             intel_crtc->pipe, pipe_config);
4117         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4118                 pipe_config->pipe_bpp -= 2*3;
4119                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4120                               pipe_config->pipe_bpp);
4121                 needs_recompute = true;
4122                 pipe_config->bw_constrained = true;
4123
4124                 goto retry;
4125         }
4126
4127         if (needs_recompute)
4128                 return RETRY;
4129
4130         return setup_ok ? 0 : -EINVAL;
4131 }
4132
4133 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4134                                    struct intel_crtc_config *pipe_config)
4135 {
4136         pipe_config->ips_enabled = i915_enable_ips &&
4137                                    hsw_crtc_supports_ips(crtc) &&
4138                                    pipe_config->pipe_bpp <= 24;
4139 }
4140
4141 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4142                                      struct intel_crtc_config *pipe_config)
4143 {
4144         struct drm_device *dev = crtc->base.dev;
4145         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4146
4147         /* FIXME should check pixel clock limits on all platforms */
4148         if (INTEL_INFO(dev)->gen < 4) {
4149                 struct drm_i915_private *dev_priv = dev->dev_private;
4150                 int clock_limit =
4151                         dev_priv->display.get_display_clock_speed(dev);
4152
4153                 /*
4154                  * Enable pixel doubling when the dot clock
4155                  * is > 90% of the (display) core speed.
4156                  *
4157                  * GDG double wide on either pipe,
4158                  * otherwise pipe A only.
4159                  */
4160                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4161                     adjusted_mode->clock > clock_limit * 9 / 10) {
4162                         clock_limit *= 2;
4163                         pipe_config->double_wide = true;
4164                 }
4165
4166                 if (adjusted_mode->clock > clock_limit * 9 / 10)
4167                         return -EINVAL;
4168         }
4169
4170         /*
4171          * Pipe horizontal size must be even in:
4172          * - DVO ganged mode
4173          * - LVDS dual channel mode
4174          * - Double wide pipe
4175          */
4176         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4177              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4178                 pipe_config->pipe_src_w &= ~1;
4179
4180         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4181          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4182          */
4183         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4184                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4185                 return -EINVAL;
4186
4187         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4188                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4189         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4190                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4191                  * for lvds. */
4192                 pipe_config->pipe_bpp = 8*3;
4193         }
4194
4195         if (HAS_IPS(dev))
4196                 hsw_compute_ips_config(crtc, pipe_config);
4197
4198         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4199          * clock survives for now. */
4200         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4201                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4202
4203         if (pipe_config->has_pch_encoder)
4204                 return ironlake_fdi_compute_config(crtc, pipe_config);
4205
4206         return 0;
4207 }
4208
4209 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4210 {
4211         return 400000; /* FIXME */
4212 }
4213
4214 static int i945_get_display_clock_speed(struct drm_device *dev)
4215 {
4216         return 400000;
4217 }
4218
4219 static int i915_get_display_clock_speed(struct drm_device *dev)
4220 {
4221         return 333000;
4222 }
4223
4224 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4225 {
4226         return 200000;
4227 }
4228
4229 static int pnv_get_display_clock_speed(struct drm_device *dev)
4230 {
4231         u16 gcfgc = 0;
4232
4233         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4234
4235         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4236         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4237                 return 267000;
4238         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4239                 return 333000;
4240         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4241                 return 444000;
4242         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4243                 return 200000;
4244         default:
4245                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4246         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4247                 return 133000;
4248         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4249                 return 167000;
4250         }
4251 }
4252
4253 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4254 {
4255         u16 gcfgc = 0;
4256
4257         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4258
4259         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4260                 return 133000;
4261         else {
4262                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4263                 case GC_DISPLAY_CLOCK_333_MHZ:
4264                         return 333000;
4265                 default:
4266                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4267                         return 190000;
4268                 }
4269         }
4270 }
4271
4272 static int i865_get_display_clock_speed(struct drm_device *dev)
4273 {
4274         return 266000;
4275 }
4276
4277 static int i855_get_display_clock_speed(struct drm_device *dev)
4278 {
4279         u16 hpllcc = 0;
4280         /* Assume that the hardware is in the high speed state.  This
4281          * should be the default.
4282          */
4283         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4284         case GC_CLOCK_133_200:
4285         case GC_CLOCK_100_200:
4286                 return 200000;
4287         case GC_CLOCK_166_250:
4288                 return 250000;
4289         case GC_CLOCK_100_133:
4290                 return 133000;
4291         }
4292
4293         /* Shouldn't happen */
4294         return 0;
4295 }
4296
4297 static int i830_get_display_clock_speed(struct drm_device *dev)
4298 {
4299         return 133000;
4300 }
4301
4302 static void
4303 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4304 {
4305         while (*num > DATA_LINK_M_N_MASK ||
4306                *den > DATA_LINK_M_N_MASK) {
4307                 *num >>= 1;
4308                 *den >>= 1;
4309         }
4310 }
4311
4312 static void compute_m_n(unsigned int m, unsigned int n,
4313                         uint32_t *ret_m, uint32_t *ret_n)
4314 {
4315         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4316         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4317         intel_reduce_m_n_ratio(ret_m, ret_n);
4318 }
4319
4320 void
4321 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4322                        int pixel_clock, int link_clock,
4323                        struct intel_link_m_n *m_n)
4324 {
4325         m_n->tu = 64;
4326
4327         compute_m_n(bits_per_pixel * pixel_clock,
4328                     link_clock * nlanes * 8,
4329                     &m_n->gmch_m, &m_n->gmch_n);
4330
4331         compute_m_n(pixel_clock, link_clock,
4332                     &m_n->link_m, &m_n->link_n);
4333 }
4334
4335 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4336 {
4337         if (i915_panel_use_ssc >= 0)
4338                 return i915_panel_use_ssc != 0;
4339         return dev_priv->vbt.lvds_use_ssc
4340                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4341 }
4342
4343 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4344 {
4345         struct drm_device *dev = crtc->dev;
4346         struct drm_i915_private *dev_priv = dev->dev_private;
4347         int refclk;
4348
4349         if (IS_VALLEYVIEW(dev)) {
4350                 refclk = 100000;
4351         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4352             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4353                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4354                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4355                               refclk / 1000);
4356         } else if (!IS_GEN2(dev)) {
4357                 refclk = 96000;
4358         } else {
4359                 refclk = 48000;
4360         }
4361
4362         return refclk;
4363 }
4364
4365 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4366 {
4367         return (1 << dpll->n) << 16 | dpll->m2;
4368 }
4369
4370 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4371 {
4372         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4373 }
4374
4375 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4376                                      intel_clock_t *reduced_clock)
4377 {
4378         struct drm_device *dev = crtc->base.dev;
4379         struct drm_i915_private *dev_priv = dev->dev_private;
4380         int pipe = crtc->pipe;
4381         u32 fp, fp2 = 0;
4382
4383         if (IS_PINEVIEW(dev)) {
4384                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4385                 if (reduced_clock)
4386                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4387         } else {
4388                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4389                 if (reduced_clock)
4390                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4391         }
4392
4393         I915_WRITE(FP0(pipe), fp);
4394         crtc->config.dpll_hw_state.fp0 = fp;
4395
4396         crtc->lowfreq_avail = false;
4397         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4398             reduced_clock && i915_powersave) {
4399                 I915_WRITE(FP1(pipe), fp2);
4400                 crtc->config.dpll_hw_state.fp1 = fp2;
4401                 crtc->lowfreq_avail = true;
4402         } else {
4403                 I915_WRITE(FP1(pipe), fp);
4404                 crtc->config.dpll_hw_state.fp1 = fp;
4405         }
4406 }
4407
4408 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4409                 pipe)
4410 {
4411         u32 reg_val;
4412
4413         /*
4414          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4415          * and set it to a reasonable value instead.
4416          */
4417         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4418         reg_val &= 0xffffff00;
4419         reg_val |= 0x00000030;
4420         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4421
4422         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4423         reg_val &= 0x8cffffff;
4424         reg_val = 0x8c000000;
4425         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4426
4427         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4428         reg_val &= 0xffffff00;
4429         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4430
4431         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4432         reg_val &= 0x00ffffff;
4433         reg_val |= 0xb0000000;
4434         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4435 }
4436
4437 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4438                                          struct intel_link_m_n *m_n)
4439 {
4440         struct drm_device *dev = crtc->base.dev;
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         int pipe = crtc->pipe;
4443
4444         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4445         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4446         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4447         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4448 }
4449
4450 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4451                                          struct intel_link_m_n *m_n)
4452 {
4453         struct drm_device *dev = crtc->base.dev;
4454         struct drm_i915_private *dev_priv = dev->dev_private;
4455         int pipe = crtc->pipe;
4456         enum transcoder transcoder = crtc->config.cpu_transcoder;
4457
4458         if (INTEL_INFO(dev)->gen >= 5) {
4459                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4460                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4461                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4462                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4463         } else {
4464                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4465                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4466                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4467                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4468         }
4469 }
4470
4471 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4472 {
4473         if (crtc->config.has_pch_encoder)
4474                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4475         else
4476                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4477 }
4478
4479 static void vlv_update_pll(struct intel_crtc *crtc)
4480 {
4481         struct drm_device *dev = crtc->base.dev;
4482         struct drm_i915_private *dev_priv = dev->dev_private;
4483         int pipe = crtc->pipe;
4484         u32 dpll, mdiv;
4485         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4486         u32 coreclk, reg_val, dpll_md;
4487
4488         mutex_lock(&dev_priv->dpio_lock);
4489
4490         bestn = crtc->config.dpll.n;
4491         bestm1 = crtc->config.dpll.m1;
4492         bestm2 = crtc->config.dpll.m2;
4493         bestp1 = crtc->config.dpll.p1;
4494         bestp2 = crtc->config.dpll.p2;
4495
4496         /* See eDP HDMI DPIO driver vbios notes doc */
4497
4498         /* PLL B needs special handling */
4499         if (pipe)
4500                 vlv_pllb_recal_opamp(dev_priv, pipe);
4501
4502         /* Set up Tx target for periodic Rcomp update */
4503         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4504
4505         /* Disable target IRef on PLL */
4506         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4507         reg_val &= 0x00ffffff;
4508         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4509
4510         /* Disable fast lock */
4511         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4512
4513         /* Set idtafcrecal before PLL is enabled */
4514         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4515         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4516         mdiv |= ((bestn << DPIO_N_SHIFT));
4517         mdiv |= (1 << DPIO_K_SHIFT);
4518
4519         /*
4520          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4521          * but we don't support that).
4522          * Note: don't use the DAC post divider as it seems unstable.
4523          */
4524         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4525         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4526
4527         mdiv |= DPIO_ENABLE_CALIBRATION;
4528         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4529
4530         /* Set HBR and RBR LPF coefficients */
4531         if (crtc->config.port_clock == 162000 ||
4532             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4533             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4534                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4535                                  0x009f0003);
4536         else
4537                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4538                                  0x00d0000f);
4539
4540         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4541             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4542                 /* Use SSC source */
4543                 if (!pipe)
4544                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4545                                          0x0df40000);
4546                 else
4547                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4548                                          0x0df70000);
4549         } else { /* HDMI or VGA */
4550                 /* Use bend source */
4551                 if (!pipe)
4552                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4553                                          0x0df70000);
4554                 else
4555                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4556                                          0x0df40000);
4557         }
4558
4559         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4560         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4561         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4562             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4563                 coreclk |= 0x01000000;
4564         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4565
4566         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4567
4568         /* Enable DPIO clock input */
4569         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4570                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4571         if (pipe)
4572                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4573
4574         dpll |= DPLL_VCO_ENABLE;
4575         crtc->config.dpll_hw_state.dpll = dpll;
4576
4577         dpll_md = (crtc->config.pixel_multiplier - 1)
4578                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4579         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4580
4581         if (crtc->config.has_dp_encoder)
4582                 intel_dp_set_m_n(crtc);
4583
4584         mutex_unlock(&dev_priv->dpio_lock);
4585 }
4586
4587 static void i9xx_update_pll(struct intel_crtc *crtc,
4588                             intel_clock_t *reduced_clock,
4589                             int num_connectors)
4590 {
4591         struct drm_device *dev = crtc->base.dev;
4592         struct drm_i915_private *dev_priv = dev->dev_private;
4593         u32 dpll;
4594         bool is_sdvo;
4595         struct dpll *clock = &crtc->config.dpll;
4596
4597         i9xx_update_pll_dividers(crtc, reduced_clock);
4598
4599         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4600                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4601
4602         dpll = DPLL_VGA_MODE_DIS;
4603
4604         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4605                 dpll |= DPLLB_MODE_LVDS;
4606         else
4607                 dpll |= DPLLB_MODE_DAC_SERIAL;
4608
4609         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4610                 dpll |= (crtc->config.pixel_multiplier - 1)
4611                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4612         }
4613
4614         if (is_sdvo)
4615                 dpll |= DPLL_SDVO_HIGH_SPEED;
4616
4617         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4618                 dpll |= DPLL_SDVO_HIGH_SPEED;
4619
4620         /* compute bitmask from p1 value */
4621         if (IS_PINEVIEW(dev))
4622                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4623         else {
4624                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4625                 if (IS_G4X(dev) && reduced_clock)
4626                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4627         }
4628         switch (clock->p2) {
4629         case 5:
4630                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4631                 break;
4632         case 7:
4633                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4634                 break;
4635         case 10:
4636                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4637                 break;
4638         case 14:
4639                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4640                 break;
4641         }
4642         if (INTEL_INFO(dev)->gen >= 4)
4643                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4644
4645         if (crtc->config.sdvo_tv_clock)
4646                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4647         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4648                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4649                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4650         else
4651                 dpll |= PLL_REF_INPUT_DREFCLK;
4652
4653         dpll |= DPLL_VCO_ENABLE;
4654         crtc->config.dpll_hw_state.dpll = dpll;
4655
4656         if (INTEL_INFO(dev)->gen >= 4) {
4657                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4658                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4659                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4660         }
4661
4662         if (crtc->config.has_dp_encoder)
4663                 intel_dp_set_m_n(crtc);
4664 }
4665
4666 static void i8xx_update_pll(struct intel_crtc *crtc,
4667                             intel_clock_t *reduced_clock,
4668                             int num_connectors)
4669 {
4670         struct drm_device *dev = crtc->base.dev;
4671         struct drm_i915_private *dev_priv = dev->dev_private;
4672         u32 dpll;
4673         struct dpll *clock = &crtc->config.dpll;
4674
4675         i9xx_update_pll_dividers(crtc, reduced_clock);
4676
4677         dpll = DPLL_VGA_MODE_DIS;
4678
4679         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4680                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4681         } else {
4682                 if (clock->p1 == 2)
4683                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4684                 else
4685                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4686                 if (clock->p2 == 4)
4687                         dpll |= PLL_P2_DIVIDE_BY_4;
4688         }
4689
4690         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4691                 dpll |= DPLL_DVO_2X_MODE;
4692
4693         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4694                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4695                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4696         else
4697                 dpll |= PLL_REF_INPUT_DREFCLK;
4698
4699         dpll |= DPLL_VCO_ENABLE;
4700         crtc->config.dpll_hw_state.dpll = dpll;
4701 }
4702
4703 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4704 {
4705         struct drm_device *dev = intel_crtc->base.dev;
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707         enum pipe pipe = intel_crtc->pipe;
4708         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4709         struct drm_display_mode *adjusted_mode =
4710                 &intel_crtc->config.adjusted_mode;
4711         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4712
4713         /* We need to be careful not to changed the adjusted mode, for otherwise
4714          * the hw state checker will get angry at the mismatch. */
4715         crtc_vtotal = adjusted_mode->crtc_vtotal;
4716         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4717
4718         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4719                 /* the chip adds 2 halflines automatically */
4720                 crtc_vtotal -= 1;
4721                 crtc_vblank_end -= 1;
4722                 vsyncshift = adjusted_mode->crtc_hsync_start
4723                              - adjusted_mode->crtc_htotal / 2;
4724         } else {
4725                 vsyncshift = 0;
4726         }
4727
4728         if (INTEL_INFO(dev)->gen > 3)
4729                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4730
4731         I915_WRITE(HTOTAL(cpu_transcoder),
4732                    (adjusted_mode->crtc_hdisplay - 1) |
4733                    ((adjusted_mode->crtc_htotal - 1) << 16));
4734         I915_WRITE(HBLANK(cpu_transcoder),
4735                    (adjusted_mode->crtc_hblank_start - 1) |
4736                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4737         I915_WRITE(HSYNC(cpu_transcoder),
4738                    (adjusted_mode->crtc_hsync_start - 1) |
4739                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4740
4741         I915_WRITE(VTOTAL(cpu_transcoder),
4742                    (adjusted_mode->crtc_vdisplay - 1) |
4743                    ((crtc_vtotal - 1) << 16));
4744         I915_WRITE(VBLANK(cpu_transcoder),
4745                    (adjusted_mode->crtc_vblank_start - 1) |
4746                    ((crtc_vblank_end - 1) << 16));
4747         I915_WRITE(VSYNC(cpu_transcoder),
4748                    (adjusted_mode->crtc_vsync_start - 1) |
4749                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4750
4751         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4752          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4753          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4754          * bits. */
4755         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4756             (pipe == PIPE_B || pipe == PIPE_C))
4757                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4758
4759         /* pipesrc controls the size that is scaled from, which should
4760          * always be the user's requested size.
4761          */
4762         I915_WRITE(PIPESRC(pipe),
4763                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4764                    (intel_crtc->config.pipe_src_h - 1));
4765 }
4766
4767 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4768                                    struct intel_crtc_config *pipe_config)
4769 {
4770         struct drm_device *dev = crtc->base.dev;
4771         struct drm_i915_private *dev_priv = dev->dev_private;
4772         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4773         uint32_t tmp;
4774
4775         tmp = I915_READ(HTOTAL(cpu_transcoder));
4776         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4777         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4778         tmp = I915_READ(HBLANK(cpu_transcoder));
4779         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4780         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4781         tmp = I915_READ(HSYNC(cpu_transcoder));
4782         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4783         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4784
4785         tmp = I915_READ(VTOTAL(cpu_transcoder));
4786         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4787         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4788         tmp = I915_READ(VBLANK(cpu_transcoder));
4789         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4790         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4791         tmp = I915_READ(VSYNC(cpu_transcoder));
4792         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4793         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4794
4795         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4796                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4797                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4798                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4799         }
4800
4801         tmp = I915_READ(PIPESRC(crtc->pipe));
4802         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4803         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4804
4805         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4806         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4807 }
4808
4809 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4810                                              struct intel_crtc_config *pipe_config)
4811 {
4812         struct drm_crtc *crtc = &intel_crtc->base;
4813
4814         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4815         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4816         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4817         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4818
4819         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4820         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4821         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4822         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4823
4824         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4825
4826         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4827         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4828 }
4829
4830 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4831 {
4832         struct drm_device *dev = intel_crtc->base.dev;
4833         struct drm_i915_private *dev_priv = dev->dev_private;
4834         uint32_t pipeconf;
4835
4836         pipeconf = 0;
4837
4838         if (intel_crtc->config.double_wide)
4839                 pipeconf |= PIPECONF_DOUBLE_WIDE;
4840
4841         /* only g4x and later have fancy bpc/dither controls */
4842         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4843                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4844                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4845                         pipeconf |= PIPECONF_DITHER_EN |
4846                                     PIPECONF_DITHER_TYPE_SP;
4847
4848                 switch (intel_crtc->config.pipe_bpp) {
4849                 case 18:
4850                         pipeconf |= PIPECONF_6BPC;
4851                         break;
4852                 case 24:
4853                         pipeconf |= PIPECONF_8BPC;
4854                         break;
4855                 case 30:
4856                         pipeconf |= PIPECONF_10BPC;
4857                         break;
4858                 default:
4859                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4860                         BUG();
4861                 }
4862         }
4863
4864         if (HAS_PIPE_CXSR(dev)) {
4865                 if (intel_crtc->lowfreq_avail) {
4866                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4867                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4868                 } else {
4869                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4870                 }
4871         }
4872
4873         if (!IS_GEN2(dev) &&
4874             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4875                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4876         else
4877                 pipeconf |= PIPECONF_PROGRESSIVE;
4878
4879         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4880                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4881
4882         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4883         POSTING_READ(PIPECONF(intel_crtc->pipe));
4884 }
4885
4886 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4887                               int x, int y,
4888                               struct drm_framebuffer *fb)
4889 {
4890         struct drm_device *dev = crtc->dev;
4891         struct drm_i915_private *dev_priv = dev->dev_private;
4892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4893         int pipe = intel_crtc->pipe;
4894         int plane = intel_crtc->plane;
4895         int refclk, num_connectors = 0;
4896         intel_clock_t clock, reduced_clock;
4897         u32 dspcntr;
4898         bool ok, has_reduced_clock = false;
4899         bool is_lvds = false, is_dsi = false;
4900         struct intel_encoder *encoder;
4901         const intel_limit_t *limit;
4902         int ret;
4903
4904         for_each_encoder_on_crtc(dev, crtc, encoder) {
4905                 switch (encoder->type) {
4906                 case INTEL_OUTPUT_LVDS:
4907                         is_lvds = true;
4908                         break;
4909                 case INTEL_OUTPUT_DSI:
4910                         is_dsi = true;
4911                         break;
4912                 }
4913
4914                 num_connectors++;
4915         }
4916
4917         refclk = i9xx_get_refclk(crtc, num_connectors);
4918
4919         if (!is_dsi && !intel_crtc->config.clock_set) {
4920                 /*
4921                  * Returns a set of divisors for the desired target clock with
4922                  * the given refclk, or FALSE.  The returned values represent
4923                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4924                  * 2) / p1 / p2.
4925                  */
4926                 limit = intel_limit(crtc, refclk);
4927                 ok = dev_priv->display.find_dpll(limit, crtc,
4928                                                  intel_crtc->config.port_clock,
4929                                                  refclk, NULL, &clock);
4930                 if (!ok && !intel_crtc->config.clock_set) {
4931                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
4932                         return -EINVAL;
4933                 }
4934         }
4935
4936         if (is_lvds && dev_priv->lvds_downclock_avail) {
4937                 /*
4938                  * Ensure we match the reduced clock's P to the target clock.
4939                  * If the clocks don't match, we can't switch the display clock
4940                  * by using the FP0/FP1. In such case we will disable the LVDS
4941                  * downclock feature.
4942                 */
4943                 limit = intel_limit(crtc, refclk);
4944                 has_reduced_clock =
4945                         dev_priv->display.find_dpll(limit, crtc,
4946                                                     dev_priv->lvds_downclock,
4947                                                     refclk, &clock,
4948                                                     &reduced_clock);
4949         }
4950         /* Compat-code for transition, will disappear. */
4951         if (!intel_crtc->config.clock_set) {
4952                 intel_crtc->config.dpll.n = clock.n;
4953                 intel_crtc->config.dpll.m1 = clock.m1;
4954                 intel_crtc->config.dpll.m2 = clock.m2;
4955                 intel_crtc->config.dpll.p1 = clock.p1;
4956                 intel_crtc->config.dpll.p2 = clock.p2;
4957         }
4958
4959         if (IS_GEN2(dev)) {
4960                 i8xx_update_pll(intel_crtc,
4961                                 has_reduced_clock ? &reduced_clock : NULL,
4962                                 num_connectors);
4963         } else if (IS_VALLEYVIEW(dev)) {
4964                 if (!is_dsi)
4965                         vlv_update_pll(intel_crtc);
4966         } else {
4967                 i9xx_update_pll(intel_crtc,
4968                                 has_reduced_clock ? &reduced_clock : NULL,
4969                                 num_connectors);
4970         }
4971
4972         /* Set up the display plane register */
4973         dspcntr = DISPPLANE_GAMMA_ENABLE;
4974
4975         if (!IS_VALLEYVIEW(dev)) {
4976                 if (pipe == 0)
4977                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4978                 else
4979                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4980         }
4981
4982         intel_set_pipe_timings(intel_crtc);
4983
4984         /* pipesrc and dspsize control the size that is scaled from,
4985          * which should always be the user's requested size.
4986          */
4987         I915_WRITE(DSPSIZE(plane),
4988                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4989                    (intel_crtc->config.pipe_src_w - 1));
4990         I915_WRITE(DSPPOS(plane), 0);
4991
4992         i9xx_set_pipeconf(intel_crtc);
4993
4994         I915_WRITE(DSPCNTR(plane), dspcntr);
4995         POSTING_READ(DSPCNTR(plane));
4996
4997         ret = intel_pipe_set_base(crtc, x, y, fb);
4998
4999         return ret;
5000 }
5001
5002 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5003                                  struct intel_crtc_config *pipe_config)
5004 {
5005         struct drm_device *dev = crtc->base.dev;
5006         struct drm_i915_private *dev_priv = dev->dev_private;
5007         uint32_t tmp;
5008
5009         tmp = I915_READ(PFIT_CONTROL);
5010         if (!(tmp & PFIT_ENABLE))
5011                 return;
5012
5013         /* Check whether the pfit is attached to our pipe. */
5014         if (INTEL_INFO(dev)->gen < 4) {
5015                 if (crtc->pipe != PIPE_B)
5016                         return;
5017         } else {
5018                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5019                         return;
5020         }
5021
5022         pipe_config->gmch_pfit.control = tmp;
5023         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5024         if (INTEL_INFO(dev)->gen < 5)
5025                 pipe_config->gmch_pfit.lvds_border_bits =
5026                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5027 }
5028
5029 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5030                                  struct intel_crtc_config *pipe_config)
5031 {
5032         struct drm_device *dev = crtc->base.dev;
5033         struct drm_i915_private *dev_priv = dev->dev_private;
5034         uint32_t tmp;
5035
5036         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5037         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5038
5039         tmp = I915_READ(PIPECONF(crtc->pipe));
5040         if (!(tmp & PIPECONF_ENABLE))
5041                 return false;
5042
5043         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5044                 switch (tmp & PIPECONF_BPC_MASK) {
5045                 case PIPECONF_6BPC:
5046                         pipe_config->pipe_bpp = 18;
5047                         break;
5048                 case PIPECONF_8BPC:
5049                         pipe_config->pipe_bpp = 24;
5050                         break;
5051                 case PIPECONF_10BPC:
5052                         pipe_config->pipe_bpp = 30;
5053                         break;
5054                 default:
5055                         break;
5056                 }
5057         }
5058
5059         if (INTEL_INFO(dev)->gen < 4)
5060                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5061
5062         intel_get_pipe_timings(crtc, pipe_config);
5063
5064         i9xx_get_pfit_config(crtc, pipe_config);
5065
5066         if (INTEL_INFO(dev)->gen >= 4) {
5067                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5068                 pipe_config->pixel_multiplier =
5069                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5070                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5071                 pipe_config->dpll_hw_state.dpll_md = tmp;
5072         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5073                 tmp = I915_READ(DPLL(crtc->pipe));
5074                 pipe_config->pixel_multiplier =
5075                         ((tmp & SDVO_MULTIPLIER_MASK)
5076                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5077         } else {
5078                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5079                  * port and will be fixed up in the encoder->get_config
5080                  * function. */
5081                 pipe_config->pixel_multiplier = 1;
5082         }
5083         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5084         if (!IS_VALLEYVIEW(dev)) {
5085                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5086                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5087         } else {
5088                 /* Mask out read-only status bits. */
5089                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5090                                                      DPLL_PORTC_READY_MASK |
5091                                                      DPLL_PORTB_READY_MASK);
5092         }
5093
5094         i9xx_crtc_clock_get(crtc, pipe_config);
5095
5096         return true;
5097 }
5098
5099 static void ironlake_init_pch_refclk(struct drm_device *dev)
5100 {
5101         struct drm_i915_private *dev_priv = dev->dev_private;
5102         struct drm_mode_config *mode_config = &dev->mode_config;
5103         struct intel_encoder *encoder;
5104         u32 val, final;
5105         bool has_lvds = false;
5106         bool has_cpu_edp = false;
5107         bool has_panel = false;
5108         bool has_ck505 = false;
5109         bool can_ssc = false;
5110
5111         /* We need to take the global config into account */
5112         list_for_each_entry(encoder, &mode_config->encoder_list,
5113                             base.head) {
5114                 switch (encoder->type) {
5115                 case INTEL_OUTPUT_LVDS:
5116                         has_panel = true;
5117                         has_lvds = true;
5118                         break;
5119                 case INTEL_OUTPUT_EDP:
5120                         has_panel = true;
5121                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5122                                 has_cpu_edp = true;
5123                         break;
5124                 }
5125         }
5126
5127         if (HAS_PCH_IBX(dev)) {
5128                 has_ck505 = dev_priv->vbt.display_clock_mode;
5129                 can_ssc = has_ck505;
5130         } else {
5131                 has_ck505 = false;
5132                 can_ssc = true;
5133         }
5134
5135         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5136                       has_panel, has_lvds, has_ck505);
5137
5138         /* Ironlake: try to setup display ref clock before DPLL
5139          * enabling. This is only under driver's control after
5140          * PCH B stepping, previous chipset stepping should be
5141          * ignoring this setting.
5142          */
5143         val = I915_READ(PCH_DREF_CONTROL);
5144
5145         /* As we must carefully and slowly disable/enable each source in turn,
5146          * compute the final state we want first and check if we need to
5147          * make any changes at all.
5148          */
5149         final = val;
5150         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5151         if (has_ck505)
5152                 final |= DREF_NONSPREAD_CK505_ENABLE;
5153         else
5154                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5155
5156         final &= ~DREF_SSC_SOURCE_MASK;
5157         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5158         final &= ~DREF_SSC1_ENABLE;
5159
5160         if (has_panel) {
5161                 final |= DREF_SSC_SOURCE_ENABLE;
5162
5163                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5164                         final |= DREF_SSC1_ENABLE;
5165
5166                 if (has_cpu_edp) {
5167                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5168                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5169                         else
5170                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5171                 } else
5172                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5173         } else {
5174                 final |= DREF_SSC_SOURCE_DISABLE;
5175                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5176         }
5177
5178         if (final == val)
5179                 return;
5180
5181         /* Always enable nonspread source */
5182         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5183
5184         if (has_ck505)
5185                 val |= DREF_NONSPREAD_CK505_ENABLE;
5186         else
5187                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5188
5189         if (has_panel) {
5190                 val &= ~DREF_SSC_SOURCE_MASK;
5191                 val |= DREF_SSC_SOURCE_ENABLE;
5192
5193                 /* SSC must be turned on before enabling the CPU output  */
5194                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5195                         DRM_DEBUG_KMS("Using SSC on panel\n");
5196                         val |= DREF_SSC1_ENABLE;
5197                 } else
5198                         val &= ~DREF_SSC1_ENABLE;
5199
5200                 /* Get SSC going before enabling the outputs */
5201                 I915_WRITE(PCH_DREF_CONTROL, val);
5202                 POSTING_READ(PCH_DREF_CONTROL);
5203                 udelay(200);
5204
5205                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5206
5207                 /* Enable CPU source on CPU attached eDP */
5208                 if (has_cpu_edp) {
5209                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5210                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5211                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5212                         }
5213                         else
5214                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5215                 } else
5216                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5217
5218                 I915_WRITE(PCH_DREF_CONTROL, val);
5219                 POSTING_READ(PCH_DREF_CONTROL);
5220                 udelay(200);
5221         } else {
5222                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5223
5224                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5225
5226                 /* Turn off CPU output */
5227                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5228
5229                 I915_WRITE(PCH_DREF_CONTROL, val);
5230                 POSTING_READ(PCH_DREF_CONTROL);
5231                 udelay(200);
5232
5233                 /* Turn off the SSC source */
5234                 val &= ~DREF_SSC_SOURCE_MASK;
5235                 val |= DREF_SSC_SOURCE_DISABLE;
5236
5237                 /* Turn off SSC1 */
5238                 val &= ~DREF_SSC1_ENABLE;
5239
5240                 I915_WRITE(PCH_DREF_CONTROL, val);
5241                 POSTING_READ(PCH_DREF_CONTROL);
5242                 udelay(200);
5243         }
5244
5245         BUG_ON(val != final);
5246 }
5247
5248 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5249 {
5250         uint32_t tmp;
5251
5252         tmp = I915_READ(SOUTH_CHICKEN2);
5253         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5254         I915_WRITE(SOUTH_CHICKEN2, tmp);
5255
5256         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5257                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5258                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5259
5260         tmp = I915_READ(SOUTH_CHICKEN2);
5261         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5262         I915_WRITE(SOUTH_CHICKEN2, tmp);
5263
5264         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5265                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5266                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5267 }
5268
5269 /* WaMPhyProgramming:hsw */
5270 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5271 {
5272         uint32_t tmp;
5273
5274         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5275         tmp &= ~(0xFF << 24);
5276         tmp |= (0x12 << 24);
5277         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5278
5279         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5280         tmp |= (1 << 11);
5281         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5282
5283         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5284         tmp |= (1 << 11);
5285         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5286
5287         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5288         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5289         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5290
5291         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5292         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5293         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5294
5295         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5296         tmp &= ~(7 << 13);
5297         tmp |= (5 << 13);
5298         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5299
5300         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5301         tmp &= ~(7 << 13);
5302         tmp |= (5 << 13);
5303         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5304
5305         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5306         tmp &= ~0xFF;
5307         tmp |= 0x1C;
5308         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5309
5310         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5311         tmp &= ~0xFF;
5312         tmp |= 0x1C;
5313         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5314
5315         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5316         tmp &= ~(0xFF << 16);
5317         tmp |= (0x1C << 16);
5318         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5319
5320         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5321         tmp &= ~(0xFF << 16);
5322         tmp |= (0x1C << 16);
5323         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5324
5325         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5326         tmp |= (1 << 27);
5327         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5328
5329         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5330         tmp |= (1 << 27);
5331         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5332
5333         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5334         tmp &= ~(0xF << 28);
5335         tmp |= (4 << 28);
5336         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5337
5338         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5339         tmp &= ~(0xF << 28);
5340         tmp |= (4 << 28);
5341         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5342 }
5343
5344 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5345  * Programming" based on the parameters passed:
5346  * - Sequence to enable CLKOUT_DP
5347  * - Sequence to enable CLKOUT_DP without spread
5348  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5349  */
5350 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5351                                  bool with_fdi)
5352 {
5353         struct drm_i915_private *dev_priv = dev->dev_private;
5354         uint32_t reg, tmp;
5355
5356         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5357                 with_spread = true;
5358         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5359                  with_fdi, "LP PCH doesn't have FDI\n"))
5360                 with_fdi = false;
5361
5362         mutex_lock(&dev_priv->dpio_lock);
5363
5364         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5365         tmp &= ~SBI_SSCCTL_DISABLE;
5366         tmp |= SBI_SSCCTL_PATHALT;
5367         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5368
5369         udelay(24);
5370
5371         if (with_spread) {
5372                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5373                 tmp &= ~SBI_SSCCTL_PATHALT;
5374                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5375
5376                 if (with_fdi) {
5377                         lpt_reset_fdi_mphy(dev_priv);
5378                         lpt_program_fdi_mphy(dev_priv);
5379                 }
5380         }
5381
5382         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5383                SBI_GEN0 : SBI_DBUFF0;
5384         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5385         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5386         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5387
5388         mutex_unlock(&dev_priv->dpio_lock);
5389 }
5390
5391 /* Sequence to disable CLKOUT_DP */
5392 static void lpt_disable_clkout_dp(struct drm_device *dev)
5393 {
5394         struct drm_i915_private *dev_priv = dev->dev_private;
5395         uint32_t reg, tmp;
5396
5397         mutex_lock(&dev_priv->dpio_lock);
5398
5399         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5400                SBI_GEN0 : SBI_DBUFF0;
5401         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5402         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5403         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5404
5405         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5406         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5407                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5408                         tmp |= SBI_SSCCTL_PATHALT;
5409                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5410                         udelay(32);
5411                 }
5412                 tmp |= SBI_SSCCTL_DISABLE;
5413                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5414         }
5415
5416         mutex_unlock(&dev_priv->dpio_lock);
5417 }
5418
5419 static void lpt_init_pch_refclk(struct drm_device *dev)
5420 {
5421         struct drm_mode_config *mode_config = &dev->mode_config;
5422         struct intel_encoder *encoder;
5423         bool has_vga = false;
5424
5425         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5426                 switch (encoder->type) {
5427                 case INTEL_OUTPUT_ANALOG:
5428                         has_vga = true;
5429                         break;
5430                 }
5431         }
5432
5433         if (has_vga)
5434                 lpt_enable_clkout_dp(dev, true, true);
5435         else
5436                 lpt_disable_clkout_dp(dev);
5437 }
5438
5439 /*
5440  * Initialize reference clocks when the driver loads
5441  */
5442 void intel_init_pch_refclk(struct drm_device *dev)
5443 {
5444         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5445                 ironlake_init_pch_refclk(dev);
5446         else if (HAS_PCH_LPT(dev))
5447                 lpt_init_pch_refclk(dev);
5448 }
5449
5450 static int ironlake_get_refclk(struct drm_crtc *crtc)
5451 {
5452         struct drm_device *dev = crtc->dev;
5453         struct drm_i915_private *dev_priv = dev->dev_private;
5454         struct intel_encoder *encoder;
5455         int num_connectors = 0;
5456         bool is_lvds = false;
5457
5458         for_each_encoder_on_crtc(dev, crtc, encoder) {
5459                 switch (encoder->type) {
5460                 case INTEL_OUTPUT_LVDS:
5461                         is_lvds = true;
5462                         break;
5463                 }
5464                 num_connectors++;
5465         }
5466
5467         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5468                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5469                               dev_priv->vbt.lvds_ssc_freq);
5470                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5471         }
5472
5473         return 120000;
5474 }
5475
5476 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5477 {
5478         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480         int pipe = intel_crtc->pipe;
5481         uint32_t val;
5482
5483         val = 0;
5484
5485         switch (intel_crtc->config.pipe_bpp) {
5486         case 18:
5487                 val |= PIPECONF_6BPC;
5488                 break;
5489         case 24:
5490                 val |= PIPECONF_8BPC;
5491                 break;
5492         case 30:
5493                 val |= PIPECONF_10BPC;
5494                 break;
5495         case 36:
5496                 val |= PIPECONF_12BPC;
5497                 break;
5498         default:
5499                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5500                 BUG();
5501         }
5502
5503         if (intel_crtc->config.dither)
5504                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5505
5506         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5507                 val |= PIPECONF_INTERLACED_ILK;
5508         else
5509                 val |= PIPECONF_PROGRESSIVE;
5510
5511         if (intel_crtc->config.limited_color_range)
5512                 val |= PIPECONF_COLOR_RANGE_SELECT;
5513
5514         I915_WRITE(PIPECONF(pipe), val);
5515         POSTING_READ(PIPECONF(pipe));
5516 }
5517
5518 /*
5519  * Set up the pipe CSC unit.
5520  *
5521  * Currently only full range RGB to limited range RGB conversion
5522  * is supported, but eventually this should handle various
5523  * RGB<->YCbCr scenarios as well.
5524  */
5525 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5526 {
5527         struct drm_device *dev = crtc->dev;
5528         struct drm_i915_private *dev_priv = dev->dev_private;
5529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5530         int pipe = intel_crtc->pipe;
5531         uint16_t coeff = 0x7800; /* 1.0 */
5532
5533         /*
5534          * TODO: Check what kind of values actually come out of the pipe
5535          * with these coeff/postoff values and adjust to get the best
5536          * accuracy. Perhaps we even need to take the bpc value into
5537          * consideration.
5538          */
5539
5540         if (intel_crtc->config.limited_color_range)
5541                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5542
5543         /*
5544          * GY/GU and RY/RU should be the other way around according
5545          * to BSpec, but reality doesn't agree. Just set them up in
5546          * a way that results in the correct picture.
5547          */
5548         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5549         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5550
5551         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5552         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5553
5554         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5555         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5556
5557         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5558         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5559         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5560
5561         if (INTEL_INFO(dev)->gen > 6) {
5562                 uint16_t postoff = 0;
5563
5564                 if (intel_crtc->config.limited_color_range)
5565                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5566
5567                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5568                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5569                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5570
5571                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5572         } else {
5573                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5574
5575                 if (intel_crtc->config.limited_color_range)
5576                         mode |= CSC_BLACK_SCREEN_OFFSET;
5577
5578                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5579         }
5580 }
5581
5582 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5583 {
5584         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5586         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5587         uint32_t val;
5588
5589         val = 0;
5590
5591         if (intel_crtc->config.dither)
5592                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5593
5594         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5595                 val |= PIPECONF_INTERLACED_ILK;
5596         else
5597                 val |= PIPECONF_PROGRESSIVE;
5598
5599         I915_WRITE(PIPECONF(cpu_transcoder), val);
5600         POSTING_READ(PIPECONF(cpu_transcoder));
5601
5602         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5603         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5604 }
5605
5606 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5607                                     intel_clock_t *clock,
5608                                     bool *has_reduced_clock,
5609                                     intel_clock_t *reduced_clock)
5610 {
5611         struct drm_device *dev = crtc->dev;
5612         struct drm_i915_private *dev_priv = dev->dev_private;
5613         struct intel_encoder *intel_encoder;
5614         int refclk;
5615         const intel_limit_t *limit;
5616         bool ret, is_lvds = false;
5617
5618         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5619                 switch (intel_encoder->type) {
5620                 case INTEL_OUTPUT_LVDS:
5621                         is_lvds = true;
5622                         break;
5623                 }
5624         }
5625
5626         refclk = ironlake_get_refclk(crtc);
5627
5628         /*
5629          * Returns a set of divisors for the desired target clock with the given
5630          * refclk, or FALSE.  The returned values represent the clock equation:
5631          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5632          */
5633         limit = intel_limit(crtc, refclk);
5634         ret = dev_priv->display.find_dpll(limit, crtc,
5635                                           to_intel_crtc(crtc)->config.port_clock,
5636                                           refclk, NULL, clock);
5637         if (!ret)
5638                 return false;
5639
5640         if (is_lvds && dev_priv->lvds_downclock_avail) {
5641                 /*
5642                  * Ensure we match the reduced clock's P to the target clock.
5643                  * If the clocks don't match, we can't switch the display clock
5644                  * by using the FP0/FP1. In such case we will disable the LVDS
5645                  * downclock feature.
5646                 */
5647                 *has_reduced_clock =
5648                         dev_priv->display.find_dpll(limit, crtc,
5649                                                     dev_priv->lvds_downclock,
5650                                                     refclk, clock,
5651                                                     reduced_clock);
5652         }
5653
5654         return true;
5655 }
5656
5657 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5658 {
5659         struct drm_i915_private *dev_priv = dev->dev_private;
5660         uint32_t temp;
5661
5662         temp = I915_READ(SOUTH_CHICKEN1);
5663         if (temp & FDI_BC_BIFURCATION_SELECT)
5664                 return;
5665
5666         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5667         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5668
5669         temp |= FDI_BC_BIFURCATION_SELECT;
5670         DRM_DEBUG_KMS("enabling fdi C rx\n");
5671         I915_WRITE(SOUTH_CHICKEN1, temp);
5672         POSTING_READ(SOUTH_CHICKEN1);
5673 }
5674
5675 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5676 {
5677         struct drm_device *dev = intel_crtc->base.dev;
5678         struct drm_i915_private *dev_priv = dev->dev_private;
5679
5680         switch (intel_crtc->pipe) {
5681         case PIPE_A:
5682                 break;
5683         case PIPE_B:
5684                 if (intel_crtc->config.fdi_lanes > 2)
5685                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5686                 else
5687                         cpt_enable_fdi_bc_bifurcation(dev);
5688
5689                 break;
5690         case PIPE_C:
5691                 cpt_enable_fdi_bc_bifurcation(dev);
5692
5693                 break;
5694         default:
5695                 BUG();
5696         }
5697 }
5698
5699 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5700 {
5701         /*
5702          * Account for spread spectrum to avoid
5703          * oversubscribing the link. Max center spread
5704          * is 2.5%; use 5% for safety's sake.
5705          */
5706         u32 bps = target_clock * bpp * 21 / 20;
5707         return bps / (link_bw * 8) + 1;
5708 }
5709
5710 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5711 {
5712         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5713 }
5714
5715 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5716                                       u32 *fp,
5717                                       intel_clock_t *reduced_clock, u32 *fp2)
5718 {
5719         struct drm_crtc *crtc = &intel_crtc->base;
5720         struct drm_device *dev = crtc->dev;
5721         struct drm_i915_private *dev_priv = dev->dev_private;
5722         struct intel_encoder *intel_encoder;
5723         uint32_t dpll;
5724         int factor, num_connectors = 0;
5725         bool is_lvds = false, is_sdvo = false;
5726
5727         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5728                 switch (intel_encoder->type) {
5729                 case INTEL_OUTPUT_LVDS:
5730                         is_lvds = true;
5731                         break;
5732                 case INTEL_OUTPUT_SDVO:
5733                 case INTEL_OUTPUT_HDMI:
5734                         is_sdvo = true;
5735                         break;
5736                 }
5737
5738                 num_connectors++;
5739         }
5740
5741         /* Enable autotuning of the PLL clock (if permissible) */
5742         factor = 21;
5743         if (is_lvds) {
5744                 if ((intel_panel_use_ssc(dev_priv) &&
5745                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5746                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5747                         factor = 25;
5748         } else if (intel_crtc->config.sdvo_tv_clock)
5749                 factor = 20;
5750
5751         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5752                 *fp |= FP_CB_TUNE;
5753
5754         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5755                 *fp2 |= FP_CB_TUNE;
5756
5757         dpll = 0;
5758
5759         if (is_lvds)
5760                 dpll |= DPLLB_MODE_LVDS;
5761         else
5762                 dpll |= DPLLB_MODE_DAC_SERIAL;
5763
5764         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5765                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5766
5767         if (is_sdvo)
5768                 dpll |= DPLL_SDVO_HIGH_SPEED;
5769         if (intel_crtc->config.has_dp_encoder)
5770                 dpll |= DPLL_SDVO_HIGH_SPEED;
5771
5772         /* compute bitmask from p1 value */
5773         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5774         /* also FPA1 */
5775         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5776
5777         switch (intel_crtc->config.dpll.p2) {
5778         case 5:
5779                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5780                 break;
5781         case 7:
5782                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5783                 break;
5784         case 10:
5785                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5786                 break;
5787         case 14:
5788                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5789                 break;
5790         }
5791
5792         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5793                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5794         else
5795                 dpll |= PLL_REF_INPUT_DREFCLK;
5796
5797         return dpll | DPLL_VCO_ENABLE;
5798 }
5799
5800 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5801                                   int x, int y,
5802                                   struct drm_framebuffer *fb)
5803 {
5804         struct drm_device *dev = crtc->dev;
5805         struct drm_i915_private *dev_priv = dev->dev_private;
5806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5807         int pipe = intel_crtc->pipe;
5808         int plane = intel_crtc->plane;
5809         int num_connectors = 0;
5810         intel_clock_t clock, reduced_clock;
5811         u32 dpll = 0, fp = 0, fp2 = 0;
5812         bool ok, has_reduced_clock = false;
5813         bool is_lvds = false;
5814         struct intel_encoder *encoder;
5815         struct intel_shared_dpll *pll;
5816         int ret;
5817
5818         for_each_encoder_on_crtc(dev, crtc, encoder) {
5819                 switch (encoder->type) {
5820                 case INTEL_OUTPUT_LVDS:
5821                         is_lvds = true;
5822                         break;
5823                 }
5824
5825                 num_connectors++;
5826         }
5827
5828         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5829              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5830
5831         ok = ironlake_compute_clocks(crtc, &clock,
5832                                      &has_reduced_clock, &reduced_clock);
5833         if (!ok && !intel_crtc->config.clock_set) {
5834                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5835                 return -EINVAL;
5836         }
5837         /* Compat-code for transition, will disappear. */
5838         if (!intel_crtc->config.clock_set) {
5839                 intel_crtc->config.dpll.n = clock.n;
5840                 intel_crtc->config.dpll.m1 = clock.m1;
5841                 intel_crtc->config.dpll.m2 = clock.m2;
5842                 intel_crtc->config.dpll.p1 = clock.p1;
5843                 intel_crtc->config.dpll.p2 = clock.p2;
5844         }
5845
5846         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5847         if (intel_crtc->config.has_pch_encoder) {
5848                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5849                 if (has_reduced_clock)
5850                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5851
5852                 dpll = ironlake_compute_dpll(intel_crtc,
5853                                              &fp, &reduced_clock,
5854                                              has_reduced_clock ? &fp2 : NULL);
5855
5856                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5857                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5858                 if (has_reduced_clock)
5859                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5860                 else
5861                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5862
5863                 pll = intel_get_shared_dpll(intel_crtc);
5864                 if (pll == NULL) {
5865                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5866                                          pipe_name(pipe));
5867                         return -EINVAL;
5868                 }
5869         } else
5870                 intel_put_shared_dpll(intel_crtc);
5871
5872         if (intel_crtc->config.has_dp_encoder)
5873                 intel_dp_set_m_n(intel_crtc);
5874
5875         if (is_lvds && has_reduced_clock && i915_powersave)
5876                 intel_crtc->lowfreq_avail = true;
5877         else
5878                 intel_crtc->lowfreq_avail = false;
5879
5880         if (intel_crtc->config.has_pch_encoder) {
5881                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5882
5883         }
5884
5885         intel_set_pipe_timings(intel_crtc);
5886
5887         if (intel_crtc->config.has_pch_encoder) {
5888                 intel_cpu_transcoder_set_m_n(intel_crtc,
5889                                              &intel_crtc->config.fdi_m_n);
5890         }
5891
5892         if (IS_IVYBRIDGE(dev))
5893                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5894
5895         ironlake_set_pipeconf(crtc);
5896
5897         /* Set up the display plane register */
5898         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5899         POSTING_READ(DSPCNTR(plane));
5900
5901         ret = intel_pipe_set_base(crtc, x, y, fb);
5902
5903         return ret;
5904 }
5905
5906 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5907                                          struct intel_link_m_n *m_n)
5908 {
5909         struct drm_device *dev = crtc->base.dev;
5910         struct drm_i915_private *dev_priv = dev->dev_private;
5911         enum pipe pipe = crtc->pipe;
5912
5913         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5914         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5915         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5916                 & ~TU_SIZE_MASK;
5917         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5918         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5919                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5920 }
5921
5922 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5923                                          enum transcoder transcoder,
5924                                          struct intel_link_m_n *m_n)
5925 {
5926         struct drm_device *dev = crtc->base.dev;
5927         struct drm_i915_private *dev_priv = dev->dev_private;
5928         enum pipe pipe = crtc->pipe;
5929
5930         if (INTEL_INFO(dev)->gen >= 5) {
5931                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5932                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5933                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5934                         & ~TU_SIZE_MASK;
5935                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5936                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5937                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5938         } else {
5939                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5940                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5941                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5942                         & ~TU_SIZE_MASK;
5943                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5944                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5945                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5946         }
5947 }
5948
5949 void intel_dp_get_m_n(struct intel_crtc *crtc,
5950                       struct intel_crtc_config *pipe_config)
5951 {
5952         if (crtc->config.has_pch_encoder)
5953                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5954         else
5955                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5956                                              &pipe_config->dp_m_n);
5957 }
5958
5959 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5960                                         struct intel_crtc_config *pipe_config)
5961 {
5962         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5963                                      &pipe_config->fdi_m_n);
5964 }
5965
5966 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5967                                      struct intel_crtc_config *pipe_config)
5968 {
5969         struct drm_device *dev = crtc->base.dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971         uint32_t tmp;
5972
5973         tmp = I915_READ(PF_CTL(crtc->pipe));
5974
5975         if (tmp & PF_ENABLE) {
5976                 pipe_config->pch_pfit.enabled = true;
5977                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5978                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5979
5980                 /* We currently do not free assignements of panel fitters on
5981                  * ivb/hsw (since we don't use the higher upscaling modes which
5982                  * differentiates them) so just WARN about this case for now. */
5983                 if (IS_GEN7(dev)) {
5984                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5985                                 PF_PIPE_SEL_IVB(crtc->pipe));
5986                 }
5987         }
5988 }
5989
5990 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5991                                      struct intel_crtc_config *pipe_config)
5992 {
5993         struct drm_device *dev = crtc->base.dev;
5994         struct drm_i915_private *dev_priv = dev->dev_private;
5995         uint32_t tmp;
5996
5997         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5998         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5999
6000         tmp = I915_READ(PIPECONF(crtc->pipe));
6001         if (!(tmp & PIPECONF_ENABLE))
6002                 return false;
6003
6004         switch (tmp & PIPECONF_BPC_MASK) {
6005         case PIPECONF_6BPC:
6006                 pipe_config->pipe_bpp = 18;
6007                 break;
6008         case PIPECONF_8BPC:
6009                 pipe_config->pipe_bpp = 24;
6010                 break;
6011         case PIPECONF_10BPC:
6012                 pipe_config->pipe_bpp = 30;
6013                 break;
6014         case PIPECONF_12BPC:
6015                 pipe_config->pipe_bpp = 36;
6016                 break;
6017         default:
6018                 break;
6019         }
6020
6021         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6022                 struct intel_shared_dpll *pll;
6023
6024                 pipe_config->has_pch_encoder = true;
6025
6026                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6027                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6028                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6029
6030                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6031
6032                 if (HAS_PCH_IBX(dev_priv->dev)) {
6033                         pipe_config->shared_dpll =
6034                                 (enum intel_dpll_id) crtc->pipe;
6035                 } else {
6036                         tmp = I915_READ(PCH_DPLL_SEL);
6037                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6038                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6039                         else
6040                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6041                 }
6042
6043                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6044
6045                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6046                                            &pipe_config->dpll_hw_state));
6047
6048                 tmp = pipe_config->dpll_hw_state.dpll;
6049                 pipe_config->pixel_multiplier =
6050                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6051                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6052
6053                 ironlake_pch_clock_get(crtc, pipe_config);
6054         } else {
6055                 pipe_config->pixel_multiplier = 1;
6056         }
6057
6058         intel_get_pipe_timings(crtc, pipe_config);
6059
6060         ironlake_get_pfit_config(crtc, pipe_config);
6061
6062         return true;
6063 }
6064
6065 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6066 {
6067         struct drm_device *dev = dev_priv->dev;
6068         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6069         struct intel_crtc *crtc;
6070         unsigned long irqflags;
6071         uint32_t val;
6072
6073         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6074                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6075                      pipe_name(crtc->pipe));
6076
6077         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6078         WARN(plls->spll_refcount, "SPLL enabled\n");
6079         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6080         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6081         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6082         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6083              "CPU PWM1 enabled\n");
6084         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6085              "CPU PWM2 enabled\n");
6086         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6087              "PCH PWM1 enabled\n");
6088         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6089              "Utility pin enabled\n");
6090         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6091
6092         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6093         val = I915_READ(DEIMR);
6094         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6095              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6096         val = I915_READ(SDEIMR);
6097         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6098              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6099         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6100 }
6101
6102 /*
6103  * This function implements pieces of two sequences from BSpec:
6104  * - Sequence for display software to disable LCPLL
6105  * - Sequence for display software to allow package C8+
6106  * The steps implemented here are just the steps that actually touch the LCPLL
6107  * register. Callers should take care of disabling all the display engine
6108  * functions, doing the mode unset, fixing interrupts, etc.
6109  */
6110 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6111                        bool switch_to_fclk, bool allow_power_down)
6112 {
6113         uint32_t val;
6114
6115         assert_can_disable_lcpll(dev_priv);
6116
6117         val = I915_READ(LCPLL_CTL);
6118
6119         if (switch_to_fclk) {
6120                 val |= LCPLL_CD_SOURCE_FCLK;
6121                 I915_WRITE(LCPLL_CTL, val);
6122
6123                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6124                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6125                         DRM_ERROR("Switching to FCLK failed\n");
6126
6127                 val = I915_READ(LCPLL_CTL);
6128         }
6129
6130         val |= LCPLL_PLL_DISABLE;
6131         I915_WRITE(LCPLL_CTL, val);
6132         POSTING_READ(LCPLL_CTL);
6133
6134         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6135                 DRM_ERROR("LCPLL still locked\n");
6136
6137         val = I915_READ(D_COMP);
6138         val |= D_COMP_COMP_DISABLE;
6139         mutex_lock(&dev_priv->rps.hw_lock);
6140         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6141                 DRM_ERROR("Failed to disable D_COMP\n");
6142         mutex_unlock(&dev_priv->rps.hw_lock);
6143         POSTING_READ(D_COMP);
6144         ndelay(100);
6145
6146         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6147                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6148
6149         if (allow_power_down) {
6150                 val = I915_READ(LCPLL_CTL);
6151                 val |= LCPLL_POWER_DOWN_ALLOW;
6152                 I915_WRITE(LCPLL_CTL, val);
6153                 POSTING_READ(LCPLL_CTL);
6154         }
6155 }
6156
6157 /*
6158  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6159  * source.
6160  */
6161 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6162 {
6163         uint32_t val;
6164
6165         val = I915_READ(LCPLL_CTL);
6166
6167         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6168                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6169                 return;
6170
6171         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6172          * we'll hang the machine! */
6173         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6174
6175         if (val & LCPLL_POWER_DOWN_ALLOW) {
6176                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6177                 I915_WRITE(LCPLL_CTL, val);
6178                 POSTING_READ(LCPLL_CTL);
6179         }
6180
6181         val = I915_READ(D_COMP);
6182         val |= D_COMP_COMP_FORCE;
6183         val &= ~D_COMP_COMP_DISABLE;
6184         mutex_lock(&dev_priv->rps.hw_lock);
6185         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6186                 DRM_ERROR("Failed to enable D_COMP\n");
6187         mutex_unlock(&dev_priv->rps.hw_lock);
6188         POSTING_READ(D_COMP);
6189
6190         val = I915_READ(LCPLL_CTL);
6191         val &= ~LCPLL_PLL_DISABLE;
6192         I915_WRITE(LCPLL_CTL, val);
6193
6194         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6195                 DRM_ERROR("LCPLL not locked yet\n");
6196
6197         if (val & LCPLL_CD_SOURCE_FCLK) {
6198                 val = I915_READ(LCPLL_CTL);
6199                 val &= ~LCPLL_CD_SOURCE_FCLK;
6200                 I915_WRITE(LCPLL_CTL, val);
6201
6202                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6203                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6204                         DRM_ERROR("Switching back to LCPLL failed\n");
6205         }
6206
6207         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6208 }
6209
6210 void hsw_enable_pc8_work(struct work_struct *__work)
6211 {
6212         struct drm_i915_private *dev_priv =
6213                 container_of(to_delayed_work(__work), struct drm_i915_private,
6214                              pc8.enable_work);
6215         struct drm_device *dev = dev_priv->dev;
6216         uint32_t val;
6217
6218         if (dev_priv->pc8.enabled)
6219                 return;
6220
6221         DRM_DEBUG_KMS("Enabling package C8+\n");
6222
6223         dev_priv->pc8.enabled = true;
6224
6225         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6226                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6227                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6228                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6229         }
6230
6231         lpt_disable_clkout_dp(dev);
6232         hsw_pc8_disable_interrupts(dev);
6233         hsw_disable_lcpll(dev_priv, true, true);
6234 }
6235
6236 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6237 {
6238         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6239         WARN(dev_priv->pc8.disable_count < 1,
6240              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6241
6242         dev_priv->pc8.disable_count--;
6243         if (dev_priv->pc8.disable_count != 0)
6244                 return;
6245
6246         schedule_delayed_work(&dev_priv->pc8.enable_work,
6247                               msecs_to_jiffies(i915_pc8_timeout));
6248 }
6249
6250 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6251 {
6252         struct drm_device *dev = dev_priv->dev;
6253         uint32_t val;
6254
6255         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6256         WARN(dev_priv->pc8.disable_count < 0,
6257              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6258
6259         dev_priv->pc8.disable_count++;
6260         if (dev_priv->pc8.disable_count != 1)
6261                 return;
6262
6263         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6264         if (!dev_priv->pc8.enabled)
6265                 return;
6266
6267         DRM_DEBUG_KMS("Disabling package C8+\n");
6268
6269         hsw_restore_lcpll(dev_priv);
6270         hsw_pc8_restore_interrupts(dev);
6271         lpt_init_pch_refclk(dev);
6272
6273         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6274                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6275                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6276                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6277         }
6278
6279         intel_prepare_ddi(dev);
6280         i915_gem_init_swizzling(dev);
6281         mutex_lock(&dev_priv->rps.hw_lock);
6282         gen6_update_ring_freq(dev);
6283         mutex_unlock(&dev_priv->rps.hw_lock);
6284         dev_priv->pc8.enabled = false;
6285 }
6286
6287 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6288 {
6289         mutex_lock(&dev_priv->pc8.lock);
6290         __hsw_enable_package_c8(dev_priv);
6291         mutex_unlock(&dev_priv->pc8.lock);
6292 }
6293
6294 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6295 {
6296         mutex_lock(&dev_priv->pc8.lock);
6297         __hsw_disable_package_c8(dev_priv);
6298         mutex_unlock(&dev_priv->pc8.lock);
6299 }
6300
6301 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6302 {
6303         struct drm_device *dev = dev_priv->dev;
6304         struct intel_crtc *crtc;
6305         uint32_t val;
6306
6307         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6308                 if (crtc->base.enabled)
6309                         return false;
6310
6311         /* This case is still possible since we have the i915.disable_power_well
6312          * parameter and also the KVMr or something else might be requesting the
6313          * power well. */
6314         val = I915_READ(HSW_PWR_WELL_DRIVER);
6315         if (val != 0) {
6316                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6317                 return false;
6318         }
6319
6320         return true;
6321 }
6322
6323 /* Since we're called from modeset_global_resources there's no way to
6324  * symmetrically increase and decrease the refcount, so we use
6325  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6326  * or not.
6327  */
6328 static void hsw_update_package_c8(struct drm_device *dev)
6329 {
6330         struct drm_i915_private *dev_priv = dev->dev_private;
6331         bool allow;
6332
6333         if (!i915_enable_pc8)
6334                 return;
6335
6336         mutex_lock(&dev_priv->pc8.lock);
6337
6338         allow = hsw_can_enable_package_c8(dev_priv);
6339
6340         if (allow == dev_priv->pc8.requirements_met)
6341                 goto done;
6342
6343         dev_priv->pc8.requirements_met = allow;
6344
6345         if (allow)
6346                 __hsw_enable_package_c8(dev_priv);
6347         else
6348                 __hsw_disable_package_c8(dev_priv);
6349
6350 done:
6351         mutex_unlock(&dev_priv->pc8.lock);
6352 }
6353
6354 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6355 {
6356         if (!dev_priv->pc8.gpu_idle) {
6357                 dev_priv->pc8.gpu_idle = true;
6358                 hsw_enable_package_c8(dev_priv);
6359         }
6360 }
6361
6362 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6363 {
6364         if (dev_priv->pc8.gpu_idle) {
6365                 dev_priv->pc8.gpu_idle = false;
6366                 hsw_disable_package_c8(dev_priv);
6367         }
6368 }
6369
6370 static void haswell_modeset_global_resources(struct drm_device *dev)
6371 {
6372         bool enable = false;
6373         struct intel_crtc *crtc;
6374
6375         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6376                 if (!crtc->base.enabled)
6377                         continue;
6378
6379                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6380                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6381                         enable = true;
6382         }
6383
6384         intel_set_power_well(dev, enable);
6385
6386         hsw_update_package_c8(dev);
6387 }
6388
6389 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6390                                  int x, int y,
6391                                  struct drm_framebuffer *fb)
6392 {
6393         struct drm_device *dev = crtc->dev;
6394         struct drm_i915_private *dev_priv = dev->dev_private;
6395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396         int plane = intel_crtc->plane;
6397         int ret;
6398
6399         if (!intel_ddi_pll_mode_set(crtc))
6400                 return -EINVAL;
6401
6402         if (intel_crtc->config.has_dp_encoder)
6403                 intel_dp_set_m_n(intel_crtc);
6404
6405         intel_crtc->lowfreq_avail = false;
6406
6407         intel_set_pipe_timings(intel_crtc);
6408
6409         if (intel_crtc->config.has_pch_encoder) {
6410                 intel_cpu_transcoder_set_m_n(intel_crtc,
6411                                              &intel_crtc->config.fdi_m_n);
6412         }
6413
6414         haswell_set_pipeconf(crtc);
6415
6416         intel_set_pipe_csc(crtc);
6417
6418         /* Set up the display plane register */
6419         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6420         POSTING_READ(DSPCNTR(plane));
6421
6422         ret = intel_pipe_set_base(crtc, x, y, fb);
6423
6424         return ret;
6425 }
6426
6427 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6428                                     struct intel_crtc_config *pipe_config)
6429 {
6430         struct drm_device *dev = crtc->base.dev;
6431         struct drm_i915_private *dev_priv = dev->dev_private;
6432         enum intel_display_power_domain pfit_domain;
6433         uint32_t tmp;
6434
6435         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6436         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6437
6438         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6439         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6440                 enum pipe trans_edp_pipe;
6441                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6442                 default:
6443                         WARN(1, "unknown pipe linked to edp transcoder\n");
6444                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6445                 case TRANS_DDI_EDP_INPUT_A_ON:
6446                         trans_edp_pipe = PIPE_A;
6447                         break;
6448                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6449                         trans_edp_pipe = PIPE_B;
6450                         break;
6451                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6452                         trans_edp_pipe = PIPE_C;
6453                         break;
6454                 }
6455
6456                 if (trans_edp_pipe == crtc->pipe)
6457                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6458         }
6459
6460         if (!intel_display_power_enabled(dev,
6461                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6462                 return false;
6463
6464         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6465         if (!(tmp & PIPECONF_ENABLE))
6466                 return false;
6467
6468         /*
6469          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6470          * DDI E. So just check whether this pipe is wired to DDI E and whether
6471          * the PCH transcoder is on.
6472          */
6473         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6474         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6475             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6476                 pipe_config->has_pch_encoder = true;
6477
6478                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6479                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6480                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6481
6482                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6483         }
6484
6485         intel_get_pipe_timings(crtc, pipe_config);
6486
6487         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6488         if (intel_display_power_enabled(dev, pfit_domain))
6489                 ironlake_get_pfit_config(crtc, pipe_config);
6490
6491         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6492                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6493
6494         pipe_config->pixel_multiplier = 1;
6495
6496         return true;
6497 }
6498
6499 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6500                                int x, int y,
6501                                struct drm_framebuffer *fb)
6502 {
6503         struct drm_device *dev = crtc->dev;
6504         struct drm_i915_private *dev_priv = dev->dev_private;
6505         struct intel_encoder *encoder;
6506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6507         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6508         int pipe = intel_crtc->pipe;
6509         int ret;
6510
6511         drm_vblank_pre_modeset(dev, pipe);
6512
6513         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6514
6515         drm_vblank_post_modeset(dev, pipe);
6516
6517         if (ret != 0)
6518                 return ret;
6519
6520         for_each_encoder_on_crtc(dev, crtc, encoder) {
6521                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6522                         encoder->base.base.id,
6523                         drm_get_encoder_name(&encoder->base),
6524                         mode->base.id, mode->name);
6525                 encoder->mode_set(encoder);
6526         }
6527
6528         return 0;
6529 }
6530
6531 static bool intel_eld_uptodate(struct drm_connector *connector,
6532                                int reg_eldv, uint32_t bits_eldv,
6533                                int reg_elda, uint32_t bits_elda,
6534                                int reg_edid)
6535 {
6536         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6537         uint8_t *eld = connector->eld;
6538         uint32_t i;
6539
6540         i = I915_READ(reg_eldv);
6541         i &= bits_eldv;
6542
6543         if (!eld[0])
6544                 return !i;
6545
6546         if (!i)
6547                 return false;
6548
6549         i = I915_READ(reg_elda);
6550         i &= ~bits_elda;
6551         I915_WRITE(reg_elda, i);
6552
6553         for (i = 0; i < eld[2]; i++)
6554                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6555                         return false;
6556
6557         return true;
6558 }
6559
6560 static void g4x_write_eld(struct drm_connector *connector,
6561                           struct drm_crtc *crtc)
6562 {
6563         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6564         uint8_t *eld = connector->eld;
6565         uint32_t eldv;
6566         uint32_t len;
6567         uint32_t i;
6568
6569         i = I915_READ(G4X_AUD_VID_DID);
6570
6571         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6572                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6573         else
6574                 eldv = G4X_ELDV_DEVCTG;
6575
6576         if (intel_eld_uptodate(connector,
6577                                G4X_AUD_CNTL_ST, eldv,
6578                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6579                                G4X_HDMIW_HDMIEDID))
6580                 return;
6581
6582         i = I915_READ(G4X_AUD_CNTL_ST);
6583         i &= ~(eldv | G4X_ELD_ADDR);
6584         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6585         I915_WRITE(G4X_AUD_CNTL_ST, i);
6586
6587         if (!eld[0])
6588                 return;
6589
6590         len = min_t(uint8_t, eld[2], len);
6591         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6592         for (i = 0; i < len; i++)
6593                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6594
6595         i = I915_READ(G4X_AUD_CNTL_ST);
6596         i |= eldv;
6597         I915_WRITE(G4X_AUD_CNTL_ST, i);
6598 }
6599
6600 static void haswell_write_eld(struct drm_connector *connector,
6601                                      struct drm_crtc *crtc)
6602 {
6603         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6604         uint8_t *eld = connector->eld;
6605         struct drm_device *dev = crtc->dev;
6606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6607         uint32_t eldv;
6608         uint32_t i;
6609         int len;
6610         int pipe = to_intel_crtc(crtc)->pipe;
6611         int tmp;
6612
6613         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6614         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6615         int aud_config = HSW_AUD_CFG(pipe);
6616         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6617
6618
6619         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6620
6621         /* Audio output enable */
6622         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6623         tmp = I915_READ(aud_cntrl_st2);
6624         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6625         I915_WRITE(aud_cntrl_st2, tmp);
6626
6627         /* Wait for 1 vertical blank */
6628         intel_wait_for_vblank(dev, pipe);
6629
6630         /* Set ELD valid state */
6631         tmp = I915_READ(aud_cntrl_st2);
6632         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6633         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6634         I915_WRITE(aud_cntrl_st2, tmp);
6635         tmp = I915_READ(aud_cntrl_st2);
6636         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6637
6638         /* Enable HDMI mode */
6639         tmp = I915_READ(aud_config);
6640         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6641         /* clear N_programing_enable and N_value_index */
6642         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6643         I915_WRITE(aud_config, tmp);
6644
6645         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6646
6647         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6648         intel_crtc->eld_vld = true;
6649
6650         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6651                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6652                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6653                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6654         } else
6655                 I915_WRITE(aud_config, 0);
6656
6657         if (intel_eld_uptodate(connector,
6658                                aud_cntrl_st2, eldv,
6659                                aud_cntl_st, IBX_ELD_ADDRESS,
6660                                hdmiw_hdmiedid))
6661                 return;
6662
6663         i = I915_READ(aud_cntrl_st2);
6664         i &= ~eldv;
6665         I915_WRITE(aud_cntrl_st2, i);
6666
6667         if (!eld[0])
6668                 return;
6669
6670         i = I915_READ(aud_cntl_st);
6671         i &= ~IBX_ELD_ADDRESS;
6672         I915_WRITE(aud_cntl_st, i);
6673         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6674         DRM_DEBUG_DRIVER("port num:%d\n", i);
6675
6676         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6677         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6678         for (i = 0; i < len; i++)
6679                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6680
6681         i = I915_READ(aud_cntrl_st2);
6682         i |= eldv;
6683         I915_WRITE(aud_cntrl_st2, i);
6684
6685 }
6686
6687 static void ironlake_write_eld(struct drm_connector *connector,
6688                                      struct drm_crtc *crtc)
6689 {
6690         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6691         uint8_t *eld = connector->eld;
6692         uint32_t eldv;
6693         uint32_t i;
6694         int len;
6695         int hdmiw_hdmiedid;
6696         int aud_config;
6697         int aud_cntl_st;
6698         int aud_cntrl_st2;
6699         int pipe = to_intel_crtc(crtc)->pipe;
6700
6701         if (HAS_PCH_IBX(connector->dev)) {
6702                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6703                 aud_config = IBX_AUD_CFG(pipe);
6704                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6705                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6706         } else {
6707                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6708                 aud_config = CPT_AUD_CFG(pipe);
6709                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6710                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6711         }
6712
6713         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6714
6715         i = I915_READ(aud_cntl_st);
6716         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6717         if (!i) {
6718                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6719                 /* operate blindly on all ports */
6720                 eldv = IBX_ELD_VALIDB;
6721                 eldv |= IBX_ELD_VALIDB << 4;
6722                 eldv |= IBX_ELD_VALIDB << 8;
6723         } else {
6724                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6725                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6726         }
6727
6728         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6729                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6730                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6731                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6732         } else
6733                 I915_WRITE(aud_config, 0);
6734
6735         if (intel_eld_uptodate(connector,
6736                                aud_cntrl_st2, eldv,
6737                                aud_cntl_st, IBX_ELD_ADDRESS,
6738                                hdmiw_hdmiedid))
6739                 return;
6740
6741         i = I915_READ(aud_cntrl_st2);
6742         i &= ~eldv;
6743         I915_WRITE(aud_cntrl_st2, i);
6744
6745         if (!eld[0])
6746                 return;
6747
6748         i = I915_READ(aud_cntl_st);
6749         i &= ~IBX_ELD_ADDRESS;
6750         I915_WRITE(aud_cntl_st, i);
6751
6752         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6753         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6754         for (i = 0; i < len; i++)
6755                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6756
6757         i = I915_READ(aud_cntrl_st2);
6758         i |= eldv;
6759         I915_WRITE(aud_cntrl_st2, i);
6760 }
6761
6762 void intel_write_eld(struct drm_encoder *encoder,
6763                      struct drm_display_mode *mode)
6764 {
6765         struct drm_crtc *crtc = encoder->crtc;
6766         struct drm_connector *connector;
6767         struct drm_device *dev = encoder->dev;
6768         struct drm_i915_private *dev_priv = dev->dev_private;
6769
6770         connector = drm_select_eld(encoder, mode);
6771         if (!connector)
6772                 return;
6773
6774         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6775                          connector->base.id,
6776                          drm_get_connector_name(connector),
6777                          connector->encoder->base.id,
6778                          drm_get_encoder_name(connector->encoder));
6779
6780         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6781
6782         if (dev_priv->display.write_eld)
6783                 dev_priv->display.write_eld(connector, crtc);
6784 }
6785
6786 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6787 void intel_crtc_load_lut(struct drm_crtc *crtc)
6788 {
6789         struct drm_device *dev = crtc->dev;
6790         struct drm_i915_private *dev_priv = dev->dev_private;
6791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6792         enum pipe pipe = intel_crtc->pipe;
6793         int palreg = PALETTE(pipe);
6794         int i;
6795         bool reenable_ips = false;
6796
6797         /* The clocks have to be on to load the palette. */
6798         if (!crtc->enabled || !intel_crtc->active)
6799                 return;
6800
6801         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6802                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6803                         assert_dsi_pll_enabled(dev_priv);
6804                 else
6805                         assert_pll_enabled(dev_priv, pipe);
6806         }
6807
6808         /* use legacy palette for Ironlake */
6809         if (HAS_PCH_SPLIT(dev))
6810                 palreg = LGC_PALETTE(pipe);
6811
6812         /* Workaround : Do not read or write the pipe palette/gamma data while
6813          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6814          */
6815         if (intel_crtc->config.ips_enabled &&
6816             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6817              GAMMA_MODE_MODE_SPLIT)) {
6818                 hsw_disable_ips(intel_crtc);
6819                 reenable_ips = true;
6820         }
6821
6822         for (i = 0; i < 256; i++) {
6823                 I915_WRITE(palreg + 4 * i,
6824                            (intel_crtc->lut_r[i] << 16) |
6825                            (intel_crtc->lut_g[i] << 8) |
6826                            intel_crtc->lut_b[i]);
6827         }
6828
6829         if (reenable_ips)
6830                 hsw_enable_ips(intel_crtc);
6831 }
6832
6833 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6834 {
6835         struct drm_device *dev = crtc->dev;
6836         struct drm_i915_private *dev_priv = dev->dev_private;
6837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838         bool visible = base != 0;
6839         u32 cntl;
6840
6841         if (intel_crtc->cursor_visible == visible)
6842                 return;
6843
6844         cntl = I915_READ(_CURACNTR);
6845         if (visible) {
6846                 /* On these chipsets we can only modify the base whilst
6847                  * the cursor is disabled.
6848                  */
6849                 I915_WRITE(_CURABASE, base);
6850
6851                 cntl &= ~(CURSOR_FORMAT_MASK);
6852                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6853                 cntl |= CURSOR_ENABLE |
6854                         CURSOR_GAMMA_ENABLE |
6855                         CURSOR_FORMAT_ARGB;
6856         } else
6857                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6858         I915_WRITE(_CURACNTR, cntl);
6859
6860         intel_crtc->cursor_visible = visible;
6861 }
6862
6863 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6864 {
6865         struct drm_device *dev = crtc->dev;
6866         struct drm_i915_private *dev_priv = dev->dev_private;
6867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6868         int pipe = intel_crtc->pipe;
6869         bool visible = base != 0;
6870
6871         if (intel_crtc->cursor_visible != visible) {
6872                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6873                 if (base) {
6874                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6875                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6876                         cntl |= pipe << 28; /* Connect to correct pipe */
6877                 } else {
6878                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6879                         cntl |= CURSOR_MODE_DISABLE;
6880                 }
6881                 I915_WRITE(CURCNTR(pipe), cntl);
6882
6883                 intel_crtc->cursor_visible = visible;
6884         }
6885         /* and commit changes on next vblank */
6886         I915_WRITE(CURBASE(pipe), base);
6887 }
6888
6889 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6890 {
6891         struct drm_device *dev = crtc->dev;
6892         struct drm_i915_private *dev_priv = dev->dev_private;
6893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6894         int pipe = intel_crtc->pipe;
6895         bool visible = base != 0;
6896
6897         if (intel_crtc->cursor_visible != visible) {
6898                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6899                 if (base) {
6900                         cntl &= ~CURSOR_MODE;
6901                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6902                 } else {
6903                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6904                         cntl |= CURSOR_MODE_DISABLE;
6905                 }
6906                 if (IS_HASWELL(dev)) {
6907                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6908                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6909                 }
6910                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6911
6912                 intel_crtc->cursor_visible = visible;
6913         }
6914         /* and commit changes on next vblank */
6915         I915_WRITE(CURBASE_IVB(pipe), base);
6916 }
6917
6918 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6919 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6920                                      bool on)
6921 {
6922         struct drm_device *dev = crtc->dev;
6923         struct drm_i915_private *dev_priv = dev->dev_private;
6924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6925         int pipe = intel_crtc->pipe;
6926         int x = intel_crtc->cursor_x;
6927         int y = intel_crtc->cursor_y;
6928         u32 base = 0, pos = 0;
6929         bool visible;
6930
6931         if (on)
6932                 base = intel_crtc->cursor_addr;
6933
6934         if (x >= intel_crtc->config.pipe_src_w)
6935                 base = 0;
6936
6937         if (y >= intel_crtc->config.pipe_src_h)
6938                 base = 0;
6939
6940         if (x < 0) {
6941                 if (x + intel_crtc->cursor_width <= 0)
6942                         base = 0;
6943
6944                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6945                 x = -x;
6946         }
6947         pos |= x << CURSOR_X_SHIFT;
6948
6949         if (y < 0) {
6950                 if (y + intel_crtc->cursor_height <= 0)
6951                         base = 0;
6952
6953                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6954                 y = -y;
6955         }
6956         pos |= y << CURSOR_Y_SHIFT;
6957
6958         visible = base != 0;
6959         if (!visible && !intel_crtc->cursor_visible)
6960                 return;
6961
6962         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6963                 I915_WRITE(CURPOS_IVB(pipe), pos);
6964                 ivb_update_cursor(crtc, base);
6965         } else {
6966                 I915_WRITE(CURPOS(pipe), pos);
6967                 if (IS_845G(dev) || IS_I865G(dev))
6968                         i845_update_cursor(crtc, base);
6969                 else
6970                         i9xx_update_cursor(crtc, base);
6971         }
6972 }
6973
6974 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6975                                  struct drm_file *file,
6976                                  uint32_t handle,
6977                                  uint32_t width, uint32_t height)
6978 {
6979         struct drm_device *dev = crtc->dev;
6980         struct drm_i915_private *dev_priv = dev->dev_private;
6981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6982         struct drm_i915_gem_object *obj;
6983         uint32_t addr;
6984         int ret;
6985
6986         /* if we want to turn off the cursor ignore width and height */
6987         if (!handle) {
6988                 DRM_DEBUG_KMS("cursor off\n");
6989                 addr = 0;
6990                 obj = NULL;
6991                 mutex_lock(&dev->struct_mutex);
6992                 goto finish;
6993         }
6994
6995         /* Currently we only support 64x64 cursors */
6996         if (width != 64 || height != 64) {
6997                 DRM_ERROR("we currently only support 64x64 cursors\n");
6998                 return -EINVAL;
6999         }
7000
7001         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7002         if (&obj->base == NULL)
7003                 return -ENOENT;
7004
7005         if (obj->base.size < width * height * 4) {
7006                 DRM_ERROR("buffer is to small\n");
7007                 ret = -ENOMEM;
7008                 goto fail;
7009         }
7010
7011         /* we only need to pin inside GTT if cursor is non-phy */
7012         mutex_lock(&dev->struct_mutex);
7013         if (!dev_priv->info->cursor_needs_physical) {
7014                 unsigned alignment;
7015
7016                 if (obj->tiling_mode) {
7017                         DRM_ERROR("cursor cannot be tiled\n");
7018                         ret = -EINVAL;
7019                         goto fail_locked;
7020                 }
7021
7022                 /* Note that the w/a also requires 2 PTE of padding following
7023                  * the bo. We currently fill all unused PTE with the shadow
7024                  * page and so we should always have valid PTE following the
7025                  * cursor preventing the VT-d warning.
7026                  */
7027                 alignment = 0;
7028                 if (need_vtd_wa(dev))
7029                         alignment = 64*1024;
7030
7031                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7032                 if (ret) {
7033                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7034                         goto fail_locked;
7035                 }
7036
7037                 ret = i915_gem_object_put_fence(obj);
7038                 if (ret) {
7039                         DRM_ERROR("failed to release fence for cursor");
7040                         goto fail_unpin;
7041                 }
7042
7043                 addr = i915_gem_obj_ggtt_offset(obj);
7044         } else {
7045                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7046                 ret = i915_gem_attach_phys_object(dev, obj,
7047                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7048                                                   align);
7049                 if (ret) {
7050                         DRM_ERROR("failed to attach phys object\n");
7051                         goto fail_locked;
7052                 }
7053                 addr = obj->phys_obj->handle->busaddr;
7054         }
7055
7056         if (IS_GEN2(dev))
7057                 I915_WRITE(CURSIZE, (height << 12) | width);
7058
7059  finish:
7060         if (intel_crtc->cursor_bo) {
7061                 if (dev_priv->info->cursor_needs_physical) {
7062                         if (intel_crtc->cursor_bo != obj)
7063                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7064                 } else
7065                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7066                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7067         }
7068
7069         mutex_unlock(&dev->struct_mutex);
7070
7071         intel_crtc->cursor_addr = addr;
7072         intel_crtc->cursor_bo = obj;
7073         intel_crtc->cursor_width = width;
7074         intel_crtc->cursor_height = height;
7075
7076         if (intel_crtc->active)
7077                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7078
7079         return 0;
7080 fail_unpin:
7081         i915_gem_object_unpin_from_display_plane(obj);
7082 fail_locked:
7083         mutex_unlock(&dev->struct_mutex);
7084 fail:
7085         drm_gem_object_unreference_unlocked(&obj->base);
7086         return ret;
7087 }
7088
7089 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7090 {
7091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7092
7093         intel_crtc->cursor_x = x;
7094         intel_crtc->cursor_y = y;
7095
7096         if (intel_crtc->active)
7097                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7098
7099         return 0;
7100 }
7101
7102 /** Sets the color ramps on behalf of RandR */
7103 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7104                                  u16 blue, int regno)
7105 {
7106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7107
7108         intel_crtc->lut_r[regno] = red >> 8;
7109         intel_crtc->lut_g[regno] = green >> 8;
7110         intel_crtc->lut_b[regno] = blue >> 8;
7111 }
7112
7113 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7114                              u16 *blue, int regno)
7115 {
7116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7117
7118         *red = intel_crtc->lut_r[regno] << 8;
7119         *green = intel_crtc->lut_g[regno] << 8;
7120         *blue = intel_crtc->lut_b[regno] << 8;
7121 }
7122
7123 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7124                                  u16 *blue, uint32_t start, uint32_t size)
7125 {
7126         int end = (start + size > 256) ? 256 : start + size, i;
7127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128
7129         for (i = start; i < end; i++) {
7130                 intel_crtc->lut_r[i] = red[i] >> 8;
7131                 intel_crtc->lut_g[i] = green[i] >> 8;
7132                 intel_crtc->lut_b[i] = blue[i] >> 8;
7133         }
7134
7135         intel_crtc_load_lut(crtc);
7136 }
7137
7138 /* VESA 640x480x72Hz mode to set on the pipe */
7139 static struct drm_display_mode load_detect_mode = {
7140         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7141                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7142 };
7143
7144 static struct drm_framebuffer *
7145 intel_framebuffer_create(struct drm_device *dev,
7146                          struct drm_mode_fb_cmd2 *mode_cmd,
7147                          struct drm_i915_gem_object *obj)
7148 {
7149         struct intel_framebuffer *intel_fb;
7150         int ret;
7151
7152         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7153         if (!intel_fb) {
7154                 drm_gem_object_unreference_unlocked(&obj->base);
7155                 return ERR_PTR(-ENOMEM);
7156         }
7157
7158         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7159         if (ret) {
7160                 drm_gem_object_unreference_unlocked(&obj->base);
7161                 kfree(intel_fb);
7162                 return ERR_PTR(ret);
7163         }
7164
7165         return &intel_fb->base;
7166 }
7167
7168 static u32
7169 intel_framebuffer_pitch_for_width(int width, int bpp)
7170 {
7171         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7172         return ALIGN(pitch, 64);
7173 }
7174
7175 static u32
7176 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7177 {
7178         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7179         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7180 }
7181
7182 static struct drm_framebuffer *
7183 intel_framebuffer_create_for_mode(struct drm_device *dev,
7184                                   struct drm_display_mode *mode,
7185                                   int depth, int bpp)
7186 {
7187         struct drm_i915_gem_object *obj;
7188         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7189
7190         obj = i915_gem_alloc_object(dev,
7191                                     intel_framebuffer_size_for_mode(mode, bpp));
7192         if (obj == NULL)
7193                 return ERR_PTR(-ENOMEM);
7194
7195         mode_cmd.width = mode->hdisplay;
7196         mode_cmd.height = mode->vdisplay;
7197         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7198                                                                 bpp);
7199         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7200
7201         return intel_framebuffer_create(dev, &mode_cmd, obj);
7202 }
7203
7204 static struct drm_framebuffer *
7205 mode_fits_in_fbdev(struct drm_device *dev,
7206                    struct drm_display_mode *mode)
7207 {
7208         struct drm_i915_private *dev_priv = dev->dev_private;
7209         struct drm_i915_gem_object *obj;
7210         struct drm_framebuffer *fb;
7211
7212         if (dev_priv->fbdev == NULL)
7213                 return NULL;
7214
7215         obj = dev_priv->fbdev->ifb.obj;
7216         if (obj == NULL)
7217                 return NULL;
7218
7219         fb = &dev_priv->fbdev->ifb.base;
7220         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7221                                                                fb->bits_per_pixel))
7222                 return NULL;
7223
7224         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7225                 return NULL;
7226
7227         return fb;
7228 }
7229
7230 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7231                                 struct drm_display_mode *mode,
7232                                 struct intel_load_detect_pipe *old)
7233 {
7234         struct intel_crtc *intel_crtc;
7235         struct intel_encoder *intel_encoder =
7236                 intel_attached_encoder(connector);
7237         struct drm_crtc *possible_crtc;
7238         struct drm_encoder *encoder = &intel_encoder->base;
7239         struct drm_crtc *crtc = NULL;
7240         struct drm_device *dev = encoder->dev;
7241         struct drm_framebuffer *fb;
7242         int i = -1;
7243
7244         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7245                       connector->base.id, drm_get_connector_name(connector),
7246                       encoder->base.id, drm_get_encoder_name(encoder));
7247
7248         /*
7249          * Algorithm gets a little messy:
7250          *
7251          *   - if the connector already has an assigned crtc, use it (but make
7252          *     sure it's on first)
7253          *
7254          *   - try to find the first unused crtc that can drive this connector,
7255          *     and use that if we find one
7256          */
7257
7258         /* See if we already have a CRTC for this connector */
7259         if (encoder->crtc) {
7260                 crtc = encoder->crtc;
7261
7262                 mutex_lock(&crtc->mutex);
7263
7264                 old->dpms_mode = connector->dpms;
7265                 old->load_detect_temp = false;
7266
7267                 /* Make sure the crtc and connector are running */
7268                 if (connector->dpms != DRM_MODE_DPMS_ON)
7269                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7270
7271                 return true;
7272         }
7273
7274         /* Find an unused one (if possible) */
7275         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7276                 i++;
7277                 if (!(encoder->possible_crtcs & (1 << i)))
7278                         continue;
7279                 if (!possible_crtc->enabled) {
7280                         crtc = possible_crtc;
7281                         break;
7282                 }
7283         }
7284
7285         /*
7286          * If we didn't find an unused CRTC, don't use any.
7287          */
7288         if (!crtc) {
7289                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7290                 return false;
7291         }
7292
7293         mutex_lock(&crtc->mutex);
7294         intel_encoder->new_crtc = to_intel_crtc(crtc);
7295         to_intel_connector(connector)->new_encoder = intel_encoder;
7296
7297         intel_crtc = to_intel_crtc(crtc);
7298         old->dpms_mode = connector->dpms;
7299         old->load_detect_temp = true;
7300         old->release_fb = NULL;
7301
7302         if (!mode)
7303                 mode = &load_detect_mode;
7304
7305         /* We need a framebuffer large enough to accommodate all accesses
7306          * that the plane may generate whilst we perform load detection.
7307          * We can not rely on the fbcon either being present (we get called
7308          * during its initialisation to detect all boot displays, or it may
7309          * not even exist) or that it is large enough to satisfy the
7310          * requested mode.
7311          */
7312         fb = mode_fits_in_fbdev(dev, mode);
7313         if (fb == NULL) {
7314                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7315                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7316                 old->release_fb = fb;
7317         } else
7318                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7319         if (IS_ERR(fb)) {
7320                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7321                 mutex_unlock(&crtc->mutex);
7322                 return false;
7323         }
7324
7325         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7326                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7327                 if (old->release_fb)
7328                         old->release_fb->funcs->destroy(old->release_fb);
7329                 mutex_unlock(&crtc->mutex);
7330                 return false;
7331         }
7332
7333         /* let the connector get through one full cycle before testing */
7334         intel_wait_for_vblank(dev, intel_crtc->pipe);
7335         return true;
7336 }
7337
7338 void intel_release_load_detect_pipe(struct drm_connector *connector,
7339                                     struct intel_load_detect_pipe *old)
7340 {
7341         struct intel_encoder *intel_encoder =
7342                 intel_attached_encoder(connector);
7343         struct drm_encoder *encoder = &intel_encoder->base;
7344         struct drm_crtc *crtc = encoder->crtc;
7345
7346         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7347                       connector->base.id, drm_get_connector_name(connector),
7348                       encoder->base.id, drm_get_encoder_name(encoder));
7349
7350         if (old->load_detect_temp) {
7351                 to_intel_connector(connector)->new_encoder = NULL;
7352                 intel_encoder->new_crtc = NULL;
7353                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7354
7355                 if (old->release_fb) {
7356                         drm_framebuffer_unregister_private(old->release_fb);
7357                         drm_framebuffer_unreference(old->release_fb);
7358                 }
7359
7360                 mutex_unlock(&crtc->mutex);
7361                 return;
7362         }
7363
7364         /* Switch crtc and encoder back off if necessary */
7365         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7366                 connector->funcs->dpms(connector, old->dpms_mode);
7367
7368         mutex_unlock(&crtc->mutex);
7369 }
7370
7371 static int i9xx_pll_refclk(struct drm_device *dev,
7372                            const struct intel_crtc_config *pipe_config)
7373 {
7374         struct drm_i915_private *dev_priv = dev->dev_private;
7375         u32 dpll = pipe_config->dpll_hw_state.dpll;
7376
7377         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7378                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7379         else if (HAS_PCH_SPLIT(dev))
7380                 return 120000;
7381         else if (!IS_GEN2(dev))
7382                 return 96000;
7383         else
7384                 return 48000;
7385 }
7386
7387 /* Returns the clock of the currently programmed mode of the given pipe. */
7388 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7389                                 struct intel_crtc_config *pipe_config)
7390 {
7391         struct drm_device *dev = crtc->base.dev;
7392         struct drm_i915_private *dev_priv = dev->dev_private;
7393         int pipe = pipe_config->cpu_transcoder;
7394         u32 dpll = pipe_config->dpll_hw_state.dpll;
7395         u32 fp;
7396         intel_clock_t clock;
7397         int refclk = i9xx_pll_refclk(dev, pipe_config);
7398
7399         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7400                 fp = pipe_config->dpll_hw_state.fp0;
7401         else
7402                 fp = pipe_config->dpll_hw_state.fp1;
7403
7404         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7405         if (IS_PINEVIEW(dev)) {
7406                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7407                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7408         } else {
7409                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7410                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7411         }
7412
7413         if (!IS_GEN2(dev)) {
7414                 if (IS_PINEVIEW(dev))
7415                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7416                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7417                 else
7418                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7419                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7420
7421                 switch (dpll & DPLL_MODE_MASK) {
7422                 case DPLLB_MODE_DAC_SERIAL:
7423                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7424                                 5 : 10;
7425                         break;
7426                 case DPLLB_MODE_LVDS:
7427                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7428                                 7 : 14;
7429                         break;
7430                 default:
7431                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7432                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7433                         return;
7434                 }
7435
7436                 if (IS_PINEVIEW(dev))
7437                         pineview_clock(refclk, &clock);
7438                 else
7439                         i9xx_clock(refclk, &clock);
7440         } else {
7441                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7442
7443                 if (is_lvds) {
7444                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7445                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7446                         clock.p2 = 14;
7447                 } else {
7448                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7449                                 clock.p1 = 2;
7450                         else {
7451                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7452                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7453                         }
7454                         if (dpll & PLL_P2_DIVIDE_BY_4)
7455                                 clock.p2 = 4;
7456                         else
7457                                 clock.p2 = 2;
7458                 }
7459
7460                 i9xx_clock(refclk, &clock);
7461         }
7462
7463         /*
7464          * This value includes pixel_multiplier. We will use
7465          * port_clock to compute adjusted_mode.clock in the
7466          * encoder's get_config() function.
7467          */
7468         pipe_config->port_clock = clock.dot;
7469 }
7470
7471 int intel_dotclock_calculate(int link_freq,
7472                              const struct intel_link_m_n *m_n)
7473 {
7474         /*
7475          * The calculation for the data clock is:
7476          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7477          * But we want to avoid losing precison if possible, so:
7478          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7479          *
7480          * and the link clock is simpler:
7481          * link_clock = (m * link_clock) / n
7482          */
7483
7484         if (!m_n->link_n)
7485                 return 0;
7486
7487         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7488 }
7489
7490 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7491                                    struct intel_crtc_config *pipe_config)
7492 {
7493         struct drm_device *dev = crtc->base.dev;
7494
7495         /* read out port_clock from the DPLL */
7496         i9xx_crtc_clock_get(crtc, pipe_config);
7497
7498         /*
7499          * This value does not include pixel_multiplier.
7500          * We will check that port_clock and adjusted_mode.clock
7501          * agree once we know their relationship in the encoder's
7502          * get_config() function.
7503          */
7504         pipe_config->adjusted_mode.clock =
7505                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7506                                          &pipe_config->fdi_m_n);
7507 }
7508
7509 /** Returns the currently programmed mode of the given pipe. */
7510 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7511                                              struct drm_crtc *crtc)
7512 {
7513         struct drm_i915_private *dev_priv = dev->dev_private;
7514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7515         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7516         struct drm_display_mode *mode;
7517         struct intel_crtc_config pipe_config;
7518         int htot = I915_READ(HTOTAL(cpu_transcoder));
7519         int hsync = I915_READ(HSYNC(cpu_transcoder));
7520         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7521         int vsync = I915_READ(VSYNC(cpu_transcoder));
7522         enum pipe pipe = intel_crtc->pipe;
7523
7524         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7525         if (!mode)
7526                 return NULL;
7527
7528         /*
7529          * Construct a pipe_config sufficient for getting the clock info
7530          * back out of crtc_clock_get.
7531          *
7532          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7533          * to use a real value here instead.
7534          */
7535         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7536         pipe_config.pixel_multiplier = 1;
7537         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7538         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7539         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7540         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7541
7542         mode->clock = pipe_config.adjusted_mode.clock;
7543         mode->hdisplay = (htot & 0xffff) + 1;
7544         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7545         mode->hsync_start = (hsync & 0xffff) + 1;
7546         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7547         mode->vdisplay = (vtot & 0xffff) + 1;
7548         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7549         mode->vsync_start = (vsync & 0xffff) + 1;
7550         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7551
7552         drm_mode_set_name(mode);
7553
7554         return mode;
7555 }
7556
7557 static void intel_increase_pllclock(struct drm_crtc *crtc)
7558 {
7559         struct drm_device *dev = crtc->dev;
7560         drm_i915_private_t *dev_priv = dev->dev_private;
7561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7562         int pipe = intel_crtc->pipe;
7563         int dpll_reg = DPLL(pipe);
7564         int dpll;
7565
7566         if (HAS_PCH_SPLIT(dev))
7567                 return;
7568
7569         if (!dev_priv->lvds_downclock_avail)
7570                 return;
7571
7572         dpll = I915_READ(dpll_reg);
7573         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7574                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7575
7576                 assert_panel_unlocked(dev_priv, pipe);
7577
7578                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7579                 I915_WRITE(dpll_reg, dpll);
7580                 intel_wait_for_vblank(dev, pipe);
7581
7582                 dpll = I915_READ(dpll_reg);
7583                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7584                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7585         }
7586 }
7587
7588 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7589 {
7590         struct drm_device *dev = crtc->dev;
7591         drm_i915_private_t *dev_priv = dev->dev_private;
7592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7593
7594         if (HAS_PCH_SPLIT(dev))
7595                 return;
7596
7597         if (!dev_priv->lvds_downclock_avail)
7598                 return;
7599
7600         /*
7601          * Since this is called by a timer, we should never get here in
7602          * the manual case.
7603          */
7604         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7605                 int pipe = intel_crtc->pipe;
7606                 int dpll_reg = DPLL(pipe);
7607                 int dpll;
7608
7609                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7610
7611                 assert_panel_unlocked(dev_priv, pipe);
7612
7613                 dpll = I915_READ(dpll_reg);
7614                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7615                 I915_WRITE(dpll_reg, dpll);
7616                 intel_wait_for_vblank(dev, pipe);
7617                 dpll = I915_READ(dpll_reg);
7618                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7619                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7620         }
7621
7622 }
7623
7624 void intel_mark_busy(struct drm_device *dev)
7625 {
7626         struct drm_i915_private *dev_priv = dev->dev_private;
7627
7628         hsw_package_c8_gpu_busy(dev_priv);
7629         i915_update_gfx_val(dev_priv);
7630 }
7631
7632 void intel_mark_idle(struct drm_device *dev)
7633 {
7634         struct drm_i915_private *dev_priv = dev->dev_private;
7635         struct drm_crtc *crtc;
7636
7637         hsw_package_c8_gpu_idle(dev_priv);
7638
7639         if (!i915_powersave)
7640                 return;
7641
7642         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7643                 if (!crtc->fb)
7644                         continue;
7645
7646                 intel_decrease_pllclock(crtc);
7647         }
7648 }
7649
7650 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7651                         struct intel_ring_buffer *ring)
7652 {
7653         struct drm_device *dev = obj->base.dev;
7654         struct drm_crtc *crtc;
7655
7656         if (!i915_powersave)
7657                 return;
7658
7659         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7660                 if (!crtc->fb)
7661                         continue;
7662
7663                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7664                         continue;
7665
7666                 intel_increase_pllclock(crtc);
7667                 if (ring && intel_fbc_enabled(dev))
7668                         ring->fbc_dirty = true;
7669         }
7670 }
7671
7672 static void intel_crtc_destroy(struct drm_crtc *crtc)
7673 {
7674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7675         struct drm_device *dev = crtc->dev;
7676         struct intel_unpin_work *work;
7677         unsigned long flags;
7678
7679         spin_lock_irqsave(&dev->event_lock, flags);
7680         work = intel_crtc->unpin_work;
7681         intel_crtc->unpin_work = NULL;
7682         spin_unlock_irqrestore(&dev->event_lock, flags);
7683
7684         if (work) {
7685                 cancel_work_sync(&work->work);
7686                 kfree(work);
7687         }
7688
7689         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7690
7691         drm_crtc_cleanup(crtc);
7692
7693         kfree(intel_crtc);
7694 }
7695
7696 static void intel_unpin_work_fn(struct work_struct *__work)
7697 {
7698         struct intel_unpin_work *work =
7699                 container_of(__work, struct intel_unpin_work, work);
7700         struct drm_device *dev = work->crtc->dev;
7701
7702         mutex_lock(&dev->struct_mutex);
7703         intel_unpin_fb_obj(work->old_fb_obj);
7704         drm_gem_object_unreference(&work->pending_flip_obj->base);
7705         drm_gem_object_unreference(&work->old_fb_obj->base);
7706
7707         intel_update_fbc(dev);
7708         mutex_unlock(&dev->struct_mutex);
7709
7710         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7711         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7712
7713         kfree(work);
7714 }
7715
7716 static void do_intel_finish_page_flip(struct drm_device *dev,
7717                                       struct drm_crtc *crtc)
7718 {
7719         drm_i915_private_t *dev_priv = dev->dev_private;
7720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7721         struct intel_unpin_work *work;
7722         unsigned long flags;
7723
7724         /* Ignore early vblank irqs */
7725         if (intel_crtc == NULL)
7726                 return;
7727
7728         spin_lock_irqsave(&dev->event_lock, flags);
7729         work = intel_crtc->unpin_work;
7730
7731         /* Ensure we don't miss a work->pending update ... */
7732         smp_rmb();
7733
7734         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7735                 spin_unlock_irqrestore(&dev->event_lock, flags);
7736                 return;
7737         }
7738
7739         /* and that the unpin work is consistent wrt ->pending. */
7740         smp_rmb();
7741
7742         intel_crtc->unpin_work = NULL;
7743
7744         if (work->event)
7745                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7746
7747         drm_vblank_put(dev, intel_crtc->pipe);
7748
7749         spin_unlock_irqrestore(&dev->event_lock, flags);
7750
7751         wake_up_all(&dev_priv->pending_flip_queue);
7752
7753         queue_work(dev_priv->wq, &work->work);
7754
7755         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7756 }
7757
7758 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7759 {
7760         drm_i915_private_t *dev_priv = dev->dev_private;
7761         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7762
7763         do_intel_finish_page_flip(dev, crtc);
7764 }
7765
7766 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7767 {
7768         drm_i915_private_t *dev_priv = dev->dev_private;
7769         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7770
7771         do_intel_finish_page_flip(dev, crtc);
7772 }
7773
7774 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7775 {
7776         drm_i915_private_t *dev_priv = dev->dev_private;
7777         struct intel_crtc *intel_crtc =
7778                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7779         unsigned long flags;
7780
7781         /* NB: An MMIO update of the plane base pointer will also
7782          * generate a page-flip completion irq, i.e. every modeset
7783          * is also accompanied by a spurious intel_prepare_page_flip().
7784          */
7785         spin_lock_irqsave(&dev->event_lock, flags);
7786         if (intel_crtc->unpin_work)
7787                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7788         spin_unlock_irqrestore(&dev->event_lock, flags);
7789 }
7790
7791 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7792 {
7793         /* Ensure that the work item is consistent when activating it ... */
7794         smp_wmb();
7795         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7796         /* and that it is marked active as soon as the irq could fire. */
7797         smp_wmb();
7798 }
7799
7800 static int intel_gen2_queue_flip(struct drm_device *dev,
7801                                  struct drm_crtc *crtc,
7802                                  struct drm_framebuffer *fb,
7803                                  struct drm_i915_gem_object *obj,
7804                                  uint32_t flags)
7805 {
7806         struct drm_i915_private *dev_priv = dev->dev_private;
7807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7808         u32 flip_mask;
7809         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7810         int ret;
7811
7812         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7813         if (ret)
7814                 goto err;
7815
7816         ret = intel_ring_begin(ring, 6);
7817         if (ret)
7818                 goto err_unpin;
7819
7820         /* Can't queue multiple flips, so wait for the previous
7821          * one to finish before executing the next.
7822          */
7823         if (intel_crtc->plane)
7824                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7825         else
7826                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7827         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7828         intel_ring_emit(ring, MI_NOOP);
7829         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7830                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7831         intel_ring_emit(ring, fb->pitches[0]);
7832         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7833         intel_ring_emit(ring, 0); /* aux display base address, unused */
7834
7835         intel_mark_page_flip_active(intel_crtc);
7836         __intel_ring_advance(ring);
7837         return 0;
7838
7839 err_unpin:
7840         intel_unpin_fb_obj(obj);
7841 err:
7842         return ret;
7843 }
7844
7845 static int intel_gen3_queue_flip(struct drm_device *dev,
7846                                  struct drm_crtc *crtc,
7847                                  struct drm_framebuffer *fb,
7848                                  struct drm_i915_gem_object *obj,
7849                                  uint32_t flags)
7850 {
7851         struct drm_i915_private *dev_priv = dev->dev_private;
7852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7853         u32 flip_mask;
7854         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7855         int ret;
7856
7857         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7858         if (ret)
7859                 goto err;
7860
7861         ret = intel_ring_begin(ring, 6);
7862         if (ret)
7863                 goto err_unpin;
7864
7865         if (intel_crtc->plane)
7866                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7867         else
7868                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7869         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7870         intel_ring_emit(ring, MI_NOOP);
7871         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7872                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7873         intel_ring_emit(ring, fb->pitches[0]);
7874         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7875         intel_ring_emit(ring, MI_NOOP);
7876
7877         intel_mark_page_flip_active(intel_crtc);
7878         __intel_ring_advance(ring);
7879         return 0;
7880
7881 err_unpin:
7882         intel_unpin_fb_obj(obj);
7883 err:
7884         return ret;
7885 }
7886
7887 static int intel_gen4_queue_flip(struct drm_device *dev,
7888                                  struct drm_crtc *crtc,
7889                                  struct drm_framebuffer *fb,
7890                                  struct drm_i915_gem_object *obj,
7891                                  uint32_t flags)
7892 {
7893         struct drm_i915_private *dev_priv = dev->dev_private;
7894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7895         uint32_t pf, pipesrc;
7896         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7897         int ret;
7898
7899         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7900         if (ret)
7901                 goto err;
7902
7903         ret = intel_ring_begin(ring, 4);
7904         if (ret)
7905                 goto err_unpin;
7906
7907         /* i965+ uses the linear or tiled offsets from the
7908          * Display Registers (which do not change across a page-flip)
7909          * so we need only reprogram the base address.
7910          */
7911         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7912                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7913         intel_ring_emit(ring, fb->pitches[0]);
7914         intel_ring_emit(ring,
7915                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7916                         obj->tiling_mode);
7917
7918         /* XXX Enabling the panel-fitter across page-flip is so far
7919          * untested on non-native modes, so ignore it for now.
7920          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7921          */
7922         pf = 0;
7923         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7924         intel_ring_emit(ring, pf | pipesrc);
7925
7926         intel_mark_page_flip_active(intel_crtc);
7927         __intel_ring_advance(ring);
7928         return 0;
7929
7930 err_unpin:
7931         intel_unpin_fb_obj(obj);
7932 err:
7933         return ret;
7934 }
7935
7936 static int intel_gen6_queue_flip(struct drm_device *dev,
7937                                  struct drm_crtc *crtc,
7938                                  struct drm_framebuffer *fb,
7939                                  struct drm_i915_gem_object *obj,
7940                                  uint32_t flags)
7941 {
7942         struct drm_i915_private *dev_priv = dev->dev_private;
7943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7944         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7945         uint32_t pf, pipesrc;
7946         int ret;
7947
7948         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7949         if (ret)
7950                 goto err;
7951
7952         ret = intel_ring_begin(ring, 4);
7953         if (ret)
7954                 goto err_unpin;
7955
7956         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7957                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7958         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7959         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7960
7961         /* Contrary to the suggestions in the documentation,
7962          * "Enable Panel Fitter" does not seem to be required when page
7963          * flipping with a non-native mode, and worse causes a normal
7964          * modeset to fail.
7965          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7966          */
7967         pf = 0;
7968         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7969         intel_ring_emit(ring, pf | pipesrc);
7970
7971         intel_mark_page_flip_active(intel_crtc);
7972         __intel_ring_advance(ring);
7973         return 0;
7974
7975 err_unpin:
7976         intel_unpin_fb_obj(obj);
7977 err:
7978         return ret;
7979 }
7980
7981 static int intel_gen7_queue_flip(struct drm_device *dev,
7982                                  struct drm_crtc *crtc,
7983                                  struct drm_framebuffer *fb,
7984                                  struct drm_i915_gem_object *obj,
7985                                  uint32_t flags)
7986 {
7987         struct drm_i915_private *dev_priv = dev->dev_private;
7988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7989         struct intel_ring_buffer *ring;
7990         uint32_t plane_bit = 0;
7991         int len, ret;
7992
7993         ring = obj->ring;
7994         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
7995                 ring = &dev_priv->ring[BCS];
7996
7997         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7998         if (ret)
7999                 goto err;
8000
8001         switch(intel_crtc->plane) {
8002         case PLANE_A:
8003                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8004                 break;
8005         case PLANE_B:
8006                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8007                 break;
8008         case PLANE_C:
8009                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8010                 break;
8011         default:
8012                 WARN_ONCE(1, "unknown plane in flip command\n");
8013                 ret = -ENODEV;
8014                 goto err_unpin;
8015         }
8016
8017         len = 4;
8018         if (ring->id == RCS)
8019                 len += 6;
8020
8021         ret = intel_ring_begin(ring, len);
8022         if (ret)
8023                 goto err_unpin;
8024
8025         /* Unmask the flip-done completion message. Note that the bspec says that
8026          * we should do this for both the BCS and RCS, and that we must not unmask
8027          * more than one flip event at any time (or ensure that one flip message
8028          * can be sent by waiting for flip-done prior to queueing new flips).
8029          * Experimentation says that BCS works despite DERRMR masking all
8030          * flip-done completion events and that unmasking all planes at once
8031          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8032          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8033          */
8034         if (ring->id == RCS) {
8035                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8036                 intel_ring_emit(ring, DERRMR);
8037                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8038                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8039                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8040                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8041                 intel_ring_emit(ring, DERRMR);
8042                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8043         }
8044
8045         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8046         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8047         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8048         intel_ring_emit(ring, (MI_NOOP));
8049
8050         intel_mark_page_flip_active(intel_crtc);
8051         __intel_ring_advance(ring);
8052         return 0;
8053
8054 err_unpin:
8055         intel_unpin_fb_obj(obj);
8056 err:
8057         return ret;
8058 }
8059
8060 static int intel_default_queue_flip(struct drm_device *dev,
8061                                     struct drm_crtc *crtc,
8062                                     struct drm_framebuffer *fb,
8063                                     struct drm_i915_gem_object *obj,
8064                                     uint32_t flags)
8065 {
8066         return -ENODEV;
8067 }
8068
8069 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8070                                 struct drm_framebuffer *fb,
8071                                 struct drm_pending_vblank_event *event,
8072                                 uint32_t page_flip_flags)
8073 {
8074         struct drm_device *dev = crtc->dev;
8075         struct drm_i915_private *dev_priv = dev->dev_private;
8076         struct drm_framebuffer *old_fb = crtc->fb;
8077         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8079         struct intel_unpin_work *work;
8080         unsigned long flags;
8081         int ret;
8082
8083         /* Can't change pixel format via MI display flips. */
8084         if (fb->pixel_format != crtc->fb->pixel_format)
8085                 return -EINVAL;
8086
8087         /*
8088          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8089          * Note that pitch changes could also affect these register.
8090          */
8091         if (INTEL_INFO(dev)->gen > 3 &&
8092             (fb->offsets[0] != crtc->fb->offsets[0] ||
8093              fb->pitches[0] != crtc->fb->pitches[0]))
8094                 return -EINVAL;
8095
8096         work = kzalloc(sizeof *work, GFP_KERNEL);
8097         if (work == NULL)
8098                 return -ENOMEM;
8099
8100         work->event = event;
8101         work->crtc = crtc;
8102         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8103         INIT_WORK(&work->work, intel_unpin_work_fn);
8104
8105         ret = drm_vblank_get(dev, intel_crtc->pipe);
8106         if (ret)
8107                 goto free_work;
8108
8109         /* We borrow the event spin lock for protecting unpin_work */
8110         spin_lock_irqsave(&dev->event_lock, flags);
8111         if (intel_crtc->unpin_work) {
8112                 spin_unlock_irqrestore(&dev->event_lock, flags);
8113                 kfree(work);
8114                 drm_vblank_put(dev, intel_crtc->pipe);
8115
8116                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8117                 return -EBUSY;
8118         }
8119         intel_crtc->unpin_work = work;
8120         spin_unlock_irqrestore(&dev->event_lock, flags);
8121
8122         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8123                 flush_workqueue(dev_priv->wq);
8124
8125         ret = i915_mutex_lock_interruptible(dev);
8126         if (ret)
8127                 goto cleanup;
8128
8129         /* Reference the objects for the scheduled work. */
8130         drm_gem_object_reference(&work->old_fb_obj->base);
8131         drm_gem_object_reference(&obj->base);
8132
8133         crtc->fb = fb;
8134
8135         work->pending_flip_obj = obj;
8136
8137         work->enable_stall_check = true;
8138
8139         atomic_inc(&intel_crtc->unpin_work_count);
8140         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8141
8142         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8143         if (ret)
8144                 goto cleanup_pending;
8145
8146         intel_disable_fbc(dev);
8147         intel_mark_fb_busy(obj, NULL);
8148         mutex_unlock(&dev->struct_mutex);
8149
8150         trace_i915_flip_request(intel_crtc->plane, obj);
8151
8152         return 0;
8153
8154 cleanup_pending:
8155         atomic_dec(&intel_crtc->unpin_work_count);
8156         crtc->fb = old_fb;
8157         drm_gem_object_unreference(&work->old_fb_obj->base);
8158         drm_gem_object_unreference(&obj->base);
8159         mutex_unlock(&dev->struct_mutex);
8160
8161 cleanup:
8162         spin_lock_irqsave(&dev->event_lock, flags);
8163         intel_crtc->unpin_work = NULL;
8164         spin_unlock_irqrestore(&dev->event_lock, flags);
8165
8166         drm_vblank_put(dev, intel_crtc->pipe);
8167 free_work:
8168         kfree(work);
8169
8170         return ret;
8171 }
8172
8173 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8174         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8175         .load_lut = intel_crtc_load_lut,
8176 };
8177
8178 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8179                                   struct drm_crtc *crtc)
8180 {
8181         struct drm_device *dev;
8182         struct drm_crtc *tmp;
8183         int crtc_mask = 1;
8184
8185         WARN(!crtc, "checking null crtc?\n");
8186
8187         dev = crtc->dev;
8188
8189         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8190                 if (tmp == crtc)
8191                         break;
8192                 crtc_mask <<= 1;
8193         }
8194
8195         if (encoder->possible_crtcs & crtc_mask)
8196                 return true;
8197         return false;
8198 }
8199
8200 /**
8201  * intel_modeset_update_staged_output_state
8202  *
8203  * Updates the staged output configuration state, e.g. after we've read out the
8204  * current hw state.
8205  */
8206 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8207 {
8208         struct intel_encoder *encoder;
8209         struct intel_connector *connector;
8210
8211         list_for_each_entry(connector, &dev->mode_config.connector_list,
8212                             base.head) {
8213                 connector->new_encoder =
8214                         to_intel_encoder(connector->base.encoder);
8215         }
8216
8217         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8218                             base.head) {
8219                 encoder->new_crtc =
8220                         to_intel_crtc(encoder->base.crtc);
8221         }
8222 }
8223
8224 /**
8225  * intel_modeset_commit_output_state
8226  *
8227  * This function copies the stage display pipe configuration to the real one.
8228  */
8229 static void intel_modeset_commit_output_state(struct drm_device *dev)
8230 {
8231         struct intel_encoder *encoder;
8232         struct intel_connector *connector;
8233
8234         list_for_each_entry(connector, &dev->mode_config.connector_list,
8235                             base.head) {
8236                 connector->base.encoder = &connector->new_encoder->base;
8237         }
8238
8239         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8240                             base.head) {
8241                 encoder->base.crtc = &encoder->new_crtc->base;
8242         }
8243 }
8244
8245 static void
8246 connected_sink_compute_bpp(struct intel_connector * connector,
8247                            struct intel_crtc_config *pipe_config)
8248 {
8249         int bpp = pipe_config->pipe_bpp;
8250
8251         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8252                 connector->base.base.id,
8253                 drm_get_connector_name(&connector->base));
8254
8255         /* Don't use an invalid EDID bpc value */
8256         if (connector->base.display_info.bpc &&
8257             connector->base.display_info.bpc * 3 < bpp) {
8258                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8259                               bpp, connector->base.display_info.bpc*3);
8260                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8261         }
8262
8263         /* Clamp bpp to 8 on screens without EDID 1.4 */
8264         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8265                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8266                               bpp);
8267                 pipe_config->pipe_bpp = 24;
8268         }
8269 }
8270
8271 static int
8272 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8273                           struct drm_framebuffer *fb,
8274                           struct intel_crtc_config *pipe_config)
8275 {
8276         struct drm_device *dev = crtc->base.dev;
8277         struct intel_connector *connector;
8278         int bpp;
8279
8280         switch (fb->pixel_format) {
8281         case DRM_FORMAT_C8:
8282                 bpp = 8*3; /* since we go through a colormap */
8283                 break;
8284         case DRM_FORMAT_XRGB1555:
8285         case DRM_FORMAT_ARGB1555:
8286                 /* checked in intel_framebuffer_init already */
8287                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8288                         return -EINVAL;
8289         case DRM_FORMAT_RGB565:
8290                 bpp = 6*3; /* min is 18bpp */
8291                 break;
8292         case DRM_FORMAT_XBGR8888:
8293         case DRM_FORMAT_ABGR8888:
8294                 /* checked in intel_framebuffer_init already */
8295                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8296                         return -EINVAL;
8297         case DRM_FORMAT_XRGB8888:
8298         case DRM_FORMAT_ARGB8888:
8299                 bpp = 8*3;
8300                 break;
8301         case DRM_FORMAT_XRGB2101010:
8302         case DRM_FORMAT_ARGB2101010:
8303         case DRM_FORMAT_XBGR2101010:
8304         case DRM_FORMAT_ABGR2101010:
8305                 /* checked in intel_framebuffer_init already */
8306                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8307                         return -EINVAL;
8308                 bpp = 10*3;
8309                 break;
8310         /* TODO: gen4+ supports 16 bpc floating point, too. */
8311         default:
8312                 DRM_DEBUG_KMS("unsupported depth\n");
8313                 return -EINVAL;
8314         }
8315
8316         pipe_config->pipe_bpp = bpp;
8317
8318         /* Clamp display bpp to EDID value */
8319         list_for_each_entry(connector, &dev->mode_config.connector_list,
8320                             base.head) {
8321                 if (!connector->new_encoder ||
8322                     connector->new_encoder->new_crtc != crtc)
8323                         continue;
8324
8325                 connected_sink_compute_bpp(connector, pipe_config);
8326         }
8327
8328         return bpp;
8329 }
8330
8331 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8332 {
8333         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8334                         "type: 0x%x flags: 0x%x\n",
8335                 mode->clock,
8336                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8337                 mode->crtc_hsync_end, mode->crtc_htotal,
8338                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8339                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8340 }
8341
8342 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8343                                    struct intel_crtc_config *pipe_config,
8344                                    const char *context)
8345 {
8346         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8347                       context, pipe_name(crtc->pipe));
8348
8349         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8350         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8351                       pipe_config->pipe_bpp, pipe_config->dither);
8352         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8353                       pipe_config->has_pch_encoder,
8354                       pipe_config->fdi_lanes,
8355                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8356                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8357                       pipe_config->fdi_m_n.tu);
8358         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8359                       pipe_config->has_dp_encoder,
8360                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8361                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8362                       pipe_config->dp_m_n.tu);
8363         DRM_DEBUG_KMS("requested mode:\n");
8364         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8365         DRM_DEBUG_KMS("adjusted mode:\n");
8366         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8367         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8368         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8369         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8370                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8371         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8372                       pipe_config->gmch_pfit.control,
8373                       pipe_config->gmch_pfit.pgm_ratios,
8374                       pipe_config->gmch_pfit.lvds_border_bits);
8375         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8376                       pipe_config->pch_pfit.pos,
8377                       pipe_config->pch_pfit.size,
8378                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8379         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8380         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8381 }
8382
8383 static bool check_encoder_cloning(struct drm_crtc *crtc)
8384 {
8385         int num_encoders = 0;
8386         bool uncloneable_encoders = false;
8387         struct intel_encoder *encoder;
8388
8389         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8390                             base.head) {
8391                 if (&encoder->new_crtc->base != crtc)
8392                         continue;
8393
8394                 num_encoders++;
8395                 if (!encoder->cloneable)
8396                         uncloneable_encoders = true;
8397         }
8398
8399         return !(num_encoders > 1 && uncloneable_encoders);
8400 }
8401
8402 static struct intel_crtc_config *
8403 intel_modeset_pipe_config(struct drm_crtc *crtc,
8404                           struct drm_framebuffer *fb,
8405                           struct drm_display_mode *mode)
8406 {
8407         struct drm_device *dev = crtc->dev;
8408         struct intel_encoder *encoder;
8409         struct intel_crtc_config *pipe_config;
8410         int plane_bpp, ret = -EINVAL;
8411         bool retry = true;
8412
8413         if (!check_encoder_cloning(crtc)) {
8414                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8415                 return ERR_PTR(-EINVAL);
8416         }
8417
8418         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8419         if (!pipe_config)
8420                 return ERR_PTR(-ENOMEM);
8421
8422         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8423         drm_mode_copy(&pipe_config->requested_mode, mode);
8424
8425         pipe_config->pipe_src_w = mode->hdisplay;
8426         pipe_config->pipe_src_h = mode->vdisplay;
8427
8428         pipe_config->cpu_transcoder =
8429                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8430         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8431
8432         /*
8433          * Sanitize sync polarity flags based on requested ones. If neither
8434          * positive or negative polarity is requested, treat this as meaning
8435          * negative polarity.
8436          */
8437         if (!(pipe_config->adjusted_mode.flags &
8438               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8439                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8440
8441         if (!(pipe_config->adjusted_mode.flags &
8442               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8443                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8444
8445         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8446          * plane pixel format and any sink constraints into account. Returns the
8447          * source plane bpp so that dithering can be selected on mismatches
8448          * after encoders and crtc also have had their say. */
8449         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8450                                               fb, pipe_config);
8451         if (plane_bpp < 0)
8452                 goto fail;
8453
8454 encoder_retry:
8455         /* Ensure the port clock defaults are reset when retrying. */
8456         pipe_config->port_clock = 0;
8457         pipe_config->pixel_multiplier = 1;
8458
8459         /* Fill in default crtc timings, allow encoders to overwrite them. */
8460         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8461
8462         /* Pass our mode to the connectors and the CRTC to give them a chance to
8463          * adjust it according to limitations or connector properties, and also
8464          * a chance to reject the mode entirely.
8465          */
8466         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8467                             base.head) {
8468
8469                 if (&encoder->new_crtc->base != crtc)
8470                         continue;
8471
8472                 if (!(encoder->compute_config(encoder, pipe_config))) {
8473                         DRM_DEBUG_KMS("Encoder config failure\n");
8474                         goto fail;
8475                 }
8476         }
8477
8478         /* Set default port clock if not overwritten by the encoder. Needs to be
8479          * done afterwards in case the encoder adjusts the mode. */
8480         if (!pipe_config->port_clock)
8481                 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8482                         pipe_config->pixel_multiplier;
8483
8484         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8485         if (ret < 0) {
8486                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8487                 goto fail;
8488         }
8489
8490         if (ret == RETRY) {
8491                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8492                         ret = -EINVAL;
8493                         goto fail;
8494                 }
8495
8496                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8497                 retry = false;
8498                 goto encoder_retry;
8499         }
8500
8501         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8502         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8503                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8504
8505         return pipe_config;
8506 fail:
8507         kfree(pipe_config);
8508         return ERR_PTR(ret);
8509 }
8510
8511 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8512  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8513 static void
8514 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8515                              unsigned *prepare_pipes, unsigned *disable_pipes)
8516 {
8517         struct intel_crtc *intel_crtc;
8518         struct drm_device *dev = crtc->dev;
8519         struct intel_encoder *encoder;
8520         struct intel_connector *connector;
8521         struct drm_crtc *tmp_crtc;
8522
8523         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8524
8525         /* Check which crtcs have changed outputs connected to them, these need
8526          * to be part of the prepare_pipes mask. We don't (yet) support global
8527          * modeset across multiple crtcs, so modeset_pipes will only have one
8528          * bit set at most. */
8529         list_for_each_entry(connector, &dev->mode_config.connector_list,
8530                             base.head) {
8531                 if (connector->base.encoder == &connector->new_encoder->base)
8532                         continue;
8533
8534                 if (connector->base.encoder) {
8535                         tmp_crtc = connector->base.encoder->crtc;
8536
8537                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8538                 }
8539
8540                 if (connector->new_encoder)
8541                         *prepare_pipes |=
8542                                 1 << connector->new_encoder->new_crtc->pipe;
8543         }
8544
8545         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8546                             base.head) {
8547                 if (encoder->base.crtc == &encoder->new_crtc->base)
8548                         continue;
8549
8550                 if (encoder->base.crtc) {
8551                         tmp_crtc = encoder->base.crtc;
8552
8553                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8554                 }
8555
8556                 if (encoder->new_crtc)
8557                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8558         }
8559
8560         /* Check for any pipes that will be fully disabled ... */
8561         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8562                             base.head) {
8563                 bool used = false;
8564
8565                 /* Don't try to disable disabled crtcs. */
8566                 if (!intel_crtc->base.enabled)
8567                         continue;
8568
8569                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8570                                     base.head) {
8571                         if (encoder->new_crtc == intel_crtc)
8572                                 used = true;
8573                 }
8574
8575                 if (!used)
8576                         *disable_pipes |= 1 << intel_crtc->pipe;
8577         }
8578
8579
8580         /* set_mode is also used to update properties on life display pipes. */
8581         intel_crtc = to_intel_crtc(crtc);
8582         if (crtc->enabled)
8583                 *prepare_pipes |= 1 << intel_crtc->pipe;
8584
8585         /*
8586          * For simplicity do a full modeset on any pipe where the output routing
8587          * changed. We could be more clever, but that would require us to be
8588          * more careful with calling the relevant encoder->mode_set functions.
8589          */
8590         if (*prepare_pipes)
8591                 *modeset_pipes = *prepare_pipes;
8592
8593         /* ... and mask these out. */
8594         *modeset_pipes &= ~(*disable_pipes);
8595         *prepare_pipes &= ~(*disable_pipes);
8596
8597         /*
8598          * HACK: We don't (yet) fully support global modesets. intel_set_config
8599          * obies this rule, but the modeset restore mode of
8600          * intel_modeset_setup_hw_state does not.
8601          */
8602         *modeset_pipes &= 1 << intel_crtc->pipe;
8603         *prepare_pipes &= 1 << intel_crtc->pipe;
8604
8605         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8606                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8607 }
8608
8609 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8610 {
8611         struct drm_encoder *encoder;
8612         struct drm_device *dev = crtc->dev;
8613
8614         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8615                 if (encoder->crtc == crtc)
8616                         return true;
8617
8618         return false;
8619 }
8620
8621 static void
8622 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8623 {
8624         struct intel_encoder *intel_encoder;
8625         struct intel_crtc *intel_crtc;
8626         struct drm_connector *connector;
8627
8628         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8629                             base.head) {
8630                 if (!intel_encoder->base.crtc)
8631                         continue;
8632
8633                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8634
8635                 if (prepare_pipes & (1 << intel_crtc->pipe))
8636                         intel_encoder->connectors_active = false;
8637         }
8638
8639         intel_modeset_commit_output_state(dev);
8640
8641         /* Update computed state. */
8642         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8643                             base.head) {
8644                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8645         }
8646
8647         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8648                 if (!connector->encoder || !connector->encoder->crtc)
8649                         continue;
8650
8651                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8652
8653                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8654                         struct drm_property *dpms_property =
8655                                 dev->mode_config.dpms_property;
8656
8657                         connector->dpms = DRM_MODE_DPMS_ON;
8658                         drm_object_property_set_value(&connector->base,
8659                                                          dpms_property,
8660                                                          DRM_MODE_DPMS_ON);
8661
8662                         intel_encoder = to_intel_encoder(connector->encoder);
8663                         intel_encoder->connectors_active = true;
8664                 }
8665         }
8666
8667 }
8668
8669 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8670 {
8671         int diff;
8672
8673         if (clock1 == clock2)
8674                 return true;
8675
8676         if (!clock1 || !clock2)
8677                 return false;
8678
8679         diff = abs(clock1 - clock2);
8680
8681         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8682                 return true;
8683
8684         return false;
8685 }
8686
8687 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8688         list_for_each_entry((intel_crtc), \
8689                             &(dev)->mode_config.crtc_list, \
8690                             base.head) \
8691                 if (mask & (1 <<(intel_crtc)->pipe))
8692
8693 static bool
8694 intel_pipe_config_compare(struct drm_device *dev,
8695                           struct intel_crtc_config *current_config,
8696                           struct intel_crtc_config *pipe_config)
8697 {
8698 #define PIPE_CONF_CHECK_X(name) \
8699         if (current_config->name != pipe_config->name) { \
8700                 DRM_ERROR("mismatch in " #name " " \
8701                           "(expected 0x%08x, found 0x%08x)\n", \
8702                           current_config->name, \
8703                           pipe_config->name); \
8704                 return false; \
8705         }
8706
8707 #define PIPE_CONF_CHECK_I(name) \
8708         if (current_config->name != pipe_config->name) { \
8709                 DRM_ERROR("mismatch in " #name " " \
8710                           "(expected %i, found %i)\n", \
8711                           current_config->name, \
8712                           pipe_config->name); \
8713                 return false; \
8714         }
8715
8716 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8717         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8718                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8719                           "(expected %i, found %i)\n", \
8720                           current_config->name & (mask), \
8721                           pipe_config->name & (mask)); \
8722                 return false; \
8723         }
8724
8725 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8726         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8727                 DRM_ERROR("mismatch in " #name " " \
8728                           "(expected %i, found %i)\n", \
8729                           current_config->name, \
8730                           pipe_config->name); \
8731                 return false; \
8732         }
8733
8734 #define PIPE_CONF_QUIRK(quirk)  \
8735         ((current_config->quirks | pipe_config->quirks) & (quirk))
8736
8737         PIPE_CONF_CHECK_I(cpu_transcoder);
8738
8739         PIPE_CONF_CHECK_I(has_pch_encoder);
8740         PIPE_CONF_CHECK_I(fdi_lanes);
8741         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8742         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8743         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8744         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8745         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8746
8747         PIPE_CONF_CHECK_I(has_dp_encoder);
8748         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8749         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8750         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8751         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8752         PIPE_CONF_CHECK_I(dp_m_n.tu);
8753
8754         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8755         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8756         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8757         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8758         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8759         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8760
8761         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8762         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8763         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8764         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8765         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8766         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8767
8768         PIPE_CONF_CHECK_I(pixel_multiplier);
8769
8770         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8771                               DRM_MODE_FLAG_INTERLACE);
8772
8773         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8774                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8775                                       DRM_MODE_FLAG_PHSYNC);
8776                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8777                                       DRM_MODE_FLAG_NHSYNC);
8778                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8779                                       DRM_MODE_FLAG_PVSYNC);
8780                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8781                                       DRM_MODE_FLAG_NVSYNC);
8782         }
8783
8784         PIPE_CONF_CHECK_I(pipe_src_w);
8785         PIPE_CONF_CHECK_I(pipe_src_h);
8786
8787         PIPE_CONF_CHECK_I(gmch_pfit.control);
8788         /* pfit ratios are autocomputed by the hw on gen4+ */
8789         if (INTEL_INFO(dev)->gen < 4)
8790                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8791         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8792         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8793         if (current_config->pch_pfit.enabled) {
8794                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8795                 PIPE_CONF_CHECK_I(pch_pfit.size);
8796         }
8797
8798         PIPE_CONF_CHECK_I(ips_enabled);
8799
8800         PIPE_CONF_CHECK_I(double_wide);
8801
8802         PIPE_CONF_CHECK_I(shared_dpll);
8803         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8804         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8805         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8806         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8807
8808         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8809                 PIPE_CONF_CHECK_I(pipe_bpp);
8810
8811         if (!IS_HASWELL(dev)) {
8812                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
8813                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8814         }
8815
8816 #undef PIPE_CONF_CHECK_X
8817 #undef PIPE_CONF_CHECK_I
8818 #undef PIPE_CONF_CHECK_FLAGS
8819 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8820 #undef PIPE_CONF_QUIRK
8821
8822         return true;
8823 }
8824
8825 static void
8826 check_connector_state(struct drm_device *dev)
8827 {
8828         struct intel_connector *connector;
8829
8830         list_for_each_entry(connector, &dev->mode_config.connector_list,
8831                             base.head) {
8832                 /* This also checks the encoder/connector hw state with the
8833                  * ->get_hw_state callbacks. */
8834                 intel_connector_check_state(connector);
8835
8836                 WARN(&connector->new_encoder->base != connector->base.encoder,
8837                      "connector's staged encoder doesn't match current encoder\n");
8838         }
8839 }
8840
8841 static void
8842 check_encoder_state(struct drm_device *dev)
8843 {
8844         struct intel_encoder *encoder;
8845         struct intel_connector *connector;
8846
8847         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8848                             base.head) {
8849                 bool enabled = false;
8850                 bool active = false;
8851                 enum pipe pipe, tracked_pipe;
8852
8853                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8854                               encoder->base.base.id,
8855                               drm_get_encoder_name(&encoder->base));
8856
8857                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8858                      "encoder's stage crtc doesn't match current crtc\n");
8859                 WARN(encoder->connectors_active && !encoder->base.crtc,
8860                      "encoder's active_connectors set, but no crtc\n");
8861
8862                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8863                                     base.head) {
8864                         if (connector->base.encoder != &encoder->base)
8865                                 continue;
8866                         enabled = true;
8867                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8868                                 active = true;
8869                 }
8870                 WARN(!!encoder->base.crtc != enabled,
8871                      "encoder's enabled state mismatch "
8872                      "(expected %i, found %i)\n",
8873                      !!encoder->base.crtc, enabled);
8874                 WARN(active && !encoder->base.crtc,
8875                      "active encoder with no crtc\n");
8876
8877                 WARN(encoder->connectors_active != active,
8878                      "encoder's computed active state doesn't match tracked active state "
8879                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8880
8881                 active = encoder->get_hw_state(encoder, &pipe);
8882                 WARN(active != encoder->connectors_active,
8883                      "encoder's hw state doesn't match sw tracking "
8884                      "(expected %i, found %i)\n",
8885                      encoder->connectors_active, active);
8886
8887                 if (!encoder->base.crtc)
8888                         continue;
8889
8890                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8891                 WARN(active && pipe != tracked_pipe,
8892                      "active encoder's pipe doesn't match"
8893                      "(expected %i, found %i)\n",
8894                      tracked_pipe, pipe);
8895
8896         }
8897 }
8898
8899 static void
8900 check_crtc_state(struct drm_device *dev)
8901 {
8902         drm_i915_private_t *dev_priv = dev->dev_private;
8903         struct intel_crtc *crtc;
8904         struct intel_encoder *encoder;
8905         struct intel_crtc_config pipe_config;
8906
8907         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8908                             base.head) {
8909                 bool enabled = false;
8910                 bool active = false;
8911
8912                 memset(&pipe_config, 0, sizeof(pipe_config));
8913
8914                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8915                               crtc->base.base.id);
8916
8917                 WARN(crtc->active && !crtc->base.enabled,
8918                      "active crtc, but not enabled in sw tracking\n");
8919
8920                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8921                                     base.head) {
8922                         if (encoder->base.crtc != &crtc->base)
8923                                 continue;
8924                         enabled = true;
8925                         if (encoder->connectors_active)
8926                                 active = true;
8927                 }
8928
8929                 WARN(active != crtc->active,
8930                      "crtc's computed active state doesn't match tracked active state "
8931                      "(expected %i, found %i)\n", active, crtc->active);
8932                 WARN(enabled != crtc->base.enabled,
8933                      "crtc's computed enabled state doesn't match tracked enabled state "
8934                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8935
8936                 active = dev_priv->display.get_pipe_config(crtc,
8937                                                            &pipe_config);
8938
8939                 /* hw state is inconsistent with the pipe A quirk */
8940                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8941                         active = crtc->active;
8942
8943                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8944                                     base.head) {
8945                         enum pipe pipe;
8946                         if (encoder->base.crtc != &crtc->base)
8947                                 continue;
8948                         if (encoder->get_config &&
8949                             encoder->get_hw_state(encoder, &pipe))
8950                                 encoder->get_config(encoder, &pipe_config);
8951                 }
8952
8953                 WARN(crtc->active != active,
8954                      "crtc active state doesn't match with hw state "
8955                      "(expected %i, found %i)\n", crtc->active, active);
8956
8957                 if (active &&
8958                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8959                         WARN(1, "pipe state doesn't match!\n");
8960                         intel_dump_pipe_config(crtc, &pipe_config,
8961                                                "[hw state]");
8962                         intel_dump_pipe_config(crtc, &crtc->config,
8963                                                "[sw state]");
8964                 }
8965         }
8966 }
8967
8968 static void
8969 check_shared_dpll_state(struct drm_device *dev)
8970 {
8971         drm_i915_private_t *dev_priv = dev->dev_private;
8972         struct intel_crtc *crtc;
8973         struct intel_dpll_hw_state dpll_hw_state;
8974         int i;
8975
8976         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8977                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8978                 int enabled_crtcs = 0, active_crtcs = 0;
8979                 bool active;
8980
8981                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8982
8983                 DRM_DEBUG_KMS("%s\n", pll->name);
8984
8985                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8986
8987                 WARN(pll->active > pll->refcount,
8988                      "more active pll users than references: %i vs %i\n",
8989                      pll->active, pll->refcount);
8990                 WARN(pll->active && !pll->on,
8991                      "pll in active use but not on in sw tracking\n");
8992                 WARN(pll->on && !pll->active,
8993                      "pll in on but not on in use in sw tracking\n");
8994                 WARN(pll->on != active,
8995                      "pll on state mismatch (expected %i, found %i)\n",
8996                      pll->on, active);
8997
8998                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8999                                     base.head) {
9000                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9001                                 enabled_crtcs++;
9002                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9003                                 active_crtcs++;
9004                 }
9005                 WARN(pll->active != active_crtcs,
9006                      "pll active crtcs mismatch (expected %i, found %i)\n",
9007                      pll->active, active_crtcs);
9008                 WARN(pll->refcount != enabled_crtcs,
9009                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9010                      pll->refcount, enabled_crtcs);
9011
9012                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9013                                        sizeof(dpll_hw_state)),
9014                      "pll hw state mismatch\n");
9015         }
9016 }
9017
9018 void
9019 intel_modeset_check_state(struct drm_device *dev)
9020 {
9021         check_connector_state(dev);
9022         check_encoder_state(dev);
9023         check_crtc_state(dev);
9024         check_shared_dpll_state(dev);
9025 }
9026
9027 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9028                                      int dotclock)
9029 {
9030         /*
9031          * FDI already provided one idea for the dotclock.
9032          * Yell if the encoder disagrees.
9033          */
9034         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9035              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9036              pipe_config->adjusted_mode.clock, dotclock);
9037 }
9038
9039 static int __intel_set_mode(struct drm_crtc *crtc,
9040                             struct drm_display_mode *mode,
9041                             int x, int y, struct drm_framebuffer *fb)
9042 {
9043         struct drm_device *dev = crtc->dev;
9044         drm_i915_private_t *dev_priv = dev->dev_private;
9045         struct drm_display_mode *saved_mode, *saved_hwmode;
9046         struct intel_crtc_config *pipe_config = NULL;
9047         struct intel_crtc *intel_crtc;
9048         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9049         int ret = 0;
9050
9051         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
9052         if (!saved_mode)
9053                 return -ENOMEM;
9054         saved_hwmode = saved_mode + 1;
9055
9056         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9057                                      &prepare_pipes, &disable_pipes);
9058
9059         *saved_hwmode = crtc->hwmode;
9060         *saved_mode = crtc->mode;
9061
9062         /* Hack: Because we don't (yet) support global modeset on multiple
9063          * crtcs, we don't keep track of the new mode for more than one crtc.
9064          * Hence simply check whether any bit is set in modeset_pipes in all the
9065          * pieces of code that are not yet converted to deal with mutliple crtcs
9066          * changing their mode at the same time. */
9067         if (modeset_pipes) {
9068                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9069                 if (IS_ERR(pipe_config)) {
9070                         ret = PTR_ERR(pipe_config);
9071                         pipe_config = NULL;
9072
9073                         goto out;
9074                 }
9075                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9076                                        "[modeset]");
9077         }
9078
9079         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9080                 intel_crtc_disable(&intel_crtc->base);
9081
9082         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9083                 if (intel_crtc->base.enabled)
9084                         dev_priv->display.crtc_disable(&intel_crtc->base);
9085         }
9086
9087         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9088          * to set it here already despite that we pass it down the callchain.
9089          */
9090         if (modeset_pipes) {
9091                 crtc->mode = *mode;
9092                 /* mode_set/enable/disable functions rely on a correct pipe
9093                  * config. */
9094                 to_intel_crtc(crtc)->config = *pipe_config;
9095         }
9096
9097         /* Only after disabling all output pipelines that will be changed can we
9098          * update the the output configuration. */
9099         intel_modeset_update_state(dev, prepare_pipes);
9100
9101         if (dev_priv->display.modeset_global_resources)
9102                 dev_priv->display.modeset_global_resources(dev);
9103
9104         /* Set up the DPLL and any encoders state that needs to adjust or depend
9105          * on the DPLL.
9106          */
9107         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9108                 ret = intel_crtc_mode_set(&intel_crtc->base,
9109                                           x, y, fb);
9110                 if (ret)
9111                         goto done;
9112         }
9113
9114         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9115         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9116                 dev_priv->display.crtc_enable(&intel_crtc->base);
9117
9118         if (modeset_pipes) {
9119                 /* Store real post-adjustment hardware mode. */
9120                 crtc->hwmode = pipe_config->adjusted_mode;
9121
9122                 /* Calculate and store various constants which
9123                  * are later needed by vblank and swap-completion
9124                  * timestamping. They are derived from true hwmode.
9125                  */
9126                 drm_calc_timestamping_constants(crtc);
9127         }
9128
9129         /* FIXME: add subpixel order */
9130 done:
9131         if (ret && crtc->enabled) {
9132                 crtc->hwmode = *saved_hwmode;
9133                 crtc->mode = *saved_mode;
9134         }
9135
9136 out:
9137         kfree(pipe_config);
9138         kfree(saved_mode);
9139         return ret;
9140 }
9141
9142 static int intel_set_mode(struct drm_crtc *crtc,
9143                           struct drm_display_mode *mode,
9144                           int x, int y, struct drm_framebuffer *fb)
9145 {
9146         int ret;
9147
9148         ret = __intel_set_mode(crtc, mode, x, y, fb);
9149
9150         if (ret == 0)
9151                 intel_modeset_check_state(crtc->dev);
9152
9153         return ret;
9154 }
9155
9156 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9157 {
9158         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9159 }
9160
9161 #undef for_each_intel_crtc_masked
9162
9163 static void intel_set_config_free(struct intel_set_config *config)
9164 {
9165         if (!config)
9166                 return;
9167
9168         kfree(config->save_connector_encoders);
9169         kfree(config->save_encoder_crtcs);
9170         kfree(config);
9171 }
9172
9173 static int intel_set_config_save_state(struct drm_device *dev,
9174                                        struct intel_set_config *config)
9175 {
9176         struct drm_encoder *encoder;
9177         struct drm_connector *connector;
9178         int count;
9179
9180         config->save_encoder_crtcs =
9181                 kcalloc(dev->mode_config.num_encoder,
9182                         sizeof(struct drm_crtc *), GFP_KERNEL);
9183         if (!config->save_encoder_crtcs)
9184                 return -ENOMEM;
9185
9186         config->save_connector_encoders =
9187                 kcalloc(dev->mode_config.num_connector,
9188                         sizeof(struct drm_encoder *), GFP_KERNEL);
9189         if (!config->save_connector_encoders)
9190                 return -ENOMEM;
9191
9192         /* Copy data. Note that driver private data is not affected.
9193          * Should anything bad happen only the expected state is
9194          * restored, not the drivers personal bookkeeping.
9195          */
9196         count = 0;
9197         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9198                 config->save_encoder_crtcs[count++] = encoder->crtc;
9199         }
9200
9201         count = 0;
9202         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9203                 config->save_connector_encoders[count++] = connector->encoder;
9204         }
9205
9206         return 0;
9207 }
9208
9209 static void intel_set_config_restore_state(struct drm_device *dev,
9210                                            struct intel_set_config *config)
9211 {
9212         struct intel_encoder *encoder;
9213         struct intel_connector *connector;
9214         int count;
9215
9216         count = 0;
9217         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9218                 encoder->new_crtc =
9219                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9220         }
9221
9222         count = 0;
9223         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9224                 connector->new_encoder =
9225                         to_intel_encoder(config->save_connector_encoders[count++]);
9226         }
9227 }
9228
9229 static bool
9230 is_crtc_connector_off(struct drm_mode_set *set)
9231 {
9232         int i;
9233
9234         if (set->num_connectors == 0)
9235                 return false;
9236
9237         if (WARN_ON(set->connectors == NULL))
9238                 return false;
9239
9240         for (i = 0; i < set->num_connectors; i++)
9241                 if (set->connectors[i]->encoder &&
9242                     set->connectors[i]->encoder->crtc == set->crtc &&
9243                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9244                         return true;
9245
9246         return false;
9247 }
9248
9249 static void
9250 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9251                                       struct intel_set_config *config)
9252 {
9253
9254         /* We should be able to check here if the fb has the same properties
9255          * and then just flip_or_move it */
9256         if (is_crtc_connector_off(set)) {
9257                 config->mode_changed = true;
9258         } else if (set->crtc->fb != set->fb) {
9259                 /* If we have no fb then treat it as a full mode set */
9260                 if (set->crtc->fb == NULL) {
9261                         struct intel_crtc *intel_crtc =
9262                                 to_intel_crtc(set->crtc);
9263
9264                         if (intel_crtc->active && i915_fastboot) {
9265                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9266                                 config->fb_changed = true;
9267                         } else {
9268                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9269                                 config->mode_changed = true;
9270                         }
9271                 } else if (set->fb == NULL) {
9272                         config->mode_changed = true;
9273                 } else if (set->fb->pixel_format !=
9274                            set->crtc->fb->pixel_format) {
9275                         config->mode_changed = true;
9276                 } else {
9277                         config->fb_changed = true;
9278                 }
9279         }
9280
9281         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9282                 config->fb_changed = true;
9283
9284         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9285                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9286                 drm_mode_debug_printmodeline(&set->crtc->mode);
9287                 drm_mode_debug_printmodeline(set->mode);
9288                 config->mode_changed = true;
9289         }
9290
9291         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9292                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9293 }
9294
9295 static int
9296 intel_modeset_stage_output_state(struct drm_device *dev,
9297                                  struct drm_mode_set *set,
9298                                  struct intel_set_config *config)
9299 {
9300         struct drm_crtc *new_crtc;
9301         struct intel_connector *connector;
9302         struct intel_encoder *encoder;
9303         int ro;
9304
9305         /* The upper layers ensure that we either disable a crtc or have a list
9306          * of connectors. For paranoia, double-check this. */
9307         WARN_ON(!set->fb && (set->num_connectors != 0));
9308         WARN_ON(set->fb && (set->num_connectors == 0));
9309
9310         list_for_each_entry(connector, &dev->mode_config.connector_list,
9311                             base.head) {
9312                 /* Otherwise traverse passed in connector list and get encoders
9313                  * for them. */
9314                 for (ro = 0; ro < set->num_connectors; ro++) {
9315                         if (set->connectors[ro] == &connector->base) {
9316                                 connector->new_encoder = connector->encoder;
9317                                 break;
9318                         }
9319                 }
9320
9321                 /* If we disable the crtc, disable all its connectors. Also, if
9322                  * the connector is on the changing crtc but not on the new
9323                  * connector list, disable it. */
9324                 if ((!set->fb || ro == set->num_connectors) &&
9325                     connector->base.encoder &&
9326                     connector->base.encoder->crtc == set->crtc) {
9327                         connector->new_encoder = NULL;
9328
9329                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9330                                 connector->base.base.id,
9331                                 drm_get_connector_name(&connector->base));
9332                 }
9333
9334
9335                 if (&connector->new_encoder->base != connector->base.encoder) {
9336                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9337                         config->mode_changed = true;
9338                 }
9339         }
9340         /* connector->new_encoder is now updated for all connectors. */
9341
9342         /* Update crtc of enabled connectors. */
9343         list_for_each_entry(connector, &dev->mode_config.connector_list,
9344                             base.head) {
9345                 if (!connector->new_encoder)
9346                         continue;
9347
9348                 new_crtc = connector->new_encoder->base.crtc;
9349
9350                 for (ro = 0; ro < set->num_connectors; ro++) {
9351                         if (set->connectors[ro] == &connector->base)
9352                                 new_crtc = set->crtc;
9353                 }
9354
9355                 /* Make sure the new CRTC will work with the encoder */
9356                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9357                                            new_crtc)) {
9358                         return -EINVAL;
9359                 }
9360                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9361
9362                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9363                         connector->base.base.id,
9364                         drm_get_connector_name(&connector->base),
9365                         new_crtc->base.id);
9366         }
9367
9368         /* Check for any encoders that needs to be disabled. */
9369         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9370                             base.head) {
9371                 list_for_each_entry(connector,
9372                                     &dev->mode_config.connector_list,
9373                                     base.head) {
9374                         if (connector->new_encoder == encoder) {
9375                                 WARN_ON(!connector->new_encoder->new_crtc);
9376
9377                                 goto next_encoder;
9378                         }
9379                 }
9380                 encoder->new_crtc = NULL;
9381 next_encoder:
9382                 /* Only now check for crtc changes so we don't miss encoders
9383                  * that will be disabled. */
9384                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9385                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9386                         config->mode_changed = true;
9387                 }
9388         }
9389         /* Now we've also updated encoder->new_crtc for all encoders. */
9390
9391         return 0;
9392 }
9393
9394 static int intel_crtc_set_config(struct drm_mode_set *set)
9395 {
9396         struct drm_device *dev;
9397         struct drm_mode_set save_set;
9398         struct intel_set_config *config;
9399         int ret;
9400
9401         BUG_ON(!set);
9402         BUG_ON(!set->crtc);
9403         BUG_ON(!set->crtc->helper_private);
9404
9405         /* Enforce sane interface api - has been abused by the fb helper. */
9406         BUG_ON(!set->mode && set->fb);
9407         BUG_ON(set->fb && set->num_connectors == 0);
9408
9409         if (set->fb) {
9410                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9411                                 set->crtc->base.id, set->fb->base.id,
9412                                 (int)set->num_connectors, set->x, set->y);
9413         } else {
9414                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9415         }
9416
9417         dev = set->crtc->dev;
9418
9419         ret = -ENOMEM;
9420         config = kzalloc(sizeof(*config), GFP_KERNEL);
9421         if (!config)
9422                 goto out_config;
9423
9424         ret = intel_set_config_save_state(dev, config);
9425         if (ret)
9426                 goto out_config;
9427
9428         save_set.crtc = set->crtc;
9429         save_set.mode = &set->crtc->mode;
9430         save_set.x = set->crtc->x;
9431         save_set.y = set->crtc->y;
9432         save_set.fb = set->crtc->fb;
9433
9434         /* Compute whether we need a full modeset, only an fb base update or no
9435          * change at all. In the future we might also check whether only the
9436          * mode changed, e.g. for LVDS where we only change the panel fitter in
9437          * such cases. */
9438         intel_set_config_compute_mode_changes(set, config);
9439
9440         ret = intel_modeset_stage_output_state(dev, set, config);
9441         if (ret)
9442                 goto fail;
9443
9444         if (config->mode_changed) {
9445                 ret = intel_set_mode(set->crtc, set->mode,
9446                                      set->x, set->y, set->fb);
9447         } else if (config->fb_changed) {
9448                 intel_crtc_wait_for_pending_flips(set->crtc);
9449
9450                 ret = intel_pipe_set_base(set->crtc,
9451                                           set->x, set->y, set->fb);
9452         }
9453
9454         if (ret) {
9455                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9456                               set->crtc->base.id, ret);
9457 fail:
9458                 intel_set_config_restore_state(dev, config);
9459
9460                 /* Try to restore the config */
9461                 if (config->mode_changed &&
9462                     intel_set_mode(save_set.crtc, save_set.mode,
9463                                    save_set.x, save_set.y, save_set.fb))
9464                         DRM_ERROR("failed to restore config after modeset failure\n");
9465         }
9466
9467 out_config:
9468         intel_set_config_free(config);
9469         return ret;
9470 }
9471
9472 static const struct drm_crtc_funcs intel_crtc_funcs = {
9473         .cursor_set = intel_crtc_cursor_set,
9474         .cursor_move = intel_crtc_cursor_move,
9475         .gamma_set = intel_crtc_gamma_set,
9476         .set_config = intel_crtc_set_config,
9477         .destroy = intel_crtc_destroy,
9478         .page_flip = intel_crtc_page_flip,
9479 };
9480
9481 static void intel_cpu_pll_init(struct drm_device *dev)
9482 {
9483         if (HAS_DDI(dev))
9484                 intel_ddi_pll_init(dev);
9485 }
9486
9487 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9488                                       struct intel_shared_dpll *pll,
9489                                       struct intel_dpll_hw_state *hw_state)
9490 {
9491         uint32_t val;
9492
9493         val = I915_READ(PCH_DPLL(pll->id));
9494         hw_state->dpll = val;
9495         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9496         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9497
9498         return val & DPLL_VCO_ENABLE;
9499 }
9500
9501 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9502                                   struct intel_shared_dpll *pll)
9503 {
9504         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9505         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9506 }
9507
9508 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9509                                 struct intel_shared_dpll *pll)
9510 {
9511         /* PCH refclock must be enabled first */
9512         assert_pch_refclk_enabled(dev_priv);
9513
9514         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9515
9516         /* Wait for the clocks to stabilize. */
9517         POSTING_READ(PCH_DPLL(pll->id));
9518         udelay(150);
9519
9520         /* The pixel multiplier can only be updated once the
9521          * DPLL is enabled and the clocks are stable.
9522          *
9523          * So write it again.
9524          */
9525         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9526         POSTING_READ(PCH_DPLL(pll->id));
9527         udelay(200);
9528 }
9529
9530 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9531                                  struct intel_shared_dpll *pll)
9532 {
9533         struct drm_device *dev = dev_priv->dev;
9534         struct intel_crtc *crtc;
9535
9536         /* Make sure no transcoder isn't still depending on us. */
9537         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9538                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9539                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9540         }
9541
9542         I915_WRITE(PCH_DPLL(pll->id), 0);
9543         POSTING_READ(PCH_DPLL(pll->id));
9544         udelay(200);
9545 }
9546
9547 static char *ibx_pch_dpll_names[] = {
9548         "PCH DPLL A",
9549         "PCH DPLL B",
9550 };
9551
9552 static void ibx_pch_dpll_init(struct drm_device *dev)
9553 {
9554         struct drm_i915_private *dev_priv = dev->dev_private;
9555         int i;
9556
9557         dev_priv->num_shared_dpll = 2;
9558
9559         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9560                 dev_priv->shared_dplls[i].id = i;
9561                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9562                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9563                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9564                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9565                 dev_priv->shared_dplls[i].get_hw_state =
9566                         ibx_pch_dpll_get_hw_state;
9567         }
9568 }
9569
9570 static void intel_shared_dpll_init(struct drm_device *dev)
9571 {
9572         struct drm_i915_private *dev_priv = dev->dev_private;
9573
9574         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9575                 ibx_pch_dpll_init(dev);
9576         else
9577                 dev_priv->num_shared_dpll = 0;
9578
9579         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9580         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9581                       dev_priv->num_shared_dpll);
9582 }
9583
9584 static void intel_crtc_init(struct drm_device *dev, int pipe)
9585 {
9586         drm_i915_private_t *dev_priv = dev->dev_private;
9587         struct intel_crtc *intel_crtc;
9588         int i;
9589
9590         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9591         if (intel_crtc == NULL)
9592                 return;
9593
9594         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9595
9596         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9597         for (i = 0; i < 256; i++) {
9598                 intel_crtc->lut_r[i] = i;
9599                 intel_crtc->lut_g[i] = i;
9600                 intel_crtc->lut_b[i] = i;
9601         }
9602
9603         /* Swap pipes & planes for FBC on pre-965 */
9604         intel_crtc->pipe = pipe;
9605         intel_crtc->plane = pipe;
9606         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9607                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9608                 intel_crtc->plane = !pipe;
9609         }
9610
9611         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9612                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9613         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9614         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9615
9616         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9617 }
9618
9619 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9620                                 struct drm_file *file)
9621 {
9622         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9623         struct drm_mode_object *drmmode_obj;
9624         struct intel_crtc *crtc;
9625
9626         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9627                 return -ENODEV;
9628
9629         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9630                         DRM_MODE_OBJECT_CRTC);
9631
9632         if (!drmmode_obj) {
9633                 DRM_ERROR("no such CRTC id\n");
9634                 return -EINVAL;
9635         }
9636
9637         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9638         pipe_from_crtc_id->pipe = crtc->pipe;
9639
9640         return 0;
9641 }
9642
9643 static int intel_encoder_clones(struct intel_encoder *encoder)
9644 {
9645         struct drm_device *dev = encoder->base.dev;
9646         struct intel_encoder *source_encoder;
9647         int index_mask = 0;
9648         int entry = 0;
9649
9650         list_for_each_entry(source_encoder,
9651                             &dev->mode_config.encoder_list, base.head) {
9652
9653                 if (encoder == source_encoder)
9654                         index_mask |= (1 << entry);
9655
9656                 /* Intel hw has only one MUX where enocoders could be cloned. */
9657                 if (encoder->cloneable && source_encoder->cloneable)
9658                         index_mask |= (1 << entry);
9659
9660                 entry++;
9661         }
9662
9663         return index_mask;
9664 }
9665
9666 static bool has_edp_a(struct drm_device *dev)
9667 {
9668         struct drm_i915_private *dev_priv = dev->dev_private;
9669
9670         if (!IS_MOBILE(dev))
9671                 return false;
9672
9673         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9674                 return false;
9675
9676         if (IS_GEN5(dev) &&
9677             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9678                 return false;
9679
9680         return true;
9681 }
9682
9683 static void intel_setup_outputs(struct drm_device *dev)
9684 {
9685         struct drm_i915_private *dev_priv = dev->dev_private;
9686         struct intel_encoder *encoder;
9687         bool dpd_is_edp = false;
9688
9689         intel_lvds_init(dev);
9690
9691         if (!IS_ULT(dev))
9692                 intel_crt_init(dev);
9693
9694         if (HAS_DDI(dev)) {
9695                 int found;
9696
9697                 /* Haswell uses DDI functions to detect digital outputs */
9698                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9699                 /* DDI A only supports eDP */
9700                 if (found)
9701                         intel_ddi_init(dev, PORT_A);
9702
9703                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9704                  * register */
9705                 found = I915_READ(SFUSE_STRAP);
9706
9707                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9708                         intel_ddi_init(dev, PORT_B);
9709                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9710                         intel_ddi_init(dev, PORT_C);
9711                 if (found & SFUSE_STRAP_DDID_DETECTED)
9712                         intel_ddi_init(dev, PORT_D);
9713         } else if (HAS_PCH_SPLIT(dev)) {
9714                 int found;
9715                 dpd_is_edp = intel_dpd_is_edp(dev);
9716
9717                 if (has_edp_a(dev))
9718                         intel_dp_init(dev, DP_A, PORT_A);
9719
9720                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9721                         /* PCH SDVOB multiplex with HDMIB */
9722                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9723                         if (!found)
9724                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9725                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9726                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9727                 }
9728
9729                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9730                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9731
9732                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9733                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9734
9735                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9736                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9737
9738                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9739                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9740         } else if (IS_VALLEYVIEW(dev)) {
9741                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9742                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9743                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9744                                         PORT_C);
9745                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9746                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9747                                               PORT_C);
9748                 }
9749
9750                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9751                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9752                                         PORT_B);
9753                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9754                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9755                 }
9756
9757                 intel_dsi_init(dev);
9758         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9759                 bool found = false;
9760
9761                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9762                         DRM_DEBUG_KMS("probing SDVOB\n");
9763                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9764                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9765                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9766                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9767                         }
9768
9769                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9770                                 intel_dp_init(dev, DP_B, PORT_B);
9771                 }
9772
9773                 /* Before G4X SDVOC doesn't have its own detect register */
9774
9775                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9776                         DRM_DEBUG_KMS("probing SDVOC\n");
9777                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9778                 }
9779
9780                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9781
9782                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9783                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9784                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9785                         }
9786                         if (SUPPORTS_INTEGRATED_DP(dev))
9787                                 intel_dp_init(dev, DP_C, PORT_C);
9788                 }
9789
9790                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9791                     (I915_READ(DP_D) & DP_DETECTED))
9792                         intel_dp_init(dev, DP_D, PORT_D);
9793         } else if (IS_GEN2(dev))
9794                 intel_dvo_init(dev);
9795
9796         if (SUPPORTS_TV(dev))
9797                 intel_tv_init(dev);
9798
9799         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9800                 encoder->base.possible_crtcs = encoder->crtc_mask;
9801                 encoder->base.possible_clones =
9802                         intel_encoder_clones(encoder);
9803         }
9804
9805         intel_init_pch_refclk(dev);
9806
9807         drm_helper_move_panel_connectors_to_head(dev);
9808 }
9809
9810 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9811 {
9812         drm_framebuffer_cleanup(&fb->base);
9813         drm_gem_object_unreference_unlocked(&fb->obj->base);
9814 }
9815
9816 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9817 {
9818         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9819
9820         intel_framebuffer_fini(intel_fb);
9821         kfree(intel_fb);
9822 }
9823
9824 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9825                                                 struct drm_file *file,
9826                                                 unsigned int *handle)
9827 {
9828         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9829         struct drm_i915_gem_object *obj = intel_fb->obj;
9830
9831         return drm_gem_handle_create(file, &obj->base, handle);
9832 }
9833
9834 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9835         .destroy = intel_user_framebuffer_destroy,
9836         .create_handle = intel_user_framebuffer_create_handle,
9837 };
9838
9839 int intel_framebuffer_init(struct drm_device *dev,
9840                            struct intel_framebuffer *intel_fb,
9841                            struct drm_mode_fb_cmd2 *mode_cmd,
9842                            struct drm_i915_gem_object *obj)
9843 {
9844         int pitch_limit;
9845         int ret;
9846
9847         if (obj->tiling_mode == I915_TILING_Y) {
9848                 DRM_DEBUG("hardware does not support tiling Y\n");
9849                 return -EINVAL;
9850         }
9851
9852         if (mode_cmd->pitches[0] & 63) {
9853                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9854                           mode_cmd->pitches[0]);
9855                 return -EINVAL;
9856         }
9857
9858         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9859                 pitch_limit = 32*1024;
9860         } else if (INTEL_INFO(dev)->gen >= 4) {
9861                 if (obj->tiling_mode)
9862                         pitch_limit = 16*1024;
9863                 else
9864                         pitch_limit = 32*1024;
9865         } else if (INTEL_INFO(dev)->gen >= 3) {
9866                 if (obj->tiling_mode)
9867                         pitch_limit = 8*1024;
9868                 else
9869                         pitch_limit = 16*1024;
9870         } else
9871                 /* XXX DSPC is limited to 4k tiled */
9872                 pitch_limit = 8*1024;
9873
9874         if (mode_cmd->pitches[0] > pitch_limit) {
9875                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9876                           obj->tiling_mode ? "tiled" : "linear",
9877                           mode_cmd->pitches[0], pitch_limit);
9878                 return -EINVAL;
9879         }
9880
9881         if (obj->tiling_mode != I915_TILING_NONE &&
9882             mode_cmd->pitches[0] != obj->stride) {
9883                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9884                           mode_cmd->pitches[0], obj->stride);
9885                 return -EINVAL;
9886         }
9887
9888         /* Reject formats not supported by any plane early. */
9889         switch (mode_cmd->pixel_format) {
9890         case DRM_FORMAT_C8:
9891         case DRM_FORMAT_RGB565:
9892         case DRM_FORMAT_XRGB8888:
9893         case DRM_FORMAT_ARGB8888:
9894                 break;
9895         case DRM_FORMAT_XRGB1555:
9896         case DRM_FORMAT_ARGB1555:
9897                 if (INTEL_INFO(dev)->gen > 3) {
9898                         DRM_DEBUG("unsupported pixel format: %s\n",
9899                                   drm_get_format_name(mode_cmd->pixel_format));
9900                         return -EINVAL;
9901                 }
9902                 break;
9903         case DRM_FORMAT_XBGR8888:
9904         case DRM_FORMAT_ABGR8888:
9905         case DRM_FORMAT_XRGB2101010:
9906         case DRM_FORMAT_ARGB2101010:
9907         case DRM_FORMAT_XBGR2101010:
9908         case DRM_FORMAT_ABGR2101010:
9909                 if (INTEL_INFO(dev)->gen < 4) {
9910                         DRM_DEBUG("unsupported pixel format: %s\n",
9911                                   drm_get_format_name(mode_cmd->pixel_format));
9912                         return -EINVAL;
9913                 }
9914                 break;
9915         case DRM_FORMAT_YUYV:
9916         case DRM_FORMAT_UYVY:
9917         case DRM_FORMAT_YVYU:
9918         case DRM_FORMAT_VYUY:
9919                 if (INTEL_INFO(dev)->gen < 5) {
9920                         DRM_DEBUG("unsupported pixel format: %s\n",
9921                                   drm_get_format_name(mode_cmd->pixel_format));
9922                         return -EINVAL;
9923                 }
9924                 break;
9925         default:
9926                 DRM_DEBUG("unsupported pixel format: %s\n",
9927                           drm_get_format_name(mode_cmd->pixel_format));
9928                 return -EINVAL;
9929         }
9930
9931         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9932         if (mode_cmd->offsets[0] != 0)
9933                 return -EINVAL;
9934
9935         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9936         intel_fb->obj = obj;
9937
9938         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9939         if (ret) {
9940                 DRM_ERROR("framebuffer init failed %d\n", ret);
9941                 return ret;
9942         }
9943
9944         return 0;
9945 }
9946
9947 static struct drm_framebuffer *
9948 intel_user_framebuffer_create(struct drm_device *dev,
9949                               struct drm_file *filp,
9950                               struct drm_mode_fb_cmd2 *mode_cmd)
9951 {
9952         struct drm_i915_gem_object *obj;
9953
9954         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9955                                                 mode_cmd->handles[0]));
9956         if (&obj->base == NULL)
9957                 return ERR_PTR(-ENOENT);
9958
9959         return intel_framebuffer_create(dev, mode_cmd, obj);
9960 }
9961
9962 static const struct drm_mode_config_funcs intel_mode_funcs = {
9963         .fb_create = intel_user_framebuffer_create,
9964         .output_poll_changed = intel_fb_output_poll_changed,
9965 };
9966
9967 /* Set up chip specific display functions */
9968 static void intel_init_display(struct drm_device *dev)
9969 {
9970         struct drm_i915_private *dev_priv = dev->dev_private;
9971
9972         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9973                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9974         else if (IS_VALLEYVIEW(dev))
9975                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9976         else if (IS_PINEVIEW(dev))
9977                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9978         else
9979                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9980
9981         if (HAS_DDI(dev)) {
9982                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9983                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9984                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9985                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9986                 dev_priv->display.off = haswell_crtc_off;
9987                 dev_priv->display.update_plane = ironlake_update_plane;
9988         } else if (HAS_PCH_SPLIT(dev)) {
9989                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9990                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9991                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9992                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9993                 dev_priv->display.off = ironlake_crtc_off;
9994                 dev_priv->display.update_plane = ironlake_update_plane;
9995         } else if (IS_VALLEYVIEW(dev)) {
9996                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9997                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9998                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9999                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10000                 dev_priv->display.off = i9xx_crtc_off;
10001                 dev_priv->display.update_plane = i9xx_update_plane;
10002         } else {
10003                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10004                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10005                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10006                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10007                 dev_priv->display.off = i9xx_crtc_off;
10008                 dev_priv->display.update_plane = i9xx_update_plane;
10009         }
10010
10011         /* Returns the core display clock speed */
10012         if (IS_VALLEYVIEW(dev))
10013                 dev_priv->display.get_display_clock_speed =
10014                         valleyview_get_display_clock_speed;
10015         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10016                 dev_priv->display.get_display_clock_speed =
10017                         i945_get_display_clock_speed;
10018         else if (IS_I915G(dev))
10019                 dev_priv->display.get_display_clock_speed =
10020                         i915_get_display_clock_speed;
10021         else if (IS_I945GM(dev) || IS_845G(dev))
10022                 dev_priv->display.get_display_clock_speed =
10023                         i9xx_misc_get_display_clock_speed;
10024         else if (IS_PINEVIEW(dev))
10025                 dev_priv->display.get_display_clock_speed =
10026                         pnv_get_display_clock_speed;
10027         else if (IS_I915GM(dev))
10028                 dev_priv->display.get_display_clock_speed =
10029                         i915gm_get_display_clock_speed;
10030         else if (IS_I865G(dev))
10031                 dev_priv->display.get_display_clock_speed =
10032                         i865_get_display_clock_speed;
10033         else if (IS_I85X(dev))
10034                 dev_priv->display.get_display_clock_speed =
10035                         i855_get_display_clock_speed;
10036         else /* 852, 830 */
10037                 dev_priv->display.get_display_clock_speed =
10038                         i830_get_display_clock_speed;
10039
10040         if (HAS_PCH_SPLIT(dev)) {
10041                 if (IS_GEN5(dev)) {
10042                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10043                         dev_priv->display.write_eld = ironlake_write_eld;
10044                 } else if (IS_GEN6(dev)) {
10045                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10046                         dev_priv->display.write_eld = ironlake_write_eld;
10047                 } else if (IS_IVYBRIDGE(dev)) {
10048                         /* FIXME: detect B0+ stepping and use auto training */
10049                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10050                         dev_priv->display.write_eld = ironlake_write_eld;
10051                         dev_priv->display.modeset_global_resources =
10052                                 ivb_modeset_global_resources;
10053                 } else if (IS_HASWELL(dev)) {
10054                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10055                         dev_priv->display.write_eld = haswell_write_eld;
10056                         dev_priv->display.modeset_global_resources =
10057                                 haswell_modeset_global_resources;
10058                 }
10059         } else if (IS_G4X(dev)) {
10060                 dev_priv->display.write_eld = g4x_write_eld;
10061         }
10062
10063         /* Default just returns -ENODEV to indicate unsupported */
10064         dev_priv->display.queue_flip = intel_default_queue_flip;
10065
10066         switch (INTEL_INFO(dev)->gen) {
10067         case 2:
10068                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10069                 break;
10070
10071         case 3:
10072                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10073                 break;
10074
10075         case 4:
10076         case 5:
10077                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10078                 break;
10079
10080         case 6:
10081                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10082                 break;
10083         case 7:
10084                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10085                 break;
10086         }
10087 }
10088
10089 /*
10090  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10091  * resume, or other times.  This quirk makes sure that's the case for
10092  * affected systems.
10093  */
10094 static void quirk_pipea_force(struct drm_device *dev)
10095 {
10096         struct drm_i915_private *dev_priv = dev->dev_private;
10097
10098         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10099         DRM_INFO("applying pipe a force quirk\n");
10100 }
10101
10102 /*
10103  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10104  */
10105 static void quirk_ssc_force_disable(struct drm_device *dev)
10106 {
10107         struct drm_i915_private *dev_priv = dev->dev_private;
10108         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10109         DRM_INFO("applying lvds SSC disable quirk\n");
10110 }
10111
10112 /*
10113  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10114  * brightness value
10115  */
10116 static void quirk_invert_brightness(struct drm_device *dev)
10117 {
10118         struct drm_i915_private *dev_priv = dev->dev_private;
10119         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10120         DRM_INFO("applying inverted panel brightness quirk\n");
10121 }
10122
10123 /*
10124  * Some machines (Dell XPS13) suffer broken backlight controls if
10125  * BLM_PCH_PWM_ENABLE is set.
10126  */
10127 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10128 {
10129         struct drm_i915_private *dev_priv = dev->dev_private;
10130         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10131         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10132 }
10133
10134 struct intel_quirk {
10135         int device;
10136         int subsystem_vendor;
10137         int subsystem_device;
10138         void (*hook)(struct drm_device *dev);
10139 };
10140
10141 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10142 struct intel_dmi_quirk {
10143         void (*hook)(struct drm_device *dev);
10144         const struct dmi_system_id (*dmi_id_list)[];
10145 };
10146
10147 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10148 {
10149         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10150         return 1;
10151 }
10152
10153 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10154         {
10155                 .dmi_id_list = &(const struct dmi_system_id[]) {
10156                         {
10157                                 .callback = intel_dmi_reverse_brightness,
10158                                 .ident = "NCR Corporation",
10159                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10160                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10161                                 },
10162                         },
10163                         { }  /* terminating entry */
10164                 },
10165                 .hook = quirk_invert_brightness,
10166         },
10167 };
10168
10169 static struct intel_quirk intel_quirks[] = {
10170         /* HP Mini needs pipe A force quirk (LP: #322104) */
10171         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10172
10173         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10174         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10175
10176         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10177         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10178
10179         /* 830/845 need to leave pipe A & dpll A up */
10180         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10181         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10182
10183         /* Lenovo U160 cannot use SSC on LVDS */
10184         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10185
10186         /* Sony Vaio Y cannot use SSC on LVDS */
10187         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10188
10189         /*
10190          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10191          * seem to use inverted backlight PWM.
10192          */
10193         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10194
10195         /* Dell XPS13 HD Sandy Bridge */
10196         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10197         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10198         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10199 };
10200
10201 static void intel_init_quirks(struct drm_device *dev)
10202 {
10203         struct pci_dev *d = dev->pdev;
10204         int i;
10205
10206         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10207                 struct intel_quirk *q = &intel_quirks[i];
10208
10209                 if (d->device == q->device &&
10210                     (d->subsystem_vendor == q->subsystem_vendor ||
10211                      q->subsystem_vendor == PCI_ANY_ID) &&
10212                     (d->subsystem_device == q->subsystem_device ||
10213                      q->subsystem_device == PCI_ANY_ID))
10214                         q->hook(dev);
10215         }
10216         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10217                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10218                         intel_dmi_quirks[i].hook(dev);
10219         }
10220 }
10221
10222 /* Disable the VGA plane that we never use */
10223 static void i915_disable_vga(struct drm_device *dev)
10224 {
10225         struct drm_i915_private *dev_priv = dev->dev_private;
10226         u8 sr1;
10227         u32 vga_reg = i915_vgacntrl_reg(dev);
10228
10229         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10230         outb(SR01, VGA_SR_INDEX);
10231         sr1 = inb(VGA_SR_DATA);
10232         outb(sr1 | 1<<5, VGA_SR_DATA);
10233         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10234         udelay(300);
10235
10236         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10237         POSTING_READ(vga_reg);
10238 }
10239
10240 static void i915_enable_vga_mem(struct drm_device *dev)
10241 {
10242         /* Enable VGA memory on Intel HD */
10243         if (HAS_PCH_SPLIT(dev)) {
10244                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10245                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10246                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10247                                                    VGA_RSRC_LEGACY_MEM |
10248                                                    VGA_RSRC_NORMAL_IO |
10249                                                    VGA_RSRC_NORMAL_MEM);
10250                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10251         }
10252 }
10253
10254 void i915_disable_vga_mem(struct drm_device *dev)
10255 {
10256         /* Disable VGA memory on Intel HD */
10257         if (HAS_PCH_SPLIT(dev)) {
10258                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10259                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10260                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10261                                                    VGA_RSRC_NORMAL_IO |
10262                                                    VGA_RSRC_NORMAL_MEM);
10263                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10264         }
10265 }
10266
10267 void intel_modeset_init_hw(struct drm_device *dev)
10268 {
10269         intel_prepare_ddi(dev);
10270
10271         intel_init_clock_gating(dev);
10272
10273         mutex_lock(&dev->struct_mutex);
10274         intel_enable_gt_powersave(dev);
10275         mutex_unlock(&dev->struct_mutex);
10276 }
10277
10278 void intel_modeset_suspend_hw(struct drm_device *dev)
10279 {
10280         intel_suspend_hw(dev);
10281 }
10282
10283 void intel_modeset_init(struct drm_device *dev)
10284 {
10285         struct drm_i915_private *dev_priv = dev->dev_private;
10286         int i, j, ret;
10287
10288         drm_mode_config_init(dev);
10289
10290         dev->mode_config.min_width = 0;
10291         dev->mode_config.min_height = 0;
10292
10293         dev->mode_config.preferred_depth = 24;
10294         dev->mode_config.prefer_shadow = 1;
10295
10296         dev->mode_config.funcs = &intel_mode_funcs;
10297
10298         intel_init_quirks(dev);
10299
10300         intel_init_pm(dev);
10301
10302         if (INTEL_INFO(dev)->num_pipes == 0)
10303                 return;
10304
10305         intel_init_display(dev);
10306
10307         if (IS_GEN2(dev)) {
10308                 dev->mode_config.max_width = 2048;
10309                 dev->mode_config.max_height = 2048;
10310         } else if (IS_GEN3(dev)) {
10311                 dev->mode_config.max_width = 4096;
10312                 dev->mode_config.max_height = 4096;
10313         } else {
10314                 dev->mode_config.max_width = 8192;
10315                 dev->mode_config.max_height = 8192;
10316         }
10317         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10318
10319         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10320                       INTEL_INFO(dev)->num_pipes,
10321                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10322
10323         for_each_pipe(i) {
10324                 intel_crtc_init(dev, i);
10325                 for (j = 0; j < dev_priv->num_plane; j++) {
10326                         ret = intel_plane_init(dev, i, j);
10327                         if (ret)
10328                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10329                                               pipe_name(i), sprite_name(i, j), ret);
10330                 }
10331         }
10332
10333         intel_cpu_pll_init(dev);
10334         intel_shared_dpll_init(dev);
10335
10336         /* Just disable it once at startup */
10337         i915_disable_vga(dev);
10338         intel_setup_outputs(dev);
10339
10340         /* Just in case the BIOS is doing something questionable. */
10341         intel_disable_fbc(dev);
10342 }
10343
10344 static void
10345 intel_connector_break_all_links(struct intel_connector *connector)
10346 {
10347         connector->base.dpms = DRM_MODE_DPMS_OFF;
10348         connector->base.encoder = NULL;
10349         connector->encoder->connectors_active = false;
10350         connector->encoder->base.crtc = NULL;
10351 }
10352
10353 static void intel_enable_pipe_a(struct drm_device *dev)
10354 {
10355         struct intel_connector *connector;
10356         struct drm_connector *crt = NULL;
10357         struct intel_load_detect_pipe load_detect_temp;
10358
10359         /* We can't just switch on the pipe A, we need to set things up with a
10360          * proper mode and output configuration. As a gross hack, enable pipe A
10361          * by enabling the load detect pipe once. */
10362         list_for_each_entry(connector,
10363                             &dev->mode_config.connector_list,
10364                             base.head) {
10365                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10366                         crt = &connector->base;
10367                         break;
10368                 }
10369         }
10370
10371         if (!crt)
10372                 return;
10373
10374         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10375                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10376
10377
10378 }
10379
10380 static bool
10381 intel_check_plane_mapping(struct intel_crtc *crtc)
10382 {
10383         struct drm_device *dev = crtc->base.dev;
10384         struct drm_i915_private *dev_priv = dev->dev_private;
10385         u32 reg, val;
10386
10387         if (INTEL_INFO(dev)->num_pipes == 1)
10388                 return true;
10389
10390         reg = DSPCNTR(!crtc->plane);
10391         val = I915_READ(reg);
10392
10393         if ((val & DISPLAY_PLANE_ENABLE) &&
10394             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10395                 return false;
10396
10397         return true;
10398 }
10399
10400 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10401 {
10402         struct drm_device *dev = crtc->base.dev;
10403         struct drm_i915_private *dev_priv = dev->dev_private;
10404         u32 reg;
10405
10406         /* Clear any frame start delays used for debugging left by the BIOS */
10407         reg = PIPECONF(crtc->config.cpu_transcoder);
10408         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10409
10410         /* We need to sanitize the plane -> pipe mapping first because this will
10411          * disable the crtc (and hence change the state) if it is wrong. Note
10412          * that gen4+ has a fixed plane -> pipe mapping.  */
10413         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10414                 struct intel_connector *connector;
10415                 bool plane;
10416
10417                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10418                               crtc->base.base.id);
10419
10420                 /* Pipe has the wrong plane attached and the plane is active.
10421                  * Temporarily change the plane mapping and disable everything
10422                  * ...  */
10423                 plane = crtc->plane;
10424                 crtc->plane = !plane;
10425                 dev_priv->display.crtc_disable(&crtc->base);
10426                 crtc->plane = plane;
10427
10428                 /* ... and break all links. */
10429                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10430                                     base.head) {
10431                         if (connector->encoder->base.crtc != &crtc->base)
10432                                 continue;
10433
10434                         intel_connector_break_all_links(connector);
10435                 }
10436
10437                 WARN_ON(crtc->active);
10438                 crtc->base.enabled = false;
10439         }
10440
10441         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10442             crtc->pipe == PIPE_A && !crtc->active) {
10443                 /* BIOS forgot to enable pipe A, this mostly happens after
10444                  * resume. Force-enable the pipe to fix this, the update_dpms
10445                  * call below we restore the pipe to the right state, but leave
10446                  * the required bits on. */
10447                 intel_enable_pipe_a(dev);
10448         }
10449
10450         /* Adjust the state of the output pipe according to whether we
10451          * have active connectors/encoders. */
10452         intel_crtc_update_dpms(&crtc->base);
10453
10454         if (crtc->active != crtc->base.enabled) {
10455                 struct intel_encoder *encoder;
10456
10457                 /* This can happen either due to bugs in the get_hw_state
10458                  * functions or because the pipe is force-enabled due to the
10459                  * pipe A quirk. */
10460                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10461                               crtc->base.base.id,
10462                               crtc->base.enabled ? "enabled" : "disabled",
10463                               crtc->active ? "enabled" : "disabled");
10464
10465                 crtc->base.enabled = crtc->active;
10466
10467                 /* Because we only establish the connector -> encoder ->
10468                  * crtc links if something is active, this means the
10469                  * crtc is now deactivated. Break the links. connector
10470                  * -> encoder links are only establish when things are
10471                  *  actually up, hence no need to break them. */
10472                 WARN_ON(crtc->active);
10473
10474                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10475                         WARN_ON(encoder->connectors_active);
10476                         encoder->base.crtc = NULL;
10477                 }
10478         }
10479 }
10480
10481 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10482 {
10483         struct intel_connector *connector;
10484         struct drm_device *dev = encoder->base.dev;
10485
10486         /* We need to check both for a crtc link (meaning that the
10487          * encoder is active and trying to read from a pipe) and the
10488          * pipe itself being active. */
10489         bool has_active_crtc = encoder->base.crtc &&
10490                 to_intel_crtc(encoder->base.crtc)->active;
10491
10492         if (encoder->connectors_active && !has_active_crtc) {
10493                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10494                               encoder->base.base.id,
10495                               drm_get_encoder_name(&encoder->base));
10496
10497                 /* Connector is active, but has no active pipe. This is
10498                  * fallout from our resume register restoring. Disable
10499                  * the encoder manually again. */
10500                 if (encoder->base.crtc) {
10501                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10502                                       encoder->base.base.id,
10503                                       drm_get_encoder_name(&encoder->base));
10504                         encoder->disable(encoder);
10505                 }
10506
10507                 /* Inconsistent output/port/pipe state happens presumably due to
10508                  * a bug in one of the get_hw_state functions. Or someplace else
10509                  * in our code, like the register restore mess on resume. Clamp
10510                  * things to off as a safer default. */
10511                 list_for_each_entry(connector,
10512                                     &dev->mode_config.connector_list,
10513                                     base.head) {
10514                         if (connector->encoder != encoder)
10515                                 continue;
10516
10517                         intel_connector_break_all_links(connector);
10518                 }
10519         }
10520         /* Enabled encoders without active connectors will be fixed in
10521          * the crtc fixup. */
10522 }
10523
10524 void i915_redisable_vga(struct drm_device *dev)
10525 {
10526         struct drm_i915_private *dev_priv = dev->dev_private;
10527         u32 vga_reg = i915_vgacntrl_reg(dev);
10528
10529         /* This function can be called both from intel_modeset_setup_hw_state or
10530          * at a very early point in our resume sequence, where the power well
10531          * structures are not yet restored. Since this function is at a very
10532          * paranoid "someone might have enabled VGA while we were not looking"
10533          * level, just check if the power well is enabled instead of trying to
10534          * follow the "don't touch the power well if we don't need it" policy
10535          * the rest of the driver uses. */
10536         if (HAS_POWER_WELL(dev) &&
10537             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10538                 return;
10539
10540         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10541                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10542                 i915_disable_vga(dev);
10543                 i915_disable_vga_mem(dev);
10544         }
10545 }
10546
10547 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10548 {
10549         struct drm_i915_private *dev_priv = dev->dev_private;
10550         enum pipe pipe;
10551         struct intel_crtc *crtc;
10552         struct intel_encoder *encoder;
10553         struct intel_connector *connector;
10554         int i;
10555
10556         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10557                             base.head) {
10558                 memset(&crtc->config, 0, sizeof(crtc->config));
10559
10560                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10561                                                                  &crtc->config);
10562
10563                 crtc->base.enabled = crtc->active;
10564
10565                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10566                               crtc->base.base.id,
10567                               crtc->active ? "enabled" : "disabled");
10568         }
10569
10570         /* FIXME: Smash this into the new shared dpll infrastructure. */
10571         if (HAS_DDI(dev))
10572                 intel_ddi_setup_hw_pll_state(dev);
10573
10574         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10575                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10576
10577                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10578                 pll->active = 0;
10579                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10580                                     base.head) {
10581                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10582                                 pll->active++;
10583                 }
10584                 pll->refcount = pll->active;
10585
10586                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10587                               pll->name, pll->refcount, pll->on);
10588         }
10589
10590         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10591                             base.head) {
10592                 pipe = 0;
10593
10594                 if (encoder->get_hw_state(encoder, &pipe)) {
10595                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10596                         encoder->base.crtc = &crtc->base;
10597                         if (encoder->get_config)
10598                                 encoder->get_config(encoder, &crtc->config);
10599                 } else {
10600                         encoder->base.crtc = NULL;
10601                 }
10602
10603                 encoder->connectors_active = false;
10604                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10605                               encoder->base.base.id,
10606                               drm_get_encoder_name(&encoder->base),
10607                               encoder->base.crtc ? "enabled" : "disabled",
10608                               pipe);
10609         }
10610
10611         list_for_each_entry(connector, &dev->mode_config.connector_list,
10612                             base.head) {
10613                 if (connector->get_hw_state(connector)) {
10614                         connector->base.dpms = DRM_MODE_DPMS_ON;
10615                         connector->encoder->connectors_active = true;
10616                         connector->base.encoder = &connector->encoder->base;
10617                 } else {
10618                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10619                         connector->base.encoder = NULL;
10620                 }
10621                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10622                               connector->base.base.id,
10623                               drm_get_connector_name(&connector->base),
10624                               connector->base.encoder ? "enabled" : "disabled");
10625         }
10626 }
10627
10628 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10629  * and i915 state tracking structures. */
10630 void intel_modeset_setup_hw_state(struct drm_device *dev,
10631                                   bool force_restore)
10632 {
10633         struct drm_i915_private *dev_priv = dev->dev_private;
10634         enum pipe pipe;
10635         struct drm_plane *plane;
10636         struct intel_crtc *crtc;
10637         struct intel_encoder *encoder;
10638         int i;
10639
10640         intel_modeset_readout_hw_state(dev);
10641
10642         /*
10643          * Now that we have the config, copy it to each CRTC struct
10644          * Note that this could go away if we move to using crtc_config
10645          * checking everywhere.
10646          */
10647         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10648                             base.head) {
10649                 if (crtc->active && i915_fastboot) {
10650                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10651
10652                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10653                                       crtc->base.base.id);
10654                         drm_mode_debug_printmodeline(&crtc->base.mode);
10655                 }
10656         }
10657
10658         /* HW state is read out, now we need to sanitize this mess. */
10659         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10660                             base.head) {
10661                 intel_sanitize_encoder(encoder);
10662         }
10663
10664         for_each_pipe(pipe) {
10665                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10666                 intel_sanitize_crtc(crtc);
10667                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10668         }
10669
10670         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10671                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10672
10673                 if (!pll->on || pll->active)
10674                         continue;
10675
10676                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10677
10678                 pll->disable(dev_priv, pll);
10679                 pll->on = false;
10680         }
10681
10682         if (force_restore) {
10683                 /*
10684                  * We need to use raw interfaces for restoring state to avoid
10685                  * checking (bogus) intermediate states.
10686                  */
10687                 for_each_pipe(pipe) {
10688                         struct drm_crtc *crtc =
10689                                 dev_priv->pipe_to_crtc_mapping[pipe];
10690
10691                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10692                                          crtc->fb);
10693                 }
10694                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10695                         intel_plane_restore(plane);
10696
10697                 i915_redisable_vga(dev);
10698         } else {
10699                 intel_modeset_update_staged_output_state(dev);
10700         }
10701
10702         intel_modeset_check_state(dev);
10703
10704         drm_mode_config_reset(dev);
10705 }
10706
10707 void intel_modeset_gem_init(struct drm_device *dev)
10708 {
10709         intel_modeset_init_hw(dev);
10710
10711         intel_setup_overlay(dev);
10712
10713         intel_modeset_setup_hw_state(dev, false);
10714 }
10715
10716 void intel_modeset_cleanup(struct drm_device *dev)
10717 {
10718         struct drm_i915_private *dev_priv = dev->dev_private;
10719         struct drm_crtc *crtc;
10720
10721         /*
10722          * Interrupts and polling as the first thing to avoid creating havoc.
10723          * Too much stuff here (turning of rps, connectors, ...) would
10724          * experience fancy races otherwise.
10725          */
10726         drm_irq_uninstall(dev);
10727         cancel_work_sync(&dev_priv->hotplug_work);
10728         /*
10729          * Due to the hpd irq storm handling the hotplug work can re-arm the
10730          * poll handlers. Hence disable polling after hpd handling is shut down.
10731          */
10732         drm_kms_helper_poll_fini(dev);
10733
10734         mutex_lock(&dev->struct_mutex);
10735
10736         intel_unregister_dsm_handler();
10737
10738         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10739                 /* Skip inactive CRTCs */
10740                 if (!crtc->fb)
10741                         continue;
10742
10743                 intel_increase_pllclock(crtc);
10744         }
10745
10746         intel_disable_fbc(dev);
10747
10748         i915_enable_vga_mem(dev);
10749
10750         intel_disable_gt_powersave(dev);
10751
10752         ironlake_teardown_rc6(dev);
10753
10754         mutex_unlock(&dev->struct_mutex);
10755
10756         /* flush any delayed tasks or pending work */
10757         flush_scheduled_work();
10758
10759         /* destroy backlight, if any, before the connectors */
10760         intel_panel_destroy_backlight(dev);
10761
10762         drm_mode_config_cleanup(dev);
10763
10764         intel_cleanup_overlay(dev);
10765 }
10766
10767 /*
10768  * Return which encoder is currently attached for connector.
10769  */
10770 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10771 {
10772         return &intel_attached_encoder(connector)->base;
10773 }
10774
10775 void intel_connector_attach_encoder(struct intel_connector *connector,
10776                                     struct intel_encoder *encoder)
10777 {
10778         connector->encoder = encoder;
10779         drm_mode_connector_attach_encoder(&connector->base,
10780                                           &encoder->base);
10781 }
10782
10783 /*
10784  * set vga decode state - true == enable VGA decode
10785  */
10786 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10787 {
10788         struct drm_i915_private *dev_priv = dev->dev_private;
10789         u16 gmch_ctrl;
10790
10791         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10792         if (state)
10793                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10794         else
10795                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10796         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10797         return 0;
10798 }
10799
10800 struct intel_display_error_state {
10801
10802         u32 power_well_driver;
10803
10804         int num_transcoders;
10805
10806         struct intel_cursor_error_state {
10807                 u32 control;
10808                 u32 position;
10809                 u32 base;
10810                 u32 size;
10811         } cursor[I915_MAX_PIPES];
10812
10813         struct intel_pipe_error_state {
10814                 u32 source;
10815         } pipe[I915_MAX_PIPES];
10816
10817         struct intel_plane_error_state {
10818                 u32 control;
10819                 u32 stride;
10820                 u32 size;
10821                 u32 pos;
10822                 u32 addr;
10823                 u32 surface;
10824                 u32 tile_offset;
10825         } plane[I915_MAX_PIPES];
10826
10827         struct intel_transcoder_error_state {
10828                 enum transcoder cpu_transcoder;
10829
10830                 u32 conf;
10831
10832                 u32 htotal;
10833                 u32 hblank;
10834                 u32 hsync;
10835                 u32 vtotal;
10836                 u32 vblank;
10837                 u32 vsync;
10838         } transcoder[4];
10839 };
10840
10841 struct intel_display_error_state *
10842 intel_display_capture_error_state(struct drm_device *dev)
10843 {
10844         drm_i915_private_t *dev_priv = dev->dev_private;
10845         struct intel_display_error_state *error;
10846         int transcoders[] = {
10847                 TRANSCODER_A,
10848                 TRANSCODER_B,
10849                 TRANSCODER_C,
10850                 TRANSCODER_EDP,
10851         };
10852         int i;
10853
10854         if (INTEL_INFO(dev)->num_pipes == 0)
10855                 return NULL;
10856
10857         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10858         if (error == NULL)
10859                 return NULL;
10860
10861         if (HAS_POWER_WELL(dev))
10862                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10863
10864         for_each_pipe(i) {
10865                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10866                         error->cursor[i].control = I915_READ(CURCNTR(i));
10867                         error->cursor[i].position = I915_READ(CURPOS(i));
10868                         error->cursor[i].base = I915_READ(CURBASE(i));
10869                 } else {
10870                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10871                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10872                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10873                 }
10874
10875                 error->plane[i].control = I915_READ(DSPCNTR(i));
10876                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10877                 if (INTEL_INFO(dev)->gen <= 3) {
10878                         error->plane[i].size = I915_READ(DSPSIZE(i));
10879                         error->plane[i].pos = I915_READ(DSPPOS(i));
10880                 }
10881                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10882                         error->plane[i].addr = I915_READ(DSPADDR(i));
10883                 if (INTEL_INFO(dev)->gen >= 4) {
10884                         error->plane[i].surface = I915_READ(DSPSURF(i));
10885                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10886                 }
10887
10888                 error->pipe[i].source = I915_READ(PIPESRC(i));
10889         }
10890
10891         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10892         if (HAS_DDI(dev_priv->dev))
10893                 error->num_transcoders++; /* Account for eDP. */
10894
10895         for (i = 0; i < error->num_transcoders; i++) {
10896                 enum transcoder cpu_transcoder = transcoders[i];
10897
10898                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10899
10900                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10901                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10902                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10903                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10904                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10905                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10906                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10907         }
10908
10909         /* In the code above we read the registers without checking if the power
10910          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10911          * prevent the next I915_WRITE from detecting it and printing an error
10912          * message. */
10913         intel_uncore_clear_errors(dev);
10914
10915         return error;
10916 }
10917
10918 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10919
10920 void
10921 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10922                                 struct drm_device *dev,
10923                                 struct intel_display_error_state *error)
10924 {
10925         int i;
10926
10927         if (!error)
10928                 return;
10929
10930         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10931         if (HAS_POWER_WELL(dev))
10932                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10933                            error->power_well_driver);
10934         for_each_pipe(i) {
10935                 err_printf(m, "Pipe [%d]:\n", i);
10936                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10937
10938                 err_printf(m, "Plane [%d]:\n", i);
10939                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10940                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10941                 if (INTEL_INFO(dev)->gen <= 3) {
10942                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10943                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10944                 }
10945                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10946                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10947                 if (INTEL_INFO(dev)->gen >= 4) {
10948                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10949                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10950                 }
10951
10952                 err_printf(m, "Cursor [%d]:\n", i);
10953                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10954                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10955                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10956         }
10957
10958         for (i = 0; i < error->num_transcoders; i++) {
10959                 err_printf(m, "  CPU transcoder: %c\n",
10960                            transcoder_name(error->transcoder[i].cpu_transcoder));
10961                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10962                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10963                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10964                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10965                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10966                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10967                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10968         }
10969 }