drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_dmabuf.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct drm_device *dev,
 101                                   struct intel_framebuffer *ifb,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd,
 103                                   struct drm_i915_gem_object *obj);
 104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 108                                          struct intel_link_m_n *m_n,
 109                                          struct intel_link_m_n *m2_n2);
 110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 113 static void vlv_prepare_pll(struct intel_crtc *crtc,
 114                             const struct intel_crtc_state *pipe_config);
 115 static void chv_prepare_pll(struct intel_crtc *crtc,
 116                             const struct intel_crtc_state *pipe_config);
 117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 120         struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_device *dev,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 617             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 622                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 623                         INTELPllInvalid("p out of range\n");
 624                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 625                         INTELPllInvalid("m out of range\n");
 626         }
 627
 628         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 629                 INTELPllInvalid("vco out of range\n");
 630         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 631          * connector, etc., rather than just a single range.
 632          */
 633         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 634                 INTELPllInvalid("dot out of range\n");
 635
 636         return true;
 637 }
 638
 639 static int
 640 i9xx_select_p2_div(const struct intel_limit *limit,
 641                    const struct intel_crtc_state *crtc_state,
 642                    int target)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645
 646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 647                 /*
 648                  * For LVDS just rely on its current settings for dual-channel.
 649                  * We haven't figured out how to reliably set up different
 650                  * single/dual channel state, if we even can.
 651                  */
 652                 if (intel_is_dual_link_lvds(dev))
 653                         return limit->p2.p2_fast;
 654                 else
 655                         return limit->p2.p2_slow;
 656         } else {
 657                 if (target < limit->p2.dot_limit)
 658                         return limit->p2.p2_slow;
 659                 else
 660                         return limit->p2.p2_fast;
 661         }
 662 }
 663
 664 /*
 665  * Returns a set of divisors for the desired target clock with the given
 666  * refclk, or FALSE.  The returned values represent the clock equation:
 667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 668  *
 669  * Target and reference clocks are specified in kHz.
 670  *
 671  * If match_clock is provided, then best_clock P divider must match the P
 672  * divider from @match_clock used for LVDS downclocking.
 673  */
 674 static bool
 675 i9xx_find_best_dpll(const struct intel_limit *limit,
 676                     struct intel_crtc_state *crtc_state,
 677                     int target, int refclk, struct dpll *match_clock,
 678                     struct dpll *best_clock)
 679 {
 680         struct drm_device *dev = crtc_state->base.crtc->dev;
 681         struct dpll clock;
 682         int err = target;
 683
 684         memset(best_clock, 0, sizeof(*best_clock));
 685
 686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 687
 688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 689              clock.m1++) {
 690                 for (clock.m2 = limit->m2.min;
 691                      clock.m2 <= limit->m2.max; clock.m2++) {
 692                         if (clock.m2 >= clock.m1)
 693                                 break;
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         i9xx_calc_dpll_params(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 /*
 722  * Returns a set of divisors for the desired target clock with the given
 723  * refclk, or FALSE.  The returned values represent the clock equation:
 724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 725  *
 726  * Target and reference clocks are specified in kHz.
 727  *
 728  * If match_clock is provided, then best_clock P divider must match the P
 729  * divider from @match_clock used for LVDS downclocking.
 730  */
 731 static bool
 732 pnv_find_best_dpll(const struct intel_limit *limit,
 733                    struct intel_crtc_state *crtc_state,
 734                    int target, int refclk, struct dpll *match_clock,
 735                    struct dpll *best_clock)
 736 {
 737         struct drm_device *dev = crtc_state->base.crtc->dev;
 738         struct dpll clock;
 739         int err = target;
 740
 741         memset(best_clock, 0, sizeof(*best_clock));
 742
 743         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 744
 745         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 746              clock.m1++) {
 747                 for (clock.m2 = limit->m2.min;
 748                      clock.m2 <= limit->m2.max; clock.m2++) {
 749                         for (clock.n = limit->n.min;
 750                              clock.n <= limit->n.max; clock.n++) {
 751                                 for (clock.p1 = limit->p1.min;
 752                                         clock.p1 <= limit->p1.max; clock.p1++) {
 753                                         int this_err;
 754
 755                                         pnv_calc_dpll_params(refclk, &clock);
 756                                         if (!intel_PLL_is_valid(dev, limit,
 757                                                                 &clock))
 758                                                 continue;
 759                                         if (match_clock &&
 760                                             clock.p != match_clock->p)
 761                                                 continue;
 762
 763                                         this_err = abs(clock.dot - target);
 764                                         if (this_err < err) {
 765                                                 *best_clock = clock;
 766                                                 err = this_err;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772
 773         return (err != target);
 774 }
 775
 776 /*
 777  * Returns a set of divisors for the desired target clock with the given
 778  * refclk, or FALSE.  The returned values represent the clock equation:
 779  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 780  *
 781  * Target and reference clocks are specified in kHz.
 782  *
 783  * If match_clock is provided, then best_clock P divider must match the P
 784  * divider from @match_clock used for LVDS downclocking.
 785  */
 786 static bool
 787 g4x_find_best_dpll(const struct intel_limit *limit,
 788                    struct intel_crtc_state *crtc_state,
 789                    int target, int refclk, struct dpll *match_clock,
 790                    struct dpll *best_clock)
 791 {
 792         struct drm_device *dev = crtc_state->base.crtc->dev;
 793         struct dpll clock;
 794         int max_n;
 795         bool found = false;
 796         /* approximately equals target * 0.00585 */
 797         int err_most = (target >> 8) + (target >> 9);
 798
 799         memset(best_clock, 0, sizeof(*best_clock));
 800
 801         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 802
 803         max_n = limit->n.max;
 804         /* based on hardware requirement, prefer smaller n to precision */
 805         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 806                 /* based on hardware requirement, prefere larger m1,m2 */
 807                 for (clock.m1 = limit->m1.max;
 808                      clock.m1 >= limit->m1.min; clock.m1--) {
 809                         for (clock.m2 = limit->m2.max;
 810                              clock.m2 >= limit->m2.min; clock.m2--) {
 811                                 for (clock.p1 = limit->p1.max;
 812                                      clock.p1 >= limit->p1.min; clock.p1--) {
 813                                         int this_err;
 814
 815                                         i9xx_calc_dpll_params(refclk, &clock);
 816                                         if (!intel_PLL_is_valid(dev, limit,
 817                                                                 &clock))
 818                                                 continue;
 819
 820                                         this_err = abs(clock.dot - target);
 821                                         if (this_err < err_most) {
 822                                                 *best_clock = clock;
 823                                                 err_most = this_err;
 824                                                 max_n = clock.n;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831         return found;
 832 }
 833
 834 /*
 835  * Check if the calculated PLL configuration is more optimal compared to the
 836  * best configuration and error found so far. Return the calculated error.
 837  */
 838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 839                                const struct dpll *calculated_clock,
 840                                const struct dpll *best_clock,
 841                                unsigned int best_error_ppm,
 842                                unsigned int *error_ppm)
 843 {
 844         /*
 845          * For CHV ignore the error and consider only the P value.
 846          * Prefer a bigger P value based on HW requirements.
 847          */
 848         if (IS_CHERRYVIEW(dev)) {
 849                 *error_ppm = 0;
 850
 851                 return calculated_clock->p > best_clock->p;
 852         }
 853
 854         if (WARN_ON_ONCE(!target_freq))
 855                 return false;
 856
 857         *error_ppm = div_u64(1000000ULL *
 858                                 abs(target_freq - calculated_clock->dot),
 859                              target_freq);
 860         /*
 861          * Prefer a better P value over a better (smaller) error if the error
 862          * is small. Ensure this preference for future configurations too by
 863          * setting the error to 0.
 864          */
 865         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 866                 *error_ppm = 0;
 867
 868                 return true;
 869         }
 870
 871         return *error_ppm + 10 < best_error_ppm;
 872 }
 873
 874 /*
 875  * Returns a set of divisors for the desired target clock with the given
 876  * refclk, or FALSE.  The returned values represent the clock equation:
 877  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 878  */
 879 static bool
 880 vlv_find_best_dpll(const struct intel_limit *limit,
 881                    struct intel_crtc_state *crtc_state,
 882                    int target, int refclk, struct dpll *match_clock,
 883                    struct dpll *best_clock)
 884 {
 885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 886         struct drm_device *dev = crtc->base.dev;
 887         struct dpll clock;
 888         unsigned int bestppm = 1000000;
 889         /* min update 19.2 MHz */
 890         int max_n = min(limit->n.max, refclk / 19200);
 891         bool found = false;
 892
 893         target *= 5; /* fast clock */
 894
 895         memset(best_clock, 0, sizeof(*best_clock));
 896
 897         /* based on hardware requirement, prefer smaller n to precision */
 898         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 899                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 900                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 901                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 902                                 clock.p = clock.p1 * clock.p2;
 903                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 904                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 905                                         unsigned int ppm;
 906
 907                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 908                                                                      refclk * clock.m1);
 909
 910                                         vlv_calc_dpll_params(refclk, &clock);
 911
 912                                         if (!intel_PLL_is_valid(dev, limit,
 913                                                                 &clock))
 914                                                 continue;
 915
 916                                         if (!vlv_PLL_is_optimal(dev, target,
 917                                                                 &clock,
 918                                                                 best_clock,
 919                                                                 bestppm, &ppm))
 920                                                 continue;
 921
 922                                         *best_clock = clock;
 923                                         bestppm = ppm;
 924                                         found = true;
 925                                 }
 926                         }
 927                 }
 928         }
 929
 930         return found;
 931 }
 932
 933 /*
 934  * Returns a set of divisors for the desired target clock with the given
 935  * refclk, or FALSE.  The returned values represent the clock equation:
 936  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 937  */
 938 static bool
 939 chv_find_best_dpll(const struct intel_limit *limit,
 940                    struct intel_crtc_state *crtc_state,
 941                    int target, int refclk, struct dpll *match_clock,
 942                    struct dpll *best_clock)
 943 {
 944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 945         struct drm_device *dev = crtc->base.dev;
 946         unsigned int best_error_ppm;
 947         struct dpll clock;
 948         uint64_t m2;
 949         int found = false;
 950
 951         memset(best_clock, 0, sizeof(*best_clock));
 952         best_error_ppm = 1000000;
 953
 954         /*
 955          * Based on hardware doc, the n always set to 1, and m1 always
 956          * set to 2.  If requires to support 200Mhz refclk, we need to
 957          * revisit this because n may not 1 anymore.
 958          */
 959         clock.n = 1, clock.m1 = 2;
 960         target *= 5;    /* fast clock */
 961
 962         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 963                 for (clock.p2 = limit->p2.p2_fast;
 964                                 clock.p2 >= limit->p2.p2_slow;
 965                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 966                         unsigned int error_ppm;
 967
 968                         clock.p = clock.p1 * clock.p2;
 969
 970                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 971                                         clock.n) << 22, refclk * clock.m1);
 972
 973                         if (m2 > INT_MAX/clock.m1)
 974                                 continue;
 975
 976                         clock.m2 = m2;
 977
 978                         chv_calc_dpll_params(refclk, &clock);
 979
 980                         if (!intel_PLL_is_valid(dev, limit, &clock))
 981                                 continue;
 982
 983                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 984                                                 best_error_ppm, &error_ppm))
 985                                 continue;
 986
 987                         *best_clock = clock;
 988                         best_error_ppm = error_ppm;
 989                         found = true;
 990                 }
 991         }
 992
 993         return found;
 994 }
 995
 996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 997                         struct dpll *best_clock)
 998 {
 999         int refclk = 100000;
1000         const struct intel_limit *limit = &intel_limits_bxt;
1001
1002         return chv_find_best_dpll(limit, crtc_state,
1003                                   target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010         /* Be paranoid as we can arrive here with only partial
1011          * state retrieved from the hardware during setup.
1012          *
1013          * We can ditch the adjusted_mode.crtc_clock check as soon
1014          * as Haswell has gained clock readout/fastboot support.
1015          *
1016          * We can ditch the crtc->primary->fb check as soon as we can
1017          * properly reconstruct framebuffers.
1018          *
1019          * FIXME: The intel_crtc->active here should be switched to
1020          * crtc->state->active once we have proper CRTC states wired up
1021          * for atomic.
1022          */
1023         return intel_crtc->active && crtc->primary->state->fb &&
1024                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe)
1029 {
1030         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033         return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(dev);
1039         i915_reg_t reg = PIPEDSL(pipe);
1040         u32 line1, line2;
1041         u32 line_mask;
1042
1043         if (IS_GEN2(dev))
1044                 line_mask = DSL_LINEMASK_GEN2;
1045         else
1046                 line_mask = DSL_LINEMASK_GEN3;
1047
1048         line1 = I915_READ(reg) & line_mask;
1049         msleep(5);
1050         line2 = I915_READ(reg) & line_mask;
1051
1052         return line1 == line2;
1053 }
1054
1055 /*
1056  * intel_wait_for_pipe_off - wait for pipe to turn off
1057  * @crtc: crtc whose pipe to wait for
1058  *
1059  * After disabling a pipe, we can't wait for vblank in the usual way,
1060  * spinning on the vblank interrupt status bit, since we won't actually
1061  * see an interrupt when the pipe is disabled.
1062  *
1063  * On Gen4 and above:
1064  *   wait for the pipe register state bit to turn off
1065  *
1066  * Otherwise:
1067  *   wait for the display line value to settle (it usually
1068  *   ends up stopping at the start of the next frame).
1069  *
1070  */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->base.dev;
1074         struct drm_i915_private *dev_priv = to_i915(dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                            enum pipe pipe)
1192 {
1193         struct drm_device *dev = &dev_priv->drm;
1194         i915_reg_t pp_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198
1199         if (WARN_ON(HAS_DDI(dev)))
1200                 return;
1201
1202         if (HAS_PCH_SPLIT(dev)) {
1203                 u32 port_sel;
1204
1205                 pp_reg = PP_CONTROL(0);
1206                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210                         panel_pipe = PIPE_B;
1211                 /* XXX: else fix for eDP */
1212         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213                 /* presumably write lock depends on pipe, not port select */
1214                 pp_reg = PP_CONTROL(pipe);
1215                 panel_pipe = pipe;
1216         } else {
1217                 pp_reg = PP_CONTROL(0);
1218                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220         }
1221
1222         val = I915_READ(pp_reg);
1223         if (!(val & PANEL_POWER_ON) ||
1224             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225                 locked = false;
1226
1227         I915_STATE_WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233                           enum pipe pipe, bool state)
1234 {
1235         struct drm_device *dev = &dev_priv->drm;
1236         bool cur_state;
1237
1238         if (IS_845G(dev) || IS_I865G(dev))
1239                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240         else
1241                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243         I915_STATE_WARN(cur_state != state,
1244              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245                         pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251                  enum pipe pipe, bool state)
1252 {
1253         bool cur_state;
1254         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255                                                                       pipe);
1256         enum intel_display_power_domain power_domain;
1257
1258         /* if we need the pipe quirk it must be always on */
1259         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261                 state = true;
1262
1263         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266                 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268                 intel_display_power_put(dev_priv, power_domain);
1269         } else {
1270                 cur_state = false;
1271         }
1272
1273         I915_STATE_WARN(cur_state != state,
1274              "pipe %c assertion failure (expected %s, current %s)\n",
1275                         pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279                          enum plane plane, bool state)
1280 {
1281         u32 val;
1282         bool cur_state;
1283
1284         val = I915_READ(DSPCNTR(plane));
1285         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286         I915_STATE_WARN(cur_state != state,
1287              "plane %c assertion failure (expected %s, current %s)\n",
1288                         plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295                                    enum pipe pipe)
1296 {
1297         struct drm_device *dev = &dev_priv->drm;
1298         int i;
1299
1300         /* Primary planes are fixed to pipes on gen4+ */
1301         if (INTEL_INFO(dev)->gen >= 4) {
1302                 u32 val = I915_READ(DSPCNTR(pipe));
1303                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304                      "plane %c assertion failure, should be disabled but not\n",
1305                      plane_name(pipe));
1306                 return;
1307         }
1308
1309         /* Need to check both planes against the pipe */
1310         for_each_pipe(dev_priv, i) {
1311                 u32 val = I915_READ(DSPCNTR(i));
1312                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313                         DISPPLANE_SEL_PIPE_SHIFT;
1314                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316                      plane_name(i), pipe_name(pipe));
1317         }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321                                     enum pipe pipe)
1322 {
1323         struct drm_device *dev = &dev_priv->drm;
1324         int sprite;
1325
1326         if (INTEL_INFO(dev)->gen >= 9) {
1327                 for_each_sprite(dev_priv, pipe, sprite) {
1328                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331                              sprite, pipe_name(pipe));
1332                 }
1333         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334                 for_each_sprite(dev_priv, pipe, sprite) {
1335                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1336                         I915_STATE_WARN(val & SP_ENABLE,
1337                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338                              sprite_name(pipe, sprite), pipe_name(pipe));
1339                 }
1340         } else if (INTEL_INFO(dev)->gen >= 7) {
1341                 u32 val = I915_READ(SPRCTL(pipe));
1342                 I915_STATE_WARN(val & SPRITE_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         } else if (INTEL_INFO(dev)->gen >= 5) {
1346                 u32 val = I915_READ(DVSCNTR(pipe));
1347                 I915_STATE_WARN(val & DVS_ENABLE,
1348                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349                      plane_name(pipe), pipe_name(pipe));
1350         }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356                 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         u32 val;
1363         bool enabled;
1364
1365         val = I915_READ(PCH_TRANSCONF(pipe));
1366         enabled = !!(val & TRANS_ENABLE);
1367         I915_STATE_WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377
1378         if (HAS_PCH_CPT(dev_priv)) {
1379                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381                         return false;
1382         } else if (IS_CHERRYVIEW(dev_priv)) {
1383                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & SDVO_ENABLE) == 0)
1396                 return false;
1397
1398         if (HAS_PCH_CPT(dev_priv)) {
1399                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400                         return false;
1401         } else if (IS_CHERRYVIEW(dev_priv)) {
1402                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403                         return false;
1404         } else {
1405                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406                         return false;
1407         }
1408         return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412                               enum pipe pipe, u32 val)
1413 {
1414         if ((val & LVDS_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419                         return false;
1420         } else {
1421                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422                         return false;
1423         }
1424         return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428                               enum pipe pipe, u32 val)
1429 {
1430         if ((val & ADPA_DAC_ENABLE) == 0)
1431                 return false;
1432         if (HAS_PCH_CPT(dev_priv)) {
1433                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434                         return false;
1435         } else {
1436                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437                         return false;
1438         }
1439         return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443                                    enum pipe pipe, i915_reg_t reg,
1444                                    u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, i915_reg_t reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         u32 val;
1473
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         val = I915_READ(PCH_ADPA);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         val = I915_READ(PCH_LVDS);
1484         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494                             const struct intel_crtc_state *pipe_config)
1495 {
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         enum pipe pipe = crtc->pipe;
1498
1499         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500         POSTING_READ(DPLL(pipe));
1501         udelay(150);
1502
1503         if (intel_wait_for_register(dev_priv,
1504                                     DPLL(pipe),
1505                                     DPLL_LOCK_VLV,
1506                                     DPLL_LOCK_VLV,
1507                                     1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         enum pipe pipe = crtc->pipe;
1516
1517         assert_pipe_disabled(dev_priv, pipe);
1518
1519         /* PLL is protected by panel, make sure we can write it */
1520         assert_panel_unlocked(dev_priv, pipe);
1521
1522         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523                 _vlv_enable_pll(crtc, pipe_config);
1524
1525         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526         POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531                             const struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534         enum pipe pipe = crtc->pipe;
1535         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536         u32 tmp;
1537
1538         mutex_lock(&dev_priv->sb_lock);
1539
1540         /* Enable back the 10bit clock to display controller */
1541         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542         tmp |= DPIO_DCLKP_EN;
1543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545         mutex_unlock(&dev_priv->sb_lock);
1546
1547         /*
1548          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549          */
1550         udelay(1);
1551
1552         /* Enable PLL */
1553         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555         /* Check PLL is locked */
1556         if (intel_wait_for_register(dev_priv,
1557                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558                                     1))
1559                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563                            const struct intel_crtc_state *pipe_config)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567
1568         assert_pipe_disabled(dev_priv, pipe);
1569
1570         /* PLL is protected by panel, make sure we can write it */
1571         assert_panel_unlocked(dev_priv, pipe);
1572
1573         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574                 _chv_enable_pll(crtc, pipe_config);
1575
1576         if (pipe != PIPE_A) {
1577                 /*
1578                  * WaPixelRepeatModeFixForC0:chv
1579                  *
1580                  * DPLLCMD is AWOL. Use chicken bits to propagate
1581                  * the value from DPLLBMD to either pipe B or C.
1582                  */
1583                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585                 I915_WRITE(CBR4_VLV, 0);
1586                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588                 /*
1589                  * DPLLB VGA mode also seems to cause problems.
1590                  * We should always have it disabled.
1591                  */
1592                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593         } else {
1594                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595                 POSTING_READ(DPLL_MD(pipe));
1596         }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601         struct intel_crtc *crtc;
1602         int count = 0;
1603
1604         for_each_intel_crtc(dev, crtc) {
1605                 count += crtc->base.state->active &&
1606                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607         }
1608
1609         return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->base.dev;
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         i915_reg_t reg = DPLL(crtc->pipe);
1617         u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619         assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         /* Enable DVO 2x clock on both PLLs if necessary */
1626         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627                 /*
1628                  * It appears to be important that we don't enable this
1629                  * for the current pipe before otherwise configuring the
1630                  * PLL. No idea how this should be handled if multiple
1631                  * DVO outputs are enabled simultaneosly.
1632                  */
1633                 dpll |= DPLL_DVO_2X_MODE;
1634                 I915_WRITE(DPLL(!crtc->pipe),
1635                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636         }
1637
1638         /*
1639          * Apparently we need to have VGA mode enabled prior to changing
1640          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641          * dividers, even though the register value does change.
1642          */
1643         I915_WRITE(reg, 0);
1644
1645         I915_WRITE(reg, dpll);
1646
1647         /* Wait for the clocks to stabilize. */
1648         POSTING_READ(reg);
1649         udelay(150);
1650
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 I915_WRITE(DPLL_MD(crtc->pipe),
1653                            crtc->config->dpll_hw_state.dpll_md);
1654         } else {
1655                 /* The pixel multiplier can only be updated once the
1656                  * DPLL is enabled and the clocks are stable.
1657                  *
1658                  * So write it again.
1659                  */
1660                 I915_WRITE(reg, dpll);
1661         }
1662
1663         /* We do this three times for luck */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676  * i9xx_disable_pll - disable a PLL
1677  * @dev_priv: i915 private structure
1678  * @pipe: pipe PLL to disable
1679  *
1680  * Disable the PLL for @pipe, making sure the pipe is off first.
1681  *
1682  * Note!  This is for pre-ILK only.
1683  */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         enum pipe pipe = crtc->pipe;
1689
1690         /* Disable DVO 2x clock on both PLLs if necessary */
1691         if (IS_I830(dev) &&
1692             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693             !intel_num_dvo_pipes(dev)) {
1694                 I915_WRITE(DPLL(PIPE_B),
1695                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696                 I915_WRITE(DPLL(PIPE_A),
1697                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698         }
1699
1700         /* Don't disable pipe or pipe PLLs if needed */
1701         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703                 return;
1704
1705         /* Make sure the pipe isn't still relying on us */
1706         assert_pipe_disabled(dev_priv, pipe);
1707
1708         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709         POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         u32 val;
1715
1716         /* Make sure the pipe isn't still relying on us */
1717         assert_pipe_disabled(dev_priv, pipe);
1718
1719         val = DPLL_INTEGRATED_REF_CLK_VLV |
1720                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721         if (pipe != PIPE_A)
1722                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731         u32 val;
1732
1733         /* Make sure the pipe isn't still relying on us */
1734         assert_pipe_disabled(dev_priv, pipe);
1735
1736         val = DPLL_SSC_REF_CLK_CHV |
1737                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738         if (pipe != PIPE_A)
1739                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741         I915_WRITE(DPLL(pipe), val);
1742         POSTING_READ(DPLL(pipe));
1743
1744         mutex_lock(&dev_priv->sb_lock);
1745
1746         /* Disable 10bit clock to display controller */
1747         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748         val &= ~DPIO_DCLKP_EN;
1749         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751         mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755                          struct intel_digital_port *dport,
1756                          unsigned int expected_mask)
1757 {
1758         u32 port_mask;
1759         i915_reg_t dpll_reg;
1760
1761         switch (dport->port) {
1762         case PORT_B:
1763                 port_mask = DPLL_PORTB_READY_MASK;
1764                 dpll_reg = DPLL(0);
1765                 break;
1766         case PORT_C:
1767                 port_mask = DPLL_PORTC_READY_MASK;
1768                 dpll_reg = DPLL(0);
1769                 expected_mask <<= 4;
1770                 break;
1771         case PORT_D:
1772                 port_mask = DPLL_PORTD_READY_MASK;
1773                 dpll_reg = DPIO_PHY_STATUS;
1774                 break;
1775         default:
1776                 BUG();
1777         }
1778
1779         if (intel_wait_for_register(dev_priv,
1780                                     dpll_reg, port_mask, expected_mask,
1781                                     1000))
1782                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787                                            enum pipe pipe)
1788 {
1789         struct drm_device *dev = &dev_priv->drm;
1790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792         i915_reg_t reg;
1793         uint32_t val, pipeconf_val;
1794
1795         /* Make sure PCH DPLL is enabled */
1796         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798         /* FDI must be feeding us bits for PCH ports */
1799         assert_fdi_tx_enabled(dev_priv, pipe);
1800         assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802         if (HAS_PCH_CPT(dev)) {
1803                 /* Workaround: Set the timing override bit before enabling the
1804                  * pch transcoder. */
1805                 reg = TRANS_CHICKEN2(pipe);
1806                 val = I915_READ(reg);
1807                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808                 I915_WRITE(reg, val);
1809         }
1810
1811         reg = PCH_TRANSCONF(pipe);
1812         val = I915_READ(reg);
1813         pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815         if (HAS_PCH_IBX(dev_priv)) {
1816                 /*
1817                  * Make the BPC in transcoder be consistent with
1818                  * that in pipeconf reg. For HDMI we must use 8bpc
1819                  * here for both 8bpc and 12bpc.
1820                  */
1821                 val &= ~PIPECONF_BPC_MASK;
1822                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823                         val |= PIPECONF_8BPC;
1824                 else
1825                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1826         }
1827
1828         val &= ~TRANS_INTERLACE_MASK;
1829         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830                 if (HAS_PCH_IBX(dev_priv) &&
1831                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832                         val |= TRANS_LEGACY_INTERLACED_ILK;
1833                 else
1834                         val |= TRANS_INTERLACED;
1835         else
1836                 val |= TRANS_PROGRESSIVE;
1837
1838         I915_WRITE(reg, val | TRANS_ENABLE);
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841                                     100))
1842                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846                                       enum transcoder cpu_transcoder)
1847 {
1848         u32 val, pipeconf_val;
1849
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854         /* Workaround: set timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859         val = TRANS_ENABLE;
1860         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863             PIPECONF_INTERLACED_ILK)
1864                 val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(LPT_TRANSCONF, val);
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF,
1871                                     TRANS_STATE_ENABLE,
1872                                     TRANS_STATE_ENABLE,
1873                                     100))
1874                 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878                                             enum pipe pipe)
1879 {
1880         struct drm_device *dev = &dev_priv->drm;
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123         return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134         return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (drm_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185         struct drm_device *dev = fb->dev;
2186         struct drm_i915_private *dev_priv = to_i915(dev);
2187         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188         struct i915_ggtt_view view;
2189         struct i915_vma *vma;
2190         u32 alignment;
2191
2192         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196         intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198         /* Note that the w/a also requires 64 PTE of padding following the
2199          * bo. We currently fill all unused PTE with the shadow page and so
2200          * we should always have valid PTE following the scanout preventing
2201          * the VT-d warning.
2202          */
2203         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204                 alignment = 256 * 1024;
2205
2206         /*
2207          * Global gtt pte registers are special registers which actually forward
2208          * writes to a chunk of system memory. Which means that there is no risk
2209          * that the register values disappear as soon as we call
2210          * intel_runtime_pm_put(), so it is correct to wrap only the
2211          * pin/unpin/fence and not more.
2212          */
2213         intel_runtime_pm_get(dev_priv);
2214
2215         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216         if (IS_ERR(vma))
2217                 goto err;
2218
2219         if (i915_vma_is_map_and_fenceable(vma)) {
2220                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221                  * fence, whereas 965+ only requires a fence if using
2222                  * framebuffer compression.  For simplicity, we always, when
2223                  * possible, install a fence as the cost is not that onerous.
2224                  *
2225                  * If we fail to fence the tiled scanout, then either the
2226                  * modeset will reject the change (which is highly unlikely as
2227                  * the affected systems, all but one, do not have unmappable
2228                  * space) or we will not be able to enable full powersaving
2229                  * techniques (also likely not to apply due to various limits
2230                  * FBC and the like impose on the size of the buffer, which
2231                  * presumably we violated anyway with this unmappable buffer).
2232                  * Anyway, it is presumably better to stumble onwards with
2233                  * something and try to run the system in a "less than optimal"
2234                  * mode that matches the user configuration.
2235                  */
2236                 if (i915_vma_get_fence(vma) == 0)
2237                         i915_vma_pin_fence(vma);
2238         }
2239
2240 err:
2241         intel_runtime_pm_put(dev_priv);
2242         return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         struct i915_ggtt_view view;
2249         struct i915_vma *vma;
2250
2251         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254         vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256         i915_vma_unpin_fence(vma);
2257         i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261                           unsigned int rotation)
2262 {
2263         if (drm_rotation_90_or_270(rotation))
2264                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265         else
2266                 return fb->pitches[plane];
2267 }
2268
2269 /*
2270  * Convert the x/y offsets into a linear offset.
2271  * Only valid with 0/180 degree rotation, which is fine since linear
2272  * offset is only used with linear buffers on pre-hsw and tiled buffers
2273  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274  */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276                           const struct intel_plane_state *state,
2277                           int plane)
2278 {
2279         const struct drm_framebuffer *fb = state->base.fb;
2280         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281         unsigned int pitch = fb->pitches[plane];
2282
2283         return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287  * Add the x/y offsets derived from fb->offsets[] to the user
2288  * specified plane src x/y offsets. The resulting x/y offsets
2289  * specify the start of scanout from the beginning of the gtt mapping.
2290  */
2291 void intel_add_fb_offsets(int *x, int *y,
2292                           const struct intel_plane_state *state,
2293                           int plane)
2294
2295 {
2296         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297         unsigned int rotation = state->base.rotation;
2298
2299         if (drm_rotation_90_or_270(rotation)) {
2300                 *x += intel_fb->rotated[plane].x;
2301                 *y += intel_fb->rotated[plane].y;
2302         } else {
2303                 *x += intel_fb->normal[plane].x;
2304                 *y += intel_fb->normal[plane].y;
2305         }
2306 }
2307
2308 /*
2309  * Input tile dimensions and pitch must already be
2310  * rotated to match x and y, and in pixel units.
2311  */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313                                      unsigned int tile_width,
2314                                      unsigned int tile_height,
2315                                      unsigned int tile_size,
2316                                      unsigned int pitch_tiles,
2317                                      u32 old_offset,
2318                                      u32 new_offset)
2319 {
2320         unsigned int pitch_pixels = pitch_tiles * tile_width;
2321         unsigned int tiles;
2322
2323         WARN_ON(old_offset & (tile_size - 1));
2324         WARN_ON(new_offset & (tile_size - 1));
2325         WARN_ON(new_offset > old_offset);
2326
2327         tiles = (old_offset - new_offset) / tile_size;
2328
2329         *y += tiles / pitch_tiles * tile_height;
2330         *x += tiles % pitch_tiles * tile_width;
2331
2332         /* minimize x in case it got needlessly big */
2333         *y += *x / pitch_pixels * tile_height;
2334         *x %= pitch_pixels;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Adjust the tile offset by moving the difference into
2341  * the x/y offsets.
2342  */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344                                     const struct intel_plane_state *state, int plane,
2345                                     u32 old_offset, u32 new_offset)
2346 {
2347         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348         const struct drm_framebuffer *fb = state->base.fb;
2349         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350         unsigned int rotation = state->base.rotation;
2351         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353         WARN_ON(new_offset > old_offset);
2354
2355         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int pitch_tiles;
2358
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361                                 fb->modifier[plane], cpp);
2362
2363                 if (drm_rotation_90_or_270(rotation)) {
2364                         pitch_tiles = pitch / tile_height;
2365                         swap(tile_width, tile_height);
2366                 } else {
2367                         pitch_tiles = pitch / (tile_width * cpp);
2368                 }
2369
2370                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371                                           tile_size, pitch_tiles,
2372                                           old_offset, new_offset);
2373         } else {
2374                 old_offset += *y * pitch + *x * cpp;
2375
2376                 *y = (old_offset - new_offset) / pitch;
2377                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378         }
2379
2380         return new_offset;
2381 }
2382
2383 /*
2384  * Computes the linear offset to the base tile and adjusts
2385  * x, y. bytes per pixel is assumed to be a power-of-two.
2386  *
2387  * In the 90/270 rotated case, x and y are assumed
2388  * to be already rotated to match the rotated GTT view, and
2389  * pitch is the tile_height aligned framebuffer height.
2390  *
2391  * This function is used when computing the derived information
2392  * under intel_framebuffer, so using any of that information
2393  * here is not allowed. Anything under drm_framebuffer can be
2394  * used. This is why the user has to pass in the pitch since it
2395  * is specified in the rotated orientation.
2396  */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398                                       int *x, int *y,
2399                                       const struct drm_framebuffer *fb, int plane,
2400                                       unsigned int pitch,
2401                                       unsigned int rotation,
2402                                       u32 alignment)
2403 {
2404         uint64_t fb_modifier = fb->modifier[plane];
2405         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406         u32 offset, offset_aligned;
2407
2408         if (alignment)
2409                 alignment--;
2410
2411         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412                 unsigned int tile_size, tile_width, tile_height;
2413                 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415                 tile_size = intel_tile_size(dev_priv);
2416                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417                                 fb_modifier, cpp);
2418
2419                 if (drm_rotation_90_or_270(rotation)) {
2420                         pitch_tiles = pitch / tile_height;
2421                         swap(tile_width, tile_height);
2422                 } else {
2423                         pitch_tiles = pitch / (tile_width * cpp);
2424                 }
2425
2426                 tile_rows = *y / tile_height;
2427                 *y %= tile_height;
2428
2429                 tiles = *x / tile_width;
2430                 *x %= tile_width;
2431
2432                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433                 offset_aligned = offset & ~alignment;
2434
2435                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436                                           tile_size, pitch_tiles,
2437                                           offset, offset_aligned);
2438         } else {
2439                 offset = *y * pitch + *x * cpp;
2440                 offset_aligned = offset & ~alignment;
2441
2442                 *y = (offset & alignment) / pitch;
2443                 *x = ((offset & alignment) - *y * pitch) / cpp;
2444         }
2445
2446         return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450                               const struct intel_plane_state *state,
2451                               int plane)
2452 {
2453         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454         const struct drm_framebuffer *fb = state->base.fb;
2455         unsigned int rotation = state->base.rotation;
2456         int pitch = intel_fb_pitch(fb, plane, rotation);
2457         u32 alignment;
2458
2459         /* AUX_DIST needs only 4K alignment */
2460         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461                 alignment = 4096;
2462         else
2463                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466                                           rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471                                   const struct drm_framebuffer *fb, int plane)
2472 {
2473         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474         unsigned int pitch = fb->pitches[plane];
2475         u32 linear_offset = fb->offsets[plane];
2476
2477         *y = linear_offset / pitch;
2478         *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483         switch (fb_modifier) {
2484         case I915_FORMAT_MOD_X_TILED:
2485                 return I915_TILING_X;
2486         case I915_FORMAT_MOD_Y_TILED:
2487                 return I915_TILING_Y;
2488         default:
2489                 return I915_TILING_NONE;
2490         }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495                    struct drm_framebuffer *fb)
2496 {
2497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499         u32 gtt_offset_rotated = 0;
2500         unsigned int max_size = 0;
2501         uint32_t format = fb->pixel_format;
2502         int i, num_planes = drm_format_num_planes(format);
2503         unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505         for (i = 0; i < num_planes; i++) {
2506                 unsigned int width, height;
2507                 unsigned int cpp, size;
2508                 u32 offset;
2509                 int x, y;
2510
2511                 cpp = drm_format_plane_cpp(format, i);
2512                 width = drm_format_plane_width(fb->width, format, i);
2513                 height = drm_format_plane_height(fb->height, format, i);
2514
2515                 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517                 /*
2518                  * The fence (if used) is aligned to the start of the object
2519                  * so having the framebuffer wrap around across the edge of the
2520                  * fenced region doesn't really work. We have no API to configure
2521                  * the fence start offset within the object (nor could we probably
2522                  * on gen2/3). So it's just easier if we just require that the
2523                  * fb layout agrees with the fence layout. We already check that the
2524                  * fb stride matches the fence stride elsewhere.
2525                  */
2526                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527                     (x + width) * cpp > fb->pitches[i]) {
2528                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529                                   i, fb->offsets[i]);
2530                         return -EINVAL;
2531                 }
2532
2533                 /*
2534                  * First pixel of the framebuffer from
2535                  * the start of the normal gtt mapping.
2536                  */
2537                 intel_fb->normal[i].x = x;
2538                 intel_fb->normal[i].y = y;
2539
2540                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541                                                     fb, 0, fb->pitches[i],
2542                                                     DRM_ROTATE_0, tile_size);
2543                 offset /= tile_size;
2544
2545                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546                         unsigned int tile_width, tile_height;
2547                         unsigned int pitch_tiles;
2548                         struct drm_rect r;
2549
2550                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551                                         fb->modifier[i], cpp);
2552
2553                         rot_info->plane[i].offset = offset;
2554                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558                         intel_fb->rotated[i].pitch =
2559                                 rot_info->plane[i].height * tile_height;
2560
2561                         /* how many tiles does this plane need */
2562                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563                         /*
2564                          * If the plane isn't horizontally tile aligned,
2565                          * we need one more tile.
2566                          */
2567                         if (x != 0)
2568                                 size++;
2569
2570                         /* rotate the x/y offsets to match the GTT view */
2571                         r.x1 = x;
2572                         r.y1 = y;
2573                         r.x2 = x + width;
2574                         r.y2 = y + height;
2575                         drm_rect_rotate(&r,
2576                                         rot_info->plane[i].width * tile_width,
2577                                         rot_info->plane[i].height * tile_height,
2578                                         DRM_ROTATE_270);
2579                         x = r.x1;
2580                         y = r.y1;
2581
2582                         /* rotate the tile dimensions to match the GTT view */
2583                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584                         swap(tile_width, tile_height);
2585
2586                         /*
2587                          * We only keep the x/y offsets, so push all of the
2588                          * gtt offset into the x/y offsets.
2589                          */
2590                         _intel_adjust_tile_offset(&x, &y, tile_size,
2591                                                   tile_width, tile_height, pitch_tiles,
2592                                                   gtt_offset_rotated * tile_size, 0);
2593
2594                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596                         /*
2597                          * First pixel of the framebuffer from
2598                          * the start of the rotated gtt mapping.
2599                          */
2600                         intel_fb->rotated[i].x = x;
2601                         intel_fb->rotated[i].y = y;
2602                 } else {
2603                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604                                             x * cpp, tile_size);
2605                 }
2606
2607                 /* how many tiles in total needed in the bo */
2608                 max_size = max(max_size, offset + size);
2609         }
2610
2611         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614                 return -EINVAL;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622         switch (format) {
2623         case DISPPLANE_8BPP:
2624                 return DRM_FORMAT_C8;
2625         case DISPPLANE_BGRX555:
2626                 return DRM_FORMAT_XRGB1555;
2627         case DISPPLANE_BGRX565:
2628                 return DRM_FORMAT_RGB565;
2629         default:
2630         case DISPPLANE_BGRX888:
2631                 return DRM_FORMAT_XRGB8888;
2632         case DISPPLANE_RGBX888:
2633                 return DRM_FORMAT_XBGR8888;
2634         case DISPPLANE_BGRX101010:
2635                 return DRM_FORMAT_XRGB2101010;
2636         case DISPPLANE_RGBX101010:
2637                 return DRM_FORMAT_XBGR2101010;
2638         }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643         switch (format) {
2644         case PLANE_CTL_FORMAT_RGB_565:
2645                 return DRM_FORMAT_RGB565;
2646         default:
2647         case PLANE_CTL_FORMAT_XRGB_8888:
2648                 if (rgb_order) {
2649                         if (alpha)
2650                                 return DRM_FORMAT_ABGR8888;
2651                         else
2652                                 return DRM_FORMAT_XBGR8888;
2653                 } else {
2654                         if (alpha)
2655                                 return DRM_FORMAT_ARGB8888;
2656                         else
2657                                 return DRM_FORMAT_XRGB8888;
2658                 }
2659         case PLANE_CTL_FORMAT_XRGB_2101010:
2660                 if (rgb_order)
2661                         return DRM_FORMAT_XBGR2101010;
2662                 else
2663                         return DRM_FORMAT_XRGB2101010;
2664         }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669                               struct intel_initial_plane_config *plane_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674         struct drm_i915_gem_object *obj = NULL;
2675         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676         struct drm_framebuffer *fb = &plane_config->fb->base;
2677         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679                                     PAGE_SIZE);
2680
2681         size_aligned -= base_aligned;
2682
2683         if (plane_config->size == 0)
2684                 return false;
2685
2686         /* If the FB is too big, just don't use it since fbdev is not very
2687          * important and we should probably use that space with FBC or other
2688          * features. */
2689         if (size_aligned * 2 > ggtt->stolen_usable_size)
2690                 return false;
2691
2692         mutex_lock(&dev->struct_mutex);
2693
2694         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695                                                              base_aligned,
2696                                                              base_aligned,
2697                                                              size_aligned);
2698         if (!obj) {
2699                 mutex_unlock(&dev->struct_mutex);
2700                 return false;
2701         }
2702
2703         if (plane_config->tiling == I915_TILING_X)
2704                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706         mode_cmd.pixel_format = fb->pixel_format;
2707         mode_cmd.width = fb->width;
2708         mode_cmd.height = fb->height;
2709         mode_cmd.pitches[0] = fb->pitches[0];
2710         mode_cmd.modifier[0] = fb->modifier[0];
2711         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714                                    &mode_cmd, obj)) {
2715                 DRM_DEBUG_KMS("intel fb init failed\n");
2716                 goto out_unref_obj;
2717         }
2718
2719         mutex_unlock(&dev->struct_mutex);
2720
2721         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722         return true;
2723
2724 out_unref_obj:
2725         i915_gem_object_put(obj);
2726         mutex_unlock(&dev->struct_mutex);
2727         return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734         if (plane->fb == plane->state->fb)
2735                 return;
2736
2737         if (plane->state->fb)
2738                 drm_framebuffer_unreference(plane->state->fb);
2739         plane->state->fb = plane->fb;
2740         if (plane->state->fb)
2741                 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746                              struct intel_initial_plane_config *plane_config)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = to_i915(dev);
2750         struct drm_crtc *c;
2751         struct intel_crtc *i;
2752         struct drm_i915_gem_object *obj;
2753         struct drm_plane *primary = intel_crtc->base.primary;
2754         struct drm_plane_state *plane_state = primary->state;
2755         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756         struct intel_plane *intel_plane = to_intel_plane(primary);
2757         struct intel_plane_state *intel_state =
2758                 to_intel_plane_state(plane_state);
2759         struct drm_framebuffer *fb;
2760
2761         if (!plane_config->fb)
2762                 return;
2763
2764         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765                 fb = &plane_config->fb->base;
2766                 goto valid_fb;
2767         }
2768
2769         kfree(plane_config->fb);
2770
2771         /*
2772          * Failed to alloc the obj, check to see if we should share
2773          * an fb with another CRTC instead
2774          */
2775         for_each_crtc(dev, c) {
2776                 i = to_intel_crtc(c);
2777
2778                 if (c == &intel_crtc->base)
2779                         continue;
2780
2781                 if (!i->active)
2782                         continue;
2783
2784                 fb = c->primary->fb;
2785                 if (!fb)
2786                         continue;
2787
2788                 obj = intel_fb_obj(fb);
2789                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790                         drm_framebuffer_reference(fb);
2791                         goto valid_fb;
2792                 }
2793         }
2794
2795         /*
2796          * We've failed to reconstruct the BIOS FB.  Current display state
2797          * indicates that the primary plane is visible, but has a NULL FB,
2798          * which will lead to problems later if we don't fix it up.  The
2799          * simplest solution is to just disable the primary plane now and
2800          * pretend the BIOS never had it enabled.
2801          */
2802         to_intel_plane_state(plane_state)->base.visible = false;
2803         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805         intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807         return;
2808
2809 valid_fb:
2810         plane_state->src_x = 0;
2811         plane_state->src_y = 0;
2812         plane_state->src_w = fb->width << 16;
2813         plane_state->src_h = fb->height << 16;
2814
2815         plane_state->crtc_x = 0;
2816         plane_state->crtc_y = 0;
2817         plane_state->crtc_w = fb->width;
2818         plane_state->crtc_h = fb->height;
2819
2820         intel_state->base.src.x1 = plane_state->src_x;
2821         intel_state->base.src.y1 = plane_state->src_y;
2822         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824         intel_state->base.dst.x1 = plane_state->crtc_x;
2825         intel_state->base.dst.y1 = plane_state->crtc_y;
2826         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829         obj = intel_fb_obj(fb);
2830         if (i915_gem_object_is_tiled(obj))
2831                 dev_priv->preserve_bios_swizzle = true;
2832
2833         drm_framebuffer_reference(fb);
2834         primary->fb = primary->state->fb = fb;
2835         primary->crtc = primary->state->crtc = &intel_crtc->base;
2836         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838                   &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842                                unsigned int rotation)
2843 {
2844         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846         switch (fb->modifier[plane]) {
2847         case DRM_FORMAT_MOD_NONE:
2848         case I915_FORMAT_MOD_X_TILED:
2849                 switch (cpp) {
2850                 case 8:
2851                         return 4096;
2852                 case 4:
2853                 case 2:
2854                 case 1:
2855                         return 8192;
2856                 default:
2857                         MISSING_CASE(cpp);
2858                         break;
2859                 }
2860                 break;
2861         case I915_FORMAT_MOD_Y_TILED:
2862         case I915_FORMAT_MOD_Yf_TILED:
2863                 switch (cpp) {
2864                 case 8:
2865                         return 2048;
2866                 case 4:
2867                         return 4096;
2868                 case 2:
2869                 case 1:
2870                         return 8192;
2871                 default:
2872                         MISSING_CASE(cpp);
2873                         break;
2874                 }
2875                 break;
2876         default:
2877                 MISSING_CASE(fb->modifier[plane]);
2878         }
2879
2880         return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886         const struct drm_framebuffer *fb = plane_state->base.fb;
2887         unsigned int rotation = plane_state->base.rotation;
2888         int x = plane_state->base.src.x1 >> 16;
2889         int y = plane_state->base.src.y1 >> 16;
2890         int w = drm_rect_width(&plane_state->base.src) >> 16;
2891         int h = drm_rect_height(&plane_state->base.src) >> 16;
2892         int max_width = skl_max_plane_width(fb, 0, rotation);
2893         int max_height = 4096;
2894         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896         if (w > max_width || h > max_height) {
2897                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898                               w, h, max_width, max_height);
2899                 return -EINVAL;
2900         }
2901
2902         intel_add_fb_offsets(&x, &y, plane_state, 0);
2903         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907         /*
2908          * AUX surface offset is specified as the distance from the
2909          * main surface offset, and it must be non-negative. Make
2910          * sure that is what we will get.
2911          */
2912         if (offset > aux_offset)
2913                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914                                                   offset, aux_offset & ~(alignment - 1));
2915
2916         /*
2917          * When using an X-tiled surface, the plane blows up
2918          * if the x offset + width exceed the stride.
2919          *
2920          * TODO: linear and Y-tiled seem fine, Yf untested,
2921          */
2922         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925                 while ((x + w) * cpp > fb->pitches[0]) {
2926                         if (offset == 0) {
2927                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928                                 return -EINVAL;
2929                         }
2930
2931                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932                                                           offset, offset - alignment);
2933                 }
2934         }
2935
2936         plane_state->main.offset = offset;
2937         plane_state->main.x = x;
2938         plane_state->main.y = y;
2939
2940         return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945         const struct drm_framebuffer *fb = plane_state->base.fb;
2946         unsigned int rotation = plane_state->base.rotation;
2947         int max_width = skl_max_plane_width(fb, 1, rotation);
2948         int max_height = 4096;
2949         int x = plane_state->base.src.x1 >> 17;
2950         int y = plane_state->base.src.y1 >> 17;
2951         int w = drm_rect_width(&plane_state->base.src) >> 17;
2952         int h = drm_rect_height(&plane_state->base.src) >> 17;
2953         u32 offset;
2954
2955         intel_add_fb_offsets(&x, &y, plane_state, 1);
2956         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958         /* FIXME not quite sure how/if these apply to the chroma plane */
2959         if (w > max_width || h > max_height) {
2960                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961                               w, h, max_width, max_height);
2962                 return -EINVAL;
2963         }
2964
2965         plane_state->aux.offset = offset;
2966         plane_state->aux.x = x;
2967         plane_state->aux.y = y;
2968
2969         return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974         const struct drm_framebuffer *fb = plane_state->base.fb;
2975         unsigned int rotation = plane_state->base.rotation;
2976         int ret;
2977
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (drm_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width, fb->height, DRM_ROTATE_270);
2982
2983         /*
2984          * Handle the AUX surface first since
2985          * the main surface setup depends on it.
2986          */
2987         if (fb->pixel_format == DRM_FORMAT_NV12) {
2988                 ret = skl_check_nv12_aux_surface(plane_state);
2989                 if (ret)
2990                         return ret;
2991         } else {
2992                 plane_state->aux.offset = ~0xfff;
2993                 plane_state->aux.x = 0;
2994                 plane_state->aux.y = 0;
2995         }
2996
2997         ret = skl_check_main_surface(plane_state);
2998         if (ret)
2999                 return ret;
3000
3001         return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005                                       const struct intel_crtc_state *crtc_state,
3006                                       const struct intel_plane_state *plane_state)
3007 {
3008         struct drm_device *dev = primary->dev;
3009         struct drm_i915_private *dev_priv = to_i915(dev);
3010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011         struct drm_framebuffer *fb = plane_state->base.fb;
3012         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013         int plane = intel_crtc->plane;
3014         u32 linear_offset;
3015         u32 dspcntr;
3016         i915_reg_t reg = DSPCNTR(plane);
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x = plane_state->base.src.x1 >> 16;
3019         int y = plane_state->base.src.y1 >> 16;
3020
3021         dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023         dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025         if (INTEL_INFO(dev)->gen < 4) {
3026                 if (intel_crtc->pipe == PIPE_B)
3027                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029                 /* pipesrc and dspsize control the size that is scaled from,
3030                  * which should always be the user's requested size.
3031                  */
3032                 I915_WRITE(DSPSIZE(plane),
3033                            ((crtc_state->pipe_src_h - 1) << 16) |
3034                            (crtc_state->pipe_src_w - 1));
3035                 I915_WRITE(DSPPOS(plane), 0);
3036         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037                 I915_WRITE(PRIMSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(PRIMPOS(plane), 0);
3041                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042         }
3043
3044         switch (fb->pixel_format) {
3045         case DRM_FORMAT_C8:
3046                 dspcntr |= DISPPLANE_8BPP;
3047                 break;
3048         case DRM_FORMAT_XRGB1555:
3049                 dspcntr |= DISPPLANE_BGRX555;
3050                 break;
3051         case DRM_FORMAT_RGB565:
3052                 dspcntr |= DISPPLANE_BGRX565;
3053                 break;
3054         case DRM_FORMAT_XRGB8888:
3055                 dspcntr |= DISPPLANE_BGRX888;
3056                 break;
3057         case DRM_FORMAT_XBGR8888:
3058                 dspcntr |= DISPPLANE_RGBX888;
3059                 break;
3060         case DRM_FORMAT_XRGB2101010:
3061                 dspcntr |= DISPPLANE_BGRX101010;
3062                 break;
3063         case DRM_FORMAT_XBGR2101010:
3064                 dspcntr |= DISPPLANE_RGBX101010;
3065                 break;
3066         default:
3067                 BUG();
3068         }
3069
3070         if (INTEL_GEN(dev_priv) >= 4 &&
3071             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072                 dspcntr |= DISPPLANE_TILED;
3073
3074         if (IS_G4X(dev))
3075                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077         intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079         if (INTEL_INFO(dev)->gen >= 4)
3080                 intel_crtc->dspaddr_offset =
3081                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083         if (rotation == DRM_ROTATE_180) {
3084                 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086                 x += (crtc_state->pipe_src_w - 1);
3087                 y += (crtc_state->pipe_src_h - 1);
3088         }
3089
3090         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092         if (INTEL_INFO(dev)->gen < 4)
3093                 intel_crtc->dspaddr_offset = linear_offset;
3094
3095         intel_crtc->adjusted_x = x;
3096         intel_crtc->adjusted_y = y;
3097
3098         I915_WRITE(reg, dspcntr);
3099
3100         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101         if (INTEL_INFO(dev)->gen >= 4) {
3102                 I915_WRITE(DSPSURF(plane),
3103                            intel_fb_gtt_offset(fb, rotation) +
3104                            intel_crtc->dspaddr_offset);
3105                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107         } else
3108                 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3177                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179         intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181         intel_crtc->dspaddr_offset =
3182                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184         if (rotation == DRM_ROTATE_180) {
3185                 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3188                         x += (crtc_state->pipe_src_w - 1);
3189                         y += (crtc_state->pipe_src_h - 1);
3190                 }
3191         }
3192
3193         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195         intel_crtc->adjusted_x = x;
3196         intel_crtc->adjusted_y = y;
3197
3198         I915_WRITE(reg, dspcntr);
3199
3200         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201         I915_WRITE(DSPSURF(plane),
3202                    intel_fb_gtt_offset(fb, rotation) +
3203                    intel_crtc->dspaddr_offset);
3204         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3205                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206         } else {
3207                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209         }
3210         POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214                               uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217                 return 64;
3218         } else {
3219                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222         }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226                         unsigned int rotation)
3227 {
3228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229         struct i915_ggtt_view view;
3230         struct i915_vma *vma;
3231
3232         intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234         vma = i915_gem_object_to_ggtt(obj, &view);
3235         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236                  view.type))
3237                 return -1;
3238
3239         return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244         struct drm_device *dev = intel_crtc->base.dev;
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253  * This function detaches (aka. unbinds) unused scalers in hardware
3254  */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257         struct intel_crtc_scaler_state *scaler_state;
3258         int i;
3259
3260         scaler_state = &intel_crtc->config->scaler_state;
3261
3262         /* loop through and disable scalers that aren't in use */
3263         for (i = 0; i < intel_crtc->num_scalers; i++) {
3264                 if (!scaler_state->scalers[i].in_use)
3265                         skl_detach_scaler(intel_crtc, i);
3266         }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270                      unsigned int rotation)
3271 {
3272         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273         u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275         /*
3276          * The stride is either expressed as a multiple of 64 bytes chunks for
3277          * linear buffers or in number of tiles for tiled buffers.
3278          */
3279         if (drm_rotation_90_or_270(rotation)) {
3280                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283         } else {
3284                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285                                                     fb->pixel_format);
3286         }
3287
3288         return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293         switch (pixel_format) {
3294         case DRM_FORMAT_C8:
3295                 return PLANE_CTL_FORMAT_INDEXED;
3296         case DRM_FORMAT_RGB565:
3297                 return PLANE_CTL_FORMAT_RGB_565;
3298         case DRM_FORMAT_XBGR8888:
3299                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300         case DRM_FORMAT_XRGB8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888;
3302         /*
3303          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304          * to be already pre-multiplied. We need to add a knob (or a different
3305          * DRM_FORMAT) for user-space to configure that.
3306          */
3307         case DRM_FORMAT_ABGR8888:
3308                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310         case DRM_FORMAT_ARGB8888:
3311                 return PLANE_CTL_FORMAT_XRGB_8888 |
3312                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313         case DRM_FORMAT_XRGB2101010:
3314                 return PLANE_CTL_FORMAT_XRGB_2101010;
3315         case DRM_FORMAT_XBGR2101010:
3316                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317         case DRM_FORMAT_YUYV:
3318                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319         case DRM_FORMAT_YVYU:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321         case DRM_FORMAT_UYVY:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323         case DRM_FORMAT_VYUY:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325         default:
3326                 MISSING_CASE(pixel_format);
3327         }
3328
3329         return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334         switch (fb_modifier) {
3335         case DRM_FORMAT_MOD_NONE:
3336                 break;
3337         case I915_FORMAT_MOD_X_TILED:
3338                 return PLANE_CTL_TILED_X;
3339         case I915_FORMAT_MOD_Y_TILED:
3340                 return PLANE_CTL_TILED_Y;
3341         case I915_FORMAT_MOD_Yf_TILED:
3342                 return PLANE_CTL_TILED_YF;
3343         default:
3344                 MISSING_CASE(fb_modifier);
3345         }
3346
3347         return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352         switch (rotation) {
3353         case DRM_ROTATE_0:
3354                 break;
3355         /*
3356          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357          * while i915 HW rotation is clockwise, thats why this swapping.
3358          */
3359         case DRM_ROTATE_90:
3360                 return PLANE_CTL_ROTATE_270;
3361         case DRM_ROTATE_180:
3362                 return PLANE_CTL_ROTATE_180;
3363         case DRM_ROTATE_270:
3364                 return PLANE_CTL_ROTATE_90;
3365         default:
3366                 MISSING_CASE(rotation);
3367         }
3368
3369         return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373                                          const struct intel_crtc_state *crtc_state,
3374                                          const struct intel_plane_state *plane_state)
3375 {
3376         struct drm_device *dev = plane->dev;
3377         struct drm_i915_private *dev_priv = to_i915(dev);
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379         struct drm_framebuffer *fb = plane_state->base.fb;
3380         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3381         int pipe = intel_crtc->pipe;
3382         u32 plane_ctl;
3383         unsigned int rotation = plane_state->base.rotation;
3384         u32 stride = skl_plane_stride(fb, 0, rotation);
3385         u32 surf_addr = plane_state->main.offset;
3386         int scaler_id = plane_state->scaler_id;
3387         int src_x = plane_state->main.x;
3388         int src_y = plane_state->main.y;
3389         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391         int dst_x = plane_state->base.dst.x1;
3392         int dst_y = plane_state->base.dst.y1;
3393         int dst_w = drm_rect_width(&plane_state->base.dst);
3394         int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396         plane_ctl = PLANE_CTL_ENABLE |
3397                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3398                     PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403         plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405         /* Sizes are 0 based */
3406         src_w--;
3407         src_h--;
3408         dst_w--;
3409         dst_h--;
3410
3411         intel_crtc->dspaddr_offset = surf_addr;
3412
3413         intel_crtc->adjusted_x = src_x;
3414         intel_crtc->adjusted_y = src_y;
3415
3416         if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3417                 skl_write_plane_wm(intel_crtc, wm, 0);
3418
3419         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3420         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3421         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3422         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3423
3424         if (scaler_id >= 0) {
3425                 uint32_t ps_ctrl = 0;
3426
3427                 WARN_ON(!dst_w || !dst_h);
3428                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3429                         crtc_state->scaler_state.scalers[scaler_id].mode;
3430                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3431                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3432                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3433                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3434                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3435         } else {
3436                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3437         }
3438
3439         I915_WRITE(PLANE_SURF(pipe, 0),
3440                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3441
3442         POSTING_READ(PLANE_SURF(pipe, 0));
3443 }
3444
3445 static void skylake_disable_primary_plane(struct drm_plane *primary,
3446                                           struct drm_crtc *crtc)
3447 {
3448         struct drm_device *dev = crtc->dev;
3449         struct drm_i915_private *dev_priv = to_i915(dev);
3450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3451         int pipe = intel_crtc->pipe;
3452
3453         /*
3454          * We only populate skl_results on watermark updates, and if the
3455          * plane's visiblity isn't actually changing neither is its watermarks.
3456          */
3457         if (!crtc->primary->state->visible)
3458                 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3459
3460         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3461         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3462         POSTING_READ(PLANE_SURF(pipe, 0));
3463 }
3464
3465 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3466 static int
3467 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3468                            int x, int y, enum mode_set_atomic state)
3469 {
3470         /* Support for kgdboc is disabled, this needs a major rework. */
3471         DRM_ERROR("legacy panic handler not supported any more.\n");
3472
3473         return -ENODEV;
3474 }
3475
3476 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3477 {
3478         struct intel_crtc *crtc;
3479
3480         for_each_intel_crtc(&dev_priv->drm, crtc)
3481                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3482 }
3483
3484 static void intel_update_primary_planes(struct drm_device *dev)
3485 {
3486         struct drm_crtc *crtc;
3487
3488         for_each_crtc(dev, crtc) {
3489                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3490                 struct intel_plane_state *plane_state =
3491                         to_intel_plane_state(plane->base.state);
3492
3493                 if (plane_state->base.visible)
3494                         plane->update_plane(&plane->base,
3495                                             to_intel_crtc_state(crtc->state),
3496                                             plane_state);
3497         }
3498 }
3499
3500 static int
3501 __intel_display_resume(struct drm_device *dev,
3502                        struct drm_atomic_state *state)
3503 {
3504         struct drm_crtc_state *crtc_state;
3505         struct drm_crtc *crtc;
3506         int i, ret;
3507
3508         intel_modeset_setup_hw_state(dev);
3509         i915_redisable_vga(dev);
3510
3511         if (!state)
3512                 return 0;
3513
3514         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3515                 /*
3516                  * Force recalculation even if we restore
3517                  * current state. With fast modeset this may not result
3518                  * in a modeset when the state is compatible.
3519                  */
3520                 crtc_state->mode_changed = true;
3521         }
3522
3523         /* ignore any reset values/BIOS leftovers in the WM registers */
3524         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3525
3526         ret = drm_atomic_commit(state);
3527
3528         WARN_ON(ret == -EDEADLK);
3529         return ret;
3530 }
3531
3532 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3533 {
3534         return intel_has_gpu_reset(dev_priv) &&
3535                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3536 }
3537
3538 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3539 {
3540         struct drm_device *dev = &dev_priv->drm;
3541         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3542         struct drm_atomic_state *state;
3543         int ret;
3544
3545         /*
3546          * Need mode_config.mutex so that we don't
3547          * trample ongoing ->detect() and whatnot.
3548          */
3549         mutex_lock(&dev->mode_config.mutex);
3550         drm_modeset_acquire_init(ctx, 0);
3551         while (1) {
3552                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3553                 if (ret != -EDEADLK)
3554                         break;
3555
3556                 drm_modeset_backoff(ctx);
3557         }
3558
3559         /* reset doesn't touch the display, but flips might get nuked anyway, */
3560         if (!i915.force_reset_modeset_test &&
3561             !gpu_reset_clobbers_display(dev_priv))
3562                 return;
3563
3564         /*
3565          * Disabling the crtcs gracefully seems nicer. Also the
3566          * g33 docs say we should at least disable all the planes.
3567          */
3568         state = drm_atomic_helper_duplicate_state(dev, ctx);
3569         if (IS_ERR(state)) {
3570                 ret = PTR_ERR(state);
3571                 state = NULL;
3572                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3573                 goto err;
3574         }
3575
3576         ret = drm_atomic_helper_disable_all(dev, ctx);
3577         if (ret) {
3578                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3579                 goto err;
3580         }
3581
3582         dev_priv->modeset_restore_state = state;
3583         state->acquire_ctx = ctx;
3584         return;
3585
3586 err:
3587         drm_atomic_state_put(state);
3588 }
3589
3590 void intel_finish_reset(struct drm_i915_private *dev_priv)
3591 {
3592         struct drm_device *dev = &dev_priv->drm;
3593         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3594         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3595         int ret;
3596
3597         /*
3598          * Flips in the rings will be nuked by the reset,
3599          * so complete all pending flips so that user space
3600          * will get its events and not get stuck.
3601          */
3602         intel_complete_page_flips(dev_priv);
3603
3604         dev_priv->modeset_restore_state = NULL;
3605
3606         dev_priv->modeset_restore_state = NULL;
3607
3608         /* reset doesn't touch the display */
3609         if (!gpu_reset_clobbers_display(dev_priv)) {
3610                 if (!state) {
3611                         /*
3612                          * Flips in the rings have been nuked by the reset,
3613                          * so update the base address of all primary
3614                          * planes to the the last fb to make sure we're
3615                          * showing the correct fb after a reset.
3616                          *
3617                          * FIXME: Atomic will make this obsolete since we won't schedule
3618                          * CS-based flips (which might get lost in gpu resets) any more.
3619                          */
3620                         intel_update_primary_planes(dev);
3621                 } else {
3622                         ret = __intel_display_resume(dev, state);
3623                         if (ret)
3624                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3625                 }
3626         } else {
3627                 /*
3628                  * The display has been reset as well,
3629                  * so need a full re-initialization.
3630                  */
3631                 intel_runtime_pm_disable_interrupts(dev_priv);
3632                 intel_runtime_pm_enable_interrupts(dev_priv);
3633
3634                 intel_pps_unlock_regs_wa(dev_priv);
3635                 intel_modeset_init_hw(dev);
3636
3637                 spin_lock_irq(&dev_priv->irq_lock);
3638                 if (dev_priv->display.hpd_irq_setup)
3639                         dev_priv->display.hpd_irq_setup(dev_priv);
3640                 spin_unlock_irq(&dev_priv->irq_lock);
3641
3642                 ret = __intel_display_resume(dev, state);
3643                 if (ret)
3644                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3645
3646                 intel_hpd_init(dev_priv);
3647         }
3648
3649         if (state)
3650                 drm_atomic_state_put(state);
3651         drm_modeset_drop_locks(ctx);
3652         drm_modeset_acquire_fini(ctx);
3653         mutex_unlock(&dev->mode_config.mutex);
3654 }
3655
3656 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3657 {
3658         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3659
3660         if (i915_reset_in_progress(error))
3661                 return true;
3662
3663         if (crtc->reset_count != i915_reset_count(error))
3664                 return true;
3665
3666         return false;
3667 }
3668
3669 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3670 {
3671         struct drm_device *dev = crtc->dev;
3672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3673         bool pending;
3674
3675         if (abort_flip_on_reset(intel_crtc))
3676                 return false;
3677
3678         spin_lock_irq(&dev->event_lock);
3679         pending = to_intel_crtc(crtc)->flip_work != NULL;
3680         spin_unlock_irq(&dev->event_lock);
3681
3682         return pending;
3683 }
3684
3685 static void intel_update_pipe_config(struct intel_crtc *crtc,
3686                                      struct intel_crtc_state *old_crtc_state)
3687 {
3688         struct drm_device *dev = crtc->base.dev;
3689         struct drm_i915_private *dev_priv = to_i915(dev);
3690         struct intel_crtc_state *pipe_config =
3691                 to_intel_crtc_state(crtc->base.state);
3692
3693         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3694         crtc->base.mode = crtc->base.state->mode;
3695
3696         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3697                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3698                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3699
3700         /*
3701          * Update pipe size and adjust fitter if needed: the reason for this is
3702          * that in compute_mode_changes we check the native mode (not the pfit
3703          * mode) to see if we can flip rather than do a full mode set. In the
3704          * fastboot case, we'll flip, but if we don't update the pipesrc and
3705          * pfit state, we'll end up with a big fb scanned out into the wrong
3706          * sized surface.
3707          */
3708
3709         I915_WRITE(PIPESRC(crtc->pipe),
3710                    ((pipe_config->pipe_src_w - 1) << 16) |
3711                    (pipe_config->pipe_src_h - 1));
3712
3713         /* on skylake this is done by detaching scalers */
3714         if (INTEL_INFO(dev)->gen >= 9) {
3715                 skl_detach_scalers(crtc);
3716
3717                 if (pipe_config->pch_pfit.enabled)
3718                         skylake_pfit_enable(crtc);
3719         } else if (HAS_PCH_SPLIT(dev)) {
3720                 if (pipe_config->pch_pfit.enabled)
3721                         ironlake_pfit_enable(crtc);
3722                 else if (old_crtc_state->pch_pfit.enabled)
3723                         ironlake_pfit_disable(crtc, true);
3724         }
3725 }
3726
3727 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3728 {
3729         struct drm_device *dev = crtc->dev;
3730         struct drm_i915_private *dev_priv = to_i915(dev);
3731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3732         int pipe = intel_crtc->pipe;
3733         i915_reg_t reg;
3734         u32 temp;
3735
3736         /* enable normal train */
3737         reg = FDI_TX_CTL(pipe);
3738         temp = I915_READ(reg);
3739         if (IS_IVYBRIDGE(dev)) {
3740                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3741                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3742         } else {
3743                 temp &= ~FDI_LINK_TRAIN_NONE;
3744                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3745         }
3746         I915_WRITE(reg, temp);
3747
3748         reg = FDI_RX_CTL(pipe);
3749         temp = I915_READ(reg);
3750         if (HAS_PCH_CPT(dev)) {
3751                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3752                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3753         } else {
3754                 temp &= ~FDI_LINK_TRAIN_NONE;
3755                 temp |= FDI_LINK_TRAIN_NONE;
3756         }
3757         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3758
3759         /* wait one idle pattern time */
3760         POSTING_READ(reg);
3761         udelay(1000);
3762
3763         /* IVB wants error correction enabled */
3764         if (IS_IVYBRIDGE(dev))
3765                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3766                            FDI_FE_ERRC_ENABLE);
3767 }
3768
3769 /* The FDI link training functions for ILK/Ibexpeak. */
3770 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3771 {
3772         struct drm_device *dev = crtc->dev;
3773         struct drm_i915_private *dev_priv = to_i915(dev);
3774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775         int pipe = intel_crtc->pipe;
3776         i915_reg_t reg;
3777         u32 temp, tries;
3778
3779         /* FDI needs bits from pipe first */
3780         assert_pipe_enabled(dev_priv, pipe);
3781
3782         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3783            for train result */
3784         reg = FDI_RX_IMR(pipe);
3785         temp = I915_READ(reg);
3786         temp &= ~FDI_RX_SYMBOL_LOCK;
3787         temp &= ~FDI_RX_BIT_LOCK;
3788         I915_WRITE(reg, temp);
3789         I915_READ(reg);
3790         udelay(150);
3791
3792         /* enable CPU FDI TX and PCH FDI RX */
3793         reg = FDI_TX_CTL(pipe);
3794         temp = I915_READ(reg);
3795         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3796         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3797         temp &= ~FDI_LINK_TRAIN_NONE;
3798         temp |= FDI_LINK_TRAIN_PATTERN_1;
3799         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3800
3801         reg = FDI_RX_CTL(pipe);
3802         temp = I915_READ(reg);
3803         temp &= ~FDI_LINK_TRAIN_NONE;
3804         temp |= FDI_LINK_TRAIN_PATTERN_1;
3805         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3806
3807         POSTING_READ(reg);
3808         udelay(150);
3809
3810         /* Ironlake workaround, enable clock pointer after FDI enable*/
3811         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3812         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3813                    FDI_RX_PHASE_SYNC_POINTER_EN);
3814
3815         reg = FDI_RX_IIR(pipe);
3816         for (tries = 0; tries < 5; tries++) {
3817                 temp = I915_READ(reg);
3818                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3819
3820                 if ((temp & FDI_RX_BIT_LOCK)) {
3821                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3822                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3823                         break;
3824                 }
3825         }
3826         if (tries == 5)
3827                 DRM_ERROR("FDI train 1 fail!\n");
3828
3829         /* Train 2 */
3830         reg = FDI_TX_CTL(pipe);
3831         temp = I915_READ(reg);
3832         temp &= ~FDI_LINK_TRAIN_NONE;
3833         temp |= FDI_LINK_TRAIN_PATTERN_2;
3834         I915_WRITE(reg, temp);
3835
3836         reg = FDI_RX_CTL(pipe);
3837         temp = I915_READ(reg);
3838         temp &= ~FDI_LINK_TRAIN_NONE;
3839         temp |= FDI_LINK_TRAIN_PATTERN_2;
3840         I915_WRITE(reg, temp);
3841
3842         POSTING_READ(reg);
3843         udelay(150);
3844
3845         reg = FDI_RX_IIR(pipe);
3846         for (tries = 0; tries < 5; tries++) {
3847                 temp = I915_READ(reg);
3848                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3849
3850                 if (temp & FDI_RX_SYMBOL_LOCK) {
3851                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3852                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3853                         break;
3854                 }
3855         }
3856         if (tries == 5)
3857                 DRM_ERROR("FDI train 2 fail!\n");
3858
3859         DRM_DEBUG_KMS("FDI train done\n");
3860
3861 }
3862
3863 static const int snb_b_fdi_train_param[] = {
3864         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3865         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3866         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3867         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3868 };
3869
3870 /* The FDI link training functions for SNB/Cougarpoint. */
3871 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3872 {
3873         struct drm_device *dev = crtc->dev;
3874         struct drm_i915_private *dev_priv = to_i915(dev);
3875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3876         int pipe = intel_crtc->pipe;
3877         i915_reg_t reg;
3878         u32 temp, i, retry;
3879
3880         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3881            for train result */
3882         reg = FDI_RX_IMR(pipe);
3883         temp = I915_READ(reg);
3884         temp &= ~FDI_RX_SYMBOL_LOCK;
3885         temp &= ~FDI_RX_BIT_LOCK;
3886         I915_WRITE(reg, temp);
3887
3888         POSTING_READ(reg);
3889         udelay(150);
3890
3891         /* enable CPU FDI TX and PCH FDI RX */
3892         reg = FDI_TX_CTL(pipe);
3893         temp = I915_READ(reg);
3894         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3895         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3896         temp &= ~FDI_LINK_TRAIN_NONE;
3897         temp |= FDI_LINK_TRAIN_PATTERN_1;
3898         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3899         /* SNB-B */
3900         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3901         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3902
3903         I915_WRITE(FDI_RX_MISC(pipe),
3904                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3905
3906         reg = FDI_RX_CTL(pipe);
3907         temp = I915_READ(reg);
3908         if (HAS_PCH_CPT(dev)) {
3909                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3910                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3911         } else {
3912                 temp &= ~FDI_LINK_TRAIN_NONE;
3913                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3914         }
3915         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3916
3917         POSTING_READ(reg);
3918         udelay(150);
3919
3920         for (i = 0; i < 4; i++) {
3921                 reg = FDI_TX_CTL(pipe);
3922                 temp = I915_READ(reg);
3923                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3924                 temp |= snb_b_fdi_train_param[i];
3925                 I915_WRITE(reg, temp);
3926
3927                 POSTING_READ(reg);
3928                 udelay(500);
3929
3930                 for (retry = 0; retry < 5; retry++) {
3931                         reg = FDI_RX_IIR(pipe);
3932                         temp = I915_READ(reg);
3933                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3934                         if (temp & FDI_RX_BIT_LOCK) {
3935                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3936                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3937                                 break;
3938                         }
3939                         udelay(50);
3940                 }
3941                 if (retry < 5)
3942                         break;
3943         }
3944         if (i == 4)
3945                 DRM_ERROR("FDI train 1 fail!\n");
3946
3947         /* Train 2 */
3948         reg = FDI_TX_CTL(pipe);
3949         temp = I915_READ(reg);
3950         temp &= ~FDI_LINK_TRAIN_NONE;
3951         temp |= FDI_LINK_TRAIN_PATTERN_2;
3952         if (IS_GEN6(dev)) {
3953                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3954                 /* SNB-B */
3955                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3956         }
3957         I915_WRITE(reg, temp);
3958
3959         reg = FDI_RX_CTL(pipe);
3960         temp = I915_READ(reg);
3961         if (HAS_PCH_CPT(dev)) {
3962                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3963                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3964         } else {
3965                 temp &= ~FDI_LINK_TRAIN_NONE;
3966                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3967         }
3968         I915_WRITE(reg, temp);
3969
3970         POSTING_READ(reg);
3971         udelay(150);
3972
3973         for (i = 0; i < 4; i++) {
3974                 reg = FDI_TX_CTL(pipe);
3975                 temp = I915_READ(reg);
3976                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3977                 temp |= snb_b_fdi_train_param[i];
3978                 I915_WRITE(reg, temp);
3979
3980                 POSTING_READ(reg);
3981                 udelay(500);
3982
3983                 for (retry = 0; retry < 5; retry++) {
3984                         reg = FDI_RX_IIR(pipe);
3985                         temp = I915_READ(reg);
3986                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3987                         if (temp & FDI_RX_SYMBOL_LOCK) {
3988                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3989                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3990                                 break;
3991                         }
3992                         udelay(50);
3993                 }
3994                 if (retry < 5)
3995                         break;
3996         }
3997         if (i == 4)
3998                 DRM_ERROR("FDI train 2 fail!\n");
3999
4000         DRM_DEBUG_KMS("FDI train done.\n");
4001 }
4002
4003 /* Manual link training for Ivy Bridge A0 parts */
4004 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4005 {
4006         struct drm_device *dev = crtc->dev;
4007         struct drm_i915_private *dev_priv = to_i915(dev);
4008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4009         int pipe = intel_crtc->pipe;
4010         i915_reg_t reg;
4011         u32 temp, i, j;
4012
4013         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4014            for train result */
4015         reg = FDI_RX_IMR(pipe);
4016         temp = I915_READ(reg);
4017         temp &= ~FDI_RX_SYMBOL_LOCK;
4018         temp &= ~FDI_RX_BIT_LOCK;
4019         I915_WRITE(reg, temp);
4020
4021         POSTING_READ(reg);
4022         udelay(150);
4023
4024         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4025                       I915_READ(FDI_RX_IIR(pipe)));
4026
4027         /* Try each vswing and preemphasis setting twice before moving on */
4028         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4029                 /* disable first in case we need to retry */
4030                 reg = FDI_TX_CTL(pipe);
4031                 temp = I915_READ(reg);
4032                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4033                 temp &= ~FDI_TX_ENABLE;
4034                 I915_WRITE(reg, temp);
4035
4036                 reg = FDI_RX_CTL(pipe);
4037                 temp = I915_READ(reg);
4038                 temp &= ~FDI_LINK_TRAIN_AUTO;
4039                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4040                 temp &= ~FDI_RX_ENABLE;
4041                 I915_WRITE(reg, temp);
4042
4043                 /* enable CPU FDI TX and PCH FDI RX */
4044                 reg = FDI_TX_CTL(pipe);
4045                 temp = I915_READ(reg);
4046                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4047                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4048                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4049                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4050                 temp |= snb_b_fdi_train_param[j/2];
4051                 temp |= FDI_COMPOSITE_SYNC;
4052                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4053
4054                 I915_WRITE(FDI_RX_MISC(pipe),
4055                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4056
4057                 reg = FDI_RX_CTL(pipe);
4058                 temp = I915_READ(reg);
4059                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4060                 temp |= FDI_COMPOSITE_SYNC;
4061                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4062
4063                 POSTING_READ(reg);
4064                 udelay(1); /* should be 0.5us */
4065
4066                 for (i = 0; i < 4; i++) {
4067                         reg = FDI_RX_IIR(pipe);
4068                         temp = I915_READ(reg);
4069                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4070
4071                         if (temp & FDI_RX_BIT_LOCK ||
4072                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4073                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4074                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4075                                               i);
4076                                 break;
4077                         }
4078                         udelay(1); /* should be 0.5us */
4079                 }
4080                 if (i == 4) {
4081                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4082                         continue;
4083                 }
4084
4085                 /* Train 2 */
4086                 reg = FDI_TX_CTL(pipe);
4087                 temp = I915_READ(reg);
4088                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4089                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4090                 I915_WRITE(reg, temp);
4091
4092                 reg = FDI_RX_CTL(pipe);
4093                 temp = I915_READ(reg);
4094                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4095                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4096                 I915_WRITE(reg, temp);
4097
4098                 POSTING_READ(reg);
4099                 udelay(2); /* should be 1.5us */
4100
4101                 for (i = 0; i < 4; i++) {
4102                         reg = FDI_RX_IIR(pipe);
4103                         temp = I915_READ(reg);
4104                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4105
4106                         if (temp & FDI_RX_SYMBOL_LOCK ||
4107                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4108                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4109                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4110                                               i);
4111                                 goto train_done;
4112                         }
4113                         udelay(2); /* should be 1.5us */
4114                 }
4115                 if (i == 4)
4116                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4117         }
4118
4119 train_done:
4120         DRM_DEBUG_KMS("FDI train done.\n");
4121 }
4122
4123 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4124 {
4125         struct drm_device *dev = intel_crtc->base.dev;
4126         struct drm_i915_private *dev_priv = to_i915(dev);
4127         int pipe = intel_crtc->pipe;
4128         i915_reg_t reg;
4129         u32 temp;
4130
4131         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4132         reg = FDI_RX_CTL(pipe);
4133         temp = I915_READ(reg);
4134         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4135         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4136         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4137         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4138
4139         POSTING_READ(reg);
4140         udelay(200);
4141
4142         /* Switch from Rawclk to PCDclk */
4143         temp = I915_READ(reg);
4144         I915_WRITE(reg, temp | FDI_PCDCLK);
4145
4146         POSTING_READ(reg);
4147         udelay(200);
4148
4149         /* Enable CPU FDI TX PLL, always on for Ironlake */
4150         reg = FDI_TX_CTL(pipe);
4151         temp = I915_READ(reg);
4152         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4153                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4154
4155                 POSTING_READ(reg);
4156                 udelay(100);
4157         }
4158 }
4159
4160 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4161 {
4162         struct drm_device *dev = intel_crtc->base.dev;
4163         struct drm_i915_private *dev_priv = to_i915(dev);
4164         int pipe = intel_crtc->pipe;
4165         i915_reg_t reg;
4166         u32 temp;
4167
4168         /* Switch from PCDclk to Rawclk */
4169         reg = FDI_RX_CTL(pipe);
4170         temp = I915_READ(reg);
4171         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4172
4173         /* Disable CPU FDI TX PLL */
4174         reg = FDI_TX_CTL(pipe);
4175         temp = I915_READ(reg);
4176         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4177
4178         POSTING_READ(reg);
4179         udelay(100);
4180
4181         reg = FDI_RX_CTL(pipe);
4182         temp = I915_READ(reg);
4183         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4184
4185         /* Wait for the clocks to turn off. */
4186         POSTING_READ(reg);
4187         udelay(100);
4188 }
4189
4190 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4191 {
4192         struct drm_device *dev = crtc->dev;
4193         struct drm_i915_private *dev_priv = to_i915(dev);
4194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4195         int pipe = intel_crtc->pipe;
4196         i915_reg_t reg;
4197         u32 temp;
4198
4199         /* disable CPU FDI tx and PCH FDI rx */
4200         reg = FDI_TX_CTL(pipe);
4201         temp = I915_READ(reg);
4202         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4203         POSTING_READ(reg);
4204
4205         reg = FDI_RX_CTL(pipe);
4206         temp = I915_READ(reg);
4207         temp &= ~(0x7 << 16);
4208         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4209         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4210
4211         POSTING_READ(reg);
4212         udelay(100);
4213
4214         /* Ironlake workaround, disable clock pointer after downing FDI */
4215         if (HAS_PCH_IBX(dev))
4216                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4217
4218         /* still set train pattern 1 */
4219         reg = FDI_TX_CTL(pipe);
4220         temp = I915_READ(reg);
4221         temp &= ~FDI_LINK_TRAIN_NONE;
4222         temp |= FDI_LINK_TRAIN_PATTERN_1;
4223         I915_WRITE(reg, temp);
4224
4225         reg = FDI_RX_CTL(pipe);
4226         temp = I915_READ(reg);
4227         if (HAS_PCH_CPT(dev)) {
4228                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4229                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4230         } else {
4231                 temp &= ~FDI_LINK_TRAIN_NONE;
4232                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4233         }
4234         /* BPC in FDI rx is consistent with that in PIPECONF */
4235         temp &= ~(0x07 << 16);
4236         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4237         I915_WRITE(reg, temp);
4238
4239         POSTING_READ(reg);
4240         udelay(100);
4241 }
4242
4243 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4244 {
4245         struct intel_crtc *crtc;
4246
4247         /* Note that we don't need to be called with mode_config.lock here
4248          * as our list of CRTC objects is static for the lifetime of the
4249          * device and so cannot disappear as we iterate. Similarly, we can
4250          * happily treat the predicates as racy, atomic checks as userspace
4251          * cannot claim and pin a new fb without at least acquring the
4252          * struct_mutex and so serialising with us.
4253          */
4254         for_each_intel_crtc(dev, crtc) {
4255                 if (atomic_read(&crtc->unpin_work_count) == 0)
4256                         continue;
4257
4258                 if (crtc->flip_work)
4259                         intel_wait_for_vblank(dev, crtc->pipe);
4260
4261                 return true;
4262         }
4263
4264         return false;
4265 }
4266
4267 static void page_flip_completed(struct intel_crtc *intel_crtc)
4268 {
4269         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4270         struct intel_flip_work *work = intel_crtc->flip_work;
4271
4272         intel_crtc->flip_work = NULL;
4273
4274         if (work->event)
4275                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4276
4277         drm_crtc_vblank_put(&intel_crtc->base);
4278
4279         wake_up_all(&dev_priv->pending_flip_queue);
4280         queue_work(dev_priv->wq, &work->unpin_work);
4281
4282         trace_i915_flip_complete(intel_crtc->plane,
4283                                  work->pending_flip_obj);
4284 }
4285
4286 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4287 {
4288         struct drm_device *dev = crtc->dev;
4289         struct drm_i915_private *dev_priv = to_i915(dev);
4290         long ret;
4291
4292         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4293
4294         ret = wait_event_interruptible_timeout(
4295                                         dev_priv->pending_flip_queue,
4296                                         !intel_crtc_has_pending_flip(crtc),
4297                                         60*HZ);
4298
4299         if (ret < 0)
4300                 return ret;
4301
4302         if (ret == 0) {
4303                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4304                 struct intel_flip_work *work;
4305
4306                 spin_lock_irq(&dev->event_lock);
4307                 work = intel_crtc->flip_work;
4308                 if (work && !is_mmio_work(work)) {
4309                         WARN_ONCE(1, "Removing stuck page flip\n");
4310                         page_flip_completed(intel_crtc);
4311                 }
4312                 spin_unlock_irq(&dev->event_lock);
4313         }
4314
4315         return 0;
4316 }
4317
4318 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4319 {
4320         u32 temp;
4321
4322         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4323
4324         mutex_lock(&dev_priv->sb_lock);
4325
4326         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4327         temp |= SBI_SSCCTL_DISABLE;
4328         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4329
4330         mutex_unlock(&dev_priv->sb_lock);
4331 }
4332
4333 /* Program iCLKIP clock to the desired frequency */
4334 static void lpt_program_iclkip(struct drm_crtc *crtc)
4335 {
4336         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4337         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4338         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4339         u32 temp;
4340
4341         lpt_disable_iclkip(dev_priv);
4342
4343         /* The iCLK virtual clock root frequency is in MHz,
4344          * but the adjusted_mode->crtc_clock in in KHz. To get the
4345          * divisors, it is necessary to divide one by another, so we
4346          * convert the virtual clock precision to KHz here for higher
4347          * precision.
4348          */
4349         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4350                 u32 iclk_virtual_root_freq = 172800 * 1000;
4351                 u32 iclk_pi_range = 64;
4352                 u32 desired_divisor;
4353
4354                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4355                                                     clock << auxdiv);
4356                 divsel = (desired_divisor / iclk_pi_range) - 2;
4357                 phaseinc = desired_divisor % iclk_pi_range;
4358
4359                 /*
4360                  * Near 20MHz is a corner case which is
4361                  * out of range for the 7-bit divisor
4362                  */
4363                 if (divsel <= 0x7f)
4364                         break;
4365         }
4366
4367         /* This should not happen with any sane values */
4368         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4369                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4370         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4371                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4372
4373         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4374                         clock,
4375                         auxdiv,
4376                         divsel,
4377                         phasedir,
4378                         phaseinc);
4379
4380         mutex_lock(&dev_priv->sb_lock);
4381
4382         /* Program SSCDIVINTPHASE6 */
4383         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4384         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4385         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4386         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4387         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4388         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4389         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4390         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4391
4392         /* Program SSCAUXDIV */
4393         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4394         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4395         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4396         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4397
4398         /* Enable modulator and associated divider */
4399         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4400         temp &= ~SBI_SSCCTL_DISABLE;
4401         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4402
4403         mutex_unlock(&dev_priv->sb_lock);
4404
4405         /* Wait for initialization time */
4406         udelay(24);
4407
4408         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4409 }
4410
4411 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4412 {
4413         u32 divsel, phaseinc, auxdiv;
4414         u32 iclk_virtual_root_freq = 172800 * 1000;
4415         u32 iclk_pi_range = 64;
4416         u32 desired_divisor;
4417         u32 temp;
4418
4419         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4420                 return 0;
4421
4422         mutex_lock(&dev_priv->sb_lock);
4423
4424         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4425         if (temp & SBI_SSCCTL_DISABLE) {
4426                 mutex_unlock(&dev_priv->sb_lock);
4427                 return 0;
4428         }
4429
4430         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4431         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4432                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4433         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4434                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4435
4436         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4437         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4438                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4439
4440         mutex_unlock(&dev_priv->sb_lock);
4441
4442         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4443
4444         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4445                                  desired_divisor << auxdiv);
4446 }
4447
4448 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4449                                                 enum pipe pch_transcoder)
4450 {
4451         struct drm_device *dev = crtc->base.dev;
4452         struct drm_i915_private *dev_priv = to_i915(dev);
4453         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4454
4455         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4456                    I915_READ(HTOTAL(cpu_transcoder)));
4457         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4458                    I915_READ(HBLANK(cpu_transcoder)));
4459         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4460                    I915_READ(HSYNC(cpu_transcoder)));
4461
4462         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4463                    I915_READ(VTOTAL(cpu_transcoder)));
4464         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4465                    I915_READ(VBLANK(cpu_transcoder)));
4466         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4467                    I915_READ(VSYNC(cpu_transcoder)));
4468         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4469                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4470 }
4471
4472 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4473 {
4474         struct drm_i915_private *dev_priv = to_i915(dev);
4475         uint32_t temp;
4476
4477         temp = I915_READ(SOUTH_CHICKEN1);
4478         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4479                 return;
4480
4481         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4482         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4483
4484         temp &= ~FDI_BC_BIFURCATION_SELECT;
4485         if (enable)
4486                 temp |= FDI_BC_BIFURCATION_SELECT;
4487
4488         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4489         I915_WRITE(SOUTH_CHICKEN1, temp);
4490         POSTING_READ(SOUTH_CHICKEN1);
4491 }
4492
4493 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4494 {
4495         struct drm_device *dev = intel_crtc->base.dev;
4496
4497         switch (intel_crtc->pipe) {
4498         case PIPE_A:
4499                 break;
4500         case PIPE_B:
4501                 if (intel_crtc->config->fdi_lanes > 2)
4502                         cpt_set_fdi_bc_bifurcation(dev, false);
4503                 else
4504                         cpt_set_fdi_bc_bifurcation(dev, true);
4505
4506                 break;
4507         case PIPE_C:
4508                 cpt_set_fdi_bc_bifurcation(dev, true);
4509
4510                 break;
4511         default:
4512                 BUG();
4513         }
4514 }
4515
4516 /* Return which DP Port should be selected for Transcoder DP control */
4517 static enum port
4518 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4519 {
4520         struct drm_device *dev = crtc->dev;
4521         struct intel_encoder *encoder;
4522
4523         for_each_encoder_on_crtc(dev, crtc, encoder) {
4524                 if (encoder->type == INTEL_OUTPUT_DP ||
4525                     encoder->type == INTEL_OUTPUT_EDP)
4526                         return enc_to_dig_port(&encoder->base)->port;
4527         }
4528
4529         return -1;
4530 }
4531
4532 /*
4533  * Enable PCH resources required for PCH ports:
4534  *   - PCH PLLs
4535  *   - FDI training & RX/TX
4536  *   - update transcoder timings
4537  *   - DP transcoding bits
4538  *   - transcoder
4539  */
4540 static void ironlake_pch_enable(struct drm_crtc *crtc)
4541 {
4542         struct drm_device *dev = crtc->dev;
4543         struct drm_i915_private *dev_priv = to_i915(dev);
4544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545         int pipe = intel_crtc->pipe;
4546         u32 temp;
4547
4548         assert_pch_transcoder_disabled(dev_priv, pipe);
4549
4550         if (IS_IVYBRIDGE(dev))
4551                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4552
4553         /* Write the TU size bits before fdi link training, so that error
4554          * detection works. */
4555         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4556                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4557
4558         /* For PCH output, training FDI link */
4559         dev_priv->display.fdi_link_train(crtc);
4560
4561         /* We need to program the right clock selection before writing the pixel
4562          * mutliplier into the DPLL. */
4563         if (HAS_PCH_CPT(dev)) {
4564                 u32 sel;
4565
4566                 temp = I915_READ(PCH_DPLL_SEL);
4567                 temp |= TRANS_DPLL_ENABLE(pipe);
4568                 sel = TRANS_DPLLB_SEL(pipe);
4569                 if (intel_crtc->config->shared_dpll ==
4570                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4571                         temp |= sel;
4572                 else
4573                         temp &= ~sel;
4574                 I915_WRITE(PCH_DPLL_SEL, temp);
4575         }
4576
4577         /* XXX: pch pll's can be enabled any time before we enable the PCH
4578          * transcoder, and we actually should do this to not upset any PCH
4579          * transcoder that already use the clock when we share it.
4580          *
4581          * Note that enable_shared_dpll tries to do the right thing, but
4582          * get_shared_dpll unconditionally resets the pll - we need that to have
4583          * the right LVDS enable sequence. */
4584         intel_enable_shared_dpll(intel_crtc);
4585
4586         /* set transcoder timing, panel must allow it */
4587         assert_panel_unlocked(dev_priv, pipe);
4588         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4589
4590         intel_fdi_normal_train(crtc);
4591
4592         /* For PCH DP, enable TRANS_DP_CTL */
4593         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4594                 const struct drm_display_mode *adjusted_mode =
4595                         &intel_crtc->config->base.adjusted_mode;
4596                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4597                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4598                 temp = I915_READ(reg);
4599                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4600                           TRANS_DP_SYNC_MASK |
4601                           TRANS_DP_BPC_MASK);
4602                 temp |= TRANS_DP_OUTPUT_ENABLE;
4603                 temp |= bpc << 9; /* same format but at 11:9 */
4604
4605                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4606                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4607                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4608                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4609
4610                 switch (intel_trans_dp_port_sel(crtc)) {
4611                 case PORT_B:
4612                         temp |= TRANS_DP_PORT_SEL_B;
4613                         break;
4614                 case PORT_C:
4615                         temp |= TRANS_DP_PORT_SEL_C;
4616                         break;
4617                 case PORT_D:
4618                         temp |= TRANS_DP_PORT_SEL_D;
4619                         break;
4620                 default:
4621                         BUG();
4622                 }
4623
4624                 I915_WRITE(reg, temp);
4625         }
4626
4627         ironlake_enable_pch_transcoder(dev_priv, pipe);
4628 }
4629
4630 static void lpt_pch_enable(struct drm_crtc *crtc)
4631 {
4632         struct drm_device *dev = crtc->dev;
4633         struct drm_i915_private *dev_priv = to_i915(dev);
4634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4635         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4636
4637         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4638
4639         lpt_program_iclkip(crtc);
4640
4641         /* Set transcoder timing. */
4642         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4643
4644         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4645 }
4646
4647 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4648 {
4649         struct drm_i915_private *dev_priv = to_i915(dev);
4650         i915_reg_t dslreg = PIPEDSL(pipe);
4651         u32 temp;
4652
4653         temp = I915_READ(dslreg);
4654         udelay(500);
4655         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4656                 if (wait_for(I915_READ(dslreg) != temp, 5))
4657                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4658         }
4659 }
4660
4661 static int
4662 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4663                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4664                   int src_w, int src_h, int dst_w, int dst_h)
4665 {
4666         struct intel_crtc_scaler_state *scaler_state =
4667                 &crtc_state->scaler_state;
4668         struct intel_crtc *intel_crtc =
4669                 to_intel_crtc(crtc_state->base.crtc);
4670         int need_scaling;
4671
4672         need_scaling = drm_rotation_90_or_270(rotation) ?
4673                 (src_h != dst_w || src_w != dst_h):
4674                 (src_w != dst_w || src_h != dst_h);
4675
4676         /*
4677          * if plane is being disabled or scaler is no more required or force detach
4678          *  - free scaler binded to this plane/crtc
4679          *  - in order to do this, update crtc->scaler_usage
4680          *
4681          * Here scaler state in crtc_state is set free so that
4682          * scaler can be assigned to other user. Actual register
4683          * update to free the scaler is done in plane/panel-fit programming.
4684          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4685          */
4686         if (force_detach || !need_scaling) {
4687                 if (*scaler_id >= 0) {
4688                         scaler_state->scaler_users &= ~(1 << scaler_user);
4689                         scaler_state->scalers[*scaler_id].in_use = 0;
4690
4691                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4692                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4693                                 intel_crtc->pipe, scaler_user, *scaler_id,
4694                                 scaler_state->scaler_users);
4695                         *scaler_id = -1;
4696                 }
4697                 return 0;
4698         }
4699
4700         /* range checks */
4701         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4702                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4703
4704                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4705                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4706                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4707                         "size is out of scaler range\n",
4708                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4709                 return -EINVAL;
4710         }
4711
4712         /* mark this plane as a scaler user in crtc_state */
4713         scaler_state->scaler_users |= (1 << scaler_user);
4714         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4715                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4716                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4717                 scaler_state->scaler_users);
4718
4719         return 0;
4720 }
4721
4722 /**
4723  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4724  *
4725  * @state: crtc's scaler state
4726  *
4727  * Return
4728  *     0 - scaler_usage updated successfully
4729  *    error - requested scaling cannot be supported or other error condition
4730  */
4731 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4732 {
4733         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4734         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4735
4736         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4737                       intel_crtc->base.base.id, intel_crtc->base.name,
4738                       intel_crtc->pipe, SKL_CRTC_INDEX);
4739
4740         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4741                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4742                 state->pipe_src_w, state->pipe_src_h,
4743                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4744 }
4745
4746 /**
4747  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4748  *
4749  * @state: crtc's scaler state
4750  * @plane_state: atomic plane state to update
4751  *
4752  * Return
4753  *     0 - scaler_usage updated successfully
4754  *    error - requested scaling cannot be supported or other error condition
4755  */
4756 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4757                                    struct intel_plane_state *plane_state)
4758 {
4759
4760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4761         struct intel_plane *intel_plane =
4762                 to_intel_plane(plane_state->base.plane);
4763         struct drm_framebuffer *fb = plane_state->base.fb;
4764         int ret;
4765
4766         bool force_detach = !fb || !plane_state->base.visible;
4767
4768         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4769                       intel_plane->base.base.id, intel_plane->base.name,
4770                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4771
4772         ret = skl_update_scaler(crtc_state, force_detach,
4773                                 drm_plane_index(&intel_plane->base),
4774                                 &plane_state->scaler_id,
4775                                 plane_state->base.rotation,
4776                                 drm_rect_width(&plane_state->base.src) >> 16,
4777                                 drm_rect_height(&plane_state->base.src) >> 16,
4778                                 drm_rect_width(&plane_state->base.dst),
4779                                 drm_rect_height(&plane_state->base.dst));
4780
4781         if (ret || plane_state->scaler_id < 0)
4782                 return ret;
4783
4784         /* check colorkey */
4785         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4786                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4787                               intel_plane->base.base.id,
4788                               intel_plane->base.name);
4789                 return -EINVAL;
4790         }
4791
4792         /* Check src format */
4793         switch (fb->pixel_format) {
4794         case DRM_FORMAT_RGB565:
4795         case DRM_FORMAT_XBGR8888:
4796         case DRM_FORMAT_XRGB8888:
4797         case DRM_FORMAT_ABGR8888:
4798         case DRM_FORMAT_ARGB8888:
4799         case DRM_FORMAT_XRGB2101010:
4800         case DRM_FORMAT_XBGR2101010:
4801         case DRM_FORMAT_YUYV:
4802         case DRM_FORMAT_YVYU:
4803         case DRM_FORMAT_UYVY:
4804         case DRM_FORMAT_VYUY:
4805                 break;
4806         default:
4807                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4808                               intel_plane->base.base.id, intel_plane->base.name,
4809                               fb->base.id, fb->pixel_format);
4810                 return -EINVAL;
4811         }
4812
4813         return 0;
4814 }
4815
4816 static void skylake_scaler_disable(struct intel_crtc *crtc)
4817 {
4818         int i;
4819
4820         for (i = 0; i < crtc->num_scalers; i++)
4821                 skl_detach_scaler(crtc, i);
4822 }
4823
4824 static void skylake_pfit_enable(struct intel_crtc *crtc)
4825 {
4826         struct drm_device *dev = crtc->base.dev;
4827         struct drm_i915_private *dev_priv = to_i915(dev);
4828         int pipe = crtc->pipe;
4829         struct intel_crtc_scaler_state *scaler_state =
4830                 &crtc->config->scaler_state;
4831
4832         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4833
4834         if (crtc->config->pch_pfit.enabled) {
4835                 int id;
4836
4837                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4838                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4839                         return;
4840                 }
4841
4842                 id = scaler_state->scaler_id;
4843                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4844                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4845                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4846                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4847
4848                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4849         }
4850 }
4851
4852 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4853 {
4854         struct drm_device *dev = crtc->base.dev;
4855         struct drm_i915_private *dev_priv = to_i915(dev);
4856         int pipe = crtc->pipe;
4857
4858         if (crtc->config->pch_pfit.enabled) {
4859                 /* Force use of hard-coded filter coefficients
4860                  * as some pre-programmed values are broken,
4861                  * e.g. x201.
4862                  */
4863                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4864                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4865                                                  PF_PIPE_SEL_IVB(pipe));
4866                 else
4867                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4868                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4869                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4870         }
4871 }
4872
4873 void hsw_enable_ips(struct intel_crtc *crtc)
4874 {
4875         struct drm_device *dev = crtc->base.dev;
4876         struct drm_i915_private *dev_priv = to_i915(dev);
4877
4878         if (!crtc->config->ips_enabled)
4879                 return;
4880
4881         /*
4882          * We can only enable IPS after we enable a plane and wait for a vblank
4883          * This function is called from post_plane_update, which is run after
4884          * a vblank wait.
4885          */
4886
4887         assert_plane_enabled(dev_priv, crtc->plane);
4888         if (IS_BROADWELL(dev)) {
4889                 mutex_lock(&dev_priv->rps.hw_lock);
4890                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4891                 mutex_unlock(&dev_priv->rps.hw_lock);
4892                 /* Quoting Art Runyan: "its not safe to expect any particular
4893                  * value in IPS_CTL bit 31 after enabling IPS through the
4894                  * mailbox." Moreover, the mailbox may return a bogus state,
4895                  * so we need to just enable it and continue on.
4896                  */
4897         } else {
4898                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4899                 /* The bit only becomes 1 in the next vblank, so this wait here
4900                  * is essentially intel_wait_for_vblank. If we don't have this
4901                  * and don't wait for vblanks until the end of crtc_enable, then
4902                  * the HW state readout code will complain that the expected
4903                  * IPS_CTL value is not the one we read. */
4904                 if (intel_wait_for_register(dev_priv,
4905                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4906                                             50))
4907                         DRM_ERROR("Timed out waiting for IPS enable\n");
4908         }
4909 }
4910
4911 void hsw_disable_ips(struct intel_crtc *crtc)
4912 {
4913         struct drm_device *dev = crtc->base.dev;
4914         struct drm_i915_private *dev_priv = to_i915(dev);
4915
4916         if (!crtc->config->ips_enabled)
4917                 return;
4918
4919         assert_plane_enabled(dev_priv, crtc->plane);
4920         if (IS_BROADWELL(dev)) {
4921                 mutex_lock(&dev_priv->rps.hw_lock);
4922                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4923                 mutex_unlock(&dev_priv->rps.hw_lock);
4924                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4925                 if (intel_wait_for_register(dev_priv,
4926                                             IPS_CTL, IPS_ENABLE, 0,
4927                                             42))
4928                         DRM_ERROR("Timed out waiting for IPS disable\n");
4929         } else {
4930                 I915_WRITE(IPS_CTL, 0);
4931                 POSTING_READ(IPS_CTL);
4932         }
4933
4934         /* We need to wait for a vblank before we can disable the plane. */
4935         intel_wait_for_vblank(dev, crtc->pipe);
4936 }
4937
4938 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4939 {
4940         if (intel_crtc->overlay) {
4941                 struct drm_device *dev = intel_crtc->base.dev;
4942                 struct drm_i915_private *dev_priv = to_i915(dev);
4943
4944                 mutex_lock(&dev->struct_mutex);
4945                 dev_priv->mm.interruptible = false;
4946                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4947                 dev_priv->mm.interruptible = true;
4948                 mutex_unlock(&dev->struct_mutex);
4949         }
4950
4951         /* Let userspace switch the overlay on again. In most cases userspace
4952          * has to recompute where to put it anyway.
4953          */
4954 }
4955
4956 /**
4957  * intel_post_enable_primary - Perform operations after enabling primary plane
4958  * @crtc: the CRTC whose primary plane was just enabled
4959  *
4960  * Performs potentially sleeping operations that must be done after the primary
4961  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4962  * called due to an explicit primary plane update, or due to an implicit
4963  * re-enable that is caused when a sprite plane is updated to no longer
4964  * completely hide the primary plane.
4965  */
4966 static void
4967 intel_post_enable_primary(struct drm_crtc *crtc)
4968 {
4969         struct drm_device *dev = crtc->dev;
4970         struct drm_i915_private *dev_priv = to_i915(dev);
4971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4972         int pipe = intel_crtc->pipe;
4973
4974         /*
4975          * FIXME IPS should be fine as long as one plane is
4976          * enabled, but in practice it seems to have problems
4977          * when going from primary only to sprite only and vice
4978          * versa.
4979          */
4980         hsw_enable_ips(intel_crtc);
4981
4982         /*
4983          * Gen2 reports pipe underruns whenever all planes are disabled.
4984          * So don't enable underrun reporting before at least some planes
4985          * are enabled.
4986          * FIXME: Need to fix the logic to work when we turn off all planes
4987          * but leave the pipe running.
4988          */
4989         if (IS_GEN2(dev))
4990                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4991
4992         /* Underruns don't always raise interrupts, so check manually. */
4993         intel_check_cpu_fifo_underruns(dev_priv);
4994         intel_check_pch_fifo_underruns(dev_priv);
4995 }
4996
4997 /* FIXME move all this to pre_plane_update() with proper state tracking */
4998 static void
4999 intel_pre_disable_primary(struct drm_crtc *crtc)
5000 {
5001         struct drm_device *dev = crtc->dev;
5002         struct drm_i915_private *dev_priv = to_i915(dev);
5003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004         int pipe = intel_crtc->pipe;
5005
5006         /*
5007          * Gen2 reports pipe underruns whenever all planes are disabled.
5008          * So diasble underrun reporting before all the planes get disabled.
5009          * FIXME: Need to fix the logic to work when we turn off all planes
5010          * but leave the pipe running.
5011          */
5012         if (IS_GEN2(dev))
5013                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5014
5015         /*
5016          * FIXME IPS should be fine as long as one plane is
5017          * enabled, but in practice it seems to have problems
5018          * when going from primary only to sprite only and vice
5019          * versa.
5020          */
5021         hsw_disable_ips(intel_crtc);
5022 }
5023
5024 /* FIXME get rid of this and use pre_plane_update */
5025 static void
5026 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5027 {
5028         struct drm_device *dev = crtc->dev;
5029         struct drm_i915_private *dev_priv = to_i915(dev);
5030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031         int pipe = intel_crtc->pipe;
5032
5033         intel_pre_disable_primary(crtc);
5034
5035         /*
5036          * Vblank time updates from the shadow to live plane control register
5037          * are blocked if the memory self-refresh mode is active at that
5038          * moment. So to make sure the plane gets truly disabled, disable
5039          * first the self-refresh mode. The self-refresh enable bit in turn
5040          * will be checked/applied by the HW only at the next frame start
5041          * event which is after the vblank start event, so we need to have a
5042          * wait-for-vblank between disabling the plane and the pipe.
5043          */
5044         if (HAS_GMCH_DISPLAY(dev)) {
5045                 intel_set_memory_cxsr(dev_priv, false);
5046                 dev_priv->wm.vlv.cxsr = false;
5047                 intel_wait_for_vblank(dev, pipe);
5048         }
5049 }
5050
5051 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5052 {
5053         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5054         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5055         struct intel_crtc_state *pipe_config =
5056                 to_intel_crtc_state(crtc->base.state);
5057         struct drm_plane *primary = crtc->base.primary;
5058         struct drm_plane_state *old_pri_state =
5059                 drm_atomic_get_existing_plane_state(old_state, primary);
5060
5061         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5062
5063         crtc->wm.cxsr_allowed = true;
5064
5065         if (pipe_config->update_wm_post && pipe_config->base.active)
5066                 intel_update_watermarks(&crtc->base);
5067
5068         if (old_pri_state) {
5069                 struct intel_plane_state *primary_state =
5070                         to_intel_plane_state(primary->state);
5071                 struct intel_plane_state *old_primary_state =
5072                         to_intel_plane_state(old_pri_state);
5073
5074                 intel_fbc_post_update(crtc);
5075
5076                 if (primary_state->base.visible &&
5077                     (needs_modeset(&pipe_config->base) ||
5078                      !old_primary_state->base.visible))
5079                         intel_post_enable_primary(&crtc->base);
5080         }
5081 }
5082
5083 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5084 {
5085         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5086         struct drm_device *dev = crtc->base.dev;
5087         struct drm_i915_private *dev_priv = to_i915(dev);
5088         struct intel_crtc_state *pipe_config =
5089                 to_intel_crtc_state(crtc->base.state);
5090         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5091         struct drm_plane *primary = crtc->base.primary;
5092         struct drm_plane_state *old_pri_state =
5093                 drm_atomic_get_existing_plane_state(old_state, primary);
5094         bool modeset = needs_modeset(&pipe_config->base);
5095
5096         if (old_pri_state) {
5097                 struct intel_plane_state *primary_state =
5098                         to_intel_plane_state(primary->state);
5099                 struct intel_plane_state *old_primary_state =
5100                         to_intel_plane_state(old_pri_state);
5101
5102                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5103
5104                 if (old_primary_state->base.visible &&
5105                     (modeset || !primary_state->base.visible))
5106                         intel_pre_disable_primary(&crtc->base);
5107         }
5108
5109         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5110                 crtc->wm.cxsr_allowed = false;
5111
5112                 /*
5113                  * Vblank time updates from the shadow to live plane control register
5114                  * are blocked if the memory self-refresh mode is active at that
5115                  * moment. So to make sure the plane gets truly disabled, disable
5116                  * first the self-refresh mode. The self-refresh enable bit in turn
5117                  * will be checked/applied by the HW only at the next frame start
5118                  * event which is after the vblank start event, so we need to have a
5119                  * wait-for-vblank between disabling the plane and the pipe.
5120                  */
5121                 if (old_crtc_state->base.active) {
5122                         intel_set_memory_cxsr(dev_priv, false);
5123                         dev_priv->wm.vlv.cxsr = false;
5124                         intel_wait_for_vblank(dev, crtc->pipe);
5125                 }
5126         }
5127
5128         /*
5129          * IVB workaround: must disable low power watermarks for at least
5130          * one frame before enabling scaling.  LP watermarks can be re-enabled
5131          * when scaling is disabled.
5132          *
5133          * WaCxSRDisabledForSpriteScaling:ivb
5134          */
5135         if (pipe_config->disable_lp_wm) {
5136                 ilk_disable_lp_wm(dev);
5137                 intel_wait_for_vblank(dev, crtc->pipe);
5138         }
5139
5140         /*
5141          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5142          * watermark programming here.
5143          */
5144         if (needs_modeset(&pipe_config->base))
5145                 return;
5146
5147         /*
5148          * For platforms that support atomic watermarks, program the
5149          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5150          * will be the intermediate values that are safe for both pre- and
5151          * post- vblank; when vblank happens, the 'active' values will be set
5152          * to the final 'target' values and we'll do this again to get the
5153          * optimal watermarks.  For gen9+ platforms, the values we program here
5154          * will be the final target values which will get automatically latched
5155          * at vblank time; no further programming will be necessary.
5156          *
5157          * If a platform hasn't been transitioned to atomic watermarks yet,
5158          * we'll continue to update watermarks the old way, if flags tell
5159          * us to.
5160          */
5161         if (dev_priv->display.initial_watermarks != NULL)
5162                 dev_priv->display.initial_watermarks(pipe_config);
5163         else if (pipe_config->update_wm_pre)
5164                 intel_update_watermarks(&crtc->base);
5165 }
5166
5167 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5168 {
5169         struct drm_device *dev = crtc->dev;
5170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5171         struct drm_plane *p;
5172         int pipe = intel_crtc->pipe;
5173
5174         intel_crtc_dpms_overlay_disable(intel_crtc);
5175
5176         drm_for_each_plane_mask(p, dev, plane_mask)
5177                 to_intel_plane(p)->disable_plane(p, crtc);
5178
5179         /*
5180          * FIXME: Once we grow proper nuclear flip support out of this we need
5181          * to compute the mask of flip planes precisely. For the time being
5182          * consider this a flip to a NULL plane.
5183          */
5184         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5185 }
5186
5187 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5188                                           struct intel_crtc_state *crtc_state,
5189                                           struct drm_atomic_state *old_state)
5190 {
5191         struct drm_connector_state *old_conn_state;
5192         struct drm_connector *conn;
5193         int i;
5194
5195         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5196                 struct drm_connector_state *conn_state = conn->state;
5197                 struct intel_encoder *encoder =
5198                         to_intel_encoder(conn_state->best_encoder);
5199
5200                 if (conn_state->crtc != crtc)
5201                         continue;
5202
5203                 if (encoder->pre_pll_enable)
5204                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5205         }
5206 }
5207
5208 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5209                                       struct intel_crtc_state *crtc_state,
5210                                       struct drm_atomic_state *old_state)
5211 {
5212         struct drm_connector_state *old_conn_state;
5213         struct drm_connector *conn;
5214         int i;
5215
5216         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5217                 struct drm_connector_state *conn_state = conn->state;
5218                 struct intel_encoder *encoder =
5219                         to_intel_encoder(conn_state->best_encoder);
5220
5221                 if (conn_state->crtc != crtc)
5222                         continue;
5223
5224                 if (encoder->pre_enable)
5225                         encoder->pre_enable(encoder, crtc_state, conn_state);
5226         }
5227 }
5228
5229 static void intel_encoders_enable(struct drm_crtc *crtc,
5230                                   struct intel_crtc_state *crtc_state,
5231                                   struct drm_atomic_state *old_state)
5232 {
5233         struct drm_connector_state *old_conn_state;
5234         struct drm_connector *conn;
5235         int i;
5236
5237         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5238                 struct drm_connector_state *conn_state = conn->state;
5239                 struct intel_encoder *encoder =
5240                         to_intel_encoder(conn_state->best_encoder);
5241
5242                 if (conn_state->crtc != crtc)
5243                         continue;
5244
5245                 encoder->enable(encoder, crtc_state, conn_state);
5246                 intel_opregion_notify_encoder(encoder, true);
5247         }
5248 }
5249
5250 static void intel_encoders_disable(struct drm_crtc *crtc,
5251                                    struct intel_crtc_state *old_crtc_state,
5252                                    struct drm_atomic_state *old_state)
5253 {
5254         struct drm_connector_state *old_conn_state;
5255         struct drm_connector *conn;
5256         int i;
5257
5258         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5259                 struct intel_encoder *encoder =
5260                         to_intel_encoder(old_conn_state->best_encoder);
5261
5262                 if (old_conn_state->crtc != crtc)
5263                         continue;
5264
5265                 intel_opregion_notify_encoder(encoder, false);
5266                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5267         }
5268 }
5269
5270 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5271                                         struct intel_crtc_state *old_crtc_state,
5272                                         struct drm_atomic_state *old_state)
5273 {
5274         struct drm_connector_state *old_conn_state;
5275         struct drm_connector *conn;
5276         int i;
5277
5278         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5279                 struct intel_encoder *encoder =
5280                         to_intel_encoder(old_conn_state->best_encoder);
5281
5282                 if (old_conn_state->crtc != crtc)
5283                         continue;
5284
5285                 if (encoder->post_disable)
5286                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5287         }
5288 }
5289
5290 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5291                                             struct intel_crtc_state *old_crtc_state,
5292                                             struct drm_atomic_state *old_state)
5293 {
5294         struct drm_connector_state *old_conn_state;
5295         struct drm_connector *conn;
5296         int i;
5297
5298         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5299                 struct intel_encoder *encoder =
5300                         to_intel_encoder(old_conn_state->best_encoder);
5301
5302                 if (old_conn_state->crtc != crtc)
5303                         continue;
5304
5305                 if (encoder->post_pll_disable)
5306                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5307         }
5308 }
5309
5310 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5311                                  struct drm_atomic_state *old_state)
5312 {
5313         struct drm_crtc *crtc = pipe_config->base.crtc;
5314         struct drm_device *dev = crtc->dev;
5315         struct drm_i915_private *dev_priv = to_i915(dev);
5316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5317         int pipe = intel_crtc->pipe;
5318
5319         if (WARN_ON(intel_crtc->active))
5320                 return;
5321
5322         /*
5323          * Sometimes spurious CPU pipe underruns happen during FDI
5324          * training, at least with VGA+HDMI cloning. Suppress them.
5325          *
5326          * On ILK we get an occasional spurious CPU pipe underruns
5327          * between eDP port A enable and vdd enable. Also PCH port
5328          * enable seems to result in the occasional CPU pipe underrun.
5329          *
5330          * Spurious PCH underruns also occur during PCH enabling.
5331          */
5332         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5333                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5334         if (intel_crtc->config->has_pch_encoder)
5335                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5336
5337         if (intel_crtc->config->has_pch_encoder)
5338                 intel_prepare_shared_dpll(intel_crtc);
5339
5340         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5341                 intel_dp_set_m_n(intel_crtc, M1_N1);
5342
5343         intel_set_pipe_timings(intel_crtc);
5344         intel_set_pipe_src_size(intel_crtc);
5345
5346         if (intel_crtc->config->has_pch_encoder) {
5347                 intel_cpu_transcoder_set_m_n(intel_crtc,
5348                                      &intel_crtc->config->fdi_m_n, NULL);
5349         }
5350
5351         ironlake_set_pipeconf(crtc);
5352
5353         intel_crtc->active = true;
5354
5355         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5356
5357         if (intel_crtc->config->has_pch_encoder) {
5358                 /* Note: FDI PLL enabling _must_ be done before we enable the
5359                  * cpu pipes, hence this is separate from all the other fdi/pch
5360                  * enabling. */
5361                 ironlake_fdi_pll_enable(intel_crtc);
5362         } else {
5363                 assert_fdi_tx_disabled(dev_priv, pipe);
5364                 assert_fdi_rx_disabled(dev_priv, pipe);
5365         }
5366
5367         ironlake_pfit_enable(intel_crtc);
5368
5369         /*
5370          * On ILK+ LUT must be loaded before the pipe is running but with
5371          * clocks enabled
5372          */
5373         intel_color_load_luts(&pipe_config->base);
5374
5375         if (dev_priv->display.initial_watermarks != NULL)
5376                 dev_priv->display.initial_watermarks(intel_crtc->config);
5377         intel_enable_pipe(intel_crtc);
5378
5379         if (intel_crtc->config->has_pch_encoder)
5380                 ironlake_pch_enable(crtc);
5381
5382         assert_vblank_disabled(crtc);
5383         drm_crtc_vblank_on(crtc);
5384
5385         intel_encoders_enable(crtc, pipe_config, old_state);
5386
5387         if (HAS_PCH_CPT(dev))
5388                 cpt_verify_modeset(dev, intel_crtc->pipe);
5389
5390         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5391         if (intel_crtc->config->has_pch_encoder)
5392                 intel_wait_for_vblank(dev, pipe);
5393         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5394         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5395 }
5396
5397 /* IPS only exists on ULT machines and is tied to pipe A. */
5398 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5399 {
5400         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5401 }
5402
5403 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5404                                 struct drm_atomic_state *old_state)
5405 {
5406         struct drm_crtc *crtc = pipe_config->base.crtc;
5407         struct drm_device *dev = crtc->dev;
5408         struct drm_i915_private *dev_priv = to_i915(dev);
5409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5410         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5411         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5412
5413         if (WARN_ON(intel_crtc->active))
5414                 return;
5415
5416         if (intel_crtc->config->has_pch_encoder)
5417                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5418                                                       false);
5419
5420         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5421
5422         if (intel_crtc->config->shared_dpll)
5423                 intel_enable_shared_dpll(intel_crtc);
5424
5425         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5426                 intel_dp_set_m_n(intel_crtc, M1_N1);
5427
5428         if (!transcoder_is_dsi(cpu_transcoder))
5429                 intel_set_pipe_timings(intel_crtc);
5430
5431         intel_set_pipe_src_size(intel_crtc);
5432
5433         if (cpu_transcoder != TRANSCODER_EDP &&
5434             !transcoder_is_dsi(cpu_transcoder)) {
5435                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5436                            intel_crtc->config->pixel_multiplier - 1);
5437         }
5438
5439         if (intel_crtc->config->has_pch_encoder) {
5440                 intel_cpu_transcoder_set_m_n(intel_crtc,
5441                                      &intel_crtc->config->fdi_m_n, NULL);
5442         }
5443
5444         if (!transcoder_is_dsi(cpu_transcoder))
5445                 haswell_set_pipeconf(crtc);
5446
5447         haswell_set_pipemisc(crtc);
5448
5449         intel_color_set_csc(&pipe_config->base);
5450
5451         intel_crtc->active = true;
5452
5453         if (intel_crtc->config->has_pch_encoder)
5454                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5455         else
5456                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5457
5458         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5459
5460         if (intel_crtc->config->has_pch_encoder)
5461                 dev_priv->display.fdi_link_train(crtc);
5462
5463         if (!transcoder_is_dsi(cpu_transcoder))
5464                 intel_ddi_enable_pipe_clock(intel_crtc);
5465
5466         if (INTEL_INFO(dev)->gen >= 9)
5467                 skylake_pfit_enable(intel_crtc);
5468         else
5469                 ironlake_pfit_enable(intel_crtc);
5470
5471         /*
5472          * On ILK+ LUT must be loaded before the pipe is running but with
5473          * clocks enabled
5474          */
5475         intel_color_load_luts(&pipe_config->base);
5476
5477         intel_ddi_set_pipe_settings(crtc);
5478         if (!transcoder_is_dsi(cpu_transcoder))
5479                 intel_ddi_enable_transcoder_func(crtc);
5480
5481         if (dev_priv->display.initial_watermarks != NULL)
5482                 dev_priv->display.initial_watermarks(pipe_config);
5483         else
5484                 intel_update_watermarks(crtc);
5485
5486         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5487         if (!transcoder_is_dsi(cpu_transcoder))
5488                 intel_enable_pipe(intel_crtc);
5489
5490         if (intel_crtc->config->has_pch_encoder)
5491                 lpt_pch_enable(crtc);
5492
5493         if (intel_crtc->config->dp_encoder_is_mst)
5494                 intel_ddi_set_vc_payload_alloc(crtc, true);
5495
5496         assert_vblank_disabled(crtc);
5497         drm_crtc_vblank_on(crtc);
5498
5499         intel_encoders_enable(crtc, pipe_config, old_state);
5500
5501         if (intel_crtc->config->has_pch_encoder) {
5502                 intel_wait_for_vblank(dev, pipe);
5503                 intel_wait_for_vblank(dev, pipe);
5504                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5505                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5506                                                       true);
5507         }
5508
5509         /* If we change the relative order between pipe/planes enabling, we need
5510          * to change the workaround. */
5511         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5512         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5513                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5514                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5515         }
5516 }
5517
5518 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5519 {
5520         struct drm_device *dev = crtc->base.dev;
5521         struct drm_i915_private *dev_priv = to_i915(dev);
5522         int pipe = crtc->pipe;
5523
5524         /* To avoid upsetting the power well on haswell only disable the pfit if
5525          * it's in use. The hw state code will make sure we get this right. */
5526         if (force || crtc->config->pch_pfit.enabled) {
5527                 I915_WRITE(PF_CTL(pipe), 0);
5528                 I915_WRITE(PF_WIN_POS(pipe), 0);
5529                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5530         }
5531 }
5532
5533 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5534                                   struct drm_atomic_state *old_state)
5535 {
5536         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5537         struct drm_device *dev = crtc->dev;
5538         struct drm_i915_private *dev_priv = to_i915(dev);
5539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5540         int pipe = intel_crtc->pipe;
5541
5542         /*
5543          * Sometimes spurious CPU pipe underruns happen when the
5544          * pipe is already disabled, but FDI RX/TX is still enabled.
5545          * Happens at least with VGA+HDMI cloning. Suppress them.
5546          */
5547         if (intel_crtc->config->has_pch_encoder) {
5548                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5549                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5550         }
5551
5552         intel_encoders_disable(crtc, old_crtc_state, old_state);
5553
5554         drm_crtc_vblank_off(crtc);
5555         assert_vblank_disabled(crtc);
5556
5557         intel_disable_pipe(intel_crtc);
5558
5559         ironlake_pfit_disable(intel_crtc, false);
5560
5561         if (intel_crtc->config->has_pch_encoder)
5562                 ironlake_fdi_disable(crtc);
5563
5564         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5565
5566         if (intel_crtc->config->has_pch_encoder) {
5567                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5568
5569                 if (HAS_PCH_CPT(dev)) {
5570                         i915_reg_t reg;
5571                         u32 temp;
5572
5573                         /* disable TRANS_DP_CTL */
5574                         reg = TRANS_DP_CTL(pipe);
5575                         temp = I915_READ(reg);
5576                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5577                                   TRANS_DP_PORT_SEL_MASK);
5578                         temp |= TRANS_DP_PORT_SEL_NONE;
5579                         I915_WRITE(reg, temp);
5580
5581                         /* disable DPLL_SEL */
5582                         temp = I915_READ(PCH_DPLL_SEL);
5583                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5584                         I915_WRITE(PCH_DPLL_SEL, temp);
5585                 }
5586
5587                 ironlake_fdi_pll_disable(intel_crtc);
5588         }
5589
5590         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5591         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5592 }
5593
5594 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5595                                  struct drm_atomic_state *old_state)
5596 {
5597         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5598         struct drm_device *dev = crtc->dev;
5599         struct drm_i915_private *dev_priv = to_i915(dev);
5600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5601         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5602
5603         if (intel_crtc->config->has_pch_encoder)
5604                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5605                                                       false);
5606
5607         intel_encoders_disable(crtc, old_crtc_state, old_state);
5608
5609         drm_crtc_vblank_off(crtc);
5610         assert_vblank_disabled(crtc);
5611
5612         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5613         if (!transcoder_is_dsi(cpu_transcoder))
5614                 intel_disable_pipe(intel_crtc);
5615
5616         if (intel_crtc->config->dp_encoder_is_mst)
5617                 intel_ddi_set_vc_payload_alloc(crtc, false);
5618
5619         if (!transcoder_is_dsi(cpu_transcoder))
5620                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5621
5622         if (INTEL_INFO(dev)->gen >= 9)
5623                 skylake_scaler_disable(intel_crtc);
5624         else
5625                 ironlake_pfit_disable(intel_crtc, false);
5626
5627         if (!transcoder_is_dsi(cpu_transcoder))
5628                 intel_ddi_disable_pipe_clock(intel_crtc);
5629
5630         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5631
5632         if (old_crtc_state->has_pch_encoder)
5633                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5634                                                       true);
5635 }
5636
5637 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5638 {
5639         struct drm_device *dev = crtc->base.dev;
5640         struct drm_i915_private *dev_priv = to_i915(dev);
5641         struct intel_crtc_state *pipe_config = crtc->config;
5642
5643         if (!pipe_config->gmch_pfit.control)
5644                 return;
5645
5646         /*
5647          * The panel fitter should only be adjusted whilst the pipe is disabled,
5648          * according to register description and PRM.
5649          */
5650         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5651         assert_pipe_disabled(dev_priv, crtc->pipe);
5652
5653         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5654         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5655
5656         /* Border color in case we don't scale up to the full screen. Black by
5657          * default, change to something else for debugging. */
5658         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5659 }
5660
5661 static enum intel_display_power_domain port_to_power_domain(enum port port)
5662 {
5663         switch (port) {
5664         case PORT_A:
5665                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5666         case PORT_B:
5667                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5668         case PORT_C:
5669                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5670         case PORT_D:
5671                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5672         case PORT_E:
5673                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5674         default:
5675                 MISSING_CASE(port);
5676                 return POWER_DOMAIN_PORT_OTHER;
5677         }
5678 }
5679
5680 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5681 {
5682         switch (port) {
5683         case PORT_A:
5684                 return POWER_DOMAIN_AUX_A;
5685         case PORT_B:
5686                 return POWER_DOMAIN_AUX_B;
5687         case PORT_C:
5688                 return POWER_DOMAIN_AUX_C;
5689         case PORT_D:
5690                 return POWER_DOMAIN_AUX_D;
5691         case PORT_E:
5692                 /* FIXME: Check VBT for actual wiring of PORT E */
5693                 return POWER_DOMAIN_AUX_D;
5694         default:
5695                 MISSING_CASE(port);
5696                 return POWER_DOMAIN_AUX_A;
5697         }
5698 }
5699
5700 enum intel_display_power_domain
5701 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5702 {
5703         struct drm_device *dev = intel_encoder->base.dev;
5704         struct intel_digital_port *intel_dig_port;
5705
5706         switch (intel_encoder->type) {
5707         case INTEL_OUTPUT_UNKNOWN:
5708                 /* Only DDI platforms should ever use this output type */
5709                 WARN_ON_ONCE(!HAS_DDI(dev));
5710         case INTEL_OUTPUT_DP:
5711         case INTEL_OUTPUT_HDMI:
5712         case INTEL_OUTPUT_EDP:
5713                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5714                 return port_to_power_domain(intel_dig_port->port);
5715         case INTEL_OUTPUT_DP_MST:
5716                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5717                 return port_to_power_domain(intel_dig_port->port);
5718         case INTEL_OUTPUT_ANALOG:
5719                 return POWER_DOMAIN_PORT_CRT;
5720         case INTEL_OUTPUT_DSI:
5721                 return POWER_DOMAIN_PORT_DSI;
5722         default:
5723                 return POWER_DOMAIN_PORT_OTHER;
5724         }
5725 }
5726
5727 enum intel_display_power_domain
5728 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5729 {
5730         struct drm_device *dev = intel_encoder->base.dev;
5731         struct intel_digital_port *intel_dig_port;
5732
5733         switch (intel_encoder->type) {
5734         case INTEL_OUTPUT_UNKNOWN:
5735         case INTEL_OUTPUT_HDMI:
5736                 /*
5737                  * Only DDI platforms should ever use these output types.
5738                  * We can get here after the HDMI detect code has already set
5739                  * the type of the shared encoder. Since we can't be sure
5740                  * what's the status of the given connectors, play safe and
5741                  * run the DP detection too.
5742                  */
5743                 WARN_ON_ONCE(!HAS_DDI(dev));
5744         case INTEL_OUTPUT_DP:
5745         case INTEL_OUTPUT_EDP:
5746                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5747                 return port_to_aux_power_domain(intel_dig_port->port);
5748         case INTEL_OUTPUT_DP_MST:
5749                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5750                 return port_to_aux_power_domain(intel_dig_port->port);
5751         default:
5752                 MISSING_CASE(intel_encoder->type);
5753                 return POWER_DOMAIN_AUX_A;
5754         }
5755 }
5756
5757 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5758                                             struct intel_crtc_state *crtc_state)
5759 {
5760         struct drm_device *dev = crtc->dev;
5761         struct drm_encoder *encoder;
5762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5763         enum pipe pipe = intel_crtc->pipe;
5764         unsigned long mask;
5765         enum transcoder transcoder = crtc_state->cpu_transcoder;
5766
5767         if (!crtc_state->base.active)
5768                 return 0;
5769
5770         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5771         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5772         if (crtc_state->pch_pfit.enabled ||
5773             crtc_state->pch_pfit.force_thru)
5774                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5775
5776         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5777                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5778
5779                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5780         }
5781
5782         if (crtc_state->shared_dpll)
5783                 mask |= BIT(POWER_DOMAIN_PLLS);
5784
5785         return mask;
5786 }
5787
5788 static unsigned long
5789 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5790                                struct intel_crtc_state *crtc_state)
5791 {
5792         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5794         enum intel_display_power_domain domain;
5795         unsigned long domains, new_domains, old_domains;
5796
5797         old_domains = intel_crtc->enabled_power_domains;
5798         intel_crtc->enabled_power_domains = new_domains =
5799                 get_crtc_power_domains(crtc, crtc_state);
5800
5801         domains = new_domains & ~old_domains;
5802
5803         for_each_power_domain(domain, domains)
5804                 intel_display_power_get(dev_priv, domain);
5805
5806         return old_domains & ~new_domains;
5807 }
5808
5809 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5810                                       unsigned long domains)
5811 {
5812         enum intel_display_power_domain domain;
5813
5814         for_each_power_domain(domain, domains)
5815                 intel_display_power_put(dev_priv, domain);
5816 }
5817
5818 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5819 {
5820         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5821
5822         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5823             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5824                 return max_cdclk_freq;
5825         else if (IS_CHERRYVIEW(dev_priv))
5826                 return max_cdclk_freq*95/100;
5827         else if (INTEL_INFO(dev_priv)->gen < 4)
5828                 return 2*max_cdclk_freq*90/100;
5829         else
5830                 return max_cdclk_freq*90/100;
5831 }
5832
5833 static int skl_calc_cdclk(int max_pixclk, int vco);
5834
5835 static void intel_update_max_cdclk(struct drm_device *dev)
5836 {
5837         struct drm_i915_private *dev_priv = to_i915(dev);
5838
5839         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5840                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5841                 int max_cdclk, vco;
5842
5843                 vco = dev_priv->skl_preferred_vco_freq;
5844                 WARN_ON(vco != 8100000 && vco != 8640000);
5845
5846                 /*
5847                  * Use the lower (vco 8640) cdclk values as a
5848                  * first guess. skl_calc_cdclk() will correct it
5849                  * if the preferred vco is 8100 instead.
5850                  */
5851                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5852                         max_cdclk = 617143;
5853                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5854                         max_cdclk = 540000;
5855                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5856                         max_cdclk = 432000;
5857                 else
5858                         max_cdclk = 308571;
5859
5860                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5861         } else if (IS_BROXTON(dev)) {
5862                 dev_priv->max_cdclk_freq = 624000;
5863         } else if (IS_BROADWELL(dev))  {
5864                 /*
5865                  * FIXME with extra cooling we can allow
5866                  * 540 MHz for ULX and 675 Mhz for ULT.
5867                  * How can we know if extra cooling is
5868                  * available? PCI ID, VTB, something else?
5869                  */
5870                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5871                         dev_priv->max_cdclk_freq = 450000;
5872                 else if (IS_BDW_ULX(dev))
5873                         dev_priv->max_cdclk_freq = 450000;
5874                 else if (IS_BDW_ULT(dev))
5875                         dev_priv->max_cdclk_freq = 540000;
5876                 else
5877                         dev_priv->max_cdclk_freq = 675000;
5878         } else if (IS_CHERRYVIEW(dev)) {
5879                 dev_priv->max_cdclk_freq = 320000;
5880         } else if (IS_VALLEYVIEW(dev)) {
5881                 dev_priv->max_cdclk_freq = 400000;
5882         } else {
5883                 /* otherwise assume cdclk is fixed */
5884                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5885         }
5886
5887         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5888
5889         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5890                          dev_priv->max_cdclk_freq);
5891
5892         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5893                          dev_priv->max_dotclk_freq);
5894 }
5895
5896 static void intel_update_cdclk(struct drm_device *dev)
5897 {
5898         struct drm_i915_private *dev_priv = to_i915(dev);
5899
5900         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5901
5902         if (INTEL_GEN(dev_priv) >= 9)
5903                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5904                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5905                                  dev_priv->cdclk_pll.ref);
5906         else
5907                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5908                                  dev_priv->cdclk_freq);
5909
5910         /*
5911          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5912          * Programmng [sic] note: bit[9:2] should be programmed to the number
5913          * of cdclk that generates 4MHz reference clock freq which is used to
5914          * generate GMBus clock. This will vary with the cdclk freq.
5915          */
5916         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5917                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5918 }
5919
5920 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5921 static int skl_cdclk_decimal(int cdclk)
5922 {
5923         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5924 }
5925
5926 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5927 {
5928         int ratio;
5929
5930         if (cdclk == dev_priv->cdclk_pll.ref)
5931                 return 0;
5932
5933         switch (cdclk) {
5934         default:
5935                 MISSING_CASE(cdclk);
5936         case 144000:
5937         case 288000:
5938         case 384000:
5939         case 576000:
5940                 ratio = 60;
5941                 break;
5942         case 624000:
5943                 ratio = 65;
5944                 break;
5945         }
5946
5947         return dev_priv->cdclk_pll.ref * ratio;
5948 }
5949
5950 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5951 {
5952         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5953
5954         /* Timeout 200us */
5955         if (intel_wait_for_register(dev_priv,
5956                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5957                                     1))
5958                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5959
5960         dev_priv->cdclk_pll.vco = 0;
5961 }
5962
5963 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5964 {
5965         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5966         u32 val;
5967
5968         val = I915_READ(BXT_DE_PLL_CTL);
5969         val &= ~BXT_DE_PLL_RATIO_MASK;
5970         val |= BXT_DE_PLL_RATIO(ratio);
5971         I915_WRITE(BXT_DE_PLL_CTL, val);
5972
5973         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5974
5975         /* Timeout 200us */
5976         if (intel_wait_for_register(dev_priv,
5977                                     BXT_DE_PLL_ENABLE,
5978                                     BXT_DE_PLL_LOCK,
5979                                     BXT_DE_PLL_LOCK,
5980                                     1))
5981                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5982
5983         dev_priv->cdclk_pll.vco = vco;
5984 }
5985
5986 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5987 {
5988         u32 val, divider;
5989         int vco, ret;
5990
5991         vco = bxt_de_pll_vco(dev_priv, cdclk);
5992
5993         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5994
5995         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5996         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5997         case 8:
5998                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5999                 break;
6000         case 4:
6001                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
6002                 break;
6003         case 3:
6004                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6005                 break;
6006         case 2:
6007                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6008                 break;
6009         default:
6010                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6011                 WARN_ON(vco != 0);
6012
6013                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6014                 break;
6015         }
6016
6017         /* Inform power controller of upcoming frequency change */
6018         mutex_lock(&dev_priv->rps.hw_lock);
6019         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6020                                       0x80000000);
6021         mutex_unlock(&dev_priv->rps.hw_lock);
6022
6023         if (ret) {
6024                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6025                           ret, cdclk);
6026                 return;
6027         }
6028
6029         if (dev_priv->cdclk_pll.vco != 0 &&
6030             dev_priv->cdclk_pll.vco != vco)
6031                 bxt_de_pll_disable(dev_priv);
6032
6033         if (dev_priv->cdclk_pll.vco != vco)
6034                 bxt_de_pll_enable(dev_priv, vco);
6035
6036         val = divider | skl_cdclk_decimal(cdclk);
6037         /*
6038          * FIXME if only the cd2x divider needs changing, it could be done
6039          * without shutting off the pipe (if only one pipe is active).
6040          */
6041         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6042         /*
6043          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6044          * enable otherwise.
6045          */
6046         if (cdclk >= 500000)
6047                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6048         I915_WRITE(CDCLK_CTL, val);
6049
6050         mutex_lock(&dev_priv->rps.hw_lock);
6051         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6052                                       DIV_ROUND_UP(cdclk, 25000));
6053         mutex_unlock(&dev_priv->rps.hw_lock);
6054
6055         if (ret) {
6056                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6057                           ret, cdclk);
6058                 return;
6059         }
6060
6061         intel_update_cdclk(&dev_priv->drm);
6062 }
6063
6064 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6065 {
6066         u32 cdctl, expected;
6067
6068         intel_update_cdclk(&dev_priv->drm);
6069
6070         if (dev_priv->cdclk_pll.vco == 0 ||
6071             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6072                 goto sanitize;
6073
6074         /* DPLL okay; verify the cdclock
6075          *
6076          * Some BIOS versions leave an incorrect decimal frequency value and
6077          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6078          * so sanitize this register.
6079          */
6080         cdctl = I915_READ(CDCLK_CTL);
6081         /*
6082          * Let's ignore the pipe field, since BIOS could have configured the
6083          * dividers both synching to an active pipe, or asynchronously
6084          * (PIPE_NONE).
6085          */
6086         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6087
6088         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6089                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6090         /*
6091          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6092          * enable otherwise.
6093          */
6094         if (dev_priv->cdclk_freq >= 500000)
6095                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6096
6097         if (cdctl == expected)
6098                 /* All well; nothing to sanitize */
6099                 return;
6100
6101 sanitize:
6102         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6103
6104         /* force cdclk programming */
6105         dev_priv->cdclk_freq = 0;
6106
6107         /* force full PLL disable + enable */
6108         dev_priv->cdclk_pll.vco = -1;
6109 }
6110
6111 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6112 {
6113         bxt_sanitize_cdclk(dev_priv);
6114
6115         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6116                 return;
6117
6118         /*
6119          * FIXME:
6120          * - The initial CDCLK needs to be read from VBT.
6121          *   Need to make this change after VBT has changes for BXT.
6122          */
6123         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6124 }
6125
6126 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6127 {
6128         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6129 }
6130
6131 static int skl_calc_cdclk(int max_pixclk, int vco)
6132 {
6133         if (vco == 8640000) {
6134                 if (max_pixclk > 540000)
6135                         return 617143;
6136                 else if (max_pixclk > 432000)
6137                         return 540000;
6138                 else if (max_pixclk > 308571)
6139                         return 432000;
6140                 else
6141                         return 308571;
6142         } else {
6143                 if (max_pixclk > 540000)
6144                         return 675000;
6145                 else if (max_pixclk > 450000)
6146                         return 540000;
6147                 else if (max_pixclk > 337500)
6148                         return 450000;
6149                 else
6150                         return 337500;
6151         }
6152 }
6153
6154 static void
6155 skl_dpll0_update(struct drm_i915_private *dev_priv)
6156 {
6157         u32 val;
6158
6159         dev_priv->cdclk_pll.ref = 24000;
6160         dev_priv->cdclk_pll.vco = 0;
6161
6162         val = I915_READ(LCPLL1_CTL);
6163         if ((val & LCPLL_PLL_ENABLE) == 0)
6164                 return;
6165
6166         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6167                 return;
6168
6169         val = I915_READ(DPLL_CTRL1);
6170
6171         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6172                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6173                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6174                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6175                 return;
6176
6177         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6178         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6179         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6180         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6181         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6182                 dev_priv->cdclk_pll.vco = 8100000;
6183                 break;
6184         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6185         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6186                 dev_priv->cdclk_pll.vco = 8640000;
6187                 break;
6188         default:
6189                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6190                 break;
6191         }
6192 }
6193
6194 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6195 {
6196         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6197
6198         dev_priv->skl_preferred_vco_freq = vco;
6199
6200         if (changed)
6201                 intel_update_max_cdclk(&dev_priv->drm);
6202 }
6203
6204 static void
6205 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6206 {
6207         int min_cdclk = skl_calc_cdclk(0, vco);
6208         u32 val;
6209
6210         WARN_ON(vco != 8100000 && vco != 8640000);
6211
6212         /* select the minimum CDCLK before enabling DPLL 0 */
6213         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6214         I915_WRITE(CDCLK_CTL, val);
6215         POSTING_READ(CDCLK_CTL);
6216
6217         /*
6218          * We always enable DPLL0 with the lowest link rate possible, but still
6219          * taking into account the VCO required to operate the eDP panel at the
6220          * desired frequency. The usual DP link rates operate with a VCO of
6221          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6222          * The modeset code is responsible for the selection of the exact link
6223          * rate later on, with the constraint of choosing a frequency that
6224          * works with vco.
6225          */
6226         val = I915_READ(DPLL_CTRL1);
6227
6228         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6229                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6230         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6231         if (vco == 8640000)
6232                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6233                                             SKL_DPLL0);
6234         else
6235                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6236                                             SKL_DPLL0);
6237
6238         I915_WRITE(DPLL_CTRL1, val);
6239         POSTING_READ(DPLL_CTRL1);
6240
6241         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6242
6243         if (intel_wait_for_register(dev_priv,
6244                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6245                                     5))
6246                 DRM_ERROR("DPLL0 not locked\n");
6247
6248         dev_priv->cdclk_pll.vco = vco;
6249
6250         /* We'll want to keep using the current vco from now on. */
6251         skl_set_preferred_cdclk_vco(dev_priv, vco);
6252 }
6253
6254 static void
6255 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6256 {
6257         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6258         if (intel_wait_for_register(dev_priv,
6259                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6260                                    1))
6261                 DRM_ERROR("Couldn't disable DPLL0\n");
6262
6263         dev_priv->cdclk_pll.vco = 0;
6264 }
6265
6266 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6267 {
6268         int ret;
6269         u32 val;
6270
6271         /* inform PCU we want to change CDCLK */
6272         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6273         mutex_lock(&dev_priv->rps.hw_lock);
6274         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6275         mutex_unlock(&dev_priv->rps.hw_lock);
6276
6277         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6278 }
6279
6280 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6281 {
6282         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6283 }
6284
6285 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6286 {
6287         struct drm_device *dev = &dev_priv->drm;
6288         u32 freq_select, pcu_ack;
6289
6290         WARN_ON((cdclk == 24000) != (vco == 0));
6291
6292         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6293
6294         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6295                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6296                 return;
6297         }
6298
6299         /* set CDCLK_CTL */
6300         switch (cdclk) {
6301         case 450000:
6302         case 432000:
6303                 freq_select = CDCLK_FREQ_450_432;
6304                 pcu_ack = 1;
6305                 break;
6306         case 540000:
6307                 freq_select = CDCLK_FREQ_540;
6308                 pcu_ack = 2;
6309                 break;
6310         case 308571:
6311         case 337500:
6312         default:
6313                 freq_select = CDCLK_FREQ_337_308;
6314                 pcu_ack = 0;
6315                 break;
6316         case 617143:
6317         case 675000:
6318                 freq_select = CDCLK_FREQ_675_617;
6319                 pcu_ack = 3;
6320                 break;
6321         }
6322
6323         if (dev_priv->cdclk_pll.vco != 0 &&
6324             dev_priv->cdclk_pll.vco != vco)
6325                 skl_dpll0_disable(dev_priv);
6326
6327         if (dev_priv->cdclk_pll.vco != vco)
6328                 skl_dpll0_enable(dev_priv, vco);
6329
6330         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6331         POSTING_READ(CDCLK_CTL);
6332
6333         /* inform PCU of the change */
6334         mutex_lock(&dev_priv->rps.hw_lock);
6335         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6336         mutex_unlock(&dev_priv->rps.hw_lock);
6337
6338         intel_update_cdclk(dev);
6339 }
6340
6341 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6342
6343 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6344 {
6345         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6346 }
6347
6348 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6349 {
6350         int cdclk, vco;
6351
6352         skl_sanitize_cdclk(dev_priv);
6353
6354         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6355                 /*
6356                  * Use the current vco as our initial
6357                  * guess as to what the preferred vco is.
6358                  */
6359                 if (dev_priv->skl_preferred_vco_freq == 0)
6360                         skl_set_preferred_cdclk_vco(dev_priv,
6361                                                     dev_priv->cdclk_pll.vco);
6362                 return;
6363         }
6364
6365         vco = dev_priv->skl_preferred_vco_freq;
6366         if (vco == 0)
6367                 vco = 8100000;
6368         cdclk = skl_calc_cdclk(0, vco);
6369
6370         skl_set_cdclk(dev_priv, cdclk, vco);
6371 }
6372
6373 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6374 {
6375         uint32_t cdctl, expected;
6376
6377         /*
6378          * check if the pre-os intialized the display
6379          * There is SWF18 scratchpad register defined which is set by the
6380          * pre-os which can be used by the OS drivers to check the status
6381          */
6382         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6383                 goto sanitize;
6384
6385         intel_update_cdclk(&dev_priv->drm);
6386         /* Is PLL enabled and locked ? */
6387         if (dev_priv->cdclk_pll.vco == 0 ||
6388             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6389                 goto sanitize;
6390
6391         /* DPLL okay; verify the cdclock
6392          *
6393          * Noticed in some instances that the freq selection is correct but
6394          * decimal part is programmed wrong from BIOS where pre-os does not
6395          * enable display. Verify the same as well.
6396          */
6397         cdctl = I915_READ(CDCLK_CTL);
6398         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6399                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6400         if (cdctl == expected)
6401                 /* All well; nothing to sanitize */
6402                 return;
6403
6404 sanitize:
6405         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6406
6407         /* force cdclk programming */
6408         dev_priv->cdclk_freq = 0;
6409         /* force full PLL disable + enable */
6410         dev_priv->cdclk_pll.vco = -1;
6411 }
6412
6413 /* Adjust CDclk dividers to allow high res or save power if possible */
6414 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6415 {
6416         struct drm_i915_private *dev_priv = to_i915(dev);
6417         u32 val, cmd;
6418
6419         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6420                                         != dev_priv->cdclk_freq);
6421
6422         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6423                 cmd = 2;
6424         else if (cdclk == 266667)
6425                 cmd = 1;
6426         else
6427                 cmd = 0;
6428
6429         mutex_lock(&dev_priv->rps.hw_lock);
6430         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6431         val &= ~DSPFREQGUAR_MASK;
6432         val |= (cmd << DSPFREQGUAR_SHIFT);
6433         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6434         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6435                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6436                      50)) {
6437                 DRM_ERROR("timed out waiting for CDclk change\n");
6438         }
6439         mutex_unlock(&dev_priv->rps.hw_lock);
6440
6441         mutex_lock(&dev_priv->sb_lock);
6442
6443         if (cdclk == 400000) {
6444                 u32 divider;
6445
6446                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6447
6448                 /* adjust cdclk divider */
6449                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6450                 val &= ~CCK_FREQUENCY_VALUES;
6451                 val |= divider;
6452                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6453
6454                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6455                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6456                              50))
6457                         DRM_ERROR("timed out waiting for CDclk change\n");
6458         }
6459
6460         /* adjust self-refresh exit latency value */
6461         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6462         val &= ~0x7f;
6463
6464         /*
6465          * For high bandwidth configs, we set a higher latency in the bunit
6466          * so that the core display fetch happens in time to avoid underruns.
6467          */
6468         if (cdclk == 400000)
6469                 val |= 4500 / 250; /* 4.5 usec */
6470         else
6471                 val |= 3000 / 250; /* 3.0 usec */
6472         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6473
6474         mutex_unlock(&dev_priv->sb_lock);
6475
6476         intel_update_cdclk(dev);
6477 }
6478
6479 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6480 {
6481         struct drm_i915_private *dev_priv = to_i915(dev);
6482         u32 val, cmd;
6483
6484         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6485                                                 != dev_priv->cdclk_freq);
6486
6487         switch (cdclk) {
6488         case 333333:
6489         case 320000:
6490         case 266667:
6491         case 200000:
6492                 break;
6493         default:
6494                 MISSING_CASE(cdclk);
6495                 return;
6496         }
6497
6498         /*
6499          * Specs are full of misinformation, but testing on actual
6500          * hardware has shown that we just need to write the desired
6501          * CCK divider into the Punit register.
6502          */
6503         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6504
6505         mutex_lock(&dev_priv->rps.hw_lock);
6506         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6507         val &= ~DSPFREQGUAR_MASK_CHV;
6508         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6509         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6510         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6511                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6512                      50)) {
6513                 DRM_ERROR("timed out waiting for CDclk change\n");
6514         }
6515         mutex_unlock(&dev_priv->rps.hw_lock);
6516
6517         intel_update_cdclk(dev);
6518 }
6519
6520 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6521                                  int max_pixclk)
6522 {
6523         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6524         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6525
6526         /*
6527          * Really only a few cases to deal with, as only 4 CDclks are supported:
6528          *   200MHz
6529          *   267MHz
6530          *   320/333MHz (depends on HPLL freq)
6531          *   400MHz (VLV only)
6532          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6533          * of the lower bin and adjust if needed.
6534          *
6535          * We seem to get an unstable or solid color picture at 200MHz.
6536          * Not sure what's wrong. For now use 200MHz only when all pipes
6537          * are off.
6538          */
6539         if (!IS_CHERRYVIEW(dev_priv) &&
6540             max_pixclk > freq_320*limit/100)
6541                 return 400000;
6542         else if (max_pixclk > 266667*limit/100)
6543                 return freq_320;
6544         else if (max_pixclk > 0)
6545                 return 266667;
6546         else
6547                 return 200000;
6548 }
6549
6550 static int bxt_calc_cdclk(int max_pixclk)
6551 {
6552         if (max_pixclk > 576000)
6553                 return 624000;
6554         else if (max_pixclk > 384000)
6555                 return 576000;
6556         else if (max_pixclk > 288000)
6557                 return 384000;
6558         else if (max_pixclk > 144000)
6559                 return 288000;
6560         else
6561                 return 144000;
6562 }
6563
6564 /* Compute the max pixel clock for new configuration. */
6565 static int intel_mode_max_pixclk(struct drm_device *dev,
6566                                  struct drm_atomic_state *state)
6567 {
6568         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6569         struct drm_i915_private *dev_priv = to_i915(dev);
6570         struct drm_crtc *crtc;
6571         struct drm_crtc_state *crtc_state;
6572         unsigned max_pixclk = 0, i;
6573         enum pipe pipe;
6574
6575         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6576                sizeof(intel_state->min_pixclk));
6577
6578         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6579                 int pixclk = 0;
6580
6581                 if (crtc_state->enable)
6582                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6583
6584                 intel_state->min_pixclk[i] = pixclk;
6585         }
6586
6587         for_each_pipe(dev_priv, pipe)
6588                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6589
6590         return max_pixclk;
6591 }
6592
6593 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6594 {
6595         struct drm_device *dev = state->dev;
6596         struct drm_i915_private *dev_priv = to_i915(dev);
6597         int max_pixclk = intel_mode_max_pixclk(dev, state);
6598         struct intel_atomic_state *intel_state =
6599                 to_intel_atomic_state(state);
6600
6601         intel_state->cdclk = intel_state->dev_cdclk =
6602                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6603
6604         if (!intel_state->active_crtcs)
6605                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6606
6607         return 0;
6608 }
6609
6610 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6611 {
6612         int max_pixclk = ilk_max_pixel_rate(state);
6613         struct intel_atomic_state *intel_state =
6614                 to_intel_atomic_state(state);
6615
6616         intel_state->cdclk = intel_state->dev_cdclk =
6617                 bxt_calc_cdclk(max_pixclk);
6618
6619         if (!intel_state->active_crtcs)
6620                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6621
6622         return 0;
6623 }
6624
6625 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6626 {
6627         unsigned int credits, default_credits;
6628
6629         if (IS_CHERRYVIEW(dev_priv))
6630                 default_credits = PFI_CREDIT(12);
6631         else
6632                 default_credits = PFI_CREDIT(8);
6633
6634         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6635                 /* CHV suggested value is 31 or 63 */
6636                 if (IS_CHERRYVIEW(dev_priv))
6637                         credits = PFI_CREDIT_63;
6638                 else
6639                         credits = PFI_CREDIT(15);
6640         } else {
6641                 credits = default_credits;
6642         }
6643
6644         /*
6645          * WA - write default credits before re-programming
6646          * FIXME: should we also set the resend bit here?
6647          */
6648         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6649                    default_credits);
6650
6651         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6652                    credits | PFI_CREDIT_RESEND);
6653
6654         /*
6655          * FIXME is this guaranteed to clear
6656          * immediately or should we poll for it?
6657          */
6658         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6659 }
6660
6661 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6662 {
6663         struct drm_device *dev = old_state->dev;
6664         struct drm_i915_private *dev_priv = to_i915(dev);
6665         struct intel_atomic_state *old_intel_state =
6666                 to_intel_atomic_state(old_state);
6667         unsigned req_cdclk = old_intel_state->dev_cdclk;
6668
6669         /*
6670          * FIXME: We can end up here with all power domains off, yet
6671          * with a CDCLK frequency other than the minimum. To account
6672          * for this take the PIPE-A power domain, which covers the HW
6673          * blocks needed for the following programming. This can be
6674          * removed once it's guaranteed that we get here either with
6675          * the minimum CDCLK set, or the required power domains
6676          * enabled.
6677          */
6678         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6679
6680         if (IS_CHERRYVIEW(dev))
6681                 cherryview_set_cdclk(dev, req_cdclk);
6682         else
6683                 valleyview_set_cdclk(dev, req_cdclk);
6684
6685         vlv_program_pfi_credits(dev_priv);
6686
6687         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6688 }
6689
6690 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6691                                    struct drm_atomic_state *old_state)
6692 {
6693         struct drm_crtc *crtc = pipe_config->base.crtc;
6694         struct drm_device *dev = crtc->dev;
6695         struct drm_i915_private *dev_priv = to_i915(dev);
6696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697         int pipe = intel_crtc->pipe;
6698
6699         if (WARN_ON(intel_crtc->active))
6700                 return;
6701
6702         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6703                 intel_dp_set_m_n(intel_crtc, M1_N1);
6704
6705         intel_set_pipe_timings(intel_crtc);
6706         intel_set_pipe_src_size(intel_crtc);
6707
6708         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6709                 struct drm_i915_private *dev_priv = to_i915(dev);
6710
6711                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6712                 I915_WRITE(CHV_CANVAS(pipe), 0);
6713         }
6714
6715         i9xx_set_pipeconf(intel_crtc);
6716
6717         intel_crtc->active = true;
6718
6719         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6720
6721         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6722
6723         if (IS_CHERRYVIEW(dev)) {
6724                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6725                 chv_enable_pll(intel_crtc, intel_crtc->config);
6726         } else {
6727                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6728                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6729         }
6730
6731         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6732
6733         i9xx_pfit_enable(intel_crtc);
6734
6735         intel_color_load_luts(&pipe_config->base);
6736
6737         intel_update_watermarks(crtc);
6738         intel_enable_pipe(intel_crtc);
6739
6740         assert_vblank_disabled(crtc);
6741         drm_crtc_vblank_on(crtc);
6742
6743         intel_encoders_enable(crtc, pipe_config, old_state);
6744 }
6745
6746 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6747 {
6748         struct drm_device *dev = crtc->base.dev;
6749         struct drm_i915_private *dev_priv = to_i915(dev);
6750
6751         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6752         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6753 }
6754
6755 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6756                              struct drm_atomic_state *old_state)
6757 {
6758         struct drm_crtc *crtc = pipe_config->base.crtc;
6759         struct drm_device *dev = crtc->dev;
6760         struct drm_i915_private *dev_priv = to_i915(dev);
6761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6762         enum pipe pipe = intel_crtc->pipe;
6763
6764         if (WARN_ON(intel_crtc->active))
6765                 return;
6766
6767         i9xx_set_pll_dividers(intel_crtc);
6768
6769         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6770                 intel_dp_set_m_n(intel_crtc, M1_N1);
6771
6772         intel_set_pipe_timings(intel_crtc);
6773         intel_set_pipe_src_size(intel_crtc);
6774
6775         i9xx_set_pipeconf(intel_crtc);
6776
6777         intel_crtc->active = true;
6778
6779         if (!IS_GEN2(dev))
6780                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6781
6782         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6783
6784         i9xx_enable_pll(intel_crtc);
6785
6786         i9xx_pfit_enable(intel_crtc);
6787
6788         intel_color_load_luts(&pipe_config->base);
6789
6790         intel_update_watermarks(crtc);
6791         intel_enable_pipe(intel_crtc);
6792
6793         assert_vblank_disabled(crtc);
6794         drm_crtc_vblank_on(crtc);
6795
6796         intel_encoders_enable(crtc, pipe_config, old_state);
6797 }
6798
6799 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6800 {
6801         struct drm_device *dev = crtc->base.dev;
6802         struct drm_i915_private *dev_priv = to_i915(dev);
6803
6804         if (!crtc->config->gmch_pfit.control)
6805                 return;
6806
6807         assert_pipe_disabled(dev_priv, crtc->pipe);
6808
6809         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6810                          I915_READ(PFIT_CONTROL));
6811         I915_WRITE(PFIT_CONTROL, 0);
6812 }
6813
6814 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6815                               struct drm_atomic_state *old_state)
6816 {
6817         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6818         struct drm_device *dev = crtc->dev;
6819         struct drm_i915_private *dev_priv = to_i915(dev);
6820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6821         int pipe = intel_crtc->pipe;
6822
6823         /*
6824          * On gen2 planes are double buffered but the pipe isn't, so we must
6825          * wait for planes to fully turn off before disabling the pipe.
6826          */
6827         if (IS_GEN2(dev))
6828                 intel_wait_for_vblank(dev, pipe);
6829
6830         intel_encoders_disable(crtc, old_crtc_state, old_state);
6831
6832         drm_crtc_vblank_off(crtc);
6833         assert_vblank_disabled(crtc);
6834
6835         intel_disable_pipe(intel_crtc);
6836
6837         i9xx_pfit_disable(intel_crtc);
6838
6839         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6840
6841         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6842                 if (IS_CHERRYVIEW(dev))
6843                         chv_disable_pll(dev_priv, pipe);
6844                 else if (IS_VALLEYVIEW(dev))
6845                         vlv_disable_pll(dev_priv, pipe);
6846                 else
6847                         i9xx_disable_pll(intel_crtc);
6848         }
6849
6850         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6851
6852         if (!IS_GEN2(dev))
6853                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6854 }
6855
6856 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6857 {
6858         struct intel_encoder *encoder;
6859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6860         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6861         enum intel_display_power_domain domain;
6862         unsigned long domains;
6863         struct drm_atomic_state *state;
6864         struct intel_crtc_state *crtc_state;
6865         int ret;
6866
6867         if (!intel_crtc->active)
6868                 return;
6869
6870         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6871                 WARN_ON(intel_crtc->flip_work);
6872
6873                 intel_pre_disable_primary_noatomic(crtc);
6874
6875                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6876                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6877         }
6878
6879         state = drm_atomic_state_alloc(crtc->dev);
6880         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6881
6882         /* Everything's already locked, -EDEADLK can't happen. */
6883         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6884         ret = drm_atomic_add_affected_connectors(state, crtc);
6885
6886         WARN_ON(IS_ERR(crtc_state) || ret);
6887
6888         dev_priv->display.crtc_disable(crtc_state, state);
6889
6890         drm_atomic_state_put(state);
6891
6892         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6893                       crtc->base.id, crtc->name);
6894
6895         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6896         crtc->state->active = false;
6897         intel_crtc->active = false;
6898         crtc->enabled = false;
6899         crtc->state->connector_mask = 0;
6900         crtc->state->encoder_mask = 0;
6901
6902         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6903                 encoder->base.crtc = NULL;
6904
6905         intel_fbc_disable(intel_crtc);
6906         intel_update_watermarks(crtc);
6907         intel_disable_shared_dpll(intel_crtc);
6908
6909         domains = intel_crtc->enabled_power_domains;
6910         for_each_power_domain(domain, domains)
6911                 intel_display_power_put(dev_priv, domain);
6912         intel_crtc->enabled_power_domains = 0;
6913
6914         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6915         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6916 }
6917
6918 /*
6919  * turn all crtc's off, but do not adjust state
6920  * This has to be paired with a call to intel_modeset_setup_hw_state.
6921  */
6922 int intel_display_suspend(struct drm_device *dev)
6923 {
6924         struct drm_i915_private *dev_priv = to_i915(dev);
6925         struct drm_atomic_state *state;
6926         int ret;
6927
6928         state = drm_atomic_helper_suspend(dev);
6929         ret = PTR_ERR_OR_ZERO(state);
6930         if (ret)
6931                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6932         else
6933                 dev_priv->modeset_restore_state = state;
6934         return ret;
6935 }
6936
6937 void intel_encoder_destroy(struct drm_encoder *encoder)
6938 {
6939         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6940
6941         drm_encoder_cleanup(encoder);
6942         kfree(intel_encoder);
6943 }
6944
6945 /* Cross check the actual hw state with our own modeset state tracking (and it's
6946  * internal consistency). */
6947 static void intel_connector_verify_state(struct intel_connector *connector)
6948 {
6949         struct drm_crtc *crtc = connector->base.state->crtc;
6950
6951         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6952                       connector->base.base.id,
6953                       connector->base.name);
6954
6955         if (connector->get_hw_state(connector)) {
6956                 struct intel_encoder *encoder = connector->encoder;
6957                 struct drm_connector_state *conn_state = connector->base.state;
6958
6959                 I915_STATE_WARN(!crtc,
6960                          "connector enabled without attached crtc\n");
6961
6962                 if (!crtc)
6963                         return;
6964
6965                 I915_STATE_WARN(!crtc->state->active,
6966                       "connector is active, but attached crtc isn't\n");
6967
6968                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6969                         return;
6970
6971                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6972                         "atomic encoder doesn't match attached encoder\n");
6973
6974                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6975                         "attached encoder crtc differs from connector crtc\n");
6976         } else {
6977                 I915_STATE_WARN(crtc && crtc->state->active,
6978                         "attached crtc is active, but connector isn't\n");
6979                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6980                         "best encoder set without crtc!\n");
6981         }
6982 }
6983
6984 int intel_connector_init(struct intel_connector *connector)
6985 {
6986         drm_atomic_helper_connector_reset(&connector->base);
6987
6988         if (!connector->base.state)
6989                 return -ENOMEM;
6990
6991         return 0;
6992 }
6993
6994 struct intel_connector *intel_connector_alloc(void)
6995 {
6996         struct intel_connector *connector;
6997
6998         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6999         if (!connector)
7000                 return NULL;
7001
7002         if (intel_connector_init(connector) < 0) {
7003                 kfree(connector);
7004                 return NULL;
7005         }
7006
7007         return connector;
7008 }
7009
7010 /* Simple connector->get_hw_state implementation for encoders that support only
7011  * one connector and no cloning and hence the encoder state determines the state
7012  * of the connector. */
7013 bool intel_connector_get_hw_state(struct intel_connector *connector)
7014 {
7015         enum pipe pipe = 0;
7016         struct intel_encoder *encoder = connector->encoder;
7017
7018         return encoder->get_hw_state(encoder, &pipe);
7019 }
7020
7021 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7022 {
7023         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7024                 return crtc_state->fdi_lanes;
7025
7026         return 0;
7027 }
7028
7029 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7030                                      struct intel_crtc_state *pipe_config)
7031 {
7032         struct drm_atomic_state *state = pipe_config->base.state;
7033         struct intel_crtc *other_crtc;
7034         struct intel_crtc_state *other_crtc_state;
7035
7036         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7037                       pipe_name(pipe), pipe_config->fdi_lanes);
7038         if (pipe_config->fdi_lanes > 4) {
7039                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7040                               pipe_name(pipe), pipe_config->fdi_lanes);
7041                 return -EINVAL;
7042         }
7043
7044         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7045                 if (pipe_config->fdi_lanes > 2) {
7046                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7047                                       pipe_config->fdi_lanes);
7048                         return -EINVAL;
7049                 } else {
7050                         return 0;
7051                 }
7052         }
7053
7054         if (INTEL_INFO(dev)->num_pipes == 2)
7055                 return 0;
7056
7057         /* Ivybridge 3 pipe is really complicated */
7058         switch (pipe) {
7059         case PIPE_A:
7060                 return 0;
7061         case PIPE_B:
7062                 if (pipe_config->fdi_lanes <= 2)
7063                         return 0;
7064
7065                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7066                 other_crtc_state =
7067                         intel_atomic_get_crtc_state(state, other_crtc);
7068                 if (IS_ERR(other_crtc_state))
7069                         return PTR_ERR(other_crtc_state);
7070
7071                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7072                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7073                                       pipe_name(pipe), pipe_config->fdi_lanes);
7074                         return -EINVAL;
7075                 }
7076                 return 0;
7077         case PIPE_C:
7078                 if (pipe_config->fdi_lanes > 2) {
7079                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7080                                       pipe_name(pipe), pipe_config->fdi_lanes);
7081                         return -EINVAL;
7082                 }
7083
7084                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7085                 other_crtc_state =
7086                         intel_atomic_get_crtc_state(state, other_crtc);
7087                 if (IS_ERR(other_crtc_state))
7088                         return PTR_ERR(other_crtc_state);
7089
7090                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7091                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7092                         return -EINVAL;
7093                 }
7094                 return 0;
7095         default:
7096                 BUG();
7097         }
7098 }
7099
7100 #define RETRY 1
7101 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7102                                        struct intel_crtc_state *pipe_config)
7103 {
7104         struct drm_device *dev = intel_crtc->base.dev;
7105         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7106         int lane, link_bw, fdi_dotclock, ret;
7107         bool needs_recompute = false;
7108
7109 retry:
7110         /* FDI is a binary signal running at ~2.7GHz, encoding
7111          * each output octet as 10 bits. The actual frequency
7112          * is stored as a divider into a 100MHz clock, and the
7113          * mode pixel clock is stored in units of 1KHz.
7114          * Hence the bw of each lane in terms of the mode signal
7115          * is:
7116          */
7117         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7118
7119         fdi_dotclock = adjusted_mode->crtc_clock;
7120
7121         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7122                                            pipe_config->pipe_bpp);
7123
7124         pipe_config->fdi_lanes = lane;
7125
7126         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7127                                link_bw, &pipe_config->fdi_m_n);
7128
7129         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7130         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7131                 pipe_config->pipe_bpp -= 2*3;
7132                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7133                               pipe_config->pipe_bpp);
7134                 needs_recompute = true;
7135                 pipe_config->bw_constrained = true;
7136
7137                 goto retry;
7138         }
7139
7140         if (needs_recompute)
7141                 return RETRY;
7142
7143         return ret;
7144 }
7145
7146 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7147                                      struct intel_crtc_state *pipe_config)
7148 {
7149         if (pipe_config->pipe_bpp > 24)
7150                 return false;
7151
7152         /* HSW can handle pixel rate up to cdclk? */
7153         if (IS_HASWELL(dev_priv))
7154                 return true;
7155
7156         /*
7157          * We compare against max which means we must take
7158          * the increased cdclk requirement into account when
7159          * calculating the new cdclk.
7160          *
7161          * Should measure whether using a lower cdclk w/o IPS
7162          */
7163         return ilk_pipe_pixel_rate(pipe_config) <=
7164                 dev_priv->max_cdclk_freq * 95 / 100;
7165 }
7166
7167 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7168                                    struct intel_crtc_state *pipe_config)
7169 {
7170         struct drm_device *dev = crtc->base.dev;
7171         struct drm_i915_private *dev_priv = to_i915(dev);
7172
7173         pipe_config->ips_enabled = i915.enable_ips &&
7174                 hsw_crtc_supports_ips(crtc) &&
7175                 pipe_config_supports_ips(dev_priv, pipe_config);
7176 }
7177
7178 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7179 {
7180         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7181
7182         /* GDG double wide on either pipe, otherwise pipe A only */
7183         return INTEL_INFO(dev_priv)->gen < 4 &&
7184                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7185 }
7186
7187 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7188                                      struct intel_crtc_state *pipe_config)
7189 {
7190         struct drm_device *dev = crtc->base.dev;
7191         struct drm_i915_private *dev_priv = to_i915(dev);
7192         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7193         int clock_limit = dev_priv->max_dotclk_freq;
7194
7195         if (INTEL_INFO(dev)->gen < 4) {
7196                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7197
7198                 /*
7199                  * Enable double wide mode when the dot clock
7200                  * is > 90% of the (display) core speed.
7201                  */
7202                 if (intel_crtc_supports_double_wide(crtc) &&
7203                     adjusted_mode->crtc_clock > clock_limit) {
7204                         clock_limit = dev_priv->max_dotclk_freq;
7205                         pipe_config->double_wide = true;
7206                 }
7207         }
7208
7209         if (adjusted_mode->crtc_clock > clock_limit) {
7210                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7211                               adjusted_mode->crtc_clock, clock_limit,
7212                               yesno(pipe_config->double_wide));
7213                 return -EINVAL;
7214         }
7215
7216         /*
7217          * Pipe horizontal size must be even in:
7218          * - DVO ganged mode
7219          * - LVDS dual channel mode
7220          * - Double wide pipe
7221          */
7222         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7223              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7224                 pipe_config->pipe_src_w &= ~1;
7225
7226         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7227          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7228          */
7229         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7230                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7231                 return -EINVAL;
7232
7233         if (HAS_IPS(dev))
7234                 hsw_compute_ips_config(crtc, pipe_config);
7235
7236         if (pipe_config->has_pch_encoder)
7237                 return ironlake_fdi_compute_config(crtc, pipe_config);
7238
7239         return 0;
7240 }
7241
7242 static int skylake_get_display_clock_speed(struct drm_device *dev)
7243 {
7244         struct drm_i915_private *dev_priv = to_i915(dev);
7245         uint32_t cdctl;
7246
7247         skl_dpll0_update(dev_priv);
7248
7249         if (dev_priv->cdclk_pll.vco == 0)
7250                 return dev_priv->cdclk_pll.ref;
7251
7252         cdctl = I915_READ(CDCLK_CTL);
7253
7254         if (dev_priv->cdclk_pll.vco == 8640000) {
7255                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7256                 case CDCLK_FREQ_450_432:
7257                         return 432000;
7258                 case CDCLK_FREQ_337_308:
7259                         return 308571;
7260                 case CDCLK_FREQ_540:
7261                         return 540000;
7262                 case CDCLK_FREQ_675_617:
7263                         return 617143;
7264                 default:
7265                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7266                 }
7267         } else {
7268                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7269                 case CDCLK_FREQ_450_432:
7270                         return 450000;
7271                 case CDCLK_FREQ_337_308:
7272                         return 337500;
7273                 case CDCLK_FREQ_540:
7274                         return 540000;
7275                 case CDCLK_FREQ_675_617:
7276                         return 675000;
7277                 default:
7278                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7279                 }
7280         }
7281
7282         return dev_priv->cdclk_pll.ref;
7283 }
7284
7285 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7286 {
7287         u32 val;
7288
7289         dev_priv->cdclk_pll.ref = 19200;
7290         dev_priv->cdclk_pll.vco = 0;
7291
7292         val = I915_READ(BXT_DE_PLL_ENABLE);
7293         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7294                 return;
7295
7296         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7297                 return;
7298
7299         val = I915_READ(BXT_DE_PLL_CTL);
7300         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7301                 dev_priv->cdclk_pll.ref;
7302 }
7303
7304 static int broxton_get_display_clock_speed(struct drm_device *dev)
7305 {
7306         struct drm_i915_private *dev_priv = to_i915(dev);
7307         u32 divider;
7308         int div, vco;
7309
7310         bxt_de_pll_update(dev_priv);
7311
7312         vco = dev_priv->cdclk_pll.vco;
7313         if (vco == 0)
7314                 return dev_priv->cdclk_pll.ref;
7315
7316         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7317
7318         switch (divider) {
7319         case BXT_CDCLK_CD2X_DIV_SEL_1:
7320                 div = 2;
7321                 break;
7322         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7323                 div = 3;
7324                 break;
7325         case BXT_CDCLK_CD2X_DIV_SEL_2:
7326                 div = 4;
7327                 break;
7328         case BXT_CDCLK_CD2X_DIV_SEL_4:
7329                 div = 8;
7330                 break;
7331         default:
7332                 MISSING_CASE(divider);
7333                 return dev_priv->cdclk_pll.ref;
7334         }
7335
7336         return DIV_ROUND_CLOSEST(vco, div);
7337 }
7338
7339 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7340 {
7341         struct drm_i915_private *dev_priv = to_i915(dev);
7342         uint32_t lcpll = I915_READ(LCPLL_CTL);
7343         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7344
7345         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7346                 return 800000;
7347         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7348                 return 450000;
7349         else if (freq == LCPLL_CLK_FREQ_450)
7350                 return 450000;
7351         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7352                 return 540000;
7353         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7354                 return 337500;
7355         else
7356                 return 675000;
7357 }
7358
7359 static int haswell_get_display_clock_speed(struct drm_device *dev)
7360 {
7361         struct drm_i915_private *dev_priv = to_i915(dev);
7362         uint32_t lcpll = I915_READ(LCPLL_CTL);
7363         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7364
7365         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7366                 return 800000;
7367         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7368                 return 450000;
7369         else if (freq == LCPLL_CLK_FREQ_450)
7370                 return 450000;
7371         else if (IS_HSW_ULT(dev))
7372                 return 337500;
7373         else
7374                 return 540000;
7375 }
7376
7377 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7378 {
7379         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7380                                       CCK_DISPLAY_CLOCK_CONTROL);
7381 }
7382
7383 static int ilk_get_display_clock_speed(struct drm_device *dev)
7384 {
7385         return 450000;
7386 }
7387
7388 static int i945_get_display_clock_speed(struct drm_device *dev)
7389 {
7390         return 400000;
7391 }
7392
7393 static int i915_get_display_clock_speed(struct drm_device *dev)
7394 {
7395         return 333333;
7396 }
7397
7398 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7399 {
7400         return 200000;
7401 }
7402
7403 static int pnv_get_display_clock_speed(struct drm_device *dev)
7404 {
7405         struct pci_dev *pdev = dev->pdev;
7406         u16 gcfgc = 0;
7407
7408         pci_read_config_word(pdev, GCFGC, &gcfgc);
7409
7410         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7411         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7412                 return 266667;
7413         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7414                 return 333333;
7415         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7416                 return 444444;
7417         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7418                 return 200000;
7419         default:
7420                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7421         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7422                 return 133333;
7423         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7424                 return 166667;
7425         }
7426 }
7427
7428 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7429 {
7430         struct pci_dev *pdev = dev->pdev;
7431         u16 gcfgc = 0;
7432
7433         pci_read_config_word(pdev, GCFGC, &gcfgc);
7434
7435         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7436                 return 133333;
7437         else {
7438                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7439                 case GC_DISPLAY_CLOCK_333_MHZ:
7440                         return 333333;
7441                 default:
7442                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7443                         return 190000;
7444                 }
7445         }
7446 }
7447
7448 static int i865_get_display_clock_speed(struct drm_device *dev)
7449 {
7450         return 266667;
7451 }
7452
7453 static int i85x_get_display_clock_speed(struct drm_device *dev)
7454 {
7455         struct pci_dev *pdev = dev->pdev;
7456         u16 hpllcc = 0;
7457
7458         /*
7459          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7460          * encoding is different :(
7461          * FIXME is this the right way to detect 852GM/852GMV?
7462          */
7463         if (pdev->revision == 0x1)
7464                 return 133333;
7465
7466         pci_bus_read_config_word(pdev->bus,
7467                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7468
7469         /* Assume that the hardware is in the high speed state.  This
7470          * should be the default.
7471          */
7472         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7473         case GC_CLOCK_133_200:
7474         case GC_CLOCK_133_200_2:
7475         case GC_CLOCK_100_200:
7476                 return 200000;
7477         case GC_CLOCK_166_250:
7478                 return 250000;
7479         case GC_CLOCK_100_133:
7480                 return 133333;
7481         case GC_CLOCK_133_266:
7482         case GC_CLOCK_133_266_2:
7483         case GC_CLOCK_166_266:
7484                 return 266667;
7485         }
7486
7487         /* Shouldn't happen */
7488         return 0;
7489 }
7490
7491 static int i830_get_display_clock_speed(struct drm_device *dev)
7492 {
7493         return 133333;
7494 }
7495
7496 static unsigned int intel_hpll_vco(struct drm_device *dev)
7497 {
7498         struct drm_i915_private *dev_priv = to_i915(dev);
7499         static const unsigned int blb_vco[8] = {
7500                 [0] = 3200000,
7501                 [1] = 4000000,
7502                 [2] = 5333333,
7503                 [3] = 4800000,
7504                 [4] = 6400000,
7505         };
7506         static const unsigned int pnv_vco[8] = {
7507                 [0] = 3200000,
7508                 [1] = 4000000,
7509                 [2] = 5333333,
7510                 [3] = 4800000,
7511                 [4] = 2666667,
7512         };
7513         static const unsigned int cl_vco[8] = {
7514                 [0] = 3200000,
7515                 [1] = 4000000,
7516                 [2] = 5333333,
7517                 [3] = 6400000,
7518                 [4] = 3333333,
7519                 [5] = 3566667,
7520                 [6] = 4266667,
7521         };
7522         static const unsigned int elk_vco[8] = {
7523                 [0] = 3200000,
7524                 [1] = 4000000,
7525                 [2] = 5333333,
7526                 [3] = 4800000,
7527         };
7528         static const unsigned int ctg_vco[8] = {
7529                 [0] = 3200000,
7530                 [1] = 4000000,
7531                 [2] = 5333333,
7532                 [3] = 6400000,
7533                 [4] = 2666667,
7534                 [5] = 4266667,
7535         };
7536         const unsigned int *vco_table;
7537         unsigned int vco;
7538         uint8_t tmp = 0;
7539
7540         /* FIXME other chipsets? */
7541         if (IS_GM45(dev))
7542                 vco_table = ctg_vco;
7543         else if (IS_G4X(dev))
7544                 vco_table = elk_vco;
7545         else if (IS_CRESTLINE(dev))
7546                 vco_table = cl_vco;
7547         else if (IS_PINEVIEW(dev))
7548                 vco_table = pnv_vco;
7549         else if (IS_G33(dev))
7550                 vco_table = blb_vco;
7551         else
7552                 return 0;
7553
7554         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7555
7556         vco = vco_table[tmp & 0x7];
7557         if (vco == 0)
7558                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7559         else
7560                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7561
7562         return vco;
7563 }
7564
7565 static int gm45_get_display_clock_speed(struct drm_device *dev)
7566 {
7567         struct pci_dev *pdev = dev->pdev;
7568         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7569         uint16_t tmp = 0;
7570
7571         pci_read_config_word(pdev, GCFGC, &tmp);
7572
7573         cdclk_sel = (tmp >> 12) & 0x1;
7574
7575         switch (vco) {
7576         case 2666667:
7577         case 4000000:
7578         case 5333333:
7579                 return cdclk_sel ? 333333 : 222222;
7580         case 3200000:
7581                 return cdclk_sel ? 320000 : 228571;
7582         default:
7583                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7584                 return 222222;
7585         }
7586 }
7587
7588 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7589 {
7590         struct pci_dev *pdev = dev->pdev;
7591         static const uint8_t div_3200[] = { 16, 10,  8 };
7592         static const uint8_t div_4000[] = { 20, 12, 10 };
7593         static const uint8_t div_5333[] = { 24, 16, 14 };
7594         const uint8_t *div_table;
7595         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7596         uint16_t tmp = 0;
7597
7598         pci_read_config_word(pdev, GCFGC, &tmp);
7599
7600         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7601
7602         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7603                 goto fail;
7604
7605         switch (vco) {
7606         case 3200000:
7607                 div_table = div_3200;
7608                 break;
7609         case 4000000:
7610                 div_table = div_4000;
7611                 break;
7612         case 5333333:
7613                 div_table = div_5333;
7614                 break;
7615         default:
7616                 goto fail;
7617         }
7618
7619         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7620
7621 fail:
7622         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7623         return 200000;
7624 }
7625
7626 static int g33_get_display_clock_speed(struct drm_device *dev)
7627 {
7628         struct pci_dev *pdev = dev->pdev;
7629         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7630         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7631         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7632         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7633         const uint8_t *div_table;
7634         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7635         uint16_t tmp = 0;
7636
7637         pci_read_config_word(pdev, GCFGC, &tmp);
7638
7639         cdclk_sel = (tmp >> 4) & 0x7;
7640
7641         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7642                 goto fail;
7643
7644         switch (vco) {
7645         case 3200000:
7646                 div_table = div_3200;
7647                 break;
7648         case 4000000:
7649                 div_table = div_4000;
7650                 break;
7651         case 4800000:
7652                 div_table = div_4800;
7653                 break;
7654         case 5333333:
7655                 div_table = div_5333;
7656                 break;
7657         default:
7658                 goto fail;
7659         }
7660
7661         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7662
7663 fail:
7664         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7665         return 190476;
7666 }
7667
7668 static void
7669 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7670 {
7671         while (*num > DATA_LINK_M_N_MASK ||
7672                *den > DATA_LINK_M_N_MASK) {
7673                 *num >>= 1;
7674                 *den >>= 1;
7675         }
7676 }
7677
7678 static void compute_m_n(unsigned int m, unsigned int n,
7679                         uint32_t *ret_m, uint32_t *ret_n)
7680 {
7681         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7682         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7683         intel_reduce_m_n_ratio(ret_m, ret_n);
7684 }
7685
7686 void
7687 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7688                        int pixel_clock, int link_clock,
7689                        struct intel_link_m_n *m_n)
7690 {
7691         m_n->tu = 64;
7692
7693         compute_m_n(bits_per_pixel * pixel_clock,
7694                     link_clock * nlanes * 8,
7695                     &m_n->gmch_m, &m_n->gmch_n);
7696
7697         compute_m_n(pixel_clock, link_clock,
7698                     &m_n->link_m, &m_n->link_n);
7699 }
7700
7701 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7702 {
7703         if (i915.panel_use_ssc >= 0)
7704                 return i915.panel_use_ssc != 0;
7705         return dev_priv->vbt.lvds_use_ssc
7706                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7707 }
7708
7709 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7710 {
7711         return (1 << dpll->n) << 16 | dpll->m2;
7712 }
7713
7714 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7715 {
7716         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7717 }
7718
7719 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7720                                      struct intel_crtc_state *crtc_state,
7721                                      struct dpll *reduced_clock)
7722 {
7723         struct drm_device *dev = crtc->base.dev;
7724         u32 fp, fp2 = 0;
7725
7726         if (IS_PINEVIEW(dev)) {
7727                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7728                 if (reduced_clock)
7729                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7730         } else {
7731                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7732                 if (reduced_clock)
7733                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7734         }
7735
7736         crtc_state->dpll_hw_state.fp0 = fp;
7737
7738         crtc->lowfreq_avail = false;
7739         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7740             reduced_clock) {
7741                 crtc_state->dpll_hw_state.fp1 = fp2;
7742                 crtc->lowfreq_avail = true;
7743         } else {
7744                 crtc_state->dpll_hw_state.fp1 = fp;
7745         }
7746 }
7747
7748 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7749                 pipe)
7750 {
7751         u32 reg_val;
7752
7753         /*
7754          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7755          * and set it to a reasonable value instead.
7756          */
7757         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7758         reg_val &= 0xffffff00;
7759         reg_val |= 0x00000030;
7760         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7761
7762         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7763         reg_val &= 0x8cffffff;
7764         reg_val = 0x8c000000;
7765         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7766
7767         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7768         reg_val &= 0xffffff00;
7769         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7770
7771         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7772         reg_val &= 0x00ffffff;
7773         reg_val |= 0xb0000000;
7774         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7775 }
7776
7777 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7778                                          struct intel_link_m_n *m_n)
7779 {
7780         struct drm_device *dev = crtc->base.dev;
7781         struct drm_i915_private *dev_priv = to_i915(dev);
7782         int pipe = crtc->pipe;
7783
7784         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7785         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7786         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7787         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7788 }
7789
7790 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7791                                          struct intel_link_m_n *m_n,
7792                                          struct intel_link_m_n *m2_n2)
7793 {
7794         struct drm_device *dev = crtc->base.dev;
7795         struct drm_i915_private *dev_priv = to_i915(dev);
7796         int pipe = crtc->pipe;
7797         enum transcoder transcoder = crtc->config->cpu_transcoder;
7798
7799         if (INTEL_INFO(dev)->gen >= 5) {
7800                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7801                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7802                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7803                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7804                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7805                  * for gen < 8) and if DRRS is supported (to make sure the
7806                  * registers are not unnecessarily accessed).
7807                  */
7808                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7809                         crtc->config->has_drrs) {
7810                         I915_WRITE(PIPE_DATA_M2(transcoder),
7811                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7812                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7813                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7814                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7815                 }
7816         } else {
7817                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7818                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7819                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7820                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7821         }
7822 }
7823
7824 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7825 {
7826         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7827
7828         if (m_n == M1_N1) {
7829                 dp_m_n = &crtc->config->dp_m_n;
7830                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7831         } else if (m_n == M2_N2) {
7832
7833                 /*
7834                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7835                  * needs to be programmed into M1_N1.
7836                  */
7837                 dp_m_n = &crtc->config->dp_m2_n2;
7838         } else {
7839                 DRM_ERROR("Unsupported divider value\n");
7840                 return;
7841         }
7842
7843         if (crtc->config->has_pch_encoder)
7844                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7845         else
7846                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7847 }
7848
7849 static void vlv_compute_dpll(struct intel_crtc *crtc,
7850                              struct intel_crtc_state *pipe_config)
7851 {
7852         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7853                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7854         if (crtc->pipe != PIPE_A)
7855                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7856
7857         /* DPLL not used with DSI, but still need the rest set up */
7858         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7859                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7860                         DPLL_EXT_BUFFER_ENABLE_VLV;
7861
7862         pipe_config->dpll_hw_state.dpll_md =
7863                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7864 }
7865
7866 static void chv_compute_dpll(struct intel_crtc *crtc,
7867                              struct intel_crtc_state *pipe_config)
7868 {
7869         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7870                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7871         if (crtc->pipe != PIPE_A)
7872                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7873
7874         /* DPLL not used with DSI, but still need the rest set up */
7875         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7876                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7877
7878         pipe_config->dpll_hw_state.dpll_md =
7879                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7880 }
7881
7882 static void vlv_prepare_pll(struct intel_crtc *crtc,
7883                             const struct intel_crtc_state *pipe_config)
7884 {
7885         struct drm_device *dev = crtc->base.dev;
7886         struct drm_i915_private *dev_priv = to_i915(dev);
7887         enum pipe pipe = crtc->pipe;
7888         u32 mdiv;
7889         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7890         u32 coreclk, reg_val;
7891
7892         /* Enable Refclk */
7893         I915_WRITE(DPLL(pipe),
7894                    pipe_config->dpll_hw_state.dpll &
7895                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7896
7897         /* No need to actually set up the DPLL with DSI */
7898         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7899                 return;
7900
7901         mutex_lock(&dev_priv->sb_lock);
7902
7903         bestn = pipe_config->dpll.n;
7904         bestm1 = pipe_config->dpll.m1;
7905         bestm2 = pipe_config->dpll.m2;
7906         bestp1 = pipe_config->dpll.p1;
7907         bestp2 = pipe_config->dpll.p2;
7908
7909         /* See eDP HDMI DPIO driver vbios notes doc */
7910
7911         /* PLL B needs special handling */
7912         if (pipe == PIPE_B)
7913                 vlv_pllb_recal_opamp(dev_priv, pipe);
7914
7915         /* Set up Tx target for periodic Rcomp update */
7916         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7917
7918         /* Disable target IRef on PLL */
7919         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7920         reg_val &= 0x00ffffff;
7921         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7922
7923         /* Disable fast lock */
7924         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7925
7926         /* Set idtafcrecal before PLL is enabled */
7927         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7928         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7929         mdiv |= ((bestn << DPIO_N_SHIFT));
7930         mdiv |= (1 << DPIO_K_SHIFT);
7931
7932         /*
7933          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7934          * but we don't support that).
7935          * Note: don't use the DAC post divider as it seems unstable.
7936          */
7937         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7938         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7939
7940         mdiv |= DPIO_ENABLE_CALIBRATION;
7941         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7942
7943         /* Set HBR and RBR LPF coefficients */
7944         if (pipe_config->port_clock == 162000 ||
7945             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7946             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7947                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7948                                  0x009f0003);
7949         else
7950                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7951                                  0x00d0000f);
7952
7953         if (intel_crtc_has_dp_encoder(pipe_config)) {
7954                 /* Use SSC source */
7955                 if (pipe == PIPE_A)
7956                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7957                                          0x0df40000);
7958                 else
7959                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7960                                          0x0df70000);
7961         } else { /* HDMI or VGA */
7962                 /* Use bend source */
7963                 if (pipe == PIPE_A)
7964                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7965                                          0x0df70000);
7966                 else
7967                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7968                                          0x0df40000);
7969         }
7970
7971         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7972         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7973         if (intel_crtc_has_dp_encoder(crtc->config))
7974                 coreclk |= 0x01000000;
7975         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7976
7977         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7978         mutex_unlock(&dev_priv->sb_lock);
7979 }
7980
7981 static void chv_prepare_pll(struct intel_crtc *crtc,
7982                             const struct intel_crtc_state *pipe_config)
7983 {
7984         struct drm_device *dev = crtc->base.dev;
7985         struct drm_i915_private *dev_priv = to_i915(dev);
7986         enum pipe pipe = crtc->pipe;
7987         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7988         u32 loopfilter, tribuf_calcntr;
7989         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7990         u32 dpio_val;
7991         int vco;
7992
7993         /* Enable Refclk and SSC */
7994         I915_WRITE(DPLL(pipe),
7995                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7996
7997         /* No need to actually set up the DPLL with DSI */
7998         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7999                 return;
8000
8001         bestn = pipe_config->dpll.n;
8002         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8003         bestm1 = pipe_config->dpll.m1;
8004         bestm2 = pipe_config->dpll.m2 >> 22;
8005         bestp1 = pipe_config->dpll.p1;
8006         bestp2 = pipe_config->dpll.p2;
8007         vco = pipe_config->dpll.vco;
8008         dpio_val = 0;
8009         loopfilter = 0;
8010
8011         mutex_lock(&dev_priv->sb_lock);
8012
8013         /* p1 and p2 divider */
8014         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8015                         5 << DPIO_CHV_S1_DIV_SHIFT |
8016                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8017                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8018                         1 << DPIO_CHV_K_DIV_SHIFT);
8019
8020         /* Feedback post-divider - m2 */
8021         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8022
8023         /* Feedback refclk divider - n and m1 */
8024         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8025                         DPIO_CHV_M1_DIV_BY_2 |
8026                         1 << DPIO_CHV_N_DIV_SHIFT);
8027
8028         /* M2 fraction division */
8029         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8030
8031         /* M2 fraction division enable */
8032         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8033         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8034         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8035         if (bestm2_frac)
8036                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8037         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8038
8039         /* Program digital lock detect threshold */
8040         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8041         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8042                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8043         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8044         if (!bestm2_frac)
8045                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8046         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8047
8048         /* Loop filter */
8049         if (vco == 5400000) {
8050                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8051                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8052                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8053                 tribuf_calcntr = 0x9;
8054         } else if (vco <= 6200000) {
8055                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8056                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8057                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8058                 tribuf_calcntr = 0x9;
8059         } else if (vco <= 6480000) {
8060                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8061                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8062                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8063                 tribuf_calcntr = 0x8;
8064         } else {
8065                 /* Not supported. Apply the same limits as in the max case */
8066                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8067                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8068                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8069                 tribuf_calcntr = 0;
8070         }
8071         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8072
8073         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8074         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8075         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8076         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8077
8078         /* AFC Recal */
8079         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8080                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8081                         DPIO_AFC_RECAL);
8082
8083         mutex_unlock(&dev_priv->sb_lock);
8084 }
8085
8086 /**
8087  * vlv_force_pll_on - forcibly enable just the PLL
8088  * @dev_priv: i915 private structure
8089  * @pipe: pipe PLL to enable
8090  * @dpll: PLL configuration
8091  *
8092  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8093  * in cases where we need the PLL enabled even when @pipe is not going to
8094  * be enabled.
8095  */
8096 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8097                      const struct dpll *dpll)
8098 {
8099         struct intel_crtc *crtc =
8100                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8101         struct intel_crtc_state *pipe_config;
8102
8103         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8104         if (!pipe_config)
8105                 return -ENOMEM;
8106
8107         pipe_config->base.crtc = &crtc->base;
8108         pipe_config->pixel_multiplier = 1;
8109         pipe_config->dpll = *dpll;
8110
8111         if (IS_CHERRYVIEW(dev)) {
8112                 chv_compute_dpll(crtc, pipe_config);
8113                 chv_prepare_pll(crtc, pipe_config);
8114                 chv_enable_pll(crtc, pipe_config);
8115         } else {
8116                 vlv_compute_dpll(crtc, pipe_config);
8117                 vlv_prepare_pll(crtc, pipe_config);
8118                 vlv_enable_pll(crtc, pipe_config);
8119         }
8120
8121         kfree(pipe_config);
8122
8123         return 0;
8124 }
8125
8126 /**
8127  * vlv_force_pll_off - forcibly disable just the PLL
8128  * @dev_priv: i915 private structure
8129  * @pipe: pipe PLL to disable
8130  *
8131  * Disable the PLL for @pipe. To be used in cases where we need
8132  * the PLL enabled even when @pipe is not going to be enabled.
8133  */
8134 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8135 {
8136         if (IS_CHERRYVIEW(dev))
8137                 chv_disable_pll(to_i915(dev), pipe);
8138         else
8139                 vlv_disable_pll(to_i915(dev), pipe);
8140 }
8141
8142 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8143                               struct intel_crtc_state *crtc_state,
8144                               struct dpll *reduced_clock)
8145 {
8146         struct drm_device *dev = crtc->base.dev;
8147         struct drm_i915_private *dev_priv = to_i915(dev);
8148         u32 dpll;
8149         struct dpll *clock = &crtc_state->dpll;
8150
8151         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8152
8153         dpll = DPLL_VGA_MODE_DIS;
8154
8155         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8156                 dpll |= DPLLB_MODE_LVDS;
8157         else
8158                 dpll |= DPLLB_MODE_DAC_SERIAL;
8159
8160         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8161                 dpll |= (crtc_state->pixel_multiplier - 1)
8162                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8163         }
8164
8165         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8166             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8167                 dpll |= DPLL_SDVO_HIGH_SPEED;
8168
8169         if (intel_crtc_has_dp_encoder(crtc_state))
8170                 dpll |= DPLL_SDVO_HIGH_SPEED;
8171
8172         /* compute bitmask from p1 value */
8173         if (IS_PINEVIEW(dev))
8174                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8175         else {
8176                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8177                 if (IS_G4X(dev) && reduced_clock)
8178                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8179         }
8180         switch (clock->p2) {
8181         case 5:
8182                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8183                 break;
8184         case 7:
8185                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8186                 break;
8187         case 10:
8188                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8189                 break;
8190         case 14:
8191                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8192                 break;
8193         }
8194         if (INTEL_INFO(dev)->gen >= 4)
8195                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8196
8197         if (crtc_state->sdvo_tv_clock)
8198                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8199         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8200                  intel_panel_use_ssc(dev_priv))
8201                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8202         else
8203                 dpll |= PLL_REF_INPUT_DREFCLK;
8204
8205         dpll |= DPLL_VCO_ENABLE;
8206         crtc_state->dpll_hw_state.dpll = dpll;
8207
8208         if (INTEL_INFO(dev)->gen >= 4) {
8209                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8210                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8211                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8212         }
8213 }
8214
8215 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8216                               struct intel_crtc_state *crtc_state,
8217                               struct dpll *reduced_clock)
8218 {
8219         struct drm_device *dev = crtc->base.dev;
8220         struct drm_i915_private *dev_priv = to_i915(dev);
8221         u32 dpll;
8222         struct dpll *clock = &crtc_state->dpll;
8223
8224         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8225
8226         dpll = DPLL_VGA_MODE_DIS;
8227
8228         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8229                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8230         } else {
8231                 if (clock->p1 == 2)
8232                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8233                 else
8234                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8235                 if (clock->p2 == 4)
8236                         dpll |= PLL_P2_DIVIDE_BY_4;
8237         }
8238
8239         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8240                 dpll |= DPLL_DVO_2X_MODE;
8241
8242         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8243             intel_panel_use_ssc(dev_priv))
8244                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8245         else
8246                 dpll |= PLL_REF_INPUT_DREFCLK;
8247
8248         dpll |= DPLL_VCO_ENABLE;
8249         crtc_state->dpll_hw_state.dpll = dpll;
8250 }
8251
8252 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8253 {
8254         struct drm_device *dev = intel_crtc->base.dev;
8255         struct drm_i915_private *dev_priv = to_i915(dev);
8256         enum pipe pipe = intel_crtc->pipe;
8257         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8258         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8259         uint32_t crtc_vtotal, crtc_vblank_end;
8260         int vsyncshift = 0;
8261
8262         /* We need to be careful not to changed the adjusted mode, for otherwise
8263          * the hw state checker will get angry at the mismatch. */
8264         crtc_vtotal = adjusted_mode->crtc_vtotal;
8265         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8266
8267         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8268                 /* the chip adds 2 halflines automatically */
8269                 crtc_vtotal -= 1;
8270                 crtc_vblank_end -= 1;
8271
8272                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8273                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8274                 else
8275                         vsyncshift = adjusted_mode->crtc_hsync_start -
8276                                 adjusted_mode->crtc_htotal / 2;
8277                 if (vsyncshift < 0)
8278                         vsyncshift += adjusted_mode->crtc_htotal;
8279         }
8280
8281         if (INTEL_INFO(dev)->gen > 3)
8282                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8283
8284         I915_WRITE(HTOTAL(cpu_transcoder),
8285                    (adjusted_mode->crtc_hdisplay - 1) |
8286                    ((adjusted_mode->crtc_htotal - 1) << 16));
8287         I915_WRITE(HBLANK(cpu_transcoder),
8288                    (adjusted_mode->crtc_hblank_start - 1) |
8289                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8290         I915_WRITE(HSYNC(cpu_transcoder),
8291                    (adjusted_mode->crtc_hsync_start - 1) |
8292                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8293
8294         I915_WRITE(VTOTAL(cpu_transcoder),
8295                    (adjusted_mode->crtc_vdisplay - 1) |
8296                    ((crtc_vtotal - 1) << 16));
8297         I915_WRITE(VBLANK(cpu_transcoder),
8298                    (adjusted_mode->crtc_vblank_start - 1) |
8299                    ((crtc_vblank_end - 1) << 16));
8300         I915_WRITE(VSYNC(cpu_transcoder),
8301                    (adjusted_mode->crtc_vsync_start - 1) |
8302                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8303
8304         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8305          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8306          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8307          * bits. */
8308         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8309             (pipe == PIPE_B || pipe == PIPE_C))
8310                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8311
8312 }
8313
8314 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8315 {
8316         struct drm_device *dev = intel_crtc->base.dev;
8317         struct drm_i915_private *dev_priv = to_i915(dev);
8318         enum pipe pipe = intel_crtc->pipe;
8319
8320         /* pipesrc controls the size that is scaled from, which should
8321          * always be the user's requested size.
8322          */
8323         I915_WRITE(PIPESRC(pipe),
8324                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8325                    (intel_crtc->config->pipe_src_h - 1));
8326 }
8327
8328 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8329                                    struct intel_crtc_state *pipe_config)
8330 {
8331         struct drm_device *dev = crtc->base.dev;
8332         struct drm_i915_private *dev_priv = to_i915(dev);
8333         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8334         uint32_t tmp;
8335
8336         tmp = I915_READ(HTOTAL(cpu_transcoder));
8337         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8338         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8339         tmp = I915_READ(HBLANK(cpu_transcoder));
8340         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8341         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8342         tmp = I915_READ(HSYNC(cpu_transcoder));
8343         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8344         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8345
8346         tmp = I915_READ(VTOTAL(cpu_transcoder));
8347         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8348         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8349         tmp = I915_READ(VBLANK(cpu_transcoder));
8350         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8351         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8352         tmp = I915_READ(VSYNC(cpu_transcoder));
8353         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8354         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8355
8356         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8357                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8358                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8359                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8360         }
8361 }
8362
8363 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8364                                     struct intel_crtc_state *pipe_config)
8365 {
8366         struct drm_device *dev = crtc->base.dev;
8367         struct drm_i915_private *dev_priv = to_i915(dev);
8368         u32 tmp;
8369
8370         tmp = I915_READ(PIPESRC(crtc->pipe));
8371         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8372         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8373
8374         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8375         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8376 }
8377
8378 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8379                                  struct intel_crtc_state *pipe_config)
8380 {
8381         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8382         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8383         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8384         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8385
8386         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8387         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8388         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8389         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8390
8391         mode->flags = pipe_config->base.adjusted_mode.flags;
8392         mode->type = DRM_MODE_TYPE_DRIVER;
8393
8394         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8395         mode->flags |= pipe_config->base.adjusted_mode.flags;
8396
8397         mode->hsync = drm_mode_hsync(mode);
8398         mode->vrefresh = drm_mode_vrefresh(mode);
8399         drm_mode_set_name(mode);
8400 }
8401
8402 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8403 {
8404         struct drm_device *dev = intel_crtc->base.dev;
8405         struct drm_i915_private *dev_priv = to_i915(dev);
8406         uint32_t pipeconf;
8407
8408         pipeconf = 0;
8409
8410         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8411             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8412                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8413
8414         if (intel_crtc->config->double_wide)
8415                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8416
8417         /* only g4x and later have fancy bpc/dither controls */
8418         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8419                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8420                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8421                         pipeconf |= PIPECONF_DITHER_EN |
8422                                     PIPECONF_DITHER_TYPE_SP;
8423
8424                 switch (intel_crtc->config->pipe_bpp) {
8425                 case 18:
8426                         pipeconf |= PIPECONF_6BPC;
8427                         break;
8428                 case 24:
8429                         pipeconf |= PIPECONF_8BPC;
8430                         break;
8431                 case 30:
8432                         pipeconf |= PIPECONF_10BPC;
8433                         break;
8434                 default:
8435                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8436                         BUG();
8437                 }
8438         }
8439
8440         if (HAS_PIPE_CXSR(dev)) {
8441                 if (intel_crtc->lowfreq_avail) {
8442                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8443                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8444                 } else {
8445                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8446                 }
8447         }
8448
8449         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8450                 if (INTEL_INFO(dev)->gen < 4 ||
8451                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8452                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8453                 else
8454                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8455         } else
8456                 pipeconf |= PIPECONF_PROGRESSIVE;
8457
8458         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8459              intel_crtc->config->limited_color_range)
8460                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8461
8462         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8463         POSTING_READ(PIPECONF(intel_crtc->pipe));
8464 }
8465
8466 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8467                                    struct intel_crtc_state *crtc_state)
8468 {
8469         struct drm_device *dev = crtc->base.dev;
8470         struct drm_i915_private *dev_priv = to_i915(dev);
8471         const struct intel_limit *limit;
8472         int refclk = 48000;
8473
8474         memset(&crtc_state->dpll_hw_state, 0,
8475                sizeof(crtc_state->dpll_hw_state));
8476
8477         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8478                 if (intel_panel_use_ssc(dev_priv)) {
8479                         refclk = dev_priv->vbt.lvds_ssc_freq;
8480                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8481                 }
8482
8483                 limit = &intel_limits_i8xx_lvds;
8484         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8485                 limit = &intel_limits_i8xx_dvo;
8486         } else {
8487                 limit = &intel_limits_i8xx_dac;
8488         }
8489
8490         if (!crtc_state->clock_set &&
8491             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8492                                  refclk, NULL, &crtc_state->dpll)) {
8493                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8494                 return -EINVAL;
8495         }
8496
8497         i8xx_compute_dpll(crtc, crtc_state, NULL);
8498
8499         return 0;
8500 }
8501
8502 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8503                                   struct intel_crtc_state *crtc_state)
8504 {
8505         struct drm_device *dev = crtc->base.dev;
8506         struct drm_i915_private *dev_priv = to_i915(dev);
8507         const struct intel_limit *limit;
8508         int refclk = 96000;
8509
8510         memset(&crtc_state->dpll_hw_state, 0,
8511                sizeof(crtc_state->dpll_hw_state));
8512
8513         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8514                 if (intel_panel_use_ssc(dev_priv)) {
8515                         refclk = dev_priv->vbt.lvds_ssc_freq;
8516                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8517                 }
8518
8519                 if (intel_is_dual_link_lvds(dev))
8520                         limit = &intel_limits_g4x_dual_channel_lvds;
8521                 else
8522                         limit = &intel_limits_g4x_single_channel_lvds;
8523         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8524                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8525                 limit = &intel_limits_g4x_hdmi;
8526         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8527                 limit = &intel_limits_g4x_sdvo;
8528         } else {
8529                 /* The option is for other outputs */
8530                 limit = &intel_limits_i9xx_sdvo;
8531         }
8532
8533         if (!crtc_state->clock_set &&
8534             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8535                                 refclk, NULL, &crtc_state->dpll)) {
8536                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8537                 return -EINVAL;
8538         }
8539
8540         i9xx_compute_dpll(crtc, crtc_state, NULL);
8541
8542         return 0;
8543 }
8544
8545 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8546                                   struct intel_crtc_state *crtc_state)
8547 {
8548         struct drm_device *dev = crtc->base.dev;
8549         struct drm_i915_private *dev_priv = to_i915(dev);
8550         const struct intel_limit *limit;
8551         int refclk = 96000;
8552
8553         memset(&crtc_state->dpll_hw_state, 0,
8554                sizeof(crtc_state->dpll_hw_state));
8555
8556         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8557                 if (intel_panel_use_ssc(dev_priv)) {
8558                         refclk = dev_priv->vbt.lvds_ssc_freq;
8559                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8560                 }
8561
8562                 limit = &intel_limits_pineview_lvds;
8563         } else {
8564                 limit = &intel_limits_pineview_sdvo;
8565         }
8566
8567         if (!crtc_state->clock_set &&
8568             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8569                                 refclk, NULL, &crtc_state->dpll)) {
8570                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8571                 return -EINVAL;
8572         }
8573
8574         i9xx_compute_dpll(crtc, crtc_state, NULL);
8575
8576         return 0;
8577 }
8578
8579 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8580                                    struct intel_crtc_state *crtc_state)
8581 {
8582         struct drm_device *dev = crtc->base.dev;
8583         struct drm_i915_private *dev_priv = to_i915(dev);
8584         const struct intel_limit *limit;
8585         int refclk = 96000;
8586
8587         memset(&crtc_state->dpll_hw_state, 0,
8588                sizeof(crtc_state->dpll_hw_state));
8589
8590         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8591                 if (intel_panel_use_ssc(dev_priv)) {
8592                         refclk = dev_priv->vbt.lvds_ssc_freq;
8593                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8594                 }
8595
8596                 limit = &intel_limits_i9xx_lvds;
8597         } else {
8598                 limit = &intel_limits_i9xx_sdvo;
8599         }
8600
8601         if (!crtc_state->clock_set &&
8602             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8603                                  refclk, NULL, &crtc_state->dpll)) {
8604                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8605                 return -EINVAL;
8606         }
8607
8608         i9xx_compute_dpll(crtc, crtc_state, NULL);
8609
8610         return 0;
8611 }
8612
8613 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8614                                   struct intel_crtc_state *crtc_state)
8615 {
8616         int refclk = 100000;
8617         const struct intel_limit *limit = &intel_limits_chv;
8618
8619         memset(&crtc_state->dpll_hw_state, 0,
8620                sizeof(crtc_state->dpll_hw_state));
8621
8622         if (!crtc_state->clock_set &&
8623             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8624                                 refclk, NULL, &crtc_state->dpll)) {
8625                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8626                 return -EINVAL;
8627         }
8628
8629         chv_compute_dpll(crtc, crtc_state);
8630
8631         return 0;
8632 }
8633
8634 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8635                                   struct intel_crtc_state *crtc_state)
8636 {
8637         int refclk = 100000;
8638         const struct intel_limit *limit = &intel_limits_vlv;
8639
8640         memset(&crtc_state->dpll_hw_state, 0,
8641                sizeof(crtc_state->dpll_hw_state));
8642
8643         if (!crtc_state->clock_set &&
8644             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8645                                 refclk, NULL, &crtc_state->dpll)) {
8646                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8647                 return -EINVAL;
8648         }
8649
8650         vlv_compute_dpll(crtc, crtc_state);
8651
8652         return 0;
8653 }
8654
8655 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8656                                  struct intel_crtc_state *pipe_config)
8657 {
8658         struct drm_device *dev = crtc->base.dev;
8659         struct drm_i915_private *dev_priv = to_i915(dev);
8660         uint32_t tmp;
8661
8662         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8663                 return;
8664
8665         tmp = I915_READ(PFIT_CONTROL);
8666         if (!(tmp & PFIT_ENABLE))
8667                 return;
8668
8669         /* Check whether the pfit is attached to our pipe. */
8670         if (INTEL_INFO(dev)->gen < 4) {
8671                 if (crtc->pipe != PIPE_B)
8672                         return;
8673         } else {
8674                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8675                         return;
8676         }
8677
8678         pipe_config->gmch_pfit.control = tmp;
8679         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8680 }
8681
8682 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8683                                struct intel_crtc_state *pipe_config)
8684 {
8685         struct drm_device *dev = crtc->base.dev;
8686         struct drm_i915_private *dev_priv = to_i915(dev);
8687         int pipe = pipe_config->cpu_transcoder;
8688         struct dpll clock;
8689         u32 mdiv;
8690         int refclk = 100000;
8691
8692         /* In case of DSI, DPLL will not be used */
8693         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8694                 return;
8695
8696         mutex_lock(&dev_priv->sb_lock);
8697         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8698         mutex_unlock(&dev_priv->sb_lock);
8699
8700         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8701         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8702         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8703         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8704         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8705
8706         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8707 }
8708
8709 static void
8710 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8711                               struct intel_initial_plane_config *plane_config)
8712 {
8713         struct drm_device *dev = crtc->base.dev;
8714         struct drm_i915_private *dev_priv = to_i915(dev);
8715         u32 val, base, offset;
8716         int pipe = crtc->pipe, plane = crtc->plane;
8717         int fourcc, pixel_format;
8718         unsigned int aligned_height;
8719         struct drm_framebuffer *fb;
8720         struct intel_framebuffer *intel_fb;
8721
8722         val = I915_READ(DSPCNTR(plane));
8723         if (!(val & DISPLAY_PLANE_ENABLE))
8724                 return;
8725
8726         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8727         if (!intel_fb) {
8728                 DRM_DEBUG_KMS("failed to alloc fb\n");
8729                 return;
8730         }
8731
8732         fb = &intel_fb->base;
8733
8734         if (INTEL_INFO(dev)->gen >= 4) {
8735                 if (val & DISPPLANE_TILED) {
8736                         plane_config->tiling = I915_TILING_X;
8737                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8738                 }
8739         }
8740
8741         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8742         fourcc = i9xx_format_to_fourcc(pixel_format);
8743         fb->pixel_format = fourcc;
8744         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8745
8746         if (INTEL_INFO(dev)->gen >= 4) {
8747                 if (plane_config->tiling)
8748                         offset = I915_READ(DSPTILEOFF(plane));
8749                 else
8750                         offset = I915_READ(DSPLINOFF(plane));
8751                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8752         } else {
8753                 base = I915_READ(DSPADDR(plane));
8754         }
8755         plane_config->base = base;
8756
8757         val = I915_READ(PIPESRC(pipe));
8758         fb->width = ((val >> 16) & 0xfff) + 1;
8759         fb->height = ((val >> 0) & 0xfff) + 1;
8760
8761         val = I915_READ(DSPSTRIDE(pipe));
8762         fb->pitches[0] = val & 0xffffffc0;
8763
8764         aligned_height = intel_fb_align_height(dev, fb->height,
8765                                                fb->pixel_format,
8766                                                fb->modifier[0]);
8767
8768         plane_config->size = fb->pitches[0] * aligned_height;
8769
8770         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8771                       pipe_name(pipe), plane, fb->width, fb->height,
8772                       fb->bits_per_pixel, base, fb->pitches[0],
8773                       plane_config->size);
8774
8775         plane_config->fb = intel_fb;
8776 }
8777
8778 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8779                                struct intel_crtc_state *pipe_config)
8780 {
8781         struct drm_device *dev = crtc->base.dev;
8782         struct drm_i915_private *dev_priv = to_i915(dev);
8783         int pipe = pipe_config->cpu_transcoder;
8784         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8785         struct dpll clock;
8786         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8787         int refclk = 100000;
8788
8789         /* In case of DSI, DPLL will not be used */
8790         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8791                 return;
8792
8793         mutex_lock(&dev_priv->sb_lock);
8794         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8795         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8796         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8797         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8798         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8799         mutex_unlock(&dev_priv->sb_lock);
8800
8801         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8802         clock.m2 = (pll_dw0 & 0xff) << 22;
8803         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8804                 clock.m2 |= pll_dw2 & 0x3fffff;
8805         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8806         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8807         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8808
8809         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8810 }
8811
8812 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8813                                  struct intel_crtc_state *pipe_config)
8814 {
8815         struct drm_device *dev = crtc->base.dev;
8816         struct drm_i915_private *dev_priv = to_i915(dev);
8817         enum intel_display_power_domain power_domain;
8818         uint32_t tmp;
8819         bool ret;
8820
8821         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8822         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8823                 return false;
8824
8825         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8826         pipe_config->shared_dpll = NULL;
8827
8828         ret = false;
8829
8830         tmp = I915_READ(PIPECONF(crtc->pipe));
8831         if (!(tmp & PIPECONF_ENABLE))
8832                 goto out;
8833
8834         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8835                 switch (tmp & PIPECONF_BPC_MASK) {
8836                 case PIPECONF_6BPC:
8837                         pipe_config->pipe_bpp = 18;
8838                         break;
8839                 case PIPECONF_8BPC:
8840                         pipe_config->pipe_bpp = 24;
8841                         break;
8842                 case PIPECONF_10BPC:
8843                         pipe_config->pipe_bpp = 30;
8844                         break;
8845                 default:
8846                         break;
8847                 }
8848         }
8849
8850         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8851             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8852                 pipe_config->limited_color_range = true;
8853
8854         if (INTEL_INFO(dev)->gen < 4)
8855                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8856
8857         intel_get_pipe_timings(crtc, pipe_config);
8858         intel_get_pipe_src_size(crtc, pipe_config);
8859
8860         i9xx_get_pfit_config(crtc, pipe_config);
8861
8862         if (INTEL_INFO(dev)->gen >= 4) {
8863                 /* No way to read it out on pipes B and C */
8864                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8865                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8866                 else
8867                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8868                 pipe_config->pixel_multiplier =
8869                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8870                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8871                 pipe_config->dpll_hw_state.dpll_md = tmp;
8872         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8873                 tmp = I915_READ(DPLL(crtc->pipe));
8874                 pipe_config->pixel_multiplier =
8875                         ((tmp & SDVO_MULTIPLIER_MASK)
8876                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8877         } else {
8878                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8879                  * port and will be fixed up in the encoder->get_config
8880                  * function. */
8881                 pipe_config->pixel_multiplier = 1;
8882         }
8883         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8884         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8885                 /*
8886                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8887                  * on 830. Filter it out here so that we don't
8888                  * report errors due to that.
8889                  */
8890                 if (IS_I830(dev))
8891                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8892
8893                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8894                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8895         } else {
8896                 /* Mask out read-only status bits. */
8897                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8898                                                      DPLL_PORTC_READY_MASK |
8899                                                      DPLL_PORTB_READY_MASK);
8900         }
8901
8902         if (IS_CHERRYVIEW(dev))
8903                 chv_crtc_clock_get(crtc, pipe_config);
8904         else if (IS_VALLEYVIEW(dev))
8905                 vlv_crtc_clock_get(crtc, pipe_config);
8906         else
8907                 i9xx_crtc_clock_get(crtc, pipe_config);
8908
8909         /*
8910          * Normally the dotclock is filled in by the encoder .get_config()
8911          * but in case the pipe is enabled w/o any ports we need a sane
8912          * default.
8913          */
8914         pipe_config->base.adjusted_mode.crtc_clock =
8915                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8916
8917         ret = true;
8918
8919 out:
8920         intel_display_power_put(dev_priv, power_domain);
8921
8922         return ret;
8923 }
8924
8925 static void ironlake_init_pch_refclk(struct drm_device *dev)
8926 {
8927         struct drm_i915_private *dev_priv = to_i915(dev);
8928         struct intel_encoder *encoder;
8929         int i;
8930         u32 val, final;
8931         bool has_lvds = false;
8932         bool has_cpu_edp = false;
8933         bool has_panel = false;
8934         bool has_ck505 = false;
8935         bool can_ssc = false;
8936         bool using_ssc_source = false;
8937
8938         /* We need to take the global config into account */
8939         for_each_intel_encoder(dev, encoder) {
8940                 switch (encoder->type) {
8941                 case INTEL_OUTPUT_LVDS:
8942                         has_panel = true;
8943                         has_lvds = true;
8944                         break;
8945                 case INTEL_OUTPUT_EDP:
8946                         has_panel = true;
8947                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8948                                 has_cpu_edp = true;
8949                         break;
8950                 default:
8951                         break;
8952                 }
8953         }
8954
8955         if (HAS_PCH_IBX(dev)) {
8956                 has_ck505 = dev_priv->vbt.display_clock_mode;
8957                 can_ssc = has_ck505;
8958         } else {
8959                 has_ck505 = false;
8960                 can_ssc = true;
8961         }
8962
8963         /* Check if any DPLLs are using the SSC source */
8964         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8965                 u32 temp = I915_READ(PCH_DPLL(i));
8966
8967                 if (!(temp & DPLL_VCO_ENABLE))
8968                         continue;
8969
8970                 if ((temp & PLL_REF_INPUT_MASK) ==
8971                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8972                         using_ssc_source = true;
8973                         break;
8974                 }
8975         }
8976
8977         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8978                       has_panel, has_lvds, has_ck505, using_ssc_source);
8979
8980         /* Ironlake: try to setup display ref clock before DPLL
8981          * enabling. This is only under driver's control after
8982          * PCH B stepping, previous chipset stepping should be
8983          * ignoring this setting.
8984          */
8985         val = I915_READ(PCH_DREF_CONTROL);
8986
8987         /* As we must carefully and slowly disable/enable each source in turn,
8988          * compute the final state we want first and check if we need to
8989          * make any changes at all.
8990          */
8991         final = val;
8992         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8993         if (has_ck505)
8994                 final |= DREF_NONSPREAD_CK505_ENABLE;
8995         else
8996                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8997
8998         final &= ~DREF_SSC_SOURCE_MASK;
8999         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9000         final &= ~DREF_SSC1_ENABLE;
9001
9002         if (has_panel) {
9003                 final |= DREF_SSC_SOURCE_ENABLE;
9004
9005                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9006                         final |= DREF_SSC1_ENABLE;
9007
9008                 if (has_cpu_edp) {
9009                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9010                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9011                         else
9012                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9013                 } else
9014                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9015         } else if (using_ssc_source) {
9016                 final |= DREF_SSC_SOURCE_ENABLE;
9017                 final |= DREF_SSC1_ENABLE;
9018         }
9019
9020         if (final == val)
9021                 return;
9022
9023         /* Always enable nonspread source */
9024         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9025
9026         if (has_ck505)
9027                 val |= DREF_NONSPREAD_CK505_ENABLE;
9028         else
9029                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9030
9031         if (has_panel) {
9032                 val &= ~DREF_SSC_SOURCE_MASK;
9033                 val |= DREF_SSC_SOURCE_ENABLE;
9034
9035                 /* SSC must be turned on before enabling the CPU output  */
9036                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9037                         DRM_DEBUG_KMS("Using SSC on panel\n");
9038                         val |= DREF_SSC1_ENABLE;
9039                 } else
9040                         val &= ~DREF_SSC1_ENABLE;
9041
9042                 /* Get SSC going before enabling the outputs */
9043                 I915_WRITE(PCH_DREF_CONTROL, val);
9044                 POSTING_READ(PCH_DREF_CONTROL);
9045                 udelay(200);
9046
9047                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9048
9049                 /* Enable CPU source on CPU attached eDP */
9050                 if (has_cpu_edp) {
9051                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9052                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9053                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9054                         } else
9055                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9056                 } else
9057                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9058
9059                 I915_WRITE(PCH_DREF_CONTROL, val);
9060                 POSTING_READ(PCH_DREF_CONTROL);
9061                 udelay(200);
9062         } else {
9063                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9064
9065                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9066
9067                 /* Turn off CPU output */
9068                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9069
9070                 I915_WRITE(PCH_DREF_CONTROL, val);
9071                 POSTING_READ(PCH_DREF_CONTROL);
9072                 udelay(200);
9073
9074                 if (!using_ssc_source) {
9075                         DRM_DEBUG_KMS("Disabling SSC source\n");
9076
9077                         /* Turn off the SSC source */
9078                         val &= ~DREF_SSC_SOURCE_MASK;
9079                         val |= DREF_SSC_SOURCE_DISABLE;
9080
9081                         /* Turn off SSC1 */
9082                         val &= ~DREF_SSC1_ENABLE;
9083
9084                         I915_WRITE(PCH_DREF_CONTROL, val);
9085                         POSTING_READ(PCH_DREF_CONTROL);
9086                         udelay(200);
9087                 }
9088         }
9089
9090         BUG_ON(val != final);
9091 }
9092
9093 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9094 {
9095         uint32_t tmp;
9096
9097         tmp = I915_READ(SOUTH_CHICKEN2);
9098         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9099         I915_WRITE(SOUTH_CHICKEN2, tmp);
9100
9101         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9102                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9103                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9104
9105         tmp = I915_READ(SOUTH_CHICKEN2);
9106         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9107         I915_WRITE(SOUTH_CHICKEN2, tmp);
9108
9109         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9110                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9111                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9112 }
9113
9114 /* WaMPhyProgramming:hsw */
9115 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9116 {
9117         uint32_t tmp;
9118
9119         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9120         tmp &= ~(0xFF << 24);
9121         tmp |= (0x12 << 24);
9122         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9123
9124         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9125         tmp |= (1 << 11);
9126         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9127
9128         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9129         tmp |= (1 << 11);
9130         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9131
9132         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9133         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9134         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9135
9136         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9137         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9138         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9139
9140         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9141         tmp &= ~(7 << 13);
9142         tmp |= (5 << 13);
9143         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9144
9145         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9146         tmp &= ~(7 << 13);
9147         tmp |= (5 << 13);
9148         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9149
9150         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9151         tmp &= ~0xFF;
9152         tmp |= 0x1C;
9153         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9154
9155         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9156         tmp &= ~0xFF;
9157         tmp |= 0x1C;
9158         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9159
9160         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9161         tmp &= ~(0xFF << 16);
9162         tmp |= (0x1C << 16);
9163         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9164
9165         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9166         tmp &= ~(0xFF << 16);
9167         tmp |= (0x1C << 16);
9168         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9169
9170         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9171         tmp |= (1 << 27);
9172         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9173
9174         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9175         tmp |= (1 << 27);
9176         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9177
9178         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9179         tmp &= ~(0xF << 28);
9180         tmp |= (4 << 28);
9181         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9182
9183         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9184         tmp &= ~(0xF << 28);
9185         tmp |= (4 << 28);
9186         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9187 }
9188
9189 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9190  * Programming" based on the parameters passed:
9191  * - Sequence to enable CLKOUT_DP
9192  * - Sequence to enable CLKOUT_DP without spread
9193  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9194  */
9195 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9196                                  bool with_fdi)
9197 {
9198         struct drm_i915_private *dev_priv = to_i915(dev);
9199         uint32_t reg, tmp;
9200
9201         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9202                 with_spread = true;
9203         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9204                 with_fdi = false;
9205
9206         mutex_lock(&dev_priv->sb_lock);
9207
9208         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9209         tmp &= ~SBI_SSCCTL_DISABLE;
9210         tmp |= SBI_SSCCTL_PATHALT;
9211         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9212
9213         udelay(24);
9214
9215         if (with_spread) {
9216                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9217                 tmp &= ~SBI_SSCCTL_PATHALT;
9218                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9219
9220                 if (with_fdi) {
9221                         lpt_reset_fdi_mphy(dev_priv);
9222                         lpt_program_fdi_mphy(dev_priv);
9223                 }
9224         }
9225
9226         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9227         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9228         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9229         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9230
9231         mutex_unlock(&dev_priv->sb_lock);
9232 }
9233
9234 /* Sequence to disable CLKOUT_DP */
9235 static void lpt_disable_clkout_dp(struct drm_device *dev)
9236 {
9237         struct drm_i915_private *dev_priv = to_i915(dev);
9238         uint32_t reg, tmp;
9239
9240         mutex_lock(&dev_priv->sb_lock);
9241
9242         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9243         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9244         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9245         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9246
9247         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9248         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9249                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9250                         tmp |= SBI_SSCCTL_PATHALT;
9251                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9252                         udelay(32);
9253                 }
9254                 tmp |= SBI_SSCCTL_DISABLE;
9255                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9256         }
9257
9258         mutex_unlock(&dev_priv->sb_lock);
9259 }
9260
9261 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9262
9263 static const uint16_t sscdivintphase[] = {
9264         [BEND_IDX( 50)] = 0x3B23,
9265         [BEND_IDX( 45)] = 0x3B23,
9266         [BEND_IDX( 40)] = 0x3C23,
9267         [BEND_IDX( 35)] = 0x3C23,
9268         [BEND_IDX( 30)] = 0x3D23,
9269         [BEND_IDX( 25)] = 0x3D23,
9270         [BEND_IDX( 20)] = 0x3E23,
9271         [BEND_IDX( 15)] = 0x3E23,
9272         [BEND_IDX( 10)] = 0x3F23,
9273         [BEND_IDX(  5)] = 0x3F23,
9274         [BEND_IDX(  0)] = 0x0025,
9275         [BEND_IDX( -5)] = 0x0025,
9276         [BEND_IDX(-10)] = 0x0125,
9277         [BEND_IDX(-15)] = 0x0125,
9278         [BEND_IDX(-20)] = 0x0225,
9279         [BEND_IDX(-25)] = 0x0225,
9280         [BEND_IDX(-30)] = 0x0325,
9281         [BEND_IDX(-35)] = 0x0325,
9282         [BEND_IDX(-40)] = 0x0425,
9283         [BEND_IDX(-45)] = 0x0425,
9284         [BEND_IDX(-50)] = 0x0525,
9285 };
9286
9287 /*
9288  * Bend CLKOUT_DP
9289  * steps -50 to 50 inclusive, in steps of 5
9290  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9291  * change in clock period = -(steps / 10) * 5.787 ps
9292  */
9293 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9294 {
9295         uint32_t tmp;
9296         int idx = BEND_IDX(steps);
9297
9298         if (WARN_ON(steps % 5 != 0))
9299                 return;
9300
9301         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9302                 return;
9303
9304         mutex_lock(&dev_priv->sb_lock);
9305
9306         if (steps % 10 != 0)
9307                 tmp = 0xAAAAAAAB;
9308         else
9309                 tmp = 0x00000000;
9310         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9311
9312         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9313         tmp &= 0xffff0000;
9314         tmp |= sscdivintphase[idx];
9315         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9316
9317         mutex_unlock(&dev_priv->sb_lock);
9318 }
9319
9320 #undef BEND_IDX
9321
9322 static void lpt_init_pch_refclk(struct drm_device *dev)
9323 {
9324         struct intel_encoder *encoder;
9325         bool has_vga = false;
9326
9327         for_each_intel_encoder(dev, encoder) {
9328                 switch (encoder->type) {
9329                 case INTEL_OUTPUT_ANALOG:
9330                         has_vga = true;
9331                         break;
9332                 default:
9333                         break;
9334                 }
9335         }
9336
9337         if (has_vga) {
9338                 lpt_bend_clkout_dp(to_i915(dev), 0);
9339                 lpt_enable_clkout_dp(dev, true, true);
9340         } else {
9341                 lpt_disable_clkout_dp(dev);
9342         }
9343 }
9344
9345 /*
9346  * Initialize reference clocks when the driver loads
9347  */
9348 void intel_init_pch_refclk(struct drm_device *dev)
9349 {
9350         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9351                 ironlake_init_pch_refclk(dev);
9352         else if (HAS_PCH_LPT(dev))
9353                 lpt_init_pch_refclk(dev);
9354 }
9355
9356 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9357 {
9358         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9360         int pipe = intel_crtc->pipe;
9361         uint32_t val;
9362
9363         val = 0;
9364
9365         switch (intel_crtc->config->pipe_bpp) {
9366         case 18:
9367                 val |= PIPECONF_6BPC;
9368                 break;
9369         case 24:
9370                 val |= PIPECONF_8BPC;
9371                 break;
9372         case 30:
9373                 val |= PIPECONF_10BPC;
9374                 break;
9375         case 36:
9376                 val |= PIPECONF_12BPC;
9377                 break;
9378         default:
9379                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9380                 BUG();
9381         }
9382
9383         if (intel_crtc->config->dither)
9384                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9385
9386         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9387                 val |= PIPECONF_INTERLACED_ILK;
9388         else
9389                 val |= PIPECONF_PROGRESSIVE;
9390
9391         if (intel_crtc->config->limited_color_range)
9392                 val |= PIPECONF_COLOR_RANGE_SELECT;
9393
9394         I915_WRITE(PIPECONF(pipe), val);
9395         POSTING_READ(PIPECONF(pipe));
9396 }
9397
9398 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9399 {
9400         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9402         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9403         u32 val = 0;
9404
9405         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9406                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9407
9408         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9409                 val |= PIPECONF_INTERLACED_ILK;
9410         else
9411                 val |= PIPECONF_PROGRESSIVE;
9412
9413         I915_WRITE(PIPECONF(cpu_transcoder), val);
9414         POSTING_READ(PIPECONF(cpu_transcoder));
9415 }
9416
9417 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9418 {
9419         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9421
9422         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9423                 u32 val = 0;
9424
9425                 switch (intel_crtc->config->pipe_bpp) {
9426                 case 18:
9427                         val |= PIPEMISC_DITHER_6_BPC;
9428                         break;
9429                 case 24:
9430                         val |= PIPEMISC_DITHER_8_BPC;
9431                         break;
9432                 case 30:
9433                         val |= PIPEMISC_DITHER_10_BPC;
9434                         break;
9435                 case 36:
9436                         val |= PIPEMISC_DITHER_12_BPC;
9437                         break;
9438                 default:
9439                         /* Case prevented by pipe_config_set_bpp. */
9440                         BUG();
9441                 }
9442
9443                 if (intel_crtc->config->dither)
9444                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9445
9446                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9447         }
9448 }
9449
9450 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9451 {
9452         /*
9453          * Account for spread spectrum to avoid
9454          * oversubscribing the link. Max center spread
9455          * is 2.5%; use 5% for safety's sake.
9456          */
9457         u32 bps = target_clock * bpp * 21 / 20;
9458         return DIV_ROUND_UP(bps, link_bw * 8);
9459 }
9460
9461 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9462 {
9463         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9464 }
9465
9466 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9467                                   struct intel_crtc_state *crtc_state,
9468                                   struct dpll *reduced_clock)
9469 {
9470         struct drm_crtc *crtc = &intel_crtc->base;
9471         struct drm_device *dev = crtc->dev;
9472         struct drm_i915_private *dev_priv = to_i915(dev);
9473         u32 dpll, fp, fp2;
9474         int factor;
9475
9476         /* Enable autotuning of the PLL clock (if permissible) */
9477         factor = 21;
9478         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9479                 if ((intel_panel_use_ssc(dev_priv) &&
9480                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9481                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9482                         factor = 25;
9483         } else if (crtc_state->sdvo_tv_clock)
9484                 factor = 20;
9485
9486         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9487
9488         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9489                 fp |= FP_CB_TUNE;
9490
9491         if (reduced_clock) {
9492                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9493
9494                 if (reduced_clock->m < factor * reduced_clock->n)
9495                         fp2 |= FP_CB_TUNE;
9496         } else {
9497                 fp2 = fp;
9498         }
9499
9500         dpll = 0;
9501
9502         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9503                 dpll |= DPLLB_MODE_LVDS;
9504         else
9505                 dpll |= DPLLB_MODE_DAC_SERIAL;
9506
9507         dpll |= (crtc_state->pixel_multiplier - 1)
9508                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9509
9510         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9511             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9512                 dpll |= DPLL_SDVO_HIGH_SPEED;
9513
9514         if (intel_crtc_has_dp_encoder(crtc_state))
9515                 dpll |= DPLL_SDVO_HIGH_SPEED;
9516
9517         /*
9518          * The high speed IO clock is only really required for
9519          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9520          * possible to share the DPLL between CRT and HDMI. Enabling
9521          * the clock needlessly does no real harm, except use up a
9522          * bit of power potentially.
9523          *
9524          * We'll limit this to IVB with 3 pipes, since it has only two
9525          * DPLLs and so DPLL sharing is the only way to get three pipes
9526          * driving PCH ports at the same time. On SNB we could do this,
9527          * and potentially avoid enabling the second DPLL, but it's not
9528          * clear if it''s a win or loss power wise. No point in doing
9529          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9530          */
9531         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9532             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9533                 dpll |= DPLL_SDVO_HIGH_SPEED;
9534
9535         /* compute bitmask from p1 value */
9536         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9537         /* also FPA1 */
9538         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9539
9540         switch (crtc_state->dpll.p2) {
9541         case 5:
9542                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9543                 break;
9544         case 7:
9545                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9546                 break;
9547         case 10:
9548                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9549                 break;
9550         case 14:
9551                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9552                 break;
9553         }
9554
9555         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9556             intel_panel_use_ssc(dev_priv))
9557                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9558         else
9559                 dpll |= PLL_REF_INPUT_DREFCLK;
9560
9561         dpll |= DPLL_VCO_ENABLE;
9562
9563         crtc_state->dpll_hw_state.dpll = dpll;
9564         crtc_state->dpll_hw_state.fp0 = fp;
9565         crtc_state->dpll_hw_state.fp1 = fp2;
9566 }
9567
9568 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9569                                        struct intel_crtc_state *crtc_state)
9570 {
9571         struct drm_device *dev = crtc->base.dev;
9572         struct drm_i915_private *dev_priv = to_i915(dev);
9573         struct dpll reduced_clock;
9574         bool has_reduced_clock = false;
9575         struct intel_shared_dpll *pll;
9576         const struct intel_limit *limit;
9577         int refclk = 120000;
9578
9579         memset(&crtc_state->dpll_hw_state, 0,
9580                sizeof(crtc_state->dpll_hw_state));
9581
9582         crtc->lowfreq_avail = false;
9583
9584         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9585         if (!crtc_state->has_pch_encoder)
9586                 return 0;
9587
9588         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9589                 if (intel_panel_use_ssc(dev_priv)) {
9590                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9591                                       dev_priv->vbt.lvds_ssc_freq);
9592                         refclk = dev_priv->vbt.lvds_ssc_freq;
9593                 }
9594
9595                 if (intel_is_dual_link_lvds(dev)) {
9596                         if (refclk == 100000)
9597                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9598                         else
9599                                 limit = &intel_limits_ironlake_dual_lvds;
9600                 } else {
9601                         if (refclk == 100000)
9602                                 limit = &intel_limits_ironlake_single_lvds_100m;
9603                         else
9604                                 limit = &intel_limits_ironlake_single_lvds;
9605                 }
9606         } else {
9607                 limit = &intel_limits_ironlake_dac;
9608         }
9609
9610         if (!crtc_state->clock_set &&
9611             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9612                                 refclk, NULL, &crtc_state->dpll)) {
9613                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9614                 return -EINVAL;
9615         }
9616
9617         ironlake_compute_dpll(crtc, crtc_state,
9618                               has_reduced_clock ? &reduced_clock : NULL);
9619
9620         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9621         if (pll == NULL) {
9622                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9623                                  pipe_name(crtc->pipe));
9624                 return -EINVAL;
9625         }
9626
9627         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9628             has_reduced_clock)
9629                 crtc->lowfreq_avail = true;
9630
9631         return 0;
9632 }
9633
9634 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9635                                          struct intel_link_m_n *m_n)
9636 {
9637         struct drm_device *dev = crtc->base.dev;
9638         struct drm_i915_private *dev_priv = to_i915(dev);
9639         enum pipe pipe = crtc->pipe;
9640
9641         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9642         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9643         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9644                 & ~TU_SIZE_MASK;
9645         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9646         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9647                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9648 }
9649
9650 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9651                                          enum transcoder transcoder,
9652                                          struct intel_link_m_n *m_n,
9653                                          struct intel_link_m_n *m2_n2)
9654 {
9655         struct drm_device *dev = crtc->base.dev;
9656         struct drm_i915_private *dev_priv = to_i915(dev);
9657         enum pipe pipe = crtc->pipe;
9658
9659         if (INTEL_INFO(dev)->gen >= 5) {
9660                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9661                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9662                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9663                         & ~TU_SIZE_MASK;
9664                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9665                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9666                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9667                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9668                  * gen < 8) and if DRRS is supported (to make sure the
9669                  * registers are not unnecessarily read).
9670                  */
9671                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9672                         crtc->config->has_drrs) {
9673                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9674                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9675                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9676                                         & ~TU_SIZE_MASK;
9677                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9678                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9679                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9680                 }
9681         } else {
9682                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9683                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9684                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9685                         & ~TU_SIZE_MASK;
9686                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9687                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9688                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9689         }
9690 }
9691
9692 void intel_dp_get_m_n(struct intel_crtc *crtc,
9693                       struct intel_crtc_state *pipe_config)
9694 {
9695         if (pipe_config->has_pch_encoder)
9696                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9697         else
9698                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9699                                              &pipe_config->dp_m_n,
9700                                              &pipe_config->dp_m2_n2);
9701 }
9702
9703 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9704                                         struct intel_crtc_state *pipe_config)
9705 {
9706         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9707                                      &pipe_config->fdi_m_n, NULL);
9708 }
9709
9710 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9711                                     struct intel_crtc_state *pipe_config)
9712 {
9713         struct drm_device *dev = crtc->base.dev;
9714         struct drm_i915_private *dev_priv = to_i915(dev);
9715         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9716         uint32_t ps_ctrl = 0;
9717         int id = -1;
9718         int i;
9719
9720         /* find scaler attached to this pipe */
9721         for (i = 0; i < crtc->num_scalers; i++) {
9722                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9723                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9724                         id = i;
9725                         pipe_config->pch_pfit.enabled = true;
9726                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9727                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9728                         break;
9729                 }
9730         }
9731
9732         scaler_state->scaler_id = id;
9733         if (id >= 0) {
9734                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9735         } else {
9736                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9737         }
9738 }
9739
9740 static void
9741 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9742                                  struct intel_initial_plane_config *plane_config)
9743 {
9744         struct drm_device *dev = crtc->base.dev;
9745         struct drm_i915_private *dev_priv = to_i915(dev);
9746         u32 val, base, offset, stride_mult, tiling;
9747         int pipe = crtc->pipe;
9748         int fourcc, pixel_format;
9749         unsigned int aligned_height;
9750         struct drm_framebuffer *fb;
9751         struct intel_framebuffer *intel_fb;
9752
9753         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9754         if (!intel_fb) {
9755                 DRM_DEBUG_KMS("failed to alloc fb\n");
9756                 return;
9757         }
9758
9759         fb = &intel_fb->base;
9760
9761         val = I915_READ(PLANE_CTL(pipe, 0));
9762         if (!(val & PLANE_CTL_ENABLE))
9763                 goto error;
9764
9765         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9766         fourcc = skl_format_to_fourcc(pixel_format,
9767                                       val & PLANE_CTL_ORDER_RGBX,
9768                                       val & PLANE_CTL_ALPHA_MASK);
9769         fb->pixel_format = fourcc;
9770         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9771
9772         tiling = val & PLANE_CTL_TILED_MASK;
9773         switch (tiling) {
9774         case PLANE_CTL_TILED_LINEAR:
9775                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9776                 break;
9777         case PLANE_CTL_TILED_X:
9778                 plane_config->tiling = I915_TILING_X;
9779                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9780                 break;
9781         case PLANE_CTL_TILED_Y:
9782                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9783                 break;
9784         case PLANE_CTL_TILED_YF:
9785                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9786                 break;
9787         default:
9788                 MISSING_CASE(tiling);
9789                 goto error;
9790         }
9791
9792         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9793         plane_config->base = base;
9794
9795         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9796
9797         val = I915_READ(PLANE_SIZE(pipe, 0));
9798         fb->height = ((val >> 16) & 0xfff) + 1;
9799         fb->width = ((val >> 0) & 0x1fff) + 1;
9800
9801         val = I915_READ(PLANE_STRIDE(pipe, 0));
9802         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9803                                                 fb->pixel_format);
9804         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9805
9806         aligned_height = intel_fb_align_height(dev, fb->height,
9807                                                fb->pixel_format,
9808                                                fb->modifier[0]);
9809
9810         plane_config->size = fb->pitches[0] * aligned_height;
9811
9812         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9813                       pipe_name(pipe), fb->width, fb->height,
9814                       fb->bits_per_pixel, base, fb->pitches[0],
9815                       plane_config->size);
9816
9817         plane_config->fb = intel_fb;
9818         return;
9819
9820 error:
9821         kfree(intel_fb);
9822 }
9823
9824 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9825                                      struct intel_crtc_state *pipe_config)
9826 {
9827         struct drm_device *dev = crtc->base.dev;
9828         struct drm_i915_private *dev_priv = to_i915(dev);
9829         uint32_t tmp;
9830
9831         tmp = I915_READ(PF_CTL(crtc->pipe));
9832
9833         if (tmp & PF_ENABLE) {
9834                 pipe_config->pch_pfit.enabled = true;
9835                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9836                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9837
9838                 /* We currently do not free assignements of panel fitters on
9839                  * ivb/hsw (since we don't use the higher upscaling modes which
9840                  * differentiates them) so just WARN about this case for now. */
9841                 if (IS_GEN7(dev)) {
9842                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9843                                 PF_PIPE_SEL_IVB(crtc->pipe));
9844                 }
9845         }
9846 }
9847
9848 static void
9849 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9850                                   struct intel_initial_plane_config *plane_config)
9851 {
9852         struct drm_device *dev = crtc->base.dev;
9853         struct drm_i915_private *dev_priv = to_i915(dev);
9854         u32 val, base, offset;
9855         int pipe = crtc->pipe;
9856         int fourcc, pixel_format;
9857         unsigned int aligned_height;
9858         struct drm_framebuffer *fb;
9859         struct intel_framebuffer *intel_fb;
9860
9861         val = I915_READ(DSPCNTR(pipe));
9862         if (!(val & DISPLAY_PLANE_ENABLE))
9863                 return;
9864
9865         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9866         if (!intel_fb) {
9867                 DRM_DEBUG_KMS("failed to alloc fb\n");
9868                 return;
9869         }
9870
9871         fb = &intel_fb->base;
9872
9873         if (INTEL_INFO(dev)->gen >= 4) {
9874                 if (val & DISPPLANE_TILED) {
9875                         plane_config->tiling = I915_TILING_X;
9876                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9877                 }
9878         }
9879
9880         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9881         fourcc = i9xx_format_to_fourcc(pixel_format);
9882         fb->pixel_format = fourcc;
9883         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9884
9885         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9886         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9887                 offset = I915_READ(DSPOFFSET(pipe));
9888         } else {
9889                 if (plane_config->tiling)
9890                         offset = I915_READ(DSPTILEOFF(pipe));
9891                 else
9892                         offset = I915_READ(DSPLINOFF(pipe));
9893         }
9894         plane_config->base = base;
9895
9896         val = I915_READ(PIPESRC(pipe));
9897         fb->width = ((val >> 16) & 0xfff) + 1;
9898         fb->height = ((val >> 0) & 0xfff) + 1;
9899
9900         val = I915_READ(DSPSTRIDE(pipe));
9901         fb->pitches[0] = val & 0xffffffc0;
9902
9903         aligned_height = intel_fb_align_height(dev, fb->height,
9904                                                fb->pixel_format,
9905                                                fb->modifier[0]);
9906
9907         plane_config->size = fb->pitches[0] * aligned_height;
9908
9909         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9910                       pipe_name(pipe), fb->width, fb->height,
9911                       fb->bits_per_pixel, base, fb->pitches[0],
9912                       plane_config->size);
9913
9914         plane_config->fb = intel_fb;
9915 }
9916
9917 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9918                                      struct intel_crtc_state *pipe_config)
9919 {
9920         struct drm_device *dev = crtc->base.dev;
9921         struct drm_i915_private *dev_priv = to_i915(dev);
9922         enum intel_display_power_domain power_domain;
9923         uint32_t tmp;
9924         bool ret;
9925
9926         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9927         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9928                 return false;
9929
9930         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9931         pipe_config->shared_dpll = NULL;
9932
9933         ret = false;
9934         tmp = I915_READ(PIPECONF(crtc->pipe));
9935         if (!(tmp & PIPECONF_ENABLE))
9936                 goto out;
9937
9938         switch (tmp & PIPECONF_BPC_MASK) {
9939         case PIPECONF_6BPC:
9940                 pipe_config->pipe_bpp = 18;
9941                 break;
9942         case PIPECONF_8BPC:
9943                 pipe_config->pipe_bpp = 24;
9944                 break;
9945         case PIPECONF_10BPC:
9946                 pipe_config->pipe_bpp = 30;
9947                 break;
9948         case PIPECONF_12BPC:
9949                 pipe_config->pipe_bpp = 36;
9950                 break;
9951         default:
9952                 break;
9953         }
9954
9955         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9956                 pipe_config->limited_color_range = true;
9957
9958         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9959                 struct intel_shared_dpll *pll;
9960                 enum intel_dpll_id pll_id;
9961
9962                 pipe_config->has_pch_encoder = true;
9963
9964                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9965                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9966                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9967
9968                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9969
9970                 if (HAS_PCH_IBX(dev_priv)) {
9971                         /*
9972                          * The pipe->pch transcoder and pch transcoder->pll
9973                          * mapping is fixed.
9974                          */
9975                         pll_id = (enum intel_dpll_id) crtc->pipe;
9976                 } else {
9977                         tmp = I915_READ(PCH_DPLL_SEL);
9978                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9979                                 pll_id = DPLL_ID_PCH_PLL_B;
9980                         else
9981                                 pll_id= DPLL_ID_PCH_PLL_A;
9982                 }
9983
9984                 pipe_config->shared_dpll =
9985                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9986                 pll = pipe_config->shared_dpll;
9987
9988                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9989                                                  &pipe_config->dpll_hw_state));
9990
9991                 tmp = pipe_config->dpll_hw_state.dpll;
9992                 pipe_config->pixel_multiplier =
9993                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9994                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9995
9996                 ironlake_pch_clock_get(crtc, pipe_config);
9997         } else {
9998                 pipe_config->pixel_multiplier = 1;
9999         }
10000
10001         intel_get_pipe_timings(crtc, pipe_config);
10002         intel_get_pipe_src_size(crtc, pipe_config);
10003
10004         ironlake_get_pfit_config(crtc, pipe_config);
10005
10006         ret = true;
10007
10008 out:
10009         intel_display_power_put(dev_priv, power_domain);
10010
10011         return ret;
10012 }
10013
10014 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10015 {
10016         struct drm_device *dev = &dev_priv->drm;
10017         struct intel_crtc *crtc;
10018
10019         for_each_intel_crtc(dev, crtc)
10020                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10021                      pipe_name(crtc->pipe));
10022
10023         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10024         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10025         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10026         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10027         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10028         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10029              "CPU PWM1 enabled\n");
10030         if (IS_HASWELL(dev))
10031                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10032                      "CPU PWM2 enabled\n");
10033         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10034              "PCH PWM1 enabled\n");
10035         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10036              "Utility pin enabled\n");
10037         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10038
10039         /*
10040          * In theory we can still leave IRQs enabled, as long as only the HPD
10041          * interrupts remain enabled. We used to check for that, but since it's
10042          * gen-specific and since we only disable LCPLL after we fully disable
10043          * the interrupts, the check below should be enough.
10044          */
10045         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10046 }
10047
10048 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10049 {
10050         struct drm_device *dev = &dev_priv->drm;
10051
10052         if (IS_HASWELL(dev))
10053                 return I915_READ(D_COMP_HSW);
10054         else
10055                 return I915_READ(D_COMP_BDW);
10056 }
10057
10058 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10059 {
10060         struct drm_device *dev = &dev_priv->drm;
10061
10062         if (IS_HASWELL(dev)) {
10063                 mutex_lock(&dev_priv->rps.hw_lock);
10064                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10065                                             val))
10066                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10067                 mutex_unlock(&dev_priv->rps.hw_lock);
10068         } else {
10069                 I915_WRITE(D_COMP_BDW, val);
10070                 POSTING_READ(D_COMP_BDW);
10071         }
10072 }
10073
10074 /*
10075  * This function implements pieces of two sequences from BSpec:
10076  * - Sequence for display software to disable LCPLL
10077  * - Sequence for display software to allow package C8+
10078  * The steps implemented here are just the steps that actually touch the LCPLL
10079  * register. Callers should take care of disabling all the display engine
10080  * functions, doing the mode unset, fixing interrupts, etc.
10081  */
10082 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10083                               bool switch_to_fclk, bool allow_power_down)
10084 {
10085         uint32_t val;
10086
10087         assert_can_disable_lcpll(dev_priv);
10088
10089         val = I915_READ(LCPLL_CTL);
10090
10091         if (switch_to_fclk) {
10092                 val |= LCPLL_CD_SOURCE_FCLK;
10093                 I915_WRITE(LCPLL_CTL, val);
10094
10095                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10096                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10097                         DRM_ERROR("Switching to FCLK failed\n");
10098
10099                 val = I915_READ(LCPLL_CTL);
10100         }
10101
10102         val |= LCPLL_PLL_DISABLE;
10103         I915_WRITE(LCPLL_CTL, val);
10104         POSTING_READ(LCPLL_CTL);
10105
10106         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10107                 DRM_ERROR("LCPLL still locked\n");
10108
10109         val = hsw_read_dcomp(dev_priv);
10110         val |= D_COMP_COMP_DISABLE;
10111         hsw_write_dcomp(dev_priv, val);
10112         ndelay(100);
10113
10114         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10115                      1))
10116                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10117
10118         if (allow_power_down) {
10119                 val = I915_READ(LCPLL_CTL);
10120                 val |= LCPLL_POWER_DOWN_ALLOW;
10121                 I915_WRITE(LCPLL_CTL, val);
10122                 POSTING_READ(LCPLL_CTL);
10123         }
10124 }
10125
10126 /*
10127  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10128  * source.
10129  */
10130 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10131 {
10132         uint32_t val;
10133
10134         val = I915_READ(LCPLL_CTL);
10135
10136         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10137                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10138                 return;
10139
10140         /*
10141          * Make sure we're not on PC8 state before disabling PC8, otherwise
10142          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10143          */
10144         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10145
10146         if (val & LCPLL_POWER_DOWN_ALLOW) {
10147                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10148                 I915_WRITE(LCPLL_CTL, val);
10149                 POSTING_READ(LCPLL_CTL);
10150         }
10151
10152         val = hsw_read_dcomp(dev_priv);
10153         val |= D_COMP_COMP_FORCE;
10154         val &= ~D_COMP_COMP_DISABLE;
10155         hsw_write_dcomp(dev_priv, val);
10156
10157         val = I915_READ(LCPLL_CTL);
10158         val &= ~LCPLL_PLL_DISABLE;
10159         I915_WRITE(LCPLL_CTL, val);
10160
10161         if (intel_wait_for_register(dev_priv,
10162                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10163                                     5))
10164                 DRM_ERROR("LCPLL not locked yet\n");
10165
10166         if (val & LCPLL_CD_SOURCE_FCLK) {
10167                 val = I915_READ(LCPLL_CTL);
10168                 val &= ~LCPLL_CD_SOURCE_FCLK;
10169                 I915_WRITE(LCPLL_CTL, val);
10170
10171                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10172                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10173                         DRM_ERROR("Switching back to LCPLL failed\n");
10174         }
10175
10176         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10177         intel_update_cdclk(&dev_priv->drm);
10178 }
10179
10180 /*
10181  * Package states C8 and deeper are really deep PC states that can only be
10182  * reached when all the devices on the system allow it, so even if the graphics
10183  * device allows PC8+, it doesn't mean the system will actually get to these
10184  * states. Our driver only allows PC8+ when going into runtime PM.
10185  *
10186  * The requirements for PC8+ are that all the outputs are disabled, the power
10187  * well is disabled and most interrupts are disabled, and these are also
10188  * requirements for runtime PM. When these conditions are met, we manually do
10189  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10190  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10191  * hang the machine.
10192  *
10193  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10194  * the state of some registers, so when we come back from PC8+ we need to
10195  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10196  * need to take care of the registers kept by RC6. Notice that this happens even
10197  * if we don't put the device in PCI D3 state (which is what currently happens
10198  * because of the runtime PM support).
10199  *
10200  * For more, read "Display Sequences for Package C8" on the hardware
10201  * documentation.
10202  */
10203 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10204 {
10205         struct drm_device *dev = &dev_priv->drm;
10206         uint32_t val;
10207
10208         DRM_DEBUG_KMS("Enabling package C8+\n");
10209
10210         if (HAS_PCH_LPT_LP(dev)) {
10211                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10212                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10213                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10214         }
10215
10216         lpt_disable_clkout_dp(dev);
10217         hsw_disable_lcpll(dev_priv, true, true);
10218 }
10219
10220 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10221 {
10222         struct drm_device *dev = &dev_priv->drm;
10223         uint32_t val;
10224
10225         DRM_DEBUG_KMS("Disabling package C8+\n");
10226
10227         hsw_restore_lcpll(dev_priv);
10228         lpt_init_pch_refclk(dev);
10229
10230         if (HAS_PCH_LPT_LP(dev)) {
10231                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10232                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10233                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10234         }
10235 }
10236
10237 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10238 {
10239         struct drm_device *dev = old_state->dev;
10240         struct intel_atomic_state *old_intel_state =
10241                 to_intel_atomic_state(old_state);
10242         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10243
10244         bxt_set_cdclk(to_i915(dev), req_cdclk);
10245 }
10246
10247 /* compute the max rate for new configuration */
10248 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10249 {
10250         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10251         struct drm_i915_private *dev_priv = to_i915(state->dev);
10252         struct drm_crtc *crtc;
10253         struct drm_crtc_state *cstate;
10254         struct intel_crtc_state *crtc_state;
10255         unsigned max_pixel_rate = 0, i;
10256         enum pipe pipe;
10257
10258         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10259                sizeof(intel_state->min_pixclk));
10260
10261         for_each_crtc_in_state(state, crtc, cstate, i) {
10262                 int pixel_rate;
10263
10264                 crtc_state = to_intel_crtc_state(cstate);
10265                 if (!crtc_state->base.enable) {
10266                         intel_state->min_pixclk[i] = 0;
10267                         continue;
10268                 }
10269
10270                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10271
10272                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10273                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10274                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10275
10276                 intel_state->min_pixclk[i] = pixel_rate;
10277         }
10278
10279         for_each_pipe(dev_priv, pipe)
10280                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10281
10282         return max_pixel_rate;
10283 }
10284
10285 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10286 {
10287         struct drm_i915_private *dev_priv = to_i915(dev);
10288         uint32_t val, data;
10289         int ret;
10290
10291         if (WARN((I915_READ(LCPLL_CTL) &
10292                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10293                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10294                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10295                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10296                  "trying to change cdclk frequency with cdclk not enabled\n"))
10297                 return;
10298
10299         mutex_lock(&dev_priv->rps.hw_lock);
10300         ret = sandybridge_pcode_write(dev_priv,
10301                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10302         mutex_unlock(&dev_priv->rps.hw_lock);
10303         if (ret) {
10304                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10305                 return;
10306         }
10307
10308         val = I915_READ(LCPLL_CTL);
10309         val |= LCPLL_CD_SOURCE_FCLK;
10310         I915_WRITE(LCPLL_CTL, val);
10311
10312         if (wait_for_us(I915_READ(LCPLL_CTL) &
10313                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10314                 DRM_ERROR("Switching to FCLK failed\n");
10315
10316         val = I915_READ(LCPLL_CTL);
10317         val &= ~LCPLL_CLK_FREQ_MASK;
10318
10319         switch (cdclk) {
10320         case 450000:
10321                 val |= LCPLL_CLK_FREQ_450;
10322                 data = 0;
10323                 break;
10324         case 540000:
10325                 val |= LCPLL_CLK_FREQ_54O_BDW;
10326                 data = 1;
10327                 break;
10328         case 337500:
10329                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10330                 data = 2;
10331                 break;
10332         case 675000:
10333                 val |= LCPLL_CLK_FREQ_675_BDW;
10334                 data = 3;
10335                 break;
10336         default:
10337                 WARN(1, "invalid cdclk frequency\n");
10338                 return;
10339         }
10340
10341         I915_WRITE(LCPLL_CTL, val);
10342
10343         val = I915_READ(LCPLL_CTL);
10344         val &= ~LCPLL_CD_SOURCE_FCLK;
10345         I915_WRITE(LCPLL_CTL, val);
10346
10347         if (wait_for_us((I915_READ(LCPLL_CTL) &
10348                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10349                 DRM_ERROR("Switching back to LCPLL failed\n");
10350
10351         mutex_lock(&dev_priv->rps.hw_lock);
10352         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10353         mutex_unlock(&dev_priv->rps.hw_lock);
10354
10355         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10356
10357         intel_update_cdclk(dev);
10358
10359         WARN(cdclk != dev_priv->cdclk_freq,
10360              "cdclk requested %d kHz but got %d kHz\n",
10361              cdclk, dev_priv->cdclk_freq);
10362 }
10363
10364 static int broadwell_calc_cdclk(int max_pixclk)
10365 {
10366         if (max_pixclk > 540000)
10367                 return 675000;
10368         else if (max_pixclk > 450000)
10369                 return 540000;
10370         else if (max_pixclk > 337500)
10371                 return 450000;
10372         else
10373                 return 337500;
10374 }
10375
10376 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10377 {
10378         struct drm_i915_private *dev_priv = to_i915(state->dev);
10379         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10380         int max_pixclk = ilk_max_pixel_rate(state);
10381         int cdclk;
10382
10383         /*
10384          * FIXME should also account for plane ratio
10385          * once 64bpp pixel formats are supported.
10386          */
10387         cdclk = broadwell_calc_cdclk(max_pixclk);
10388
10389         if (cdclk > dev_priv->max_cdclk_freq) {
10390                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10391                               cdclk, dev_priv->max_cdclk_freq);
10392                 return -EINVAL;
10393         }
10394
10395         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10396         if (!intel_state->active_crtcs)
10397                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10398
10399         return 0;
10400 }
10401
10402 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10403 {
10404         struct drm_device *dev = old_state->dev;
10405         struct intel_atomic_state *old_intel_state =
10406                 to_intel_atomic_state(old_state);
10407         unsigned req_cdclk = old_intel_state->dev_cdclk;
10408
10409         broadwell_set_cdclk(dev, req_cdclk);
10410 }
10411
10412 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10413 {
10414         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10415         struct drm_i915_private *dev_priv = to_i915(state->dev);
10416         const int max_pixclk = ilk_max_pixel_rate(state);
10417         int vco = intel_state->cdclk_pll_vco;
10418         int cdclk;
10419
10420         /*
10421          * FIXME should also account for plane ratio
10422          * once 64bpp pixel formats are supported.
10423          */
10424         cdclk = skl_calc_cdclk(max_pixclk, vco);
10425
10426         /*
10427          * FIXME move the cdclk caclulation to
10428          * compute_config() so we can fail gracegully.
10429          */
10430         if (cdclk > dev_priv->max_cdclk_freq) {
10431                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10432                           cdclk, dev_priv->max_cdclk_freq);
10433                 cdclk = dev_priv->max_cdclk_freq;
10434         }
10435
10436         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10437         if (!intel_state->active_crtcs)
10438                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10439
10440         return 0;
10441 }
10442
10443 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10444 {
10445         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10446         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10447         unsigned int req_cdclk = intel_state->dev_cdclk;
10448         unsigned int req_vco = intel_state->cdclk_pll_vco;
10449
10450         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10451 }
10452
10453 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10454                                       struct intel_crtc_state *crtc_state)
10455 {
10456         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10457                 if (!intel_ddi_pll_select(crtc, crtc_state))
10458                         return -EINVAL;
10459         }
10460
10461         crtc->lowfreq_avail = false;
10462
10463         return 0;
10464 }
10465
10466 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10467                                 enum port port,
10468                                 struct intel_crtc_state *pipe_config)
10469 {
10470         enum intel_dpll_id id;
10471
10472         switch (port) {
10473         case PORT_A:
10474                 id = DPLL_ID_SKL_DPLL0;
10475                 break;
10476         case PORT_B:
10477                 id = DPLL_ID_SKL_DPLL1;
10478                 break;
10479         case PORT_C:
10480                 id = DPLL_ID_SKL_DPLL2;
10481                 break;
10482         default:
10483                 DRM_ERROR("Incorrect port type\n");
10484                 return;
10485         }
10486
10487         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10488 }
10489
10490 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10491                                 enum port port,
10492                                 struct intel_crtc_state *pipe_config)
10493 {
10494         enum intel_dpll_id id;
10495         u32 temp;
10496
10497         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10498         id = temp >> (port * 3 + 1);
10499
10500         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10501                 return;
10502
10503         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10504 }
10505
10506 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10507                                 enum port port,
10508                                 struct intel_crtc_state *pipe_config)
10509 {
10510         enum intel_dpll_id id;
10511         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10512
10513         switch (ddi_pll_sel) {
10514         case PORT_CLK_SEL_WRPLL1:
10515                 id = DPLL_ID_WRPLL1;
10516                 break;
10517         case PORT_CLK_SEL_WRPLL2:
10518                 id = DPLL_ID_WRPLL2;
10519                 break;
10520         case PORT_CLK_SEL_SPLL:
10521                 id = DPLL_ID_SPLL;
10522                 break;
10523         case PORT_CLK_SEL_LCPLL_810:
10524                 id = DPLL_ID_LCPLL_810;
10525                 break;
10526         case PORT_CLK_SEL_LCPLL_1350:
10527                 id = DPLL_ID_LCPLL_1350;
10528                 break;
10529         case PORT_CLK_SEL_LCPLL_2700:
10530                 id = DPLL_ID_LCPLL_2700;
10531                 break;
10532         default:
10533                 MISSING_CASE(ddi_pll_sel);
10534                 /* fall through */
10535         case PORT_CLK_SEL_NONE:
10536                 return;
10537         }
10538
10539         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10540 }
10541
10542 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10543                                      struct intel_crtc_state *pipe_config,
10544                                      unsigned long *power_domain_mask)
10545 {
10546         struct drm_device *dev = crtc->base.dev;
10547         struct drm_i915_private *dev_priv = to_i915(dev);
10548         enum intel_display_power_domain power_domain;
10549         u32 tmp;
10550
10551         /*
10552          * The pipe->transcoder mapping is fixed with the exception of the eDP
10553          * transcoder handled below.
10554          */
10555         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10556
10557         /*
10558          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10559          * consistency and less surprising code; it's in always on power).
10560          */
10561         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10562         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10563                 enum pipe trans_edp_pipe;
10564                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10565                 default:
10566                         WARN(1, "unknown pipe linked to edp transcoder\n");
10567                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10568                 case TRANS_DDI_EDP_INPUT_A_ON:
10569                         trans_edp_pipe = PIPE_A;
10570                         break;
10571                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10572                         trans_edp_pipe = PIPE_B;
10573                         break;
10574                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10575                         trans_edp_pipe = PIPE_C;
10576                         break;
10577                 }
10578
10579                 if (trans_edp_pipe == crtc->pipe)
10580                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10581         }
10582
10583         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10584         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10585                 return false;
10586         *power_domain_mask |= BIT(power_domain);
10587
10588         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10589
10590         return tmp & PIPECONF_ENABLE;
10591 }
10592
10593 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10594                                          struct intel_crtc_state *pipe_config,
10595                                          unsigned long *power_domain_mask)
10596 {
10597         struct drm_device *dev = crtc->base.dev;
10598         struct drm_i915_private *dev_priv = to_i915(dev);
10599         enum intel_display_power_domain power_domain;
10600         enum port port;
10601         enum transcoder cpu_transcoder;
10602         u32 tmp;
10603
10604         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10605                 if (port == PORT_A)
10606                         cpu_transcoder = TRANSCODER_DSI_A;
10607                 else
10608                         cpu_transcoder = TRANSCODER_DSI_C;
10609
10610                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10611                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10612                         continue;
10613                 *power_domain_mask |= BIT(power_domain);
10614
10615                 /*
10616                  * The PLL needs to be enabled with a valid divider
10617                  * configuration, otherwise accessing DSI registers will hang
10618                  * the machine. See BSpec North Display Engine
10619                  * registers/MIPI[BXT]. We can break out here early, since we
10620                  * need the same DSI PLL to be enabled for both DSI ports.
10621                  */
10622                 if (!intel_dsi_pll_is_enabled(dev_priv))
10623                         break;
10624
10625                 /* XXX: this works for video mode only */
10626                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10627                 if (!(tmp & DPI_ENABLE))
10628                         continue;
10629
10630                 tmp = I915_READ(MIPI_CTRL(port));
10631                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10632                         continue;
10633
10634                 pipe_config->cpu_transcoder = cpu_transcoder;
10635                 break;
10636         }
10637
10638         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10639 }
10640
10641 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10642                                        struct intel_crtc_state *pipe_config)
10643 {
10644         struct drm_device *dev = crtc->base.dev;
10645         struct drm_i915_private *dev_priv = to_i915(dev);
10646         struct intel_shared_dpll *pll;
10647         enum port port;
10648         uint32_t tmp;
10649
10650         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10651
10652         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10653
10654         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10655                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10656         else if (IS_BROXTON(dev))
10657                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10658         else
10659                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10660
10661         pll = pipe_config->shared_dpll;
10662         if (pll) {
10663                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10664                                                  &pipe_config->dpll_hw_state));
10665         }
10666
10667         /*
10668          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10669          * DDI E. So just check whether this pipe is wired to DDI E and whether
10670          * the PCH transcoder is on.
10671          */
10672         if (INTEL_INFO(dev)->gen < 9 &&
10673             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10674                 pipe_config->has_pch_encoder = true;
10675
10676                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10677                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10678                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10679
10680                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10681         }
10682 }
10683
10684 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10685                                     struct intel_crtc_state *pipe_config)
10686 {
10687         struct drm_device *dev = crtc->base.dev;
10688         struct drm_i915_private *dev_priv = to_i915(dev);
10689         enum intel_display_power_domain power_domain;
10690         unsigned long power_domain_mask;
10691         bool active;
10692
10693         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10694         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10695                 return false;
10696         power_domain_mask = BIT(power_domain);
10697
10698         pipe_config->shared_dpll = NULL;
10699
10700         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10701
10702         if (IS_BROXTON(dev_priv) &&
10703             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10704                 WARN_ON(active);
10705                 active = true;
10706         }
10707
10708         if (!active)
10709                 goto out;
10710
10711         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10712                 haswell_get_ddi_port_state(crtc, pipe_config);
10713                 intel_get_pipe_timings(crtc, pipe_config);
10714         }
10715
10716         intel_get_pipe_src_size(crtc, pipe_config);
10717
10718         pipe_config->gamma_mode =
10719                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10720
10721         if (INTEL_INFO(dev)->gen >= 9) {
10722                 skl_init_scalers(dev, crtc, pipe_config);
10723         }
10724
10725         if (INTEL_INFO(dev)->gen >= 9) {
10726                 pipe_config->scaler_state.scaler_id = -1;
10727                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10728         }
10729
10730         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10731         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10732                 power_domain_mask |= BIT(power_domain);
10733                 if (INTEL_INFO(dev)->gen >= 9)
10734                         skylake_get_pfit_config(crtc, pipe_config);
10735                 else
10736                         ironlake_get_pfit_config(crtc, pipe_config);
10737         }
10738
10739         if (IS_HASWELL(dev))
10740                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10741                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10742
10743         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10744             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10745                 pipe_config->pixel_multiplier =
10746                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10747         } else {
10748                 pipe_config->pixel_multiplier = 1;
10749         }
10750
10751 out:
10752         for_each_power_domain(power_domain, power_domain_mask)
10753                 intel_display_power_put(dev_priv, power_domain);
10754
10755         return active;
10756 }
10757
10758 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10759                                const struct intel_plane_state *plane_state)
10760 {
10761         struct drm_device *dev = crtc->dev;
10762         struct drm_i915_private *dev_priv = to_i915(dev);
10763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10764         uint32_t cntl = 0, size = 0;
10765
10766         if (plane_state && plane_state->base.visible) {
10767                 unsigned int width = plane_state->base.crtc_w;
10768                 unsigned int height = plane_state->base.crtc_h;
10769                 unsigned int stride = roundup_pow_of_two(width) * 4;
10770
10771                 switch (stride) {
10772                 default:
10773                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10774                                   width, stride);
10775                         stride = 256;
10776                         /* fallthrough */
10777                 case 256:
10778                 case 512:
10779                 case 1024:
10780                 case 2048:
10781                         break;
10782                 }
10783
10784                 cntl |= CURSOR_ENABLE |
10785                         CURSOR_GAMMA_ENABLE |
10786                         CURSOR_FORMAT_ARGB |
10787                         CURSOR_STRIDE(stride);
10788
10789                 size = (height << 12) | width;
10790         }
10791
10792         if (intel_crtc->cursor_cntl != 0 &&
10793             (intel_crtc->cursor_base != base ||
10794              intel_crtc->cursor_size != size ||
10795              intel_crtc->cursor_cntl != cntl)) {
10796                 /* On these chipsets we can only modify the base/size/stride
10797                  * whilst the cursor is disabled.
10798                  */
10799                 I915_WRITE(CURCNTR(PIPE_A), 0);
10800                 POSTING_READ(CURCNTR(PIPE_A));
10801                 intel_crtc->cursor_cntl = 0;
10802         }
10803
10804         if (intel_crtc->cursor_base != base) {
10805                 I915_WRITE(CURBASE(PIPE_A), base);
10806                 intel_crtc->cursor_base = base;
10807         }
10808
10809         if (intel_crtc->cursor_size != size) {
10810                 I915_WRITE(CURSIZE, size);
10811                 intel_crtc->cursor_size = size;
10812         }
10813
10814         if (intel_crtc->cursor_cntl != cntl) {
10815                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10816                 POSTING_READ(CURCNTR(PIPE_A));
10817                 intel_crtc->cursor_cntl = cntl;
10818         }
10819 }
10820
10821 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10822                                const struct intel_plane_state *plane_state)
10823 {
10824         struct drm_device *dev = crtc->dev;
10825         struct drm_i915_private *dev_priv = to_i915(dev);
10826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10827         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10828         int pipe = intel_crtc->pipe;
10829         uint32_t cntl = 0;
10830
10831         if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10832                 skl_write_cursor_wm(intel_crtc, wm);
10833
10834         if (plane_state && plane_state->base.visible) {
10835                 cntl = MCURSOR_GAMMA_ENABLE;
10836                 switch (plane_state->base.crtc_w) {
10837                         case 64:
10838                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10839                                 break;
10840                         case 128:
10841                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10842                                 break;
10843                         case 256:
10844                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10845                                 break;
10846                         default:
10847                                 MISSING_CASE(plane_state->base.crtc_w);
10848                                 return;
10849                 }
10850                 cntl |= pipe << 28; /* Connect to correct pipe */
10851
10852                 if (HAS_DDI(dev))
10853                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10854
10855                 if (plane_state->base.rotation == DRM_ROTATE_180)
10856                         cntl |= CURSOR_ROTATE_180;
10857         }
10858
10859         if (intel_crtc->cursor_cntl != cntl) {
10860                 I915_WRITE(CURCNTR(pipe), cntl);
10861                 POSTING_READ(CURCNTR(pipe));
10862                 intel_crtc->cursor_cntl = cntl;
10863         }
10864
10865         /* and commit changes on next vblank */
10866         I915_WRITE(CURBASE(pipe), base);
10867         POSTING_READ(CURBASE(pipe));
10868
10869         intel_crtc->cursor_base = base;
10870 }
10871
10872 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10873 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10874                                      const struct intel_plane_state *plane_state)
10875 {
10876         struct drm_device *dev = crtc->dev;
10877         struct drm_i915_private *dev_priv = to_i915(dev);
10878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10879         int pipe = intel_crtc->pipe;
10880         u32 base = intel_crtc->cursor_addr;
10881         u32 pos = 0;
10882
10883         if (plane_state) {
10884                 int x = plane_state->base.crtc_x;
10885                 int y = plane_state->base.crtc_y;
10886
10887                 if (x < 0) {
10888                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10889                         x = -x;
10890                 }
10891                 pos |= x << CURSOR_X_SHIFT;
10892
10893                 if (y < 0) {
10894                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10895                         y = -y;
10896                 }
10897                 pos |= y << CURSOR_Y_SHIFT;
10898
10899                 /* ILK+ do this automagically */
10900                 if (HAS_GMCH_DISPLAY(dev) &&
10901                     plane_state->base.rotation == DRM_ROTATE_180) {
10902                         base += (plane_state->base.crtc_h *
10903                                  plane_state->base.crtc_w - 1) * 4;
10904                 }
10905         }
10906
10907         I915_WRITE(CURPOS(pipe), pos);
10908
10909         if (IS_845G(dev) || IS_I865G(dev))
10910                 i845_update_cursor(crtc, base, plane_state);
10911         else
10912                 i9xx_update_cursor(crtc, base, plane_state);
10913 }
10914
10915 static bool cursor_size_ok(struct drm_device *dev,
10916                            uint32_t width, uint32_t height)
10917 {
10918         if (width == 0 || height == 0)
10919                 return false;
10920
10921         /*
10922          * 845g/865g are special in that they are only limited by
10923          * the width of their cursors, the height is arbitrary up to
10924          * the precision of the register. Everything else requires
10925          * square cursors, limited to a few power-of-two sizes.
10926          */
10927         if (IS_845G(dev) || IS_I865G(dev)) {
10928                 if ((width & 63) != 0)
10929                         return false;
10930
10931                 if (width > (IS_845G(dev) ? 64 : 512))
10932                         return false;
10933
10934                 if (height > 1023)
10935                         return false;
10936         } else {
10937                 switch (width | height) {
10938                 case 256:
10939                 case 128:
10940                         if (IS_GEN2(dev))
10941                                 return false;
10942                 case 64:
10943                         break;
10944                 default:
10945                         return false;
10946                 }
10947         }
10948
10949         return true;
10950 }
10951
10952 /* VESA 640x480x72Hz mode to set on the pipe */
10953 static struct drm_display_mode load_detect_mode = {
10954         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10955                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10956 };
10957
10958 struct drm_framebuffer *
10959 __intel_framebuffer_create(struct drm_device *dev,
10960                            struct drm_mode_fb_cmd2 *mode_cmd,
10961                            struct drm_i915_gem_object *obj)
10962 {
10963         struct intel_framebuffer *intel_fb;
10964         int ret;
10965
10966         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10967         if (!intel_fb)
10968                 return ERR_PTR(-ENOMEM);
10969
10970         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10971         if (ret)
10972                 goto err;
10973
10974         return &intel_fb->base;
10975
10976 err:
10977         kfree(intel_fb);
10978         return ERR_PTR(ret);
10979 }
10980
10981 static struct drm_framebuffer *
10982 intel_framebuffer_create(struct drm_device *dev,
10983                          struct drm_mode_fb_cmd2 *mode_cmd,
10984                          struct drm_i915_gem_object *obj)
10985 {
10986         struct drm_framebuffer *fb;
10987         int ret;
10988
10989         ret = i915_mutex_lock_interruptible(dev);
10990         if (ret)
10991                 return ERR_PTR(ret);
10992         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10993         mutex_unlock(&dev->struct_mutex);
10994
10995         return fb;
10996 }
10997
10998 static u32
10999 intel_framebuffer_pitch_for_width(int width, int bpp)
11000 {
11001         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11002         return ALIGN(pitch, 64);
11003 }
11004
11005 static u32
11006 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11007 {
11008         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11009         return PAGE_ALIGN(pitch * mode->vdisplay);
11010 }
11011
11012 static struct drm_framebuffer *
11013 intel_framebuffer_create_for_mode(struct drm_device *dev,
11014                                   struct drm_display_mode *mode,
11015                                   int depth, int bpp)
11016 {
11017         struct drm_framebuffer *fb;
11018         struct drm_i915_gem_object *obj;
11019         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11020
11021         obj = i915_gem_object_create(dev,
11022                                     intel_framebuffer_size_for_mode(mode, bpp));
11023         if (IS_ERR(obj))
11024                 return ERR_CAST(obj);
11025
11026         mode_cmd.width = mode->hdisplay;
11027         mode_cmd.height = mode->vdisplay;
11028         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11029                                                                 bpp);
11030         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11031
11032         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11033         if (IS_ERR(fb))
11034                 i915_gem_object_put_unlocked(obj);
11035
11036         return fb;
11037 }
11038
11039 static struct drm_framebuffer *
11040 mode_fits_in_fbdev(struct drm_device *dev,
11041                    struct drm_display_mode *mode)
11042 {
11043 #ifdef CONFIG_DRM_FBDEV_EMULATION
11044         struct drm_i915_private *dev_priv = to_i915(dev);
11045         struct drm_i915_gem_object *obj;
11046         struct drm_framebuffer *fb;
11047
11048         if (!dev_priv->fbdev)
11049                 return NULL;
11050
11051         if (!dev_priv->fbdev->fb)
11052                 return NULL;
11053
11054         obj = dev_priv->fbdev->fb->obj;
11055         BUG_ON(!obj);
11056
11057         fb = &dev_priv->fbdev->fb->base;
11058         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11059                                                                fb->bits_per_pixel))
11060                 return NULL;
11061
11062         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11063                 return NULL;
11064
11065         drm_framebuffer_reference(fb);
11066         return fb;
11067 #else
11068         return NULL;
11069 #endif
11070 }
11071
11072 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11073                                            struct drm_crtc *crtc,
11074                                            struct drm_display_mode *mode,
11075                                            struct drm_framebuffer *fb,
11076                                            int x, int y)
11077 {
11078         struct drm_plane_state *plane_state;
11079         int hdisplay, vdisplay;
11080         int ret;
11081
11082         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11083         if (IS_ERR(plane_state))
11084                 return PTR_ERR(plane_state);
11085
11086         if (mode)
11087                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11088         else
11089                 hdisplay = vdisplay = 0;
11090
11091         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11092         if (ret)
11093                 return ret;
11094         drm_atomic_set_fb_for_plane(plane_state, fb);
11095         plane_state->crtc_x = 0;
11096         plane_state->crtc_y = 0;
11097         plane_state->crtc_w = hdisplay;
11098         plane_state->crtc_h = vdisplay;
11099         plane_state->src_x = x << 16;
11100         plane_state->src_y = y << 16;
11101         plane_state->src_w = hdisplay << 16;
11102         plane_state->src_h = vdisplay << 16;
11103
11104         return 0;
11105 }
11106
11107 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11108                                 struct drm_display_mode *mode,
11109                                 struct intel_load_detect_pipe *old,
11110                                 struct drm_modeset_acquire_ctx *ctx)
11111 {
11112         struct intel_crtc *intel_crtc;
11113         struct intel_encoder *intel_encoder =
11114                 intel_attached_encoder(connector);
11115         struct drm_crtc *possible_crtc;
11116         struct drm_encoder *encoder = &intel_encoder->base;
11117         struct drm_crtc *crtc = NULL;
11118         struct drm_device *dev = encoder->dev;
11119         struct drm_framebuffer *fb;
11120         struct drm_mode_config *config = &dev->mode_config;
11121         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11122         struct drm_connector_state *connector_state;
11123         struct intel_crtc_state *crtc_state;
11124         int ret, i = -1;
11125
11126         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11127                       connector->base.id, connector->name,
11128                       encoder->base.id, encoder->name);
11129
11130         old->restore_state = NULL;
11131
11132 retry:
11133         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11134         if (ret)
11135                 goto fail;
11136
11137         /*
11138          * Algorithm gets a little messy:
11139          *
11140          *   - if the connector already has an assigned crtc, use it (but make
11141          *     sure it's on first)
11142          *
11143          *   - try to find the first unused crtc that can drive this connector,
11144          *     and use that if we find one
11145          */
11146
11147         /* See if we already have a CRTC for this connector */
11148         if (connector->state->crtc) {
11149                 crtc = connector->state->crtc;
11150
11151                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11152                 if (ret)
11153                         goto fail;
11154
11155                 /* Make sure the crtc and connector are running */
11156                 goto found;
11157         }
11158
11159         /* Find an unused one (if possible) */
11160         for_each_crtc(dev, possible_crtc) {
11161                 i++;
11162                 if (!(encoder->possible_crtcs & (1 << i)))
11163                         continue;
11164
11165                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11166                 if (ret)
11167                         goto fail;
11168
11169                 if (possible_crtc->state->enable) {
11170                         drm_modeset_unlock(&possible_crtc->mutex);
11171                         continue;
11172                 }
11173
11174                 crtc = possible_crtc;
11175                 break;
11176         }
11177
11178         /*
11179          * If we didn't find an unused CRTC, don't use any.
11180          */
11181         if (!crtc) {
11182                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11183                 goto fail;
11184         }
11185
11186 found:
11187         intel_crtc = to_intel_crtc(crtc);
11188
11189         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11190         if (ret)
11191                 goto fail;
11192
11193         state = drm_atomic_state_alloc(dev);
11194         restore_state = drm_atomic_state_alloc(dev);
11195         if (!state || !restore_state) {
11196                 ret = -ENOMEM;
11197                 goto fail;
11198         }
11199
11200         state->acquire_ctx = ctx;
11201         restore_state->acquire_ctx = ctx;
11202
11203         connector_state = drm_atomic_get_connector_state(state, connector);
11204         if (IS_ERR(connector_state)) {
11205                 ret = PTR_ERR(connector_state);
11206                 goto fail;
11207         }
11208
11209         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11210         if (ret)
11211                 goto fail;
11212
11213         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11214         if (IS_ERR(crtc_state)) {
11215                 ret = PTR_ERR(crtc_state);
11216                 goto fail;
11217         }
11218
11219         crtc_state->base.active = crtc_state->base.enable = true;
11220
11221         if (!mode)
11222                 mode = &load_detect_mode;
11223
11224         /* We need a framebuffer large enough to accommodate all accesses
11225          * that the plane may generate whilst we perform load detection.
11226          * We can not rely on the fbcon either being present (we get called
11227          * during its initialisation to detect all boot displays, or it may
11228          * not even exist) or that it is large enough to satisfy the
11229          * requested mode.
11230          */
11231         fb = mode_fits_in_fbdev(dev, mode);
11232         if (fb == NULL) {
11233                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11234                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11235         } else
11236                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11237         if (IS_ERR(fb)) {
11238                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11239                 goto fail;
11240         }
11241
11242         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11243         if (ret)
11244                 goto fail;
11245
11246         drm_framebuffer_unreference(fb);
11247
11248         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11249         if (ret)
11250                 goto fail;
11251
11252         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11253         if (!ret)
11254                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11255         if (!ret)
11256                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11257         if (ret) {
11258                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11259                 goto fail;
11260         }
11261
11262         ret = drm_atomic_commit(state);
11263         if (ret) {
11264                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11265                 goto fail;
11266         }
11267
11268         old->restore_state = restore_state;
11269
11270         /* let the connector get through one full cycle before testing */
11271         intel_wait_for_vblank(dev, intel_crtc->pipe);
11272         return true;
11273
11274 fail:
11275         if (state) {
11276                 drm_atomic_state_put(state);
11277                 state = NULL;
11278         }
11279         if (restore_state) {
11280                 drm_atomic_state_put(restore_state);
11281                 restore_state = NULL;
11282         }
11283
11284         if (ret == -EDEADLK) {
11285                 drm_modeset_backoff(ctx);
11286                 goto retry;
11287         }
11288
11289         return false;
11290 }
11291
11292 void intel_release_load_detect_pipe(struct drm_connector *connector,
11293                                     struct intel_load_detect_pipe *old,
11294                                     struct drm_modeset_acquire_ctx *ctx)
11295 {
11296         struct intel_encoder *intel_encoder =
11297                 intel_attached_encoder(connector);
11298         struct drm_encoder *encoder = &intel_encoder->base;
11299         struct drm_atomic_state *state = old->restore_state;
11300         int ret;
11301
11302         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11303                       connector->base.id, connector->name,
11304                       encoder->base.id, encoder->name);
11305
11306         if (!state)
11307                 return;
11308
11309         ret = drm_atomic_commit(state);
11310         if (ret)
11311                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11312         drm_atomic_state_put(state);
11313 }
11314
11315 static int i9xx_pll_refclk(struct drm_device *dev,
11316                            const struct intel_crtc_state *pipe_config)
11317 {
11318         struct drm_i915_private *dev_priv = to_i915(dev);
11319         u32 dpll = pipe_config->dpll_hw_state.dpll;
11320
11321         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11322                 return dev_priv->vbt.lvds_ssc_freq;
11323         else if (HAS_PCH_SPLIT(dev))
11324                 return 120000;
11325         else if (!IS_GEN2(dev))
11326                 return 96000;
11327         else
11328                 return 48000;
11329 }
11330
11331 /* Returns the clock of the currently programmed mode of the given pipe. */
11332 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11333                                 struct intel_crtc_state *pipe_config)
11334 {
11335         struct drm_device *dev = crtc->base.dev;
11336         struct drm_i915_private *dev_priv = to_i915(dev);
11337         int pipe = pipe_config->cpu_transcoder;
11338         u32 dpll = pipe_config->dpll_hw_state.dpll;
11339         u32 fp;
11340         struct dpll clock;
11341         int port_clock;
11342         int refclk = i9xx_pll_refclk(dev, pipe_config);
11343
11344         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11345                 fp = pipe_config->dpll_hw_state.fp0;
11346         else
11347                 fp = pipe_config->dpll_hw_state.fp1;
11348
11349         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11350         if (IS_PINEVIEW(dev)) {
11351                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11352                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11353         } else {
11354                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11355                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11356         }
11357
11358         if (!IS_GEN2(dev)) {
11359                 if (IS_PINEVIEW(dev))
11360                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11361                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11362                 else
11363                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11364                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11365
11366                 switch (dpll & DPLL_MODE_MASK) {
11367                 case DPLLB_MODE_DAC_SERIAL:
11368                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11369                                 5 : 10;
11370                         break;
11371                 case DPLLB_MODE_LVDS:
11372                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11373                                 7 : 14;
11374                         break;
11375                 default:
11376                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11377                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11378                         return;
11379                 }
11380
11381                 if (IS_PINEVIEW(dev))
11382                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11383                 else
11384                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11385         } else {
11386                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11387                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11388
11389                 if (is_lvds) {
11390                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11391                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11392
11393                         if (lvds & LVDS_CLKB_POWER_UP)
11394                                 clock.p2 = 7;
11395                         else
11396                                 clock.p2 = 14;
11397                 } else {
11398                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11399                                 clock.p1 = 2;
11400                         else {
11401                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11402                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11403                         }
11404                         if (dpll & PLL_P2_DIVIDE_BY_4)
11405                                 clock.p2 = 4;
11406                         else
11407                                 clock.p2 = 2;
11408                 }
11409
11410                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11411         }
11412
11413         /*
11414          * This value includes pixel_multiplier. We will use
11415          * port_clock to compute adjusted_mode.crtc_clock in the
11416          * encoder's get_config() function.
11417          */
11418         pipe_config->port_clock = port_clock;
11419 }
11420
11421 int intel_dotclock_calculate(int link_freq,
11422                              const struct intel_link_m_n *m_n)
11423 {
11424         /*
11425          * The calculation for the data clock is:
11426          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11427          * But we want to avoid losing precison if possible, so:
11428          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11429          *
11430          * and the link clock is simpler:
11431          * link_clock = (m * link_clock) / n
11432          */
11433
11434         if (!m_n->link_n)
11435                 return 0;
11436
11437         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11438 }
11439
11440 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11441                                    struct intel_crtc_state *pipe_config)
11442 {
11443         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11444
11445         /* read out port_clock from the DPLL */
11446         i9xx_crtc_clock_get(crtc, pipe_config);
11447
11448         /*
11449          * In case there is an active pipe without active ports,
11450          * we may need some idea for the dotclock anyway.
11451          * Calculate one based on the FDI configuration.
11452          */
11453         pipe_config->base.adjusted_mode.crtc_clock =
11454                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11455                                          &pipe_config->fdi_m_n);
11456 }
11457
11458 /** Returns the currently programmed mode of the given pipe. */
11459 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11460                                              struct drm_crtc *crtc)
11461 {
11462         struct drm_i915_private *dev_priv = to_i915(dev);
11463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11464         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11465         struct drm_display_mode *mode;
11466         struct intel_crtc_state *pipe_config;
11467         int htot = I915_READ(HTOTAL(cpu_transcoder));
11468         int hsync = I915_READ(HSYNC(cpu_transcoder));
11469         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11470         int vsync = I915_READ(VSYNC(cpu_transcoder));
11471         enum pipe pipe = intel_crtc->pipe;
11472
11473         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11474         if (!mode)
11475                 return NULL;
11476
11477         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11478         if (!pipe_config) {
11479                 kfree(mode);
11480                 return NULL;
11481         }
11482
11483         /*
11484          * Construct a pipe_config sufficient for getting the clock info
11485          * back out of crtc_clock_get.
11486          *
11487          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11488          * to use a real value here instead.
11489          */
11490         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11491         pipe_config->pixel_multiplier = 1;
11492         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11493         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11494         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11495         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11496
11497         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11498         mode->hdisplay = (htot & 0xffff) + 1;
11499         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11500         mode->hsync_start = (hsync & 0xffff) + 1;
11501         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11502         mode->vdisplay = (vtot & 0xffff) + 1;
11503         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11504         mode->vsync_start = (vsync & 0xffff) + 1;
11505         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11506
11507         drm_mode_set_name(mode);
11508
11509         kfree(pipe_config);
11510
11511         return mode;
11512 }
11513
11514 static void intel_crtc_destroy(struct drm_crtc *crtc)
11515 {
11516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11517         struct drm_device *dev = crtc->dev;
11518         struct intel_flip_work *work;
11519
11520         spin_lock_irq(&dev->event_lock);
11521         work = intel_crtc->flip_work;
11522         intel_crtc->flip_work = NULL;
11523         spin_unlock_irq(&dev->event_lock);
11524
11525         if (work) {
11526                 cancel_work_sync(&work->mmio_work);
11527                 cancel_work_sync(&work->unpin_work);
11528                 kfree(work);
11529         }
11530
11531         drm_crtc_cleanup(crtc);
11532
11533         kfree(intel_crtc);
11534 }
11535
11536 static void intel_unpin_work_fn(struct work_struct *__work)
11537 {
11538         struct intel_flip_work *work =
11539                 container_of(__work, struct intel_flip_work, unpin_work);
11540         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11541         struct drm_device *dev = crtc->base.dev;
11542         struct drm_plane *primary = crtc->base.primary;
11543
11544         if (is_mmio_work(work))
11545                 flush_work(&work->mmio_work);
11546
11547         mutex_lock(&dev->struct_mutex);
11548         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11549         i915_gem_object_put(work->pending_flip_obj);
11550         mutex_unlock(&dev->struct_mutex);
11551
11552         i915_gem_request_put(work->flip_queued_req);
11553
11554         intel_frontbuffer_flip_complete(to_i915(dev),
11555                                         to_intel_plane(primary)->frontbuffer_bit);
11556         intel_fbc_post_update(crtc);
11557         drm_framebuffer_unreference(work->old_fb);
11558
11559         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11560         atomic_dec(&crtc->unpin_work_count);
11561
11562         kfree(work);
11563 }
11564
11565 /* Is 'a' after or equal to 'b'? */
11566 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11567 {
11568         return !((a - b) & 0x80000000);
11569 }
11570
11571 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11572                                    struct intel_flip_work *work)
11573 {
11574         struct drm_device *dev = crtc->base.dev;
11575         struct drm_i915_private *dev_priv = to_i915(dev);
11576
11577         if (abort_flip_on_reset(crtc))
11578                 return true;
11579
11580         /*
11581          * The relevant registers doen't exist on pre-ctg.
11582          * As the flip done interrupt doesn't trigger for mmio
11583          * flips on gmch platforms, a flip count check isn't
11584          * really needed there. But since ctg has the registers,
11585          * include it in the check anyway.
11586          */
11587         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11588                 return true;
11589
11590         /*
11591          * BDW signals flip done immediately if the plane
11592          * is disabled, even if the plane enable is already
11593          * armed to occur at the next vblank :(
11594          */
11595
11596         /*
11597          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11598          * used the same base address. In that case the mmio flip might
11599          * have completed, but the CS hasn't even executed the flip yet.
11600          *
11601          * A flip count check isn't enough as the CS might have updated
11602          * the base address just after start of vblank, but before we
11603          * managed to process the interrupt. This means we'd complete the
11604          * CS flip too soon.
11605          *
11606          * Combining both checks should get us a good enough result. It may
11607          * still happen that the CS flip has been executed, but has not
11608          * yet actually completed. But in case the base address is the same
11609          * anyway, we don't really care.
11610          */
11611         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11612                 crtc->flip_work->gtt_offset &&
11613                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11614                                     crtc->flip_work->flip_count);
11615 }
11616
11617 static bool
11618 __pageflip_finished_mmio(struct intel_crtc *crtc,
11619                                struct intel_flip_work *work)
11620 {
11621         /*
11622          * MMIO work completes when vblank is different from
11623          * flip_queued_vblank.
11624          *
11625          * Reset counter value doesn't matter, this is handled by
11626          * i915_wait_request finishing early, so no need to handle
11627          * reset here.
11628          */
11629         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11630 }
11631
11632
11633 static bool pageflip_finished(struct intel_crtc *crtc,
11634                               struct intel_flip_work *work)
11635 {
11636         if (!atomic_read(&work->pending))
11637                 return false;
11638
11639         smp_rmb();
11640
11641         if (is_mmio_work(work))
11642                 return __pageflip_finished_mmio(crtc, work);
11643         else
11644                 return __pageflip_finished_cs(crtc, work);
11645 }
11646
11647 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11648 {
11649         struct drm_device *dev = &dev_priv->drm;
11650         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11652         struct intel_flip_work *work;
11653         unsigned long flags;
11654
11655         /* Ignore early vblank irqs */
11656         if (!crtc)
11657                 return;
11658
11659         /*
11660          * This is called both by irq handlers and the reset code (to complete
11661          * lost pageflips) so needs the full irqsave spinlocks.
11662          */
11663         spin_lock_irqsave(&dev->event_lock, flags);
11664         work = intel_crtc->flip_work;
11665
11666         if (work != NULL &&
11667             !is_mmio_work(work) &&
11668             pageflip_finished(intel_crtc, work))
11669                 page_flip_completed(intel_crtc);
11670
11671         spin_unlock_irqrestore(&dev->event_lock, flags);
11672 }
11673
11674 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11675 {
11676         struct drm_device *dev = &dev_priv->drm;
11677         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11679         struct intel_flip_work *work;
11680         unsigned long flags;
11681
11682         /* Ignore early vblank irqs */
11683         if (!crtc)
11684                 return;
11685
11686         /*
11687          * This is called both by irq handlers and the reset code (to complete
11688          * lost pageflips) so needs the full irqsave spinlocks.
11689          */
11690         spin_lock_irqsave(&dev->event_lock, flags);
11691         work = intel_crtc->flip_work;
11692
11693         if (work != NULL &&
11694             is_mmio_work(work) &&
11695             pageflip_finished(intel_crtc, work))
11696                 page_flip_completed(intel_crtc);
11697
11698         spin_unlock_irqrestore(&dev->event_lock, flags);
11699 }
11700
11701 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11702                                                struct intel_flip_work *work)
11703 {
11704         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11705
11706         /* Ensure that the work item is consistent when activating it ... */
11707         smp_mb__before_atomic();
11708         atomic_set(&work->pending, 1);
11709 }
11710
11711 static int intel_gen2_queue_flip(struct drm_device *dev,
11712                                  struct drm_crtc *crtc,
11713                                  struct drm_framebuffer *fb,
11714                                  struct drm_i915_gem_object *obj,
11715                                  struct drm_i915_gem_request *req,
11716                                  uint32_t flags)
11717 {
11718         struct intel_ring *ring = req->ring;
11719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11720         u32 flip_mask;
11721         int ret;
11722
11723         ret = intel_ring_begin(req, 6);
11724         if (ret)
11725                 return ret;
11726
11727         /* Can't queue multiple flips, so wait for the previous
11728          * one to finish before executing the next.
11729          */
11730         if (intel_crtc->plane)
11731                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11732         else
11733                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11734         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11735         intel_ring_emit(ring, MI_NOOP);
11736         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11737                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11738         intel_ring_emit(ring, fb->pitches[0]);
11739         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11740         intel_ring_emit(ring, 0); /* aux display base address, unused */
11741
11742         return 0;
11743 }
11744
11745 static int intel_gen3_queue_flip(struct drm_device *dev,
11746                                  struct drm_crtc *crtc,
11747                                  struct drm_framebuffer *fb,
11748                                  struct drm_i915_gem_object *obj,
11749                                  struct drm_i915_gem_request *req,
11750                                  uint32_t flags)
11751 {
11752         struct intel_ring *ring = req->ring;
11753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11754         u32 flip_mask;
11755         int ret;
11756
11757         ret = intel_ring_begin(req, 6);
11758         if (ret)
11759                 return ret;
11760
11761         if (intel_crtc->plane)
11762                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11763         else
11764                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11765         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11766         intel_ring_emit(ring, MI_NOOP);
11767         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11768                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11769         intel_ring_emit(ring, fb->pitches[0]);
11770         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11771         intel_ring_emit(ring, MI_NOOP);
11772
11773         return 0;
11774 }
11775
11776 static int intel_gen4_queue_flip(struct drm_device *dev,
11777                                  struct drm_crtc *crtc,
11778                                  struct drm_framebuffer *fb,
11779                                  struct drm_i915_gem_object *obj,
11780                                  struct drm_i915_gem_request *req,
11781                                  uint32_t flags)
11782 {
11783         struct intel_ring *ring = req->ring;
11784         struct drm_i915_private *dev_priv = to_i915(dev);
11785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11786         uint32_t pf, pipesrc;
11787         int ret;
11788
11789         ret = intel_ring_begin(req, 4);
11790         if (ret)
11791                 return ret;
11792
11793         /* i965+ uses the linear or tiled offsets from the
11794          * Display Registers (which do not change across a page-flip)
11795          * so we need only reprogram the base address.
11796          */
11797         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11798                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11799         intel_ring_emit(ring, fb->pitches[0]);
11800         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11801                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11802
11803         /* XXX Enabling the panel-fitter across page-flip is so far
11804          * untested on non-native modes, so ignore it for now.
11805          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11806          */
11807         pf = 0;
11808         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11809         intel_ring_emit(ring, pf | pipesrc);
11810
11811         return 0;
11812 }
11813
11814 static int intel_gen6_queue_flip(struct drm_device *dev,
11815                                  struct drm_crtc *crtc,
11816                                  struct drm_framebuffer *fb,
11817                                  struct drm_i915_gem_object *obj,
11818                                  struct drm_i915_gem_request *req,
11819                                  uint32_t flags)
11820 {
11821         struct intel_ring *ring = req->ring;
11822         struct drm_i915_private *dev_priv = to_i915(dev);
11823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11824         uint32_t pf, pipesrc;
11825         int ret;
11826
11827         ret = intel_ring_begin(req, 4);
11828         if (ret)
11829                 return ret;
11830
11831         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11832                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11833         intel_ring_emit(ring, fb->pitches[0] |
11834                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11835         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11836
11837         /* Contrary to the suggestions in the documentation,
11838          * "Enable Panel Fitter" does not seem to be required when page
11839          * flipping with a non-native mode, and worse causes a normal
11840          * modeset to fail.
11841          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11842          */
11843         pf = 0;
11844         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11845         intel_ring_emit(ring, pf | pipesrc);
11846
11847         return 0;
11848 }
11849
11850 static int intel_gen7_queue_flip(struct drm_device *dev,
11851                                  struct drm_crtc *crtc,
11852                                  struct drm_framebuffer *fb,
11853                                  struct drm_i915_gem_object *obj,
11854                                  struct drm_i915_gem_request *req,
11855                                  uint32_t flags)
11856 {
11857         struct intel_ring *ring = req->ring;
11858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11859         uint32_t plane_bit = 0;
11860         int len, ret;
11861
11862         switch (intel_crtc->plane) {
11863         case PLANE_A:
11864                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11865                 break;
11866         case PLANE_B:
11867                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11868                 break;
11869         case PLANE_C:
11870                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11871                 break;
11872         default:
11873                 WARN_ONCE(1, "unknown plane in flip command\n");
11874                 return -ENODEV;
11875         }
11876
11877         len = 4;
11878         if (req->engine->id == RCS) {
11879                 len += 6;
11880                 /*
11881                  * On Gen 8, SRM is now taking an extra dword to accommodate
11882                  * 48bits addresses, and we need a NOOP for the batch size to
11883                  * stay even.
11884                  */
11885                 if (IS_GEN8(dev))
11886                         len += 2;
11887         }
11888
11889         /*
11890          * BSpec MI_DISPLAY_FLIP for IVB:
11891          * "The full packet must be contained within the same cache line."
11892          *
11893          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11894          * cacheline, if we ever start emitting more commands before
11895          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11896          * then do the cacheline alignment, and finally emit the
11897          * MI_DISPLAY_FLIP.
11898          */
11899         ret = intel_ring_cacheline_align(req);
11900         if (ret)
11901                 return ret;
11902
11903         ret = intel_ring_begin(req, len);
11904         if (ret)
11905                 return ret;
11906
11907         /* Unmask the flip-done completion message. Note that the bspec says that
11908          * we should do this for both the BCS and RCS, and that we must not unmask
11909          * more than one flip event at any time (or ensure that one flip message
11910          * can be sent by waiting for flip-done prior to queueing new flips).
11911          * Experimentation says that BCS works despite DERRMR masking all
11912          * flip-done completion events and that unmasking all planes at once
11913          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11914          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11915          */
11916         if (req->engine->id == RCS) {
11917                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11918                 intel_ring_emit_reg(ring, DERRMR);
11919                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11920                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11921                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11922                 if (IS_GEN8(dev))
11923                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11924                                               MI_SRM_LRM_GLOBAL_GTT);
11925                 else
11926                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11927                                               MI_SRM_LRM_GLOBAL_GTT);
11928                 intel_ring_emit_reg(ring, DERRMR);
11929                 intel_ring_emit(ring,
11930                                 i915_ggtt_offset(req->engine->scratch) + 256);
11931                 if (IS_GEN8(dev)) {
11932                         intel_ring_emit(ring, 0);
11933                         intel_ring_emit(ring, MI_NOOP);
11934                 }
11935         }
11936
11937         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11938         intel_ring_emit(ring, fb->pitches[0] |
11939                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11940         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11941         intel_ring_emit(ring, (MI_NOOP));
11942
11943         return 0;
11944 }
11945
11946 static bool use_mmio_flip(struct intel_engine_cs *engine,
11947                           struct drm_i915_gem_object *obj)
11948 {
11949         struct reservation_object *resv;
11950
11951         /*
11952          * This is not being used for older platforms, because
11953          * non-availability of flip done interrupt forces us to use
11954          * CS flips. Older platforms derive flip done using some clever
11955          * tricks involving the flip_pending status bits and vblank irqs.
11956          * So using MMIO flips there would disrupt this mechanism.
11957          */
11958
11959         if (engine == NULL)
11960                 return true;
11961
11962         if (INTEL_GEN(engine->i915) < 5)
11963                 return false;
11964
11965         if (i915.use_mmio_flip < 0)
11966                 return false;
11967         else if (i915.use_mmio_flip > 0)
11968                 return true;
11969         else if (i915.enable_execlists)
11970                 return true;
11971
11972         resv = i915_gem_object_get_dmabuf_resv(obj);
11973         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11974                 return true;
11975
11976         return engine != i915_gem_active_get_engine(&obj->last_write,
11977                                                     &obj->base.dev->struct_mutex);
11978 }
11979
11980 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11981                              unsigned int rotation,
11982                              struct intel_flip_work *work)
11983 {
11984         struct drm_device *dev = intel_crtc->base.dev;
11985         struct drm_i915_private *dev_priv = to_i915(dev);
11986         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11987         const enum pipe pipe = intel_crtc->pipe;
11988         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11989
11990         ctl = I915_READ(PLANE_CTL(pipe, 0));
11991         ctl &= ~PLANE_CTL_TILED_MASK;
11992         switch (fb->modifier[0]) {
11993         case DRM_FORMAT_MOD_NONE:
11994                 break;
11995         case I915_FORMAT_MOD_X_TILED:
11996                 ctl |= PLANE_CTL_TILED_X;
11997                 break;
11998         case I915_FORMAT_MOD_Y_TILED:
11999                 ctl |= PLANE_CTL_TILED_Y;
12000                 break;
12001         case I915_FORMAT_MOD_Yf_TILED:
12002                 ctl |= PLANE_CTL_TILED_YF;
12003                 break;
12004         default:
12005                 MISSING_CASE(fb->modifier[0]);
12006         }
12007
12008         /*
12009          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12010          * PLANE_SURF updates, the update is then guaranteed to be atomic.
12011          */
12012         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12013         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12014
12015         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12016         POSTING_READ(PLANE_SURF(pipe, 0));
12017 }
12018
12019 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12020                              struct intel_flip_work *work)
12021 {
12022         struct drm_device *dev = intel_crtc->base.dev;
12023         struct drm_i915_private *dev_priv = to_i915(dev);
12024         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12025         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12026         u32 dspcntr;
12027
12028         dspcntr = I915_READ(reg);
12029
12030         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12031                 dspcntr |= DISPPLANE_TILED;
12032         else
12033                 dspcntr &= ~DISPPLANE_TILED;
12034
12035         I915_WRITE(reg, dspcntr);
12036
12037         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12038         POSTING_READ(DSPSURF(intel_crtc->plane));
12039 }
12040
12041 static void intel_mmio_flip_work_func(struct work_struct *w)
12042 {
12043         struct intel_flip_work *work =
12044                 container_of(w, struct intel_flip_work, mmio_work);
12045         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12046         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12047         struct intel_framebuffer *intel_fb =
12048                 to_intel_framebuffer(crtc->base.primary->fb);
12049         struct drm_i915_gem_object *obj = intel_fb->obj;
12050         struct reservation_object *resv;
12051
12052         if (work->flip_queued_req)
12053                 WARN_ON(i915_wait_request(work->flip_queued_req,
12054                                           0, NULL, NO_WAITBOOST));
12055
12056         /* For framebuffer backed by dmabuf, wait for fence */
12057         resv = i915_gem_object_get_dmabuf_resv(obj);
12058         if (resv)
12059                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12060                                                             MAX_SCHEDULE_TIMEOUT) < 0);
12061
12062         intel_pipe_update_start(crtc);
12063
12064         if (INTEL_GEN(dev_priv) >= 9)
12065                 skl_do_mmio_flip(crtc, work->rotation, work);
12066         else
12067                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12068                 ilk_do_mmio_flip(crtc, work);
12069
12070         intel_pipe_update_end(crtc, work);
12071 }
12072
12073 static int intel_default_queue_flip(struct drm_device *dev,
12074                                     struct drm_crtc *crtc,
12075                                     struct drm_framebuffer *fb,
12076                                     struct drm_i915_gem_object *obj,
12077                                     struct drm_i915_gem_request *req,
12078                                     uint32_t flags)
12079 {
12080         return -ENODEV;
12081 }
12082
12083 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12084                                       struct intel_crtc *intel_crtc,
12085                                       struct intel_flip_work *work)
12086 {
12087         u32 addr, vblank;
12088
12089         if (!atomic_read(&work->pending))
12090                 return false;
12091
12092         smp_rmb();
12093
12094         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12095         if (work->flip_ready_vblank == 0) {
12096                 if (work->flip_queued_req &&
12097                     !i915_gem_request_completed(work->flip_queued_req))
12098                         return false;
12099
12100                 work->flip_ready_vblank = vblank;
12101         }
12102
12103         if (vblank - work->flip_ready_vblank < 3)
12104                 return false;
12105
12106         /* Potential stall - if we see that the flip has happened,
12107          * assume a missed interrupt. */
12108         if (INTEL_GEN(dev_priv) >= 4)
12109                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12110         else
12111                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12112
12113         /* There is a potential issue here with a false positive after a flip
12114          * to the same address. We could address this by checking for a
12115          * non-incrementing frame counter.
12116          */
12117         return addr == work->gtt_offset;
12118 }
12119
12120 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12121 {
12122         struct drm_device *dev = &dev_priv->drm;
12123         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12125         struct intel_flip_work *work;
12126
12127         WARN_ON(!in_interrupt());
12128
12129         if (crtc == NULL)
12130                 return;
12131
12132         spin_lock(&dev->event_lock);
12133         work = intel_crtc->flip_work;
12134
12135         if (work != NULL && !is_mmio_work(work) &&
12136             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12137                 WARN_ONCE(1,
12138                           "Kicking stuck page flip: queued at %d, now %d\n",
12139                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12140                 page_flip_completed(intel_crtc);
12141                 work = NULL;
12142         }
12143
12144         if (work != NULL && !is_mmio_work(work) &&
12145             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12146                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12147         spin_unlock(&dev->event_lock);
12148 }
12149
12150 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12151                                 struct drm_framebuffer *fb,
12152                                 struct drm_pending_vblank_event *event,
12153                                 uint32_t page_flip_flags)
12154 {
12155         struct drm_device *dev = crtc->dev;
12156         struct drm_i915_private *dev_priv = to_i915(dev);
12157         struct drm_framebuffer *old_fb = crtc->primary->fb;
12158         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12160         struct drm_plane *primary = crtc->primary;
12161         enum pipe pipe = intel_crtc->pipe;
12162         struct intel_flip_work *work;
12163         struct intel_engine_cs *engine;
12164         bool mmio_flip;
12165         struct drm_i915_gem_request *request;
12166         struct i915_vma *vma;
12167         int ret;
12168
12169         /*
12170          * drm_mode_page_flip_ioctl() should already catch this, but double
12171          * check to be safe.  In the future we may enable pageflipping from
12172          * a disabled primary plane.
12173          */
12174         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12175                 return -EBUSY;
12176
12177         /* Can't change pixel format via MI display flips. */
12178         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12179                 return -EINVAL;
12180
12181         /*
12182          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12183          * Note that pitch changes could also affect these register.
12184          */
12185         if (INTEL_INFO(dev)->gen > 3 &&
12186             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12187              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12188                 return -EINVAL;
12189
12190         if (i915_terminally_wedged(&dev_priv->gpu_error))
12191                 goto out_hang;
12192
12193         work = kzalloc(sizeof(*work), GFP_KERNEL);
12194         if (work == NULL)
12195                 return -ENOMEM;
12196
12197         work->event = event;
12198         work->crtc = crtc;
12199         work->old_fb = old_fb;
12200         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12201
12202         ret = drm_crtc_vblank_get(crtc);
12203         if (ret)
12204                 goto free_work;
12205
12206         /* We borrow the event spin lock for protecting flip_work */
12207         spin_lock_irq(&dev->event_lock);
12208         if (intel_crtc->flip_work) {
12209                 /* Before declaring the flip queue wedged, check if
12210                  * the hardware completed the operation behind our backs.
12211                  */
12212                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12213                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12214                         page_flip_completed(intel_crtc);
12215                 } else {
12216                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12217                         spin_unlock_irq(&dev->event_lock);
12218
12219                         drm_crtc_vblank_put(crtc);
12220                         kfree(work);
12221                         return -EBUSY;
12222                 }
12223         }
12224         intel_crtc->flip_work = work;
12225         spin_unlock_irq(&dev->event_lock);
12226
12227         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12228                 flush_workqueue(dev_priv->wq);
12229
12230         /* Reference the objects for the scheduled work. */
12231         drm_framebuffer_reference(work->old_fb);
12232
12233         crtc->primary->fb = fb;
12234         update_state_fb(crtc->primary);
12235
12236         work->pending_flip_obj = i915_gem_object_get(obj);
12237
12238         ret = i915_mutex_lock_interruptible(dev);
12239         if (ret)
12240                 goto cleanup;
12241
12242         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12243         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12244                 ret = -EIO;
12245                 goto cleanup;
12246         }
12247
12248         atomic_inc(&intel_crtc->unpin_work_count);
12249
12250         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12251                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12252
12253         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12254                 engine = &dev_priv->engine[BCS];
12255                 if (fb->modifier[0] != old_fb->modifier[0])
12256                         /* vlv: DISPLAY_FLIP fails to change tiling */
12257                         engine = NULL;
12258         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12259                 engine = &dev_priv->engine[BCS];
12260         } else if (INTEL_INFO(dev)->gen >= 7) {
12261                 engine = i915_gem_active_get_engine(&obj->last_write,
12262                                                     &obj->base.dev->struct_mutex);
12263                 if (engine == NULL || engine->id != RCS)
12264                         engine = &dev_priv->engine[BCS];
12265         } else {
12266                 engine = &dev_priv->engine[RCS];
12267         }
12268
12269         mmio_flip = use_mmio_flip(engine, obj);
12270
12271         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12272         if (IS_ERR(vma)) {
12273                 ret = PTR_ERR(vma);
12274                 goto cleanup_pending;
12275         }
12276
12277         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12278         work->gtt_offset += intel_crtc->dspaddr_offset;
12279         work->rotation = crtc->primary->state->rotation;
12280
12281         /*
12282          * There's the potential that the next frame will not be compatible with
12283          * FBC, so we want to call pre_update() before the actual page flip.
12284          * The problem is that pre_update() caches some information about the fb
12285          * object, so we want to do this only after the object is pinned. Let's
12286          * be on the safe side and do this immediately before scheduling the
12287          * flip.
12288          */
12289         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12290                              to_intel_plane_state(primary->state));
12291
12292         if (mmio_flip) {
12293                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12294
12295                 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12296                                                             &obj->base.dev->struct_mutex);
12297                 schedule_work(&work->mmio_work);
12298         } else {
12299                 request = i915_gem_request_alloc(engine, engine->last_context);
12300                 if (IS_ERR(request)) {
12301                         ret = PTR_ERR(request);
12302                         goto cleanup_unpin;
12303                 }
12304
12305                 ret = i915_gem_request_await_object(request, obj, false);
12306                 if (ret)
12307                         goto cleanup_request;
12308
12309                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12310                                                    page_flip_flags);
12311                 if (ret)
12312                         goto cleanup_request;
12313
12314                 intel_mark_page_flip_active(intel_crtc, work);
12315
12316                 work->flip_queued_req = i915_gem_request_get(request);
12317                 i915_add_request_no_flush(request);
12318         }
12319
12320         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12321                           to_intel_plane(primary)->frontbuffer_bit);
12322         mutex_unlock(&dev->struct_mutex);
12323
12324         intel_frontbuffer_flip_prepare(to_i915(dev),
12325                                        to_intel_plane(primary)->frontbuffer_bit);
12326
12327         trace_i915_flip_request(intel_crtc->plane, obj);
12328
12329         return 0;
12330
12331 cleanup_request:
12332         i915_add_request_no_flush(request);
12333 cleanup_unpin:
12334         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12335 cleanup_pending:
12336         atomic_dec(&intel_crtc->unpin_work_count);
12337         mutex_unlock(&dev->struct_mutex);
12338 cleanup:
12339         crtc->primary->fb = old_fb;
12340         update_state_fb(crtc->primary);
12341
12342         i915_gem_object_put_unlocked(obj);
12343         drm_framebuffer_unreference(work->old_fb);
12344
12345         spin_lock_irq(&dev->event_lock);
12346         intel_crtc->flip_work = NULL;
12347         spin_unlock_irq(&dev->event_lock);
12348
12349         drm_crtc_vblank_put(crtc);
12350 free_work:
12351         kfree(work);
12352
12353         if (ret == -EIO) {
12354                 struct drm_atomic_state *state;
12355                 struct drm_plane_state *plane_state;
12356
12357 out_hang:
12358                 state = drm_atomic_state_alloc(dev);
12359                 if (!state)
12360                         return -ENOMEM;
12361                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12362
12363 retry:
12364                 plane_state = drm_atomic_get_plane_state(state, primary);
12365                 ret = PTR_ERR_OR_ZERO(plane_state);
12366                 if (!ret) {
12367                         drm_atomic_set_fb_for_plane(plane_state, fb);
12368
12369                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12370                         if (!ret)
12371                                 ret = drm_atomic_commit(state);
12372                 }
12373
12374                 if (ret == -EDEADLK) {
12375                         drm_modeset_backoff(state->acquire_ctx);
12376                         drm_atomic_state_clear(state);
12377                         goto retry;
12378                 }
12379
12380                 drm_atomic_state_put(state);
12381
12382                 if (ret == 0 && event) {
12383                         spin_lock_irq(&dev->event_lock);
12384                         drm_crtc_send_vblank_event(crtc, event);
12385                         spin_unlock_irq(&dev->event_lock);
12386                 }
12387         }
12388         return ret;
12389 }
12390
12391
12392 /**
12393  * intel_wm_need_update - Check whether watermarks need updating
12394  * @plane: drm plane
12395  * @state: new plane state
12396  *
12397  * Check current plane state versus the new one to determine whether
12398  * watermarks need to be recalculated.
12399  *
12400  * Returns true or false.
12401  */
12402 static bool intel_wm_need_update(struct drm_plane *plane,
12403                                  struct drm_plane_state *state)
12404 {
12405         struct intel_plane_state *new = to_intel_plane_state(state);
12406         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12407
12408         /* Update watermarks on tiling or size changes. */
12409         if (new->base.visible != cur->base.visible)
12410                 return true;
12411
12412         if (!cur->base.fb || !new->base.fb)
12413                 return false;
12414
12415         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12416             cur->base.rotation != new->base.rotation ||
12417             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12418             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12419             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12420             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12421                 return true;
12422
12423         return false;
12424 }
12425
12426 static bool needs_scaling(struct intel_plane_state *state)
12427 {
12428         int src_w = drm_rect_width(&state->base.src) >> 16;
12429         int src_h = drm_rect_height(&state->base.src) >> 16;
12430         int dst_w = drm_rect_width(&state->base.dst);
12431         int dst_h = drm_rect_height(&state->base.dst);
12432
12433         return (src_w != dst_w || src_h != dst_h);
12434 }
12435
12436 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12437                                     struct drm_plane_state *plane_state)
12438 {
12439         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12440         struct drm_crtc *crtc = crtc_state->crtc;
12441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12442         struct drm_plane *plane = plane_state->plane;
12443         struct drm_device *dev = crtc->dev;
12444         struct drm_i915_private *dev_priv = to_i915(dev);
12445         struct intel_plane_state *old_plane_state =
12446                 to_intel_plane_state(plane->state);
12447         bool mode_changed = needs_modeset(crtc_state);
12448         bool was_crtc_enabled = crtc->state->active;
12449         bool is_crtc_enabled = crtc_state->active;
12450         bool turn_off, turn_on, visible, was_visible;
12451         struct drm_framebuffer *fb = plane_state->fb;
12452         int ret;
12453
12454         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12455                 ret = skl_update_scaler_plane(
12456                         to_intel_crtc_state(crtc_state),
12457                         to_intel_plane_state(plane_state));
12458                 if (ret)
12459                         return ret;
12460         }
12461
12462         was_visible = old_plane_state->base.visible;
12463         visible = to_intel_plane_state(plane_state)->base.visible;
12464
12465         if (!was_crtc_enabled && WARN_ON(was_visible))
12466                 was_visible = false;
12467
12468         /*
12469          * Visibility is calculated as if the crtc was on, but
12470          * after scaler setup everything depends on it being off
12471          * when the crtc isn't active.
12472          *
12473          * FIXME this is wrong for watermarks. Watermarks should also
12474          * be computed as if the pipe would be active. Perhaps move
12475          * per-plane wm computation to the .check_plane() hook, and
12476          * only combine the results from all planes in the current place?
12477          */
12478         if (!is_crtc_enabled)
12479                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12480
12481         if (!was_visible && !visible)
12482                 return 0;
12483
12484         if (fb != old_plane_state->base.fb)
12485                 pipe_config->fb_changed = true;
12486
12487         turn_off = was_visible && (!visible || mode_changed);
12488         turn_on = visible && (!was_visible || mode_changed);
12489
12490         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12491                          intel_crtc->base.base.id,
12492                          intel_crtc->base.name,
12493                          plane->base.id, plane->name,
12494                          fb ? fb->base.id : -1);
12495
12496         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12497                          plane->base.id, plane->name,
12498                          was_visible, visible,
12499                          turn_off, turn_on, mode_changed);
12500
12501         if (turn_on) {
12502                 pipe_config->update_wm_pre = true;
12503
12504                 /* must disable cxsr around plane enable/disable */
12505                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12506                         pipe_config->disable_cxsr = true;
12507         } else if (turn_off) {
12508                 pipe_config->update_wm_post = true;
12509
12510                 /* must disable cxsr around plane enable/disable */
12511                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12512                         pipe_config->disable_cxsr = true;
12513         } else if (intel_wm_need_update(plane, plane_state)) {
12514                 /* FIXME bollocks */
12515                 pipe_config->update_wm_pre = true;
12516                 pipe_config->update_wm_post = true;
12517         }
12518
12519         /* Pre-gen9 platforms need two-step watermark updates */
12520         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12521             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12522                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12523
12524         if (visible || was_visible)
12525                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12526
12527         /*
12528          * WaCxSRDisabledForSpriteScaling:ivb
12529          *
12530          * cstate->update_wm was already set above, so this flag will
12531          * take effect when we commit and program watermarks.
12532          */
12533         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12534             needs_scaling(to_intel_plane_state(plane_state)) &&
12535             !needs_scaling(old_plane_state))
12536                 pipe_config->disable_lp_wm = true;
12537
12538         return 0;
12539 }
12540
12541 static bool encoders_cloneable(const struct intel_encoder *a,
12542                                const struct intel_encoder *b)
12543 {
12544         /* masks could be asymmetric, so check both ways */
12545         return a == b || (a->cloneable & (1 << b->type) &&
12546                           b->cloneable & (1 << a->type));
12547 }
12548
12549 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12550                                          struct intel_crtc *crtc,
12551                                          struct intel_encoder *encoder)
12552 {
12553         struct intel_encoder *source_encoder;
12554         struct drm_connector *connector;
12555         struct drm_connector_state *connector_state;
12556         int i;
12557
12558         for_each_connector_in_state(state, connector, connector_state, i) {
12559                 if (connector_state->crtc != &crtc->base)
12560                         continue;
12561
12562                 source_encoder =
12563                         to_intel_encoder(connector_state->best_encoder);
12564                 if (!encoders_cloneable(encoder, source_encoder))
12565                         return false;
12566         }
12567
12568         return true;
12569 }
12570
12571 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12572                                    struct drm_crtc_state *crtc_state)
12573 {
12574         struct drm_device *dev = crtc->dev;
12575         struct drm_i915_private *dev_priv = to_i915(dev);
12576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12577         struct intel_crtc_state *pipe_config =
12578                 to_intel_crtc_state(crtc_state);
12579         struct drm_atomic_state *state = crtc_state->state;
12580         int ret;
12581         bool mode_changed = needs_modeset(crtc_state);
12582
12583         if (mode_changed && !crtc_state->active)
12584                 pipe_config->update_wm_post = true;
12585
12586         if (mode_changed && crtc_state->enable &&
12587             dev_priv->display.crtc_compute_clock &&
12588             !WARN_ON(pipe_config->shared_dpll)) {
12589                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12590                                                            pipe_config);
12591                 if (ret)
12592                         return ret;
12593         }
12594
12595         if (crtc_state->color_mgmt_changed) {
12596                 ret = intel_color_check(crtc, crtc_state);
12597                 if (ret)
12598                         return ret;
12599
12600                 /*
12601                  * Changing color management on Intel hardware is
12602                  * handled as part of planes update.
12603                  */
12604                 crtc_state->planes_changed = true;
12605         }
12606
12607         ret = 0;
12608         if (dev_priv->display.compute_pipe_wm) {
12609                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12610                 if (ret) {
12611                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12612                         return ret;
12613                 }
12614         }
12615
12616         if (dev_priv->display.compute_intermediate_wm &&
12617             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12618                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12619                         return 0;
12620
12621                 /*
12622                  * Calculate 'intermediate' watermarks that satisfy both the
12623                  * old state and the new state.  We can program these
12624                  * immediately.
12625                  */
12626                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12627                                                                 intel_crtc,
12628                                                                 pipe_config);
12629                 if (ret) {
12630                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12631                         return ret;
12632                 }
12633         } else if (dev_priv->display.compute_intermediate_wm) {
12634                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12635                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12636         }
12637
12638         if (INTEL_INFO(dev)->gen >= 9) {
12639                 if (mode_changed)
12640                         ret = skl_update_scaler_crtc(pipe_config);
12641
12642                 if (!ret)
12643                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12644                                                          pipe_config);
12645         }
12646
12647         return ret;
12648 }
12649
12650 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12651         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12652         .atomic_begin = intel_begin_crtc_commit,
12653         .atomic_flush = intel_finish_crtc_commit,
12654         .atomic_check = intel_crtc_atomic_check,
12655 };
12656
12657 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12658 {
12659         struct intel_connector *connector;
12660
12661         for_each_intel_connector(dev, connector) {
12662                 if (connector->base.state->crtc)
12663                         drm_connector_unreference(&connector->base);
12664
12665                 if (connector->base.encoder) {
12666                         connector->base.state->best_encoder =
12667                                 connector->base.encoder;
12668                         connector->base.state->crtc =
12669                                 connector->base.encoder->crtc;
12670
12671                         drm_connector_reference(&connector->base);
12672                 } else {
12673                         connector->base.state->best_encoder = NULL;
12674                         connector->base.state->crtc = NULL;
12675                 }
12676         }
12677 }
12678
12679 static void
12680 connected_sink_compute_bpp(struct intel_connector *connector,
12681                            struct intel_crtc_state *pipe_config)
12682 {
12683         const struct drm_display_info *info = &connector->base.display_info;
12684         int bpp = pipe_config->pipe_bpp;
12685
12686         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12687                       connector->base.base.id,
12688                       connector->base.name);
12689
12690         /* Don't use an invalid EDID bpc value */
12691         if (info->bpc != 0 && info->bpc * 3 < bpp) {
12692                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12693                               bpp, info->bpc * 3);
12694                 pipe_config->pipe_bpp = info->bpc * 3;
12695         }
12696
12697         /* Clamp bpp to 8 on screens without EDID 1.4 */
12698         if (info->bpc == 0 && bpp > 24) {
12699                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12700                               bpp);
12701                 pipe_config->pipe_bpp = 24;
12702         }
12703 }
12704
12705 static int
12706 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12707                           struct intel_crtc_state *pipe_config)
12708 {
12709         struct drm_device *dev = crtc->base.dev;
12710         struct drm_atomic_state *state;
12711         struct drm_connector *connector;
12712         struct drm_connector_state *connector_state;
12713         int bpp, i;
12714
12715         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12716                 bpp = 10*3;
12717         else if (INTEL_INFO(dev)->gen >= 5)
12718                 bpp = 12*3;
12719         else
12720                 bpp = 8*3;
12721
12722
12723         pipe_config->pipe_bpp = bpp;
12724
12725         state = pipe_config->base.state;
12726
12727         /* Clamp display bpp to EDID value */
12728         for_each_connector_in_state(state, connector, connector_state, i) {
12729                 if (connector_state->crtc != &crtc->base)
12730                         continue;
12731
12732                 connected_sink_compute_bpp(to_intel_connector(connector),
12733                                            pipe_config);
12734         }
12735
12736         return bpp;
12737 }
12738
12739 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12740 {
12741         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12742                         "type: 0x%x flags: 0x%x\n",
12743                 mode->crtc_clock,
12744                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12745                 mode->crtc_hsync_end, mode->crtc_htotal,
12746                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12747                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12748 }
12749
12750 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12751                                    struct intel_crtc_state *pipe_config,
12752                                    const char *context)
12753 {
12754         struct drm_device *dev = crtc->base.dev;
12755         struct drm_plane *plane;
12756         struct intel_plane *intel_plane;
12757         struct intel_plane_state *state;
12758         struct drm_framebuffer *fb;
12759
12760         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12761                       crtc->base.base.id, crtc->base.name,
12762                       context, pipe_config, pipe_name(crtc->pipe));
12763
12764         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12765         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12766                       pipe_config->pipe_bpp, pipe_config->dither);
12767         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12768                       pipe_config->has_pch_encoder,
12769                       pipe_config->fdi_lanes,
12770                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12771                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12772                       pipe_config->fdi_m_n.tu);
12773         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12774                       intel_crtc_has_dp_encoder(pipe_config),
12775                       pipe_config->lane_count,
12776                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12777                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12778                       pipe_config->dp_m_n.tu);
12779
12780         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12781                       intel_crtc_has_dp_encoder(pipe_config),
12782                       pipe_config->lane_count,
12783                       pipe_config->dp_m2_n2.gmch_m,
12784                       pipe_config->dp_m2_n2.gmch_n,
12785                       pipe_config->dp_m2_n2.link_m,
12786                       pipe_config->dp_m2_n2.link_n,
12787                       pipe_config->dp_m2_n2.tu);
12788
12789         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12790                       pipe_config->has_audio,
12791                       pipe_config->has_infoframe);
12792
12793         DRM_DEBUG_KMS("requested mode:\n");
12794         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12795         DRM_DEBUG_KMS("adjusted mode:\n");
12796         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12797         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12798         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12799         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12800                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12801         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12802                       crtc->num_scalers,
12803                       pipe_config->scaler_state.scaler_users,
12804                       pipe_config->scaler_state.scaler_id);
12805         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12806                       pipe_config->gmch_pfit.control,
12807                       pipe_config->gmch_pfit.pgm_ratios,
12808                       pipe_config->gmch_pfit.lvds_border_bits);
12809         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12810                       pipe_config->pch_pfit.pos,
12811                       pipe_config->pch_pfit.size,
12812                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12813         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12814         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12815
12816         if (IS_BROXTON(dev)) {
12817                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12818                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12819                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12820                               pipe_config->dpll_hw_state.ebb0,
12821                               pipe_config->dpll_hw_state.ebb4,
12822                               pipe_config->dpll_hw_state.pll0,
12823                               pipe_config->dpll_hw_state.pll1,
12824                               pipe_config->dpll_hw_state.pll2,
12825                               pipe_config->dpll_hw_state.pll3,
12826                               pipe_config->dpll_hw_state.pll6,
12827                               pipe_config->dpll_hw_state.pll8,
12828                               pipe_config->dpll_hw_state.pll9,
12829                               pipe_config->dpll_hw_state.pll10,
12830                               pipe_config->dpll_hw_state.pcsdw12);
12831         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12832                 DRM_DEBUG_KMS("dpll_hw_state: "
12833                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12834                               pipe_config->dpll_hw_state.ctrl1,
12835                               pipe_config->dpll_hw_state.cfgcr1,
12836                               pipe_config->dpll_hw_state.cfgcr2);
12837         } else if (HAS_DDI(dev)) {
12838                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12839                               pipe_config->dpll_hw_state.wrpll,
12840                               pipe_config->dpll_hw_state.spll);
12841         } else {
12842                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12843                               "fp0: 0x%x, fp1: 0x%x\n",
12844                               pipe_config->dpll_hw_state.dpll,
12845                               pipe_config->dpll_hw_state.dpll_md,
12846                               pipe_config->dpll_hw_state.fp0,
12847                               pipe_config->dpll_hw_state.fp1);
12848         }
12849
12850         DRM_DEBUG_KMS("planes on this crtc\n");
12851         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12852                 char *format_name;
12853                 intel_plane = to_intel_plane(plane);
12854                 if (intel_plane->pipe != crtc->pipe)
12855                         continue;
12856
12857                 state = to_intel_plane_state(plane->state);
12858                 fb = state->base.fb;
12859                 if (!fb) {
12860                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12861                                       plane->base.id, plane->name, state->scaler_id);
12862                         continue;
12863                 }
12864
12865                 format_name = drm_get_format_name(fb->pixel_format);
12866
12867                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12868                               plane->base.id, plane->name);
12869                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12870                               fb->base.id, fb->width, fb->height, format_name);
12871                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12872                               state->scaler_id,
12873                               state->base.src.x1 >> 16,
12874                               state->base.src.y1 >> 16,
12875                               drm_rect_width(&state->base.src) >> 16,
12876                               drm_rect_height(&state->base.src) >> 16,
12877                               state->base.dst.x1, state->base.dst.y1,
12878                               drm_rect_width(&state->base.dst),
12879                               drm_rect_height(&state->base.dst));
12880
12881                 kfree(format_name);
12882         }
12883 }
12884
12885 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12886 {
12887         struct drm_device *dev = state->dev;
12888         struct drm_connector *connector;
12889         unsigned int used_ports = 0;
12890         unsigned int used_mst_ports = 0;
12891
12892         /*
12893          * Walk the connector list instead of the encoder
12894          * list to detect the problem on ddi platforms
12895          * where there's just one encoder per digital port.
12896          */
12897         drm_for_each_connector(connector, dev) {
12898                 struct drm_connector_state *connector_state;
12899                 struct intel_encoder *encoder;
12900
12901                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12902                 if (!connector_state)
12903                         connector_state = connector->state;
12904
12905                 if (!connector_state->best_encoder)
12906                         continue;
12907
12908                 encoder = to_intel_encoder(connector_state->best_encoder);
12909
12910                 WARN_ON(!connector_state->crtc);
12911
12912                 switch (encoder->type) {
12913                         unsigned int port_mask;
12914                 case INTEL_OUTPUT_UNKNOWN:
12915                         if (WARN_ON(!HAS_DDI(dev)))
12916                                 break;
12917                 case INTEL_OUTPUT_DP:
12918                 case INTEL_OUTPUT_HDMI:
12919                 case INTEL_OUTPUT_EDP:
12920                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12921
12922                         /* the same port mustn't appear more than once */
12923                         if (used_ports & port_mask)
12924                                 return false;
12925
12926                         used_ports |= port_mask;
12927                         break;
12928                 case INTEL_OUTPUT_DP_MST:
12929                         used_mst_ports |=
12930                                 1 << enc_to_mst(&encoder->base)->primary->port;
12931                         break;
12932                 default:
12933                         break;
12934                 }
12935         }
12936
12937         /* can't mix MST and SST/HDMI on the same port */
12938         if (used_ports & used_mst_ports)
12939                 return false;
12940
12941         return true;
12942 }
12943
12944 static void
12945 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12946 {
12947         struct drm_crtc_state tmp_state;
12948         struct intel_crtc_scaler_state scaler_state;
12949         struct intel_dpll_hw_state dpll_hw_state;
12950         struct intel_shared_dpll *shared_dpll;
12951         bool force_thru;
12952
12953         /* FIXME: before the switch to atomic started, a new pipe_config was
12954          * kzalloc'd. Code that depends on any field being zero should be
12955          * fixed, so that the crtc_state can be safely duplicated. For now,
12956          * only fields that are know to not cause problems are preserved. */
12957
12958         tmp_state = crtc_state->base;
12959         scaler_state = crtc_state->scaler_state;
12960         shared_dpll = crtc_state->shared_dpll;
12961         dpll_hw_state = crtc_state->dpll_hw_state;
12962         force_thru = crtc_state->pch_pfit.force_thru;
12963
12964         memset(crtc_state, 0, sizeof *crtc_state);
12965
12966         crtc_state->base = tmp_state;
12967         crtc_state->scaler_state = scaler_state;
12968         crtc_state->shared_dpll = shared_dpll;
12969         crtc_state->dpll_hw_state = dpll_hw_state;
12970         crtc_state->pch_pfit.force_thru = force_thru;
12971 }
12972
12973 static int
12974 intel_modeset_pipe_config(struct drm_crtc *crtc,
12975                           struct intel_crtc_state *pipe_config)
12976 {
12977         struct drm_atomic_state *state = pipe_config->base.state;
12978         struct intel_encoder *encoder;
12979         struct drm_connector *connector;
12980         struct drm_connector_state *connector_state;
12981         int base_bpp, ret = -EINVAL;
12982         int i;
12983         bool retry = true;
12984
12985         clear_intel_crtc_state(pipe_config);
12986
12987         pipe_config->cpu_transcoder =
12988                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12989
12990         /*
12991          * Sanitize sync polarity flags based on requested ones. If neither
12992          * positive or negative polarity is requested, treat this as meaning
12993          * negative polarity.
12994          */
12995         if (!(pipe_config->base.adjusted_mode.flags &
12996               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12997                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12998
12999         if (!(pipe_config->base.adjusted_mode.flags &
13000               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13001                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13002
13003         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13004                                              pipe_config);
13005         if (base_bpp < 0)
13006                 goto fail;
13007
13008         /*
13009          * Determine the real pipe dimensions. Note that stereo modes can
13010          * increase the actual pipe size due to the frame doubling and
13011          * insertion of additional space for blanks between the frame. This
13012          * is stored in the crtc timings. We use the requested mode to do this
13013          * computation to clearly distinguish it from the adjusted mode, which
13014          * can be changed by the connectors in the below retry loop.
13015          */
13016         drm_crtc_get_hv_timing(&pipe_config->base.mode,
13017                                &pipe_config->pipe_src_w,
13018                                &pipe_config->pipe_src_h);
13019
13020         for_each_connector_in_state(state, connector, connector_state, i) {
13021                 if (connector_state->crtc != crtc)
13022                         continue;
13023
13024                 encoder = to_intel_encoder(connector_state->best_encoder);
13025
13026                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13027                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13028                         goto fail;
13029                 }
13030
13031                 /*
13032                  * Determine output_types before calling the .compute_config()
13033                  * hooks so that the hooks can use this information safely.
13034                  */
13035                 pipe_config->output_types |= 1 << encoder->type;
13036         }
13037
13038 encoder_retry:
13039         /* Ensure the port clock defaults are reset when retrying. */
13040         pipe_config->port_clock = 0;
13041         pipe_config->pixel_multiplier = 1;
13042
13043         /* Fill in default crtc timings, allow encoders to overwrite them. */
13044         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13045                               CRTC_STEREO_DOUBLE);
13046
13047         /* Pass our mode to the connectors and the CRTC to give them a chance to
13048          * adjust it according to limitations or connector properties, and also
13049          * a chance to reject the mode entirely.
13050          */
13051         for_each_connector_in_state(state, connector, connector_state, i) {
13052                 if (connector_state->crtc != crtc)
13053                         continue;
13054
13055                 encoder = to_intel_encoder(connector_state->best_encoder);
13056
13057                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13058                         DRM_DEBUG_KMS("Encoder config failure\n");
13059                         goto fail;
13060                 }
13061         }
13062
13063         /* Set default port clock if not overwritten by the encoder. Needs to be
13064          * done afterwards in case the encoder adjusts the mode. */
13065         if (!pipe_config->port_clock)
13066                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13067                         * pipe_config->pixel_multiplier;
13068
13069         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13070         if (ret < 0) {
13071                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13072                 goto fail;
13073         }
13074
13075         if (ret == RETRY) {
13076                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13077                         ret = -EINVAL;
13078                         goto fail;
13079                 }
13080
13081                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13082                 retry = false;
13083                 goto encoder_retry;
13084         }
13085
13086         /* Dithering seems to not pass-through bits correctly when it should, so
13087          * only enable it on 6bpc panels. */
13088         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13089         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13090                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13091
13092 fail:
13093         return ret;
13094 }
13095
13096 static void
13097 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13098 {
13099         struct drm_crtc *crtc;
13100         struct drm_crtc_state *crtc_state;
13101         int i;
13102
13103         /* Double check state. */
13104         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13105                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13106
13107                 /* Update hwmode for vblank functions */
13108                 if (crtc->state->active)
13109                         crtc->hwmode = crtc->state->adjusted_mode;
13110                 else
13111                         crtc->hwmode.crtc_clock = 0;
13112
13113                 /*
13114                  * Update legacy state to satisfy fbc code. This can
13115                  * be removed when fbc uses the atomic state.
13116                  */
13117                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13118                         struct drm_plane_state *plane_state = crtc->primary->state;
13119
13120                         crtc->primary->fb = plane_state->fb;
13121                         crtc->x = plane_state->src_x >> 16;
13122                         crtc->y = plane_state->src_y >> 16;
13123                 }
13124         }
13125 }
13126
13127 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13128 {
13129         int diff;
13130
13131         if (clock1 == clock2)
13132                 return true;
13133
13134         if (!clock1 || !clock2)
13135                 return false;
13136
13137         diff = abs(clock1 - clock2);
13138
13139         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13140                 return true;
13141
13142         return false;
13143 }
13144
13145 static bool
13146 intel_compare_m_n(unsigned int m, unsigned int n,
13147                   unsigned int m2, unsigned int n2,
13148                   bool exact)
13149 {
13150         if (m == m2 && n == n2)
13151                 return true;
13152
13153         if (exact || !m || !n || !m2 || !n2)
13154                 return false;
13155
13156         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13157
13158         if (n > n2) {
13159                 while (n > n2) {
13160                         m2 <<= 1;
13161                         n2 <<= 1;
13162                 }
13163         } else if (n < n2) {
13164                 while (n < n2) {
13165                         m <<= 1;
13166                         n <<= 1;
13167                 }
13168         }
13169
13170         if (n != n2)
13171                 return false;
13172
13173         return intel_fuzzy_clock_check(m, m2);
13174 }
13175
13176 static bool
13177 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13178                        struct intel_link_m_n *m2_n2,
13179                        bool adjust)
13180 {
13181         if (m_n->tu == m2_n2->tu &&
13182             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13183                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13184             intel_compare_m_n(m_n->link_m, m_n->link_n,
13185                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13186                 if (adjust)
13187                         *m2_n2 = *m_n;
13188
13189                 return true;
13190         }
13191
13192         return false;
13193 }
13194
13195 static bool
13196 intel_pipe_config_compare(struct drm_device *dev,
13197                           struct intel_crtc_state *current_config,
13198                           struct intel_crtc_state *pipe_config,
13199                           bool adjust)
13200 {
13201         bool ret = true;
13202
13203 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13204         do { \
13205                 if (!adjust) \
13206                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13207                 else \
13208                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13209         } while (0)
13210
13211 #define PIPE_CONF_CHECK_X(name) \
13212         if (current_config->name != pipe_config->name) { \
13213                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13214                           "(expected 0x%08x, found 0x%08x)\n", \
13215                           current_config->name, \
13216                           pipe_config->name); \
13217                 ret = false; \
13218         }
13219
13220 #define PIPE_CONF_CHECK_I(name) \
13221         if (current_config->name != pipe_config->name) { \
13222                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13223                           "(expected %i, found %i)\n", \
13224                           current_config->name, \
13225                           pipe_config->name); \
13226                 ret = false; \
13227         }
13228
13229 #define PIPE_CONF_CHECK_P(name) \
13230         if (current_config->name != pipe_config->name) { \
13231                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13232                           "(expected %p, found %p)\n", \
13233                           current_config->name, \
13234                           pipe_config->name); \
13235                 ret = false; \
13236         }
13237
13238 #define PIPE_CONF_CHECK_M_N(name) \
13239         if (!intel_compare_link_m_n(&current_config->name, \
13240                                     &pipe_config->name,\
13241                                     adjust)) { \
13242                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13243                           "(expected tu %i gmch %i/%i link %i/%i, " \
13244                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13245                           current_config->name.tu, \
13246                           current_config->name.gmch_m, \
13247                           current_config->name.gmch_n, \
13248                           current_config->name.link_m, \
13249                           current_config->name.link_n, \
13250                           pipe_config->name.tu, \
13251                           pipe_config->name.gmch_m, \
13252                           pipe_config->name.gmch_n, \
13253                           pipe_config->name.link_m, \
13254                           pipe_config->name.link_n); \
13255                 ret = false; \
13256         }
13257
13258 /* This is required for BDW+ where there is only one set of registers for
13259  * switching between high and low RR.
13260  * This macro can be used whenever a comparison has to be made between one
13261  * hw state and multiple sw state variables.
13262  */
13263 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13264         if (!intel_compare_link_m_n(&current_config->name, \
13265                                     &pipe_config->name, adjust) && \
13266             !intel_compare_link_m_n(&current_config->alt_name, \
13267                                     &pipe_config->name, adjust)) { \
13268                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13269                           "(expected tu %i gmch %i/%i link %i/%i, " \
13270                           "or tu %i gmch %i/%i link %i/%i, " \
13271                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13272                           current_config->name.tu, \
13273                           current_config->name.gmch_m, \
13274                           current_config->name.gmch_n, \
13275                           current_config->name.link_m, \
13276                           current_config->name.link_n, \
13277                           current_config->alt_name.tu, \
13278                           current_config->alt_name.gmch_m, \
13279                           current_config->alt_name.gmch_n, \
13280                           current_config->alt_name.link_m, \
13281                           current_config->alt_name.link_n, \
13282                           pipe_config->name.tu, \
13283                           pipe_config->name.gmch_m, \
13284                           pipe_config->name.gmch_n, \
13285                           pipe_config->name.link_m, \
13286                           pipe_config->name.link_n); \
13287                 ret = false; \
13288         }
13289
13290 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13291         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13292                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13293                           "(expected %i, found %i)\n", \
13294                           current_config->name & (mask), \
13295                           pipe_config->name & (mask)); \
13296                 ret = false; \
13297         }
13298
13299 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13300         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13301                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13302                           "(expected %i, found %i)\n", \
13303                           current_config->name, \
13304                           pipe_config->name); \
13305                 ret = false; \
13306         }
13307
13308 #define PIPE_CONF_QUIRK(quirk)  \
13309         ((current_config->quirks | pipe_config->quirks) & (quirk))
13310
13311         PIPE_CONF_CHECK_I(cpu_transcoder);
13312
13313         PIPE_CONF_CHECK_I(has_pch_encoder);
13314         PIPE_CONF_CHECK_I(fdi_lanes);
13315         PIPE_CONF_CHECK_M_N(fdi_m_n);
13316
13317         PIPE_CONF_CHECK_I(lane_count);
13318         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13319
13320         if (INTEL_INFO(dev)->gen < 8) {
13321                 PIPE_CONF_CHECK_M_N(dp_m_n);
13322
13323                 if (current_config->has_drrs)
13324                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13325         } else
13326                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13327
13328         PIPE_CONF_CHECK_X(output_types);
13329
13330         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13331         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13332         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13333         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13334         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13335         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13336
13337         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13338         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13339         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13340         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13341         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13342         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13343
13344         PIPE_CONF_CHECK_I(pixel_multiplier);
13345         PIPE_CONF_CHECK_I(has_hdmi_sink);
13346         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13347             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13348                 PIPE_CONF_CHECK_I(limited_color_range);
13349         PIPE_CONF_CHECK_I(has_infoframe);
13350
13351         PIPE_CONF_CHECK_I(has_audio);
13352
13353         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13354                               DRM_MODE_FLAG_INTERLACE);
13355
13356         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13357                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13358                                       DRM_MODE_FLAG_PHSYNC);
13359                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13360                                       DRM_MODE_FLAG_NHSYNC);
13361                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13362                                       DRM_MODE_FLAG_PVSYNC);
13363                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13364                                       DRM_MODE_FLAG_NVSYNC);
13365         }
13366
13367         PIPE_CONF_CHECK_X(gmch_pfit.control);
13368         /* pfit ratios are autocomputed by the hw on gen4+ */
13369         if (INTEL_INFO(dev)->gen < 4)
13370                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13371         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13372
13373         if (!adjust) {
13374                 PIPE_CONF_CHECK_I(pipe_src_w);
13375                 PIPE_CONF_CHECK_I(pipe_src_h);
13376
13377                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13378                 if (current_config->pch_pfit.enabled) {
13379                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13380                         PIPE_CONF_CHECK_X(pch_pfit.size);
13381                 }
13382
13383                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13384         }
13385
13386         /* BDW+ don't expose a synchronous way to read the state */
13387         if (IS_HASWELL(dev))
13388                 PIPE_CONF_CHECK_I(ips_enabled);
13389
13390         PIPE_CONF_CHECK_I(double_wide);
13391
13392         PIPE_CONF_CHECK_P(shared_dpll);
13393         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13394         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13395         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13396         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13397         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13398         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13399         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13400         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13401         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13402
13403         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13404         PIPE_CONF_CHECK_X(dsi_pll.div);
13405
13406         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13407                 PIPE_CONF_CHECK_I(pipe_bpp);
13408
13409         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13410         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13411
13412 #undef PIPE_CONF_CHECK_X
13413 #undef PIPE_CONF_CHECK_I
13414 #undef PIPE_CONF_CHECK_P
13415 #undef PIPE_CONF_CHECK_FLAGS
13416 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13417 #undef PIPE_CONF_QUIRK
13418 #undef INTEL_ERR_OR_DBG_KMS
13419
13420         return ret;
13421 }
13422
13423 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13424                                            const struct intel_crtc_state *pipe_config)
13425 {
13426         if (pipe_config->has_pch_encoder) {
13427                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13428                                                             &pipe_config->fdi_m_n);
13429                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13430
13431                 /*
13432                  * FDI already provided one idea for the dotclock.
13433                  * Yell if the encoder disagrees.
13434                  */
13435                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13436                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13437                      fdi_dotclock, dotclock);
13438         }
13439 }
13440
13441 static void verify_wm_state(struct drm_crtc *crtc,
13442                             struct drm_crtc_state *new_state)
13443 {
13444         struct drm_device *dev = crtc->dev;
13445         struct drm_i915_private *dev_priv = to_i915(dev);
13446         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13447         struct skl_ddb_entry *hw_entry, *sw_entry;
13448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13449         const enum pipe pipe = intel_crtc->pipe;
13450         int plane;
13451
13452         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13453                 return;
13454
13455         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13456         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13457
13458         /* planes */
13459         for_each_plane(dev_priv, pipe, plane) {
13460                 hw_entry = &hw_ddb.plane[pipe][plane];
13461                 sw_entry = &sw_ddb->plane[pipe][plane];
13462
13463                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13464                         continue;
13465
13466                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13467                           "(expected (%u,%u), found (%u,%u))\n",
13468                           pipe_name(pipe), plane + 1,
13469                           sw_entry->start, sw_entry->end,
13470                           hw_entry->start, hw_entry->end);
13471         }
13472
13473         /*
13474          * cursor
13475          * If the cursor plane isn't active, we may not have updated it's ddb
13476          * allocation. In that case since the ddb allocation will be updated
13477          * once the plane becomes visible, we can skip this check
13478          */
13479         if (intel_crtc->cursor_addr) {
13480                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13481                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13482
13483                 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13484                         DRM_ERROR("mismatch in DDB state pipe %c cursor "
13485                                   "(expected (%u,%u), found (%u,%u))\n",
13486                                   pipe_name(pipe),
13487                                   sw_entry->start, sw_entry->end,
13488                                   hw_entry->start, hw_entry->end);
13489                 }
13490         }
13491 }
13492
13493 static void
13494 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13495 {
13496         struct drm_connector *connector;
13497
13498         drm_for_each_connector(connector, dev) {
13499                 struct drm_encoder *encoder = connector->encoder;
13500                 struct drm_connector_state *state = connector->state;
13501
13502                 if (state->crtc != crtc)
13503                         continue;
13504
13505                 intel_connector_verify_state(to_intel_connector(connector));
13506
13507                 I915_STATE_WARN(state->best_encoder != encoder,
13508                      "connector's atomic encoder doesn't match legacy encoder\n");
13509         }
13510 }
13511
13512 static void
13513 verify_encoder_state(struct drm_device *dev)
13514 {
13515         struct intel_encoder *encoder;
13516         struct intel_connector *connector;
13517
13518         for_each_intel_encoder(dev, encoder) {
13519                 bool enabled = false;
13520                 enum pipe pipe;
13521
13522                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13523                               encoder->base.base.id,
13524                               encoder->base.name);
13525
13526                 for_each_intel_connector(dev, connector) {
13527                         if (connector->base.state->best_encoder != &encoder->base)
13528                                 continue;
13529                         enabled = true;
13530
13531                         I915_STATE_WARN(connector->base.state->crtc !=
13532                                         encoder->base.crtc,
13533                              "connector's crtc doesn't match encoder crtc\n");
13534                 }
13535
13536                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13537                      "encoder's enabled state mismatch "
13538                      "(expected %i, found %i)\n",
13539                      !!encoder->base.crtc, enabled);
13540
13541                 if (!encoder->base.crtc) {
13542                         bool active;
13543
13544                         active = encoder->get_hw_state(encoder, &pipe);
13545                         I915_STATE_WARN(active,
13546                              "encoder detached but still enabled on pipe %c.\n",
13547                              pipe_name(pipe));
13548                 }
13549         }
13550 }
13551
13552 static void
13553 verify_crtc_state(struct drm_crtc *crtc,
13554                   struct drm_crtc_state *old_crtc_state,
13555                   struct drm_crtc_state *new_crtc_state)
13556 {
13557         struct drm_device *dev = crtc->dev;
13558         struct drm_i915_private *dev_priv = to_i915(dev);
13559         struct intel_encoder *encoder;
13560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13561         struct intel_crtc_state *pipe_config, *sw_config;
13562         struct drm_atomic_state *old_state;
13563         bool active;
13564
13565         old_state = old_crtc_state->state;
13566         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13567         pipe_config = to_intel_crtc_state(old_crtc_state);
13568         memset(pipe_config, 0, sizeof(*pipe_config));
13569         pipe_config->base.crtc = crtc;
13570         pipe_config->base.state = old_state;
13571
13572         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13573
13574         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13575
13576         /* hw state is inconsistent with the pipe quirk */
13577         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13578             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13579                 active = new_crtc_state->active;
13580
13581         I915_STATE_WARN(new_crtc_state->active != active,
13582              "crtc active state doesn't match with hw state "
13583              "(expected %i, found %i)\n", new_crtc_state->active, active);
13584
13585         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13586              "transitional active state does not match atomic hw state "
13587              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13588
13589         for_each_encoder_on_crtc(dev, crtc, encoder) {
13590                 enum pipe pipe;
13591
13592                 active = encoder->get_hw_state(encoder, &pipe);
13593                 I915_STATE_WARN(active != new_crtc_state->active,
13594                         "[ENCODER:%i] active %i with crtc active %i\n",
13595                         encoder->base.base.id, active, new_crtc_state->active);
13596
13597                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13598                                 "Encoder connected to wrong pipe %c\n",
13599                                 pipe_name(pipe));
13600
13601                 if (active) {
13602                         pipe_config->output_types |= 1 << encoder->type;
13603                         encoder->get_config(encoder, pipe_config);
13604                 }
13605         }
13606
13607         if (!new_crtc_state->active)
13608                 return;
13609
13610         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13611
13612         sw_config = to_intel_crtc_state(crtc->state);
13613         if (!intel_pipe_config_compare(dev, sw_config,
13614                                        pipe_config, false)) {
13615                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13616                 intel_dump_pipe_config(intel_crtc, pipe_config,
13617                                        "[hw state]");
13618                 intel_dump_pipe_config(intel_crtc, sw_config,
13619                                        "[sw state]");
13620         }
13621 }
13622
13623 static void
13624 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13625                          struct intel_shared_dpll *pll,
13626                          struct drm_crtc *crtc,
13627                          struct drm_crtc_state *new_state)
13628 {
13629         struct intel_dpll_hw_state dpll_hw_state;
13630         unsigned crtc_mask;
13631         bool active;
13632
13633         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13634
13635         DRM_DEBUG_KMS("%s\n", pll->name);
13636
13637         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13638
13639         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13640                 I915_STATE_WARN(!pll->on && pll->active_mask,
13641                      "pll in active use but not on in sw tracking\n");
13642                 I915_STATE_WARN(pll->on && !pll->active_mask,
13643                      "pll is on but not used by any active crtc\n");
13644                 I915_STATE_WARN(pll->on != active,
13645                      "pll on state mismatch (expected %i, found %i)\n",
13646                      pll->on, active);
13647         }
13648
13649         if (!crtc) {
13650                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13651                                 "more active pll users than references: %x vs %x\n",
13652                                 pll->active_mask, pll->config.crtc_mask);
13653
13654                 return;
13655         }
13656
13657         crtc_mask = 1 << drm_crtc_index(crtc);
13658
13659         if (new_state->active)
13660                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13661                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13662                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13663         else
13664                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13665                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13666                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13667
13668         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13669                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13670                         crtc_mask, pll->config.crtc_mask);
13671
13672         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13673                                           &dpll_hw_state,
13674                                           sizeof(dpll_hw_state)),
13675                         "pll hw state mismatch\n");
13676 }
13677
13678 static void
13679 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13680                          struct drm_crtc_state *old_crtc_state,
13681                          struct drm_crtc_state *new_crtc_state)
13682 {
13683         struct drm_i915_private *dev_priv = to_i915(dev);
13684         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13685         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13686
13687         if (new_state->shared_dpll)
13688                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13689
13690         if (old_state->shared_dpll &&
13691             old_state->shared_dpll != new_state->shared_dpll) {
13692                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13693                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13694
13695                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13696                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13697                                 pipe_name(drm_crtc_index(crtc)));
13698                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13699                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13700                                 pipe_name(drm_crtc_index(crtc)));
13701         }
13702 }
13703
13704 static void
13705 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13706                          struct drm_crtc_state *old_state,
13707                          struct drm_crtc_state *new_state)
13708 {
13709         if (!needs_modeset(new_state) &&
13710             !to_intel_crtc_state(new_state)->update_pipe)
13711                 return;
13712
13713         verify_wm_state(crtc, new_state);
13714         verify_connector_state(crtc->dev, crtc);
13715         verify_crtc_state(crtc, old_state, new_state);
13716         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13717 }
13718
13719 static void
13720 verify_disabled_dpll_state(struct drm_device *dev)
13721 {
13722         struct drm_i915_private *dev_priv = to_i915(dev);
13723         int i;
13724
13725         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13726                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13727 }
13728
13729 static void
13730 intel_modeset_verify_disabled(struct drm_device *dev)
13731 {
13732         verify_encoder_state(dev);
13733         verify_connector_state(dev, NULL);
13734         verify_disabled_dpll_state(dev);
13735 }
13736
13737 static void update_scanline_offset(struct intel_crtc *crtc)
13738 {
13739         struct drm_device *dev = crtc->base.dev;
13740
13741         /*
13742          * The scanline counter increments at the leading edge of hsync.
13743          *
13744          * On most platforms it starts counting from vtotal-1 on the
13745          * first active line. That means the scanline counter value is
13746          * always one less than what we would expect. Ie. just after
13747          * start of vblank, which also occurs at start of hsync (on the
13748          * last active line), the scanline counter will read vblank_start-1.
13749          *
13750          * On gen2 the scanline counter starts counting from 1 instead
13751          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13752          * to keep the value positive), instead of adding one.
13753          *
13754          * On HSW+ the behaviour of the scanline counter depends on the output
13755          * type. For DP ports it behaves like most other platforms, but on HDMI
13756          * there's an extra 1 line difference. So we need to add two instead of
13757          * one to the value.
13758          */
13759         if (IS_GEN2(dev)) {
13760                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13761                 int vtotal;
13762
13763                 vtotal = adjusted_mode->crtc_vtotal;
13764                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13765                         vtotal /= 2;
13766
13767                 crtc->scanline_offset = vtotal - 1;
13768         } else if (HAS_DDI(dev) &&
13769                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13770                 crtc->scanline_offset = 2;
13771         } else
13772                 crtc->scanline_offset = 1;
13773 }
13774
13775 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13776 {
13777         struct drm_device *dev = state->dev;
13778         struct drm_i915_private *dev_priv = to_i915(dev);
13779         struct intel_shared_dpll_config *shared_dpll = NULL;
13780         struct drm_crtc *crtc;
13781         struct drm_crtc_state *crtc_state;
13782         int i;
13783
13784         if (!dev_priv->display.crtc_compute_clock)
13785                 return;
13786
13787         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13788                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13789                 struct intel_shared_dpll *old_dpll =
13790                         to_intel_crtc_state(crtc->state)->shared_dpll;
13791
13792                 if (!needs_modeset(crtc_state))
13793                         continue;
13794
13795                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13796
13797                 if (!old_dpll)
13798                         continue;
13799
13800                 if (!shared_dpll)
13801                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13802
13803                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13804         }
13805 }
13806
13807 /*
13808  * This implements the workaround described in the "notes" section of the mode
13809  * set sequence documentation. When going from no pipes or single pipe to
13810  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13811  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13812  */
13813 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13814 {
13815         struct drm_crtc_state *crtc_state;
13816         struct intel_crtc *intel_crtc;
13817         struct drm_crtc *crtc;
13818         struct intel_crtc_state *first_crtc_state = NULL;
13819         struct intel_crtc_state *other_crtc_state = NULL;
13820         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13821         int i;
13822
13823         /* look at all crtc's that are going to be enabled in during modeset */
13824         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13825                 intel_crtc = to_intel_crtc(crtc);
13826
13827                 if (!crtc_state->active || !needs_modeset(crtc_state))
13828                         continue;
13829
13830                 if (first_crtc_state) {
13831                         other_crtc_state = to_intel_crtc_state(crtc_state);
13832                         break;
13833                 } else {
13834                         first_crtc_state = to_intel_crtc_state(crtc_state);
13835                         first_pipe = intel_crtc->pipe;
13836                 }
13837         }
13838
13839         /* No workaround needed? */
13840         if (!first_crtc_state)
13841                 return 0;
13842
13843         /* w/a possibly needed, check how many crtc's are already enabled. */
13844         for_each_intel_crtc(state->dev, intel_crtc) {
13845                 struct intel_crtc_state *pipe_config;
13846
13847                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13848                 if (IS_ERR(pipe_config))
13849                         return PTR_ERR(pipe_config);
13850
13851                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13852
13853                 if (!pipe_config->base.active ||
13854                     needs_modeset(&pipe_config->base))
13855                         continue;
13856
13857                 /* 2 or more enabled crtcs means no need for w/a */
13858                 if (enabled_pipe != INVALID_PIPE)
13859                         return 0;
13860
13861                 enabled_pipe = intel_crtc->pipe;
13862         }
13863
13864         if (enabled_pipe != INVALID_PIPE)
13865                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13866         else if (other_crtc_state)
13867                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13868
13869         return 0;
13870 }
13871
13872 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13873 {
13874         struct drm_crtc *crtc;
13875         struct drm_crtc_state *crtc_state;
13876         int ret = 0;
13877
13878         /* add all active pipes to the state */
13879         for_each_crtc(state->dev, crtc) {
13880                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13881                 if (IS_ERR(crtc_state))
13882                         return PTR_ERR(crtc_state);
13883
13884                 if (!crtc_state->active || needs_modeset(crtc_state))
13885                         continue;
13886
13887                 crtc_state->mode_changed = true;
13888
13889                 ret = drm_atomic_add_affected_connectors(state, crtc);
13890                 if (ret)
13891                         break;
13892
13893                 ret = drm_atomic_add_affected_planes(state, crtc);
13894                 if (ret)
13895                         break;
13896         }
13897
13898         return ret;
13899 }
13900
13901 static int intel_modeset_checks(struct drm_atomic_state *state)
13902 {
13903         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13904         struct drm_i915_private *dev_priv = to_i915(state->dev);
13905         struct drm_crtc *crtc;
13906         struct drm_crtc_state *crtc_state;
13907         int ret = 0, i;
13908
13909         if (!check_digital_port_conflicts(state)) {
13910                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13911                 return -EINVAL;
13912         }
13913
13914         intel_state->modeset = true;
13915         intel_state->active_crtcs = dev_priv->active_crtcs;
13916
13917         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13918                 if (crtc_state->active)
13919                         intel_state->active_crtcs |= 1 << i;
13920                 else
13921                         intel_state->active_crtcs &= ~(1 << i);
13922
13923                 if (crtc_state->active != crtc->state->active)
13924                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13925         }
13926
13927         /*
13928          * See if the config requires any additional preparation, e.g.
13929          * to adjust global state with pipes off.  We need to do this
13930          * here so we can get the modeset_pipe updated config for the new
13931          * mode set on this crtc.  For other crtcs we need to use the
13932          * adjusted_mode bits in the crtc directly.
13933          */
13934         if (dev_priv->display.modeset_calc_cdclk) {
13935                 if (!intel_state->cdclk_pll_vco)
13936                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13937                 if (!intel_state->cdclk_pll_vco)
13938                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13939
13940                 ret = dev_priv->display.modeset_calc_cdclk(state);
13941                 if (ret < 0)
13942                         return ret;
13943
13944                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13945                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13946                         ret = intel_modeset_all_pipes(state);
13947
13948                 if (ret < 0)
13949                         return ret;
13950
13951                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13952                               intel_state->cdclk, intel_state->dev_cdclk);
13953         } else
13954                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13955
13956         intel_modeset_clear_plls(state);
13957
13958         if (IS_HASWELL(dev_priv))
13959                 return haswell_mode_set_planes_workaround(state);
13960
13961         return 0;
13962 }
13963
13964 /*
13965  * Handle calculation of various watermark data at the end of the atomic check
13966  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13967  * handlers to ensure that all derived state has been updated.
13968  */
13969 static int calc_watermark_data(struct drm_atomic_state *state)
13970 {
13971         struct drm_device *dev = state->dev;
13972         struct drm_i915_private *dev_priv = to_i915(dev);
13973
13974         /* Is there platform-specific watermark information to calculate? */
13975         if (dev_priv->display.compute_global_watermarks)
13976                 return dev_priv->display.compute_global_watermarks(state);
13977
13978         return 0;
13979 }
13980
13981 /**
13982  * intel_atomic_check - validate state object
13983  * @dev: drm device
13984  * @state: state to validate
13985  */
13986 static int intel_atomic_check(struct drm_device *dev,
13987                               struct drm_atomic_state *state)
13988 {
13989         struct drm_i915_private *dev_priv = to_i915(dev);
13990         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13991         struct drm_crtc *crtc;
13992         struct drm_crtc_state *crtc_state;
13993         int ret, i;
13994         bool any_ms = false;
13995
13996         ret = drm_atomic_helper_check_modeset(dev, state);
13997         if (ret)
13998                 return ret;
13999
14000         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14001                 struct intel_crtc_state *pipe_config =
14002                         to_intel_crtc_state(crtc_state);
14003
14004                 /* Catch I915_MODE_FLAG_INHERITED */
14005                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14006                         crtc_state->mode_changed = true;
14007
14008                 if (!needs_modeset(crtc_state))
14009                         continue;
14010
14011                 if (!crtc_state->enable) {
14012                         any_ms = true;
14013                         continue;
14014                 }
14015
14016                 /* FIXME: For only active_changed we shouldn't need to do any
14017                  * state recomputation at all. */
14018
14019                 ret = drm_atomic_add_affected_connectors(state, crtc);
14020                 if (ret)
14021                         return ret;
14022
14023                 ret = intel_modeset_pipe_config(crtc, pipe_config);
14024                 if (ret) {
14025                         intel_dump_pipe_config(to_intel_crtc(crtc),
14026                                                pipe_config, "[failed]");
14027                         return ret;
14028                 }
14029
14030                 if (i915.fastboot &&
14031                     intel_pipe_config_compare(dev,
14032                                         to_intel_crtc_state(crtc->state),
14033                                         pipe_config, true)) {
14034                         crtc_state->mode_changed = false;
14035                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14036                 }
14037
14038                 if (needs_modeset(crtc_state))
14039                         any_ms = true;
14040
14041                 ret = drm_atomic_add_affected_planes(state, crtc);
14042                 if (ret)
14043                         return ret;
14044
14045                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14046                                        needs_modeset(crtc_state) ?
14047                                        "[modeset]" : "[fastset]");
14048         }
14049
14050         if (any_ms) {
14051                 ret = intel_modeset_checks(state);
14052
14053                 if (ret)
14054                         return ret;
14055         } else
14056                 intel_state->cdclk = dev_priv->cdclk_freq;
14057
14058         ret = drm_atomic_helper_check_planes(dev, state);
14059         if (ret)
14060                 return ret;
14061
14062         intel_fbc_choose_crtc(dev_priv, state);
14063         return calc_watermark_data(state);
14064 }
14065
14066 static int intel_atomic_prepare_commit(struct drm_device *dev,
14067                                        struct drm_atomic_state *state,
14068                                        bool nonblock)
14069 {
14070         struct drm_i915_private *dev_priv = to_i915(dev);
14071         struct drm_plane_state *plane_state;
14072         struct drm_crtc_state *crtc_state;
14073         struct drm_plane *plane;
14074         struct drm_crtc *crtc;
14075         int i, ret;
14076
14077         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14078                 if (state->legacy_cursor_update)
14079                         continue;
14080
14081                 ret = intel_crtc_wait_for_pending_flips(crtc);
14082                 if (ret)
14083                         return ret;
14084
14085                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14086                         flush_workqueue(dev_priv->wq);
14087         }
14088
14089         ret = mutex_lock_interruptible(&dev->struct_mutex);
14090         if (ret)
14091                 return ret;
14092
14093         ret = drm_atomic_helper_prepare_planes(dev, state);
14094         mutex_unlock(&dev->struct_mutex);
14095
14096         if (!ret && !nonblock) {
14097                 for_each_plane_in_state(state, plane, plane_state, i) {
14098                         struct intel_plane_state *intel_plane_state =
14099                                 to_intel_plane_state(plane_state);
14100
14101                         if (!intel_plane_state->wait_req)
14102                                 continue;
14103
14104                         ret = i915_wait_request(intel_plane_state->wait_req,
14105                                                 I915_WAIT_INTERRUPTIBLE,
14106                                                 NULL, NULL);
14107                         if (ret) {
14108                                 /* Any hang should be swallowed by the wait */
14109                                 WARN_ON(ret == -EIO);
14110                                 mutex_lock(&dev->struct_mutex);
14111                                 drm_atomic_helper_cleanup_planes(dev, state);
14112                                 mutex_unlock(&dev->struct_mutex);
14113                                 break;
14114                         }
14115                 }
14116         }
14117
14118         return ret;
14119 }
14120
14121 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14122 {
14123         struct drm_device *dev = crtc->base.dev;
14124
14125         if (!dev->max_vblank_count)
14126                 return drm_accurate_vblank_count(&crtc->base);
14127
14128         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14129 }
14130
14131 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14132                                           struct drm_i915_private *dev_priv,
14133                                           unsigned crtc_mask)
14134 {
14135         unsigned last_vblank_count[I915_MAX_PIPES];
14136         enum pipe pipe;
14137         int ret;
14138
14139         if (!crtc_mask)
14140                 return;
14141
14142         for_each_pipe(dev_priv, pipe) {
14143                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14144
14145                 if (!((1 << pipe) & crtc_mask))
14146                         continue;
14147
14148                 ret = drm_crtc_vblank_get(crtc);
14149                 if (WARN_ON(ret != 0)) {
14150                         crtc_mask &= ~(1 << pipe);
14151                         continue;
14152                 }
14153
14154                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14155         }
14156
14157         for_each_pipe(dev_priv, pipe) {
14158                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14159                 long lret;
14160
14161                 if (!((1 << pipe) & crtc_mask))
14162                         continue;
14163
14164                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14165                                 last_vblank_count[pipe] !=
14166                                         drm_crtc_vblank_count(crtc),
14167                                 msecs_to_jiffies(50));
14168
14169                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14170
14171                 drm_crtc_vblank_put(crtc);
14172         }
14173 }
14174
14175 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14176 {
14177         /* fb updated, need to unpin old fb */
14178         if (crtc_state->fb_changed)
14179                 return true;
14180
14181         /* wm changes, need vblank before final wm's */
14182         if (crtc_state->update_wm_post)
14183                 return true;
14184
14185         /*
14186          * cxsr is re-enabled after vblank.
14187          * This is already handled by crtc_state->update_wm_post,
14188          * but added for clarity.
14189          */
14190         if (crtc_state->disable_cxsr)
14191                 return true;
14192
14193         return false;
14194 }
14195
14196 static void intel_update_crtc(struct drm_crtc *crtc,
14197                               struct drm_atomic_state *state,
14198                               struct drm_crtc_state *old_crtc_state,
14199                               unsigned int *crtc_vblank_mask)
14200 {
14201         struct drm_device *dev = crtc->dev;
14202         struct drm_i915_private *dev_priv = to_i915(dev);
14203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14204         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14205         bool modeset = needs_modeset(crtc->state);
14206
14207         if (modeset) {
14208                 update_scanline_offset(intel_crtc);
14209                 dev_priv->display.crtc_enable(pipe_config, state);
14210         } else {
14211                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14212         }
14213
14214         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14215                 intel_fbc_enable(
14216                     intel_crtc, pipe_config,
14217                     to_intel_plane_state(crtc->primary->state));
14218         }
14219
14220         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14221
14222         if (needs_vblank_wait(pipe_config))
14223                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14224 }
14225
14226 static void intel_update_crtcs(struct drm_atomic_state *state,
14227                                unsigned int *crtc_vblank_mask)
14228 {
14229         struct drm_crtc *crtc;
14230         struct drm_crtc_state *old_crtc_state;
14231         int i;
14232
14233         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14234                 if (!crtc->state->active)
14235                         continue;
14236
14237                 intel_update_crtc(crtc, state, old_crtc_state,
14238                                   crtc_vblank_mask);
14239         }
14240 }
14241
14242 static void skl_update_crtcs(struct drm_atomic_state *state,
14243                              unsigned int *crtc_vblank_mask)
14244 {
14245         struct drm_device *dev = state->dev;
14246         struct drm_i915_private *dev_priv = to_i915(dev);
14247         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14248         struct drm_crtc *crtc;
14249         struct drm_crtc_state *old_crtc_state;
14250         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14251         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14252         unsigned int updated = 0;
14253         bool progress;
14254         enum pipe pipe;
14255
14256         /*
14257          * Whenever the number of active pipes changes, we need to make sure we
14258          * update the pipes in the right order so that their ddb allocations
14259          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14260          * cause pipe underruns and other bad stuff.
14261          */
14262         do {
14263                 int i;
14264                 progress = false;
14265
14266                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14267                         bool vbl_wait = false;
14268                         unsigned int cmask = drm_crtc_mask(crtc);
14269                         pipe = to_intel_crtc(crtc)->pipe;
14270
14271                         if (updated & cmask || !crtc->state->active)
14272                                 continue;
14273                         if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14274                                                         pipe))
14275                                 continue;
14276
14277                         updated |= cmask;
14278
14279                         /*
14280                          * If this is an already active pipe, it's DDB changed,
14281                          * and this isn't the last pipe that needs updating
14282                          * then we need to wait for a vblank to pass for the
14283                          * new ddb allocation to take effect.
14284                          */
14285                         if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14286                             !crtc->state->active_changed &&
14287                             intel_state->wm_results.dirty_pipes != updated)
14288                                 vbl_wait = true;
14289
14290                         intel_update_crtc(crtc, state, old_crtc_state,
14291                                           crtc_vblank_mask);
14292
14293                         if (vbl_wait)
14294                                 intel_wait_for_vblank(dev, pipe);
14295
14296                         progress = true;
14297                 }
14298         } while (progress);
14299 }
14300
14301 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14302 {
14303         struct drm_device *dev = state->dev;
14304         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14305         struct drm_i915_private *dev_priv = to_i915(dev);
14306         struct drm_crtc_state *old_crtc_state;
14307         struct drm_crtc *crtc;
14308         struct intel_crtc_state *intel_cstate;
14309         struct drm_plane *plane;
14310         struct drm_plane_state *plane_state;
14311         bool hw_check = intel_state->modeset;
14312         unsigned long put_domains[I915_MAX_PIPES] = {};
14313         unsigned crtc_vblank_mask = 0;
14314         int i, ret;
14315
14316         for_each_plane_in_state(state, plane, plane_state, i) {
14317                 struct intel_plane_state *intel_plane_state =
14318                         to_intel_plane_state(plane_state);
14319
14320                 if (!intel_plane_state->wait_req)
14321                         continue;
14322
14323                 ret = i915_wait_request(intel_plane_state->wait_req,
14324                                         0, NULL, NULL);
14325                 /* EIO should be eaten, and we can't get interrupted in the
14326                  * worker, and blocking commits have waited already. */
14327                 WARN_ON(ret);
14328         }
14329
14330         drm_atomic_helper_wait_for_dependencies(state);
14331
14332         if (intel_state->modeset) {
14333                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14334                        sizeof(intel_state->min_pixclk));
14335                 dev_priv->active_crtcs = intel_state->active_crtcs;
14336                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14337
14338                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14339         }
14340
14341         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14342                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14343
14344                 if (needs_modeset(crtc->state) ||
14345                     to_intel_crtc_state(crtc->state)->update_pipe) {
14346                         hw_check = true;
14347
14348                         put_domains[to_intel_crtc(crtc)->pipe] =
14349                                 modeset_get_crtc_power_domains(crtc,
14350                                         to_intel_crtc_state(crtc->state));
14351                 }
14352
14353                 if (!needs_modeset(crtc->state))
14354                         continue;
14355
14356                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14357
14358                 if (old_crtc_state->active) {
14359                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14360                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14361                         intel_crtc->active = false;
14362                         intel_fbc_disable(intel_crtc);
14363                         intel_disable_shared_dpll(intel_crtc);
14364
14365                         /*
14366                          * Underruns don't always raise
14367                          * interrupts, so check manually.
14368                          */
14369                         intel_check_cpu_fifo_underruns(dev_priv);
14370                         intel_check_pch_fifo_underruns(dev_priv);
14371
14372                         if (!crtc->state->active)
14373                                 intel_update_watermarks(crtc);
14374                 }
14375         }
14376
14377         /* Only after disabling all output pipelines that will be changed can we
14378          * update the the output configuration. */
14379         intel_modeset_update_crtc_state(state);
14380
14381         if (intel_state->modeset) {
14382                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14383
14384                 if (dev_priv->display.modeset_commit_cdclk &&
14385                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14386                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14387                         dev_priv->display.modeset_commit_cdclk(state);
14388
14389                 /*
14390                  * SKL workaround: bspec recommends we disable the SAGV when we
14391                  * have more then one pipe enabled
14392                  */
14393                 if (!intel_can_enable_sagv(state))
14394                         intel_disable_sagv(dev_priv);
14395
14396                 intel_modeset_verify_disabled(dev);
14397         }
14398
14399         /* Complete the events for pipes that have now been disabled */
14400         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14401                 bool modeset = needs_modeset(crtc->state);
14402
14403                 /* Complete events for now disable pipes here. */
14404                 if (modeset && !crtc->state->active && crtc->state->event) {
14405                         spin_lock_irq(&dev->event_lock);
14406                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14407                         spin_unlock_irq(&dev->event_lock);
14408
14409                         crtc->state->event = NULL;
14410                 }
14411         }
14412
14413         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14414         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14415
14416         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14417          * already, but still need the state for the delayed optimization. To
14418          * fix this:
14419          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14420          * - schedule that vblank worker _before_ calling hw_done
14421          * - at the start of commit_tail, cancel it _synchrously
14422          * - switch over to the vblank wait helper in the core after that since
14423          *   we don't need out special handling any more.
14424          */
14425         if (!state->legacy_cursor_update)
14426                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14427
14428         /*
14429          * Now that the vblank has passed, we can go ahead and program the
14430          * optimal watermarks on platforms that need two-step watermark
14431          * programming.
14432          *
14433          * TODO: Move this (and other cleanup) to an async worker eventually.
14434          */
14435         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14436                 intel_cstate = to_intel_crtc_state(crtc->state);
14437
14438                 if (dev_priv->display.optimize_watermarks)
14439                         dev_priv->display.optimize_watermarks(intel_cstate);
14440         }
14441
14442         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14443                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14444
14445                 if (put_domains[i])
14446                         modeset_put_power_domains(dev_priv, put_domains[i]);
14447
14448                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14449         }
14450
14451         if (intel_state->modeset && intel_can_enable_sagv(state))
14452                 intel_enable_sagv(dev_priv);
14453
14454         drm_atomic_helper_commit_hw_done(state);
14455
14456         if (intel_state->modeset)
14457                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14458
14459         mutex_lock(&dev->struct_mutex);
14460         drm_atomic_helper_cleanup_planes(dev, state);
14461         mutex_unlock(&dev->struct_mutex);
14462
14463         drm_atomic_helper_commit_cleanup_done(state);
14464
14465         drm_atomic_state_put(state);
14466
14467         /* As one of the primary mmio accessors, KMS has a high likelihood
14468          * of triggering bugs in unclaimed access. After we finish
14469          * modesetting, see if an error has been flagged, and if so
14470          * enable debugging for the next modeset - and hope we catch
14471          * the culprit.
14472          *
14473          * XXX note that we assume display power is on at this point.
14474          * This might hold true now but we need to add pm helper to check
14475          * unclaimed only when the hardware is on, as atomic commits
14476          * can happen also when the device is completely off.
14477          */
14478         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14479 }
14480
14481 static void intel_atomic_commit_work(struct work_struct *work)
14482 {
14483         struct drm_atomic_state *state = container_of(work,
14484                                                       struct drm_atomic_state,
14485                                                       commit_work);
14486         intel_atomic_commit_tail(state);
14487 }
14488
14489 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14490 {
14491         struct drm_plane_state *old_plane_state;
14492         struct drm_plane *plane;
14493         int i;
14494
14495         for_each_plane_in_state(state, plane, old_plane_state, i)
14496                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14497                                   intel_fb_obj(plane->state->fb),
14498                                   to_intel_plane(plane)->frontbuffer_bit);
14499 }
14500
14501 /**
14502  * intel_atomic_commit - commit validated state object
14503  * @dev: DRM device
14504  * @state: the top-level driver state object
14505  * @nonblock: nonblocking commit
14506  *
14507  * This function commits a top-level state object that has been validated
14508  * with drm_atomic_helper_check().
14509  *
14510  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
14511  * nonblocking commits are only safe for pure plane updates. Everything else
14512  * should work though.
14513  *
14514  * RETURNS
14515  * Zero for success or -errno.
14516  */
14517 static int intel_atomic_commit(struct drm_device *dev,
14518                                struct drm_atomic_state *state,
14519                                bool nonblock)
14520 {
14521         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14522         struct drm_i915_private *dev_priv = to_i915(dev);
14523         int ret = 0;
14524
14525         if (intel_state->modeset && nonblock) {
14526                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14527                 return -EINVAL;
14528         }
14529
14530         ret = drm_atomic_helper_setup_commit(state, nonblock);
14531         if (ret)
14532                 return ret;
14533
14534         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14535
14536         ret = intel_atomic_prepare_commit(dev, state, nonblock);
14537         if (ret) {
14538                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14539                 return ret;
14540         }
14541
14542         drm_atomic_helper_swap_state(state, true);
14543         dev_priv->wm.distrust_bios_wm = false;
14544         dev_priv->wm.skl_results = intel_state->wm_results;
14545         intel_shared_dpll_commit(state);
14546         intel_atomic_track_fbs(state);
14547
14548         drm_atomic_state_get(state);
14549         if (nonblock)
14550                 queue_work(system_unbound_wq, &state->commit_work);
14551         else
14552                 intel_atomic_commit_tail(state);
14553
14554         return 0;
14555 }
14556
14557 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14558 {
14559         struct drm_device *dev = crtc->dev;
14560         struct drm_atomic_state *state;
14561         struct drm_crtc_state *crtc_state;
14562         int ret;
14563
14564         state = drm_atomic_state_alloc(dev);
14565         if (!state) {
14566                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14567                               crtc->base.id, crtc->name);
14568                 return;
14569         }
14570
14571         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14572
14573 retry:
14574         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14575         ret = PTR_ERR_OR_ZERO(crtc_state);
14576         if (!ret) {
14577                 if (!crtc_state->active)
14578                         goto out;
14579
14580                 crtc_state->mode_changed = true;
14581                 ret = drm_atomic_commit(state);
14582         }
14583
14584         if (ret == -EDEADLK) {
14585                 drm_atomic_state_clear(state);
14586                 drm_modeset_backoff(state->acquire_ctx);
14587                 goto retry;
14588         }
14589
14590 out:
14591         drm_atomic_state_put(state);
14592 }
14593
14594 /*
14595  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14596  *        drm_atomic_helper_legacy_gamma_set() directly.
14597  */
14598 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14599                                          u16 *red, u16 *green, u16 *blue,
14600                                          uint32_t size)
14601 {
14602         struct drm_device *dev = crtc->dev;
14603         struct drm_mode_config *config = &dev->mode_config;
14604         struct drm_crtc_state *state;
14605         int ret;
14606
14607         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14608         if (ret)
14609                 return ret;
14610
14611         /*
14612          * Make sure we update the legacy properties so this works when
14613          * atomic is not enabled.
14614          */
14615
14616         state = crtc->state;
14617
14618         drm_object_property_set_value(&crtc->base,
14619                                       config->degamma_lut_property,
14620                                       (state->degamma_lut) ?
14621                                       state->degamma_lut->base.id : 0);
14622
14623         drm_object_property_set_value(&crtc->base,
14624                                       config->ctm_property,
14625                                       (state->ctm) ?
14626                                       state->ctm->base.id : 0);
14627
14628         drm_object_property_set_value(&crtc->base,
14629                                       config->gamma_lut_property,
14630                                       (state->gamma_lut) ?
14631                                       state->gamma_lut->base.id : 0);
14632
14633         return 0;
14634 }
14635
14636 static const struct drm_crtc_funcs intel_crtc_funcs = {
14637         .gamma_set = intel_atomic_legacy_gamma_set,
14638         .set_config = drm_atomic_helper_set_config,
14639         .set_property = drm_atomic_helper_crtc_set_property,
14640         .destroy = intel_crtc_destroy,
14641         .page_flip = intel_crtc_page_flip,
14642         .atomic_duplicate_state = intel_crtc_duplicate_state,
14643         .atomic_destroy_state = intel_crtc_destroy_state,
14644 };
14645
14646 /**
14647  * intel_prepare_plane_fb - Prepare fb for usage on plane
14648  * @plane: drm plane to prepare for
14649  * @fb: framebuffer to prepare for presentation
14650  *
14651  * Prepares a framebuffer for usage on a display plane.  Generally this
14652  * involves pinning the underlying object and updating the frontbuffer tracking
14653  * bits.  Some older platforms need special physical address handling for
14654  * cursor planes.
14655  *
14656  * Must be called with struct_mutex held.
14657  *
14658  * Returns 0 on success, negative error code on failure.
14659  */
14660 int
14661 intel_prepare_plane_fb(struct drm_plane *plane,
14662                        struct drm_plane_state *new_state)
14663 {
14664         struct drm_device *dev = plane->dev;
14665         struct drm_framebuffer *fb = new_state->fb;
14666         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14667         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14668         struct reservation_object *resv;
14669         int ret = 0;
14670
14671         if (!obj && !old_obj)
14672                 return 0;
14673
14674         if (old_obj) {
14675                 struct drm_crtc_state *crtc_state =
14676                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14677
14678                 /* Big Hammer, we also need to ensure that any pending
14679                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14680                  * current scanout is retired before unpinning the old
14681                  * framebuffer. Note that we rely on userspace rendering
14682                  * into the buffer attached to the pipe they are waiting
14683                  * on. If not, userspace generates a GPU hang with IPEHR
14684                  * point to the MI_WAIT_FOR_EVENT.
14685                  *
14686                  * This should only fail upon a hung GPU, in which case we
14687                  * can safely continue.
14688                  */
14689                 if (needs_modeset(crtc_state))
14690                         ret = i915_gem_object_wait_rendering(old_obj, true);
14691                 if (ret) {
14692                         /* GPU hangs should have been swallowed by the wait */
14693                         WARN_ON(ret == -EIO);
14694                         return ret;
14695                 }
14696         }
14697
14698         if (!obj)
14699                 return 0;
14700
14701         /* For framebuffer backed by dmabuf, wait for fence */
14702         resv = i915_gem_object_get_dmabuf_resv(obj);
14703         if (resv) {
14704                 long lret;
14705
14706                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14707                                                            MAX_SCHEDULE_TIMEOUT);
14708                 if (lret == -ERESTARTSYS)
14709                         return lret;
14710
14711                 WARN(lret < 0, "waiting returns %li\n", lret);
14712         }
14713
14714         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14715             INTEL_INFO(dev)->cursor_needs_physical) {
14716                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14717                 ret = i915_gem_object_attach_phys(obj, align);
14718                 if (ret)
14719                         DRM_DEBUG_KMS("failed to attach phys object\n");
14720         } else {
14721                 struct i915_vma *vma;
14722
14723                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14724                 if (IS_ERR(vma))
14725                         ret = PTR_ERR(vma);
14726         }
14727
14728         if (ret == 0) {
14729                 to_intel_plane_state(new_state)->wait_req =
14730                         i915_gem_active_get(&obj->last_write,
14731                                             &obj->base.dev->struct_mutex);
14732         }
14733
14734         return ret;
14735 }
14736
14737 /**
14738  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14739  * @plane: drm plane to clean up for
14740  * @fb: old framebuffer that was on plane
14741  *
14742  * Cleans up a framebuffer that has just been removed from a plane.
14743  *
14744  * Must be called with struct_mutex held.
14745  */
14746 void
14747 intel_cleanup_plane_fb(struct drm_plane *plane,
14748                        struct drm_plane_state *old_state)
14749 {
14750         struct drm_device *dev = plane->dev;
14751         struct intel_plane_state *old_intel_state;
14752         struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14753         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14754         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14755
14756         old_intel_state = to_intel_plane_state(old_state);
14757
14758         if (!obj && !old_obj)
14759                 return;
14760
14761         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14762             !INTEL_INFO(dev)->cursor_needs_physical))
14763                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14764
14765         i915_gem_request_assign(&intel_state->wait_req, NULL);
14766         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14767 }
14768
14769 int
14770 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14771 {
14772         int max_scale;
14773         int crtc_clock, cdclk;
14774
14775         if (!intel_crtc || !crtc_state->base.enable)
14776                 return DRM_PLANE_HELPER_NO_SCALING;
14777
14778         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14779         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14780
14781         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14782                 return DRM_PLANE_HELPER_NO_SCALING;
14783
14784         /*
14785          * skl max scale is lower of:
14786          *    close to 3 but not 3, -1 is for that purpose
14787          *            or
14788          *    cdclk/crtc_clock
14789          */
14790         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14791
14792         return max_scale;
14793 }
14794
14795 static int
14796 intel_check_primary_plane(struct drm_plane *plane,
14797                           struct intel_crtc_state *crtc_state,
14798                           struct intel_plane_state *state)
14799 {
14800         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14801         struct drm_crtc *crtc = state->base.crtc;
14802         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14803         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14804         bool can_position = false;
14805         int ret;
14806
14807         if (INTEL_GEN(dev_priv) >= 9) {
14808                 /* use scaler when colorkey is not required */
14809                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14810                         min_scale = 1;
14811                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14812                 }
14813                 can_position = true;
14814         }
14815
14816         ret = drm_plane_helper_check_state(&state->base,
14817                                            &state->clip,
14818                                            min_scale, max_scale,
14819                                            can_position, true);
14820         if (ret)
14821                 return ret;
14822
14823         if (!state->base.fb)
14824                 return 0;
14825
14826         if (INTEL_GEN(dev_priv) >= 9) {
14827                 ret = skl_check_plane_surface(state);
14828                 if (ret)
14829                         return ret;
14830         }
14831
14832         return 0;
14833 }
14834
14835 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14836                                     struct drm_crtc_state *old_crtc_state)
14837 {
14838         struct drm_device *dev = crtc->dev;
14839         struct drm_i915_private *dev_priv = to_i915(dev);
14840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14841         struct intel_crtc_state *old_intel_state =
14842                 to_intel_crtc_state(old_crtc_state);
14843         bool modeset = needs_modeset(crtc->state);
14844         enum pipe pipe = intel_crtc->pipe;
14845
14846         /* Perform vblank evasion around commit operation */
14847         intel_pipe_update_start(intel_crtc);
14848
14849         if (modeset)
14850                 return;
14851
14852         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14853                 intel_color_set_csc(crtc->state);
14854                 intel_color_load_luts(crtc->state);
14855         }
14856
14857         if (to_intel_crtc_state(crtc->state)->update_pipe)
14858                 intel_update_pipe_config(intel_crtc, old_intel_state);
14859         else if (INTEL_GEN(dev_priv) >= 9) {
14860                 skl_detach_scalers(intel_crtc);
14861
14862                 I915_WRITE(PIPE_WM_LINETIME(pipe),
14863                            dev_priv->wm.skl_hw.wm_linetime[pipe]);
14864         }
14865 }
14866
14867 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14868                                      struct drm_crtc_state *old_crtc_state)
14869 {
14870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14871
14872         intel_pipe_update_end(intel_crtc, NULL);
14873 }
14874
14875 /**
14876  * intel_plane_destroy - destroy a plane
14877  * @plane: plane to destroy
14878  *
14879  * Common destruction function for all types of planes (primary, cursor,
14880  * sprite).
14881  */
14882 void intel_plane_destroy(struct drm_plane *plane)
14883 {
14884         if (!plane)
14885                 return;
14886
14887         drm_plane_cleanup(plane);
14888         kfree(to_intel_plane(plane));
14889 }
14890
14891 const struct drm_plane_funcs intel_plane_funcs = {
14892         .update_plane = drm_atomic_helper_update_plane,
14893         .disable_plane = drm_atomic_helper_disable_plane,
14894         .destroy = intel_plane_destroy,
14895         .set_property = drm_atomic_helper_plane_set_property,
14896         .atomic_get_property = intel_plane_atomic_get_property,
14897         .atomic_set_property = intel_plane_atomic_set_property,
14898         .atomic_duplicate_state = intel_plane_duplicate_state,
14899         .atomic_destroy_state = intel_plane_destroy_state,
14900
14901 };
14902
14903 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14904                                                     int pipe)
14905 {
14906         struct intel_plane *primary = NULL;
14907         struct intel_plane_state *state = NULL;
14908         const uint32_t *intel_primary_formats;
14909         unsigned int supported_rotations;
14910         unsigned int num_formats;
14911         int ret;
14912
14913         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14914         if (!primary)
14915                 goto fail;
14916
14917         state = intel_create_plane_state(&primary->base);
14918         if (!state)
14919                 goto fail;
14920         primary->base.state = &state->base;
14921
14922         primary->can_scale = false;
14923         primary->max_downscale = 1;
14924         if (INTEL_INFO(dev)->gen >= 9) {
14925                 primary->can_scale = true;
14926                 state->scaler_id = -1;
14927         }
14928         primary->pipe = pipe;
14929         primary->plane = pipe;
14930         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14931         primary->check_plane = intel_check_primary_plane;
14932         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14933                 primary->plane = !pipe;
14934
14935         if (INTEL_INFO(dev)->gen >= 9) {
14936                 intel_primary_formats = skl_primary_formats;
14937                 num_formats = ARRAY_SIZE(skl_primary_formats);
14938
14939                 primary->update_plane = skylake_update_primary_plane;
14940                 primary->disable_plane = skylake_disable_primary_plane;
14941         } else if (HAS_PCH_SPLIT(dev)) {
14942                 intel_primary_formats = i965_primary_formats;
14943                 num_formats = ARRAY_SIZE(i965_primary_formats);
14944
14945                 primary->update_plane = ironlake_update_primary_plane;
14946                 primary->disable_plane = i9xx_disable_primary_plane;
14947         } else if (INTEL_INFO(dev)->gen >= 4) {
14948                 intel_primary_formats = i965_primary_formats;
14949                 num_formats = ARRAY_SIZE(i965_primary_formats);
14950
14951                 primary->update_plane = i9xx_update_primary_plane;
14952                 primary->disable_plane = i9xx_disable_primary_plane;
14953         } else {
14954                 intel_primary_formats = i8xx_primary_formats;
14955                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14956
14957                 primary->update_plane = i9xx_update_primary_plane;
14958                 primary->disable_plane = i9xx_disable_primary_plane;
14959         }
14960
14961         if (INTEL_INFO(dev)->gen >= 9)
14962                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14963                                                &intel_plane_funcs,
14964                                                intel_primary_formats, num_formats,
14965                                                DRM_PLANE_TYPE_PRIMARY,
14966                                                "plane 1%c", pipe_name(pipe));
14967         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14968                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14969                                                &intel_plane_funcs,
14970                                                intel_primary_formats, num_formats,
14971                                                DRM_PLANE_TYPE_PRIMARY,
14972                                                "primary %c", pipe_name(pipe));
14973         else
14974                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14975                                                &intel_plane_funcs,
14976                                                intel_primary_formats, num_formats,
14977                                                DRM_PLANE_TYPE_PRIMARY,
14978                                                "plane %c", plane_name(primary->plane));
14979         if (ret)
14980                 goto fail;
14981
14982         if (INTEL_GEN(dev) >= 9) {
14983                 supported_rotations =
14984                         DRM_ROTATE_0 | DRM_ROTATE_90 |
14985                         DRM_ROTATE_180 | DRM_ROTATE_270;
14986         } else if (INTEL_GEN(dev) >= 4) {
14987                 supported_rotations =
14988                         DRM_ROTATE_0 | DRM_ROTATE_180;
14989         } else {
14990                 supported_rotations = DRM_ROTATE_0;
14991         }
14992
14993         if (INTEL_GEN(dev) >= 4)
14994                 drm_plane_create_rotation_property(&primary->base,
14995                                                    DRM_ROTATE_0,
14996                                                    supported_rotations);
14997
14998         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14999
15000         return &primary->base;
15001
15002 fail:
15003         kfree(state);
15004         kfree(primary);
15005
15006         return NULL;
15007 }
15008
15009 static int
15010 intel_check_cursor_plane(struct drm_plane *plane,
15011                          struct intel_crtc_state *crtc_state,
15012                          struct intel_plane_state *state)
15013 {
15014         struct drm_framebuffer *fb = state->base.fb;
15015         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15016         enum pipe pipe = to_intel_plane(plane)->pipe;
15017         unsigned stride;
15018         int ret;
15019
15020         ret = drm_plane_helper_check_state(&state->base,
15021                                            &state->clip,
15022                                            DRM_PLANE_HELPER_NO_SCALING,
15023                                            DRM_PLANE_HELPER_NO_SCALING,
15024                                            true, true);
15025         if (ret)
15026                 return ret;
15027
15028         /* if we want to turn off the cursor ignore width and height */
15029         if (!obj)
15030                 return 0;
15031
15032         /* Check for which cursor types we support */
15033         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
15034                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15035                           state->base.crtc_w, state->base.crtc_h);
15036                 return -EINVAL;
15037         }
15038
15039         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15040         if (obj->base.size < stride * state->base.crtc_h) {
15041                 DRM_DEBUG_KMS("buffer is too small\n");
15042                 return -ENOMEM;
15043         }
15044
15045         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15046                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15047                 return -EINVAL;
15048         }
15049
15050         /*
15051          * There's something wrong with the cursor on CHV pipe C.
15052          * If it straddles the left edge of the screen then
15053          * moving it away from the edge or disabling it often
15054          * results in a pipe underrun, and often that can lead to
15055          * dead pipe (constant underrun reported, and it scans
15056          * out just a solid color). To recover from that, the
15057          * display power well must be turned off and on again.
15058          * Refuse the put the cursor into that compromised position.
15059          */
15060         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15061             state->base.visible && state->base.crtc_x < 0) {
15062                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15063                 return -EINVAL;
15064         }
15065
15066         return 0;
15067 }
15068
15069 static void
15070 intel_disable_cursor_plane(struct drm_plane *plane,
15071                            struct drm_crtc *crtc)
15072 {
15073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15074
15075         intel_crtc->cursor_addr = 0;
15076         intel_crtc_update_cursor(crtc, NULL);
15077 }
15078
15079 static void
15080 intel_update_cursor_plane(struct drm_plane *plane,
15081                           const struct intel_crtc_state *crtc_state,
15082                           const struct intel_plane_state *state)
15083 {
15084         struct drm_crtc *crtc = crtc_state->base.crtc;
15085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15086         struct drm_device *dev = plane->dev;
15087         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15088         uint32_t addr;
15089
15090         if (!obj)
15091                 addr = 0;
15092         else if (!INTEL_INFO(dev)->cursor_needs_physical)
15093                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15094         else
15095                 addr = obj->phys_handle->busaddr;
15096
15097         intel_crtc->cursor_addr = addr;
15098         intel_crtc_update_cursor(crtc, state);
15099 }
15100
15101 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15102                                                    int pipe)
15103 {
15104         struct intel_plane *cursor = NULL;
15105         struct intel_plane_state *state = NULL;
15106         int ret;
15107
15108         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15109         if (!cursor)
15110                 goto fail;
15111
15112         state = intel_create_plane_state(&cursor->base);
15113         if (!state)
15114                 goto fail;
15115         cursor->base.state = &state->base;
15116
15117         cursor->can_scale = false;
15118         cursor->max_downscale = 1;
15119         cursor->pipe = pipe;
15120         cursor->plane = pipe;
15121         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15122         cursor->check_plane = intel_check_cursor_plane;
15123         cursor->update_plane = intel_update_cursor_plane;
15124         cursor->disable_plane = intel_disable_cursor_plane;
15125
15126         ret = drm_universal_plane_init(dev, &cursor->base, 0,
15127                                        &intel_plane_funcs,
15128                                        intel_cursor_formats,
15129                                        ARRAY_SIZE(intel_cursor_formats),
15130                                        DRM_PLANE_TYPE_CURSOR,
15131                                        "cursor %c", pipe_name(pipe));
15132         if (ret)
15133                 goto fail;
15134
15135         if (INTEL_GEN(dev) >= 4)
15136                 drm_plane_create_rotation_property(&cursor->base,
15137                                                    DRM_ROTATE_0,
15138                                                    DRM_ROTATE_0 |
15139                                                    DRM_ROTATE_180);
15140
15141         if (INTEL_INFO(dev)->gen >=9)
15142                 state->scaler_id = -1;
15143
15144         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15145
15146         return &cursor->base;
15147
15148 fail:
15149         kfree(state);
15150         kfree(cursor);
15151
15152         return NULL;
15153 }
15154
15155 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15156         struct intel_crtc_state *crtc_state)
15157 {
15158         int i;
15159         struct intel_scaler *intel_scaler;
15160         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15161
15162         for (i = 0; i < intel_crtc->num_scalers; i++) {
15163                 intel_scaler = &scaler_state->scalers[i];
15164                 intel_scaler->in_use = 0;
15165                 intel_scaler->mode = PS_SCALER_MODE_DYN;
15166         }
15167
15168         scaler_state->scaler_id = -1;
15169 }
15170
15171 static void intel_crtc_init(struct drm_device *dev, int pipe)
15172 {
15173         struct drm_i915_private *dev_priv = to_i915(dev);
15174         struct intel_crtc *intel_crtc;
15175         struct intel_crtc_state *crtc_state = NULL;
15176         struct drm_plane *primary = NULL;
15177         struct drm_plane *cursor = NULL;
15178         int ret;
15179
15180         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15181         if (intel_crtc == NULL)
15182                 return;
15183
15184         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15185         if (!crtc_state)
15186                 goto fail;
15187         intel_crtc->config = crtc_state;
15188         intel_crtc->base.state = &crtc_state->base;
15189         crtc_state->base.crtc = &intel_crtc->base;
15190
15191         /* initialize shared scalers */
15192         if (INTEL_INFO(dev)->gen >= 9) {
15193                 if (pipe == PIPE_C)
15194                         intel_crtc->num_scalers = 1;
15195                 else
15196                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15197
15198                 skl_init_scalers(dev, intel_crtc, crtc_state);
15199         }
15200
15201         primary = intel_primary_plane_create(dev, pipe);
15202         if (!primary)
15203                 goto fail;
15204
15205         cursor = intel_cursor_plane_create(dev, pipe);
15206         if (!cursor)
15207                 goto fail;
15208
15209         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15210                                         cursor, &intel_crtc_funcs,
15211                                         "pipe %c", pipe_name(pipe));
15212         if (ret)
15213                 goto fail;
15214
15215         /*
15216          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15217          * is hooked to pipe B. Hence we want plane A feeding pipe B.
15218          */
15219         intel_crtc->pipe = pipe;
15220         intel_crtc->plane = pipe;
15221         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15222                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15223                 intel_crtc->plane = !pipe;
15224         }
15225
15226         intel_crtc->cursor_base = ~0;
15227         intel_crtc->cursor_cntl = ~0;
15228         intel_crtc->cursor_size = ~0;
15229
15230         intel_crtc->wm.cxsr_allowed = true;
15231
15232         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15233                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15234         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15235         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15236
15237         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15238
15239         intel_color_init(&intel_crtc->base);
15240
15241         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15242         return;
15243
15244 fail:
15245         intel_plane_destroy(primary);
15246         intel_plane_destroy(cursor);
15247         kfree(crtc_state);
15248         kfree(intel_crtc);
15249 }
15250
15251 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15252 {
15253         struct drm_encoder *encoder = connector->base.encoder;
15254         struct drm_device *dev = connector->base.dev;
15255
15256         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15257
15258         if (!encoder || WARN_ON(!encoder->crtc))
15259                 return INVALID_PIPE;
15260
15261         return to_intel_crtc(encoder->crtc)->pipe;
15262 }
15263
15264 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15265                                 struct drm_file *file)
15266 {
15267         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15268         struct drm_crtc *drmmode_crtc;
15269         struct intel_crtc *crtc;
15270
15271         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15272         if (!drmmode_crtc)
15273                 return -ENOENT;
15274
15275         crtc = to_intel_crtc(drmmode_crtc);
15276         pipe_from_crtc_id->pipe = crtc->pipe;
15277
15278         return 0;
15279 }
15280
15281 static int intel_encoder_clones(struct intel_encoder *encoder)
15282 {
15283         struct drm_device *dev = encoder->base.dev;
15284         struct intel_encoder *source_encoder;
15285         int index_mask = 0;
15286         int entry = 0;
15287
15288         for_each_intel_encoder(dev, source_encoder) {
15289                 if (encoders_cloneable(encoder, source_encoder))
15290                         index_mask |= (1 << entry);
15291
15292                 entry++;
15293         }
15294
15295         return index_mask;
15296 }
15297
15298 static bool has_edp_a(struct drm_device *dev)
15299 {
15300         struct drm_i915_private *dev_priv = to_i915(dev);
15301
15302         if (!IS_MOBILE(dev))
15303                 return false;
15304
15305         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15306                 return false;
15307
15308         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15309                 return false;
15310
15311         return true;
15312 }
15313
15314 static bool intel_crt_present(struct drm_device *dev)
15315 {
15316         struct drm_i915_private *dev_priv = to_i915(dev);
15317
15318         if (INTEL_INFO(dev)->gen >= 9)
15319                 return false;
15320
15321         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15322                 return false;
15323
15324         if (IS_CHERRYVIEW(dev))
15325                 return false;
15326
15327         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15328                 return false;
15329
15330         /* DDI E can't be used if DDI A requires 4 lanes */
15331         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15332                 return false;
15333
15334         if (!dev_priv->vbt.int_crt_support)
15335                 return false;
15336
15337         return true;
15338 }
15339
15340 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15341 {
15342         int pps_num;
15343         int pps_idx;
15344
15345         if (HAS_DDI(dev_priv))
15346                 return;
15347         /*
15348          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15349          * everywhere where registers can be write protected.
15350          */
15351         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15352                 pps_num = 2;
15353         else
15354                 pps_num = 1;
15355
15356         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15357                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15358
15359                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15360                 I915_WRITE(PP_CONTROL(pps_idx), val);
15361         }
15362 }
15363
15364 static void intel_pps_init(struct drm_i915_private *dev_priv)
15365 {
15366         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15367                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15368         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15369                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15370         else
15371                 dev_priv->pps_mmio_base = PPS_BASE;
15372
15373         intel_pps_unlock_regs_wa(dev_priv);
15374 }
15375
15376 static void intel_setup_outputs(struct drm_device *dev)
15377 {
15378         struct drm_i915_private *dev_priv = to_i915(dev);
15379         struct intel_encoder *encoder;
15380         bool dpd_is_edp = false;
15381
15382         intel_pps_init(dev_priv);
15383
15384         /*
15385          * intel_edp_init_connector() depends on this completing first, to
15386          * prevent the registeration of both eDP and LVDS and the incorrect
15387          * sharing of the PPS.
15388          */
15389         intel_lvds_init(dev);
15390
15391         if (intel_crt_present(dev))
15392                 intel_crt_init(dev);
15393
15394         if (IS_BROXTON(dev)) {
15395                 /*
15396                  * FIXME: Broxton doesn't support port detection via the
15397                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15398                  * detect the ports.
15399                  */
15400                 intel_ddi_init(dev, PORT_A);
15401                 intel_ddi_init(dev, PORT_B);
15402                 intel_ddi_init(dev, PORT_C);
15403
15404                 intel_dsi_init(dev);
15405         } else if (HAS_DDI(dev)) {
15406                 int found;
15407
15408                 /*
15409                  * Haswell uses DDI functions to detect digital outputs.
15410                  * On SKL pre-D0 the strap isn't connected, so we assume
15411                  * it's there.
15412                  */
15413                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15414                 /* WaIgnoreDDIAStrap: skl */
15415                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15416                         intel_ddi_init(dev, PORT_A);
15417
15418                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15419                  * register */
15420                 found = I915_READ(SFUSE_STRAP);
15421
15422                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15423                         intel_ddi_init(dev, PORT_B);
15424                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15425                         intel_ddi_init(dev, PORT_C);
15426                 if (found & SFUSE_STRAP_DDID_DETECTED)
15427                         intel_ddi_init(dev, PORT_D);
15428                 /*
15429                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15430                  */
15431                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15432                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15433                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15434                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15435                         intel_ddi_init(dev, PORT_E);
15436
15437         } else if (HAS_PCH_SPLIT(dev)) {
15438                 int found;
15439                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15440
15441                 if (has_edp_a(dev))
15442                         intel_dp_init(dev, DP_A, PORT_A);
15443
15444                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15445                         /* PCH SDVOB multiplex with HDMIB */
15446                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15447                         if (!found)
15448                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15449                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15450                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15451                 }
15452
15453                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15454                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15455
15456                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15457                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15458
15459                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15460                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15461
15462                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15463                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15464         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15465                 bool has_edp, has_port;
15466
15467                 /*
15468                  * The DP_DETECTED bit is the latched state of the DDC
15469                  * SDA pin at boot. However since eDP doesn't require DDC
15470                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15471                  * eDP ports may have been muxed to an alternate function.
15472                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15473                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15474                  * detect eDP ports.
15475                  *
15476                  * Sadly the straps seem to be missing sometimes even for HDMI
15477                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15478                  * and VBT for the presence of the port. Additionally we can't
15479                  * trust the port type the VBT declares as we've seen at least
15480                  * HDMI ports that the VBT claim are DP or eDP.
15481                  */
15482                 has_edp = intel_dp_is_edp(dev, PORT_B);
15483                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15484                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15485                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15486                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15487                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15488
15489                 has_edp = intel_dp_is_edp(dev, PORT_C);
15490                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15491                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15492                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15493                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15494                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15495
15496                 if (IS_CHERRYVIEW(dev)) {
15497                         /*
15498                          * eDP not supported on port D,
15499                          * so no need to worry about it
15500                          */
15501                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15502                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15503                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15504                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15505                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15506                 }
15507
15508                 intel_dsi_init(dev);
15509         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15510                 bool found = false;
15511
15512                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15513                         DRM_DEBUG_KMS("probing SDVOB\n");
15514                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15515                         if (!found && IS_G4X(dev)) {
15516                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15517                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15518                         }
15519
15520                         if (!found && IS_G4X(dev))
15521                                 intel_dp_init(dev, DP_B, PORT_B);
15522                 }
15523
15524                 /* Before G4X SDVOC doesn't have its own detect register */
15525
15526                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15527                         DRM_DEBUG_KMS("probing SDVOC\n");
15528                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15529                 }
15530
15531                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15532
15533                         if (IS_G4X(dev)) {
15534                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15535                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15536                         }
15537                         if (IS_G4X(dev))
15538                                 intel_dp_init(dev, DP_C, PORT_C);
15539                 }
15540
15541                 if (IS_G4X(dev) &&
15542                     (I915_READ(DP_D) & DP_DETECTED))
15543                         intel_dp_init(dev, DP_D, PORT_D);
15544         } else if (IS_GEN2(dev))
15545                 intel_dvo_init(dev);
15546
15547         if (SUPPORTS_TV(dev))
15548                 intel_tv_init(dev);
15549
15550         intel_psr_init(dev);
15551
15552         for_each_intel_encoder(dev, encoder) {
15553                 encoder->base.possible_crtcs = encoder->crtc_mask;
15554                 encoder->base.possible_clones =
15555                         intel_encoder_clones(encoder);
15556         }
15557
15558         intel_init_pch_refclk(dev);
15559
15560         drm_helper_move_panel_connectors_to_head(dev);
15561 }
15562
15563 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15564 {
15565         struct drm_device *dev = fb->dev;
15566         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15567
15568         drm_framebuffer_cleanup(fb);
15569         mutex_lock(&dev->struct_mutex);
15570         WARN_ON(!intel_fb->obj->framebuffer_references--);
15571         i915_gem_object_put(intel_fb->obj);
15572         mutex_unlock(&dev->struct_mutex);
15573         kfree(intel_fb);
15574 }
15575
15576 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15577                                                 struct drm_file *file,
15578                                                 unsigned int *handle)
15579 {
15580         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15581         struct drm_i915_gem_object *obj = intel_fb->obj;
15582
15583         if (obj->userptr.mm) {
15584                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15585                 return -EINVAL;
15586         }
15587
15588         return drm_gem_handle_create(file, &obj->base, handle);
15589 }
15590
15591 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15592                                         struct drm_file *file,
15593                                         unsigned flags, unsigned color,
15594                                         struct drm_clip_rect *clips,
15595                                         unsigned num_clips)
15596 {
15597         struct drm_device *dev = fb->dev;
15598         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15599         struct drm_i915_gem_object *obj = intel_fb->obj;
15600
15601         mutex_lock(&dev->struct_mutex);
15602         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15603         mutex_unlock(&dev->struct_mutex);
15604
15605         return 0;
15606 }
15607
15608 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15609         .destroy = intel_user_framebuffer_destroy,
15610         .create_handle = intel_user_framebuffer_create_handle,
15611         .dirty = intel_user_framebuffer_dirty,
15612 };
15613
15614 static
15615 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15616                          uint32_t pixel_format)
15617 {
15618         u32 gen = INTEL_INFO(dev)->gen;
15619
15620         if (gen >= 9) {
15621                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15622
15623                 /* "The stride in bytes must not exceed the of the size of 8K
15624                  *  pixels and 32K bytes."
15625                  */
15626                 return min(8192 * cpp, 32768);
15627         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15628                 return 32*1024;
15629         } else if (gen >= 4) {
15630                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15631                         return 16*1024;
15632                 else
15633                         return 32*1024;
15634         } else if (gen >= 3) {
15635                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15636                         return 8*1024;
15637                 else
15638                         return 16*1024;
15639         } else {
15640                 /* XXX DSPC is limited to 4k tiled */
15641                 return 8*1024;
15642         }
15643 }
15644
15645 static int intel_framebuffer_init(struct drm_device *dev,
15646                                   struct intel_framebuffer *intel_fb,
15647                                   struct drm_mode_fb_cmd2 *mode_cmd,
15648                                   struct drm_i915_gem_object *obj)
15649 {
15650         struct drm_i915_private *dev_priv = to_i915(dev);
15651         unsigned int tiling = i915_gem_object_get_tiling(obj);
15652         int ret;
15653         u32 pitch_limit, stride_alignment;
15654         char *format_name;
15655
15656         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15657
15658         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15659                 /*
15660                  * If there's a fence, enforce that
15661                  * the fb modifier and tiling mode match.
15662                  */
15663                 if (tiling != I915_TILING_NONE &&
15664                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15665                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15666                         return -EINVAL;
15667                 }
15668         } else {
15669                 if (tiling == I915_TILING_X) {
15670                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15671                 } else if (tiling == I915_TILING_Y) {
15672                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15673                         return -EINVAL;
15674                 }
15675         }
15676
15677         /* Passed in modifier sanity checking. */
15678         switch (mode_cmd->modifier[0]) {
15679         case I915_FORMAT_MOD_Y_TILED:
15680         case I915_FORMAT_MOD_Yf_TILED:
15681                 if (INTEL_INFO(dev)->gen < 9) {
15682                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15683                                   mode_cmd->modifier[0]);
15684                         return -EINVAL;
15685                 }
15686         case DRM_FORMAT_MOD_NONE:
15687         case I915_FORMAT_MOD_X_TILED:
15688                 break;
15689         default:
15690                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15691                           mode_cmd->modifier[0]);
15692                 return -EINVAL;
15693         }
15694
15695         /*
15696          * gen2/3 display engine uses the fence if present,
15697          * so the tiling mode must match the fb modifier exactly.
15698          */
15699         if (INTEL_INFO(dev_priv)->gen < 4 &&
15700             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15701                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15702                 return -EINVAL;
15703         }
15704
15705         stride_alignment = intel_fb_stride_alignment(dev_priv,
15706                                                      mode_cmd->modifier[0],
15707                                                      mode_cmd->pixel_format);
15708         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15709                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15710                           mode_cmd->pitches[0], stride_alignment);
15711                 return -EINVAL;
15712         }
15713
15714         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15715                                            mode_cmd->pixel_format);
15716         if (mode_cmd->pitches[0] > pitch_limit) {
15717                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15718                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15719                           "tiled" : "linear",
15720                           mode_cmd->pitches[0], pitch_limit);
15721                 return -EINVAL;
15722         }
15723
15724         /*
15725          * If there's a fence, enforce that
15726          * the fb pitch and fence stride match.
15727          */
15728         if (tiling != I915_TILING_NONE &&
15729             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15730                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15731                           mode_cmd->pitches[0],
15732                           i915_gem_object_get_stride(obj));
15733                 return -EINVAL;
15734         }
15735
15736         /* Reject formats not supported by any plane early. */
15737         switch (mode_cmd->pixel_format) {
15738         case DRM_FORMAT_C8:
15739         case DRM_FORMAT_RGB565:
15740         case DRM_FORMAT_XRGB8888:
15741         case DRM_FORMAT_ARGB8888:
15742                 break;
15743         case DRM_FORMAT_XRGB1555:
15744                 if (INTEL_INFO(dev)->gen > 3) {
15745                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15746                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15747                         kfree(format_name);
15748                         return -EINVAL;
15749                 }
15750                 break;
15751         case DRM_FORMAT_ABGR8888:
15752                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15753                     INTEL_INFO(dev)->gen < 9) {
15754                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15755                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15756                         kfree(format_name);
15757                         return -EINVAL;
15758                 }
15759                 break;
15760         case DRM_FORMAT_XBGR8888:
15761         case DRM_FORMAT_XRGB2101010:
15762         case DRM_FORMAT_XBGR2101010:
15763                 if (INTEL_INFO(dev)->gen < 4) {
15764                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15765                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15766                         kfree(format_name);
15767                         return -EINVAL;
15768                 }
15769                 break;
15770         case DRM_FORMAT_ABGR2101010:
15771                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15772                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15773                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15774                         kfree(format_name);
15775                         return -EINVAL;
15776                 }
15777                 break;
15778         case DRM_FORMAT_YUYV:
15779         case DRM_FORMAT_UYVY:
15780         case DRM_FORMAT_YVYU:
15781         case DRM_FORMAT_VYUY:
15782                 if (INTEL_INFO(dev)->gen < 5) {
15783                         format_name = drm_get_format_name(mode_cmd->pixel_format);
15784                         DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15785                         kfree(format_name);
15786                         return -EINVAL;
15787                 }
15788                 break;
15789         default:
15790                 format_name = drm_get_format_name(mode_cmd->pixel_format);
15791                 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15792                 kfree(format_name);
15793                 return -EINVAL;
15794         }
15795
15796         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15797         if (mode_cmd->offsets[0] != 0)
15798                 return -EINVAL;
15799
15800         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15801         intel_fb->obj = obj;
15802
15803         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15804         if (ret)
15805                 return ret;
15806
15807         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15808         if (ret) {
15809                 DRM_ERROR("framebuffer init failed %d\n", ret);
15810                 return ret;
15811         }
15812
15813         intel_fb->obj->framebuffer_references++;
15814
15815         return 0;
15816 }
15817
15818 static struct drm_framebuffer *
15819 intel_user_framebuffer_create(struct drm_device *dev,
15820                               struct drm_file *filp,
15821                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15822 {
15823         struct drm_framebuffer *fb;
15824         struct drm_i915_gem_object *obj;
15825         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15826
15827         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15828         if (!obj)
15829                 return ERR_PTR(-ENOENT);
15830
15831         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15832         if (IS_ERR(fb))
15833                 i915_gem_object_put_unlocked(obj);
15834
15835         return fb;
15836 }
15837
15838 #ifndef CONFIG_DRM_FBDEV_EMULATION
15839 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15840 {
15841 }
15842 #endif
15843
15844 static const struct drm_mode_config_funcs intel_mode_funcs = {
15845         .fb_create = intel_user_framebuffer_create,
15846         .output_poll_changed = intel_fbdev_output_poll_changed,
15847         .atomic_check = intel_atomic_check,
15848         .atomic_commit = intel_atomic_commit,
15849         .atomic_state_alloc = intel_atomic_state_alloc,
15850         .atomic_state_clear = intel_atomic_state_clear,
15851 };
15852
15853 /**
15854  * intel_init_display_hooks - initialize the display modesetting hooks
15855  * @dev_priv: device private
15856  */
15857 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15858 {
15859         if (INTEL_INFO(dev_priv)->gen >= 9) {
15860                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15861                 dev_priv->display.get_initial_plane_config =
15862                         skylake_get_initial_plane_config;
15863                 dev_priv->display.crtc_compute_clock =
15864                         haswell_crtc_compute_clock;
15865                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15866                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15867         } else if (HAS_DDI(dev_priv)) {
15868                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15869                 dev_priv->display.get_initial_plane_config =
15870                         ironlake_get_initial_plane_config;
15871                 dev_priv->display.crtc_compute_clock =
15872                         haswell_crtc_compute_clock;
15873                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15874                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15875         } else if (HAS_PCH_SPLIT(dev_priv)) {
15876                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15877                 dev_priv->display.get_initial_plane_config =
15878                         ironlake_get_initial_plane_config;
15879                 dev_priv->display.crtc_compute_clock =
15880                         ironlake_crtc_compute_clock;
15881                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15882                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15883         } else if (IS_CHERRYVIEW(dev_priv)) {
15884                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15885                 dev_priv->display.get_initial_plane_config =
15886                         i9xx_get_initial_plane_config;
15887                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15888                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15889                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15890         } else if (IS_VALLEYVIEW(dev_priv)) {
15891                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15892                 dev_priv->display.get_initial_plane_config =
15893                         i9xx_get_initial_plane_config;
15894                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15895                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15896                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15897         } else if (IS_G4X(dev_priv)) {
15898                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15899                 dev_priv->display.get_initial_plane_config =
15900                         i9xx_get_initial_plane_config;
15901                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15902                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15903                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15904         } else if (IS_PINEVIEW(dev_priv)) {
15905                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15906                 dev_priv->display.get_initial_plane_config =
15907                         i9xx_get_initial_plane_config;
15908                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15909                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15910                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15911         } else if (!IS_GEN2(dev_priv)) {
15912                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15913                 dev_priv->display.get_initial_plane_config =
15914                         i9xx_get_initial_plane_config;
15915                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15916                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15917                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15918         } else {
15919                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15920                 dev_priv->display.get_initial_plane_config =
15921                         i9xx_get_initial_plane_config;
15922                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15923                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15924                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15925         }
15926
15927         /* Returns the core display clock speed */
15928         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15929                 dev_priv->display.get_display_clock_speed =
15930                         skylake_get_display_clock_speed;
15931         else if (IS_BROXTON(dev_priv))
15932                 dev_priv->display.get_display_clock_speed =
15933                         broxton_get_display_clock_speed;
15934         else if (IS_BROADWELL(dev_priv))
15935                 dev_priv->display.get_display_clock_speed =
15936                         broadwell_get_display_clock_speed;
15937         else if (IS_HASWELL(dev_priv))
15938                 dev_priv->display.get_display_clock_speed =
15939                         haswell_get_display_clock_speed;
15940         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15941                 dev_priv->display.get_display_clock_speed =
15942                         valleyview_get_display_clock_speed;
15943         else if (IS_GEN5(dev_priv))
15944                 dev_priv->display.get_display_clock_speed =
15945                         ilk_get_display_clock_speed;
15946         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15947                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15948                 dev_priv->display.get_display_clock_speed =
15949                         i945_get_display_clock_speed;
15950         else if (IS_GM45(dev_priv))
15951                 dev_priv->display.get_display_clock_speed =
15952                         gm45_get_display_clock_speed;
15953         else if (IS_CRESTLINE(dev_priv))
15954                 dev_priv->display.get_display_clock_speed =
15955                         i965gm_get_display_clock_speed;
15956         else if (IS_PINEVIEW(dev_priv))
15957                 dev_priv->display.get_display_clock_speed =
15958                         pnv_get_display_clock_speed;
15959         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15960                 dev_priv->display.get_display_clock_speed =
15961                         g33_get_display_clock_speed;
15962         else if (IS_I915G(dev_priv))
15963                 dev_priv->display.get_display_clock_speed =
15964                         i915_get_display_clock_speed;
15965         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15966                 dev_priv->display.get_display_clock_speed =
15967                         i9xx_misc_get_display_clock_speed;
15968         else if (IS_I915GM(dev_priv))
15969                 dev_priv->display.get_display_clock_speed =
15970                         i915gm_get_display_clock_speed;
15971         else if (IS_I865G(dev_priv))
15972                 dev_priv->display.get_display_clock_speed =
15973                         i865_get_display_clock_speed;
15974         else if (IS_I85X(dev_priv))
15975                 dev_priv->display.get_display_clock_speed =
15976                         i85x_get_display_clock_speed;
15977         else { /* 830 */
15978                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15979                 dev_priv->display.get_display_clock_speed =
15980                         i830_get_display_clock_speed;
15981         }
15982
15983         if (IS_GEN5(dev_priv)) {
15984                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15985         } else if (IS_GEN6(dev_priv)) {
15986                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15987         } else if (IS_IVYBRIDGE(dev_priv)) {
15988                 /* FIXME: detect B0+ stepping and use auto training */
15989                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15990         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15991                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15992         }
15993
15994         if (IS_BROADWELL(dev_priv)) {
15995                 dev_priv->display.modeset_commit_cdclk =
15996                         broadwell_modeset_commit_cdclk;
15997                 dev_priv->display.modeset_calc_cdclk =
15998                         broadwell_modeset_calc_cdclk;
15999         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16000                 dev_priv->display.modeset_commit_cdclk =
16001                         valleyview_modeset_commit_cdclk;
16002                 dev_priv->display.modeset_calc_cdclk =
16003                         valleyview_modeset_calc_cdclk;
16004         } else if (IS_BROXTON(dev_priv)) {
16005                 dev_priv->display.modeset_commit_cdclk =
16006                         bxt_modeset_commit_cdclk;
16007                 dev_priv->display.modeset_calc_cdclk =
16008                         bxt_modeset_calc_cdclk;
16009         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16010                 dev_priv->display.modeset_commit_cdclk =
16011                         skl_modeset_commit_cdclk;
16012                 dev_priv->display.modeset_calc_cdclk =
16013                         skl_modeset_calc_cdclk;
16014         }
16015
16016         if (dev_priv->info.gen >= 9)
16017                 dev_priv->display.update_crtcs = skl_update_crtcs;
16018         else
16019                 dev_priv->display.update_crtcs = intel_update_crtcs;
16020
16021         switch (INTEL_INFO(dev_priv)->gen) {
16022         case 2:
16023                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16024                 break;
16025
16026         case 3:
16027                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16028                 break;
16029
16030         case 4:
16031         case 5:
16032                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16033                 break;
16034
16035         case 6:
16036                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16037                 break;
16038         case 7:
16039         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16040                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16041                 break;
16042         case 9:
16043                 /* Drop through - unsupported since execlist only. */
16044         default:
16045                 /* Default just returns -ENODEV to indicate unsupported */
16046                 dev_priv->display.queue_flip = intel_default_queue_flip;
16047         }
16048 }
16049
16050 /*
16051  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16052  * resume, or other times.  This quirk makes sure that's the case for
16053  * affected systems.
16054  */
16055 static void quirk_pipea_force(struct drm_device *dev)
16056 {
16057         struct drm_i915_private *dev_priv = to_i915(dev);
16058
16059         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16060         DRM_INFO("applying pipe a force quirk\n");
16061 }
16062
16063 static void quirk_pipeb_force(struct drm_device *dev)
16064 {
16065         struct drm_i915_private *dev_priv = to_i915(dev);
16066
16067         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16068         DRM_INFO("applying pipe b force quirk\n");
16069 }
16070
16071 /*
16072  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16073  */
16074 static void quirk_ssc_force_disable(struct drm_device *dev)
16075 {
16076         struct drm_i915_private *dev_priv = to_i915(dev);
16077         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16078         DRM_INFO("applying lvds SSC disable quirk\n");
16079 }
16080
16081 /*
16082  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16083  * brightness value
16084  */
16085 static void quirk_invert_brightness(struct drm_device *dev)
16086 {
16087         struct drm_i915_private *dev_priv = to_i915(dev);
16088         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16089         DRM_INFO("applying inverted panel brightness quirk\n");
16090 }
16091
16092 /* Some VBT's incorrectly indicate no backlight is present */
16093 static void quirk_backlight_present(struct drm_device *dev)
16094 {
16095         struct drm_i915_private *dev_priv = to_i915(dev);
16096         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16097         DRM_INFO("applying backlight present quirk\n");
16098 }
16099
16100 struct intel_quirk {
16101         int device;
16102         int subsystem_vendor;
16103         int subsystem_device;
16104         void (*hook)(struct drm_device *dev);
16105 };
16106
16107 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16108 struct intel_dmi_quirk {
16109         void (*hook)(struct drm_device *dev);
16110         const struct dmi_system_id (*dmi_id_list)[];
16111 };
16112
16113 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16114 {
16115         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16116         return 1;
16117 }
16118
16119 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16120         {
16121                 .dmi_id_list = &(const struct dmi_system_id[]) {
16122                         {
16123                                 .callback = intel_dmi_reverse_brightness,
16124                                 .ident = "NCR Corporation",
16125                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16126                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16127                                 },
16128                         },
16129                         { }  /* terminating entry */
16130                 },
16131                 .hook = quirk_invert_brightness,
16132         },
16133 };
16134
16135 static struct intel_quirk intel_quirks[] = {
16136         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16137         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16138
16139         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16140         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16141
16142         /* 830 needs to leave pipe A & dpll A up */
16143         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16144
16145         /* 830 needs to leave pipe B & dpll B up */
16146         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16147
16148         /* Lenovo U160 cannot use SSC on LVDS */
16149         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16150
16151         /* Sony Vaio Y cannot use SSC on LVDS */
16152         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16153
16154         /* Acer Aspire 5734Z must invert backlight brightness */
16155         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16156
16157         /* Acer/eMachines G725 */
16158         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16159
16160         /* Acer/eMachines e725 */
16161         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16162
16163         /* Acer/Packard Bell NCL20 */
16164         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16165
16166         /* Acer Aspire 4736Z */
16167         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16168
16169         /* Acer Aspire 5336 */
16170         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16171
16172         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16173         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16174
16175         /* Acer C720 Chromebook (Core i3 4005U) */
16176         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16177
16178         /* Apple Macbook 2,1 (Core 2 T7400) */
16179         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16180
16181         /* Apple Macbook 4,1 */
16182         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16183
16184         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16185         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16186
16187         /* HP Chromebook 14 (Celeron 2955U) */
16188         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16189
16190         /* Dell Chromebook 11 */
16191         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16192
16193         /* Dell Chromebook 11 (2015 version) */
16194         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16195 };
16196
16197 static void intel_init_quirks(struct drm_device *dev)
16198 {
16199         struct pci_dev *d = dev->pdev;
16200         int i;
16201
16202         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16203                 struct intel_quirk *q = &intel_quirks[i];
16204
16205                 if (d->device == q->device &&
16206                     (d->subsystem_vendor == q->subsystem_vendor ||
16207                      q->subsystem_vendor == PCI_ANY_ID) &&
16208                     (d->subsystem_device == q->subsystem_device ||
16209                      q->subsystem_device == PCI_ANY_ID))
16210                         q->hook(dev);
16211         }
16212         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16213                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16214                         intel_dmi_quirks[i].hook(dev);
16215         }
16216 }
16217
16218 /* Disable the VGA plane that we never use */
16219 static void i915_disable_vga(struct drm_device *dev)
16220 {
16221         struct drm_i915_private *dev_priv = to_i915(dev);
16222         struct pci_dev *pdev = dev_priv->drm.pdev;
16223         u8 sr1;
16224         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16225
16226         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16227         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16228         outb(SR01, VGA_SR_INDEX);
16229         sr1 = inb(VGA_SR_DATA);
16230         outb(sr1 | 1<<5, VGA_SR_DATA);
16231         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16232         udelay(300);
16233
16234         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16235         POSTING_READ(vga_reg);
16236 }
16237
16238 void intel_modeset_init_hw(struct drm_device *dev)
16239 {
16240         struct drm_i915_private *dev_priv = to_i915(dev);
16241
16242         intel_update_cdclk(dev);
16243
16244         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16245
16246         intel_init_clock_gating(dev);
16247 }
16248
16249 /*
16250  * Calculate what we think the watermarks should be for the state we've read
16251  * out of the hardware and then immediately program those watermarks so that
16252  * we ensure the hardware settings match our internal state.
16253  *
16254  * We can calculate what we think WM's should be by creating a duplicate of the
16255  * current state (which was constructed during hardware readout) and running it
16256  * through the atomic check code to calculate new watermark values in the
16257  * state object.
16258  */
16259 static void sanitize_watermarks(struct drm_device *dev)
16260 {
16261         struct drm_i915_private *dev_priv = to_i915(dev);
16262         struct drm_atomic_state *state;
16263         struct drm_crtc *crtc;
16264         struct drm_crtc_state *cstate;
16265         struct drm_modeset_acquire_ctx ctx;
16266         int ret;
16267         int i;
16268
16269         /* Only supported on platforms that use atomic watermark design */
16270         if (!dev_priv->display.optimize_watermarks)
16271                 return;
16272
16273         /*
16274          * We need to hold connection_mutex before calling duplicate_state so
16275          * that the connector loop is protected.
16276          */
16277         drm_modeset_acquire_init(&ctx, 0);
16278 retry:
16279         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16280         if (ret == -EDEADLK) {
16281                 drm_modeset_backoff(&ctx);
16282                 goto retry;
16283         } else if (WARN_ON(ret)) {
16284                 goto fail;
16285         }
16286
16287         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16288         if (WARN_ON(IS_ERR(state)))
16289                 goto fail;
16290
16291         /*
16292          * Hardware readout is the only time we don't want to calculate
16293          * intermediate watermarks (since we don't trust the current
16294          * watermarks).
16295          */
16296         to_intel_atomic_state(state)->skip_intermediate_wm = true;
16297
16298         ret = intel_atomic_check(dev, state);
16299         if (ret) {
16300                 /*
16301                  * If we fail here, it means that the hardware appears to be
16302                  * programmed in a way that shouldn't be possible, given our
16303                  * understanding of watermark requirements.  This might mean a
16304                  * mistake in the hardware readout code or a mistake in the
16305                  * watermark calculations for a given platform.  Raise a WARN
16306                  * so that this is noticeable.
16307                  *
16308                  * If this actually happens, we'll have to just leave the
16309                  * BIOS-programmed watermarks untouched and hope for the best.
16310                  */
16311                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16312                 goto put_state;
16313         }
16314
16315         /* Write calculated watermark values back */
16316         for_each_crtc_in_state(state, crtc, cstate, i) {
16317                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16318
16319                 cs->wm.need_postvbl_update = true;
16320                 dev_priv->display.optimize_watermarks(cs);
16321         }
16322
16323 put_state:
16324         drm_atomic_state_put(state);
16325 fail:
16326         drm_modeset_drop_locks(&ctx);
16327         drm_modeset_acquire_fini(&ctx);
16328 }
16329
16330 void intel_modeset_init(struct drm_device *dev)
16331 {
16332         struct drm_i915_private *dev_priv = to_i915(dev);
16333         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16334         int sprite, ret;
16335         enum pipe pipe;
16336         struct intel_crtc *crtc;
16337
16338         drm_mode_config_init(dev);
16339
16340         dev->mode_config.min_width = 0;
16341         dev->mode_config.min_height = 0;
16342
16343         dev->mode_config.preferred_depth = 24;
16344         dev->mode_config.prefer_shadow = 1;
16345
16346         dev->mode_config.allow_fb_modifiers = true;
16347
16348         dev->mode_config.funcs = &intel_mode_funcs;
16349
16350         intel_init_quirks(dev);
16351
16352         intel_init_pm(dev);
16353
16354         if (INTEL_INFO(dev)->num_pipes == 0)
16355                 return;
16356
16357         /*
16358          * There may be no VBT; and if the BIOS enabled SSC we can
16359          * just keep using it to avoid unnecessary flicker.  Whereas if the
16360          * BIOS isn't using it, don't assume it will work even if the VBT
16361          * indicates as much.
16362          */
16363         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16364                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16365                                             DREF_SSC1_ENABLE);
16366
16367                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16368                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16369                                      bios_lvds_use_ssc ? "en" : "dis",
16370                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16371                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16372                 }
16373         }
16374
16375         if (IS_GEN2(dev)) {
16376                 dev->mode_config.max_width = 2048;
16377                 dev->mode_config.max_height = 2048;
16378         } else if (IS_GEN3(dev)) {
16379                 dev->mode_config.max_width = 4096;
16380                 dev->mode_config.max_height = 4096;
16381         } else {
16382                 dev->mode_config.max_width = 8192;
16383                 dev->mode_config.max_height = 8192;
16384         }
16385
16386         if (IS_845G(dev) || IS_I865G(dev)) {
16387                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16388                 dev->mode_config.cursor_height = 1023;
16389         } else if (IS_GEN2(dev)) {
16390                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16391                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16392         } else {
16393                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16394                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16395         }
16396
16397         dev->mode_config.fb_base = ggtt->mappable_base;
16398
16399         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16400                       INTEL_INFO(dev)->num_pipes,
16401                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16402
16403         for_each_pipe(dev_priv, pipe) {
16404                 intel_crtc_init(dev, pipe);
16405                 for_each_sprite(dev_priv, pipe, sprite) {
16406                         ret = intel_plane_init(dev, pipe, sprite);
16407                         if (ret)
16408                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16409                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
16410                 }
16411         }
16412
16413         intel_update_czclk(dev_priv);
16414         intel_update_cdclk(dev);
16415
16416         intel_shared_dpll_init(dev);
16417
16418         if (dev_priv->max_cdclk_freq == 0)
16419                 intel_update_max_cdclk(dev);
16420
16421         /* Just disable it once at startup */
16422         i915_disable_vga(dev);
16423         intel_setup_outputs(dev);
16424
16425         drm_modeset_lock_all(dev);
16426         intel_modeset_setup_hw_state(dev);
16427         drm_modeset_unlock_all(dev);
16428
16429         for_each_intel_crtc(dev, crtc) {
16430                 struct intel_initial_plane_config plane_config = {};
16431
16432                 if (!crtc->active)
16433                         continue;
16434
16435                 /*
16436                  * Note that reserving the BIOS fb up front prevents us
16437                  * from stuffing other stolen allocations like the ring
16438                  * on top.  This prevents some ugliness at boot time, and
16439                  * can even allow for smooth boot transitions if the BIOS
16440                  * fb is large enough for the active pipe configuration.
16441                  */
16442                 dev_priv->display.get_initial_plane_config(crtc,
16443                                                            &plane_config);
16444
16445                 /*
16446                  * If the fb is shared between multiple heads, we'll
16447                  * just get the first one.
16448                  */
16449                 intel_find_initial_plane_obj(crtc, &plane_config);
16450         }
16451
16452         /*
16453          * Make sure hardware watermarks really match the state we read out.
16454          * Note that we need to do this after reconstructing the BIOS fb's
16455          * since the watermark calculation done here will use pstate->fb.
16456          */
16457         sanitize_watermarks(dev);
16458 }
16459
16460 static void intel_enable_pipe_a(struct drm_device *dev)
16461 {
16462         struct intel_connector *connector;
16463         struct drm_connector *crt = NULL;
16464         struct intel_load_detect_pipe load_detect_temp;
16465         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16466
16467         /* We can't just switch on the pipe A, we need to set things up with a
16468          * proper mode and output configuration. As a gross hack, enable pipe A
16469          * by enabling the load detect pipe once. */
16470         for_each_intel_connector(dev, connector) {
16471                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16472                         crt = &connector->base;
16473                         break;
16474                 }
16475         }
16476
16477         if (!crt)
16478                 return;
16479
16480         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16481                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16482 }
16483
16484 static bool
16485 intel_check_plane_mapping(struct intel_crtc *crtc)
16486 {
16487         struct drm_device *dev = crtc->base.dev;
16488         struct drm_i915_private *dev_priv = to_i915(dev);
16489         u32 val;
16490
16491         if (INTEL_INFO(dev)->num_pipes == 1)
16492                 return true;
16493
16494         val = I915_READ(DSPCNTR(!crtc->plane));
16495
16496         if ((val & DISPLAY_PLANE_ENABLE) &&
16497             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16498                 return false;
16499
16500         return true;
16501 }
16502
16503 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16504 {
16505         struct drm_device *dev = crtc->base.dev;
16506         struct intel_encoder *encoder;
16507
16508         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16509                 return true;
16510
16511         return false;
16512 }
16513
16514 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16515 {
16516         struct drm_device *dev = encoder->base.dev;
16517         struct intel_connector *connector;
16518
16519         for_each_connector_on_encoder(dev, &encoder->base, connector)
16520                 return connector;
16521
16522         return NULL;
16523 }
16524
16525 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16526                               enum transcoder pch_transcoder)
16527 {
16528         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16529                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16530 }
16531
16532 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16533 {
16534         struct drm_device *dev = crtc->base.dev;
16535         struct drm_i915_private *dev_priv = to_i915(dev);
16536         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16537
16538         /* Clear any frame start delays used for debugging left by the BIOS */
16539         if (!transcoder_is_dsi(cpu_transcoder)) {
16540                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16541
16542                 I915_WRITE(reg,
16543                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16544         }
16545
16546         /* restore vblank interrupts to correct state */
16547         drm_crtc_vblank_reset(&crtc->base);
16548         if (crtc->active) {
16549                 struct intel_plane *plane;
16550
16551                 drm_crtc_vblank_on(&crtc->base);
16552
16553                 /* Disable everything but the primary plane */
16554                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16555                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16556                                 continue;
16557
16558                         plane->disable_plane(&plane->base, &crtc->base);
16559                 }
16560         }
16561
16562         /* We need to sanitize the plane -> pipe mapping first because this will
16563          * disable the crtc (and hence change the state) if it is wrong. Note
16564          * that gen4+ has a fixed plane -> pipe mapping.  */
16565         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16566                 bool plane;
16567
16568                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16569                               crtc->base.base.id, crtc->base.name);
16570
16571                 /* Pipe has the wrong plane attached and the plane is active.
16572                  * Temporarily change the plane mapping and disable everything
16573                  * ...  */
16574                 plane = crtc->plane;
16575                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16576                 crtc->plane = !plane;
16577                 intel_crtc_disable_noatomic(&crtc->base);
16578                 crtc->plane = plane;
16579         }
16580
16581         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16582             crtc->pipe == PIPE_A && !crtc->active) {
16583                 /* BIOS forgot to enable pipe A, this mostly happens after
16584                  * resume. Force-enable the pipe to fix this, the update_dpms
16585                  * call below we restore the pipe to the right state, but leave
16586                  * the required bits on. */
16587                 intel_enable_pipe_a(dev);
16588         }
16589
16590         /* Adjust the state of the output pipe according to whether we
16591          * have active connectors/encoders. */
16592         if (crtc->active && !intel_crtc_has_encoders(crtc))
16593                 intel_crtc_disable_noatomic(&crtc->base);
16594
16595         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16596                 /*
16597                  * We start out with underrun reporting disabled to avoid races.
16598                  * For correct bookkeeping mark this on active crtcs.
16599                  *
16600                  * Also on gmch platforms we dont have any hardware bits to
16601                  * disable the underrun reporting. Which means we need to start
16602                  * out with underrun reporting disabled also on inactive pipes,
16603                  * since otherwise we'll complain about the garbage we read when
16604                  * e.g. coming up after runtime pm.
16605                  *
16606                  * No protection against concurrent access is required - at
16607                  * worst a fifo underrun happens which also sets this to false.
16608                  */
16609                 crtc->cpu_fifo_underrun_disabled = true;
16610                 /*
16611                  * We track the PCH trancoder underrun reporting state
16612                  * within the crtc. With crtc for pipe A housing the underrun
16613                  * reporting state for PCH transcoder A, crtc for pipe B housing
16614                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16615                  * and marking underrun reporting as disabled for the non-existing
16616                  * PCH transcoders B and C would prevent enabling the south
16617                  * error interrupt (see cpt_can_enable_serr_int()).
16618                  */
16619                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16620                         crtc->pch_fifo_underrun_disabled = true;
16621         }
16622 }
16623
16624 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16625 {
16626         struct intel_connector *connector;
16627
16628         /* We need to check both for a crtc link (meaning that the
16629          * encoder is active and trying to read from a pipe) and the
16630          * pipe itself being active. */
16631         bool has_active_crtc = encoder->base.crtc &&
16632                 to_intel_crtc(encoder->base.crtc)->active;
16633
16634         connector = intel_encoder_find_connector(encoder);
16635         if (connector && !has_active_crtc) {
16636                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16637                               encoder->base.base.id,
16638                               encoder->base.name);
16639
16640                 /* Connector is active, but has no active pipe. This is
16641                  * fallout from our resume register restoring. Disable
16642                  * the encoder manually again. */
16643                 if (encoder->base.crtc) {
16644                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16645
16646                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16647                                       encoder->base.base.id,
16648                                       encoder->base.name);
16649                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16650                         if (encoder->post_disable)
16651                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16652                 }
16653                 encoder->base.crtc = NULL;
16654
16655                 /* Inconsistent output/port/pipe state happens presumably due to
16656                  * a bug in one of the get_hw_state functions. Or someplace else
16657                  * in our code, like the register restore mess on resume. Clamp
16658                  * things to off as a safer default. */
16659
16660                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16661                 connector->base.encoder = NULL;
16662         }
16663         /* Enabled encoders without active connectors will be fixed in
16664          * the crtc fixup. */
16665 }
16666
16667 void i915_redisable_vga_power_on(struct drm_device *dev)
16668 {
16669         struct drm_i915_private *dev_priv = to_i915(dev);
16670         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16671
16672         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16673                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16674                 i915_disable_vga(dev);
16675         }
16676 }
16677
16678 void i915_redisable_vga(struct drm_device *dev)
16679 {
16680         struct drm_i915_private *dev_priv = to_i915(dev);
16681
16682         /* This function can be called both from intel_modeset_setup_hw_state or
16683          * at a very early point in our resume sequence, where the power well
16684          * structures are not yet restored. Since this function is at a very
16685          * paranoid "someone might have enabled VGA while we were not looking"
16686          * level, just check if the power well is enabled instead of trying to
16687          * follow the "don't touch the power well if we don't need it" policy
16688          * the rest of the driver uses. */
16689         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16690                 return;
16691
16692         i915_redisable_vga_power_on(dev);
16693
16694         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16695 }
16696
16697 static bool primary_get_hw_state(struct intel_plane *plane)
16698 {
16699         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16700
16701         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16702 }
16703
16704 /* FIXME read out full plane state for all planes */
16705 static void readout_plane_state(struct intel_crtc *crtc)
16706 {
16707         struct drm_plane *primary = crtc->base.primary;
16708         struct intel_plane_state *plane_state =
16709                 to_intel_plane_state(primary->state);
16710
16711         plane_state->base.visible = crtc->active &&
16712                 primary_get_hw_state(to_intel_plane(primary));
16713
16714         if (plane_state->base.visible)
16715                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16716 }
16717
16718 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16719 {
16720         struct drm_i915_private *dev_priv = to_i915(dev);
16721         enum pipe pipe;
16722         struct intel_crtc *crtc;
16723         struct intel_encoder *encoder;
16724         struct intel_connector *connector;
16725         int i;
16726
16727         dev_priv->active_crtcs = 0;
16728
16729         for_each_intel_crtc(dev, crtc) {
16730                 struct intel_crtc_state *crtc_state = crtc->config;
16731                 int pixclk = 0;
16732
16733                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16734                 memset(crtc_state, 0, sizeof(*crtc_state));
16735                 crtc_state->base.crtc = &crtc->base;
16736
16737                 crtc_state->base.active = crtc_state->base.enable =
16738                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16739
16740                 crtc->base.enabled = crtc_state->base.enable;
16741                 crtc->active = crtc_state->base.active;
16742
16743                 if (crtc_state->base.active) {
16744                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16745
16746                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16747                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16748                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16749                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16750                         else
16751                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16752
16753                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16754                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16755                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16756                 }
16757
16758                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16759
16760                 readout_plane_state(crtc);
16761
16762                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16763                               crtc->base.base.id, crtc->base.name,
16764                               crtc->active ? "enabled" : "disabled");
16765         }
16766
16767         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16768                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16769
16770                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16771                                                   &pll->config.hw_state);
16772                 pll->config.crtc_mask = 0;
16773                 for_each_intel_crtc(dev, crtc) {
16774                         if (crtc->active && crtc->config->shared_dpll == pll)
16775                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16776                 }
16777                 pll->active_mask = pll->config.crtc_mask;
16778
16779                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16780                               pll->name, pll->config.crtc_mask, pll->on);
16781         }
16782
16783         for_each_intel_encoder(dev, encoder) {
16784                 pipe = 0;
16785
16786                 if (encoder->get_hw_state(encoder, &pipe)) {
16787                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16788                         encoder->base.crtc = &crtc->base;
16789                         crtc->config->output_types |= 1 << encoder->type;
16790                         encoder->get_config(encoder, crtc->config);
16791                 } else {
16792                         encoder->base.crtc = NULL;
16793                 }
16794
16795                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16796                               encoder->base.base.id,
16797                               encoder->base.name,
16798                               encoder->base.crtc ? "enabled" : "disabled",
16799                               pipe_name(pipe));
16800         }
16801
16802         for_each_intel_connector(dev, connector) {
16803                 if (connector->get_hw_state(connector)) {
16804                         connector->base.dpms = DRM_MODE_DPMS_ON;
16805
16806                         encoder = connector->encoder;
16807                         connector->base.encoder = &encoder->base;
16808
16809                         if (encoder->base.crtc &&
16810                             encoder->base.crtc->state->active) {
16811                                 /*
16812                                  * This has to be done during hardware readout
16813                                  * because anything calling .crtc_disable may
16814                                  * rely on the connector_mask being accurate.
16815                                  */
16816                                 encoder->base.crtc->state->connector_mask |=
16817                                         1 << drm_connector_index(&connector->base);
16818                                 encoder->base.crtc->state->encoder_mask |=
16819                                         1 << drm_encoder_index(&encoder->base);
16820                         }
16821
16822                 } else {
16823                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16824                         connector->base.encoder = NULL;
16825                 }
16826                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16827                               connector->base.base.id,
16828                               connector->base.name,
16829                               connector->base.encoder ? "enabled" : "disabled");
16830         }
16831
16832         for_each_intel_crtc(dev, crtc) {
16833                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16834
16835                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16836                 if (crtc->base.state->active) {
16837                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16838                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16839                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16840
16841                         /*
16842                          * The initial mode needs to be set in order to keep
16843                          * the atomic core happy. It wants a valid mode if the
16844                          * crtc's enabled, so we do the above call.
16845                          *
16846                          * At this point some state updated by the connectors
16847                          * in their ->detect() callback has not run yet, so
16848                          * no recalculation can be done yet.
16849                          *
16850                          * Even if we could do a recalculation and modeset
16851                          * right now it would cause a double modeset if
16852                          * fbdev or userspace chooses a different initial mode.
16853                          *
16854                          * If that happens, someone indicated they wanted a
16855                          * mode change, which means it's safe to do a full
16856                          * recalculation.
16857                          */
16858                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16859
16860                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16861                         update_scanline_offset(crtc);
16862                 }
16863
16864                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16865         }
16866 }
16867
16868 /* Scan out the current hw modeset state,
16869  * and sanitizes it to the current state
16870  */
16871 static void
16872 intel_modeset_setup_hw_state(struct drm_device *dev)
16873 {
16874         struct drm_i915_private *dev_priv = to_i915(dev);
16875         enum pipe pipe;
16876         struct intel_crtc *crtc;
16877         struct intel_encoder *encoder;
16878         int i;
16879
16880         intel_modeset_readout_hw_state(dev);
16881
16882         /* HW state is read out, now we need to sanitize this mess. */
16883         for_each_intel_encoder(dev, encoder) {
16884                 intel_sanitize_encoder(encoder);
16885         }
16886
16887         for_each_pipe(dev_priv, pipe) {
16888                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16889                 intel_sanitize_crtc(crtc);
16890                 intel_dump_pipe_config(crtc, crtc->config,
16891                                        "[setup_hw_state]");
16892         }
16893
16894         intel_modeset_update_connector_atomic_state(dev);
16895
16896         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16897                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16898
16899                 if (!pll->on || pll->active_mask)
16900                         continue;
16901
16902                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16903
16904                 pll->funcs.disable(dev_priv, pll);
16905                 pll->on = false;
16906         }
16907
16908         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16909                 vlv_wm_get_hw_state(dev);
16910         else if (IS_GEN9(dev))
16911                 skl_wm_get_hw_state(dev);
16912         else if (HAS_PCH_SPLIT(dev))
16913                 ilk_wm_get_hw_state(dev);
16914
16915         for_each_intel_crtc(dev, crtc) {
16916                 unsigned long put_domains;
16917
16918                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16919                 if (WARN_ON(put_domains))
16920                         modeset_put_power_domains(dev_priv, put_domains);
16921         }
16922         intel_display_set_init_power(dev_priv, false);
16923
16924         intel_fbc_init_pipe_state(dev_priv);
16925 }
16926
16927 void intel_display_resume(struct drm_device *dev)
16928 {
16929         struct drm_i915_private *dev_priv = to_i915(dev);
16930         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16931         struct drm_modeset_acquire_ctx ctx;
16932         int ret;
16933
16934         dev_priv->modeset_restore_state = NULL;
16935         if (state)
16936                 state->acquire_ctx = &ctx;
16937
16938         /*
16939          * This is a cludge because with real atomic modeset mode_config.mutex
16940          * won't be taken. Unfortunately some probed state like
16941          * audio_codec_enable is still protected by mode_config.mutex, so lock
16942          * it here for now.
16943          */
16944         mutex_lock(&dev->mode_config.mutex);
16945         drm_modeset_acquire_init(&ctx, 0);
16946
16947         while (1) {
16948                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16949                 if (ret != -EDEADLK)
16950                         break;
16951
16952                 drm_modeset_backoff(&ctx);
16953         }
16954
16955         if (!ret)
16956                 ret = __intel_display_resume(dev, state);
16957
16958         drm_modeset_drop_locks(&ctx);
16959         drm_modeset_acquire_fini(&ctx);
16960         mutex_unlock(&dev->mode_config.mutex);
16961
16962         if (ret)
16963                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16964         drm_atomic_state_put(state);
16965 }
16966
16967 void intel_modeset_gem_init(struct drm_device *dev)
16968 {
16969         struct drm_i915_private *dev_priv = to_i915(dev);
16970         struct drm_crtc *c;
16971         struct drm_i915_gem_object *obj;
16972
16973         intel_init_gt_powersave(dev_priv);
16974
16975         intel_modeset_init_hw(dev);
16976
16977         intel_setup_overlay(dev_priv);
16978
16979         /*
16980          * Make sure any fbs we allocated at startup are properly
16981          * pinned & fenced.  When we do the allocation it's too early
16982          * for this.
16983          */
16984         for_each_crtc(dev, c) {
16985                 struct i915_vma *vma;
16986
16987                 obj = intel_fb_obj(c->primary->fb);
16988                 if (obj == NULL)
16989                         continue;
16990
16991                 mutex_lock(&dev->struct_mutex);
16992                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
16993                                                  c->primary->state->rotation);
16994                 mutex_unlock(&dev->struct_mutex);
16995                 if (IS_ERR(vma)) {
16996                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16997                                   to_intel_crtc(c)->pipe);
16998                         drm_framebuffer_unreference(c->primary->fb);
16999                         c->primary->fb = NULL;
17000                         c->primary->crtc = c->primary->state->crtc = NULL;
17001                         update_state_fb(c->primary);
17002                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17003                 }
17004         }
17005 }
17006
17007 int intel_connector_register(struct drm_connector *connector)
17008 {
17009         struct intel_connector *intel_connector = to_intel_connector(connector);
17010         int ret;
17011
17012         ret = intel_backlight_device_register(intel_connector);
17013         if (ret)
17014                 goto err;
17015
17016         return 0;
17017
17018 err:
17019         return ret;
17020 }
17021
17022 void intel_connector_unregister(struct drm_connector *connector)
17023 {
17024         struct intel_connector *intel_connector = to_intel_connector(connector);
17025
17026         intel_backlight_device_unregister(intel_connector);
17027         intel_panel_destroy_backlight(connector);
17028 }
17029
17030 void intel_modeset_cleanup(struct drm_device *dev)
17031 {
17032         struct drm_i915_private *dev_priv = to_i915(dev);
17033
17034         intel_disable_gt_powersave(dev_priv);
17035
17036         /*
17037          * Interrupts and polling as the first thing to avoid creating havoc.
17038          * Too much stuff here (turning of connectors, ...) would
17039          * experience fancy races otherwise.
17040          */
17041         intel_irq_uninstall(dev_priv);
17042
17043         /*
17044          * Due to the hpd irq storm handling the hotplug work can re-arm the
17045          * poll handlers. Hence disable polling after hpd handling is shut down.
17046          */
17047         drm_kms_helper_poll_fini(dev);
17048
17049         intel_unregister_dsm_handler();
17050
17051         intel_fbc_global_disable(dev_priv);
17052
17053         /* flush any delayed tasks or pending work */
17054         flush_scheduled_work();
17055
17056         drm_mode_config_cleanup(dev);
17057
17058         intel_cleanup_overlay(dev_priv);
17059
17060         intel_cleanup_gt_powersave(dev_priv);
17061
17062         intel_teardown_gmbus(dev);
17063 }
17064
17065 void intel_connector_attach_encoder(struct intel_connector *connector,
17066                                     struct intel_encoder *encoder)
17067 {
17068         connector->encoder = encoder;
17069         drm_mode_connector_attach_encoder(&connector->base,
17070                                           &encoder->base);
17071 }
17072
17073 /*
17074  * set vga decode state - true == enable VGA decode
17075  */
17076 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17077 {
17078         struct drm_i915_private *dev_priv = to_i915(dev);
17079         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17080         u16 gmch_ctrl;
17081
17082         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17083                 DRM_ERROR("failed to read control word\n");
17084                 return -EIO;
17085         }
17086
17087         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17088                 return 0;
17089
17090         if (state)
17091                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17092         else
17093                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17094
17095         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17096                 DRM_ERROR("failed to write control word\n");
17097                 return -EIO;
17098         }
17099
17100         return 0;
17101 }
17102
17103 struct intel_display_error_state {
17104
17105         u32 power_well_driver;
17106
17107         int num_transcoders;
17108
17109         struct intel_cursor_error_state {
17110                 u32 control;
17111                 u32 position;
17112                 u32 base;
17113                 u32 size;
17114         } cursor[I915_MAX_PIPES];
17115
17116         struct intel_pipe_error_state {
17117                 bool power_domain_on;
17118                 u32 source;
17119                 u32 stat;
17120         } pipe[I915_MAX_PIPES];
17121
17122         struct intel_plane_error_state {
17123                 u32 control;
17124                 u32 stride;
17125                 u32 size;
17126                 u32 pos;
17127                 u32 addr;
17128                 u32 surface;
17129                 u32 tile_offset;
17130         } plane[I915_MAX_PIPES];
17131
17132         struct intel_transcoder_error_state {
17133                 bool power_domain_on;
17134                 enum transcoder cpu_transcoder;
17135
17136                 u32 conf;
17137
17138                 u32 htotal;
17139                 u32 hblank;
17140                 u32 hsync;
17141                 u32 vtotal;
17142                 u32 vblank;
17143                 u32 vsync;
17144         } transcoder[4];
17145 };
17146
17147 struct intel_display_error_state *
17148 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17149 {
17150         struct intel_display_error_state *error;
17151         int transcoders[] = {
17152                 TRANSCODER_A,
17153                 TRANSCODER_B,
17154                 TRANSCODER_C,
17155                 TRANSCODER_EDP,
17156         };
17157         int i;
17158
17159         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17160                 return NULL;
17161
17162         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17163         if (error == NULL)
17164                 return NULL;
17165
17166         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17167                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17168
17169         for_each_pipe(dev_priv, i) {
17170                 error->pipe[i].power_domain_on =
17171                         __intel_display_power_is_enabled(dev_priv,
17172                                                          POWER_DOMAIN_PIPE(i));
17173                 if (!error->pipe[i].power_domain_on)
17174                         continue;
17175
17176                 error->cursor[i].control = I915_READ(CURCNTR(i));
17177                 error->cursor[i].position = I915_READ(CURPOS(i));
17178                 error->cursor[i].base = I915_READ(CURBASE(i));
17179
17180                 error->plane[i].control = I915_READ(DSPCNTR(i));
17181                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17182                 if (INTEL_GEN(dev_priv) <= 3) {
17183                         error->plane[i].size = I915_READ(DSPSIZE(i));
17184                         error->plane[i].pos = I915_READ(DSPPOS(i));
17185                 }
17186                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17187                         error->plane[i].addr = I915_READ(DSPADDR(i));
17188                 if (INTEL_GEN(dev_priv) >= 4) {
17189                         error->plane[i].surface = I915_READ(DSPSURF(i));
17190                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17191                 }
17192
17193                 error->pipe[i].source = I915_READ(PIPESRC(i));
17194
17195                 if (HAS_GMCH_DISPLAY(dev_priv))
17196                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17197         }
17198
17199         /* Note: this does not include DSI transcoders. */
17200         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17201         if (HAS_DDI(dev_priv))
17202                 error->num_transcoders++; /* Account for eDP. */
17203
17204         for (i = 0; i < error->num_transcoders; i++) {
17205                 enum transcoder cpu_transcoder = transcoders[i];
17206
17207                 error->transcoder[i].power_domain_on =
17208                         __intel_display_power_is_enabled(dev_priv,
17209                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17210                 if (!error->transcoder[i].power_domain_on)
17211                         continue;
17212
17213                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17214
17215                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17216                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17217                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17218                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17219                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17220                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17221                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17222         }
17223
17224         return error;
17225 }
17226
17227 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17228
17229 void
17230 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17231                                 struct drm_device *dev,
17232                                 struct intel_display_error_state *error)
17233 {
17234         struct drm_i915_private *dev_priv = to_i915(dev);
17235         int i;
17236
17237         if (!error)
17238                 return;
17239
17240         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17241         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17242                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17243                            error->power_well_driver);
17244         for_each_pipe(dev_priv, i) {
17245                 err_printf(m, "Pipe [%d]:\n", i);
17246                 err_printf(m, "  Power: %s\n",
17247                            onoff(error->pipe[i].power_domain_on));
17248                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17249                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17250
17251                 err_printf(m, "Plane [%d]:\n", i);
17252                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17253                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17254                 if (INTEL_INFO(dev)->gen <= 3) {
17255                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17256                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17257                 }
17258                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17259                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17260                 if (INTEL_INFO(dev)->gen >= 4) {
17261                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17262                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17263                 }
17264
17265                 err_printf(m, "Cursor [%d]:\n", i);
17266                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17267                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17268                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17269         }
17270
17271         for (i = 0; i < error->num_transcoders; i++) {
17272                 err_printf(m, "CPU transcoder: %s\n",
17273                            transcoder_name(error->transcoder[i].cpu_transcoder));
17274                 err_printf(m, "  Power: %s\n",
17275                            onoff(error->transcoder[i].power_domain_on));
17276                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17277                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17278                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17279                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17280                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17281                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17282                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17283         }
17284 }