2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 static bool is_mmio_work(struct intel_flip_work *work)
54 return work->mmio_work.func;
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
75 static const uint32_t skl_primary_formats[] = {
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
91 static const uint32_t intel_cursor_formats[] = {
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
100 static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
132 } dot, vco, n, m, m1, m2, p, p1;
136 int p2_slow, p2_fast;
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
151 return vco_freq[hpll_freq] * 1000;
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
164 divider = val & CCK_FREQUENCY_VALUES;
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
213 case CLKCFG_FSB_1067:
215 case CLKCFG_FSB_1333:
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
235 return; /* no rawclk on other platforms, or no need to know it */
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
413 /* Ironlake / Sandybridge
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
484 static const struct intel_limit intel_limits_vlv = {
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
500 static const struct intel_limit intel_limits_chv = {
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
529 needs_modeset(struct drm_crtc_state *state)
531 return drm_atomic_crtc_needs_modeset(state);
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
581 return clock->dot / 5;
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 return clock->dot / 5;
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
603 static bool intel_PLL_is_valid(struct drm_device *dev,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
621 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
629 INTELPllInvalid("vco out of range\n");
630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
634 INTELPllInvalid("dot out of range\n");
640 i9xx_select_p2_div(const struct intel_limit *limit,
641 const struct intel_crtc_state *crtc_state,
644 struct drm_device *dev = crtc_state->base.crtc->dev;
646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648 * For LVDS just rely on its current settings for dual-channel.
649 * We haven't figured out how to reliably set up different
650 * single/dual channel state, if we even can.
652 if (intel_is_dual_link_lvds(dev))
653 return limit->p2.p2_fast;
655 return limit->p2.p2_slow;
657 if (target < limit->p2.dot_limit)
658 return limit->p2.p2_slow;
660 return limit->p2.p2_fast;
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669 * Target and reference clocks are specified in kHz.
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
675 i9xx_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
680 struct drm_device *dev = crtc_state->base.crtc->dev;
684 memset(best_clock, 0, sizeof(*best_clock));
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 if (clock.m2 >= clock.m1)
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
700 i9xx_calc_dpll_params(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
705 clock.p != match_clock->p)
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
718 return (err != target);
722 * Returns a set of divisors for the desired target clock with the given
723 * refclk, or FALSE. The returned values represent the clock equation:
724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
726 * Target and reference clocks are specified in kHz.
728 * If match_clock is provided, then best_clock P divider must match the P
729 * divider from @match_clock used for LVDS downclocking.
732 pnv_find_best_dpll(const struct intel_limit *limit,
733 struct intel_crtc_state *crtc_state,
734 int target, int refclk, struct dpll *match_clock,
735 struct dpll *best_clock)
737 struct drm_device *dev = crtc_state->base.crtc->dev;
741 memset(best_clock, 0, sizeof(*best_clock));
743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
747 for (clock.m2 = limit->m2.min;
748 clock.m2 <= limit->m2.max; clock.m2++) {
749 for (clock.n = limit->n.min;
750 clock.n <= limit->n.max; clock.n++) {
751 for (clock.p1 = limit->p1.min;
752 clock.p1 <= limit->p1.max; clock.p1++) {
755 pnv_calc_dpll_params(refclk, &clock);
756 if (!intel_PLL_is_valid(dev, limit,
760 clock.p != match_clock->p)
763 this_err = abs(clock.dot - target);
764 if (this_err < err) {
773 return (err != target);
777 * Returns a set of divisors for the desired target clock with the given
778 * refclk, or FALSE. The returned values represent the clock equation:
779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
781 * Target and reference clocks are specified in kHz.
783 * If match_clock is provided, then best_clock P divider must match the P
784 * divider from @match_clock used for LVDS downclocking.
787 g4x_find_best_dpll(const struct intel_limit *limit,
788 struct intel_crtc_state *crtc_state,
789 int target, int refclk, struct dpll *match_clock,
790 struct dpll *best_clock)
792 struct drm_device *dev = crtc_state->base.crtc->dev;
796 /* approximately equals target * 0.00585 */
797 int err_most = (target >> 8) + (target >> 9);
799 memset(best_clock, 0, sizeof(*best_clock));
801 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
803 max_n = limit->n.max;
804 /* based on hardware requirement, prefer smaller n to precision */
805 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
806 /* based on hardware requirement, prefere larger m1,m2 */
807 for (clock.m1 = limit->m1.max;
808 clock.m1 >= limit->m1.min; clock.m1--) {
809 for (clock.m2 = limit->m2.max;
810 clock.m2 >= limit->m2.min; clock.m2--) {
811 for (clock.p1 = limit->p1.max;
812 clock.p1 >= limit->p1.min; clock.p1--) {
815 i9xx_calc_dpll_params(refclk, &clock);
816 if (!intel_PLL_is_valid(dev, limit,
820 this_err = abs(clock.dot - target);
821 if (this_err < err_most) {
835 * Check if the calculated PLL configuration is more optimal compared to the
836 * best configuration and error found so far. Return the calculated error.
838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
839 const struct dpll *calculated_clock,
840 const struct dpll *best_clock,
841 unsigned int best_error_ppm,
842 unsigned int *error_ppm)
845 * For CHV ignore the error and consider only the P value.
846 * Prefer a bigger P value based on HW requirements.
848 if (IS_CHERRYVIEW(dev)) {
851 return calculated_clock->p > best_clock->p;
854 if (WARN_ON_ONCE(!target_freq))
857 *error_ppm = div_u64(1000000ULL *
858 abs(target_freq - calculated_clock->dot),
861 * Prefer a better P value over a better (smaller) error if the error
862 * is small. Ensure this preference for future configurations too by
863 * setting the error to 0.
865 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
871 return *error_ppm + 10 < best_error_ppm;
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
880 vlv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
888 unsigned int bestppm = 1000000;
889 /* min update 19.2 MHz */
890 int max_n = min(limit->n.max, refclk / 19200);
893 target *= 5; /* fast clock */
895 memset(best_clock, 0, sizeof(*best_clock));
897 /* based on hardware requirement, prefer smaller n to precision */
898 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
899 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
900 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
901 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
902 clock.p = clock.p1 * clock.p2;
903 /* based on hardware requirement, prefer bigger m1,m2 values */
904 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
907 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
910 vlv_calc_dpll_params(refclk, &clock);
912 if (!intel_PLL_is_valid(dev, limit,
916 if (!vlv_PLL_is_optimal(dev, target,
934 * Returns a set of divisors for the desired target clock with the given
935 * refclk, or FALSE. The returned values represent the clock equation:
936 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
939 chv_find_best_dpll(const struct intel_limit *limit,
940 struct intel_crtc_state *crtc_state,
941 int target, int refclk, struct dpll *match_clock,
942 struct dpll *best_clock)
944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
945 struct drm_device *dev = crtc->base.dev;
946 unsigned int best_error_ppm;
951 memset(best_clock, 0, sizeof(*best_clock));
952 best_error_ppm = 1000000;
955 * Based on hardware doc, the n always set to 1, and m1 always
956 * set to 2. If requires to support 200Mhz refclk, we need to
957 * revisit this because n may not 1 anymore.
959 clock.n = 1, clock.m1 = 2;
960 target *= 5; /* fast clock */
962 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963 for (clock.p2 = limit->p2.p2_fast;
964 clock.p2 >= limit->p2.p2_slow;
965 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
966 unsigned int error_ppm;
968 clock.p = clock.p1 * clock.p2;
970 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971 clock.n) << 22, refclk * clock.m1);
973 if (m2 > INT_MAX/clock.m1)
978 chv_calc_dpll_params(refclk, &clock);
980 if (!intel_PLL_is_valid(dev, limit, &clock))
983 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984 best_error_ppm, &error_ppm))
988 best_error_ppm = error_ppm;
996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
997 struct dpll *best_clock)
1000 const struct intel_limit *limit = &intel_limits_bxt;
1002 return chv_find_best_dpll(limit, crtc_state,
1003 target_clock, refclk, NULL, best_clock);
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1010 /* Be paranoid as we can arrive here with only partial
1011 * state retrieved from the hardware during setup.
1013 * We can ditch the adjusted_mode.crtc_clock check as soon
1014 * as Haswell has gained clock readout/fastboot support.
1016 * We can ditch the crtc->primary->fb check as soon as we can
1017 * properly reconstruct framebuffers.
1019 * FIXME: The intel_crtc->active here should be switched to
1020 * crtc->state->active once we have proper CRTC states wired up
1023 return intel_crtc->active && crtc->primary->state->fb &&
1024 intel_crtc->config->base.adjusted_mode.crtc_clock;
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1033 return intel_crtc->config->cpu_transcoder;
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1038 struct drm_i915_private *dev_priv = to_i915(dev);
1039 i915_reg_t reg = PIPEDSL(pipe);
1044 line_mask = DSL_LINEMASK_GEN2;
1046 line_mask = DSL_LINEMASK_GEN3;
1048 line1 = I915_READ(reg) & line_mask;
1050 line2 = I915_READ(reg) & line_mask;
1052 return line1 == line2;
1056 * intel_wait_for_pipe_off - wait for pipe to turn off
1057 * @crtc: crtc whose pipe to wait for
1059 * After disabling a pipe, we can't wait for vblank in the usual way,
1060 * spinning on the vblank interrupt status bit, since we won't actually
1061 * see an interrupt when the pipe is disabled.
1063 * On Gen4 and above:
1064 * wait for the pipe register state bit to turn off
1067 * wait for the display line value to settle (it usually
1068 * ends up stopping at the start of the next frame).
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 struct drm_device *dev = crtc->base.dev;
1074 struct drm_i915_private *dev_priv = to_i915(dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1078 if (INTEL_INFO(dev)->gen >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1085 WARN(1, "pipe_off wait timed out\n");
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 struct drm_device *dev = &dev_priv->drm;
1196 enum pipe panel_pipe = PIPE_A;
1199 if (WARN_ON(HAS_DDI(dev)))
1202 if (HAS_PCH_SPLIT(dev)) {
1205 pp_reg = PP_CONTROL(0);
1206 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1208 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211 /* XXX: else fix for eDP */
1212 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213 /* presumably write lock depends on pipe, not port select */
1214 pp_reg = PP_CONTROL(pipe);
1217 pp_reg = PP_CONTROL(0);
1218 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219 panel_pipe = PIPE_B;
1222 val = I915_READ(pp_reg);
1223 if (!(val & PANEL_POWER_ON) ||
1224 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1227 I915_STATE_WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1235 struct drm_device *dev = &dev_priv->drm;
1238 if (IS_845G(dev) || IS_I865G(dev))
1239 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1241 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1243 I915_STATE_WARN(cur_state != state,
1244 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe), onoff(state), onoff(cur_state));
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe, bool state)
1254 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1256 enum intel_display_power_domain power_domain;
1258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1263 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266 cur_state = !!(val & PIPECONF_ENABLE);
1268 intel_display_power_put(dev_priv, power_domain);
1273 I915_STATE_WARN(cur_state != state,
1274 "pipe %c assertion failure (expected %s, current %s)\n",
1275 pipe_name(pipe), onoff(state), onoff(cur_state));
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279 enum plane plane, bool state)
1284 val = I915_READ(DSPCNTR(plane));
1285 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286 I915_STATE_WARN(cur_state != state,
1287 "plane %c assertion failure (expected %s, current %s)\n",
1288 plane_name(plane), onoff(state), onoff(cur_state));
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1297 struct drm_device *dev = &dev_priv->drm;
1300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
1302 u32 val = I915_READ(DSPCNTR(pipe));
1303 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304 "plane %c assertion failure, should be disabled but not\n",
1309 /* Need to check both planes against the pipe */
1310 for_each_pipe(dev_priv, i) {
1311 u32 val = I915_READ(DSPCNTR(i));
1312 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313 DISPPLANE_SEL_PIPE_SHIFT;
1314 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316 plane_name(i), pipe_name(pipe));
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1323 struct drm_device *dev = &dev_priv->drm;
1326 if (INTEL_INFO(dev)->gen >= 9) {
1327 for_each_sprite(dev_priv, pipe, sprite) {
1328 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331 sprite, pipe_name(pipe));
1333 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334 for_each_sprite(dev_priv, pipe, sprite) {
1335 u32 val = I915_READ(SPCNTR(pipe, sprite));
1336 I915_STATE_WARN(val & SP_ENABLE,
1337 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338 sprite_name(pipe, sprite), pipe_name(pipe));
1340 } else if (INTEL_INFO(dev)->gen >= 7) {
1341 u32 val = I915_READ(SPRCTL(pipe));
1342 I915_STATE_WARN(val & SPRITE_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 } else if (INTEL_INFO(dev)->gen >= 5) {
1346 u32 val = I915_READ(DVSCNTR(pipe));
1347 I915_STATE_WARN(val & DVS_ENABLE,
1348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1355 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356 drm_crtc_vblank_put(crtc);
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1365 val = I915_READ(PCH_TRANSCONF(pipe));
1366 enabled = !!(val & TRANS_ENABLE);
1367 I915_STATE_WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1375 if ((val & DP_PORT_EN) == 0)
1378 if (HAS_PCH_CPT(dev_priv)) {
1379 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1382 } else if (IS_CHERRYVIEW(dev_priv)) {
1383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1395 if ((val & SDVO_ENABLE) == 0)
1398 if (HAS_PCH_CPT(dev_priv)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1401 } else if (IS_CHERRYVIEW(dev_priv)) {
1402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1414 if ((val & LVDS_PORT_EN) == 0)
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1432 if (HAS_PCH_CPT(dev_priv)) {
1433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, i915_reg_t reg,
1446 u32 val = I915_READ(reg);
1447 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 i915_mmio_reg_offset(reg), pipe_name(pipe));
1451 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, i915_reg_t reg)
1459 u32 val = I915_READ(reg);
1460 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 i915_mmio_reg_offset(reg), pipe_name(pipe));
1464 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1478 val = I915_READ(PCH_ADPA);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1483 val = I915_READ(PCH_LVDS);
1484 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *pipe_config)
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1499 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500 POSTING_READ(DPLL(pipe));
1503 if (intel_wait_for_register(dev_priv,
1508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *pipe_config)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 enum pipe pipe = crtc->pipe;
1517 assert_pipe_disabled(dev_priv, pipe);
1519 /* PLL is protected by panel, make sure we can write it */
1520 assert_panel_unlocked(dev_priv, pipe);
1522 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523 _vlv_enable_pll(crtc, pipe_config);
1525 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526 POSTING_READ(DPLL_MD(pipe));
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
1533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534 enum pipe pipe = crtc->pipe;
1535 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1538 mutex_lock(&dev_priv->sb_lock);
1540 /* Enable back the 10bit clock to display controller */
1541 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542 tmp |= DPIO_DCLKP_EN;
1543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1545 mutex_unlock(&dev_priv->sb_lock);
1548 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1553 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1555 /* Check PLL is locked */
1556 if (intel_wait_for_register(dev_priv,
1557 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1559 DRM_ERROR("PLL %d failed to lock\n", pipe);
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563 const struct intel_crtc_state *pipe_config)
1565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566 enum pipe pipe = crtc->pipe;
1568 assert_pipe_disabled(dev_priv, pipe);
1570 /* PLL is protected by panel, make sure we can write it */
1571 assert_panel_unlocked(dev_priv, pipe);
1573 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574 _chv_enable_pll(crtc, pipe_config);
1576 if (pipe != PIPE_A) {
1578 * WaPixelRepeatModeFixForC0:chv
1580 * DPLLCMD is AWOL. Use chicken bits to propagate
1581 * the value from DPLLBMD to either pipe B or C.
1583 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585 I915_WRITE(CBR4_VLV, 0);
1586 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1589 * DPLLB VGA mode also seems to cause problems.
1590 * We should always have it disabled.
1592 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1594 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595 POSTING_READ(DPLL_MD(pipe));
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1601 struct intel_crtc *crtc;
1604 for_each_intel_crtc(dev, crtc) {
1605 count += crtc->base.state->active &&
1606 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = to_i915(dev);
1616 i915_reg_t reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config->dpll_hw_state.dpll;
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1625 /* Enable DVO 2x clock on both PLLs if necessary */
1626 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1628 * It appears to be important that we don't enable this
1629 * for the current pipe before otherwise configuring the
1630 * PLL. No idea how this should be handled if multiple
1631 * DVO outputs are enabled simultaneosly.
1633 dpll |= DPLL_DVO_2X_MODE;
1634 I915_WRITE(DPLL(!crtc->pipe),
1635 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1639 * Apparently we need to have VGA mode enabled prior to changing
1640 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641 * dividers, even though the register value does change.
1645 I915_WRITE(reg, dpll);
1647 /* Wait for the clocks to stabilize. */
1651 if (INTEL_INFO(dev)->gen >= 4) {
1652 I915_WRITE(DPLL_MD(crtc->pipe),
1653 crtc->config->dpll_hw_state.dpll_md);
1655 /* The pixel multiplier can only be updated once the
1656 * DPLL is enabled and the clocks are stable.
1658 * So write it again.
1660 I915_WRITE(reg, dpll);
1663 /* We do this three times for luck */
1664 I915_WRITE(reg, dpll);
1666 udelay(150); /* wait for warmup */
1667 I915_WRITE(reg, dpll);
1669 udelay(150); /* wait for warmup */
1670 I915_WRITE(reg, dpll);
1672 udelay(150); /* wait for warmup */
1676 * i9xx_disable_pll - disable a PLL
1677 * @dev_priv: i915 private structure
1678 * @pipe: pipe PLL to disable
1680 * Disable the PLL for @pipe, making sure the pipe is off first.
1682 * Note! This is for pre-ILK only.
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1686 struct drm_device *dev = crtc->base.dev;
1687 struct drm_i915_private *dev_priv = to_i915(dev);
1688 enum pipe pipe = crtc->pipe;
1690 /* Disable DVO 2x clock on both PLLs if necessary */
1692 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693 !intel_num_dvo_pipes(dev)) {
1694 I915_WRITE(DPLL(PIPE_B),
1695 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696 I915_WRITE(DPLL(PIPE_A),
1697 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1700 /* Don't disable pipe or pipe PLLs if needed */
1701 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1705 /* Make sure the pipe isn't still relying on us */
1706 assert_pipe_disabled(dev_priv, pipe);
1708 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709 POSTING_READ(DPLL(pipe));
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1719 val = DPLL_INTEGRATED_REF_CLK_VLV |
1720 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1730 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
1736 val = DPLL_SSC_REF_CLK_CHV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
1744 mutex_lock(&dev_priv->sb_lock);
1746 /* Disable 10bit clock to display controller */
1747 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748 val &= ~DPIO_DCLKP_EN;
1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1751 mutex_unlock(&dev_priv->sb_lock);
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755 struct intel_digital_port *dport,
1756 unsigned int expected_mask)
1759 i915_reg_t dpll_reg;
1761 switch (dport->port) {
1763 port_mask = DPLL_PORTB_READY_MASK;
1767 port_mask = DPLL_PORTC_READY_MASK;
1769 expected_mask <<= 4;
1772 port_mask = DPLL_PORTD_READY_MASK;
1773 dpll_reg = DPIO_PHY_STATUS;
1779 if (intel_wait_for_register(dev_priv,
1780 dpll_reg, port_mask, expected_mask,
1782 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789 struct drm_device *dev = &dev_priv->drm;
1790 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1793 uint32_t val, pipeconf_val;
1795 /* Make sure PCH DPLL is enabled */
1796 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1798 /* FDI must be feeding us bits for PCH ports */
1799 assert_fdi_tx_enabled(dev_priv, pipe);
1800 assert_fdi_rx_enabled(dev_priv, pipe);
1802 if (HAS_PCH_CPT(dev)) {
1803 /* Workaround: Set the timing override bit before enabling the
1804 * pch transcoder. */
1805 reg = TRANS_CHICKEN2(pipe);
1806 val = I915_READ(reg);
1807 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808 I915_WRITE(reg, val);
1811 reg = PCH_TRANSCONF(pipe);
1812 val = I915_READ(reg);
1813 pipeconf_val = I915_READ(PIPECONF(pipe));
1815 if (HAS_PCH_IBX(dev_priv)) {
1817 * Make the BPC in transcoder be consistent with
1818 * that in pipeconf reg. For HDMI we must use 8bpc
1819 * here for both 8bpc and 12bpc.
1821 val &= ~PIPECONF_BPC_MASK;
1822 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823 val |= PIPECONF_8BPC;
1825 val |= pipeconf_val & PIPECONF_BPC_MASK;
1828 val &= ~TRANS_INTERLACE_MASK;
1829 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830 if (HAS_PCH_IBX(dev_priv) &&
1831 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832 val |= TRANS_LEGACY_INTERLACED_ILK;
1834 val |= TRANS_INTERLACED;
1836 val |= TRANS_PROGRESSIVE;
1838 I915_WRITE(reg, val | TRANS_ENABLE);
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1842 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846 enum transcoder cpu_transcoder)
1848 u32 val, pipeconf_val;
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1854 /* Workaround: set timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1860 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1862 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863 PIPECONF_INTERLACED_ILK)
1864 val |= TRANS_INTERLACED;
1866 val |= TRANS_PROGRESSIVE;
1868 I915_WRITE(LPT_TRANSCONF, val);
1869 if (intel_wait_for_register(dev_priv,
1874 DRM_ERROR("Failed to enable PCH transcoder\n");
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1880 struct drm_device *dev = &dev_priv->drm;
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1891 reg = PCH_TRANSCONF(pipe);
1892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
1896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1901 if (HAS_PCH_CPT(dev)) {
1902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1910 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1914 val = I915_READ(LPT_TRANSCONF);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(LPT_TRANSCONF, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1921 DRM_ERROR("Failed to disable PCH transcoder\n");
1923 /* Workaround: clear timing override bit. */
1924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1930 * intel_enable_pipe - enable a pipe, asserting requirements
1931 * @crtc: crtc responsible for the pipe
1933 * Enable @crtc's pipe, making sure that various hardware specific requirements
1934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1938 struct drm_device *dev = crtc->base.dev;
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 enum pipe pipe = crtc->pipe;
1941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942 enum pipe pch_transcoder;
1946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1948 assert_planes_disabled(dev_priv, pipe);
1949 assert_cursor_disabled(dev_priv, pipe);
1950 assert_sprites_disabled(dev_priv, pipe);
1952 if (HAS_PCH_LPT(dev_priv))
1953 pch_transcoder = TRANSCODER_A;
1955 pch_transcoder = pipe;
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1962 if (HAS_GMCH_DISPLAY(dev_priv)) {
1963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964 assert_dsi_pll_enabled(dev_priv);
1966 assert_pll_enabled(dev_priv, pipe);
1968 if (crtc->config->has_pch_encoder) {
1969 /* if driving the PCH, we need FDI enabled */
1970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
1974 /* FIXME: assert CPU port conditions for SNB+ */
1977 reg = PIPECONF(cpu_transcoder);
1978 val = I915_READ(reg);
1979 if (val & PIPECONF_ENABLE) {
1980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2001 * intel_disable_pipe - disable a pipe, asserting requirements
2002 * @crtc: crtc whose pipes is to be disabled
2004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
2008 * Will wait until the pipe has shut down before returning.
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014 enum pipe pipe = crtc->pipe;
2018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if ((val & PIPECONF_ENABLE) == 0)
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2037 if (crtc->config->double_wide)
2038 val &= ~PIPECONF_DOUBLE_WIDE;
2040 /* Don't disable pipe or pipe PLLs if needed */
2041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043 val &= ~PIPECONF_ENABLE;
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2071 case I915_FORMAT_MOD_Yf_TILED:
2087 MISSING_CASE(fb_modifier);
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
2095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2098 return intel_tile_size(dev_priv) /
2099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118 uint32_t pixel_format, uint64_t fb_modifier)
2120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2123 return ALIGN(height, tile_height);
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2128 unsigned int size = 0;
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
2142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2146 *view = i915_ggtt_view_normal;
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2152 if (INTEL_INFO(dev_priv)->gen >= 9)
2154 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2157 else if (INTEL_INFO(dev_priv)->gen >= 4)
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164 uint64_t fb_modifier)
2166 switch (fb_modifier) {
2167 case DRM_FORMAT_MOD_NONE:
2168 return intel_linear_alignment(dev_priv);
2169 case I915_FORMAT_MOD_X_TILED:
2170 if (INTEL_INFO(dev_priv)->gen >= 9)
2173 case I915_FORMAT_MOD_Y_TILED:
2174 case I915_FORMAT_MOD_Yf_TILED:
2175 return 1 * 1024 * 1024;
2177 MISSING_CASE(fb_modifier);
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2184 unsigned int rotation)
2186 struct drm_device *dev = fb->dev;
2187 struct drm_i915_private *dev_priv = to_i915(dev);
2188 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2189 struct i915_ggtt_view view;
2193 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2195 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2197 intel_fill_fb_ggtt_view(&view, fb, rotation);
2199 /* Note that the w/a also requires 64 PTE of padding following the
2200 * bo. We currently fill all unused PTE with the shadow page and so
2201 * we should always have valid PTE following the scanout preventing
2204 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2205 alignment = 256 * 1024;
2208 * Global gtt pte registers are special registers which actually forward
2209 * writes to a chunk of system memory. Which means that there is no risk
2210 * that the register values disappear as soon as we call
2211 * intel_runtime_pm_put(), so it is correct to wrap only the
2212 * pin/unpin/fence and not more.
2214 intel_runtime_pm_get(dev_priv);
2216 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2221 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2222 * fence, whereas 965+ only requires a fence if using
2223 * framebuffer compression. For simplicity, we always install
2224 * a fence as the cost is not that onerous.
2226 if (view.type == I915_GGTT_VIEW_NORMAL) {
2227 ret = i915_gem_object_get_fence(obj);
2228 if (ret == -EDEADLK) {
2230 * -EDEADLK means there are no free fences
2233 * This is propagated to atomic, but it uses
2234 * -EDEADLK to force a locking recovery, so
2235 * change the returned error to -EBUSY.
2242 i915_gem_object_pin_fence(obj);
2245 intel_runtime_pm_put(dev_priv);
2249 i915_gem_object_unpin_from_display_plane(obj, &view);
2251 intel_runtime_pm_put(dev_priv);
2255 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2257 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2258 struct i915_ggtt_view view;
2260 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2262 intel_fill_fb_ggtt_view(&view, fb, rotation);
2264 if (view.type == I915_GGTT_VIEW_NORMAL)
2265 i915_gem_object_unpin_fence(obj);
2267 i915_gem_object_unpin_from_display_plane(obj, &view);
2270 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2271 unsigned int rotation)
2273 if (intel_rotation_90_or_270(rotation))
2274 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2276 return fb->pitches[plane];
2280 * Convert the x/y offsets into a linear offset.
2281 * Only valid with 0/180 degree rotation, which is fine since linear
2282 * offset is only used with linear buffers on pre-hsw and tiled buffers
2283 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2285 u32 intel_fb_xy_to_linear(int x, int y,
2286 const struct intel_plane_state *state,
2289 const struct drm_framebuffer *fb = state->base.fb;
2290 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2291 unsigned int pitch = fb->pitches[plane];
2293 return y * pitch + x * cpp;
2297 * Add the x/y offsets derived from fb->offsets[] to the user
2298 * specified plane src x/y offsets. The resulting x/y offsets
2299 * specify the start of scanout from the beginning of the gtt mapping.
2301 void intel_add_fb_offsets(int *x, int *y,
2302 const struct intel_plane_state *state,
2306 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2307 unsigned int rotation = state->base.rotation;
2309 if (intel_rotation_90_or_270(rotation)) {
2310 *x += intel_fb->rotated[plane].x;
2311 *y += intel_fb->rotated[plane].y;
2313 *x += intel_fb->normal[plane].x;
2314 *y += intel_fb->normal[plane].y;
2319 * Input tile dimensions and pitch must already be
2320 * rotated to match x and y, and in pixel units.
2322 static u32 _intel_adjust_tile_offset(int *x, int *y,
2323 unsigned int tile_width,
2324 unsigned int tile_height,
2325 unsigned int tile_size,
2326 unsigned int pitch_tiles,
2330 unsigned int pitch_pixels = pitch_tiles * tile_width;
2333 WARN_ON(old_offset & (tile_size - 1));
2334 WARN_ON(new_offset & (tile_size - 1));
2335 WARN_ON(new_offset > old_offset);
2337 tiles = (old_offset - new_offset) / tile_size;
2339 *y += tiles / pitch_tiles * tile_height;
2340 *x += tiles % pitch_tiles * tile_width;
2342 /* minimize x in case it got needlessly big */
2343 *y += *x / pitch_pixels * tile_height;
2350 * Adjust the tile offset by moving the difference into
2353 static u32 intel_adjust_tile_offset(int *x, int *y,
2354 const struct intel_plane_state *state, int plane,
2355 u32 old_offset, u32 new_offset)
2357 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2358 const struct drm_framebuffer *fb = state->base.fb;
2359 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2360 unsigned int rotation = state->base.rotation;
2361 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2363 WARN_ON(new_offset > old_offset);
2365 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2366 unsigned int tile_size, tile_width, tile_height;
2367 unsigned int pitch_tiles;
2369 tile_size = intel_tile_size(dev_priv);
2370 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2371 fb->modifier[plane], cpp);
2373 if (intel_rotation_90_or_270(rotation)) {
2374 pitch_tiles = pitch / tile_height;
2375 swap(tile_width, tile_height);
2377 pitch_tiles = pitch / (tile_width * cpp);
2380 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2381 tile_size, pitch_tiles,
2382 old_offset, new_offset);
2384 old_offset += *y * pitch + *x * cpp;
2386 *y = (old_offset - new_offset) / pitch;
2387 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2394 * Computes the linear offset to the base tile and adjusts
2395 * x, y. bytes per pixel is assumed to be a power-of-two.
2397 * In the 90/270 rotated case, x and y are assumed
2398 * to be already rotated to match the rotated GTT view, and
2399 * pitch is the tile_height aligned framebuffer height.
2401 * This function is used when computing the derived information
2402 * under intel_framebuffer, so using any of that information
2403 * here is not allowed. Anything under drm_framebuffer can be
2404 * used. This is why the user has to pass in the pitch since it
2405 * is specified in the rotated orientation.
2407 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2409 const struct drm_framebuffer *fb, int plane,
2411 unsigned int rotation,
2414 uint64_t fb_modifier = fb->modifier[plane];
2415 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2416 u32 offset, offset_aligned;
2421 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2422 unsigned int tile_size, tile_width, tile_height;
2423 unsigned int tile_rows, tiles, pitch_tiles;
2425 tile_size = intel_tile_size(dev_priv);
2426 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2429 if (intel_rotation_90_or_270(rotation)) {
2430 pitch_tiles = pitch / tile_height;
2431 swap(tile_width, tile_height);
2433 pitch_tiles = pitch / (tile_width * cpp);
2436 tile_rows = *y / tile_height;
2439 tiles = *x / tile_width;
2442 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2443 offset_aligned = offset & ~alignment;
2445 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2446 tile_size, pitch_tiles,
2447 offset, offset_aligned);
2449 offset = *y * pitch + *x * cpp;
2450 offset_aligned = offset & ~alignment;
2452 *y = (offset & alignment) / pitch;
2453 *x = ((offset & alignment) - *y * pitch) / cpp;
2456 return offset_aligned;
2459 u32 intel_compute_tile_offset(int *x, int *y,
2460 const struct intel_plane_state *state,
2463 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2464 const struct drm_framebuffer *fb = state->base.fb;
2465 unsigned int rotation = state->base.rotation;
2466 int pitch = intel_fb_pitch(fb, plane, rotation);
2469 /* AUX_DIST needs only 4K alignment */
2470 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2473 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2475 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2476 rotation, alignment);
2479 /* Convert the fb->offset[] linear offset into x/y offsets */
2480 static void intel_fb_offset_to_xy(int *x, int *y,
2481 const struct drm_framebuffer *fb, int plane)
2483 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2484 unsigned int pitch = fb->pitches[plane];
2485 u32 linear_offset = fb->offsets[plane];
2487 *y = linear_offset / pitch;
2488 *x = linear_offset % pitch / cpp;
2491 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2493 switch (fb_modifier) {
2494 case I915_FORMAT_MOD_X_TILED:
2495 return I915_TILING_X;
2496 case I915_FORMAT_MOD_Y_TILED:
2497 return I915_TILING_Y;
2499 return I915_TILING_NONE;
2504 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2505 struct drm_framebuffer *fb)
2507 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2508 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2509 u32 gtt_offset_rotated = 0;
2510 unsigned int max_size = 0;
2511 uint32_t format = fb->pixel_format;
2512 int i, num_planes = drm_format_num_planes(format);
2513 unsigned int tile_size = intel_tile_size(dev_priv);
2515 for (i = 0; i < num_planes; i++) {
2516 unsigned int width, height;
2517 unsigned int cpp, size;
2521 cpp = drm_format_plane_cpp(format, i);
2522 width = drm_format_plane_width(fb->width, format, i);
2523 height = drm_format_plane_height(fb->height, format, i);
2525 intel_fb_offset_to_xy(&x, &y, fb, i);
2528 * The fence (if used) is aligned to the start of the object
2529 * so having the framebuffer wrap around across the edge of the
2530 * fenced region doesn't really work. We have no API to configure
2531 * the fence start offset within the object (nor could we probably
2532 * on gen2/3). So it's just easier if we just require that the
2533 * fb layout agrees with the fence layout. We already check that the
2534 * fb stride matches the fence stride elsewhere.
2536 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2537 (x + width) * cpp > fb->pitches[i]) {
2538 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2544 * First pixel of the framebuffer from
2545 * the start of the normal gtt mapping.
2547 intel_fb->normal[i].x = x;
2548 intel_fb->normal[i].y = y;
2550 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2551 fb, 0, fb->pitches[i],
2552 BIT(DRM_ROTATE_0), tile_size);
2553 offset /= tile_size;
2555 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2556 unsigned int tile_width, tile_height;
2557 unsigned int pitch_tiles;
2560 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2561 fb->modifier[i], cpp);
2563 rot_info->plane[i].offset = offset;
2564 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2565 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2566 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2568 intel_fb->rotated[i].pitch =
2569 rot_info->plane[i].height * tile_height;
2571 /* how many tiles does this plane need */
2572 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2574 * If the plane isn't horizontally tile aligned,
2575 * we need one more tile.
2580 /* rotate the x/y offsets to match the GTT view */
2586 rot_info->plane[i].width * tile_width,
2587 rot_info->plane[i].height * tile_height,
2588 BIT(DRM_ROTATE_270));
2592 /* rotate the tile dimensions to match the GTT view */
2593 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2594 swap(tile_width, tile_height);
2597 * We only keep the x/y offsets, so push all of the
2598 * gtt offset into the x/y offsets.
2600 _intel_adjust_tile_offset(&x, &y, tile_size,
2601 tile_width, tile_height, pitch_tiles,
2602 gtt_offset_rotated * tile_size, 0);
2604 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2607 * First pixel of the framebuffer from
2608 * the start of the rotated gtt mapping.
2610 intel_fb->rotated[i].x = x;
2611 intel_fb->rotated[i].y = y;
2613 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2614 x * cpp, tile_size);
2617 /* how many tiles in total needed in the bo */
2618 max_size = max(max_size, offset + size);
2621 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2622 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2623 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2630 static int i9xx_format_to_fourcc(int format)
2633 case DISPPLANE_8BPP:
2634 return DRM_FORMAT_C8;
2635 case DISPPLANE_BGRX555:
2636 return DRM_FORMAT_XRGB1555;
2637 case DISPPLANE_BGRX565:
2638 return DRM_FORMAT_RGB565;
2640 case DISPPLANE_BGRX888:
2641 return DRM_FORMAT_XRGB8888;
2642 case DISPPLANE_RGBX888:
2643 return DRM_FORMAT_XBGR8888;
2644 case DISPPLANE_BGRX101010:
2645 return DRM_FORMAT_XRGB2101010;
2646 case DISPPLANE_RGBX101010:
2647 return DRM_FORMAT_XBGR2101010;
2651 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2654 case PLANE_CTL_FORMAT_RGB_565:
2655 return DRM_FORMAT_RGB565;
2657 case PLANE_CTL_FORMAT_XRGB_8888:
2660 return DRM_FORMAT_ABGR8888;
2662 return DRM_FORMAT_XBGR8888;
2665 return DRM_FORMAT_ARGB8888;
2667 return DRM_FORMAT_XRGB8888;
2669 case PLANE_CTL_FORMAT_XRGB_2101010:
2671 return DRM_FORMAT_XBGR2101010;
2673 return DRM_FORMAT_XRGB2101010;
2678 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2679 struct intel_initial_plane_config *plane_config)
2681 struct drm_device *dev = crtc->base.dev;
2682 struct drm_i915_private *dev_priv = to_i915(dev);
2683 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2684 struct drm_i915_gem_object *obj = NULL;
2685 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2686 struct drm_framebuffer *fb = &plane_config->fb->base;
2687 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2688 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2691 size_aligned -= base_aligned;
2693 if (plane_config->size == 0)
2696 /* If the FB is too big, just don't use it since fbdev is not very
2697 * important and we should probably use that space with FBC or other
2699 if (size_aligned * 2 > ggtt->stolen_usable_size)
2702 mutex_lock(&dev->struct_mutex);
2704 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2709 mutex_unlock(&dev->struct_mutex);
2713 if (plane_config->tiling == I915_TILING_X)
2714 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2716 mode_cmd.pixel_format = fb->pixel_format;
2717 mode_cmd.width = fb->width;
2718 mode_cmd.height = fb->height;
2719 mode_cmd.pitches[0] = fb->pitches[0];
2720 mode_cmd.modifier[0] = fb->modifier[0];
2721 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2723 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2725 DRM_DEBUG_KMS("intel fb init failed\n");
2729 mutex_unlock(&dev->struct_mutex);
2731 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2735 i915_gem_object_put(obj);
2736 mutex_unlock(&dev->struct_mutex);
2740 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2742 update_state_fb(struct drm_plane *plane)
2744 if (plane->fb == plane->state->fb)
2747 if (plane->state->fb)
2748 drm_framebuffer_unreference(plane->state->fb);
2749 plane->state->fb = plane->fb;
2750 if (plane->state->fb)
2751 drm_framebuffer_reference(plane->state->fb);
2755 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2756 struct intel_initial_plane_config *plane_config)
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = to_i915(dev);
2761 struct intel_crtc *i;
2762 struct drm_i915_gem_object *obj;
2763 struct drm_plane *primary = intel_crtc->base.primary;
2764 struct drm_plane_state *plane_state = primary->state;
2765 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2766 struct intel_plane *intel_plane = to_intel_plane(primary);
2767 struct intel_plane_state *intel_state =
2768 to_intel_plane_state(plane_state);
2769 struct drm_framebuffer *fb;
2771 if (!plane_config->fb)
2774 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2775 fb = &plane_config->fb->base;
2779 kfree(plane_config->fb);
2782 * Failed to alloc the obj, check to see if we should share
2783 * an fb with another CRTC instead
2785 for_each_crtc(dev, c) {
2786 i = to_intel_crtc(c);
2788 if (c == &intel_crtc->base)
2794 fb = c->primary->fb;
2798 obj = intel_fb_obj(fb);
2799 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2800 drm_framebuffer_reference(fb);
2806 * We've failed to reconstruct the BIOS FB. Current display state
2807 * indicates that the primary plane is visible, but has a NULL FB,
2808 * which will lead to problems later if we don't fix it up. The
2809 * simplest solution is to just disable the primary plane now and
2810 * pretend the BIOS never had it enabled.
2812 to_intel_plane_state(plane_state)->visible = false;
2813 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2814 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2815 intel_plane->disable_plane(primary, &intel_crtc->base);
2820 plane_state->src_x = 0;
2821 plane_state->src_y = 0;
2822 plane_state->src_w = fb->width << 16;
2823 plane_state->src_h = fb->height << 16;
2825 plane_state->crtc_x = 0;
2826 plane_state->crtc_y = 0;
2827 plane_state->crtc_w = fb->width;
2828 plane_state->crtc_h = fb->height;
2830 intel_state->src.x1 = plane_state->src_x;
2831 intel_state->src.y1 = plane_state->src_y;
2832 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2833 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2834 intel_state->dst.x1 = plane_state->crtc_x;
2835 intel_state->dst.y1 = plane_state->crtc_y;
2836 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2837 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2839 obj = intel_fb_obj(fb);
2840 if (i915_gem_object_is_tiled(obj))
2841 dev_priv->preserve_bios_swizzle = true;
2843 drm_framebuffer_reference(fb);
2844 primary->fb = primary->state->fb = fb;
2845 primary->crtc = primary->state->crtc = &intel_crtc->base;
2846 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2847 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2848 &obj->frontbuffer_bits);
2851 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2852 unsigned int rotation)
2854 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2856 switch (fb->modifier[plane]) {
2857 case DRM_FORMAT_MOD_NONE:
2858 case I915_FORMAT_MOD_X_TILED:
2871 case I915_FORMAT_MOD_Y_TILED:
2872 case I915_FORMAT_MOD_Yf_TILED:
2887 MISSING_CASE(fb->modifier[plane]);
2893 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2895 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2896 const struct drm_framebuffer *fb = plane_state->base.fb;
2897 unsigned int rotation = plane_state->base.rotation;
2898 int x = plane_state->src.x1 >> 16;
2899 int y = plane_state->src.y1 >> 16;
2900 int w = drm_rect_width(&plane_state->src) >> 16;
2901 int h = drm_rect_height(&plane_state->src) >> 16;
2902 int max_width = skl_max_plane_width(fb, 0, rotation);
2903 int max_height = 4096;
2904 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2906 if (w > max_width || h > max_height) {
2907 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2908 w, h, max_width, max_height);
2912 intel_add_fb_offsets(&x, &y, plane_state, 0);
2913 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2915 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2918 * AUX surface offset is specified as the distance from the
2919 * main surface offset, and it must be non-negative. Make
2920 * sure that is what we will get.
2922 if (offset > aux_offset)
2923 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2924 offset, aux_offset & ~(alignment - 1));
2927 * When using an X-tiled surface, the plane blows up
2928 * if the x offset + width exceed the stride.
2930 * TODO: linear and Y-tiled seem fine, Yf untested,
2932 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2933 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2935 while ((x + w) * cpp > fb->pitches[0]) {
2937 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2941 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2942 offset, offset - alignment);
2946 plane_state->main.offset = offset;
2947 plane_state->main.x = x;
2948 plane_state->main.y = y;
2953 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2955 const struct drm_framebuffer *fb = plane_state->base.fb;
2956 unsigned int rotation = plane_state->base.rotation;
2957 int max_width = skl_max_plane_width(fb, 1, rotation);
2958 int max_height = 4096;
2959 int x = plane_state->src.x1 >> 17;
2960 int y = plane_state->src.y1 >> 17;
2961 int w = drm_rect_width(&plane_state->src) >> 17;
2962 int h = drm_rect_height(&plane_state->src) >> 17;
2965 intel_add_fb_offsets(&x, &y, plane_state, 1);
2966 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2968 /* FIXME not quite sure how/if these apply to the chroma plane */
2969 if (w > max_width || h > max_height) {
2970 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2971 w, h, max_width, max_height);
2975 plane_state->aux.offset = offset;
2976 plane_state->aux.x = x;
2977 plane_state->aux.y = y;
2982 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2984 const struct drm_framebuffer *fb = plane_state->base.fb;
2985 unsigned int rotation = plane_state->base.rotation;
2988 /* Rotate src coordinates to match rotated GTT view */
2989 if (intel_rotation_90_or_270(rotation))
2990 drm_rect_rotate(&plane_state->src,
2991 fb->width, fb->height, BIT(DRM_ROTATE_270));
2994 * Handle the AUX surface first since
2995 * the main surface setup depends on it.
2997 if (fb->pixel_format == DRM_FORMAT_NV12) {
2998 ret = skl_check_nv12_aux_surface(plane_state);
3002 plane_state->aux.offset = ~0xfff;
3003 plane_state->aux.x = 0;
3004 plane_state->aux.y = 0;
3007 ret = skl_check_main_surface(plane_state);
3014 static void i9xx_update_primary_plane(struct drm_plane *primary,
3015 const struct intel_crtc_state *crtc_state,
3016 const struct intel_plane_state *plane_state)
3018 struct drm_device *dev = primary->dev;
3019 struct drm_i915_private *dev_priv = to_i915(dev);
3020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3021 struct drm_framebuffer *fb = plane_state->base.fb;
3022 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3023 int plane = intel_crtc->plane;
3026 i915_reg_t reg = DSPCNTR(plane);
3027 unsigned int rotation = plane_state->base.rotation;
3028 int x = plane_state->src.x1 >> 16;
3029 int y = plane_state->src.y1 >> 16;
3031 dspcntr = DISPPLANE_GAMMA_ENABLE;
3033 dspcntr |= DISPLAY_PLANE_ENABLE;
3035 if (INTEL_INFO(dev)->gen < 4) {
3036 if (intel_crtc->pipe == PIPE_B)
3037 dspcntr |= DISPPLANE_SEL_PIPE_B;
3039 /* pipesrc and dspsize control the size that is scaled from,
3040 * which should always be the user's requested size.
3042 I915_WRITE(DSPSIZE(plane),
3043 ((crtc_state->pipe_src_h - 1) << 16) |
3044 (crtc_state->pipe_src_w - 1));
3045 I915_WRITE(DSPPOS(plane), 0);
3046 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3047 I915_WRITE(PRIMSIZE(plane),
3048 ((crtc_state->pipe_src_h - 1) << 16) |
3049 (crtc_state->pipe_src_w - 1));
3050 I915_WRITE(PRIMPOS(plane), 0);
3051 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3054 switch (fb->pixel_format) {
3056 dspcntr |= DISPPLANE_8BPP;
3058 case DRM_FORMAT_XRGB1555:
3059 dspcntr |= DISPPLANE_BGRX555;
3061 case DRM_FORMAT_RGB565:
3062 dspcntr |= DISPPLANE_BGRX565;
3064 case DRM_FORMAT_XRGB8888:
3065 dspcntr |= DISPPLANE_BGRX888;
3067 case DRM_FORMAT_XBGR8888:
3068 dspcntr |= DISPPLANE_RGBX888;
3070 case DRM_FORMAT_XRGB2101010:
3071 dspcntr |= DISPPLANE_BGRX101010;
3073 case DRM_FORMAT_XBGR2101010:
3074 dspcntr |= DISPPLANE_RGBX101010;
3080 if (INTEL_GEN(dev_priv) >= 4 &&
3081 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3082 dspcntr |= DISPPLANE_TILED;
3085 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3087 intel_add_fb_offsets(&x, &y, plane_state, 0);
3089 if (INTEL_INFO(dev)->gen >= 4)
3090 intel_crtc->dspaddr_offset =
3091 intel_compute_tile_offset(&x, &y, plane_state, 0);
3093 if (rotation == BIT(DRM_ROTATE_180)) {
3094 dspcntr |= DISPPLANE_ROTATE_180;
3096 x += (crtc_state->pipe_src_w - 1);
3097 y += (crtc_state->pipe_src_h - 1);
3100 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3102 if (INTEL_INFO(dev)->gen < 4)
3103 intel_crtc->dspaddr_offset = linear_offset;
3105 intel_crtc->adjusted_x = x;
3106 intel_crtc->adjusted_y = y;
3108 I915_WRITE(reg, dspcntr);
3110 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3111 if (INTEL_INFO(dev)->gen >= 4) {
3112 I915_WRITE(DSPSURF(plane),
3113 intel_fb_gtt_offset(fb, rotation) +
3114 intel_crtc->dspaddr_offset);
3115 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3116 I915_WRITE(DSPLINOFF(plane), linear_offset);
3118 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
3122 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3123 struct drm_crtc *crtc)
3125 struct drm_device *dev = crtc->dev;
3126 struct drm_i915_private *dev_priv = to_i915(dev);
3127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3128 int plane = intel_crtc->plane;
3130 I915_WRITE(DSPCNTR(plane), 0);
3131 if (INTEL_INFO(dev_priv)->gen >= 4)
3132 I915_WRITE(DSPSURF(plane), 0);
3134 I915_WRITE(DSPADDR(plane), 0);
3135 POSTING_READ(DSPCNTR(plane));
3138 static void ironlake_update_primary_plane(struct drm_plane *primary,
3139 const struct intel_crtc_state *crtc_state,
3140 const struct intel_plane_state *plane_state)
3142 struct drm_device *dev = primary->dev;
3143 struct drm_i915_private *dev_priv = to_i915(dev);
3144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3145 struct drm_framebuffer *fb = plane_state->base.fb;
3146 int plane = intel_crtc->plane;
3149 i915_reg_t reg = DSPCNTR(plane);
3150 unsigned int rotation = plane_state->base.rotation;
3151 int x = plane_state->src.x1 >> 16;
3152 int y = plane_state->src.y1 >> 16;
3154 dspcntr = DISPPLANE_GAMMA_ENABLE;
3155 dspcntr |= DISPLAY_PLANE_ENABLE;
3157 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3158 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3160 switch (fb->pixel_format) {
3162 dspcntr |= DISPPLANE_8BPP;
3164 case DRM_FORMAT_RGB565:
3165 dspcntr |= DISPPLANE_BGRX565;
3167 case DRM_FORMAT_XRGB8888:
3168 dspcntr |= DISPPLANE_BGRX888;
3170 case DRM_FORMAT_XBGR8888:
3171 dspcntr |= DISPPLANE_RGBX888;
3173 case DRM_FORMAT_XRGB2101010:
3174 dspcntr |= DISPPLANE_BGRX101010;
3176 case DRM_FORMAT_XBGR2101010:
3177 dspcntr |= DISPPLANE_RGBX101010;
3183 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3184 dspcntr |= DISPPLANE_TILED;
3186 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3187 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3189 intel_add_fb_offsets(&x, &y, plane_state, 0);
3191 intel_crtc->dspaddr_offset =
3192 intel_compute_tile_offset(&x, &y, plane_state, 0);
3194 if (rotation == BIT(DRM_ROTATE_180)) {
3195 dspcntr |= DISPPLANE_ROTATE_180;
3197 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3198 x += (crtc_state->pipe_src_w - 1);
3199 y += (crtc_state->pipe_src_h - 1);
3203 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3205 intel_crtc->adjusted_x = x;
3206 intel_crtc->adjusted_y = y;
3208 I915_WRITE(reg, dspcntr);
3210 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3211 I915_WRITE(DSPSURF(plane),
3212 intel_fb_gtt_offset(fb, rotation) +
3213 intel_crtc->dspaddr_offset);
3214 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3215 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3217 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3218 I915_WRITE(DSPLINOFF(plane), linear_offset);
3223 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3224 uint64_t fb_modifier, uint32_t pixel_format)
3226 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3229 int cpp = drm_format_plane_cpp(pixel_format, 0);
3231 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3235 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3236 unsigned int rotation)
3238 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3239 struct i915_ggtt_view view;
3242 intel_fill_fb_ggtt_view(&view, fb, rotation);
3244 offset = i915_gem_obj_ggtt_offset_view(obj, &view);
3246 WARN_ON(upper_32_bits(offset));
3248 return lower_32_bits(offset);
3251 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3253 struct drm_device *dev = intel_crtc->base.dev;
3254 struct drm_i915_private *dev_priv = to_i915(dev);
3256 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3257 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3258 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3262 * This function detaches (aka. unbinds) unused scalers in hardware
3264 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3266 struct intel_crtc_scaler_state *scaler_state;
3269 scaler_state = &intel_crtc->config->scaler_state;
3271 /* loop through and disable scalers that aren't in use */
3272 for (i = 0; i < intel_crtc->num_scalers; i++) {
3273 if (!scaler_state->scalers[i].in_use)
3274 skl_detach_scaler(intel_crtc, i);
3278 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3279 unsigned int rotation)
3281 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3282 u32 stride = intel_fb_pitch(fb, plane, rotation);
3285 * The stride is either expressed as a multiple of 64 bytes chunks for
3286 * linear buffers or in number of tiles for tiled buffers.
3288 if (intel_rotation_90_or_270(rotation)) {
3289 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3291 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3293 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3300 u32 skl_plane_ctl_format(uint32_t pixel_format)
3302 switch (pixel_format) {
3304 return PLANE_CTL_FORMAT_INDEXED;
3305 case DRM_FORMAT_RGB565:
3306 return PLANE_CTL_FORMAT_RGB_565;
3307 case DRM_FORMAT_XBGR8888:
3308 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3309 case DRM_FORMAT_XRGB8888:
3310 return PLANE_CTL_FORMAT_XRGB_8888;
3312 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3313 * to be already pre-multiplied. We need to add a knob (or a different
3314 * DRM_FORMAT) for user-space to configure that.
3316 case DRM_FORMAT_ABGR8888:
3317 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3318 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3319 case DRM_FORMAT_ARGB8888:
3320 return PLANE_CTL_FORMAT_XRGB_8888 |
3321 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3322 case DRM_FORMAT_XRGB2101010:
3323 return PLANE_CTL_FORMAT_XRGB_2101010;
3324 case DRM_FORMAT_XBGR2101010:
3325 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3326 case DRM_FORMAT_YUYV:
3327 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3328 case DRM_FORMAT_YVYU:
3329 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3330 case DRM_FORMAT_UYVY:
3331 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3332 case DRM_FORMAT_VYUY:
3333 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3335 MISSING_CASE(pixel_format);
3341 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3343 switch (fb_modifier) {
3344 case DRM_FORMAT_MOD_NONE:
3346 case I915_FORMAT_MOD_X_TILED:
3347 return PLANE_CTL_TILED_X;
3348 case I915_FORMAT_MOD_Y_TILED:
3349 return PLANE_CTL_TILED_Y;
3350 case I915_FORMAT_MOD_Yf_TILED:
3351 return PLANE_CTL_TILED_YF;
3353 MISSING_CASE(fb_modifier);
3359 u32 skl_plane_ctl_rotation(unsigned int rotation)
3362 case BIT(DRM_ROTATE_0):
3365 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3366 * while i915 HW rotation is clockwise, thats why this swapping.
3368 case BIT(DRM_ROTATE_90):
3369 return PLANE_CTL_ROTATE_270;
3370 case BIT(DRM_ROTATE_180):
3371 return PLANE_CTL_ROTATE_180;
3372 case BIT(DRM_ROTATE_270):
3373 return PLANE_CTL_ROTATE_90;
3375 MISSING_CASE(rotation);
3381 static void skylake_update_primary_plane(struct drm_plane *plane,
3382 const struct intel_crtc_state *crtc_state,
3383 const struct intel_plane_state *plane_state)
3385 struct drm_device *dev = plane->dev;
3386 struct drm_i915_private *dev_priv = to_i915(dev);
3387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3388 struct drm_framebuffer *fb = plane_state->base.fb;
3389 int pipe = intel_crtc->pipe;
3391 unsigned int rotation = plane_state->base.rotation;
3392 u32 stride = skl_plane_stride(fb, 0, rotation);
3393 u32 surf_addr = plane_state->main.offset;
3394 int scaler_id = plane_state->scaler_id;
3395 int src_x = plane_state->main.x;
3396 int src_y = plane_state->main.y;
3397 int src_w = drm_rect_width(&plane_state->src) >> 16;
3398 int src_h = drm_rect_height(&plane_state->src) >> 16;
3399 int dst_x = plane_state->dst.x1;
3400 int dst_y = plane_state->dst.y1;
3401 int dst_w = drm_rect_width(&plane_state->dst);
3402 int dst_h = drm_rect_height(&plane_state->dst);
3404 plane_ctl = PLANE_CTL_ENABLE |
3405 PLANE_CTL_PIPE_GAMMA_ENABLE |
3406 PLANE_CTL_PIPE_CSC_ENABLE;
3408 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3409 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3410 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3411 plane_ctl |= skl_plane_ctl_rotation(rotation);
3413 /* Sizes are 0 based */
3419 intel_crtc->adjusted_x = src_x;
3420 intel_crtc->adjusted_y = src_y;
3422 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3423 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3424 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3425 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3427 if (scaler_id >= 0) {
3428 uint32_t ps_ctrl = 0;
3430 WARN_ON(!dst_w || !dst_h);
3431 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3432 crtc_state->scaler_state.scalers[scaler_id].mode;
3433 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3434 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3435 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3436 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3437 I915_WRITE(PLANE_POS(pipe, 0), 0);
3439 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3442 I915_WRITE(PLANE_SURF(pipe, 0),
3443 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3445 POSTING_READ(PLANE_SURF(pipe, 0));
3448 static void skylake_disable_primary_plane(struct drm_plane *primary,
3449 struct drm_crtc *crtc)
3451 struct drm_device *dev = crtc->dev;
3452 struct drm_i915_private *dev_priv = to_i915(dev);
3453 int pipe = to_intel_crtc(crtc)->pipe;
3455 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3456 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3457 POSTING_READ(PLANE_SURF(pipe, 0));
3460 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3462 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3463 int x, int y, enum mode_set_atomic state)
3465 /* Support for kgdboc is disabled, this needs a major rework. */
3466 DRM_ERROR("legacy panic handler not supported any more.\n");
3471 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3473 struct intel_crtc *crtc;
3475 for_each_intel_crtc(&dev_priv->drm, crtc)
3476 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3479 static void intel_update_primary_planes(struct drm_device *dev)
3481 struct drm_crtc *crtc;
3483 for_each_crtc(dev, crtc) {
3484 struct intel_plane *plane = to_intel_plane(crtc->primary);
3485 struct intel_plane_state *plane_state =
3486 to_intel_plane_state(plane->base.state);
3488 if (plane_state->visible)
3489 plane->update_plane(&plane->base,
3490 to_intel_crtc_state(crtc->state),
3496 __intel_display_resume(struct drm_device *dev,
3497 struct drm_atomic_state *state)
3499 struct drm_crtc_state *crtc_state;
3500 struct drm_crtc *crtc;
3503 intel_modeset_setup_hw_state(dev);
3504 i915_redisable_vga(dev);
3509 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3511 * Force recalculation even if we restore
3512 * current state. With fast modeset this may not result
3513 * in a modeset when the state is compatible.
3515 crtc_state->mode_changed = true;
3518 /* ignore any reset values/BIOS leftovers in the WM registers */
3519 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3521 ret = drm_atomic_commit(state);
3523 WARN_ON(ret == -EDEADLK);
3527 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3529 return intel_has_gpu_reset(dev_priv) &&
3530 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3533 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3535 struct drm_device *dev = &dev_priv->drm;
3536 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3537 struct drm_atomic_state *state;
3541 * Need mode_config.mutex so that we don't
3542 * trample ongoing ->detect() and whatnot.
3544 mutex_lock(&dev->mode_config.mutex);
3545 drm_modeset_acquire_init(ctx, 0);
3547 ret = drm_modeset_lock_all_ctx(dev, ctx);
3548 if (ret != -EDEADLK)
3551 drm_modeset_backoff(ctx);
3554 /* reset doesn't touch the display, but flips might get nuked anyway, */
3555 if (!i915.force_reset_modeset_test &&
3556 !gpu_reset_clobbers_display(dev_priv))
3560 * Disabling the crtcs gracefully seems nicer. Also the
3561 * g33 docs say we should at least disable all the planes.
3563 state = drm_atomic_helper_duplicate_state(dev, ctx);
3564 if (IS_ERR(state)) {
3565 ret = PTR_ERR(state);
3567 DRM_ERROR("Duplicating state failed with %i\n", ret);
3571 ret = drm_atomic_helper_disable_all(dev, ctx);
3573 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3577 dev_priv->modeset_restore_state = state;
3578 state->acquire_ctx = ctx;
3582 drm_atomic_state_free(state);
3585 void intel_finish_reset(struct drm_i915_private *dev_priv)
3587 struct drm_device *dev = &dev_priv->drm;
3588 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3589 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3593 * Flips in the rings will be nuked by the reset,
3594 * so complete all pending flips so that user space
3595 * will get its events and not get stuck.
3597 intel_complete_page_flips(dev_priv);
3599 dev_priv->modeset_restore_state = NULL;
3601 /* reset doesn't touch the display */
3602 if (!gpu_reset_clobbers_display(dev_priv)) {
3605 * Flips in the rings have been nuked by the reset,
3606 * so update the base address of all primary
3607 * planes to the the last fb to make sure we're
3608 * showing the correct fb after a reset.
3610 * FIXME: Atomic will make this obsolete since we won't schedule
3611 * CS-based flips (which might get lost in gpu resets) any more.
3613 intel_update_primary_planes(dev);
3615 ret = __intel_display_resume(dev, state);
3617 DRM_ERROR("Restoring old state failed with %i\n", ret);
3621 * The display has been reset as well,
3622 * so need a full re-initialization.
3624 intel_runtime_pm_disable_interrupts(dev_priv);
3625 intel_runtime_pm_enable_interrupts(dev_priv);
3627 intel_modeset_init_hw(dev);
3629 spin_lock_irq(&dev_priv->irq_lock);
3630 if (dev_priv->display.hpd_irq_setup)
3631 dev_priv->display.hpd_irq_setup(dev_priv);
3632 spin_unlock_irq(&dev_priv->irq_lock);
3634 ret = __intel_display_resume(dev, state);
3636 DRM_ERROR("Restoring old state failed with %i\n", ret);
3638 intel_hpd_init(dev_priv);
3641 drm_modeset_drop_locks(ctx);
3642 drm_modeset_acquire_fini(ctx);
3643 mutex_unlock(&dev->mode_config.mutex);
3646 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3648 struct drm_device *dev = crtc->dev;
3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650 unsigned reset_counter;
3653 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3654 if (intel_crtc->reset_counter != reset_counter)
3657 spin_lock_irq(&dev->event_lock);
3658 pending = to_intel_crtc(crtc)->flip_work != NULL;
3659 spin_unlock_irq(&dev->event_lock);
3664 static void intel_update_pipe_config(struct intel_crtc *crtc,
3665 struct intel_crtc_state *old_crtc_state)
3667 struct drm_device *dev = crtc->base.dev;
3668 struct drm_i915_private *dev_priv = to_i915(dev);
3669 struct intel_crtc_state *pipe_config =
3670 to_intel_crtc_state(crtc->base.state);
3672 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3673 crtc->base.mode = crtc->base.state->mode;
3675 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3676 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3677 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3680 * Update pipe size and adjust fitter if needed: the reason for this is
3681 * that in compute_mode_changes we check the native mode (not the pfit
3682 * mode) to see if we can flip rather than do a full mode set. In the
3683 * fastboot case, we'll flip, but if we don't update the pipesrc and
3684 * pfit state, we'll end up with a big fb scanned out into the wrong
3688 I915_WRITE(PIPESRC(crtc->pipe),
3689 ((pipe_config->pipe_src_w - 1) << 16) |
3690 (pipe_config->pipe_src_h - 1));
3692 /* on skylake this is done by detaching scalers */
3693 if (INTEL_INFO(dev)->gen >= 9) {
3694 skl_detach_scalers(crtc);
3696 if (pipe_config->pch_pfit.enabled)
3697 skylake_pfit_enable(crtc);
3698 } else if (HAS_PCH_SPLIT(dev)) {
3699 if (pipe_config->pch_pfit.enabled)
3700 ironlake_pfit_enable(crtc);
3701 else if (old_crtc_state->pch_pfit.enabled)
3702 ironlake_pfit_disable(crtc, true);
3706 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3708 struct drm_device *dev = crtc->dev;
3709 struct drm_i915_private *dev_priv = to_i915(dev);
3710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3711 int pipe = intel_crtc->pipe;
3715 /* enable normal train */
3716 reg = FDI_TX_CTL(pipe);
3717 temp = I915_READ(reg);
3718 if (IS_IVYBRIDGE(dev)) {
3719 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3720 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3722 temp &= ~FDI_LINK_TRAIN_NONE;
3723 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3725 I915_WRITE(reg, temp);
3727 reg = FDI_RX_CTL(pipe);
3728 temp = I915_READ(reg);
3729 if (HAS_PCH_CPT(dev)) {
3730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3731 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3733 temp &= ~FDI_LINK_TRAIN_NONE;
3734 temp |= FDI_LINK_TRAIN_NONE;
3736 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3738 /* wait one idle pattern time */
3742 /* IVB wants error correction enabled */
3743 if (IS_IVYBRIDGE(dev))
3744 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3745 FDI_FE_ERRC_ENABLE);
3748 /* The FDI link training functions for ILK/Ibexpeak. */
3749 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3751 struct drm_device *dev = crtc->dev;
3752 struct drm_i915_private *dev_priv = to_i915(dev);
3753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3754 int pipe = intel_crtc->pipe;
3758 /* FDI needs bits from pipe first */
3759 assert_pipe_enabled(dev_priv, pipe);
3761 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3763 reg = FDI_RX_IMR(pipe);
3764 temp = I915_READ(reg);
3765 temp &= ~FDI_RX_SYMBOL_LOCK;
3766 temp &= ~FDI_RX_BIT_LOCK;
3767 I915_WRITE(reg, temp);
3771 /* enable CPU FDI TX and PCH FDI RX */
3772 reg = FDI_TX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3775 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3776 temp &= ~FDI_LINK_TRAIN_NONE;
3777 temp |= FDI_LINK_TRAIN_PATTERN_1;
3778 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3780 reg = FDI_RX_CTL(pipe);
3781 temp = I915_READ(reg);
3782 temp &= ~FDI_LINK_TRAIN_NONE;
3783 temp |= FDI_LINK_TRAIN_PATTERN_1;
3784 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3789 /* Ironlake workaround, enable clock pointer after FDI enable*/
3790 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3791 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3792 FDI_RX_PHASE_SYNC_POINTER_EN);
3794 reg = FDI_RX_IIR(pipe);
3795 for (tries = 0; tries < 5; tries++) {
3796 temp = I915_READ(reg);
3797 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3799 if ((temp & FDI_RX_BIT_LOCK)) {
3800 DRM_DEBUG_KMS("FDI train 1 done.\n");
3801 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3806 DRM_ERROR("FDI train 1 fail!\n");
3809 reg = FDI_TX_CTL(pipe);
3810 temp = I915_READ(reg);
3811 temp &= ~FDI_LINK_TRAIN_NONE;
3812 temp |= FDI_LINK_TRAIN_PATTERN_2;
3813 I915_WRITE(reg, temp);
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 temp &= ~FDI_LINK_TRAIN_NONE;
3818 temp |= FDI_LINK_TRAIN_PATTERN_2;
3819 I915_WRITE(reg, temp);
3824 reg = FDI_RX_IIR(pipe);
3825 for (tries = 0; tries < 5; tries++) {
3826 temp = I915_READ(reg);
3827 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3829 if (temp & FDI_RX_SYMBOL_LOCK) {
3830 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3831 DRM_DEBUG_KMS("FDI train 2 done.\n");
3836 DRM_ERROR("FDI train 2 fail!\n");
3838 DRM_DEBUG_KMS("FDI train done\n");
3842 static const int snb_b_fdi_train_param[] = {
3843 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3844 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3845 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3846 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3849 /* The FDI link training functions for SNB/Cougarpoint. */
3850 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3852 struct drm_device *dev = crtc->dev;
3853 struct drm_i915_private *dev_priv = to_i915(dev);
3854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3855 int pipe = intel_crtc->pipe;
3859 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3861 reg = FDI_RX_IMR(pipe);
3862 temp = I915_READ(reg);
3863 temp &= ~FDI_RX_SYMBOL_LOCK;
3864 temp &= ~FDI_RX_BIT_LOCK;
3865 I915_WRITE(reg, temp);
3870 /* enable CPU FDI TX and PCH FDI RX */
3871 reg = FDI_TX_CTL(pipe);
3872 temp = I915_READ(reg);
3873 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3874 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3875 temp &= ~FDI_LINK_TRAIN_NONE;
3876 temp |= FDI_LINK_TRAIN_PATTERN_1;
3877 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3879 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3880 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3882 I915_WRITE(FDI_RX_MISC(pipe),
3883 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3885 reg = FDI_RX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 if (HAS_PCH_CPT(dev)) {
3888 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3889 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3891 temp &= ~FDI_LINK_TRAIN_NONE;
3892 temp |= FDI_LINK_TRAIN_PATTERN_1;
3894 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3899 for (i = 0; i < 4; i++) {
3900 reg = FDI_TX_CTL(pipe);
3901 temp = I915_READ(reg);
3902 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3903 temp |= snb_b_fdi_train_param[i];
3904 I915_WRITE(reg, temp);
3909 for (retry = 0; retry < 5; retry++) {
3910 reg = FDI_RX_IIR(pipe);
3911 temp = I915_READ(reg);
3912 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3913 if (temp & FDI_RX_BIT_LOCK) {
3914 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3915 DRM_DEBUG_KMS("FDI train 1 done.\n");
3924 DRM_ERROR("FDI train 1 fail!\n");
3927 reg = FDI_TX_CTL(pipe);
3928 temp = I915_READ(reg);
3929 temp &= ~FDI_LINK_TRAIN_NONE;
3930 temp |= FDI_LINK_TRAIN_PATTERN_2;
3932 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3934 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3936 I915_WRITE(reg, temp);
3938 reg = FDI_RX_CTL(pipe);
3939 temp = I915_READ(reg);
3940 if (HAS_PCH_CPT(dev)) {
3941 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3942 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3944 temp &= ~FDI_LINK_TRAIN_NONE;
3945 temp |= FDI_LINK_TRAIN_PATTERN_2;
3947 I915_WRITE(reg, temp);
3952 for (i = 0; i < 4; i++) {
3953 reg = FDI_TX_CTL(pipe);
3954 temp = I915_READ(reg);
3955 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3956 temp |= snb_b_fdi_train_param[i];
3957 I915_WRITE(reg, temp);
3962 for (retry = 0; retry < 5; retry++) {
3963 reg = FDI_RX_IIR(pipe);
3964 temp = I915_READ(reg);
3965 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3966 if (temp & FDI_RX_SYMBOL_LOCK) {
3967 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3968 DRM_DEBUG_KMS("FDI train 2 done.\n");
3977 DRM_ERROR("FDI train 2 fail!\n");
3979 DRM_DEBUG_KMS("FDI train done.\n");
3982 /* Manual link training for Ivy Bridge A0 parts */
3983 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = to_i915(dev);
3987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988 int pipe = intel_crtc->pipe;
3992 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3994 reg = FDI_RX_IMR(pipe);
3995 temp = I915_READ(reg);
3996 temp &= ~FDI_RX_SYMBOL_LOCK;
3997 temp &= ~FDI_RX_BIT_LOCK;
3998 I915_WRITE(reg, temp);
4003 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4004 I915_READ(FDI_RX_IIR(pipe)));
4006 /* Try each vswing and preemphasis setting twice before moving on */
4007 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4008 /* disable first in case we need to retry */
4009 reg = FDI_TX_CTL(pipe);
4010 temp = I915_READ(reg);
4011 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4012 temp &= ~FDI_TX_ENABLE;
4013 I915_WRITE(reg, temp);
4015 reg = FDI_RX_CTL(pipe);
4016 temp = I915_READ(reg);
4017 temp &= ~FDI_LINK_TRAIN_AUTO;
4018 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4019 temp &= ~FDI_RX_ENABLE;
4020 I915_WRITE(reg, temp);
4022 /* enable CPU FDI TX and PCH FDI RX */
4023 reg = FDI_TX_CTL(pipe);
4024 temp = I915_READ(reg);
4025 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4026 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4027 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4028 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4029 temp |= snb_b_fdi_train_param[j/2];
4030 temp |= FDI_COMPOSITE_SYNC;
4031 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4033 I915_WRITE(FDI_RX_MISC(pipe),
4034 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4036 reg = FDI_RX_CTL(pipe);
4037 temp = I915_READ(reg);
4038 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4039 temp |= FDI_COMPOSITE_SYNC;
4040 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4043 udelay(1); /* should be 0.5us */
4045 for (i = 0; i < 4; i++) {
4046 reg = FDI_RX_IIR(pipe);
4047 temp = I915_READ(reg);
4048 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4050 if (temp & FDI_RX_BIT_LOCK ||
4051 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4052 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4053 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4057 udelay(1); /* should be 0.5us */
4060 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4065 reg = FDI_TX_CTL(pipe);
4066 temp = I915_READ(reg);
4067 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4068 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4069 I915_WRITE(reg, temp);
4071 reg = FDI_RX_CTL(pipe);
4072 temp = I915_READ(reg);
4073 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4074 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4075 I915_WRITE(reg, temp);
4078 udelay(2); /* should be 1.5us */
4080 for (i = 0; i < 4; i++) {
4081 reg = FDI_RX_IIR(pipe);
4082 temp = I915_READ(reg);
4083 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4085 if (temp & FDI_RX_SYMBOL_LOCK ||
4086 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4087 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4088 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4092 udelay(2); /* should be 1.5us */
4095 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4099 DRM_DEBUG_KMS("FDI train done.\n");
4102 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4104 struct drm_device *dev = intel_crtc->base.dev;
4105 struct drm_i915_private *dev_priv = to_i915(dev);
4106 int pipe = intel_crtc->pipe;
4110 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4111 reg = FDI_RX_CTL(pipe);
4112 temp = I915_READ(reg);
4113 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4114 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4115 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4116 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4121 /* Switch from Rawclk to PCDclk */
4122 temp = I915_READ(reg);
4123 I915_WRITE(reg, temp | FDI_PCDCLK);
4128 /* Enable CPU FDI TX PLL, always on for Ironlake */
4129 reg = FDI_TX_CTL(pipe);
4130 temp = I915_READ(reg);
4131 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4132 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4139 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4141 struct drm_device *dev = intel_crtc->base.dev;
4142 struct drm_i915_private *dev_priv = to_i915(dev);
4143 int pipe = intel_crtc->pipe;
4147 /* Switch from PCDclk to Rawclk */
4148 reg = FDI_RX_CTL(pipe);
4149 temp = I915_READ(reg);
4150 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4152 /* Disable CPU FDI TX PLL */
4153 reg = FDI_TX_CTL(pipe);
4154 temp = I915_READ(reg);
4155 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4160 reg = FDI_RX_CTL(pipe);
4161 temp = I915_READ(reg);
4162 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4164 /* Wait for the clocks to turn off. */
4169 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4171 struct drm_device *dev = crtc->dev;
4172 struct drm_i915_private *dev_priv = to_i915(dev);
4173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4174 int pipe = intel_crtc->pipe;
4178 /* disable CPU FDI tx and PCH FDI rx */
4179 reg = FDI_TX_CTL(pipe);
4180 temp = I915_READ(reg);
4181 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4184 reg = FDI_RX_CTL(pipe);
4185 temp = I915_READ(reg);
4186 temp &= ~(0x7 << 16);
4187 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4188 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4193 /* Ironlake workaround, disable clock pointer after downing FDI */
4194 if (HAS_PCH_IBX(dev))
4195 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4197 /* still set train pattern 1 */
4198 reg = FDI_TX_CTL(pipe);
4199 temp = I915_READ(reg);
4200 temp &= ~FDI_LINK_TRAIN_NONE;
4201 temp |= FDI_LINK_TRAIN_PATTERN_1;
4202 I915_WRITE(reg, temp);
4204 reg = FDI_RX_CTL(pipe);
4205 temp = I915_READ(reg);
4206 if (HAS_PCH_CPT(dev)) {
4207 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4208 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4210 temp &= ~FDI_LINK_TRAIN_NONE;
4211 temp |= FDI_LINK_TRAIN_PATTERN_1;
4213 /* BPC in FDI rx is consistent with that in PIPECONF */
4214 temp &= ~(0x07 << 16);
4215 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4216 I915_WRITE(reg, temp);
4222 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4224 struct intel_crtc *crtc;
4226 /* Note that we don't need to be called with mode_config.lock here
4227 * as our list of CRTC objects is static for the lifetime of the
4228 * device and so cannot disappear as we iterate. Similarly, we can
4229 * happily treat the predicates as racy, atomic checks as userspace
4230 * cannot claim and pin a new fb without at least acquring the
4231 * struct_mutex and so serialising with us.
4233 for_each_intel_crtc(dev, crtc) {
4234 if (atomic_read(&crtc->unpin_work_count) == 0)
4237 if (crtc->flip_work)
4238 intel_wait_for_vblank(dev, crtc->pipe);
4246 static void page_flip_completed(struct intel_crtc *intel_crtc)
4248 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4249 struct intel_flip_work *work = intel_crtc->flip_work;
4251 intel_crtc->flip_work = NULL;
4254 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4256 drm_crtc_vblank_put(&intel_crtc->base);
4258 wake_up_all(&dev_priv->pending_flip_queue);
4259 queue_work(dev_priv->wq, &work->unpin_work);
4261 trace_i915_flip_complete(intel_crtc->plane,
4262 work->pending_flip_obj);
4265 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4267 struct drm_device *dev = crtc->dev;
4268 struct drm_i915_private *dev_priv = to_i915(dev);
4271 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4273 ret = wait_event_interruptible_timeout(
4274 dev_priv->pending_flip_queue,
4275 !intel_crtc_has_pending_flip(crtc),
4282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4283 struct intel_flip_work *work;
4285 spin_lock_irq(&dev->event_lock);
4286 work = intel_crtc->flip_work;
4287 if (work && !is_mmio_work(work)) {
4288 WARN_ONCE(1, "Removing stuck page flip\n");
4289 page_flip_completed(intel_crtc);
4291 spin_unlock_irq(&dev->event_lock);
4297 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4301 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4303 mutex_lock(&dev_priv->sb_lock);
4305 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4306 temp |= SBI_SSCCTL_DISABLE;
4307 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4309 mutex_unlock(&dev_priv->sb_lock);
4312 /* Program iCLKIP clock to the desired frequency */
4313 static void lpt_program_iclkip(struct drm_crtc *crtc)
4315 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4316 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4317 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4320 lpt_disable_iclkip(dev_priv);
4322 /* The iCLK virtual clock root frequency is in MHz,
4323 * but the adjusted_mode->crtc_clock in in KHz. To get the
4324 * divisors, it is necessary to divide one by another, so we
4325 * convert the virtual clock precision to KHz here for higher
4328 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4329 u32 iclk_virtual_root_freq = 172800 * 1000;
4330 u32 iclk_pi_range = 64;
4331 u32 desired_divisor;
4333 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4335 divsel = (desired_divisor / iclk_pi_range) - 2;
4336 phaseinc = desired_divisor % iclk_pi_range;
4339 * Near 20MHz is a corner case which is
4340 * out of range for the 7-bit divisor
4346 /* This should not happen with any sane values */
4347 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4348 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4349 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4350 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4352 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4359 mutex_lock(&dev_priv->sb_lock);
4361 /* Program SSCDIVINTPHASE6 */
4362 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4363 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4364 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4365 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4366 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4367 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4368 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4369 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4371 /* Program SSCAUXDIV */
4372 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4373 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4374 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4375 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4377 /* Enable modulator and associated divider */
4378 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4379 temp &= ~SBI_SSCCTL_DISABLE;
4380 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4382 mutex_unlock(&dev_priv->sb_lock);
4384 /* Wait for initialization time */
4387 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4390 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4392 u32 divsel, phaseinc, auxdiv;
4393 u32 iclk_virtual_root_freq = 172800 * 1000;
4394 u32 iclk_pi_range = 64;
4395 u32 desired_divisor;
4398 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4401 mutex_lock(&dev_priv->sb_lock);
4403 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4404 if (temp & SBI_SSCCTL_DISABLE) {
4405 mutex_unlock(&dev_priv->sb_lock);
4409 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4410 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4411 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4412 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4413 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4415 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4416 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4417 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4419 mutex_unlock(&dev_priv->sb_lock);
4421 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4423 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4424 desired_divisor << auxdiv);
4427 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4428 enum pipe pch_transcoder)
4430 struct drm_device *dev = crtc->base.dev;
4431 struct drm_i915_private *dev_priv = to_i915(dev);
4432 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4434 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4435 I915_READ(HTOTAL(cpu_transcoder)));
4436 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4437 I915_READ(HBLANK(cpu_transcoder)));
4438 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4439 I915_READ(HSYNC(cpu_transcoder)));
4441 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4442 I915_READ(VTOTAL(cpu_transcoder)));
4443 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4444 I915_READ(VBLANK(cpu_transcoder)));
4445 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4446 I915_READ(VSYNC(cpu_transcoder)));
4447 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4448 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4451 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4453 struct drm_i915_private *dev_priv = to_i915(dev);
4456 temp = I915_READ(SOUTH_CHICKEN1);
4457 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4460 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4461 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4463 temp &= ~FDI_BC_BIFURCATION_SELECT;
4465 temp |= FDI_BC_BIFURCATION_SELECT;
4467 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4468 I915_WRITE(SOUTH_CHICKEN1, temp);
4469 POSTING_READ(SOUTH_CHICKEN1);
4472 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4474 struct drm_device *dev = intel_crtc->base.dev;
4476 switch (intel_crtc->pipe) {
4480 if (intel_crtc->config->fdi_lanes > 2)
4481 cpt_set_fdi_bc_bifurcation(dev, false);
4483 cpt_set_fdi_bc_bifurcation(dev, true);
4487 cpt_set_fdi_bc_bifurcation(dev, true);
4495 /* Return which DP Port should be selected for Transcoder DP control */
4497 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4499 struct drm_device *dev = crtc->dev;
4500 struct intel_encoder *encoder;
4502 for_each_encoder_on_crtc(dev, crtc, encoder) {
4503 if (encoder->type == INTEL_OUTPUT_DP ||
4504 encoder->type == INTEL_OUTPUT_EDP)
4505 return enc_to_dig_port(&encoder->base)->port;
4512 * Enable PCH resources required for PCH ports:
4514 * - FDI training & RX/TX
4515 * - update transcoder timings
4516 * - DP transcoding bits
4519 static void ironlake_pch_enable(struct drm_crtc *crtc)
4521 struct drm_device *dev = crtc->dev;
4522 struct drm_i915_private *dev_priv = to_i915(dev);
4523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4524 int pipe = intel_crtc->pipe;
4527 assert_pch_transcoder_disabled(dev_priv, pipe);
4529 if (IS_IVYBRIDGE(dev))
4530 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4532 /* Write the TU size bits before fdi link training, so that error
4533 * detection works. */
4534 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4535 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4537 /* For PCH output, training FDI link */
4538 dev_priv->display.fdi_link_train(crtc);
4540 /* We need to program the right clock selection before writing the pixel
4541 * mutliplier into the DPLL. */
4542 if (HAS_PCH_CPT(dev)) {
4545 temp = I915_READ(PCH_DPLL_SEL);
4546 temp |= TRANS_DPLL_ENABLE(pipe);
4547 sel = TRANS_DPLLB_SEL(pipe);
4548 if (intel_crtc->config->shared_dpll ==
4549 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4553 I915_WRITE(PCH_DPLL_SEL, temp);
4556 /* XXX: pch pll's can be enabled any time before we enable the PCH
4557 * transcoder, and we actually should do this to not upset any PCH
4558 * transcoder that already use the clock when we share it.
4560 * Note that enable_shared_dpll tries to do the right thing, but
4561 * get_shared_dpll unconditionally resets the pll - we need that to have
4562 * the right LVDS enable sequence. */
4563 intel_enable_shared_dpll(intel_crtc);
4565 /* set transcoder timing, panel must allow it */
4566 assert_panel_unlocked(dev_priv, pipe);
4567 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4569 intel_fdi_normal_train(crtc);
4571 /* For PCH DP, enable TRANS_DP_CTL */
4572 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4573 const struct drm_display_mode *adjusted_mode =
4574 &intel_crtc->config->base.adjusted_mode;
4575 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4576 i915_reg_t reg = TRANS_DP_CTL(pipe);
4577 temp = I915_READ(reg);
4578 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4579 TRANS_DP_SYNC_MASK |
4581 temp |= TRANS_DP_OUTPUT_ENABLE;
4582 temp |= bpc << 9; /* same format but at 11:9 */
4584 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4585 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4586 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4587 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4589 switch (intel_trans_dp_port_sel(crtc)) {
4591 temp |= TRANS_DP_PORT_SEL_B;
4594 temp |= TRANS_DP_PORT_SEL_C;
4597 temp |= TRANS_DP_PORT_SEL_D;
4603 I915_WRITE(reg, temp);
4606 ironlake_enable_pch_transcoder(dev_priv, pipe);
4609 static void lpt_pch_enable(struct drm_crtc *crtc)
4611 struct drm_device *dev = crtc->dev;
4612 struct drm_i915_private *dev_priv = to_i915(dev);
4613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4614 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4616 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4618 lpt_program_iclkip(crtc);
4620 /* Set transcoder timing. */
4621 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4623 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4626 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4628 struct drm_i915_private *dev_priv = to_i915(dev);
4629 i915_reg_t dslreg = PIPEDSL(pipe);
4632 temp = I915_READ(dslreg);
4634 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4635 if (wait_for(I915_READ(dslreg) != temp, 5))
4636 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4641 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4642 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4643 int src_w, int src_h, int dst_w, int dst_h)
4645 struct intel_crtc_scaler_state *scaler_state =
4646 &crtc_state->scaler_state;
4647 struct intel_crtc *intel_crtc =
4648 to_intel_crtc(crtc_state->base.crtc);
4651 need_scaling = intel_rotation_90_or_270(rotation) ?
4652 (src_h != dst_w || src_w != dst_h):
4653 (src_w != dst_w || src_h != dst_h);
4656 * if plane is being disabled or scaler is no more required or force detach
4657 * - free scaler binded to this plane/crtc
4658 * - in order to do this, update crtc->scaler_usage
4660 * Here scaler state in crtc_state is set free so that
4661 * scaler can be assigned to other user. Actual register
4662 * update to free the scaler is done in plane/panel-fit programming.
4663 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4665 if (force_detach || !need_scaling) {
4666 if (*scaler_id >= 0) {
4667 scaler_state->scaler_users &= ~(1 << scaler_user);
4668 scaler_state->scalers[*scaler_id].in_use = 0;
4670 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4671 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4672 intel_crtc->pipe, scaler_user, *scaler_id,
4673 scaler_state->scaler_users);
4680 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4681 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4683 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4684 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4685 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4686 "size is out of scaler range\n",
4687 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4691 /* mark this plane as a scaler user in crtc_state */
4692 scaler_state->scaler_users |= (1 << scaler_user);
4693 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4694 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4695 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4696 scaler_state->scaler_users);
4702 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4704 * @state: crtc's scaler state
4707 * 0 - scaler_usage updated successfully
4708 * error - requested scaling cannot be supported or other error condition
4710 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4712 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4713 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4715 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4716 intel_crtc->base.base.id, intel_crtc->base.name,
4717 intel_crtc->pipe, SKL_CRTC_INDEX);
4719 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4720 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4721 state->pipe_src_w, state->pipe_src_h,
4722 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4726 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4728 * @state: crtc's scaler state
4729 * @plane_state: atomic plane state to update
4732 * 0 - scaler_usage updated successfully
4733 * error - requested scaling cannot be supported or other error condition
4735 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4736 struct intel_plane_state *plane_state)
4739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4740 struct intel_plane *intel_plane =
4741 to_intel_plane(plane_state->base.plane);
4742 struct drm_framebuffer *fb = plane_state->base.fb;
4745 bool force_detach = !fb || !plane_state->visible;
4747 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4748 intel_plane->base.base.id, intel_plane->base.name,
4749 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4751 ret = skl_update_scaler(crtc_state, force_detach,
4752 drm_plane_index(&intel_plane->base),
4753 &plane_state->scaler_id,
4754 plane_state->base.rotation,
4755 drm_rect_width(&plane_state->src) >> 16,
4756 drm_rect_height(&plane_state->src) >> 16,
4757 drm_rect_width(&plane_state->dst),
4758 drm_rect_height(&plane_state->dst));
4760 if (ret || plane_state->scaler_id < 0)
4763 /* check colorkey */
4764 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4765 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4766 intel_plane->base.base.id,
4767 intel_plane->base.name);
4771 /* Check src format */
4772 switch (fb->pixel_format) {
4773 case DRM_FORMAT_RGB565:
4774 case DRM_FORMAT_XBGR8888:
4775 case DRM_FORMAT_XRGB8888:
4776 case DRM_FORMAT_ABGR8888:
4777 case DRM_FORMAT_ARGB8888:
4778 case DRM_FORMAT_XRGB2101010:
4779 case DRM_FORMAT_XBGR2101010:
4780 case DRM_FORMAT_YUYV:
4781 case DRM_FORMAT_YVYU:
4782 case DRM_FORMAT_UYVY:
4783 case DRM_FORMAT_VYUY:
4786 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4787 intel_plane->base.base.id, intel_plane->base.name,
4788 fb->base.id, fb->pixel_format);
4795 static void skylake_scaler_disable(struct intel_crtc *crtc)
4799 for (i = 0; i < crtc->num_scalers; i++)
4800 skl_detach_scaler(crtc, i);
4803 static void skylake_pfit_enable(struct intel_crtc *crtc)
4805 struct drm_device *dev = crtc->base.dev;
4806 struct drm_i915_private *dev_priv = to_i915(dev);
4807 int pipe = crtc->pipe;
4808 struct intel_crtc_scaler_state *scaler_state =
4809 &crtc->config->scaler_state;
4811 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4813 if (crtc->config->pch_pfit.enabled) {
4816 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4817 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4821 id = scaler_state->scaler_id;
4822 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4823 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4824 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4825 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4827 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4831 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4833 struct drm_device *dev = crtc->base.dev;
4834 struct drm_i915_private *dev_priv = to_i915(dev);
4835 int pipe = crtc->pipe;
4837 if (crtc->config->pch_pfit.enabled) {
4838 /* Force use of hard-coded filter coefficients
4839 * as some pre-programmed values are broken,
4842 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4843 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4844 PF_PIPE_SEL_IVB(pipe));
4846 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4847 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4848 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4852 void hsw_enable_ips(struct intel_crtc *crtc)
4854 struct drm_device *dev = crtc->base.dev;
4855 struct drm_i915_private *dev_priv = to_i915(dev);
4857 if (!crtc->config->ips_enabled)
4861 * We can only enable IPS after we enable a plane and wait for a vblank
4862 * This function is called from post_plane_update, which is run after
4866 assert_plane_enabled(dev_priv, crtc->plane);
4867 if (IS_BROADWELL(dev)) {
4868 mutex_lock(&dev_priv->rps.hw_lock);
4869 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4870 mutex_unlock(&dev_priv->rps.hw_lock);
4871 /* Quoting Art Runyan: "its not safe to expect any particular
4872 * value in IPS_CTL bit 31 after enabling IPS through the
4873 * mailbox." Moreover, the mailbox may return a bogus state,
4874 * so we need to just enable it and continue on.
4877 I915_WRITE(IPS_CTL, IPS_ENABLE);
4878 /* The bit only becomes 1 in the next vblank, so this wait here
4879 * is essentially intel_wait_for_vblank. If we don't have this
4880 * and don't wait for vblanks until the end of crtc_enable, then
4881 * the HW state readout code will complain that the expected
4882 * IPS_CTL value is not the one we read. */
4883 if (intel_wait_for_register(dev_priv,
4884 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4886 DRM_ERROR("Timed out waiting for IPS enable\n");
4890 void hsw_disable_ips(struct intel_crtc *crtc)
4892 struct drm_device *dev = crtc->base.dev;
4893 struct drm_i915_private *dev_priv = to_i915(dev);
4895 if (!crtc->config->ips_enabled)
4898 assert_plane_enabled(dev_priv, crtc->plane);
4899 if (IS_BROADWELL(dev)) {
4900 mutex_lock(&dev_priv->rps.hw_lock);
4901 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4902 mutex_unlock(&dev_priv->rps.hw_lock);
4903 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4904 if (intel_wait_for_register(dev_priv,
4905 IPS_CTL, IPS_ENABLE, 0,
4907 DRM_ERROR("Timed out waiting for IPS disable\n");
4909 I915_WRITE(IPS_CTL, 0);
4910 POSTING_READ(IPS_CTL);
4913 /* We need to wait for a vblank before we can disable the plane. */
4914 intel_wait_for_vblank(dev, crtc->pipe);
4917 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4919 if (intel_crtc->overlay) {
4920 struct drm_device *dev = intel_crtc->base.dev;
4921 struct drm_i915_private *dev_priv = to_i915(dev);
4923 mutex_lock(&dev->struct_mutex);
4924 dev_priv->mm.interruptible = false;
4925 (void) intel_overlay_switch_off(intel_crtc->overlay);
4926 dev_priv->mm.interruptible = true;
4927 mutex_unlock(&dev->struct_mutex);
4930 /* Let userspace switch the overlay on again. In most cases userspace
4931 * has to recompute where to put it anyway.
4936 * intel_post_enable_primary - Perform operations after enabling primary plane
4937 * @crtc: the CRTC whose primary plane was just enabled
4939 * Performs potentially sleeping operations that must be done after the primary
4940 * plane is enabled, such as updating FBC and IPS. Note that this may be
4941 * called due to an explicit primary plane update, or due to an implicit
4942 * re-enable that is caused when a sprite plane is updated to no longer
4943 * completely hide the primary plane.
4946 intel_post_enable_primary(struct drm_crtc *crtc)
4948 struct drm_device *dev = crtc->dev;
4949 struct drm_i915_private *dev_priv = to_i915(dev);
4950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951 int pipe = intel_crtc->pipe;
4954 * FIXME IPS should be fine as long as one plane is
4955 * enabled, but in practice it seems to have problems
4956 * when going from primary only to sprite only and vice
4959 hsw_enable_ips(intel_crtc);
4962 * Gen2 reports pipe underruns whenever all planes are disabled.
4963 * So don't enable underrun reporting before at least some planes
4965 * FIXME: Need to fix the logic to work when we turn off all planes
4966 * but leave the pipe running.
4969 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4971 /* Underruns don't always raise interrupts, so check manually. */
4972 intel_check_cpu_fifo_underruns(dev_priv);
4973 intel_check_pch_fifo_underruns(dev_priv);
4976 /* FIXME move all this to pre_plane_update() with proper state tracking */
4978 intel_pre_disable_primary(struct drm_crtc *crtc)
4980 struct drm_device *dev = crtc->dev;
4981 struct drm_i915_private *dev_priv = to_i915(dev);
4982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983 int pipe = intel_crtc->pipe;
4986 * Gen2 reports pipe underruns whenever all planes are disabled.
4987 * So diasble underrun reporting before all the planes get disabled.
4988 * FIXME: Need to fix the logic to work when we turn off all planes
4989 * but leave the pipe running.
4992 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4995 * FIXME IPS should be fine as long as one plane is
4996 * enabled, but in practice it seems to have problems
4997 * when going from primary only to sprite only and vice
5000 hsw_disable_ips(intel_crtc);
5003 /* FIXME get rid of this and use pre_plane_update */
5005 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5007 struct drm_device *dev = crtc->dev;
5008 struct drm_i915_private *dev_priv = to_i915(dev);
5009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010 int pipe = intel_crtc->pipe;
5012 intel_pre_disable_primary(crtc);
5015 * Vblank time updates from the shadow to live plane control register
5016 * are blocked if the memory self-refresh mode is active at that
5017 * moment. So to make sure the plane gets truly disabled, disable
5018 * first the self-refresh mode. The self-refresh enable bit in turn
5019 * will be checked/applied by the HW only at the next frame start
5020 * event which is after the vblank start event, so we need to have a
5021 * wait-for-vblank between disabling the plane and the pipe.
5023 if (HAS_GMCH_DISPLAY(dev)) {
5024 intel_set_memory_cxsr(dev_priv, false);
5025 dev_priv->wm.vlv.cxsr = false;
5026 intel_wait_for_vblank(dev, pipe);
5030 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5032 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5033 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5034 struct intel_crtc_state *pipe_config =
5035 to_intel_crtc_state(crtc->base.state);
5036 struct drm_plane *primary = crtc->base.primary;
5037 struct drm_plane_state *old_pri_state =
5038 drm_atomic_get_existing_plane_state(old_state, primary);
5040 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5042 crtc->wm.cxsr_allowed = true;
5044 if (pipe_config->update_wm_post && pipe_config->base.active)
5045 intel_update_watermarks(&crtc->base);
5047 if (old_pri_state) {
5048 struct intel_plane_state *primary_state =
5049 to_intel_plane_state(primary->state);
5050 struct intel_plane_state *old_primary_state =
5051 to_intel_plane_state(old_pri_state);
5053 intel_fbc_post_update(crtc);
5055 if (primary_state->visible &&
5056 (needs_modeset(&pipe_config->base) ||
5057 !old_primary_state->visible))
5058 intel_post_enable_primary(&crtc->base);
5062 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5064 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5065 struct drm_device *dev = crtc->base.dev;
5066 struct drm_i915_private *dev_priv = to_i915(dev);
5067 struct intel_crtc_state *pipe_config =
5068 to_intel_crtc_state(crtc->base.state);
5069 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5070 struct drm_plane *primary = crtc->base.primary;
5071 struct drm_plane_state *old_pri_state =
5072 drm_atomic_get_existing_plane_state(old_state, primary);
5073 bool modeset = needs_modeset(&pipe_config->base);
5075 if (old_pri_state) {
5076 struct intel_plane_state *primary_state =
5077 to_intel_plane_state(primary->state);
5078 struct intel_plane_state *old_primary_state =
5079 to_intel_plane_state(old_pri_state);
5081 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5083 if (old_primary_state->visible &&
5084 (modeset || !primary_state->visible))
5085 intel_pre_disable_primary(&crtc->base);
5088 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5089 crtc->wm.cxsr_allowed = false;
5092 * Vblank time updates from the shadow to live plane control register
5093 * are blocked if the memory self-refresh mode is active at that
5094 * moment. So to make sure the plane gets truly disabled, disable
5095 * first the self-refresh mode. The self-refresh enable bit in turn
5096 * will be checked/applied by the HW only at the next frame start
5097 * event which is after the vblank start event, so we need to have a
5098 * wait-for-vblank between disabling the plane and the pipe.
5100 if (old_crtc_state->base.active) {
5101 intel_set_memory_cxsr(dev_priv, false);
5102 dev_priv->wm.vlv.cxsr = false;
5103 intel_wait_for_vblank(dev, crtc->pipe);
5108 * IVB workaround: must disable low power watermarks for at least
5109 * one frame before enabling scaling. LP watermarks can be re-enabled
5110 * when scaling is disabled.
5112 * WaCxSRDisabledForSpriteScaling:ivb
5114 if (pipe_config->disable_lp_wm) {
5115 ilk_disable_lp_wm(dev);
5116 intel_wait_for_vblank(dev, crtc->pipe);
5120 * If we're doing a modeset, we're done. No need to do any pre-vblank
5121 * watermark programming here.
5123 if (needs_modeset(&pipe_config->base))
5127 * For platforms that support atomic watermarks, program the
5128 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5129 * will be the intermediate values that are safe for both pre- and
5130 * post- vblank; when vblank happens, the 'active' values will be set
5131 * to the final 'target' values and we'll do this again to get the
5132 * optimal watermarks. For gen9+ platforms, the values we program here
5133 * will be the final target values which will get automatically latched
5134 * at vblank time; no further programming will be necessary.
5136 * If a platform hasn't been transitioned to atomic watermarks yet,
5137 * we'll continue to update watermarks the old way, if flags tell
5140 if (dev_priv->display.initial_watermarks != NULL)
5141 dev_priv->display.initial_watermarks(pipe_config);
5142 else if (pipe_config->update_wm_pre)
5143 intel_update_watermarks(&crtc->base);
5146 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5148 struct drm_device *dev = crtc->dev;
5149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5150 struct drm_plane *p;
5151 int pipe = intel_crtc->pipe;
5153 intel_crtc_dpms_overlay_disable(intel_crtc);
5155 drm_for_each_plane_mask(p, dev, plane_mask)
5156 to_intel_plane(p)->disable_plane(p, crtc);
5159 * FIXME: Once we grow proper nuclear flip support out of this we need
5160 * to compute the mask of flip planes precisely. For the time being
5161 * consider this a flip to a NULL plane.
5163 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5166 static void ironlake_crtc_enable(struct drm_crtc *crtc)
5168 struct drm_device *dev = crtc->dev;
5169 struct drm_i915_private *dev_priv = to_i915(dev);
5170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5171 struct intel_encoder *encoder;
5172 int pipe = intel_crtc->pipe;
5173 struct intel_crtc_state *pipe_config =
5174 to_intel_crtc_state(crtc->state);
5176 if (WARN_ON(intel_crtc->active))
5180 * Sometimes spurious CPU pipe underruns happen during FDI
5181 * training, at least with VGA+HDMI cloning. Suppress them.
5183 * On ILK we get an occasional spurious CPU pipe underruns
5184 * between eDP port A enable and vdd enable. Also PCH port
5185 * enable seems to result in the occasional CPU pipe underrun.
5187 * Spurious PCH underruns also occur during PCH enabling.
5189 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5190 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5191 if (intel_crtc->config->has_pch_encoder)
5192 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5194 if (intel_crtc->config->has_pch_encoder)
5195 intel_prepare_shared_dpll(intel_crtc);
5197 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5198 intel_dp_set_m_n(intel_crtc, M1_N1);
5200 intel_set_pipe_timings(intel_crtc);
5201 intel_set_pipe_src_size(intel_crtc);
5203 if (intel_crtc->config->has_pch_encoder) {
5204 intel_cpu_transcoder_set_m_n(intel_crtc,
5205 &intel_crtc->config->fdi_m_n, NULL);
5208 ironlake_set_pipeconf(crtc);
5210 intel_crtc->active = true;
5212 for_each_encoder_on_crtc(dev, crtc, encoder)
5213 if (encoder->pre_enable)
5214 encoder->pre_enable(encoder);
5216 if (intel_crtc->config->has_pch_encoder) {
5217 /* Note: FDI PLL enabling _must_ be done before we enable the
5218 * cpu pipes, hence this is separate from all the other fdi/pch
5220 ironlake_fdi_pll_enable(intel_crtc);
5222 assert_fdi_tx_disabled(dev_priv, pipe);
5223 assert_fdi_rx_disabled(dev_priv, pipe);
5226 ironlake_pfit_enable(intel_crtc);
5229 * On ILK+ LUT must be loaded before the pipe is running but with
5232 intel_color_load_luts(&pipe_config->base);
5234 if (dev_priv->display.initial_watermarks != NULL)
5235 dev_priv->display.initial_watermarks(intel_crtc->config);
5236 intel_enable_pipe(intel_crtc);
5238 if (intel_crtc->config->has_pch_encoder)
5239 ironlake_pch_enable(crtc);
5241 assert_vblank_disabled(crtc);
5242 drm_crtc_vblank_on(crtc);
5244 for_each_encoder_on_crtc(dev, crtc, encoder)
5245 encoder->enable(encoder);
5247 if (HAS_PCH_CPT(dev))
5248 cpt_verify_modeset(dev, intel_crtc->pipe);
5250 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5251 if (intel_crtc->config->has_pch_encoder)
5252 intel_wait_for_vblank(dev, pipe);
5253 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5254 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5257 /* IPS only exists on ULT machines and is tied to pipe A. */
5258 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5260 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5263 static void haswell_crtc_enable(struct drm_crtc *crtc)
5265 struct drm_device *dev = crtc->dev;
5266 struct drm_i915_private *dev_priv = to_i915(dev);
5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268 struct intel_encoder *encoder;
5269 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5270 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5271 struct intel_crtc_state *pipe_config =
5272 to_intel_crtc_state(crtc->state);
5274 if (WARN_ON(intel_crtc->active))
5277 if (intel_crtc->config->has_pch_encoder)
5278 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5281 for_each_encoder_on_crtc(dev, crtc, encoder)
5282 if (encoder->pre_pll_enable)
5283 encoder->pre_pll_enable(encoder);
5285 if (intel_crtc->config->shared_dpll)
5286 intel_enable_shared_dpll(intel_crtc);
5288 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5289 intel_dp_set_m_n(intel_crtc, M1_N1);
5291 if (!transcoder_is_dsi(cpu_transcoder))
5292 intel_set_pipe_timings(intel_crtc);
5294 intel_set_pipe_src_size(intel_crtc);
5296 if (cpu_transcoder != TRANSCODER_EDP &&
5297 !transcoder_is_dsi(cpu_transcoder)) {
5298 I915_WRITE(PIPE_MULT(cpu_transcoder),
5299 intel_crtc->config->pixel_multiplier - 1);
5302 if (intel_crtc->config->has_pch_encoder) {
5303 intel_cpu_transcoder_set_m_n(intel_crtc,
5304 &intel_crtc->config->fdi_m_n, NULL);
5307 if (!transcoder_is_dsi(cpu_transcoder))
5308 haswell_set_pipeconf(crtc);
5310 haswell_set_pipemisc(crtc);
5312 intel_color_set_csc(&pipe_config->base);
5314 intel_crtc->active = true;
5316 if (intel_crtc->config->has_pch_encoder)
5317 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5319 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5321 for_each_encoder_on_crtc(dev, crtc, encoder) {
5322 if (encoder->pre_enable)
5323 encoder->pre_enable(encoder);
5326 if (intel_crtc->config->has_pch_encoder)
5327 dev_priv->display.fdi_link_train(crtc);
5329 if (!transcoder_is_dsi(cpu_transcoder))
5330 intel_ddi_enable_pipe_clock(intel_crtc);
5332 if (INTEL_INFO(dev)->gen >= 9)
5333 skylake_pfit_enable(intel_crtc);
5335 ironlake_pfit_enable(intel_crtc);
5338 * On ILK+ LUT must be loaded before the pipe is running but with
5341 intel_color_load_luts(&pipe_config->base);
5343 intel_ddi_set_pipe_settings(crtc);
5344 if (!transcoder_is_dsi(cpu_transcoder))
5345 intel_ddi_enable_transcoder_func(crtc);
5347 if (dev_priv->display.initial_watermarks != NULL)
5348 dev_priv->display.initial_watermarks(pipe_config);
5350 intel_update_watermarks(crtc);
5352 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5353 if (!transcoder_is_dsi(cpu_transcoder))
5354 intel_enable_pipe(intel_crtc);
5356 if (intel_crtc->config->has_pch_encoder)
5357 lpt_pch_enable(crtc);
5359 if (intel_crtc->config->dp_encoder_is_mst)
5360 intel_ddi_set_vc_payload_alloc(crtc, true);
5362 assert_vblank_disabled(crtc);
5363 drm_crtc_vblank_on(crtc);
5365 for_each_encoder_on_crtc(dev, crtc, encoder) {
5366 encoder->enable(encoder);
5367 intel_opregion_notify_encoder(encoder, true);
5370 if (intel_crtc->config->has_pch_encoder) {
5371 intel_wait_for_vblank(dev, pipe);
5372 intel_wait_for_vblank(dev, pipe);
5373 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5374 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5378 /* If we change the relative order between pipe/planes enabling, we need
5379 * to change the workaround. */
5380 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5381 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5382 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5383 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5387 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5389 struct drm_device *dev = crtc->base.dev;
5390 struct drm_i915_private *dev_priv = to_i915(dev);
5391 int pipe = crtc->pipe;
5393 /* To avoid upsetting the power well on haswell only disable the pfit if
5394 * it's in use. The hw state code will make sure we get this right. */
5395 if (force || crtc->config->pch_pfit.enabled) {
5396 I915_WRITE(PF_CTL(pipe), 0);
5397 I915_WRITE(PF_WIN_POS(pipe), 0);
5398 I915_WRITE(PF_WIN_SZ(pipe), 0);
5402 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5404 struct drm_device *dev = crtc->dev;
5405 struct drm_i915_private *dev_priv = to_i915(dev);
5406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5407 struct intel_encoder *encoder;
5408 int pipe = intel_crtc->pipe;
5411 * Sometimes spurious CPU pipe underruns happen when the
5412 * pipe is already disabled, but FDI RX/TX is still enabled.
5413 * Happens at least with VGA+HDMI cloning. Suppress them.
5415 if (intel_crtc->config->has_pch_encoder) {
5416 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5417 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5420 for_each_encoder_on_crtc(dev, crtc, encoder)
5421 encoder->disable(encoder);
5423 drm_crtc_vblank_off(crtc);
5424 assert_vblank_disabled(crtc);
5426 intel_disable_pipe(intel_crtc);
5428 ironlake_pfit_disable(intel_crtc, false);
5430 if (intel_crtc->config->has_pch_encoder)
5431 ironlake_fdi_disable(crtc);
5433 for_each_encoder_on_crtc(dev, crtc, encoder)
5434 if (encoder->post_disable)
5435 encoder->post_disable(encoder);
5437 if (intel_crtc->config->has_pch_encoder) {
5438 ironlake_disable_pch_transcoder(dev_priv, pipe);
5440 if (HAS_PCH_CPT(dev)) {
5444 /* disable TRANS_DP_CTL */
5445 reg = TRANS_DP_CTL(pipe);
5446 temp = I915_READ(reg);
5447 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5448 TRANS_DP_PORT_SEL_MASK);
5449 temp |= TRANS_DP_PORT_SEL_NONE;
5450 I915_WRITE(reg, temp);
5452 /* disable DPLL_SEL */
5453 temp = I915_READ(PCH_DPLL_SEL);
5454 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5455 I915_WRITE(PCH_DPLL_SEL, temp);
5458 ironlake_fdi_pll_disable(intel_crtc);
5461 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5462 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5465 static void haswell_crtc_disable(struct drm_crtc *crtc)
5467 struct drm_device *dev = crtc->dev;
5468 struct drm_i915_private *dev_priv = to_i915(dev);
5469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5470 struct intel_encoder *encoder;
5471 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5473 if (intel_crtc->config->has_pch_encoder)
5474 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5477 for_each_encoder_on_crtc(dev, crtc, encoder) {
5478 intel_opregion_notify_encoder(encoder, false);
5479 encoder->disable(encoder);
5482 drm_crtc_vblank_off(crtc);
5483 assert_vblank_disabled(crtc);
5485 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5486 if (!transcoder_is_dsi(cpu_transcoder))
5487 intel_disable_pipe(intel_crtc);
5489 if (intel_crtc->config->dp_encoder_is_mst)
5490 intel_ddi_set_vc_payload_alloc(crtc, false);
5492 if (!transcoder_is_dsi(cpu_transcoder))
5493 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5495 if (INTEL_INFO(dev)->gen >= 9)
5496 skylake_scaler_disable(intel_crtc);
5498 ironlake_pfit_disable(intel_crtc, false);
5500 if (!transcoder_is_dsi(cpu_transcoder))
5501 intel_ddi_disable_pipe_clock(intel_crtc);
5503 for_each_encoder_on_crtc(dev, crtc, encoder)
5504 if (encoder->post_disable)
5505 encoder->post_disable(encoder);
5507 if (intel_crtc->config->has_pch_encoder) {
5508 lpt_disable_pch_transcoder(dev_priv);
5509 lpt_disable_iclkip(dev_priv);
5510 intel_ddi_fdi_disable(crtc);
5512 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5517 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5519 struct drm_device *dev = crtc->base.dev;
5520 struct drm_i915_private *dev_priv = to_i915(dev);
5521 struct intel_crtc_state *pipe_config = crtc->config;
5523 if (!pipe_config->gmch_pfit.control)
5527 * The panel fitter should only be adjusted whilst the pipe is disabled,
5528 * according to register description and PRM.
5530 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5531 assert_pipe_disabled(dev_priv, crtc->pipe);
5533 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5534 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5536 /* Border color in case we don't scale up to the full screen. Black by
5537 * default, change to something else for debugging. */
5538 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5541 static enum intel_display_power_domain port_to_power_domain(enum port port)
5545 return POWER_DOMAIN_PORT_DDI_A_LANES;
5547 return POWER_DOMAIN_PORT_DDI_B_LANES;
5549 return POWER_DOMAIN_PORT_DDI_C_LANES;
5551 return POWER_DOMAIN_PORT_DDI_D_LANES;
5553 return POWER_DOMAIN_PORT_DDI_E_LANES;
5556 return POWER_DOMAIN_PORT_OTHER;
5560 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5564 return POWER_DOMAIN_AUX_A;
5566 return POWER_DOMAIN_AUX_B;
5568 return POWER_DOMAIN_AUX_C;
5570 return POWER_DOMAIN_AUX_D;
5572 /* FIXME: Check VBT for actual wiring of PORT E */
5573 return POWER_DOMAIN_AUX_D;
5576 return POWER_DOMAIN_AUX_A;
5580 enum intel_display_power_domain
5581 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5583 struct drm_device *dev = intel_encoder->base.dev;
5584 struct intel_digital_port *intel_dig_port;
5586 switch (intel_encoder->type) {
5587 case INTEL_OUTPUT_UNKNOWN:
5588 /* Only DDI platforms should ever use this output type */
5589 WARN_ON_ONCE(!HAS_DDI(dev));
5590 case INTEL_OUTPUT_DP:
5591 case INTEL_OUTPUT_HDMI:
5592 case INTEL_OUTPUT_EDP:
5593 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5594 return port_to_power_domain(intel_dig_port->port);
5595 case INTEL_OUTPUT_DP_MST:
5596 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5597 return port_to_power_domain(intel_dig_port->port);
5598 case INTEL_OUTPUT_ANALOG:
5599 return POWER_DOMAIN_PORT_CRT;
5600 case INTEL_OUTPUT_DSI:
5601 return POWER_DOMAIN_PORT_DSI;
5603 return POWER_DOMAIN_PORT_OTHER;
5607 enum intel_display_power_domain
5608 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5610 struct drm_device *dev = intel_encoder->base.dev;
5611 struct intel_digital_port *intel_dig_port;
5613 switch (intel_encoder->type) {
5614 case INTEL_OUTPUT_UNKNOWN:
5615 case INTEL_OUTPUT_HDMI:
5617 * Only DDI platforms should ever use these output types.
5618 * We can get here after the HDMI detect code has already set
5619 * the type of the shared encoder. Since we can't be sure
5620 * what's the status of the given connectors, play safe and
5621 * run the DP detection too.
5623 WARN_ON_ONCE(!HAS_DDI(dev));
5624 case INTEL_OUTPUT_DP:
5625 case INTEL_OUTPUT_EDP:
5626 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5627 return port_to_aux_power_domain(intel_dig_port->port);
5628 case INTEL_OUTPUT_DP_MST:
5629 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5630 return port_to_aux_power_domain(intel_dig_port->port);
5632 MISSING_CASE(intel_encoder->type);
5633 return POWER_DOMAIN_AUX_A;
5637 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5638 struct intel_crtc_state *crtc_state)
5640 struct drm_device *dev = crtc->dev;
5641 struct drm_encoder *encoder;
5642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5643 enum pipe pipe = intel_crtc->pipe;
5645 enum transcoder transcoder = crtc_state->cpu_transcoder;
5647 if (!crtc_state->base.active)
5650 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5651 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5652 if (crtc_state->pch_pfit.enabled ||
5653 crtc_state->pch_pfit.force_thru)
5654 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5656 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5657 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5659 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5662 if (crtc_state->shared_dpll)
5663 mask |= BIT(POWER_DOMAIN_PLLS);
5668 static unsigned long
5669 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5670 struct intel_crtc_state *crtc_state)
5672 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5674 enum intel_display_power_domain domain;
5675 unsigned long domains, new_domains, old_domains;
5677 old_domains = intel_crtc->enabled_power_domains;
5678 intel_crtc->enabled_power_domains = new_domains =
5679 get_crtc_power_domains(crtc, crtc_state);
5681 domains = new_domains & ~old_domains;
5683 for_each_power_domain(domain, domains)
5684 intel_display_power_get(dev_priv, domain);
5686 return old_domains & ~new_domains;
5689 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5690 unsigned long domains)
5692 enum intel_display_power_domain domain;
5694 for_each_power_domain(domain, domains)
5695 intel_display_power_put(dev_priv, domain);
5698 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5700 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5702 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5703 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5704 return max_cdclk_freq;
5705 else if (IS_CHERRYVIEW(dev_priv))
5706 return max_cdclk_freq*95/100;
5707 else if (INTEL_INFO(dev_priv)->gen < 4)
5708 return 2*max_cdclk_freq*90/100;
5710 return max_cdclk_freq*90/100;
5713 static int skl_calc_cdclk(int max_pixclk, int vco);
5715 static void intel_update_max_cdclk(struct drm_device *dev)
5717 struct drm_i915_private *dev_priv = to_i915(dev);
5719 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5720 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5723 vco = dev_priv->skl_preferred_vco_freq;
5724 WARN_ON(vco != 8100000 && vco != 8640000);
5727 * Use the lower (vco 8640) cdclk values as a
5728 * first guess. skl_calc_cdclk() will correct it
5729 * if the preferred vco is 8100 instead.
5731 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5733 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5735 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5740 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5741 } else if (IS_BROXTON(dev)) {
5742 dev_priv->max_cdclk_freq = 624000;
5743 } else if (IS_BROADWELL(dev)) {
5745 * FIXME with extra cooling we can allow
5746 * 540 MHz for ULX and 675 Mhz for ULT.
5747 * How can we know if extra cooling is
5748 * available? PCI ID, VTB, something else?
5750 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5751 dev_priv->max_cdclk_freq = 450000;
5752 else if (IS_BDW_ULX(dev))
5753 dev_priv->max_cdclk_freq = 450000;
5754 else if (IS_BDW_ULT(dev))
5755 dev_priv->max_cdclk_freq = 540000;
5757 dev_priv->max_cdclk_freq = 675000;
5758 } else if (IS_CHERRYVIEW(dev)) {
5759 dev_priv->max_cdclk_freq = 320000;
5760 } else if (IS_VALLEYVIEW(dev)) {
5761 dev_priv->max_cdclk_freq = 400000;
5763 /* otherwise assume cdclk is fixed */
5764 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5767 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5769 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5770 dev_priv->max_cdclk_freq);
5772 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5773 dev_priv->max_dotclk_freq);
5776 static void intel_update_cdclk(struct drm_device *dev)
5778 struct drm_i915_private *dev_priv = to_i915(dev);
5780 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5782 if (INTEL_GEN(dev_priv) >= 9)
5783 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5784 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5785 dev_priv->cdclk_pll.ref);
5787 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5788 dev_priv->cdclk_freq);
5791 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5792 * Programmng [sic] note: bit[9:2] should be programmed to the number
5793 * of cdclk that generates 4MHz reference clock freq which is used to
5794 * generate GMBus clock. This will vary with the cdclk freq.
5796 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5797 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5800 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5801 static int skl_cdclk_decimal(int cdclk)
5803 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5806 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5810 if (cdclk == dev_priv->cdclk_pll.ref)
5815 MISSING_CASE(cdclk);
5827 return dev_priv->cdclk_pll.ref * ratio;
5830 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5832 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5835 if (intel_wait_for_register(dev_priv,
5836 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5838 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5840 dev_priv->cdclk_pll.vco = 0;
5843 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5845 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5848 val = I915_READ(BXT_DE_PLL_CTL);
5849 val &= ~BXT_DE_PLL_RATIO_MASK;
5850 val |= BXT_DE_PLL_RATIO(ratio);
5851 I915_WRITE(BXT_DE_PLL_CTL, val);
5853 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5856 if (intel_wait_for_register(dev_priv,
5861 DRM_ERROR("timeout waiting for DE PLL lock\n");
5863 dev_priv->cdclk_pll.vco = vco;
5866 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5871 vco = bxt_de_pll_vco(dev_priv, cdclk);
5873 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5875 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5876 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5878 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5881 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5884 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5887 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5890 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5893 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5897 /* Inform power controller of upcoming frequency change */
5898 mutex_lock(&dev_priv->rps.hw_lock);
5899 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5901 mutex_unlock(&dev_priv->rps.hw_lock);
5904 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5909 if (dev_priv->cdclk_pll.vco != 0 &&
5910 dev_priv->cdclk_pll.vco != vco)
5911 bxt_de_pll_disable(dev_priv);
5913 if (dev_priv->cdclk_pll.vco != vco)
5914 bxt_de_pll_enable(dev_priv, vco);
5916 val = divider | skl_cdclk_decimal(cdclk);
5918 * FIXME if only the cd2x divider needs changing, it could be done
5919 * without shutting off the pipe (if only one pipe is active).
5921 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5923 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5926 if (cdclk >= 500000)
5927 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5928 I915_WRITE(CDCLK_CTL, val);
5930 mutex_lock(&dev_priv->rps.hw_lock);
5931 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5932 DIV_ROUND_UP(cdclk, 25000));
5933 mutex_unlock(&dev_priv->rps.hw_lock);
5936 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5941 intel_update_cdclk(&dev_priv->drm);
5944 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5946 u32 cdctl, expected;
5948 intel_update_cdclk(&dev_priv->drm);
5950 if (dev_priv->cdclk_pll.vco == 0 ||
5951 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5954 /* DPLL okay; verify the cdclock
5956 * Some BIOS versions leave an incorrect decimal frequency value and
5957 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5958 * so sanitize this register.
5960 cdctl = I915_READ(CDCLK_CTL);
5962 * Let's ignore the pipe field, since BIOS could have configured the
5963 * dividers both synching to an active pipe, or asynchronously
5966 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5968 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5969 skl_cdclk_decimal(dev_priv->cdclk_freq);
5971 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5974 if (dev_priv->cdclk_freq >= 500000)
5975 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5977 if (cdctl == expected)
5978 /* All well; nothing to sanitize */
5982 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5984 /* force cdclk programming */
5985 dev_priv->cdclk_freq = 0;
5987 /* force full PLL disable + enable */
5988 dev_priv->cdclk_pll.vco = -1;
5991 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5993 bxt_sanitize_cdclk(dev_priv);
5995 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6000 * - The initial CDCLK needs to be read from VBT.
6001 * Need to make this change after VBT has changes for BXT.
6003 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6006 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6008 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6011 static int skl_calc_cdclk(int max_pixclk, int vco)
6013 if (vco == 8640000) {
6014 if (max_pixclk > 540000)
6016 else if (max_pixclk > 432000)
6018 else if (max_pixclk > 308571)
6023 if (max_pixclk > 540000)
6025 else if (max_pixclk > 450000)
6027 else if (max_pixclk > 337500)
6035 skl_dpll0_update(struct drm_i915_private *dev_priv)
6039 dev_priv->cdclk_pll.ref = 24000;
6040 dev_priv->cdclk_pll.vco = 0;
6042 val = I915_READ(LCPLL1_CTL);
6043 if ((val & LCPLL_PLL_ENABLE) == 0)
6046 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6049 val = I915_READ(DPLL_CTRL1);
6051 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6052 DPLL_CTRL1_SSC(SKL_DPLL0) |
6053 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6054 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6057 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6058 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6059 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6060 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6061 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6062 dev_priv->cdclk_pll.vco = 8100000;
6064 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6065 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6066 dev_priv->cdclk_pll.vco = 8640000;
6069 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6074 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6076 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6078 dev_priv->skl_preferred_vco_freq = vco;
6081 intel_update_max_cdclk(&dev_priv->drm);
6085 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6087 int min_cdclk = skl_calc_cdclk(0, vco);
6090 WARN_ON(vco != 8100000 && vco != 8640000);
6092 /* select the minimum CDCLK before enabling DPLL 0 */
6093 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6094 I915_WRITE(CDCLK_CTL, val);
6095 POSTING_READ(CDCLK_CTL);
6098 * We always enable DPLL0 with the lowest link rate possible, but still
6099 * taking into account the VCO required to operate the eDP panel at the
6100 * desired frequency. The usual DP link rates operate with a VCO of
6101 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6102 * The modeset code is responsible for the selection of the exact link
6103 * rate later on, with the constraint of choosing a frequency that
6106 val = I915_READ(DPLL_CTRL1);
6108 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6109 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6110 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6112 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6115 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6118 I915_WRITE(DPLL_CTRL1, val);
6119 POSTING_READ(DPLL_CTRL1);
6121 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6123 if (intel_wait_for_register(dev_priv,
6124 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6126 DRM_ERROR("DPLL0 not locked\n");
6128 dev_priv->cdclk_pll.vco = vco;
6130 /* We'll want to keep using the current vco from now on. */
6131 skl_set_preferred_cdclk_vco(dev_priv, vco);
6135 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6137 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6138 if (intel_wait_for_register(dev_priv,
6139 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6141 DRM_ERROR("Couldn't disable DPLL0\n");
6143 dev_priv->cdclk_pll.vco = 0;
6146 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6151 /* inform PCU we want to change CDCLK */
6152 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6153 mutex_lock(&dev_priv->rps.hw_lock);
6154 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6155 mutex_unlock(&dev_priv->rps.hw_lock);
6157 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6160 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6162 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6165 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6167 struct drm_device *dev = &dev_priv->drm;
6168 u32 freq_select, pcu_ack;
6170 WARN_ON((cdclk == 24000) != (vco == 0));
6172 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6174 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6175 DRM_ERROR("failed to inform PCU about cdclk change\n");
6183 freq_select = CDCLK_FREQ_450_432;
6187 freq_select = CDCLK_FREQ_540;
6193 freq_select = CDCLK_FREQ_337_308;
6198 freq_select = CDCLK_FREQ_675_617;
6203 if (dev_priv->cdclk_pll.vco != 0 &&
6204 dev_priv->cdclk_pll.vco != vco)
6205 skl_dpll0_disable(dev_priv);
6207 if (dev_priv->cdclk_pll.vco != vco)
6208 skl_dpll0_enable(dev_priv, vco);
6210 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6211 POSTING_READ(CDCLK_CTL);
6213 /* inform PCU of the change */
6214 mutex_lock(&dev_priv->rps.hw_lock);
6215 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6216 mutex_unlock(&dev_priv->rps.hw_lock);
6218 intel_update_cdclk(dev);
6221 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6223 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6225 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6228 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6232 skl_sanitize_cdclk(dev_priv);
6234 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6236 * Use the current vco as our initial
6237 * guess as to what the preferred vco is.
6239 if (dev_priv->skl_preferred_vco_freq == 0)
6240 skl_set_preferred_cdclk_vco(dev_priv,
6241 dev_priv->cdclk_pll.vco);
6245 vco = dev_priv->skl_preferred_vco_freq;
6248 cdclk = skl_calc_cdclk(0, vco);
6250 skl_set_cdclk(dev_priv, cdclk, vco);
6253 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6255 uint32_t cdctl, expected;
6258 * check if the pre-os intialized the display
6259 * There is SWF18 scratchpad register defined which is set by the
6260 * pre-os which can be used by the OS drivers to check the status
6262 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6265 intel_update_cdclk(&dev_priv->drm);
6266 /* Is PLL enabled and locked ? */
6267 if (dev_priv->cdclk_pll.vco == 0 ||
6268 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6271 /* DPLL okay; verify the cdclock
6273 * Noticed in some instances that the freq selection is correct but
6274 * decimal part is programmed wrong from BIOS where pre-os does not
6275 * enable display. Verify the same as well.
6277 cdctl = I915_READ(CDCLK_CTL);
6278 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6279 skl_cdclk_decimal(dev_priv->cdclk_freq);
6280 if (cdctl == expected)
6281 /* All well; nothing to sanitize */
6285 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6287 /* force cdclk programming */
6288 dev_priv->cdclk_freq = 0;
6289 /* force full PLL disable + enable */
6290 dev_priv->cdclk_pll.vco = -1;
6293 /* Adjust CDclk dividers to allow high res or save power if possible */
6294 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6296 struct drm_i915_private *dev_priv = to_i915(dev);
6299 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6300 != dev_priv->cdclk_freq);
6302 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6304 else if (cdclk == 266667)
6309 mutex_lock(&dev_priv->rps.hw_lock);
6310 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6311 val &= ~DSPFREQGUAR_MASK;
6312 val |= (cmd << DSPFREQGUAR_SHIFT);
6313 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6314 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6315 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6317 DRM_ERROR("timed out waiting for CDclk change\n");
6319 mutex_unlock(&dev_priv->rps.hw_lock);
6321 mutex_lock(&dev_priv->sb_lock);
6323 if (cdclk == 400000) {
6326 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6328 /* adjust cdclk divider */
6329 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6330 val &= ~CCK_FREQUENCY_VALUES;
6332 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6334 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6335 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6337 DRM_ERROR("timed out waiting for CDclk change\n");
6340 /* adjust self-refresh exit latency value */
6341 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6345 * For high bandwidth configs, we set a higher latency in the bunit
6346 * so that the core display fetch happens in time to avoid underruns.
6348 if (cdclk == 400000)
6349 val |= 4500 / 250; /* 4.5 usec */
6351 val |= 3000 / 250; /* 3.0 usec */
6352 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6354 mutex_unlock(&dev_priv->sb_lock);
6356 intel_update_cdclk(dev);
6359 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6361 struct drm_i915_private *dev_priv = to_i915(dev);
6364 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6365 != dev_priv->cdclk_freq);
6374 MISSING_CASE(cdclk);
6379 * Specs are full of misinformation, but testing on actual
6380 * hardware has shown that we just need to write the desired
6381 * CCK divider into the Punit register.
6383 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6385 mutex_lock(&dev_priv->rps.hw_lock);
6386 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6387 val &= ~DSPFREQGUAR_MASK_CHV;
6388 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6389 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6390 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6391 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6393 DRM_ERROR("timed out waiting for CDclk change\n");
6395 mutex_unlock(&dev_priv->rps.hw_lock);
6397 intel_update_cdclk(dev);
6400 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6403 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6404 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6407 * Really only a few cases to deal with, as only 4 CDclks are supported:
6410 * 320/333MHz (depends on HPLL freq)
6412 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6413 * of the lower bin and adjust if needed.
6415 * We seem to get an unstable or solid color picture at 200MHz.
6416 * Not sure what's wrong. For now use 200MHz only when all pipes
6419 if (!IS_CHERRYVIEW(dev_priv) &&
6420 max_pixclk > freq_320*limit/100)
6422 else if (max_pixclk > 266667*limit/100)
6424 else if (max_pixclk > 0)
6430 static int bxt_calc_cdclk(int max_pixclk)
6432 if (max_pixclk > 576000)
6434 else if (max_pixclk > 384000)
6436 else if (max_pixclk > 288000)
6438 else if (max_pixclk > 144000)
6444 /* Compute the max pixel clock for new configuration. */
6445 static int intel_mode_max_pixclk(struct drm_device *dev,
6446 struct drm_atomic_state *state)
6448 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6449 struct drm_i915_private *dev_priv = to_i915(dev);
6450 struct drm_crtc *crtc;
6451 struct drm_crtc_state *crtc_state;
6452 unsigned max_pixclk = 0, i;
6455 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6456 sizeof(intel_state->min_pixclk));
6458 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6461 if (crtc_state->enable)
6462 pixclk = crtc_state->adjusted_mode.crtc_clock;
6464 intel_state->min_pixclk[i] = pixclk;
6467 for_each_pipe(dev_priv, pipe)
6468 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6473 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6475 struct drm_device *dev = state->dev;
6476 struct drm_i915_private *dev_priv = to_i915(dev);
6477 int max_pixclk = intel_mode_max_pixclk(dev, state);
6478 struct intel_atomic_state *intel_state =
6479 to_intel_atomic_state(state);
6481 intel_state->cdclk = intel_state->dev_cdclk =
6482 valleyview_calc_cdclk(dev_priv, max_pixclk);
6484 if (!intel_state->active_crtcs)
6485 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6490 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6492 int max_pixclk = ilk_max_pixel_rate(state);
6493 struct intel_atomic_state *intel_state =
6494 to_intel_atomic_state(state);
6496 intel_state->cdclk = intel_state->dev_cdclk =
6497 bxt_calc_cdclk(max_pixclk);
6499 if (!intel_state->active_crtcs)
6500 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6505 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6507 unsigned int credits, default_credits;
6509 if (IS_CHERRYVIEW(dev_priv))
6510 default_credits = PFI_CREDIT(12);
6512 default_credits = PFI_CREDIT(8);
6514 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6515 /* CHV suggested value is 31 or 63 */
6516 if (IS_CHERRYVIEW(dev_priv))
6517 credits = PFI_CREDIT_63;
6519 credits = PFI_CREDIT(15);
6521 credits = default_credits;
6525 * WA - write default credits before re-programming
6526 * FIXME: should we also set the resend bit here?
6528 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6531 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6532 credits | PFI_CREDIT_RESEND);
6535 * FIXME is this guaranteed to clear
6536 * immediately or should we poll for it?
6538 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6541 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6543 struct drm_device *dev = old_state->dev;
6544 struct drm_i915_private *dev_priv = to_i915(dev);
6545 struct intel_atomic_state *old_intel_state =
6546 to_intel_atomic_state(old_state);
6547 unsigned req_cdclk = old_intel_state->dev_cdclk;
6550 * FIXME: We can end up here with all power domains off, yet
6551 * with a CDCLK frequency other than the minimum. To account
6552 * for this take the PIPE-A power domain, which covers the HW
6553 * blocks needed for the following programming. This can be
6554 * removed once it's guaranteed that we get here either with
6555 * the minimum CDCLK set, or the required power domains
6558 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6560 if (IS_CHERRYVIEW(dev))
6561 cherryview_set_cdclk(dev, req_cdclk);
6563 valleyview_set_cdclk(dev, req_cdclk);
6565 vlv_program_pfi_credits(dev_priv);
6567 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6570 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6572 struct drm_device *dev = crtc->dev;
6573 struct drm_i915_private *dev_priv = to_i915(dev);
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575 struct intel_encoder *encoder;
6576 struct intel_crtc_state *pipe_config =
6577 to_intel_crtc_state(crtc->state);
6578 int pipe = intel_crtc->pipe;
6580 if (WARN_ON(intel_crtc->active))
6583 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6584 intel_dp_set_m_n(intel_crtc, M1_N1);
6586 intel_set_pipe_timings(intel_crtc);
6587 intel_set_pipe_src_size(intel_crtc);
6589 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6590 struct drm_i915_private *dev_priv = to_i915(dev);
6592 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6593 I915_WRITE(CHV_CANVAS(pipe), 0);
6596 i9xx_set_pipeconf(intel_crtc);
6598 intel_crtc->active = true;
6600 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6602 for_each_encoder_on_crtc(dev, crtc, encoder)
6603 if (encoder->pre_pll_enable)
6604 encoder->pre_pll_enable(encoder);
6606 if (IS_CHERRYVIEW(dev)) {
6607 chv_prepare_pll(intel_crtc, intel_crtc->config);
6608 chv_enable_pll(intel_crtc, intel_crtc->config);
6610 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6611 vlv_enable_pll(intel_crtc, intel_crtc->config);
6614 for_each_encoder_on_crtc(dev, crtc, encoder)
6615 if (encoder->pre_enable)
6616 encoder->pre_enable(encoder);
6618 i9xx_pfit_enable(intel_crtc);
6620 intel_color_load_luts(&pipe_config->base);
6622 intel_update_watermarks(crtc);
6623 intel_enable_pipe(intel_crtc);
6625 assert_vblank_disabled(crtc);
6626 drm_crtc_vblank_on(crtc);
6628 for_each_encoder_on_crtc(dev, crtc, encoder)
6629 encoder->enable(encoder);
6632 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6634 struct drm_device *dev = crtc->base.dev;
6635 struct drm_i915_private *dev_priv = to_i915(dev);
6637 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6638 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6641 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6643 struct drm_device *dev = crtc->dev;
6644 struct drm_i915_private *dev_priv = to_i915(dev);
6645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646 struct intel_encoder *encoder;
6647 struct intel_crtc_state *pipe_config =
6648 to_intel_crtc_state(crtc->state);
6649 enum pipe pipe = intel_crtc->pipe;
6651 if (WARN_ON(intel_crtc->active))
6654 i9xx_set_pll_dividers(intel_crtc);
6656 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6657 intel_dp_set_m_n(intel_crtc, M1_N1);
6659 intel_set_pipe_timings(intel_crtc);
6660 intel_set_pipe_src_size(intel_crtc);
6662 i9xx_set_pipeconf(intel_crtc);
6664 intel_crtc->active = true;
6667 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6669 for_each_encoder_on_crtc(dev, crtc, encoder)
6670 if (encoder->pre_enable)
6671 encoder->pre_enable(encoder);
6673 i9xx_enable_pll(intel_crtc);
6675 i9xx_pfit_enable(intel_crtc);
6677 intel_color_load_luts(&pipe_config->base);
6679 intel_update_watermarks(crtc);
6680 intel_enable_pipe(intel_crtc);
6682 assert_vblank_disabled(crtc);
6683 drm_crtc_vblank_on(crtc);
6685 for_each_encoder_on_crtc(dev, crtc, encoder)
6686 encoder->enable(encoder);
6689 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6691 struct drm_device *dev = crtc->base.dev;
6692 struct drm_i915_private *dev_priv = to_i915(dev);
6694 if (!crtc->config->gmch_pfit.control)
6697 assert_pipe_disabled(dev_priv, crtc->pipe);
6699 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6700 I915_READ(PFIT_CONTROL));
6701 I915_WRITE(PFIT_CONTROL, 0);
6704 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6706 struct drm_device *dev = crtc->dev;
6707 struct drm_i915_private *dev_priv = to_i915(dev);
6708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6709 struct intel_encoder *encoder;
6710 int pipe = intel_crtc->pipe;
6713 * On gen2 planes are double buffered but the pipe isn't, so we must
6714 * wait for planes to fully turn off before disabling the pipe.
6717 intel_wait_for_vblank(dev, pipe);
6719 for_each_encoder_on_crtc(dev, crtc, encoder)
6720 encoder->disable(encoder);
6722 drm_crtc_vblank_off(crtc);
6723 assert_vblank_disabled(crtc);
6725 intel_disable_pipe(intel_crtc);
6727 i9xx_pfit_disable(intel_crtc);
6729 for_each_encoder_on_crtc(dev, crtc, encoder)
6730 if (encoder->post_disable)
6731 encoder->post_disable(encoder);
6733 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6734 if (IS_CHERRYVIEW(dev))
6735 chv_disable_pll(dev_priv, pipe);
6736 else if (IS_VALLEYVIEW(dev))
6737 vlv_disable_pll(dev_priv, pipe);
6739 i9xx_disable_pll(intel_crtc);
6742 for_each_encoder_on_crtc(dev, crtc, encoder)
6743 if (encoder->post_pll_disable)
6744 encoder->post_pll_disable(encoder);
6747 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6750 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6752 struct intel_encoder *encoder;
6753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6754 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6755 enum intel_display_power_domain domain;
6756 unsigned long domains;
6758 if (!intel_crtc->active)
6761 if (to_intel_plane_state(crtc->primary->state)->visible) {
6762 WARN_ON(intel_crtc->flip_work);
6764 intel_pre_disable_primary_noatomic(crtc);
6766 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6767 to_intel_plane_state(crtc->primary->state)->visible = false;
6770 dev_priv->display.crtc_disable(crtc);
6772 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6773 crtc->base.id, crtc->name);
6775 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6776 crtc->state->active = false;
6777 intel_crtc->active = false;
6778 crtc->enabled = false;
6779 crtc->state->connector_mask = 0;
6780 crtc->state->encoder_mask = 0;
6782 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6783 encoder->base.crtc = NULL;
6785 intel_fbc_disable(intel_crtc);
6786 intel_update_watermarks(crtc);
6787 intel_disable_shared_dpll(intel_crtc);
6789 domains = intel_crtc->enabled_power_domains;
6790 for_each_power_domain(domain, domains)
6791 intel_display_power_put(dev_priv, domain);
6792 intel_crtc->enabled_power_domains = 0;
6794 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6795 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6799 * turn all crtc's off, but do not adjust state
6800 * This has to be paired with a call to intel_modeset_setup_hw_state.
6802 int intel_display_suspend(struct drm_device *dev)
6804 struct drm_i915_private *dev_priv = to_i915(dev);
6805 struct drm_atomic_state *state;
6808 state = drm_atomic_helper_suspend(dev);
6809 ret = PTR_ERR_OR_ZERO(state);
6811 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6813 dev_priv->modeset_restore_state = state;
6817 void intel_encoder_destroy(struct drm_encoder *encoder)
6819 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6821 drm_encoder_cleanup(encoder);
6822 kfree(intel_encoder);
6825 /* Cross check the actual hw state with our own modeset state tracking (and it's
6826 * internal consistency). */
6827 static void intel_connector_verify_state(struct intel_connector *connector)
6829 struct drm_crtc *crtc = connector->base.state->crtc;
6831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6832 connector->base.base.id,
6833 connector->base.name);
6835 if (connector->get_hw_state(connector)) {
6836 struct intel_encoder *encoder = connector->encoder;
6837 struct drm_connector_state *conn_state = connector->base.state;
6839 I915_STATE_WARN(!crtc,
6840 "connector enabled without attached crtc\n");
6845 I915_STATE_WARN(!crtc->state->active,
6846 "connector is active, but attached crtc isn't\n");
6848 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6851 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6852 "atomic encoder doesn't match attached encoder\n");
6854 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6855 "attached encoder crtc differs from connector crtc\n");
6857 I915_STATE_WARN(crtc && crtc->state->active,
6858 "attached crtc is active, but connector isn't\n");
6859 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6860 "best encoder set without crtc!\n");
6864 int intel_connector_init(struct intel_connector *connector)
6866 drm_atomic_helper_connector_reset(&connector->base);
6868 if (!connector->base.state)
6874 struct intel_connector *intel_connector_alloc(void)
6876 struct intel_connector *connector;
6878 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6882 if (intel_connector_init(connector) < 0) {
6890 /* Simple connector->get_hw_state implementation for encoders that support only
6891 * one connector and no cloning and hence the encoder state determines the state
6892 * of the connector. */
6893 bool intel_connector_get_hw_state(struct intel_connector *connector)
6896 struct intel_encoder *encoder = connector->encoder;
6898 return encoder->get_hw_state(encoder, &pipe);
6901 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6903 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6904 return crtc_state->fdi_lanes;
6909 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6910 struct intel_crtc_state *pipe_config)
6912 struct drm_atomic_state *state = pipe_config->base.state;
6913 struct intel_crtc *other_crtc;
6914 struct intel_crtc_state *other_crtc_state;
6916 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6917 pipe_name(pipe), pipe_config->fdi_lanes);
6918 if (pipe_config->fdi_lanes > 4) {
6919 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6920 pipe_name(pipe), pipe_config->fdi_lanes);
6924 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6925 if (pipe_config->fdi_lanes > 2) {
6926 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6927 pipe_config->fdi_lanes);
6934 if (INTEL_INFO(dev)->num_pipes == 2)
6937 /* Ivybridge 3 pipe is really complicated */
6942 if (pipe_config->fdi_lanes <= 2)
6945 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6947 intel_atomic_get_crtc_state(state, other_crtc);
6948 if (IS_ERR(other_crtc_state))
6949 return PTR_ERR(other_crtc_state);
6951 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6952 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6953 pipe_name(pipe), pipe_config->fdi_lanes);
6958 if (pipe_config->fdi_lanes > 2) {
6959 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6960 pipe_name(pipe), pipe_config->fdi_lanes);
6964 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6966 intel_atomic_get_crtc_state(state, other_crtc);
6967 if (IS_ERR(other_crtc_state))
6968 return PTR_ERR(other_crtc_state);
6970 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6971 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6981 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6982 struct intel_crtc_state *pipe_config)
6984 struct drm_device *dev = intel_crtc->base.dev;
6985 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6986 int lane, link_bw, fdi_dotclock, ret;
6987 bool needs_recompute = false;
6990 /* FDI is a binary signal running at ~2.7GHz, encoding
6991 * each output octet as 10 bits. The actual frequency
6992 * is stored as a divider into a 100MHz clock, and the
6993 * mode pixel clock is stored in units of 1KHz.
6994 * Hence the bw of each lane in terms of the mode signal
6997 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6999 fdi_dotclock = adjusted_mode->crtc_clock;
7001 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7002 pipe_config->pipe_bpp);
7004 pipe_config->fdi_lanes = lane;
7006 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7007 link_bw, &pipe_config->fdi_m_n);
7009 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7010 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7011 pipe_config->pipe_bpp -= 2*3;
7012 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7013 pipe_config->pipe_bpp);
7014 needs_recompute = true;
7015 pipe_config->bw_constrained = true;
7020 if (needs_recompute)
7026 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7027 struct intel_crtc_state *pipe_config)
7029 if (pipe_config->pipe_bpp > 24)
7032 /* HSW can handle pixel rate up to cdclk? */
7033 if (IS_HASWELL(dev_priv))
7037 * We compare against max which means we must take
7038 * the increased cdclk requirement into account when
7039 * calculating the new cdclk.
7041 * Should measure whether using a lower cdclk w/o IPS
7043 return ilk_pipe_pixel_rate(pipe_config) <=
7044 dev_priv->max_cdclk_freq * 95 / 100;
7047 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7048 struct intel_crtc_state *pipe_config)
7050 struct drm_device *dev = crtc->base.dev;
7051 struct drm_i915_private *dev_priv = to_i915(dev);
7053 pipe_config->ips_enabled = i915.enable_ips &&
7054 hsw_crtc_supports_ips(crtc) &&
7055 pipe_config_supports_ips(dev_priv, pipe_config);
7058 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7060 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7062 /* GDG double wide on either pipe, otherwise pipe A only */
7063 return INTEL_INFO(dev_priv)->gen < 4 &&
7064 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7067 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7068 struct intel_crtc_state *pipe_config)
7070 struct drm_device *dev = crtc->base.dev;
7071 struct drm_i915_private *dev_priv = to_i915(dev);
7072 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7073 int clock_limit = dev_priv->max_dotclk_freq;
7075 if (INTEL_INFO(dev)->gen < 4) {
7076 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7079 * Enable double wide mode when the dot clock
7080 * is > 90% of the (display) core speed.
7082 if (intel_crtc_supports_double_wide(crtc) &&
7083 adjusted_mode->crtc_clock > clock_limit) {
7084 clock_limit = dev_priv->max_dotclk_freq;
7085 pipe_config->double_wide = true;
7089 if (adjusted_mode->crtc_clock > clock_limit) {
7090 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7091 adjusted_mode->crtc_clock, clock_limit,
7092 yesno(pipe_config->double_wide));
7097 * Pipe horizontal size must be even in:
7099 * - LVDS dual channel mode
7100 * - Double wide pipe
7102 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7103 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7104 pipe_config->pipe_src_w &= ~1;
7106 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7107 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7109 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7110 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7114 hsw_compute_ips_config(crtc, pipe_config);
7116 if (pipe_config->has_pch_encoder)
7117 return ironlake_fdi_compute_config(crtc, pipe_config);
7122 static int skylake_get_display_clock_speed(struct drm_device *dev)
7124 struct drm_i915_private *dev_priv = to_i915(dev);
7127 skl_dpll0_update(dev_priv);
7129 if (dev_priv->cdclk_pll.vco == 0)
7130 return dev_priv->cdclk_pll.ref;
7132 cdctl = I915_READ(CDCLK_CTL);
7134 if (dev_priv->cdclk_pll.vco == 8640000) {
7135 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7136 case CDCLK_FREQ_450_432:
7138 case CDCLK_FREQ_337_308:
7140 case CDCLK_FREQ_540:
7142 case CDCLK_FREQ_675_617:
7145 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7148 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7149 case CDCLK_FREQ_450_432:
7151 case CDCLK_FREQ_337_308:
7153 case CDCLK_FREQ_540:
7155 case CDCLK_FREQ_675_617:
7158 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7162 return dev_priv->cdclk_pll.ref;
7165 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7169 dev_priv->cdclk_pll.ref = 19200;
7170 dev_priv->cdclk_pll.vco = 0;
7172 val = I915_READ(BXT_DE_PLL_ENABLE);
7173 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7176 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7179 val = I915_READ(BXT_DE_PLL_CTL);
7180 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7181 dev_priv->cdclk_pll.ref;
7184 static int broxton_get_display_clock_speed(struct drm_device *dev)
7186 struct drm_i915_private *dev_priv = to_i915(dev);
7190 bxt_de_pll_update(dev_priv);
7192 vco = dev_priv->cdclk_pll.vco;
7194 return dev_priv->cdclk_pll.ref;
7196 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7199 case BXT_CDCLK_CD2X_DIV_SEL_1:
7202 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7205 case BXT_CDCLK_CD2X_DIV_SEL_2:
7208 case BXT_CDCLK_CD2X_DIV_SEL_4:
7212 MISSING_CASE(divider);
7213 return dev_priv->cdclk_pll.ref;
7216 return DIV_ROUND_CLOSEST(vco, div);
7219 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7221 struct drm_i915_private *dev_priv = to_i915(dev);
7222 uint32_t lcpll = I915_READ(LCPLL_CTL);
7223 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7225 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7227 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7229 else if (freq == LCPLL_CLK_FREQ_450)
7231 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7233 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7239 static int haswell_get_display_clock_speed(struct drm_device *dev)
7241 struct drm_i915_private *dev_priv = to_i915(dev);
7242 uint32_t lcpll = I915_READ(LCPLL_CTL);
7243 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7245 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7247 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7249 else if (freq == LCPLL_CLK_FREQ_450)
7251 else if (IS_HSW_ULT(dev))
7257 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7259 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7260 CCK_DISPLAY_CLOCK_CONTROL);
7263 static int ilk_get_display_clock_speed(struct drm_device *dev)
7268 static int i945_get_display_clock_speed(struct drm_device *dev)
7273 static int i915_get_display_clock_speed(struct drm_device *dev)
7278 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7283 static int pnv_get_display_clock_speed(struct drm_device *dev)
7287 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7289 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7290 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7292 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7294 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7296 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7299 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7300 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7302 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7307 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7311 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7313 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7316 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7317 case GC_DISPLAY_CLOCK_333_MHZ:
7320 case GC_DISPLAY_CLOCK_190_200_MHZ:
7326 static int i865_get_display_clock_speed(struct drm_device *dev)
7331 static int i85x_get_display_clock_speed(struct drm_device *dev)
7336 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7337 * encoding is different :(
7338 * FIXME is this the right way to detect 852GM/852GMV?
7340 if (dev->pdev->revision == 0x1)
7343 pci_bus_read_config_word(dev->pdev->bus,
7344 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7346 /* Assume that the hardware is in the high speed state. This
7347 * should be the default.
7349 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7350 case GC_CLOCK_133_200:
7351 case GC_CLOCK_133_200_2:
7352 case GC_CLOCK_100_200:
7354 case GC_CLOCK_166_250:
7356 case GC_CLOCK_100_133:
7358 case GC_CLOCK_133_266:
7359 case GC_CLOCK_133_266_2:
7360 case GC_CLOCK_166_266:
7364 /* Shouldn't happen */
7368 static int i830_get_display_clock_speed(struct drm_device *dev)
7373 static unsigned int intel_hpll_vco(struct drm_device *dev)
7375 struct drm_i915_private *dev_priv = to_i915(dev);
7376 static const unsigned int blb_vco[8] = {
7383 static const unsigned int pnv_vco[8] = {
7390 static const unsigned int cl_vco[8] = {
7399 static const unsigned int elk_vco[8] = {
7405 static const unsigned int ctg_vco[8] = {
7413 const unsigned int *vco_table;
7417 /* FIXME other chipsets? */
7419 vco_table = ctg_vco;
7420 else if (IS_G4X(dev))
7421 vco_table = elk_vco;
7422 else if (IS_CRESTLINE(dev))
7424 else if (IS_PINEVIEW(dev))
7425 vco_table = pnv_vco;
7426 else if (IS_G33(dev))
7427 vco_table = blb_vco;
7431 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7433 vco = vco_table[tmp & 0x7];
7435 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7437 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7442 static int gm45_get_display_clock_speed(struct drm_device *dev)
7444 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7447 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7449 cdclk_sel = (tmp >> 12) & 0x1;
7455 return cdclk_sel ? 333333 : 222222;
7457 return cdclk_sel ? 320000 : 228571;
7459 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7464 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7466 static const uint8_t div_3200[] = { 16, 10, 8 };
7467 static const uint8_t div_4000[] = { 20, 12, 10 };
7468 static const uint8_t div_5333[] = { 24, 16, 14 };
7469 const uint8_t *div_table;
7470 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7473 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7475 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7477 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7482 div_table = div_3200;
7485 div_table = div_4000;
7488 div_table = div_5333;
7494 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7497 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7501 static int g33_get_display_clock_speed(struct drm_device *dev)
7503 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7504 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7505 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7506 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7507 const uint8_t *div_table;
7508 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7511 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7513 cdclk_sel = (tmp >> 4) & 0x7;
7515 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7520 div_table = div_3200;
7523 div_table = div_4000;
7526 div_table = div_4800;
7529 div_table = div_5333;
7535 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7538 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7543 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7545 while (*num > DATA_LINK_M_N_MASK ||
7546 *den > DATA_LINK_M_N_MASK) {
7552 static void compute_m_n(unsigned int m, unsigned int n,
7553 uint32_t *ret_m, uint32_t *ret_n)
7555 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7556 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7557 intel_reduce_m_n_ratio(ret_m, ret_n);
7561 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7562 int pixel_clock, int link_clock,
7563 struct intel_link_m_n *m_n)
7567 compute_m_n(bits_per_pixel * pixel_clock,
7568 link_clock * nlanes * 8,
7569 &m_n->gmch_m, &m_n->gmch_n);
7571 compute_m_n(pixel_clock, link_clock,
7572 &m_n->link_m, &m_n->link_n);
7575 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7577 if (i915.panel_use_ssc >= 0)
7578 return i915.panel_use_ssc != 0;
7579 return dev_priv->vbt.lvds_use_ssc
7580 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7583 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7585 return (1 << dpll->n) << 16 | dpll->m2;
7588 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7590 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7593 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7594 struct intel_crtc_state *crtc_state,
7595 struct dpll *reduced_clock)
7597 struct drm_device *dev = crtc->base.dev;
7600 if (IS_PINEVIEW(dev)) {
7601 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7603 fp2 = pnv_dpll_compute_fp(reduced_clock);
7605 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7607 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7610 crtc_state->dpll_hw_state.fp0 = fp;
7612 crtc->lowfreq_avail = false;
7613 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7615 crtc_state->dpll_hw_state.fp1 = fp2;
7616 crtc->lowfreq_avail = true;
7618 crtc_state->dpll_hw_state.fp1 = fp;
7622 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7628 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7629 * and set it to a reasonable value instead.
7631 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7632 reg_val &= 0xffffff00;
7633 reg_val |= 0x00000030;
7634 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7636 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7637 reg_val &= 0x8cffffff;
7638 reg_val = 0x8c000000;
7639 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7641 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7642 reg_val &= 0xffffff00;
7643 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7645 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7646 reg_val &= 0x00ffffff;
7647 reg_val |= 0xb0000000;
7648 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7651 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7652 struct intel_link_m_n *m_n)
7654 struct drm_device *dev = crtc->base.dev;
7655 struct drm_i915_private *dev_priv = to_i915(dev);
7656 int pipe = crtc->pipe;
7658 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7659 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7660 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7661 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7664 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7665 struct intel_link_m_n *m_n,
7666 struct intel_link_m_n *m2_n2)
7668 struct drm_device *dev = crtc->base.dev;
7669 struct drm_i915_private *dev_priv = to_i915(dev);
7670 int pipe = crtc->pipe;
7671 enum transcoder transcoder = crtc->config->cpu_transcoder;
7673 if (INTEL_INFO(dev)->gen >= 5) {
7674 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7675 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7676 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7677 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7678 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7679 * for gen < 8) and if DRRS is supported (to make sure the
7680 * registers are not unnecessarily accessed).
7682 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7683 crtc->config->has_drrs) {
7684 I915_WRITE(PIPE_DATA_M2(transcoder),
7685 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7686 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7687 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7688 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7691 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7692 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7693 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7694 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7698 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7700 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7703 dp_m_n = &crtc->config->dp_m_n;
7704 dp_m2_n2 = &crtc->config->dp_m2_n2;
7705 } else if (m_n == M2_N2) {
7708 * M2_N2 registers are not supported. Hence m2_n2 divider value
7709 * needs to be programmed into M1_N1.
7711 dp_m_n = &crtc->config->dp_m2_n2;
7713 DRM_ERROR("Unsupported divider value\n");
7717 if (crtc->config->has_pch_encoder)
7718 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7720 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7723 static void vlv_compute_dpll(struct intel_crtc *crtc,
7724 struct intel_crtc_state *pipe_config)
7726 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7727 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7728 if (crtc->pipe != PIPE_A)
7729 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7731 /* DPLL not used with DSI, but still need the rest set up */
7732 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7733 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7734 DPLL_EXT_BUFFER_ENABLE_VLV;
7736 pipe_config->dpll_hw_state.dpll_md =
7737 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7740 static void chv_compute_dpll(struct intel_crtc *crtc,
7741 struct intel_crtc_state *pipe_config)
7743 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7744 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7745 if (crtc->pipe != PIPE_A)
7746 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7748 /* DPLL not used with DSI, but still need the rest set up */
7749 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7750 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7752 pipe_config->dpll_hw_state.dpll_md =
7753 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7756 static void vlv_prepare_pll(struct intel_crtc *crtc,
7757 const struct intel_crtc_state *pipe_config)
7759 struct drm_device *dev = crtc->base.dev;
7760 struct drm_i915_private *dev_priv = to_i915(dev);
7761 enum pipe pipe = crtc->pipe;
7763 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7764 u32 coreclk, reg_val;
7767 I915_WRITE(DPLL(pipe),
7768 pipe_config->dpll_hw_state.dpll &
7769 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7771 /* No need to actually set up the DPLL with DSI */
7772 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7775 mutex_lock(&dev_priv->sb_lock);
7777 bestn = pipe_config->dpll.n;
7778 bestm1 = pipe_config->dpll.m1;
7779 bestm2 = pipe_config->dpll.m2;
7780 bestp1 = pipe_config->dpll.p1;
7781 bestp2 = pipe_config->dpll.p2;
7783 /* See eDP HDMI DPIO driver vbios notes doc */
7785 /* PLL B needs special handling */
7787 vlv_pllb_recal_opamp(dev_priv, pipe);
7789 /* Set up Tx target for periodic Rcomp update */
7790 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7792 /* Disable target IRef on PLL */
7793 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7794 reg_val &= 0x00ffffff;
7795 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7797 /* Disable fast lock */
7798 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7800 /* Set idtafcrecal before PLL is enabled */
7801 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7802 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7803 mdiv |= ((bestn << DPIO_N_SHIFT));
7804 mdiv |= (1 << DPIO_K_SHIFT);
7807 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7808 * but we don't support that).
7809 * Note: don't use the DAC post divider as it seems unstable.
7811 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7812 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7814 mdiv |= DPIO_ENABLE_CALIBRATION;
7815 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7817 /* Set HBR and RBR LPF coefficients */
7818 if (pipe_config->port_clock == 162000 ||
7819 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7820 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7821 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7824 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7827 if (intel_crtc_has_dp_encoder(pipe_config)) {
7828 /* Use SSC source */
7830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7833 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7835 } else { /* HDMI or VGA */
7836 /* Use bend source */
7838 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7841 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7845 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7846 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7847 if (intel_crtc_has_dp_encoder(crtc->config))
7848 coreclk |= 0x01000000;
7849 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7851 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7852 mutex_unlock(&dev_priv->sb_lock);
7855 static void chv_prepare_pll(struct intel_crtc *crtc,
7856 const struct intel_crtc_state *pipe_config)
7858 struct drm_device *dev = crtc->base.dev;
7859 struct drm_i915_private *dev_priv = to_i915(dev);
7860 enum pipe pipe = crtc->pipe;
7861 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7862 u32 loopfilter, tribuf_calcntr;
7863 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7867 /* Enable Refclk and SSC */
7868 I915_WRITE(DPLL(pipe),
7869 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7871 /* No need to actually set up the DPLL with DSI */
7872 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7875 bestn = pipe_config->dpll.n;
7876 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7877 bestm1 = pipe_config->dpll.m1;
7878 bestm2 = pipe_config->dpll.m2 >> 22;
7879 bestp1 = pipe_config->dpll.p1;
7880 bestp2 = pipe_config->dpll.p2;
7881 vco = pipe_config->dpll.vco;
7885 mutex_lock(&dev_priv->sb_lock);
7887 /* p1 and p2 divider */
7888 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7889 5 << DPIO_CHV_S1_DIV_SHIFT |
7890 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7891 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7892 1 << DPIO_CHV_K_DIV_SHIFT);
7894 /* Feedback post-divider - m2 */
7895 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7897 /* Feedback refclk divider - n and m1 */
7898 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7899 DPIO_CHV_M1_DIV_BY_2 |
7900 1 << DPIO_CHV_N_DIV_SHIFT);
7902 /* M2 fraction division */
7903 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7905 /* M2 fraction division enable */
7906 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7907 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7908 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7910 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7911 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7913 /* Program digital lock detect threshold */
7914 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7915 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7916 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7917 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7919 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7920 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7923 if (vco == 5400000) {
7924 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7925 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7926 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7927 tribuf_calcntr = 0x9;
7928 } else if (vco <= 6200000) {
7929 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7930 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7931 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7932 tribuf_calcntr = 0x9;
7933 } else if (vco <= 6480000) {
7934 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7935 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7936 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7937 tribuf_calcntr = 0x8;
7939 /* Not supported. Apply the same limits as in the max case */
7940 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7941 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7942 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7945 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7947 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7948 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7949 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7950 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7953 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7954 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7957 mutex_unlock(&dev_priv->sb_lock);
7961 * vlv_force_pll_on - forcibly enable just the PLL
7962 * @dev_priv: i915 private structure
7963 * @pipe: pipe PLL to enable
7964 * @dpll: PLL configuration
7966 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7967 * in cases where we need the PLL enabled even when @pipe is not going to
7970 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7971 const struct dpll *dpll)
7973 struct intel_crtc *crtc =
7974 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7975 struct intel_crtc_state *pipe_config;
7977 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7981 pipe_config->base.crtc = &crtc->base;
7982 pipe_config->pixel_multiplier = 1;
7983 pipe_config->dpll = *dpll;
7985 if (IS_CHERRYVIEW(dev)) {
7986 chv_compute_dpll(crtc, pipe_config);
7987 chv_prepare_pll(crtc, pipe_config);
7988 chv_enable_pll(crtc, pipe_config);
7990 vlv_compute_dpll(crtc, pipe_config);
7991 vlv_prepare_pll(crtc, pipe_config);
7992 vlv_enable_pll(crtc, pipe_config);
8001 * vlv_force_pll_off - forcibly disable just the PLL
8002 * @dev_priv: i915 private structure
8003 * @pipe: pipe PLL to disable
8005 * Disable the PLL for @pipe. To be used in cases where we need
8006 * the PLL enabled even when @pipe is not going to be enabled.
8008 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8010 if (IS_CHERRYVIEW(dev))
8011 chv_disable_pll(to_i915(dev), pipe);
8013 vlv_disable_pll(to_i915(dev), pipe);
8016 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8017 struct intel_crtc_state *crtc_state,
8018 struct dpll *reduced_clock)
8020 struct drm_device *dev = crtc->base.dev;
8021 struct drm_i915_private *dev_priv = to_i915(dev);
8023 struct dpll *clock = &crtc_state->dpll;
8025 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8027 dpll = DPLL_VGA_MODE_DIS;
8029 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8030 dpll |= DPLLB_MODE_LVDS;
8032 dpll |= DPLLB_MODE_DAC_SERIAL;
8034 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8035 dpll |= (crtc_state->pixel_multiplier - 1)
8036 << SDVO_MULTIPLIER_SHIFT_HIRES;
8039 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8040 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8041 dpll |= DPLL_SDVO_HIGH_SPEED;
8043 if (intel_crtc_has_dp_encoder(crtc_state))
8044 dpll |= DPLL_SDVO_HIGH_SPEED;
8046 /* compute bitmask from p1 value */
8047 if (IS_PINEVIEW(dev))
8048 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8050 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8051 if (IS_G4X(dev) && reduced_clock)
8052 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8054 switch (clock->p2) {
8056 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8059 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8062 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8065 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8068 if (INTEL_INFO(dev)->gen >= 4)
8069 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8071 if (crtc_state->sdvo_tv_clock)
8072 dpll |= PLL_REF_INPUT_TVCLKINBC;
8073 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8074 intel_panel_use_ssc(dev_priv))
8075 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8077 dpll |= PLL_REF_INPUT_DREFCLK;
8079 dpll |= DPLL_VCO_ENABLE;
8080 crtc_state->dpll_hw_state.dpll = dpll;
8082 if (INTEL_INFO(dev)->gen >= 4) {
8083 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8084 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8085 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8089 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8090 struct intel_crtc_state *crtc_state,
8091 struct dpll *reduced_clock)
8093 struct drm_device *dev = crtc->base.dev;
8094 struct drm_i915_private *dev_priv = to_i915(dev);
8096 struct dpll *clock = &crtc_state->dpll;
8098 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8100 dpll = DPLL_VGA_MODE_DIS;
8102 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8103 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8106 dpll |= PLL_P1_DIVIDE_BY_TWO;
8108 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8110 dpll |= PLL_P2_DIVIDE_BY_4;
8113 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8114 dpll |= DPLL_DVO_2X_MODE;
8116 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8117 intel_panel_use_ssc(dev_priv))
8118 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8120 dpll |= PLL_REF_INPUT_DREFCLK;
8122 dpll |= DPLL_VCO_ENABLE;
8123 crtc_state->dpll_hw_state.dpll = dpll;
8126 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8128 struct drm_device *dev = intel_crtc->base.dev;
8129 struct drm_i915_private *dev_priv = to_i915(dev);
8130 enum pipe pipe = intel_crtc->pipe;
8131 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8132 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8133 uint32_t crtc_vtotal, crtc_vblank_end;
8136 /* We need to be careful not to changed the adjusted mode, for otherwise
8137 * the hw state checker will get angry at the mismatch. */
8138 crtc_vtotal = adjusted_mode->crtc_vtotal;
8139 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8141 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8142 /* the chip adds 2 halflines automatically */
8144 crtc_vblank_end -= 1;
8146 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8147 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8149 vsyncshift = adjusted_mode->crtc_hsync_start -
8150 adjusted_mode->crtc_htotal / 2;
8152 vsyncshift += adjusted_mode->crtc_htotal;
8155 if (INTEL_INFO(dev)->gen > 3)
8156 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8158 I915_WRITE(HTOTAL(cpu_transcoder),
8159 (adjusted_mode->crtc_hdisplay - 1) |
8160 ((adjusted_mode->crtc_htotal - 1) << 16));
8161 I915_WRITE(HBLANK(cpu_transcoder),
8162 (adjusted_mode->crtc_hblank_start - 1) |
8163 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8164 I915_WRITE(HSYNC(cpu_transcoder),
8165 (adjusted_mode->crtc_hsync_start - 1) |
8166 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8168 I915_WRITE(VTOTAL(cpu_transcoder),
8169 (adjusted_mode->crtc_vdisplay - 1) |
8170 ((crtc_vtotal - 1) << 16));
8171 I915_WRITE(VBLANK(cpu_transcoder),
8172 (adjusted_mode->crtc_vblank_start - 1) |
8173 ((crtc_vblank_end - 1) << 16));
8174 I915_WRITE(VSYNC(cpu_transcoder),
8175 (adjusted_mode->crtc_vsync_start - 1) |
8176 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8178 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8179 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8180 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8182 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8183 (pipe == PIPE_B || pipe == PIPE_C))
8184 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8188 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8190 struct drm_device *dev = intel_crtc->base.dev;
8191 struct drm_i915_private *dev_priv = to_i915(dev);
8192 enum pipe pipe = intel_crtc->pipe;
8194 /* pipesrc controls the size that is scaled from, which should
8195 * always be the user's requested size.
8197 I915_WRITE(PIPESRC(pipe),
8198 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8199 (intel_crtc->config->pipe_src_h - 1));
8202 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8203 struct intel_crtc_state *pipe_config)
8205 struct drm_device *dev = crtc->base.dev;
8206 struct drm_i915_private *dev_priv = to_i915(dev);
8207 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8210 tmp = I915_READ(HTOTAL(cpu_transcoder));
8211 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8212 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8213 tmp = I915_READ(HBLANK(cpu_transcoder));
8214 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8215 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8216 tmp = I915_READ(HSYNC(cpu_transcoder));
8217 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8218 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8220 tmp = I915_READ(VTOTAL(cpu_transcoder));
8221 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8222 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8223 tmp = I915_READ(VBLANK(cpu_transcoder));
8224 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8225 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8226 tmp = I915_READ(VSYNC(cpu_transcoder));
8227 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8228 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8230 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8231 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8232 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8233 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8237 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8238 struct intel_crtc_state *pipe_config)
8240 struct drm_device *dev = crtc->base.dev;
8241 struct drm_i915_private *dev_priv = to_i915(dev);
8244 tmp = I915_READ(PIPESRC(crtc->pipe));
8245 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8246 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8248 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8249 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8252 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8253 struct intel_crtc_state *pipe_config)
8255 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8256 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8257 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8258 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8260 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8261 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8262 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8263 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8265 mode->flags = pipe_config->base.adjusted_mode.flags;
8266 mode->type = DRM_MODE_TYPE_DRIVER;
8268 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8269 mode->flags |= pipe_config->base.adjusted_mode.flags;
8271 mode->hsync = drm_mode_hsync(mode);
8272 mode->vrefresh = drm_mode_vrefresh(mode);
8273 drm_mode_set_name(mode);
8276 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8278 struct drm_device *dev = intel_crtc->base.dev;
8279 struct drm_i915_private *dev_priv = to_i915(dev);
8284 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8285 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8286 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8288 if (intel_crtc->config->double_wide)
8289 pipeconf |= PIPECONF_DOUBLE_WIDE;
8291 /* only g4x and later have fancy bpc/dither controls */
8292 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8293 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8294 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8295 pipeconf |= PIPECONF_DITHER_EN |
8296 PIPECONF_DITHER_TYPE_SP;
8298 switch (intel_crtc->config->pipe_bpp) {
8300 pipeconf |= PIPECONF_6BPC;
8303 pipeconf |= PIPECONF_8BPC;
8306 pipeconf |= PIPECONF_10BPC;
8309 /* Case prevented by intel_choose_pipe_bpp_dither. */
8314 if (HAS_PIPE_CXSR(dev)) {
8315 if (intel_crtc->lowfreq_avail) {
8316 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8317 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8319 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8323 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8324 if (INTEL_INFO(dev)->gen < 4 ||
8325 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8326 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8328 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8330 pipeconf |= PIPECONF_PROGRESSIVE;
8332 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8333 intel_crtc->config->limited_color_range)
8334 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8336 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8337 POSTING_READ(PIPECONF(intel_crtc->pipe));
8340 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8341 struct intel_crtc_state *crtc_state)
8343 struct drm_device *dev = crtc->base.dev;
8344 struct drm_i915_private *dev_priv = to_i915(dev);
8345 const struct intel_limit *limit;
8348 memset(&crtc_state->dpll_hw_state, 0,
8349 sizeof(crtc_state->dpll_hw_state));
8351 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8352 if (intel_panel_use_ssc(dev_priv)) {
8353 refclk = dev_priv->vbt.lvds_ssc_freq;
8354 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8357 limit = &intel_limits_i8xx_lvds;
8358 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8359 limit = &intel_limits_i8xx_dvo;
8361 limit = &intel_limits_i8xx_dac;
8364 if (!crtc_state->clock_set &&
8365 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8366 refclk, NULL, &crtc_state->dpll)) {
8367 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8371 i8xx_compute_dpll(crtc, crtc_state, NULL);
8376 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8377 struct intel_crtc_state *crtc_state)
8379 struct drm_device *dev = crtc->base.dev;
8380 struct drm_i915_private *dev_priv = to_i915(dev);
8381 const struct intel_limit *limit;
8384 memset(&crtc_state->dpll_hw_state, 0,
8385 sizeof(crtc_state->dpll_hw_state));
8387 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8388 if (intel_panel_use_ssc(dev_priv)) {
8389 refclk = dev_priv->vbt.lvds_ssc_freq;
8390 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8393 if (intel_is_dual_link_lvds(dev))
8394 limit = &intel_limits_g4x_dual_channel_lvds;
8396 limit = &intel_limits_g4x_single_channel_lvds;
8397 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8398 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8399 limit = &intel_limits_g4x_hdmi;
8400 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8401 limit = &intel_limits_g4x_sdvo;
8403 /* The option is for other outputs */
8404 limit = &intel_limits_i9xx_sdvo;
8407 if (!crtc_state->clock_set &&
8408 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8409 refclk, NULL, &crtc_state->dpll)) {
8410 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8414 i9xx_compute_dpll(crtc, crtc_state, NULL);
8419 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8420 struct intel_crtc_state *crtc_state)
8422 struct drm_device *dev = crtc->base.dev;
8423 struct drm_i915_private *dev_priv = to_i915(dev);
8424 const struct intel_limit *limit;
8427 memset(&crtc_state->dpll_hw_state, 0,
8428 sizeof(crtc_state->dpll_hw_state));
8430 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8431 if (intel_panel_use_ssc(dev_priv)) {
8432 refclk = dev_priv->vbt.lvds_ssc_freq;
8433 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8436 limit = &intel_limits_pineview_lvds;
8438 limit = &intel_limits_pineview_sdvo;
8441 if (!crtc_state->clock_set &&
8442 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8443 refclk, NULL, &crtc_state->dpll)) {
8444 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8448 i9xx_compute_dpll(crtc, crtc_state, NULL);
8453 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8454 struct intel_crtc_state *crtc_state)
8456 struct drm_device *dev = crtc->base.dev;
8457 struct drm_i915_private *dev_priv = to_i915(dev);
8458 const struct intel_limit *limit;
8461 memset(&crtc_state->dpll_hw_state, 0,
8462 sizeof(crtc_state->dpll_hw_state));
8464 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8465 if (intel_panel_use_ssc(dev_priv)) {
8466 refclk = dev_priv->vbt.lvds_ssc_freq;
8467 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8470 limit = &intel_limits_i9xx_lvds;
8472 limit = &intel_limits_i9xx_sdvo;
8475 if (!crtc_state->clock_set &&
8476 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8477 refclk, NULL, &crtc_state->dpll)) {
8478 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8482 i9xx_compute_dpll(crtc, crtc_state, NULL);
8487 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8488 struct intel_crtc_state *crtc_state)
8490 int refclk = 100000;
8491 const struct intel_limit *limit = &intel_limits_chv;
8493 memset(&crtc_state->dpll_hw_state, 0,
8494 sizeof(crtc_state->dpll_hw_state));
8496 if (!crtc_state->clock_set &&
8497 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8498 refclk, NULL, &crtc_state->dpll)) {
8499 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8503 chv_compute_dpll(crtc, crtc_state);
8508 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8509 struct intel_crtc_state *crtc_state)
8511 int refclk = 100000;
8512 const struct intel_limit *limit = &intel_limits_vlv;
8514 memset(&crtc_state->dpll_hw_state, 0,
8515 sizeof(crtc_state->dpll_hw_state));
8517 if (!crtc_state->clock_set &&
8518 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8519 refclk, NULL, &crtc_state->dpll)) {
8520 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8524 vlv_compute_dpll(crtc, crtc_state);
8529 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8530 struct intel_crtc_state *pipe_config)
8532 struct drm_device *dev = crtc->base.dev;
8533 struct drm_i915_private *dev_priv = to_i915(dev);
8536 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8539 tmp = I915_READ(PFIT_CONTROL);
8540 if (!(tmp & PFIT_ENABLE))
8543 /* Check whether the pfit is attached to our pipe. */
8544 if (INTEL_INFO(dev)->gen < 4) {
8545 if (crtc->pipe != PIPE_B)
8548 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8552 pipe_config->gmch_pfit.control = tmp;
8553 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8556 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8557 struct intel_crtc_state *pipe_config)
8559 struct drm_device *dev = crtc->base.dev;
8560 struct drm_i915_private *dev_priv = to_i915(dev);
8561 int pipe = pipe_config->cpu_transcoder;
8564 int refclk = 100000;
8566 /* In case of DSI, DPLL will not be used */
8567 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8570 mutex_lock(&dev_priv->sb_lock);
8571 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8572 mutex_unlock(&dev_priv->sb_lock);
8574 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8575 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8576 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8577 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8578 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8580 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8584 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8585 struct intel_initial_plane_config *plane_config)
8587 struct drm_device *dev = crtc->base.dev;
8588 struct drm_i915_private *dev_priv = to_i915(dev);
8589 u32 val, base, offset;
8590 int pipe = crtc->pipe, plane = crtc->plane;
8591 int fourcc, pixel_format;
8592 unsigned int aligned_height;
8593 struct drm_framebuffer *fb;
8594 struct intel_framebuffer *intel_fb;
8596 val = I915_READ(DSPCNTR(plane));
8597 if (!(val & DISPLAY_PLANE_ENABLE))
8600 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8602 DRM_DEBUG_KMS("failed to alloc fb\n");
8606 fb = &intel_fb->base;
8608 if (INTEL_INFO(dev)->gen >= 4) {
8609 if (val & DISPPLANE_TILED) {
8610 plane_config->tiling = I915_TILING_X;
8611 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8615 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8616 fourcc = i9xx_format_to_fourcc(pixel_format);
8617 fb->pixel_format = fourcc;
8618 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8620 if (INTEL_INFO(dev)->gen >= 4) {
8621 if (plane_config->tiling)
8622 offset = I915_READ(DSPTILEOFF(plane));
8624 offset = I915_READ(DSPLINOFF(plane));
8625 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8627 base = I915_READ(DSPADDR(plane));
8629 plane_config->base = base;
8631 val = I915_READ(PIPESRC(pipe));
8632 fb->width = ((val >> 16) & 0xfff) + 1;
8633 fb->height = ((val >> 0) & 0xfff) + 1;
8635 val = I915_READ(DSPSTRIDE(pipe));
8636 fb->pitches[0] = val & 0xffffffc0;
8638 aligned_height = intel_fb_align_height(dev, fb->height,
8642 plane_config->size = fb->pitches[0] * aligned_height;
8644 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8645 pipe_name(pipe), plane, fb->width, fb->height,
8646 fb->bits_per_pixel, base, fb->pitches[0],
8647 plane_config->size);
8649 plane_config->fb = intel_fb;
8652 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8653 struct intel_crtc_state *pipe_config)
8655 struct drm_device *dev = crtc->base.dev;
8656 struct drm_i915_private *dev_priv = to_i915(dev);
8657 int pipe = pipe_config->cpu_transcoder;
8658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8660 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8661 int refclk = 100000;
8663 /* In case of DSI, DPLL will not be used */
8664 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8667 mutex_lock(&dev_priv->sb_lock);
8668 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8669 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8670 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8671 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8672 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8673 mutex_unlock(&dev_priv->sb_lock);
8675 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8676 clock.m2 = (pll_dw0 & 0xff) << 22;
8677 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8678 clock.m2 |= pll_dw2 & 0x3fffff;
8679 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8680 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8681 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8683 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8686 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8687 struct intel_crtc_state *pipe_config)
8689 struct drm_device *dev = crtc->base.dev;
8690 struct drm_i915_private *dev_priv = to_i915(dev);
8691 enum intel_display_power_domain power_domain;
8695 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8696 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8699 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8700 pipe_config->shared_dpll = NULL;
8704 tmp = I915_READ(PIPECONF(crtc->pipe));
8705 if (!(tmp & PIPECONF_ENABLE))
8708 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8709 switch (tmp & PIPECONF_BPC_MASK) {
8711 pipe_config->pipe_bpp = 18;
8714 pipe_config->pipe_bpp = 24;
8716 case PIPECONF_10BPC:
8717 pipe_config->pipe_bpp = 30;
8724 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8725 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8726 pipe_config->limited_color_range = true;
8728 if (INTEL_INFO(dev)->gen < 4)
8729 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8731 intel_get_pipe_timings(crtc, pipe_config);
8732 intel_get_pipe_src_size(crtc, pipe_config);
8734 i9xx_get_pfit_config(crtc, pipe_config);
8736 if (INTEL_INFO(dev)->gen >= 4) {
8737 /* No way to read it out on pipes B and C */
8738 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8739 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8741 tmp = I915_READ(DPLL_MD(crtc->pipe));
8742 pipe_config->pixel_multiplier =
8743 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8744 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8745 pipe_config->dpll_hw_state.dpll_md = tmp;
8746 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8747 tmp = I915_READ(DPLL(crtc->pipe));
8748 pipe_config->pixel_multiplier =
8749 ((tmp & SDVO_MULTIPLIER_MASK)
8750 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8752 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8753 * port and will be fixed up in the encoder->get_config
8755 pipe_config->pixel_multiplier = 1;
8757 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8758 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8760 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8761 * on 830. Filter it out here so that we don't
8762 * report errors due to that.
8765 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8767 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8768 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8770 /* Mask out read-only status bits. */
8771 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8772 DPLL_PORTC_READY_MASK |
8773 DPLL_PORTB_READY_MASK);
8776 if (IS_CHERRYVIEW(dev))
8777 chv_crtc_clock_get(crtc, pipe_config);
8778 else if (IS_VALLEYVIEW(dev))
8779 vlv_crtc_clock_get(crtc, pipe_config);
8781 i9xx_crtc_clock_get(crtc, pipe_config);
8784 * Normally the dotclock is filled in by the encoder .get_config()
8785 * but in case the pipe is enabled w/o any ports we need a sane
8788 pipe_config->base.adjusted_mode.crtc_clock =
8789 pipe_config->port_clock / pipe_config->pixel_multiplier;
8794 intel_display_power_put(dev_priv, power_domain);
8799 static void ironlake_init_pch_refclk(struct drm_device *dev)
8801 struct drm_i915_private *dev_priv = to_i915(dev);
8802 struct intel_encoder *encoder;
8805 bool has_lvds = false;
8806 bool has_cpu_edp = false;
8807 bool has_panel = false;
8808 bool has_ck505 = false;
8809 bool can_ssc = false;
8810 bool using_ssc_source = false;
8812 /* We need to take the global config into account */
8813 for_each_intel_encoder(dev, encoder) {
8814 switch (encoder->type) {
8815 case INTEL_OUTPUT_LVDS:
8819 case INTEL_OUTPUT_EDP:
8821 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8829 if (HAS_PCH_IBX(dev)) {
8830 has_ck505 = dev_priv->vbt.display_clock_mode;
8831 can_ssc = has_ck505;
8837 /* Check if any DPLLs are using the SSC source */
8838 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8839 u32 temp = I915_READ(PCH_DPLL(i));
8841 if (!(temp & DPLL_VCO_ENABLE))
8844 if ((temp & PLL_REF_INPUT_MASK) ==
8845 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8846 using_ssc_source = true;
8851 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8852 has_panel, has_lvds, has_ck505, using_ssc_source);
8854 /* Ironlake: try to setup display ref clock before DPLL
8855 * enabling. This is only under driver's control after
8856 * PCH B stepping, previous chipset stepping should be
8857 * ignoring this setting.
8859 val = I915_READ(PCH_DREF_CONTROL);
8861 /* As we must carefully and slowly disable/enable each source in turn,
8862 * compute the final state we want first and check if we need to
8863 * make any changes at all.
8866 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8868 final |= DREF_NONSPREAD_CK505_ENABLE;
8870 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8872 final &= ~DREF_SSC_SOURCE_MASK;
8873 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8874 final &= ~DREF_SSC1_ENABLE;
8877 final |= DREF_SSC_SOURCE_ENABLE;
8879 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8880 final |= DREF_SSC1_ENABLE;
8883 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8884 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8886 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8888 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8889 } else if (using_ssc_source) {
8890 final |= DREF_SSC_SOURCE_ENABLE;
8891 final |= DREF_SSC1_ENABLE;
8897 /* Always enable nonspread source */
8898 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8901 val |= DREF_NONSPREAD_CK505_ENABLE;
8903 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8906 val &= ~DREF_SSC_SOURCE_MASK;
8907 val |= DREF_SSC_SOURCE_ENABLE;
8909 /* SSC must be turned on before enabling the CPU output */
8910 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8911 DRM_DEBUG_KMS("Using SSC on panel\n");
8912 val |= DREF_SSC1_ENABLE;
8914 val &= ~DREF_SSC1_ENABLE;
8916 /* Get SSC going before enabling the outputs */
8917 I915_WRITE(PCH_DREF_CONTROL, val);
8918 POSTING_READ(PCH_DREF_CONTROL);
8921 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8923 /* Enable CPU source on CPU attached eDP */
8925 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8926 DRM_DEBUG_KMS("Using SSC on eDP\n");
8927 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8929 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8931 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8933 I915_WRITE(PCH_DREF_CONTROL, val);
8934 POSTING_READ(PCH_DREF_CONTROL);
8937 DRM_DEBUG_KMS("Disabling CPU source output\n");
8939 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8941 /* Turn off CPU output */
8942 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8944 I915_WRITE(PCH_DREF_CONTROL, val);
8945 POSTING_READ(PCH_DREF_CONTROL);
8948 if (!using_ssc_source) {
8949 DRM_DEBUG_KMS("Disabling SSC source\n");
8951 /* Turn off the SSC source */
8952 val &= ~DREF_SSC_SOURCE_MASK;
8953 val |= DREF_SSC_SOURCE_DISABLE;
8956 val &= ~DREF_SSC1_ENABLE;
8958 I915_WRITE(PCH_DREF_CONTROL, val);
8959 POSTING_READ(PCH_DREF_CONTROL);
8964 BUG_ON(val != final);
8967 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8971 tmp = I915_READ(SOUTH_CHICKEN2);
8972 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8973 I915_WRITE(SOUTH_CHICKEN2, tmp);
8975 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8976 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8977 DRM_ERROR("FDI mPHY reset assert timeout\n");
8979 tmp = I915_READ(SOUTH_CHICKEN2);
8980 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8981 I915_WRITE(SOUTH_CHICKEN2, tmp);
8983 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8984 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8985 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8988 /* WaMPhyProgramming:hsw */
8989 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8993 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8994 tmp &= ~(0xFF << 24);
8995 tmp |= (0x12 << 24);
8996 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8998 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9000 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9002 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9004 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9006 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9007 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9008 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9010 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9011 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9012 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9014 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9017 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9019 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9022 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9024 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9027 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9029 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9032 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9034 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9035 tmp &= ~(0xFF << 16);
9036 tmp |= (0x1C << 16);
9037 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9039 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9040 tmp &= ~(0xFF << 16);
9041 tmp |= (0x1C << 16);
9042 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9044 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9046 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9048 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9050 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9052 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9053 tmp &= ~(0xF << 28);
9055 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9057 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9058 tmp &= ~(0xF << 28);
9060 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9063 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9064 * Programming" based on the parameters passed:
9065 * - Sequence to enable CLKOUT_DP
9066 * - Sequence to enable CLKOUT_DP without spread
9067 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9069 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9072 struct drm_i915_private *dev_priv = to_i915(dev);
9075 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9077 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9080 mutex_lock(&dev_priv->sb_lock);
9082 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9083 tmp &= ~SBI_SSCCTL_DISABLE;
9084 tmp |= SBI_SSCCTL_PATHALT;
9085 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9090 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9091 tmp &= ~SBI_SSCCTL_PATHALT;
9092 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9095 lpt_reset_fdi_mphy(dev_priv);
9096 lpt_program_fdi_mphy(dev_priv);
9100 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9101 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9102 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9103 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9105 mutex_unlock(&dev_priv->sb_lock);
9108 /* Sequence to disable CLKOUT_DP */
9109 static void lpt_disable_clkout_dp(struct drm_device *dev)
9111 struct drm_i915_private *dev_priv = to_i915(dev);
9114 mutex_lock(&dev_priv->sb_lock);
9116 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9117 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9118 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9119 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9121 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9122 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9123 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9124 tmp |= SBI_SSCCTL_PATHALT;
9125 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9128 tmp |= SBI_SSCCTL_DISABLE;
9129 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9132 mutex_unlock(&dev_priv->sb_lock);
9135 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9137 static const uint16_t sscdivintphase[] = {
9138 [BEND_IDX( 50)] = 0x3B23,
9139 [BEND_IDX( 45)] = 0x3B23,
9140 [BEND_IDX( 40)] = 0x3C23,
9141 [BEND_IDX( 35)] = 0x3C23,
9142 [BEND_IDX( 30)] = 0x3D23,
9143 [BEND_IDX( 25)] = 0x3D23,
9144 [BEND_IDX( 20)] = 0x3E23,
9145 [BEND_IDX( 15)] = 0x3E23,
9146 [BEND_IDX( 10)] = 0x3F23,
9147 [BEND_IDX( 5)] = 0x3F23,
9148 [BEND_IDX( 0)] = 0x0025,
9149 [BEND_IDX( -5)] = 0x0025,
9150 [BEND_IDX(-10)] = 0x0125,
9151 [BEND_IDX(-15)] = 0x0125,
9152 [BEND_IDX(-20)] = 0x0225,
9153 [BEND_IDX(-25)] = 0x0225,
9154 [BEND_IDX(-30)] = 0x0325,
9155 [BEND_IDX(-35)] = 0x0325,
9156 [BEND_IDX(-40)] = 0x0425,
9157 [BEND_IDX(-45)] = 0x0425,
9158 [BEND_IDX(-50)] = 0x0525,
9163 * steps -50 to 50 inclusive, in steps of 5
9164 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9165 * change in clock period = -(steps / 10) * 5.787 ps
9167 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9170 int idx = BEND_IDX(steps);
9172 if (WARN_ON(steps % 5 != 0))
9175 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9178 mutex_lock(&dev_priv->sb_lock);
9180 if (steps % 10 != 0)
9184 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9186 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9188 tmp |= sscdivintphase[idx];
9189 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9191 mutex_unlock(&dev_priv->sb_lock);
9196 static void lpt_init_pch_refclk(struct drm_device *dev)
9198 struct intel_encoder *encoder;
9199 bool has_vga = false;
9201 for_each_intel_encoder(dev, encoder) {
9202 switch (encoder->type) {
9203 case INTEL_OUTPUT_ANALOG:
9212 lpt_bend_clkout_dp(to_i915(dev), 0);
9213 lpt_enable_clkout_dp(dev, true, true);
9215 lpt_disable_clkout_dp(dev);
9220 * Initialize reference clocks when the driver loads
9222 void intel_init_pch_refclk(struct drm_device *dev)
9224 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9225 ironlake_init_pch_refclk(dev);
9226 else if (HAS_PCH_LPT(dev))
9227 lpt_init_pch_refclk(dev);
9230 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9232 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9234 int pipe = intel_crtc->pipe;
9239 switch (intel_crtc->config->pipe_bpp) {
9241 val |= PIPECONF_6BPC;
9244 val |= PIPECONF_8BPC;
9247 val |= PIPECONF_10BPC;
9250 val |= PIPECONF_12BPC;
9253 /* Case prevented by intel_choose_pipe_bpp_dither. */
9257 if (intel_crtc->config->dither)
9258 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9260 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9261 val |= PIPECONF_INTERLACED_ILK;
9263 val |= PIPECONF_PROGRESSIVE;
9265 if (intel_crtc->config->limited_color_range)
9266 val |= PIPECONF_COLOR_RANGE_SELECT;
9268 I915_WRITE(PIPECONF(pipe), val);
9269 POSTING_READ(PIPECONF(pipe));
9272 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9274 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9276 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9279 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9280 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9282 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9283 val |= PIPECONF_INTERLACED_ILK;
9285 val |= PIPECONF_PROGRESSIVE;
9287 I915_WRITE(PIPECONF(cpu_transcoder), val);
9288 POSTING_READ(PIPECONF(cpu_transcoder));
9291 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9293 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9296 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9299 switch (intel_crtc->config->pipe_bpp) {
9301 val |= PIPEMISC_DITHER_6_BPC;
9304 val |= PIPEMISC_DITHER_8_BPC;
9307 val |= PIPEMISC_DITHER_10_BPC;
9310 val |= PIPEMISC_DITHER_12_BPC;
9313 /* Case prevented by pipe_config_set_bpp. */
9317 if (intel_crtc->config->dither)
9318 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9320 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9324 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9327 * Account for spread spectrum to avoid
9328 * oversubscribing the link. Max center spread
9329 * is 2.5%; use 5% for safety's sake.
9331 u32 bps = target_clock * bpp * 21 / 20;
9332 return DIV_ROUND_UP(bps, link_bw * 8);
9335 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9337 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9340 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9341 struct intel_crtc_state *crtc_state,
9342 struct dpll *reduced_clock)
9344 struct drm_crtc *crtc = &intel_crtc->base;
9345 struct drm_device *dev = crtc->dev;
9346 struct drm_i915_private *dev_priv = to_i915(dev);
9350 /* Enable autotuning of the PLL clock (if permissible) */
9352 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9353 if ((intel_panel_use_ssc(dev_priv) &&
9354 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9355 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9357 } else if (crtc_state->sdvo_tv_clock)
9360 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9362 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9365 if (reduced_clock) {
9366 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9368 if (reduced_clock->m < factor * reduced_clock->n)
9376 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9377 dpll |= DPLLB_MODE_LVDS;
9379 dpll |= DPLLB_MODE_DAC_SERIAL;
9381 dpll |= (crtc_state->pixel_multiplier - 1)
9382 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9384 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9385 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9386 dpll |= DPLL_SDVO_HIGH_SPEED;
9388 if (intel_crtc_has_dp_encoder(crtc_state))
9389 dpll |= DPLL_SDVO_HIGH_SPEED;
9391 /* compute bitmask from p1 value */
9392 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9394 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9396 switch (crtc_state->dpll.p2) {
9398 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9401 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9404 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9407 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9411 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9412 intel_panel_use_ssc(dev_priv))
9413 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9415 dpll |= PLL_REF_INPUT_DREFCLK;
9417 dpll |= DPLL_VCO_ENABLE;
9419 crtc_state->dpll_hw_state.dpll = dpll;
9420 crtc_state->dpll_hw_state.fp0 = fp;
9421 crtc_state->dpll_hw_state.fp1 = fp2;
9424 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9425 struct intel_crtc_state *crtc_state)
9427 struct drm_device *dev = crtc->base.dev;
9428 struct drm_i915_private *dev_priv = to_i915(dev);
9429 struct dpll reduced_clock;
9430 bool has_reduced_clock = false;
9431 struct intel_shared_dpll *pll;
9432 const struct intel_limit *limit;
9433 int refclk = 120000;
9435 memset(&crtc_state->dpll_hw_state, 0,
9436 sizeof(crtc_state->dpll_hw_state));
9438 crtc->lowfreq_avail = false;
9440 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9441 if (!crtc_state->has_pch_encoder)
9444 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9445 if (intel_panel_use_ssc(dev_priv)) {
9446 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9447 dev_priv->vbt.lvds_ssc_freq);
9448 refclk = dev_priv->vbt.lvds_ssc_freq;
9451 if (intel_is_dual_link_lvds(dev)) {
9452 if (refclk == 100000)
9453 limit = &intel_limits_ironlake_dual_lvds_100m;
9455 limit = &intel_limits_ironlake_dual_lvds;
9457 if (refclk == 100000)
9458 limit = &intel_limits_ironlake_single_lvds_100m;
9460 limit = &intel_limits_ironlake_single_lvds;
9463 limit = &intel_limits_ironlake_dac;
9466 if (!crtc_state->clock_set &&
9467 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9468 refclk, NULL, &crtc_state->dpll)) {
9469 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9473 ironlake_compute_dpll(crtc, crtc_state,
9474 has_reduced_clock ? &reduced_clock : NULL);
9476 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9478 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9479 pipe_name(crtc->pipe));
9483 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9485 crtc->lowfreq_avail = true;
9490 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9491 struct intel_link_m_n *m_n)
9493 struct drm_device *dev = crtc->base.dev;
9494 struct drm_i915_private *dev_priv = to_i915(dev);
9495 enum pipe pipe = crtc->pipe;
9497 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9498 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9499 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9501 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9502 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9503 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9506 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9507 enum transcoder transcoder,
9508 struct intel_link_m_n *m_n,
9509 struct intel_link_m_n *m2_n2)
9511 struct drm_device *dev = crtc->base.dev;
9512 struct drm_i915_private *dev_priv = to_i915(dev);
9513 enum pipe pipe = crtc->pipe;
9515 if (INTEL_INFO(dev)->gen >= 5) {
9516 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9517 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9518 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9520 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9521 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9522 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9523 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9524 * gen < 8) and if DRRS is supported (to make sure the
9525 * registers are not unnecessarily read).
9527 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9528 crtc->config->has_drrs) {
9529 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9530 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9531 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9533 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9534 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9535 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9538 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9539 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9540 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9542 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9543 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9544 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9548 void intel_dp_get_m_n(struct intel_crtc *crtc,
9549 struct intel_crtc_state *pipe_config)
9551 if (pipe_config->has_pch_encoder)
9552 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9554 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9555 &pipe_config->dp_m_n,
9556 &pipe_config->dp_m2_n2);
9559 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9560 struct intel_crtc_state *pipe_config)
9562 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9563 &pipe_config->fdi_m_n, NULL);
9566 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9567 struct intel_crtc_state *pipe_config)
9569 struct drm_device *dev = crtc->base.dev;
9570 struct drm_i915_private *dev_priv = to_i915(dev);
9571 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9572 uint32_t ps_ctrl = 0;
9576 /* find scaler attached to this pipe */
9577 for (i = 0; i < crtc->num_scalers; i++) {
9578 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9579 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9581 pipe_config->pch_pfit.enabled = true;
9582 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9583 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9588 scaler_state->scaler_id = id;
9590 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9592 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9597 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9598 struct intel_initial_plane_config *plane_config)
9600 struct drm_device *dev = crtc->base.dev;
9601 struct drm_i915_private *dev_priv = to_i915(dev);
9602 u32 val, base, offset, stride_mult, tiling;
9603 int pipe = crtc->pipe;
9604 int fourcc, pixel_format;
9605 unsigned int aligned_height;
9606 struct drm_framebuffer *fb;
9607 struct intel_framebuffer *intel_fb;
9609 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9611 DRM_DEBUG_KMS("failed to alloc fb\n");
9615 fb = &intel_fb->base;
9617 val = I915_READ(PLANE_CTL(pipe, 0));
9618 if (!(val & PLANE_CTL_ENABLE))
9621 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9622 fourcc = skl_format_to_fourcc(pixel_format,
9623 val & PLANE_CTL_ORDER_RGBX,
9624 val & PLANE_CTL_ALPHA_MASK);
9625 fb->pixel_format = fourcc;
9626 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9628 tiling = val & PLANE_CTL_TILED_MASK;
9630 case PLANE_CTL_TILED_LINEAR:
9631 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9633 case PLANE_CTL_TILED_X:
9634 plane_config->tiling = I915_TILING_X;
9635 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9637 case PLANE_CTL_TILED_Y:
9638 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9640 case PLANE_CTL_TILED_YF:
9641 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9644 MISSING_CASE(tiling);
9648 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9649 plane_config->base = base;
9651 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9653 val = I915_READ(PLANE_SIZE(pipe, 0));
9654 fb->height = ((val >> 16) & 0xfff) + 1;
9655 fb->width = ((val >> 0) & 0x1fff) + 1;
9657 val = I915_READ(PLANE_STRIDE(pipe, 0));
9658 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9660 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9662 aligned_height = intel_fb_align_height(dev, fb->height,
9666 plane_config->size = fb->pitches[0] * aligned_height;
9668 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9669 pipe_name(pipe), fb->width, fb->height,
9670 fb->bits_per_pixel, base, fb->pitches[0],
9671 plane_config->size);
9673 plane_config->fb = intel_fb;
9680 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9681 struct intel_crtc_state *pipe_config)
9683 struct drm_device *dev = crtc->base.dev;
9684 struct drm_i915_private *dev_priv = to_i915(dev);
9687 tmp = I915_READ(PF_CTL(crtc->pipe));
9689 if (tmp & PF_ENABLE) {
9690 pipe_config->pch_pfit.enabled = true;
9691 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9692 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9694 /* We currently do not free assignements of panel fitters on
9695 * ivb/hsw (since we don't use the higher upscaling modes which
9696 * differentiates them) so just WARN about this case for now. */
9698 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9699 PF_PIPE_SEL_IVB(crtc->pipe));
9705 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9706 struct intel_initial_plane_config *plane_config)
9708 struct drm_device *dev = crtc->base.dev;
9709 struct drm_i915_private *dev_priv = to_i915(dev);
9710 u32 val, base, offset;
9711 int pipe = crtc->pipe;
9712 int fourcc, pixel_format;
9713 unsigned int aligned_height;
9714 struct drm_framebuffer *fb;
9715 struct intel_framebuffer *intel_fb;
9717 val = I915_READ(DSPCNTR(pipe));
9718 if (!(val & DISPLAY_PLANE_ENABLE))
9721 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9723 DRM_DEBUG_KMS("failed to alloc fb\n");
9727 fb = &intel_fb->base;
9729 if (INTEL_INFO(dev)->gen >= 4) {
9730 if (val & DISPPLANE_TILED) {
9731 plane_config->tiling = I915_TILING_X;
9732 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9736 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9737 fourcc = i9xx_format_to_fourcc(pixel_format);
9738 fb->pixel_format = fourcc;
9739 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9741 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9742 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9743 offset = I915_READ(DSPOFFSET(pipe));
9745 if (plane_config->tiling)
9746 offset = I915_READ(DSPTILEOFF(pipe));
9748 offset = I915_READ(DSPLINOFF(pipe));
9750 plane_config->base = base;
9752 val = I915_READ(PIPESRC(pipe));
9753 fb->width = ((val >> 16) & 0xfff) + 1;
9754 fb->height = ((val >> 0) & 0xfff) + 1;
9756 val = I915_READ(DSPSTRIDE(pipe));
9757 fb->pitches[0] = val & 0xffffffc0;
9759 aligned_height = intel_fb_align_height(dev, fb->height,
9763 plane_config->size = fb->pitches[0] * aligned_height;
9765 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9766 pipe_name(pipe), fb->width, fb->height,
9767 fb->bits_per_pixel, base, fb->pitches[0],
9768 plane_config->size);
9770 plane_config->fb = intel_fb;
9773 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9774 struct intel_crtc_state *pipe_config)
9776 struct drm_device *dev = crtc->base.dev;
9777 struct drm_i915_private *dev_priv = to_i915(dev);
9778 enum intel_display_power_domain power_domain;
9782 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9783 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9786 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9787 pipe_config->shared_dpll = NULL;
9790 tmp = I915_READ(PIPECONF(crtc->pipe));
9791 if (!(tmp & PIPECONF_ENABLE))
9794 switch (tmp & PIPECONF_BPC_MASK) {
9796 pipe_config->pipe_bpp = 18;
9799 pipe_config->pipe_bpp = 24;
9801 case PIPECONF_10BPC:
9802 pipe_config->pipe_bpp = 30;
9804 case PIPECONF_12BPC:
9805 pipe_config->pipe_bpp = 36;
9811 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9812 pipe_config->limited_color_range = true;
9814 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9815 struct intel_shared_dpll *pll;
9816 enum intel_dpll_id pll_id;
9818 pipe_config->has_pch_encoder = true;
9820 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9821 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9822 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9824 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9826 if (HAS_PCH_IBX(dev_priv)) {
9828 * The pipe->pch transcoder and pch transcoder->pll
9831 pll_id = (enum intel_dpll_id) crtc->pipe;
9833 tmp = I915_READ(PCH_DPLL_SEL);
9834 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9835 pll_id = DPLL_ID_PCH_PLL_B;
9837 pll_id= DPLL_ID_PCH_PLL_A;
9840 pipe_config->shared_dpll =
9841 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9842 pll = pipe_config->shared_dpll;
9844 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9845 &pipe_config->dpll_hw_state));
9847 tmp = pipe_config->dpll_hw_state.dpll;
9848 pipe_config->pixel_multiplier =
9849 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9850 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9852 ironlake_pch_clock_get(crtc, pipe_config);
9854 pipe_config->pixel_multiplier = 1;
9857 intel_get_pipe_timings(crtc, pipe_config);
9858 intel_get_pipe_src_size(crtc, pipe_config);
9860 ironlake_get_pfit_config(crtc, pipe_config);
9865 intel_display_power_put(dev_priv, power_domain);
9870 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9872 struct drm_device *dev = &dev_priv->drm;
9873 struct intel_crtc *crtc;
9875 for_each_intel_crtc(dev, crtc)
9876 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9877 pipe_name(crtc->pipe));
9879 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9880 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9881 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9882 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9883 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9884 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9885 "CPU PWM1 enabled\n");
9886 if (IS_HASWELL(dev))
9887 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9888 "CPU PWM2 enabled\n");
9889 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9890 "PCH PWM1 enabled\n");
9891 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9892 "Utility pin enabled\n");
9893 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9896 * In theory we can still leave IRQs enabled, as long as only the HPD
9897 * interrupts remain enabled. We used to check for that, but since it's
9898 * gen-specific and since we only disable LCPLL after we fully disable
9899 * the interrupts, the check below should be enough.
9901 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9904 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9906 struct drm_device *dev = &dev_priv->drm;
9908 if (IS_HASWELL(dev))
9909 return I915_READ(D_COMP_HSW);
9911 return I915_READ(D_COMP_BDW);
9914 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9916 struct drm_device *dev = &dev_priv->drm;
9918 if (IS_HASWELL(dev)) {
9919 mutex_lock(&dev_priv->rps.hw_lock);
9920 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9922 DRM_ERROR("Failed to write to D_COMP\n");
9923 mutex_unlock(&dev_priv->rps.hw_lock);
9925 I915_WRITE(D_COMP_BDW, val);
9926 POSTING_READ(D_COMP_BDW);
9931 * This function implements pieces of two sequences from BSpec:
9932 * - Sequence for display software to disable LCPLL
9933 * - Sequence for display software to allow package C8+
9934 * The steps implemented here are just the steps that actually touch the LCPLL
9935 * register. Callers should take care of disabling all the display engine
9936 * functions, doing the mode unset, fixing interrupts, etc.
9938 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9939 bool switch_to_fclk, bool allow_power_down)
9943 assert_can_disable_lcpll(dev_priv);
9945 val = I915_READ(LCPLL_CTL);
9947 if (switch_to_fclk) {
9948 val |= LCPLL_CD_SOURCE_FCLK;
9949 I915_WRITE(LCPLL_CTL, val);
9951 if (wait_for_us(I915_READ(LCPLL_CTL) &
9952 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9953 DRM_ERROR("Switching to FCLK failed\n");
9955 val = I915_READ(LCPLL_CTL);
9958 val |= LCPLL_PLL_DISABLE;
9959 I915_WRITE(LCPLL_CTL, val);
9960 POSTING_READ(LCPLL_CTL);
9962 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9963 DRM_ERROR("LCPLL still locked\n");
9965 val = hsw_read_dcomp(dev_priv);
9966 val |= D_COMP_COMP_DISABLE;
9967 hsw_write_dcomp(dev_priv, val);
9970 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9972 DRM_ERROR("D_COMP RCOMP still in progress\n");
9974 if (allow_power_down) {
9975 val = I915_READ(LCPLL_CTL);
9976 val |= LCPLL_POWER_DOWN_ALLOW;
9977 I915_WRITE(LCPLL_CTL, val);
9978 POSTING_READ(LCPLL_CTL);
9983 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9986 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9990 val = I915_READ(LCPLL_CTL);
9992 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9993 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9997 * Make sure we're not on PC8 state before disabling PC8, otherwise
9998 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10000 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10002 if (val & LCPLL_POWER_DOWN_ALLOW) {
10003 val &= ~LCPLL_POWER_DOWN_ALLOW;
10004 I915_WRITE(LCPLL_CTL, val);
10005 POSTING_READ(LCPLL_CTL);
10008 val = hsw_read_dcomp(dev_priv);
10009 val |= D_COMP_COMP_FORCE;
10010 val &= ~D_COMP_COMP_DISABLE;
10011 hsw_write_dcomp(dev_priv, val);
10013 val = I915_READ(LCPLL_CTL);
10014 val &= ~LCPLL_PLL_DISABLE;
10015 I915_WRITE(LCPLL_CTL, val);
10017 if (intel_wait_for_register(dev_priv,
10018 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10020 DRM_ERROR("LCPLL not locked yet\n");
10022 if (val & LCPLL_CD_SOURCE_FCLK) {
10023 val = I915_READ(LCPLL_CTL);
10024 val &= ~LCPLL_CD_SOURCE_FCLK;
10025 I915_WRITE(LCPLL_CTL, val);
10027 if (wait_for_us((I915_READ(LCPLL_CTL) &
10028 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10029 DRM_ERROR("Switching back to LCPLL failed\n");
10032 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10033 intel_update_cdclk(&dev_priv->drm);
10037 * Package states C8 and deeper are really deep PC states that can only be
10038 * reached when all the devices on the system allow it, so even if the graphics
10039 * device allows PC8+, it doesn't mean the system will actually get to these
10040 * states. Our driver only allows PC8+ when going into runtime PM.
10042 * The requirements for PC8+ are that all the outputs are disabled, the power
10043 * well is disabled and most interrupts are disabled, and these are also
10044 * requirements for runtime PM. When these conditions are met, we manually do
10045 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10046 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10047 * hang the machine.
10049 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10050 * the state of some registers, so when we come back from PC8+ we need to
10051 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10052 * need to take care of the registers kept by RC6. Notice that this happens even
10053 * if we don't put the device in PCI D3 state (which is what currently happens
10054 * because of the runtime PM support).
10056 * For more, read "Display Sequences for Package C8" on the hardware
10059 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10061 struct drm_device *dev = &dev_priv->drm;
10064 DRM_DEBUG_KMS("Enabling package C8+\n");
10066 if (HAS_PCH_LPT_LP(dev)) {
10067 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10068 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10069 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10072 lpt_disable_clkout_dp(dev);
10073 hsw_disable_lcpll(dev_priv, true, true);
10076 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10078 struct drm_device *dev = &dev_priv->drm;
10081 DRM_DEBUG_KMS("Disabling package C8+\n");
10083 hsw_restore_lcpll(dev_priv);
10084 lpt_init_pch_refclk(dev);
10086 if (HAS_PCH_LPT_LP(dev)) {
10087 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10088 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10089 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10093 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10095 struct drm_device *dev = old_state->dev;
10096 struct intel_atomic_state *old_intel_state =
10097 to_intel_atomic_state(old_state);
10098 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10100 bxt_set_cdclk(to_i915(dev), req_cdclk);
10103 /* compute the max rate for new configuration */
10104 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10106 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10107 struct drm_i915_private *dev_priv = to_i915(state->dev);
10108 struct drm_crtc *crtc;
10109 struct drm_crtc_state *cstate;
10110 struct intel_crtc_state *crtc_state;
10111 unsigned max_pixel_rate = 0, i;
10114 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10115 sizeof(intel_state->min_pixclk));
10117 for_each_crtc_in_state(state, crtc, cstate, i) {
10120 crtc_state = to_intel_crtc_state(cstate);
10121 if (!crtc_state->base.enable) {
10122 intel_state->min_pixclk[i] = 0;
10126 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10128 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10129 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10130 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10132 intel_state->min_pixclk[i] = pixel_rate;
10135 for_each_pipe(dev_priv, pipe)
10136 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10138 return max_pixel_rate;
10141 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10143 struct drm_i915_private *dev_priv = to_i915(dev);
10144 uint32_t val, data;
10147 if (WARN((I915_READ(LCPLL_CTL) &
10148 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10149 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10150 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10151 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10152 "trying to change cdclk frequency with cdclk not enabled\n"))
10155 mutex_lock(&dev_priv->rps.hw_lock);
10156 ret = sandybridge_pcode_write(dev_priv,
10157 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10158 mutex_unlock(&dev_priv->rps.hw_lock);
10160 DRM_ERROR("failed to inform pcode about cdclk change\n");
10164 val = I915_READ(LCPLL_CTL);
10165 val |= LCPLL_CD_SOURCE_FCLK;
10166 I915_WRITE(LCPLL_CTL, val);
10168 if (wait_for_us(I915_READ(LCPLL_CTL) &
10169 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10170 DRM_ERROR("Switching to FCLK failed\n");
10172 val = I915_READ(LCPLL_CTL);
10173 val &= ~LCPLL_CLK_FREQ_MASK;
10177 val |= LCPLL_CLK_FREQ_450;
10181 val |= LCPLL_CLK_FREQ_54O_BDW;
10185 val |= LCPLL_CLK_FREQ_337_5_BDW;
10189 val |= LCPLL_CLK_FREQ_675_BDW;
10193 WARN(1, "invalid cdclk frequency\n");
10197 I915_WRITE(LCPLL_CTL, val);
10199 val = I915_READ(LCPLL_CTL);
10200 val &= ~LCPLL_CD_SOURCE_FCLK;
10201 I915_WRITE(LCPLL_CTL, val);
10203 if (wait_for_us((I915_READ(LCPLL_CTL) &
10204 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10205 DRM_ERROR("Switching back to LCPLL failed\n");
10207 mutex_lock(&dev_priv->rps.hw_lock);
10208 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10209 mutex_unlock(&dev_priv->rps.hw_lock);
10211 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10213 intel_update_cdclk(dev);
10215 WARN(cdclk != dev_priv->cdclk_freq,
10216 "cdclk requested %d kHz but got %d kHz\n",
10217 cdclk, dev_priv->cdclk_freq);
10220 static int broadwell_calc_cdclk(int max_pixclk)
10222 if (max_pixclk > 540000)
10224 else if (max_pixclk > 450000)
10226 else if (max_pixclk > 337500)
10232 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10234 struct drm_i915_private *dev_priv = to_i915(state->dev);
10235 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10236 int max_pixclk = ilk_max_pixel_rate(state);
10240 * FIXME should also account for plane ratio
10241 * once 64bpp pixel formats are supported.
10243 cdclk = broadwell_calc_cdclk(max_pixclk);
10245 if (cdclk > dev_priv->max_cdclk_freq) {
10246 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10247 cdclk, dev_priv->max_cdclk_freq);
10251 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10252 if (!intel_state->active_crtcs)
10253 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10258 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10260 struct drm_device *dev = old_state->dev;
10261 struct intel_atomic_state *old_intel_state =
10262 to_intel_atomic_state(old_state);
10263 unsigned req_cdclk = old_intel_state->dev_cdclk;
10265 broadwell_set_cdclk(dev, req_cdclk);
10268 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10270 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10271 struct drm_i915_private *dev_priv = to_i915(state->dev);
10272 const int max_pixclk = ilk_max_pixel_rate(state);
10273 int vco = intel_state->cdclk_pll_vco;
10277 * FIXME should also account for plane ratio
10278 * once 64bpp pixel formats are supported.
10280 cdclk = skl_calc_cdclk(max_pixclk, vco);
10283 * FIXME move the cdclk caclulation to
10284 * compute_config() so we can fail gracegully.
10286 if (cdclk > dev_priv->max_cdclk_freq) {
10287 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10288 cdclk, dev_priv->max_cdclk_freq);
10289 cdclk = dev_priv->max_cdclk_freq;
10292 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10293 if (!intel_state->active_crtcs)
10294 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10299 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10301 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10302 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10303 unsigned int req_cdclk = intel_state->dev_cdclk;
10304 unsigned int req_vco = intel_state->cdclk_pll_vco;
10306 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10309 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10310 struct intel_crtc_state *crtc_state)
10312 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10313 if (!intel_ddi_pll_select(crtc, crtc_state))
10317 crtc->lowfreq_avail = false;
10322 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10324 struct intel_crtc_state *pipe_config)
10326 enum intel_dpll_id id;
10330 pipe_config->ddi_pll_sel = SKL_DPLL0;
10331 id = DPLL_ID_SKL_DPLL0;
10334 pipe_config->ddi_pll_sel = SKL_DPLL1;
10335 id = DPLL_ID_SKL_DPLL1;
10338 pipe_config->ddi_pll_sel = SKL_DPLL2;
10339 id = DPLL_ID_SKL_DPLL2;
10342 DRM_ERROR("Incorrect port type\n");
10346 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10349 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10351 struct intel_crtc_state *pipe_config)
10353 enum intel_dpll_id id;
10356 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10357 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
10359 switch (pipe_config->ddi_pll_sel) {
10361 id = DPLL_ID_SKL_DPLL0;
10364 id = DPLL_ID_SKL_DPLL1;
10367 id = DPLL_ID_SKL_DPLL2;
10370 id = DPLL_ID_SKL_DPLL3;
10373 MISSING_CASE(pipe_config->ddi_pll_sel);
10377 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10380 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10382 struct intel_crtc_state *pipe_config)
10384 enum intel_dpll_id id;
10386 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10388 switch (pipe_config->ddi_pll_sel) {
10389 case PORT_CLK_SEL_WRPLL1:
10390 id = DPLL_ID_WRPLL1;
10392 case PORT_CLK_SEL_WRPLL2:
10393 id = DPLL_ID_WRPLL2;
10395 case PORT_CLK_SEL_SPLL:
10398 case PORT_CLK_SEL_LCPLL_810:
10399 id = DPLL_ID_LCPLL_810;
10401 case PORT_CLK_SEL_LCPLL_1350:
10402 id = DPLL_ID_LCPLL_1350;
10404 case PORT_CLK_SEL_LCPLL_2700:
10405 id = DPLL_ID_LCPLL_2700;
10408 MISSING_CASE(pipe_config->ddi_pll_sel);
10410 case PORT_CLK_SEL_NONE:
10414 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10417 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10418 struct intel_crtc_state *pipe_config,
10419 unsigned long *power_domain_mask)
10421 struct drm_device *dev = crtc->base.dev;
10422 struct drm_i915_private *dev_priv = to_i915(dev);
10423 enum intel_display_power_domain power_domain;
10427 * The pipe->transcoder mapping is fixed with the exception of the eDP
10428 * transcoder handled below.
10430 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10433 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10434 * consistency and less surprising code; it's in always on power).
10436 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10437 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10438 enum pipe trans_edp_pipe;
10439 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10441 WARN(1, "unknown pipe linked to edp transcoder\n");
10442 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10443 case TRANS_DDI_EDP_INPUT_A_ON:
10444 trans_edp_pipe = PIPE_A;
10446 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10447 trans_edp_pipe = PIPE_B;
10449 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10450 trans_edp_pipe = PIPE_C;
10454 if (trans_edp_pipe == crtc->pipe)
10455 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10458 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10459 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10461 *power_domain_mask |= BIT(power_domain);
10463 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10465 return tmp & PIPECONF_ENABLE;
10468 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10469 struct intel_crtc_state *pipe_config,
10470 unsigned long *power_domain_mask)
10472 struct drm_device *dev = crtc->base.dev;
10473 struct drm_i915_private *dev_priv = to_i915(dev);
10474 enum intel_display_power_domain power_domain;
10476 enum transcoder cpu_transcoder;
10479 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10480 if (port == PORT_A)
10481 cpu_transcoder = TRANSCODER_DSI_A;
10483 cpu_transcoder = TRANSCODER_DSI_C;
10485 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10486 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10488 *power_domain_mask |= BIT(power_domain);
10491 * The PLL needs to be enabled with a valid divider
10492 * configuration, otherwise accessing DSI registers will hang
10493 * the machine. See BSpec North Display Engine
10494 * registers/MIPI[BXT]. We can break out here early, since we
10495 * need the same DSI PLL to be enabled for both DSI ports.
10497 if (!intel_dsi_pll_is_enabled(dev_priv))
10500 /* XXX: this works for video mode only */
10501 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10502 if (!(tmp & DPI_ENABLE))
10505 tmp = I915_READ(MIPI_CTRL(port));
10506 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10509 pipe_config->cpu_transcoder = cpu_transcoder;
10513 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10516 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10517 struct intel_crtc_state *pipe_config)
10519 struct drm_device *dev = crtc->base.dev;
10520 struct drm_i915_private *dev_priv = to_i915(dev);
10521 struct intel_shared_dpll *pll;
10525 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10527 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10529 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10530 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10531 else if (IS_BROXTON(dev))
10532 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10534 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10536 pll = pipe_config->shared_dpll;
10538 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10539 &pipe_config->dpll_hw_state));
10543 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10544 * DDI E. So just check whether this pipe is wired to DDI E and whether
10545 * the PCH transcoder is on.
10547 if (INTEL_INFO(dev)->gen < 9 &&
10548 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10549 pipe_config->has_pch_encoder = true;
10551 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10552 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10553 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10555 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10559 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10560 struct intel_crtc_state *pipe_config)
10562 struct drm_device *dev = crtc->base.dev;
10563 struct drm_i915_private *dev_priv = to_i915(dev);
10564 enum intel_display_power_domain power_domain;
10565 unsigned long power_domain_mask;
10568 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10569 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10571 power_domain_mask = BIT(power_domain);
10573 pipe_config->shared_dpll = NULL;
10575 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10577 if (IS_BROXTON(dev_priv) &&
10578 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10586 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10587 haswell_get_ddi_port_state(crtc, pipe_config);
10588 intel_get_pipe_timings(crtc, pipe_config);
10591 intel_get_pipe_src_size(crtc, pipe_config);
10593 pipe_config->gamma_mode =
10594 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10596 if (INTEL_INFO(dev)->gen >= 9) {
10597 skl_init_scalers(dev, crtc, pipe_config);
10600 if (INTEL_INFO(dev)->gen >= 9) {
10601 pipe_config->scaler_state.scaler_id = -1;
10602 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10605 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10606 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10607 power_domain_mask |= BIT(power_domain);
10608 if (INTEL_INFO(dev)->gen >= 9)
10609 skylake_get_pfit_config(crtc, pipe_config);
10611 ironlake_get_pfit_config(crtc, pipe_config);
10614 if (IS_HASWELL(dev))
10615 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10616 (I915_READ(IPS_CTL) & IPS_ENABLE);
10618 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10619 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10620 pipe_config->pixel_multiplier =
10621 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10623 pipe_config->pixel_multiplier = 1;
10627 for_each_power_domain(power_domain, power_domain_mask)
10628 intel_display_power_put(dev_priv, power_domain);
10633 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10634 const struct intel_plane_state *plane_state)
10636 struct drm_device *dev = crtc->dev;
10637 struct drm_i915_private *dev_priv = to_i915(dev);
10638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10639 uint32_t cntl = 0, size = 0;
10641 if (plane_state && plane_state->visible) {
10642 unsigned int width = plane_state->base.crtc_w;
10643 unsigned int height = plane_state->base.crtc_h;
10644 unsigned int stride = roundup_pow_of_two(width) * 4;
10648 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10659 cntl |= CURSOR_ENABLE |
10660 CURSOR_GAMMA_ENABLE |
10661 CURSOR_FORMAT_ARGB |
10662 CURSOR_STRIDE(stride);
10664 size = (height << 12) | width;
10667 if (intel_crtc->cursor_cntl != 0 &&
10668 (intel_crtc->cursor_base != base ||
10669 intel_crtc->cursor_size != size ||
10670 intel_crtc->cursor_cntl != cntl)) {
10671 /* On these chipsets we can only modify the base/size/stride
10672 * whilst the cursor is disabled.
10674 I915_WRITE(CURCNTR(PIPE_A), 0);
10675 POSTING_READ(CURCNTR(PIPE_A));
10676 intel_crtc->cursor_cntl = 0;
10679 if (intel_crtc->cursor_base != base) {
10680 I915_WRITE(CURBASE(PIPE_A), base);
10681 intel_crtc->cursor_base = base;
10684 if (intel_crtc->cursor_size != size) {
10685 I915_WRITE(CURSIZE, size);
10686 intel_crtc->cursor_size = size;
10689 if (intel_crtc->cursor_cntl != cntl) {
10690 I915_WRITE(CURCNTR(PIPE_A), cntl);
10691 POSTING_READ(CURCNTR(PIPE_A));
10692 intel_crtc->cursor_cntl = cntl;
10696 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10697 const struct intel_plane_state *plane_state)
10699 struct drm_device *dev = crtc->dev;
10700 struct drm_i915_private *dev_priv = to_i915(dev);
10701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702 int pipe = intel_crtc->pipe;
10705 if (plane_state && plane_state->visible) {
10706 cntl = MCURSOR_GAMMA_ENABLE;
10707 switch (plane_state->base.crtc_w) {
10709 cntl |= CURSOR_MODE_64_ARGB_AX;
10712 cntl |= CURSOR_MODE_128_ARGB_AX;
10715 cntl |= CURSOR_MODE_256_ARGB_AX;
10718 MISSING_CASE(plane_state->base.crtc_w);
10721 cntl |= pipe << 28; /* Connect to correct pipe */
10724 cntl |= CURSOR_PIPE_CSC_ENABLE;
10726 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10727 cntl |= CURSOR_ROTATE_180;
10730 if (intel_crtc->cursor_cntl != cntl) {
10731 I915_WRITE(CURCNTR(pipe), cntl);
10732 POSTING_READ(CURCNTR(pipe));
10733 intel_crtc->cursor_cntl = cntl;
10736 /* and commit changes on next vblank */
10737 I915_WRITE(CURBASE(pipe), base);
10738 POSTING_READ(CURBASE(pipe));
10740 intel_crtc->cursor_base = base;
10743 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10744 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10745 const struct intel_plane_state *plane_state)
10747 struct drm_device *dev = crtc->dev;
10748 struct drm_i915_private *dev_priv = to_i915(dev);
10749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10750 int pipe = intel_crtc->pipe;
10751 u32 base = intel_crtc->cursor_addr;
10755 int x = plane_state->base.crtc_x;
10756 int y = plane_state->base.crtc_y;
10759 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10762 pos |= x << CURSOR_X_SHIFT;
10765 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10768 pos |= y << CURSOR_Y_SHIFT;
10770 /* ILK+ do this automagically */
10771 if (HAS_GMCH_DISPLAY(dev) &&
10772 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10773 base += (plane_state->base.crtc_h *
10774 plane_state->base.crtc_w - 1) * 4;
10778 I915_WRITE(CURPOS(pipe), pos);
10780 if (IS_845G(dev) || IS_I865G(dev))
10781 i845_update_cursor(crtc, base, plane_state);
10783 i9xx_update_cursor(crtc, base, plane_state);
10786 static bool cursor_size_ok(struct drm_device *dev,
10787 uint32_t width, uint32_t height)
10789 if (width == 0 || height == 0)
10793 * 845g/865g are special in that they are only limited by
10794 * the width of their cursors, the height is arbitrary up to
10795 * the precision of the register. Everything else requires
10796 * square cursors, limited to a few power-of-two sizes.
10798 if (IS_845G(dev) || IS_I865G(dev)) {
10799 if ((width & 63) != 0)
10802 if (width > (IS_845G(dev) ? 64 : 512))
10808 switch (width | height) {
10823 /* VESA 640x480x72Hz mode to set on the pipe */
10824 static struct drm_display_mode load_detect_mode = {
10825 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10826 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10829 struct drm_framebuffer *
10830 __intel_framebuffer_create(struct drm_device *dev,
10831 struct drm_mode_fb_cmd2 *mode_cmd,
10832 struct drm_i915_gem_object *obj)
10834 struct intel_framebuffer *intel_fb;
10837 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10839 return ERR_PTR(-ENOMEM);
10841 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10845 return &intel_fb->base;
10849 return ERR_PTR(ret);
10852 static struct drm_framebuffer *
10853 intel_framebuffer_create(struct drm_device *dev,
10854 struct drm_mode_fb_cmd2 *mode_cmd,
10855 struct drm_i915_gem_object *obj)
10857 struct drm_framebuffer *fb;
10860 ret = i915_mutex_lock_interruptible(dev);
10862 return ERR_PTR(ret);
10863 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10864 mutex_unlock(&dev->struct_mutex);
10870 intel_framebuffer_pitch_for_width(int width, int bpp)
10872 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10873 return ALIGN(pitch, 64);
10877 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10879 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10880 return PAGE_ALIGN(pitch * mode->vdisplay);
10883 static struct drm_framebuffer *
10884 intel_framebuffer_create_for_mode(struct drm_device *dev,
10885 struct drm_display_mode *mode,
10886 int depth, int bpp)
10888 struct drm_framebuffer *fb;
10889 struct drm_i915_gem_object *obj;
10890 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10892 obj = i915_gem_object_create(dev,
10893 intel_framebuffer_size_for_mode(mode, bpp));
10895 return ERR_CAST(obj);
10897 mode_cmd.width = mode->hdisplay;
10898 mode_cmd.height = mode->vdisplay;
10899 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10901 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10903 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10905 i915_gem_object_put_unlocked(obj);
10910 static struct drm_framebuffer *
10911 mode_fits_in_fbdev(struct drm_device *dev,
10912 struct drm_display_mode *mode)
10914 #ifdef CONFIG_DRM_FBDEV_EMULATION
10915 struct drm_i915_private *dev_priv = to_i915(dev);
10916 struct drm_i915_gem_object *obj;
10917 struct drm_framebuffer *fb;
10919 if (!dev_priv->fbdev)
10922 if (!dev_priv->fbdev->fb)
10925 obj = dev_priv->fbdev->fb->obj;
10928 fb = &dev_priv->fbdev->fb->base;
10929 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10930 fb->bits_per_pixel))
10933 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10936 drm_framebuffer_reference(fb);
10943 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10944 struct drm_crtc *crtc,
10945 struct drm_display_mode *mode,
10946 struct drm_framebuffer *fb,
10949 struct drm_plane_state *plane_state;
10950 int hdisplay, vdisplay;
10953 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10954 if (IS_ERR(plane_state))
10955 return PTR_ERR(plane_state);
10958 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10960 hdisplay = vdisplay = 0;
10962 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10965 drm_atomic_set_fb_for_plane(plane_state, fb);
10966 plane_state->crtc_x = 0;
10967 plane_state->crtc_y = 0;
10968 plane_state->crtc_w = hdisplay;
10969 plane_state->crtc_h = vdisplay;
10970 plane_state->src_x = x << 16;
10971 plane_state->src_y = y << 16;
10972 plane_state->src_w = hdisplay << 16;
10973 plane_state->src_h = vdisplay << 16;
10978 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10979 struct drm_display_mode *mode,
10980 struct intel_load_detect_pipe *old,
10981 struct drm_modeset_acquire_ctx *ctx)
10983 struct intel_crtc *intel_crtc;
10984 struct intel_encoder *intel_encoder =
10985 intel_attached_encoder(connector);
10986 struct drm_crtc *possible_crtc;
10987 struct drm_encoder *encoder = &intel_encoder->base;
10988 struct drm_crtc *crtc = NULL;
10989 struct drm_device *dev = encoder->dev;
10990 struct drm_framebuffer *fb;
10991 struct drm_mode_config *config = &dev->mode_config;
10992 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10993 struct drm_connector_state *connector_state;
10994 struct intel_crtc_state *crtc_state;
10997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10998 connector->base.id, connector->name,
10999 encoder->base.id, encoder->name);
11001 old->restore_state = NULL;
11004 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11009 * Algorithm gets a little messy:
11011 * - if the connector already has an assigned crtc, use it (but make
11012 * sure it's on first)
11014 * - try to find the first unused crtc that can drive this connector,
11015 * and use that if we find one
11018 /* See if we already have a CRTC for this connector */
11019 if (connector->state->crtc) {
11020 crtc = connector->state->crtc;
11022 ret = drm_modeset_lock(&crtc->mutex, ctx);
11026 /* Make sure the crtc and connector are running */
11030 /* Find an unused one (if possible) */
11031 for_each_crtc(dev, possible_crtc) {
11033 if (!(encoder->possible_crtcs & (1 << i)))
11036 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11040 if (possible_crtc->state->enable) {
11041 drm_modeset_unlock(&possible_crtc->mutex);
11045 crtc = possible_crtc;
11050 * If we didn't find an unused CRTC, don't use any.
11053 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11058 intel_crtc = to_intel_crtc(crtc);
11060 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11064 state = drm_atomic_state_alloc(dev);
11065 restore_state = drm_atomic_state_alloc(dev);
11066 if (!state || !restore_state) {
11071 state->acquire_ctx = ctx;
11072 restore_state->acquire_ctx = ctx;
11074 connector_state = drm_atomic_get_connector_state(state, connector);
11075 if (IS_ERR(connector_state)) {
11076 ret = PTR_ERR(connector_state);
11080 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11084 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11085 if (IS_ERR(crtc_state)) {
11086 ret = PTR_ERR(crtc_state);
11090 crtc_state->base.active = crtc_state->base.enable = true;
11093 mode = &load_detect_mode;
11095 /* We need a framebuffer large enough to accommodate all accesses
11096 * that the plane may generate whilst we perform load detection.
11097 * We can not rely on the fbcon either being present (we get called
11098 * during its initialisation to detect all boot displays, or it may
11099 * not even exist) or that it is large enough to satisfy the
11102 fb = mode_fits_in_fbdev(dev, mode);
11104 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11105 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11107 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11109 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11113 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11117 drm_framebuffer_unreference(fb);
11119 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11123 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11125 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11127 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11129 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11133 ret = drm_atomic_commit(state);
11135 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11139 old->restore_state = restore_state;
11141 /* let the connector get through one full cycle before testing */
11142 intel_wait_for_vblank(dev, intel_crtc->pipe);
11146 drm_atomic_state_free(state);
11147 drm_atomic_state_free(restore_state);
11148 restore_state = state = NULL;
11150 if (ret == -EDEADLK) {
11151 drm_modeset_backoff(ctx);
11158 void intel_release_load_detect_pipe(struct drm_connector *connector,
11159 struct intel_load_detect_pipe *old,
11160 struct drm_modeset_acquire_ctx *ctx)
11162 struct intel_encoder *intel_encoder =
11163 intel_attached_encoder(connector);
11164 struct drm_encoder *encoder = &intel_encoder->base;
11165 struct drm_atomic_state *state = old->restore_state;
11168 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11169 connector->base.id, connector->name,
11170 encoder->base.id, encoder->name);
11175 ret = drm_atomic_commit(state);
11177 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11178 drm_atomic_state_free(state);
11182 static int i9xx_pll_refclk(struct drm_device *dev,
11183 const struct intel_crtc_state *pipe_config)
11185 struct drm_i915_private *dev_priv = to_i915(dev);
11186 u32 dpll = pipe_config->dpll_hw_state.dpll;
11188 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11189 return dev_priv->vbt.lvds_ssc_freq;
11190 else if (HAS_PCH_SPLIT(dev))
11192 else if (!IS_GEN2(dev))
11198 /* Returns the clock of the currently programmed mode of the given pipe. */
11199 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11200 struct intel_crtc_state *pipe_config)
11202 struct drm_device *dev = crtc->base.dev;
11203 struct drm_i915_private *dev_priv = to_i915(dev);
11204 int pipe = pipe_config->cpu_transcoder;
11205 u32 dpll = pipe_config->dpll_hw_state.dpll;
11209 int refclk = i9xx_pll_refclk(dev, pipe_config);
11211 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11212 fp = pipe_config->dpll_hw_state.fp0;
11214 fp = pipe_config->dpll_hw_state.fp1;
11216 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11217 if (IS_PINEVIEW(dev)) {
11218 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11219 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11221 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11222 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11225 if (!IS_GEN2(dev)) {
11226 if (IS_PINEVIEW(dev))
11227 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11228 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11230 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11231 DPLL_FPA01_P1_POST_DIV_SHIFT);
11233 switch (dpll & DPLL_MODE_MASK) {
11234 case DPLLB_MODE_DAC_SERIAL:
11235 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11238 case DPLLB_MODE_LVDS:
11239 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11243 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11244 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11248 if (IS_PINEVIEW(dev))
11249 port_clock = pnv_calc_dpll_params(refclk, &clock);
11251 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11253 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11254 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11257 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11258 DPLL_FPA01_P1_POST_DIV_SHIFT);
11260 if (lvds & LVDS_CLKB_POWER_UP)
11265 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11268 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11269 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11271 if (dpll & PLL_P2_DIVIDE_BY_4)
11277 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11281 * This value includes pixel_multiplier. We will use
11282 * port_clock to compute adjusted_mode.crtc_clock in the
11283 * encoder's get_config() function.
11285 pipe_config->port_clock = port_clock;
11288 int intel_dotclock_calculate(int link_freq,
11289 const struct intel_link_m_n *m_n)
11292 * The calculation for the data clock is:
11293 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11294 * But we want to avoid losing precison if possible, so:
11295 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11297 * and the link clock is simpler:
11298 * link_clock = (m * link_clock) / n
11304 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11307 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11308 struct intel_crtc_state *pipe_config)
11310 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11312 /* read out port_clock from the DPLL */
11313 i9xx_crtc_clock_get(crtc, pipe_config);
11316 * In case there is an active pipe without active ports,
11317 * we may need some idea for the dotclock anyway.
11318 * Calculate one based on the FDI configuration.
11320 pipe_config->base.adjusted_mode.crtc_clock =
11321 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11322 &pipe_config->fdi_m_n);
11325 /** Returns the currently programmed mode of the given pipe. */
11326 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11327 struct drm_crtc *crtc)
11329 struct drm_i915_private *dev_priv = to_i915(dev);
11330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11331 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11332 struct drm_display_mode *mode;
11333 struct intel_crtc_state *pipe_config;
11334 int htot = I915_READ(HTOTAL(cpu_transcoder));
11335 int hsync = I915_READ(HSYNC(cpu_transcoder));
11336 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11337 int vsync = I915_READ(VSYNC(cpu_transcoder));
11338 enum pipe pipe = intel_crtc->pipe;
11340 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11344 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11345 if (!pipe_config) {
11351 * Construct a pipe_config sufficient for getting the clock info
11352 * back out of crtc_clock_get.
11354 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11355 * to use a real value here instead.
11357 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11358 pipe_config->pixel_multiplier = 1;
11359 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11360 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11361 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11362 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11364 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11365 mode->hdisplay = (htot & 0xffff) + 1;
11366 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11367 mode->hsync_start = (hsync & 0xffff) + 1;
11368 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11369 mode->vdisplay = (vtot & 0xffff) + 1;
11370 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11371 mode->vsync_start = (vsync & 0xffff) + 1;
11372 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11374 drm_mode_set_name(mode);
11376 kfree(pipe_config);
11381 static void intel_crtc_destroy(struct drm_crtc *crtc)
11383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11384 struct drm_device *dev = crtc->dev;
11385 struct intel_flip_work *work;
11387 spin_lock_irq(&dev->event_lock);
11388 work = intel_crtc->flip_work;
11389 intel_crtc->flip_work = NULL;
11390 spin_unlock_irq(&dev->event_lock);
11393 cancel_work_sync(&work->mmio_work);
11394 cancel_work_sync(&work->unpin_work);
11398 drm_crtc_cleanup(crtc);
11403 static void intel_unpin_work_fn(struct work_struct *__work)
11405 struct intel_flip_work *work =
11406 container_of(__work, struct intel_flip_work, unpin_work);
11407 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11408 struct drm_device *dev = crtc->base.dev;
11409 struct drm_plane *primary = crtc->base.primary;
11411 if (is_mmio_work(work))
11412 flush_work(&work->mmio_work);
11414 mutex_lock(&dev->struct_mutex);
11415 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11416 i915_gem_object_put(work->pending_flip_obj);
11417 mutex_unlock(&dev->struct_mutex);
11419 i915_gem_request_put(work->flip_queued_req);
11421 intel_frontbuffer_flip_complete(to_i915(dev),
11422 to_intel_plane(primary)->frontbuffer_bit);
11423 intel_fbc_post_update(crtc);
11424 drm_framebuffer_unreference(work->old_fb);
11426 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11427 atomic_dec(&crtc->unpin_work_count);
11432 /* Is 'a' after or equal to 'b'? */
11433 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11435 return !((a - b) & 0x80000000);
11438 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11439 struct intel_flip_work *work)
11441 struct drm_device *dev = crtc->base.dev;
11442 struct drm_i915_private *dev_priv = to_i915(dev);
11443 unsigned reset_counter;
11445 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11446 if (crtc->reset_counter != reset_counter)
11450 * The relevant registers doen't exist on pre-ctg.
11451 * As the flip done interrupt doesn't trigger for mmio
11452 * flips on gmch platforms, a flip count check isn't
11453 * really needed there. But since ctg has the registers,
11454 * include it in the check anyway.
11456 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11460 * BDW signals flip done immediately if the plane
11461 * is disabled, even if the plane enable is already
11462 * armed to occur at the next vblank :(
11466 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11467 * used the same base address. In that case the mmio flip might
11468 * have completed, but the CS hasn't even executed the flip yet.
11470 * A flip count check isn't enough as the CS might have updated
11471 * the base address just after start of vblank, but before we
11472 * managed to process the interrupt. This means we'd complete the
11473 * CS flip too soon.
11475 * Combining both checks should get us a good enough result. It may
11476 * still happen that the CS flip has been executed, but has not
11477 * yet actually completed. But in case the base address is the same
11478 * anyway, we don't really care.
11480 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11481 crtc->flip_work->gtt_offset &&
11482 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11483 crtc->flip_work->flip_count);
11487 __pageflip_finished_mmio(struct intel_crtc *crtc,
11488 struct intel_flip_work *work)
11491 * MMIO work completes when vblank is different from
11492 * flip_queued_vblank.
11494 * Reset counter value doesn't matter, this is handled by
11495 * i915_wait_request finishing early, so no need to handle
11498 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11502 static bool pageflip_finished(struct intel_crtc *crtc,
11503 struct intel_flip_work *work)
11505 if (!atomic_read(&work->pending))
11510 if (is_mmio_work(work))
11511 return __pageflip_finished_mmio(crtc, work);
11513 return __pageflip_finished_cs(crtc, work);
11516 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11518 struct drm_device *dev = &dev_priv->drm;
11519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11521 struct intel_flip_work *work;
11522 unsigned long flags;
11524 /* Ignore early vblank irqs */
11529 * This is called both by irq handlers and the reset code (to complete
11530 * lost pageflips) so needs the full irqsave spinlocks.
11532 spin_lock_irqsave(&dev->event_lock, flags);
11533 work = intel_crtc->flip_work;
11535 if (work != NULL &&
11536 !is_mmio_work(work) &&
11537 pageflip_finished(intel_crtc, work))
11538 page_flip_completed(intel_crtc);
11540 spin_unlock_irqrestore(&dev->event_lock, flags);
11543 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11545 struct drm_device *dev = &dev_priv->drm;
11546 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11548 struct intel_flip_work *work;
11549 unsigned long flags;
11551 /* Ignore early vblank irqs */
11556 * This is called both by irq handlers and the reset code (to complete
11557 * lost pageflips) so needs the full irqsave spinlocks.
11559 spin_lock_irqsave(&dev->event_lock, flags);
11560 work = intel_crtc->flip_work;
11562 if (work != NULL &&
11563 is_mmio_work(work) &&
11564 pageflip_finished(intel_crtc, work))
11565 page_flip_completed(intel_crtc);
11567 spin_unlock_irqrestore(&dev->event_lock, flags);
11570 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11571 struct intel_flip_work *work)
11573 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11575 /* Ensure that the work item is consistent when activating it ... */
11576 smp_mb__before_atomic();
11577 atomic_set(&work->pending, 1);
11580 static int intel_gen2_queue_flip(struct drm_device *dev,
11581 struct drm_crtc *crtc,
11582 struct drm_framebuffer *fb,
11583 struct drm_i915_gem_object *obj,
11584 struct drm_i915_gem_request *req,
11587 struct intel_ring *ring = req->ring;
11588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11592 ret = intel_ring_begin(req, 6);
11596 /* Can't queue multiple flips, so wait for the previous
11597 * one to finish before executing the next.
11599 if (intel_crtc->plane)
11600 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11602 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11603 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11604 intel_ring_emit(ring, MI_NOOP);
11605 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11606 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11607 intel_ring_emit(ring, fb->pitches[0]);
11608 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11609 intel_ring_emit(ring, 0); /* aux display base address, unused */
11614 static int intel_gen3_queue_flip(struct drm_device *dev,
11615 struct drm_crtc *crtc,
11616 struct drm_framebuffer *fb,
11617 struct drm_i915_gem_object *obj,
11618 struct drm_i915_gem_request *req,
11621 struct intel_ring *ring = req->ring;
11622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11626 ret = intel_ring_begin(req, 6);
11630 if (intel_crtc->plane)
11631 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11633 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11634 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11635 intel_ring_emit(ring, MI_NOOP);
11636 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11637 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11638 intel_ring_emit(ring, fb->pitches[0]);
11639 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11640 intel_ring_emit(ring, MI_NOOP);
11645 static int intel_gen4_queue_flip(struct drm_device *dev,
11646 struct drm_crtc *crtc,
11647 struct drm_framebuffer *fb,
11648 struct drm_i915_gem_object *obj,
11649 struct drm_i915_gem_request *req,
11652 struct intel_ring *ring = req->ring;
11653 struct drm_i915_private *dev_priv = to_i915(dev);
11654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11655 uint32_t pf, pipesrc;
11658 ret = intel_ring_begin(req, 4);
11662 /* i965+ uses the linear or tiled offsets from the
11663 * Display Registers (which do not change across a page-flip)
11664 * so we need only reprogram the base address.
11666 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11667 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11668 intel_ring_emit(ring, fb->pitches[0]);
11669 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11670 intel_fb_modifier_to_tiling(fb->modifier[0]));
11672 /* XXX Enabling the panel-fitter across page-flip is so far
11673 * untested on non-native modes, so ignore it for now.
11674 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11677 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11678 intel_ring_emit(ring, pf | pipesrc);
11683 static int intel_gen6_queue_flip(struct drm_device *dev,
11684 struct drm_crtc *crtc,
11685 struct drm_framebuffer *fb,
11686 struct drm_i915_gem_object *obj,
11687 struct drm_i915_gem_request *req,
11690 struct intel_ring *ring = req->ring;
11691 struct drm_i915_private *dev_priv = to_i915(dev);
11692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11693 uint32_t pf, pipesrc;
11696 ret = intel_ring_begin(req, 4);
11700 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11701 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11702 intel_ring_emit(ring, fb->pitches[0] |
11703 intel_fb_modifier_to_tiling(fb->modifier[0]));
11704 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11706 /* Contrary to the suggestions in the documentation,
11707 * "Enable Panel Fitter" does not seem to be required when page
11708 * flipping with a non-native mode, and worse causes a normal
11710 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11713 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11714 intel_ring_emit(ring, pf | pipesrc);
11719 static int intel_gen7_queue_flip(struct drm_device *dev,
11720 struct drm_crtc *crtc,
11721 struct drm_framebuffer *fb,
11722 struct drm_i915_gem_object *obj,
11723 struct drm_i915_gem_request *req,
11726 struct intel_ring *ring = req->ring;
11727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11728 uint32_t plane_bit = 0;
11731 switch (intel_crtc->plane) {
11733 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11736 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11739 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11742 WARN_ONCE(1, "unknown plane in flip command\n");
11747 if (req->engine->id == RCS) {
11750 * On Gen 8, SRM is now taking an extra dword to accommodate
11751 * 48bits addresses, and we need a NOOP for the batch size to
11759 * BSpec MI_DISPLAY_FLIP for IVB:
11760 * "The full packet must be contained within the same cache line."
11762 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11763 * cacheline, if we ever start emitting more commands before
11764 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11765 * then do the cacheline alignment, and finally emit the
11768 ret = intel_ring_cacheline_align(req);
11772 ret = intel_ring_begin(req, len);
11776 /* Unmask the flip-done completion message. Note that the bspec says that
11777 * we should do this for both the BCS and RCS, and that we must not unmask
11778 * more than one flip event at any time (or ensure that one flip message
11779 * can be sent by waiting for flip-done prior to queueing new flips).
11780 * Experimentation says that BCS works despite DERRMR masking all
11781 * flip-done completion events and that unmasking all planes at once
11782 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11783 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11785 if (req->engine->id == RCS) {
11786 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11787 intel_ring_emit_reg(ring, DERRMR);
11788 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11789 DERRMR_PIPEB_PRI_FLIP_DONE |
11790 DERRMR_PIPEC_PRI_FLIP_DONE));
11792 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11793 MI_SRM_LRM_GLOBAL_GTT);
11795 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11796 MI_SRM_LRM_GLOBAL_GTT);
11797 intel_ring_emit_reg(ring, DERRMR);
11798 intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);
11799 if (IS_GEN8(dev)) {
11800 intel_ring_emit(ring, 0);
11801 intel_ring_emit(ring, MI_NOOP);
11805 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11806 intel_ring_emit(ring, fb->pitches[0] |
11807 intel_fb_modifier_to_tiling(fb->modifier[0]));
11808 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11809 intel_ring_emit(ring, (MI_NOOP));
11814 static bool use_mmio_flip(struct intel_engine_cs *engine,
11815 struct drm_i915_gem_object *obj)
11817 struct reservation_object *resv;
11820 * This is not being used for older platforms, because
11821 * non-availability of flip done interrupt forces us to use
11822 * CS flips. Older platforms derive flip done using some clever
11823 * tricks involving the flip_pending status bits and vblank irqs.
11824 * So using MMIO flips there would disrupt this mechanism.
11827 if (engine == NULL)
11830 if (INTEL_GEN(engine->i915) < 5)
11833 if (i915.use_mmio_flip < 0)
11835 else if (i915.use_mmio_flip > 0)
11837 else if (i915.enable_execlists)
11840 resv = i915_gem_object_get_dmabuf_resv(obj);
11841 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11844 return engine != i915_gem_active_get_engine(&obj->last_write,
11845 &obj->base.dev->struct_mutex);
11848 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11849 unsigned int rotation,
11850 struct intel_flip_work *work)
11852 struct drm_device *dev = intel_crtc->base.dev;
11853 struct drm_i915_private *dev_priv = to_i915(dev);
11854 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11855 const enum pipe pipe = intel_crtc->pipe;
11856 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11858 ctl = I915_READ(PLANE_CTL(pipe, 0));
11859 ctl &= ~PLANE_CTL_TILED_MASK;
11860 switch (fb->modifier[0]) {
11861 case DRM_FORMAT_MOD_NONE:
11863 case I915_FORMAT_MOD_X_TILED:
11864 ctl |= PLANE_CTL_TILED_X;
11866 case I915_FORMAT_MOD_Y_TILED:
11867 ctl |= PLANE_CTL_TILED_Y;
11869 case I915_FORMAT_MOD_Yf_TILED:
11870 ctl |= PLANE_CTL_TILED_YF;
11873 MISSING_CASE(fb->modifier[0]);
11877 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11878 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11880 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11881 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11883 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11884 POSTING_READ(PLANE_SURF(pipe, 0));
11887 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11888 struct intel_flip_work *work)
11890 struct drm_device *dev = intel_crtc->base.dev;
11891 struct drm_i915_private *dev_priv = to_i915(dev);
11892 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11893 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11896 dspcntr = I915_READ(reg);
11898 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
11899 dspcntr |= DISPPLANE_TILED;
11901 dspcntr &= ~DISPPLANE_TILED;
11903 I915_WRITE(reg, dspcntr);
11905 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11906 POSTING_READ(DSPSURF(intel_crtc->plane));
11909 static void intel_mmio_flip_work_func(struct work_struct *w)
11911 struct intel_flip_work *work =
11912 container_of(w, struct intel_flip_work, mmio_work);
11913 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11914 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11915 struct intel_framebuffer *intel_fb =
11916 to_intel_framebuffer(crtc->base.primary->fb);
11917 struct drm_i915_gem_object *obj = intel_fb->obj;
11918 struct reservation_object *resv;
11920 if (work->flip_queued_req)
11921 WARN_ON(i915_wait_request(work->flip_queued_req,
11925 /* For framebuffer backed by dmabuf, wait for fence */
11926 resv = i915_gem_object_get_dmabuf_resv(obj);
11928 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11929 MAX_SCHEDULE_TIMEOUT) < 0);
11931 intel_pipe_update_start(crtc);
11933 if (INTEL_GEN(dev_priv) >= 9)
11934 skl_do_mmio_flip(crtc, work->rotation, work);
11936 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11937 ilk_do_mmio_flip(crtc, work);
11939 intel_pipe_update_end(crtc, work);
11942 static int intel_default_queue_flip(struct drm_device *dev,
11943 struct drm_crtc *crtc,
11944 struct drm_framebuffer *fb,
11945 struct drm_i915_gem_object *obj,
11946 struct drm_i915_gem_request *req,
11952 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11953 struct intel_crtc *intel_crtc,
11954 struct intel_flip_work *work)
11958 if (!atomic_read(&work->pending))
11963 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11964 if (work->flip_ready_vblank == 0) {
11965 if (work->flip_queued_req &&
11966 !i915_gem_request_completed(work->flip_queued_req))
11969 work->flip_ready_vblank = vblank;
11972 if (vblank - work->flip_ready_vblank < 3)
11975 /* Potential stall - if we see that the flip has happened,
11976 * assume a missed interrupt. */
11977 if (INTEL_GEN(dev_priv) >= 4)
11978 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11980 addr = I915_READ(DSPADDR(intel_crtc->plane));
11982 /* There is a potential issue here with a false positive after a flip
11983 * to the same address. We could address this by checking for a
11984 * non-incrementing frame counter.
11986 return addr == work->gtt_offset;
11989 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11991 struct drm_device *dev = &dev_priv->drm;
11992 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11994 struct intel_flip_work *work;
11996 WARN_ON(!in_interrupt());
12001 spin_lock(&dev->event_lock);
12002 work = intel_crtc->flip_work;
12004 if (work != NULL && !is_mmio_work(work) &&
12005 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12007 "Kicking stuck page flip: queued at %d, now %d\n",
12008 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12009 page_flip_completed(intel_crtc);
12013 if (work != NULL && !is_mmio_work(work) &&
12014 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12015 intel_queue_rps_boost_for_request(work->flip_queued_req);
12016 spin_unlock(&dev->event_lock);
12019 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12020 struct drm_framebuffer *fb,
12021 struct drm_pending_vblank_event *event,
12022 uint32_t page_flip_flags)
12024 struct drm_device *dev = crtc->dev;
12025 struct drm_i915_private *dev_priv = to_i915(dev);
12026 struct drm_framebuffer *old_fb = crtc->primary->fb;
12027 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12029 struct drm_plane *primary = crtc->primary;
12030 enum pipe pipe = intel_crtc->pipe;
12031 struct intel_flip_work *work;
12032 struct intel_engine_cs *engine;
12034 struct drm_i915_gem_request *request;
12038 * drm_mode_page_flip_ioctl() should already catch this, but double
12039 * check to be safe. In the future we may enable pageflipping from
12040 * a disabled primary plane.
12042 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12045 /* Can't change pixel format via MI display flips. */
12046 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12050 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12051 * Note that pitch changes could also affect these register.
12053 if (INTEL_INFO(dev)->gen > 3 &&
12054 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12055 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12058 if (i915_terminally_wedged(&dev_priv->gpu_error))
12061 work = kzalloc(sizeof(*work), GFP_KERNEL);
12065 work->event = event;
12067 work->old_fb = old_fb;
12068 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12070 ret = drm_crtc_vblank_get(crtc);
12074 /* We borrow the event spin lock for protecting flip_work */
12075 spin_lock_irq(&dev->event_lock);
12076 if (intel_crtc->flip_work) {
12077 /* Before declaring the flip queue wedged, check if
12078 * the hardware completed the operation behind our backs.
12080 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12081 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12082 page_flip_completed(intel_crtc);
12084 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12085 spin_unlock_irq(&dev->event_lock);
12087 drm_crtc_vblank_put(crtc);
12092 intel_crtc->flip_work = work;
12093 spin_unlock_irq(&dev->event_lock);
12095 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12096 flush_workqueue(dev_priv->wq);
12098 /* Reference the objects for the scheduled work. */
12099 drm_framebuffer_reference(work->old_fb);
12101 crtc->primary->fb = fb;
12102 update_state_fb(crtc->primary);
12104 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12105 to_intel_plane_state(primary->state));
12107 work->pending_flip_obj = i915_gem_object_get(obj);
12109 ret = i915_mutex_lock_interruptible(dev);
12113 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
12114 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
12119 atomic_inc(&intel_crtc->unpin_work_count);
12121 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12122 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12124 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12125 engine = &dev_priv->engine[BCS];
12126 if (fb->modifier[0] != old_fb->modifier[0])
12127 /* vlv: DISPLAY_FLIP fails to change tiling */
12129 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12130 engine = &dev_priv->engine[BCS];
12131 } else if (INTEL_INFO(dev)->gen >= 7) {
12132 engine = i915_gem_active_get_engine(&obj->last_write,
12133 &obj->base.dev->struct_mutex);
12134 if (engine == NULL || engine->id != RCS)
12135 engine = &dev_priv->engine[BCS];
12137 engine = &dev_priv->engine[RCS];
12140 mmio_flip = use_mmio_flip(engine, obj);
12142 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12144 goto cleanup_pending;
12146 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12147 work->gtt_offset += intel_crtc->dspaddr_offset;
12148 work->rotation = crtc->primary->state->rotation;
12151 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12153 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12154 &obj->base.dev->struct_mutex);
12155 schedule_work(&work->mmio_work);
12157 request = i915_gem_request_alloc(engine, engine->last_context);
12158 if (IS_ERR(request)) {
12159 ret = PTR_ERR(request);
12160 goto cleanup_unpin;
12163 ret = i915_gem_object_sync(obj, request);
12165 goto cleanup_request;
12167 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12170 goto cleanup_request;
12172 intel_mark_page_flip_active(intel_crtc, work);
12174 work->flip_queued_req = i915_gem_request_get(request);
12175 i915_add_request_no_flush(request);
12178 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12179 to_intel_plane(primary)->frontbuffer_bit);
12180 mutex_unlock(&dev->struct_mutex);
12182 intel_frontbuffer_flip_prepare(to_i915(dev),
12183 to_intel_plane(primary)->frontbuffer_bit);
12185 trace_i915_flip_request(intel_crtc->plane, obj);
12190 i915_add_request_no_flush(request);
12192 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12194 atomic_dec(&intel_crtc->unpin_work_count);
12195 mutex_unlock(&dev->struct_mutex);
12197 crtc->primary->fb = old_fb;
12198 update_state_fb(crtc->primary);
12200 i915_gem_object_put_unlocked(obj);
12201 drm_framebuffer_unreference(work->old_fb);
12203 spin_lock_irq(&dev->event_lock);
12204 intel_crtc->flip_work = NULL;
12205 spin_unlock_irq(&dev->event_lock);
12207 drm_crtc_vblank_put(crtc);
12212 struct drm_atomic_state *state;
12213 struct drm_plane_state *plane_state;
12216 state = drm_atomic_state_alloc(dev);
12219 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12222 plane_state = drm_atomic_get_plane_state(state, primary);
12223 ret = PTR_ERR_OR_ZERO(plane_state);
12225 drm_atomic_set_fb_for_plane(plane_state, fb);
12227 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12229 ret = drm_atomic_commit(state);
12232 if (ret == -EDEADLK) {
12233 drm_modeset_backoff(state->acquire_ctx);
12234 drm_atomic_state_clear(state);
12239 drm_atomic_state_free(state);
12241 if (ret == 0 && event) {
12242 spin_lock_irq(&dev->event_lock);
12243 drm_crtc_send_vblank_event(crtc, event);
12244 spin_unlock_irq(&dev->event_lock);
12252 * intel_wm_need_update - Check whether watermarks need updating
12253 * @plane: drm plane
12254 * @state: new plane state
12256 * Check current plane state versus the new one to determine whether
12257 * watermarks need to be recalculated.
12259 * Returns true or false.
12261 static bool intel_wm_need_update(struct drm_plane *plane,
12262 struct drm_plane_state *state)
12264 struct intel_plane_state *new = to_intel_plane_state(state);
12265 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12267 /* Update watermarks on tiling or size changes. */
12268 if (new->visible != cur->visible)
12271 if (!cur->base.fb || !new->base.fb)
12274 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12275 cur->base.rotation != new->base.rotation ||
12276 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
12277 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
12278 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
12279 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
12285 static bool needs_scaling(struct intel_plane_state *state)
12287 int src_w = drm_rect_width(&state->src) >> 16;
12288 int src_h = drm_rect_height(&state->src) >> 16;
12289 int dst_w = drm_rect_width(&state->dst);
12290 int dst_h = drm_rect_height(&state->dst);
12292 return (src_w != dst_w || src_h != dst_h);
12295 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12296 struct drm_plane_state *plane_state)
12298 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12299 struct drm_crtc *crtc = crtc_state->crtc;
12300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12301 struct drm_plane *plane = plane_state->plane;
12302 struct drm_device *dev = crtc->dev;
12303 struct drm_i915_private *dev_priv = to_i915(dev);
12304 struct intel_plane_state *old_plane_state =
12305 to_intel_plane_state(plane->state);
12306 bool mode_changed = needs_modeset(crtc_state);
12307 bool was_crtc_enabled = crtc->state->active;
12308 bool is_crtc_enabled = crtc_state->active;
12309 bool turn_off, turn_on, visible, was_visible;
12310 struct drm_framebuffer *fb = plane_state->fb;
12313 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12314 ret = skl_update_scaler_plane(
12315 to_intel_crtc_state(crtc_state),
12316 to_intel_plane_state(plane_state));
12321 was_visible = old_plane_state->visible;
12322 visible = to_intel_plane_state(plane_state)->visible;
12324 if (!was_crtc_enabled && WARN_ON(was_visible))
12325 was_visible = false;
12328 * Visibility is calculated as if the crtc was on, but
12329 * after scaler setup everything depends on it being off
12330 * when the crtc isn't active.
12332 * FIXME this is wrong for watermarks. Watermarks should also
12333 * be computed as if the pipe would be active. Perhaps move
12334 * per-plane wm computation to the .check_plane() hook, and
12335 * only combine the results from all planes in the current place?
12337 if (!is_crtc_enabled)
12338 to_intel_plane_state(plane_state)->visible = visible = false;
12340 if (!was_visible && !visible)
12343 if (fb != old_plane_state->base.fb)
12344 pipe_config->fb_changed = true;
12346 turn_off = was_visible && (!visible || mode_changed);
12347 turn_on = visible && (!was_visible || mode_changed);
12349 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12350 intel_crtc->base.base.id,
12351 intel_crtc->base.name,
12352 plane->base.id, plane->name,
12353 fb ? fb->base.id : -1);
12355 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12356 plane->base.id, plane->name,
12357 was_visible, visible,
12358 turn_off, turn_on, mode_changed);
12361 pipe_config->update_wm_pre = true;
12363 /* must disable cxsr around plane enable/disable */
12364 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12365 pipe_config->disable_cxsr = true;
12366 } else if (turn_off) {
12367 pipe_config->update_wm_post = true;
12369 /* must disable cxsr around plane enable/disable */
12370 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12371 pipe_config->disable_cxsr = true;
12372 } else if (intel_wm_need_update(plane, plane_state)) {
12373 /* FIXME bollocks */
12374 pipe_config->update_wm_pre = true;
12375 pipe_config->update_wm_post = true;
12378 /* Pre-gen9 platforms need two-step watermark updates */
12379 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12380 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12381 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12383 if (visible || was_visible)
12384 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12387 * WaCxSRDisabledForSpriteScaling:ivb
12389 * cstate->update_wm was already set above, so this flag will
12390 * take effect when we commit and program watermarks.
12392 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12393 needs_scaling(to_intel_plane_state(plane_state)) &&
12394 !needs_scaling(old_plane_state))
12395 pipe_config->disable_lp_wm = true;
12400 static bool encoders_cloneable(const struct intel_encoder *a,
12401 const struct intel_encoder *b)
12403 /* masks could be asymmetric, so check both ways */
12404 return a == b || (a->cloneable & (1 << b->type) &&
12405 b->cloneable & (1 << a->type));
12408 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12409 struct intel_crtc *crtc,
12410 struct intel_encoder *encoder)
12412 struct intel_encoder *source_encoder;
12413 struct drm_connector *connector;
12414 struct drm_connector_state *connector_state;
12417 for_each_connector_in_state(state, connector, connector_state, i) {
12418 if (connector_state->crtc != &crtc->base)
12422 to_intel_encoder(connector_state->best_encoder);
12423 if (!encoders_cloneable(encoder, source_encoder))
12430 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12431 struct drm_crtc_state *crtc_state)
12433 struct drm_device *dev = crtc->dev;
12434 struct drm_i915_private *dev_priv = to_i915(dev);
12435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12436 struct intel_crtc_state *pipe_config =
12437 to_intel_crtc_state(crtc_state);
12438 struct drm_atomic_state *state = crtc_state->state;
12440 bool mode_changed = needs_modeset(crtc_state);
12442 if (mode_changed && !crtc_state->active)
12443 pipe_config->update_wm_post = true;
12445 if (mode_changed && crtc_state->enable &&
12446 dev_priv->display.crtc_compute_clock &&
12447 !WARN_ON(pipe_config->shared_dpll)) {
12448 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12454 if (crtc_state->color_mgmt_changed) {
12455 ret = intel_color_check(crtc, crtc_state);
12460 * Changing color management on Intel hardware is
12461 * handled as part of planes update.
12463 crtc_state->planes_changed = true;
12467 if (dev_priv->display.compute_pipe_wm) {
12468 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12470 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12475 if (dev_priv->display.compute_intermediate_wm &&
12476 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12477 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12481 * Calculate 'intermediate' watermarks that satisfy both the
12482 * old state and the new state. We can program these
12485 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12489 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12492 } else if (dev_priv->display.compute_intermediate_wm) {
12493 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12494 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12497 if (INTEL_INFO(dev)->gen >= 9) {
12499 ret = skl_update_scaler_crtc(pipe_config);
12502 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12509 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12510 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12511 .atomic_begin = intel_begin_crtc_commit,
12512 .atomic_flush = intel_finish_crtc_commit,
12513 .atomic_check = intel_crtc_atomic_check,
12516 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12518 struct intel_connector *connector;
12520 for_each_intel_connector(dev, connector) {
12521 if (connector->base.state->crtc)
12522 drm_connector_unreference(&connector->base);
12524 if (connector->base.encoder) {
12525 connector->base.state->best_encoder =
12526 connector->base.encoder;
12527 connector->base.state->crtc =
12528 connector->base.encoder->crtc;
12530 drm_connector_reference(&connector->base);
12532 connector->base.state->best_encoder = NULL;
12533 connector->base.state->crtc = NULL;
12539 connected_sink_compute_bpp(struct intel_connector *connector,
12540 struct intel_crtc_state *pipe_config)
12542 int bpp = pipe_config->pipe_bpp;
12544 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12545 connector->base.base.id,
12546 connector->base.name);
12548 /* Don't use an invalid EDID bpc value */
12549 if (connector->base.display_info.bpc &&
12550 connector->base.display_info.bpc * 3 < bpp) {
12551 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12552 bpp, connector->base.display_info.bpc*3);
12553 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12556 /* Clamp bpp to default limit on screens without EDID 1.4 */
12557 if (connector->base.display_info.bpc == 0) {
12558 int type = connector->base.connector_type;
12559 int clamp_bpp = 24;
12561 /* Fall back to 18 bpp when DP sink capability is unknown. */
12562 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12563 type == DRM_MODE_CONNECTOR_eDP)
12566 if (bpp > clamp_bpp) {
12567 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12569 pipe_config->pipe_bpp = clamp_bpp;
12575 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12576 struct intel_crtc_state *pipe_config)
12578 struct drm_device *dev = crtc->base.dev;
12579 struct drm_atomic_state *state;
12580 struct drm_connector *connector;
12581 struct drm_connector_state *connector_state;
12584 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12586 else if (INTEL_INFO(dev)->gen >= 5)
12592 pipe_config->pipe_bpp = bpp;
12594 state = pipe_config->base.state;
12596 /* Clamp display bpp to EDID value */
12597 for_each_connector_in_state(state, connector, connector_state, i) {
12598 if (connector_state->crtc != &crtc->base)
12601 connected_sink_compute_bpp(to_intel_connector(connector),
12608 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12610 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12611 "type: 0x%x flags: 0x%x\n",
12613 mode->crtc_hdisplay, mode->crtc_hsync_start,
12614 mode->crtc_hsync_end, mode->crtc_htotal,
12615 mode->crtc_vdisplay, mode->crtc_vsync_start,
12616 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12619 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12620 struct intel_crtc_state *pipe_config,
12621 const char *context)
12623 struct drm_device *dev = crtc->base.dev;
12624 struct drm_plane *plane;
12625 struct intel_plane *intel_plane;
12626 struct intel_plane_state *state;
12627 struct drm_framebuffer *fb;
12629 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12630 crtc->base.base.id, crtc->base.name,
12631 context, pipe_config, pipe_name(crtc->pipe));
12633 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12634 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12635 pipe_config->pipe_bpp, pipe_config->dither);
12636 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12637 pipe_config->has_pch_encoder,
12638 pipe_config->fdi_lanes,
12639 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12640 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12641 pipe_config->fdi_m_n.tu);
12642 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12643 intel_crtc_has_dp_encoder(pipe_config),
12644 pipe_config->lane_count,
12645 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12646 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12647 pipe_config->dp_m_n.tu);
12649 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12650 intel_crtc_has_dp_encoder(pipe_config),
12651 pipe_config->lane_count,
12652 pipe_config->dp_m2_n2.gmch_m,
12653 pipe_config->dp_m2_n2.gmch_n,
12654 pipe_config->dp_m2_n2.link_m,
12655 pipe_config->dp_m2_n2.link_n,
12656 pipe_config->dp_m2_n2.tu);
12658 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12659 pipe_config->has_audio,
12660 pipe_config->has_infoframe);
12662 DRM_DEBUG_KMS("requested mode:\n");
12663 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12664 DRM_DEBUG_KMS("adjusted mode:\n");
12665 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12666 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12667 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12668 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12669 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12670 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12672 pipe_config->scaler_state.scaler_users,
12673 pipe_config->scaler_state.scaler_id);
12674 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12675 pipe_config->gmch_pfit.control,
12676 pipe_config->gmch_pfit.pgm_ratios,
12677 pipe_config->gmch_pfit.lvds_border_bits);
12678 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12679 pipe_config->pch_pfit.pos,
12680 pipe_config->pch_pfit.size,
12681 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12682 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12683 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12685 if (IS_BROXTON(dev)) {
12686 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12687 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12688 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12689 pipe_config->ddi_pll_sel,
12690 pipe_config->dpll_hw_state.ebb0,
12691 pipe_config->dpll_hw_state.ebb4,
12692 pipe_config->dpll_hw_state.pll0,
12693 pipe_config->dpll_hw_state.pll1,
12694 pipe_config->dpll_hw_state.pll2,
12695 pipe_config->dpll_hw_state.pll3,
12696 pipe_config->dpll_hw_state.pll6,
12697 pipe_config->dpll_hw_state.pll8,
12698 pipe_config->dpll_hw_state.pll9,
12699 pipe_config->dpll_hw_state.pll10,
12700 pipe_config->dpll_hw_state.pcsdw12);
12701 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12702 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12703 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12704 pipe_config->ddi_pll_sel,
12705 pipe_config->dpll_hw_state.ctrl1,
12706 pipe_config->dpll_hw_state.cfgcr1,
12707 pipe_config->dpll_hw_state.cfgcr2);
12708 } else if (HAS_DDI(dev)) {
12709 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12710 pipe_config->ddi_pll_sel,
12711 pipe_config->dpll_hw_state.wrpll,
12712 pipe_config->dpll_hw_state.spll);
12714 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12715 "fp0: 0x%x, fp1: 0x%x\n",
12716 pipe_config->dpll_hw_state.dpll,
12717 pipe_config->dpll_hw_state.dpll_md,
12718 pipe_config->dpll_hw_state.fp0,
12719 pipe_config->dpll_hw_state.fp1);
12722 DRM_DEBUG_KMS("planes on this crtc\n");
12723 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12724 intel_plane = to_intel_plane(plane);
12725 if (intel_plane->pipe != crtc->pipe)
12728 state = to_intel_plane_state(plane->state);
12729 fb = state->base.fb;
12731 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12732 plane->base.id, plane->name, state->scaler_id);
12736 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12737 plane->base.id, plane->name);
12738 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12739 fb->base.id, fb->width, fb->height,
12740 drm_get_format_name(fb->pixel_format));
12741 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12743 state->src.x1 >> 16, state->src.y1 >> 16,
12744 drm_rect_width(&state->src) >> 16,
12745 drm_rect_height(&state->src) >> 16,
12746 state->dst.x1, state->dst.y1,
12747 drm_rect_width(&state->dst),
12748 drm_rect_height(&state->dst));
12752 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12754 struct drm_device *dev = state->dev;
12755 struct drm_connector *connector;
12756 unsigned int used_ports = 0;
12757 unsigned int used_mst_ports = 0;
12760 * Walk the connector list instead of the encoder
12761 * list to detect the problem on ddi platforms
12762 * where there's just one encoder per digital port.
12764 drm_for_each_connector(connector, dev) {
12765 struct drm_connector_state *connector_state;
12766 struct intel_encoder *encoder;
12768 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12769 if (!connector_state)
12770 connector_state = connector->state;
12772 if (!connector_state->best_encoder)
12775 encoder = to_intel_encoder(connector_state->best_encoder);
12777 WARN_ON(!connector_state->crtc);
12779 switch (encoder->type) {
12780 unsigned int port_mask;
12781 case INTEL_OUTPUT_UNKNOWN:
12782 if (WARN_ON(!HAS_DDI(dev)))
12784 case INTEL_OUTPUT_DP:
12785 case INTEL_OUTPUT_HDMI:
12786 case INTEL_OUTPUT_EDP:
12787 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12789 /* the same port mustn't appear more than once */
12790 if (used_ports & port_mask)
12793 used_ports |= port_mask;
12795 case INTEL_OUTPUT_DP_MST:
12797 1 << enc_to_mst(&encoder->base)->primary->port;
12804 /* can't mix MST and SST/HDMI on the same port */
12805 if (used_ports & used_mst_ports)
12812 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12814 struct drm_crtc_state tmp_state;
12815 struct intel_crtc_scaler_state scaler_state;
12816 struct intel_dpll_hw_state dpll_hw_state;
12817 struct intel_shared_dpll *shared_dpll;
12818 uint32_t ddi_pll_sel;
12821 /* FIXME: before the switch to atomic started, a new pipe_config was
12822 * kzalloc'd. Code that depends on any field being zero should be
12823 * fixed, so that the crtc_state can be safely duplicated. For now,
12824 * only fields that are know to not cause problems are preserved. */
12826 tmp_state = crtc_state->base;
12827 scaler_state = crtc_state->scaler_state;
12828 shared_dpll = crtc_state->shared_dpll;
12829 dpll_hw_state = crtc_state->dpll_hw_state;
12830 ddi_pll_sel = crtc_state->ddi_pll_sel;
12831 force_thru = crtc_state->pch_pfit.force_thru;
12833 memset(crtc_state, 0, sizeof *crtc_state);
12835 crtc_state->base = tmp_state;
12836 crtc_state->scaler_state = scaler_state;
12837 crtc_state->shared_dpll = shared_dpll;
12838 crtc_state->dpll_hw_state = dpll_hw_state;
12839 crtc_state->ddi_pll_sel = ddi_pll_sel;
12840 crtc_state->pch_pfit.force_thru = force_thru;
12844 intel_modeset_pipe_config(struct drm_crtc *crtc,
12845 struct intel_crtc_state *pipe_config)
12847 struct drm_atomic_state *state = pipe_config->base.state;
12848 struct intel_encoder *encoder;
12849 struct drm_connector *connector;
12850 struct drm_connector_state *connector_state;
12851 int base_bpp, ret = -EINVAL;
12855 clear_intel_crtc_state(pipe_config);
12857 pipe_config->cpu_transcoder =
12858 (enum transcoder) to_intel_crtc(crtc)->pipe;
12861 * Sanitize sync polarity flags based on requested ones. If neither
12862 * positive or negative polarity is requested, treat this as meaning
12863 * negative polarity.
12865 if (!(pipe_config->base.adjusted_mode.flags &
12866 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12867 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12869 if (!(pipe_config->base.adjusted_mode.flags &
12870 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12871 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12873 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12879 * Determine the real pipe dimensions. Note that stereo modes can
12880 * increase the actual pipe size due to the frame doubling and
12881 * insertion of additional space for blanks between the frame. This
12882 * is stored in the crtc timings. We use the requested mode to do this
12883 * computation to clearly distinguish it from the adjusted mode, which
12884 * can be changed by the connectors in the below retry loop.
12886 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12887 &pipe_config->pipe_src_w,
12888 &pipe_config->pipe_src_h);
12890 for_each_connector_in_state(state, connector, connector_state, i) {
12891 if (connector_state->crtc != crtc)
12894 encoder = to_intel_encoder(connector_state->best_encoder);
12896 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12897 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12902 * Determine output_types before calling the .compute_config()
12903 * hooks so that the hooks can use this information safely.
12905 pipe_config->output_types |= 1 << encoder->type;
12909 /* Ensure the port clock defaults are reset when retrying. */
12910 pipe_config->port_clock = 0;
12911 pipe_config->pixel_multiplier = 1;
12913 /* Fill in default crtc timings, allow encoders to overwrite them. */
12914 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12915 CRTC_STEREO_DOUBLE);
12917 /* Pass our mode to the connectors and the CRTC to give them a chance to
12918 * adjust it according to limitations or connector properties, and also
12919 * a chance to reject the mode entirely.
12921 for_each_connector_in_state(state, connector, connector_state, i) {
12922 if (connector_state->crtc != crtc)
12925 encoder = to_intel_encoder(connector_state->best_encoder);
12927 if (!(encoder->compute_config(encoder, pipe_config))) {
12928 DRM_DEBUG_KMS("Encoder config failure\n");
12933 /* Set default port clock if not overwritten by the encoder. Needs to be
12934 * done afterwards in case the encoder adjusts the mode. */
12935 if (!pipe_config->port_clock)
12936 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12937 * pipe_config->pixel_multiplier;
12939 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12941 DRM_DEBUG_KMS("CRTC fixup failed\n");
12945 if (ret == RETRY) {
12946 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12951 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12953 goto encoder_retry;
12956 /* Dithering seems to not pass-through bits correctly when it should, so
12957 * only enable it on 6bpc panels. */
12958 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12959 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12960 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12967 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12969 struct drm_crtc *crtc;
12970 struct drm_crtc_state *crtc_state;
12973 /* Double check state. */
12974 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12975 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12977 /* Update hwmode for vblank functions */
12978 if (crtc->state->active)
12979 crtc->hwmode = crtc->state->adjusted_mode;
12981 crtc->hwmode.crtc_clock = 0;
12984 * Update legacy state to satisfy fbc code. This can
12985 * be removed when fbc uses the atomic state.
12987 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12988 struct drm_plane_state *plane_state = crtc->primary->state;
12990 crtc->primary->fb = plane_state->fb;
12991 crtc->x = plane_state->src_x >> 16;
12992 crtc->y = plane_state->src_y >> 16;
12997 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13001 if (clock1 == clock2)
13004 if (!clock1 || !clock2)
13007 diff = abs(clock1 - clock2);
13009 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13015 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
13016 list_for_each_entry((intel_crtc), \
13017 &(dev)->mode_config.crtc_list, \
13019 for_each_if (mask & (1 <<(intel_crtc)->pipe))
13022 intel_compare_m_n(unsigned int m, unsigned int n,
13023 unsigned int m2, unsigned int n2,
13026 if (m == m2 && n == n2)
13029 if (exact || !m || !n || !m2 || !n2)
13032 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13039 } else if (n < n2) {
13049 return intel_fuzzy_clock_check(m, m2);
13053 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13054 struct intel_link_m_n *m2_n2,
13057 if (m_n->tu == m2_n2->tu &&
13058 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13059 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13060 intel_compare_m_n(m_n->link_m, m_n->link_n,
13061 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13072 intel_pipe_config_compare(struct drm_device *dev,
13073 struct intel_crtc_state *current_config,
13074 struct intel_crtc_state *pipe_config,
13079 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13082 DRM_ERROR(fmt, ##__VA_ARGS__); \
13084 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13087 #define PIPE_CONF_CHECK_X(name) \
13088 if (current_config->name != pipe_config->name) { \
13089 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13090 "(expected 0x%08x, found 0x%08x)\n", \
13091 current_config->name, \
13092 pipe_config->name); \
13096 #define PIPE_CONF_CHECK_I(name) \
13097 if (current_config->name != pipe_config->name) { \
13098 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13099 "(expected %i, found %i)\n", \
13100 current_config->name, \
13101 pipe_config->name); \
13105 #define PIPE_CONF_CHECK_P(name) \
13106 if (current_config->name != pipe_config->name) { \
13107 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13108 "(expected %p, found %p)\n", \
13109 current_config->name, \
13110 pipe_config->name); \
13114 #define PIPE_CONF_CHECK_M_N(name) \
13115 if (!intel_compare_link_m_n(¤t_config->name, \
13116 &pipe_config->name,\
13118 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13119 "(expected tu %i gmch %i/%i link %i/%i, " \
13120 "found tu %i, gmch %i/%i link %i/%i)\n", \
13121 current_config->name.tu, \
13122 current_config->name.gmch_m, \
13123 current_config->name.gmch_n, \
13124 current_config->name.link_m, \
13125 current_config->name.link_n, \
13126 pipe_config->name.tu, \
13127 pipe_config->name.gmch_m, \
13128 pipe_config->name.gmch_n, \
13129 pipe_config->name.link_m, \
13130 pipe_config->name.link_n); \
13134 /* This is required for BDW+ where there is only one set of registers for
13135 * switching between high and low RR.
13136 * This macro can be used whenever a comparison has to be made between one
13137 * hw state and multiple sw state variables.
13139 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13140 if (!intel_compare_link_m_n(¤t_config->name, \
13141 &pipe_config->name, adjust) && \
13142 !intel_compare_link_m_n(¤t_config->alt_name, \
13143 &pipe_config->name, adjust)) { \
13144 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13145 "(expected tu %i gmch %i/%i link %i/%i, " \
13146 "or tu %i gmch %i/%i link %i/%i, " \
13147 "found tu %i, gmch %i/%i link %i/%i)\n", \
13148 current_config->name.tu, \
13149 current_config->name.gmch_m, \
13150 current_config->name.gmch_n, \
13151 current_config->name.link_m, \
13152 current_config->name.link_n, \
13153 current_config->alt_name.tu, \
13154 current_config->alt_name.gmch_m, \
13155 current_config->alt_name.gmch_n, \
13156 current_config->alt_name.link_m, \
13157 current_config->alt_name.link_n, \
13158 pipe_config->name.tu, \
13159 pipe_config->name.gmch_m, \
13160 pipe_config->name.gmch_n, \
13161 pipe_config->name.link_m, \
13162 pipe_config->name.link_n); \
13166 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13167 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13168 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13169 "(expected %i, found %i)\n", \
13170 current_config->name & (mask), \
13171 pipe_config->name & (mask)); \
13175 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13176 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13177 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13178 "(expected %i, found %i)\n", \
13179 current_config->name, \
13180 pipe_config->name); \
13184 #define PIPE_CONF_QUIRK(quirk) \
13185 ((current_config->quirks | pipe_config->quirks) & (quirk))
13187 PIPE_CONF_CHECK_I(cpu_transcoder);
13189 PIPE_CONF_CHECK_I(has_pch_encoder);
13190 PIPE_CONF_CHECK_I(fdi_lanes);
13191 PIPE_CONF_CHECK_M_N(fdi_m_n);
13193 PIPE_CONF_CHECK_I(lane_count);
13194 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13196 if (INTEL_INFO(dev)->gen < 8) {
13197 PIPE_CONF_CHECK_M_N(dp_m_n);
13199 if (current_config->has_drrs)
13200 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13202 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13204 PIPE_CONF_CHECK_X(output_types);
13206 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13207 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13208 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13209 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13210 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13211 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13213 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13214 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13215 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13216 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13217 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13218 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13220 PIPE_CONF_CHECK_I(pixel_multiplier);
13221 PIPE_CONF_CHECK_I(has_hdmi_sink);
13222 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13223 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13224 PIPE_CONF_CHECK_I(limited_color_range);
13225 PIPE_CONF_CHECK_I(has_infoframe);
13227 PIPE_CONF_CHECK_I(has_audio);
13229 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13230 DRM_MODE_FLAG_INTERLACE);
13232 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13233 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13234 DRM_MODE_FLAG_PHSYNC);
13235 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13236 DRM_MODE_FLAG_NHSYNC);
13237 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13238 DRM_MODE_FLAG_PVSYNC);
13239 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13240 DRM_MODE_FLAG_NVSYNC);
13243 PIPE_CONF_CHECK_X(gmch_pfit.control);
13244 /* pfit ratios are autocomputed by the hw on gen4+ */
13245 if (INTEL_INFO(dev)->gen < 4)
13246 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13247 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13250 PIPE_CONF_CHECK_I(pipe_src_w);
13251 PIPE_CONF_CHECK_I(pipe_src_h);
13253 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13254 if (current_config->pch_pfit.enabled) {
13255 PIPE_CONF_CHECK_X(pch_pfit.pos);
13256 PIPE_CONF_CHECK_X(pch_pfit.size);
13259 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13262 /* BDW+ don't expose a synchronous way to read the state */
13263 if (IS_HASWELL(dev))
13264 PIPE_CONF_CHECK_I(ips_enabled);
13266 PIPE_CONF_CHECK_I(double_wide);
13268 PIPE_CONF_CHECK_X(ddi_pll_sel);
13270 PIPE_CONF_CHECK_P(shared_dpll);
13271 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13272 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13273 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13274 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13275 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13276 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13277 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13278 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13279 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13281 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13282 PIPE_CONF_CHECK_X(dsi_pll.div);
13284 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13285 PIPE_CONF_CHECK_I(pipe_bpp);
13287 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13288 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13290 #undef PIPE_CONF_CHECK_X
13291 #undef PIPE_CONF_CHECK_I
13292 #undef PIPE_CONF_CHECK_P
13293 #undef PIPE_CONF_CHECK_FLAGS
13294 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13295 #undef PIPE_CONF_QUIRK
13296 #undef INTEL_ERR_OR_DBG_KMS
13301 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13302 const struct intel_crtc_state *pipe_config)
13304 if (pipe_config->has_pch_encoder) {
13305 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13306 &pipe_config->fdi_m_n);
13307 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13310 * FDI already provided one idea for the dotclock.
13311 * Yell if the encoder disagrees.
13313 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13314 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13315 fdi_dotclock, dotclock);
13319 static void verify_wm_state(struct drm_crtc *crtc,
13320 struct drm_crtc_state *new_state)
13322 struct drm_device *dev = crtc->dev;
13323 struct drm_i915_private *dev_priv = to_i915(dev);
13324 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13325 struct skl_ddb_entry *hw_entry, *sw_entry;
13326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13327 const enum pipe pipe = intel_crtc->pipe;
13330 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13333 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13334 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13337 for_each_plane(dev_priv, pipe, plane) {
13338 hw_entry = &hw_ddb.plane[pipe][plane];
13339 sw_entry = &sw_ddb->plane[pipe][plane];
13341 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13344 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13345 "(expected (%u,%u), found (%u,%u))\n",
13346 pipe_name(pipe), plane + 1,
13347 sw_entry->start, sw_entry->end,
13348 hw_entry->start, hw_entry->end);
13352 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13353 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13355 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13356 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13357 "(expected (%u,%u), found (%u,%u))\n",
13359 sw_entry->start, sw_entry->end,
13360 hw_entry->start, hw_entry->end);
13365 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13367 struct drm_connector *connector;
13369 drm_for_each_connector(connector, dev) {
13370 struct drm_encoder *encoder = connector->encoder;
13371 struct drm_connector_state *state = connector->state;
13373 if (state->crtc != crtc)
13376 intel_connector_verify_state(to_intel_connector(connector));
13378 I915_STATE_WARN(state->best_encoder != encoder,
13379 "connector's atomic encoder doesn't match legacy encoder\n");
13384 verify_encoder_state(struct drm_device *dev)
13386 struct intel_encoder *encoder;
13387 struct intel_connector *connector;
13389 for_each_intel_encoder(dev, encoder) {
13390 bool enabled = false;
13393 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13394 encoder->base.base.id,
13395 encoder->base.name);
13397 for_each_intel_connector(dev, connector) {
13398 if (connector->base.state->best_encoder != &encoder->base)
13402 I915_STATE_WARN(connector->base.state->crtc !=
13403 encoder->base.crtc,
13404 "connector's crtc doesn't match encoder crtc\n");
13407 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13408 "encoder's enabled state mismatch "
13409 "(expected %i, found %i)\n",
13410 !!encoder->base.crtc, enabled);
13412 if (!encoder->base.crtc) {
13415 active = encoder->get_hw_state(encoder, &pipe);
13416 I915_STATE_WARN(active,
13417 "encoder detached but still enabled on pipe %c.\n",
13424 verify_crtc_state(struct drm_crtc *crtc,
13425 struct drm_crtc_state *old_crtc_state,
13426 struct drm_crtc_state *new_crtc_state)
13428 struct drm_device *dev = crtc->dev;
13429 struct drm_i915_private *dev_priv = to_i915(dev);
13430 struct intel_encoder *encoder;
13431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13432 struct intel_crtc_state *pipe_config, *sw_config;
13433 struct drm_atomic_state *old_state;
13436 old_state = old_crtc_state->state;
13437 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13438 pipe_config = to_intel_crtc_state(old_crtc_state);
13439 memset(pipe_config, 0, sizeof(*pipe_config));
13440 pipe_config->base.crtc = crtc;
13441 pipe_config->base.state = old_state;
13443 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13445 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13447 /* hw state is inconsistent with the pipe quirk */
13448 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13449 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13450 active = new_crtc_state->active;
13452 I915_STATE_WARN(new_crtc_state->active != active,
13453 "crtc active state doesn't match with hw state "
13454 "(expected %i, found %i)\n", new_crtc_state->active, active);
13456 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13457 "transitional active state does not match atomic hw state "
13458 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13460 for_each_encoder_on_crtc(dev, crtc, encoder) {
13463 active = encoder->get_hw_state(encoder, &pipe);
13464 I915_STATE_WARN(active != new_crtc_state->active,
13465 "[ENCODER:%i] active %i with crtc active %i\n",
13466 encoder->base.base.id, active, new_crtc_state->active);
13468 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13469 "Encoder connected to wrong pipe %c\n",
13473 pipe_config->output_types |= 1 << encoder->type;
13474 encoder->get_config(encoder, pipe_config);
13478 if (!new_crtc_state->active)
13481 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13483 sw_config = to_intel_crtc_state(crtc->state);
13484 if (!intel_pipe_config_compare(dev, sw_config,
13485 pipe_config, false)) {
13486 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13487 intel_dump_pipe_config(intel_crtc, pipe_config,
13489 intel_dump_pipe_config(intel_crtc, sw_config,
13495 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13496 struct intel_shared_dpll *pll,
13497 struct drm_crtc *crtc,
13498 struct drm_crtc_state *new_state)
13500 struct intel_dpll_hw_state dpll_hw_state;
13501 unsigned crtc_mask;
13504 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13506 DRM_DEBUG_KMS("%s\n", pll->name);
13508 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13510 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13511 I915_STATE_WARN(!pll->on && pll->active_mask,
13512 "pll in active use but not on in sw tracking\n");
13513 I915_STATE_WARN(pll->on && !pll->active_mask,
13514 "pll is on but not used by any active crtc\n");
13515 I915_STATE_WARN(pll->on != active,
13516 "pll on state mismatch (expected %i, found %i)\n",
13521 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13522 "more active pll users than references: %x vs %x\n",
13523 pll->active_mask, pll->config.crtc_mask);
13528 crtc_mask = 1 << drm_crtc_index(crtc);
13530 if (new_state->active)
13531 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13532 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13533 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13535 I915_STATE_WARN(pll->active_mask & crtc_mask,
13536 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13537 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13539 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13540 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13541 crtc_mask, pll->config.crtc_mask);
13543 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13545 sizeof(dpll_hw_state)),
13546 "pll hw state mismatch\n");
13550 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13551 struct drm_crtc_state *old_crtc_state,
13552 struct drm_crtc_state *new_crtc_state)
13554 struct drm_i915_private *dev_priv = to_i915(dev);
13555 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13556 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13558 if (new_state->shared_dpll)
13559 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13561 if (old_state->shared_dpll &&
13562 old_state->shared_dpll != new_state->shared_dpll) {
13563 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13564 struct intel_shared_dpll *pll = old_state->shared_dpll;
13566 I915_STATE_WARN(pll->active_mask & crtc_mask,
13567 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13568 pipe_name(drm_crtc_index(crtc)));
13569 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13570 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13571 pipe_name(drm_crtc_index(crtc)));
13576 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13577 struct drm_crtc_state *old_state,
13578 struct drm_crtc_state *new_state)
13580 if (!needs_modeset(new_state) &&
13581 !to_intel_crtc_state(new_state)->update_pipe)
13584 verify_wm_state(crtc, new_state);
13585 verify_connector_state(crtc->dev, crtc);
13586 verify_crtc_state(crtc, old_state, new_state);
13587 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13591 verify_disabled_dpll_state(struct drm_device *dev)
13593 struct drm_i915_private *dev_priv = to_i915(dev);
13596 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13597 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13601 intel_modeset_verify_disabled(struct drm_device *dev)
13603 verify_encoder_state(dev);
13604 verify_connector_state(dev, NULL);
13605 verify_disabled_dpll_state(dev);
13608 static void update_scanline_offset(struct intel_crtc *crtc)
13610 struct drm_device *dev = crtc->base.dev;
13613 * The scanline counter increments at the leading edge of hsync.
13615 * On most platforms it starts counting from vtotal-1 on the
13616 * first active line. That means the scanline counter value is
13617 * always one less than what we would expect. Ie. just after
13618 * start of vblank, which also occurs at start of hsync (on the
13619 * last active line), the scanline counter will read vblank_start-1.
13621 * On gen2 the scanline counter starts counting from 1 instead
13622 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13623 * to keep the value positive), instead of adding one.
13625 * On HSW+ the behaviour of the scanline counter depends on the output
13626 * type. For DP ports it behaves like most other platforms, but on HDMI
13627 * there's an extra 1 line difference. So we need to add two instead of
13628 * one to the value.
13630 if (IS_GEN2(dev)) {
13631 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13634 vtotal = adjusted_mode->crtc_vtotal;
13635 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13638 crtc->scanline_offset = vtotal - 1;
13639 } else if (HAS_DDI(dev) &&
13640 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13641 crtc->scanline_offset = 2;
13643 crtc->scanline_offset = 1;
13646 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13648 struct drm_device *dev = state->dev;
13649 struct drm_i915_private *dev_priv = to_i915(dev);
13650 struct intel_shared_dpll_config *shared_dpll = NULL;
13651 struct drm_crtc *crtc;
13652 struct drm_crtc_state *crtc_state;
13655 if (!dev_priv->display.crtc_compute_clock)
13658 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13660 struct intel_shared_dpll *old_dpll =
13661 to_intel_crtc_state(crtc->state)->shared_dpll;
13663 if (!needs_modeset(crtc_state))
13666 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13672 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13674 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13679 * This implements the workaround described in the "notes" section of the mode
13680 * set sequence documentation. When going from no pipes or single pipe to
13681 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13682 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13684 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13686 struct drm_crtc_state *crtc_state;
13687 struct intel_crtc *intel_crtc;
13688 struct drm_crtc *crtc;
13689 struct intel_crtc_state *first_crtc_state = NULL;
13690 struct intel_crtc_state *other_crtc_state = NULL;
13691 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13694 /* look at all crtc's that are going to be enabled in during modeset */
13695 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13696 intel_crtc = to_intel_crtc(crtc);
13698 if (!crtc_state->active || !needs_modeset(crtc_state))
13701 if (first_crtc_state) {
13702 other_crtc_state = to_intel_crtc_state(crtc_state);
13705 first_crtc_state = to_intel_crtc_state(crtc_state);
13706 first_pipe = intel_crtc->pipe;
13710 /* No workaround needed? */
13711 if (!first_crtc_state)
13714 /* w/a possibly needed, check how many crtc's are already enabled. */
13715 for_each_intel_crtc(state->dev, intel_crtc) {
13716 struct intel_crtc_state *pipe_config;
13718 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13719 if (IS_ERR(pipe_config))
13720 return PTR_ERR(pipe_config);
13722 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13724 if (!pipe_config->base.active ||
13725 needs_modeset(&pipe_config->base))
13728 /* 2 or more enabled crtcs means no need for w/a */
13729 if (enabled_pipe != INVALID_PIPE)
13732 enabled_pipe = intel_crtc->pipe;
13735 if (enabled_pipe != INVALID_PIPE)
13736 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13737 else if (other_crtc_state)
13738 other_crtc_state->hsw_workaround_pipe = first_pipe;
13743 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13745 struct drm_crtc *crtc;
13746 struct drm_crtc_state *crtc_state;
13749 /* add all active pipes to the state */
13750 for_each_crtc(state->dev, crtc) {
13751 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13752 if (IS_ERR(crtc_state))
13753 return PTR_ERR(crtc_state);
13755 if (!crtc_state->active || needs_modeset(crtc_state))
13758 crtc_state->mode_changed = true;
13760 ret = drm_atomic_add_affected_connectors(state, crtc);
13764 ret = drm_atomic_add_affected_planes(state, crtc);
13772 static int intel_modeset_checks(struct drm_atomic_state *state)
13774 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13775 struct drm_i915_private *dev_priv = to_i915(state->dev);
13776 struct drm_crtc *crtc;
13777 struct drm_crtc_state *crtc_state;
13780 if (!check_digital_port_conflicts(state)) {
13781 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13785 intel_state->modeset = true;
13786 intel_state->active_crtcs = dev_priv->active_crtcs;
13788 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13789 if (crtc_state->active)
13790 intel_state->active_crtcs |= 1 << i;
13792 intel_state->active_crtcs &= ~(1 << i);
13794 if (crtc_state->active != crtc->state->active)
13795 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13799 * See if the config requires any additional preparation, e.g.
13800 * to adjust global state with pipes off. We need to do this
13801 * here so we can get the modeset_pipe updated config for the new
13802 * mode set on this crtc. For other crtcs we need to use the
13803 * adjusted_mode bits in the crtc directly.
13805 if (dev_priv->display.modeset_calc_cdclk) {
13806 if (!intel_state->cdclk_pll_vco)
13807 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13808 if (!intel_state->cdclk_pll_vco)
13809 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13811 ret = dev_priv->display.modeset_calc_cdclk(state);
13815 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13816 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13817 ret = intel_modeset_all_pipes(state);
13822 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13823 intel_state->cdclk, intel_state->dev_cdclk);
13825 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13827 intel_modeset_clear_plls(state);
13829 if (IS_HASWELL(dev_priv))
13830 return haswell_mode_set_planes_workaround(state);
13836 * Handle calculation of various watermark data at the end of the atomic check
13837 * phase. The code here should be run after the per-crtc and per-plane 'check'
13838 * handlers to ensure that all derived state has been updated.
13840 static int calc_watermark_data(struct drm_atomic_state *state)
13842 struct drm_device *dev = state->dev;
13843 struct drm_i915_private *dev_priv = to_i915(dev);
13845 /* Is there platform-specific watermark information to calculate? */
13846 if (dev_priv->display.compute_global_watermarks)
13847 return dev_priv->display.compute_global_watermarks(state);
13853 * intel_atomic_check - validate state object
13855 * @state: state to validate
13857 static int intel_atomic_check(struct drm_device *dev,
13858 struct drm_atomic_state *state)
13860 struct drm_i915_private *dev_priv = to_i915(dev);
13861 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13862 struct drm_crtc *crtc;
13863 struct drm_crtc_state *crtc_state;
13865 bool any_ms = false;
13867 ret = drm_atomic_helper_check_modeset(dev, state);
13871 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13872 struct intel_crtc_state *pipe_config =
13873 to_intel_crtc_state(crtc_state);
13875 /* Catch I915_MODE_FLAG_INHERITED */
13876 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13877 crtc_state->mode_changed = true;
13879 if (!needs_modeset(crtc_state))
13882 if (!crtc_state->enable) {
13887 /* FIXME: For only active_changed we shouldn't need to do any
13888 * state recomputation at all. */
13890 ret = drm_atomic_add_affected_connectors(state, crtc);
13894 ret = intel_modeset_pipe_config(crtc, pipe_config);
13896 intel_dump_pipe_config(to_intel_crtc(crtc),
13897 pipe_config, "[failed]");
13901 if (i915.fastboot &&
13902 intel_pipe_config_compare(dev,
13903 to_intel_crtc_state(crtc->state),
13904 pipe_config, true)) {
13905 crtc_state->mode_changed = false;
13906 to_intel_crtc_state(crtc_state)->update_pipe = true;
13909 if (needs_modeset(crtc_state))
13912 ret = drm_atomic_add_affected_planes(state, crtc);
13916 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13917 needs_modeset(crtc_state) ?
13918 "[modeset]" : "[fastset]");
13922 ret = intel_modeset_checks(state);
13927 intel_state->cdclk = dev_priv->cdclk_freq;
13929 ret = drm_atomic_helper_check_planes(dev, state);
13933 intel_fbc_choose_crtc(dev_priv, state);
13934 return calc_watermark_data(state);
13937 static int intel_atomic_prepare_commit(struct drm_device *dev,
13938 struct drm_atomic_state *state,
13941 struct drm_i915_private *dev_priv = to_i915(dev);
13942 struct drm_plane_state *plane_state;
13943 struct drm_crtc_state *crtc_state;
13944 struct drm_plane *plane;
13945 struct drm_crtc *crtc;
13948 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13949 if (state->legacy_cursor_update)
13952 ret = intel_crtc_wait_for_pending_flips(crtc);
13956 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13957 flush_workqueue(dev_priv->wq);
13960 ret = mutex_lock_interruptible(&dev->struct_mutex);
13964 ret = drm_atomic_helper_prepare_planes(dev, state);
13965 mutex_unlock(&dev->struct_mutex);
13967 if (!ret && !nonblock) {
13968 for_each_plane_in_state(state, plane, plane_state, i) {
13969 struct intel_plane_state *intel_plane_state =
13970 to_intel_plane_state(plane_state);
13972 if (!intel_plane_state->wait_req)
13975 ret = i915_wait_request(intel_plane_state->wait_req,
13978 /* Any hang should be swallowed by the wait */
13979 WARN_ON(ret == -EIO);
13980 mutex_lock(&dev->struct_mutex);
13981 drm_atomic_helper_cleanup_planes(dev, state);
13982 mutex_unlock(&dev->struct_mutex);
13991 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13993 struct drm_device *dev = crtc->base.dev;
13995 if (!dev->max_vblank_count)
13996 return drm_accurate_vblank_count(&crtc->base);
13998 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14001 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14002 struct drm_i915_private *dev_priv,
14003 unsigned crtc_mask)
14005 unsigned last_vblank_count[I915_MAX_PIPES];
14012 for_each_pipe(dev_priv, pipe) {
14013 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14015 if (!((1 << pipe) & crtc_mask))
14018 ret = drm_crtc_vblank_get(crtc);
14019 if (WARN_ON(ret != 0)) {
14020 crtc_mask &= ~(1 << pipe);
14024 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14027 for_each_pipe(dev_priv, pipe) {
14028 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14031 if (!((1 << pipe) & crtc_mask))
14034 lret = wait_event_timeout(dev->vblank[pipe].queue,
14035 last_vblank_count[pipe] !=
14036 drm_crtc_vblank_count(crtc),
14037 msecs_to_jiffies(50));
14039 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14041 drm_crtc_vblank_put(crtc);
14045 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14047 /* fb updated, need to unpin old fb */
14048 if (crtc_state->fb_changed)
14051 /* wm changes, need vblank before final wm's */
14052 if (crtc_state->update_wm_post)
14056 * cxsr is re-enabled after vblank.
14057 * This is already handled by crtc_state->update_wm_post,
14058 * but added for clarity.
14060 if (crtc_state->disable_cxsr)
14066 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14068 struct drm_device *dev = state->dev;
14069 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14070 struct drm_i915_private *dev_priv = to_i915(dev);
14071 struct drm_crtc_state *old_crtc_state;
14072 struct drm_crtc *crtc;
14073 struct intel_crtc_state *intel_cstate;
14074 struct drm_plane *plane;
14075 struct drm_plane_state *plane_state;
14076 bool hw_check = intel_state->modeset;
14077 unsigned long put_domains[I915_MAX_PIPES] = {};
14078 unsigned crtc_vblank_mask = 0;
14081 for_each_plane_in_state(state, plane, plane_state, i) {
14082 struct intel_plane_state *intel_plane_state =
14083 to_intel_plane_state(plane_state);
14085 if (!intel_plane_state->wait_req)
14088 ret = i915_wait_request(intel_plane_state->wait_req,
14090 /* EIO should be eaten, and we can't get interrupted in the
14091 * worker, and blocking commits have waited already. */
14095 drm_atomic_helper_wait_for_dependencies(state);
14097 if (intel_state->modeset) {
14098 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14099 sizeof(intel_state->min_pixclk));
14100 dev_priv->active_crtcs = intel_state->active_crtcs;
14101 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14103 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14106 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14109 if (needs_modeset(crtc->state) ||
14110 to_intel_crtc_state(crtc->state)->update_pipe) {
14113 put_domains[to_intel_crtc(crtc)->pipe] =
14114 modeset_get_crtc_power_domains(crtc,
14115 to_intel_crtc_state(crtc->state));
14118 if (!needs_modeset(crtc->state))
14121 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14123 if (old_crtc_state->active) {
14124 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14125 dev_priv->display.crtc_disable(crtc);
14126 intel_crtc->active = false;
14127 intel_fbc_disable(intel_crtc);
14128 intel_disable_shared_dpll(intel_crtc);
14131 * Underruns don't always raise
14132 * interrupts, so check manually.
14134 intel_check_cpu_fifo_underruns(dev_priv);
14135 intel_check_pch_fifo_underruns(dev_priv);
14137 if (!crtc->state->active)
14138 intel_update_watermarks(crtc);
14142 /* Only after disabling all output pipelines that will be changed can we
14143 * update the the output configuration. */
14144 intel_modeset_update_crtc_state(state);
14146 if (intel_state->modeset) {
14147 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14149 if (dev_priv->display.modeset_commit_cdclk &&
14150 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14151 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14152 dev_priv->display.modeset_commit_cdclk(state);
14154 intel_modeset_verify_disabled(dev);
14157 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14158 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14160 bool modeset = needs_modeset(crtc->state);
14161 struct intel_crtc_state *pipe_config =
14162 to_intel_crtc_state(crtc->state);
14164 if (modeset && crtc->state->active) {
14165 update_scanline_offset(to_intel_crtc(crtc));
14166 dev_priv->display.crtc_enable(crtc);
14169 /* Complete events for now disable pipes here. */
14170 if (modeset && !crtc->state->active && crtc->state->event) {
14171 spin_lock_irq(&dev->event_lock);
14172 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14173 spin_unlock_irq(&dev->event_lock);
14175 crtc->state->event = NULL;
14179 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14181 if (crtc->state->active &&
14182 drm_atomic_get_existing_plane_state(state, crtc->primary))
14183 intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
14185 if (crtc->state->active)
14186 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14188 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
14189 crtc_vblank_mask |= 1 << i;
14192 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14193 * already, but still need the state for the delayed optimization. To
14195 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14196 * - schedule that vblank worker _before_ calling hw_done
14197 * - at the start of commit_tail, cancel it _synchrously
14198 * - switch over to the vblank wait helper in the core after that since
14199 * we don't need out special handling any more.
14201 if (!state->legacy_cursor_update)
14202 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14205 * Now that the vblank has passed, we can go ahead and program the
14206 * optimal watermarks on platforms that need two-step watermark
14209 * TODO: Move this (and other cleanup) to an async worker eventually.
14211 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14212 intel_cstate = to_intel_crtc_state(crtc->state);
14214 if (dev_priv->display.optimize_watermarks)
14215 dev_priv->display.optimize_watermarks(intel_cstate);
14218 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14219 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14221 if (put_domains[i])
14222 modeset_put_power_domains(dev_priv, put_domains[i]);
14224 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14227 drm_atomic_helper_commit_hw_done(state);
14229 if (intel_state->modeset)
14230 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14232 mutex_lock(&dev->struct_mutex);
14233 drm_atomic_helper_cleanup_planes(dev, state);
14234 mutex_unlock(&dev->struct_mutex);
14236 drm_atomic_helper_commit_cleanup_done(state);
14238 drm_atomic_state_free(state);
14240 /* As one of the primary mmio accessors, KMS has a high likelihood
14241 * of triggering bugs in unclaimed access. After we finish
14242 * modesetting, see if an error has been flagged, and if so
14243 * enable debugging for the next modeset - and hope we catch
14246 * XXX note that we assume display power is on at this point.
14247 * This might hold true now but we need to add pm helper to check
14248 * unclaimed only when the hardware is on, as atomic commits
14249 * can happen also when the device is completely off.
14251 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14254 static void intel_atomic_commit_work(struct work_struct *work)
14256 struct drm_atomic_state *state = container_of(work,
14257 struct drm_atomic_state,
14259 intel_atomic_commit_tail(state);
14262 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14264 struct drm_plane_state *old_plane_state;
14265 struct drm_plane *plane;
14268 for_each_plane_in_state(state, plane, old_plane_state, i)
14269 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14270 intel_fb_obj(plane->state->fb),
14271 to_intel_plane(plane)->frontbuffer_bit);
14275 * intel_atomic_commit - commit validated state object
14277 * @state: the top-level driver state object
14278 * @nonblock: nonblocking commit
14280 * This function commits a top-level state object that has been validated
14281 * with drm_atomic_helper_check().
14283 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14284 * nonblocking commits are only safe for pure plane updates. Everything else
14285 * should work though.
14288 * Zero for success or -errno.
14290 static int intel_atomic_commit(struct drm_device *dev,
14291 struct drm_atomic_state *state,
14294 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14295 struct drm_i915_private *dev_priv = to_i915(dev);
14298 if (intel_state->modeset && nonblock) {
14299 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14303 ret = drm_atomic_helper_setup_commit(state, nonblock);
14307 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14309 ret = intel_atomic_prepare_commit(dev, state, nonblock);
14311 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14315 drm_atomic_helper_swap_state(state, true);
14316 dev_priv->wm.distrust_bios_wm = false;
14317 dev_priv->wm.skl_results = intel_state->wm_results;
14318 intel_shared_dpll_commit(state);
14319 intel_atomic_track_fbs(state);
14322 queue_work(system_unbound_wq, &state->commit_work);
14324 intel_atomic_commit_tail(state);
14329 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14331 struct drm_device *dev = crtc->dev;
14332 struct drm_atomic_state *state;
14333 struct drm_crtc_state *crtc_state;
14336 state = drm_atomic_state_alloc(dev);
14338 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14339 crtc->base.id, crtc->name);
14343 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14346 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14347 ret = PTR_ERR_OR_ZERO(crtc_state);
14349 if (!crtc_state->active)
14352 crtc_state->mode_changed = true;
14353 ret = drm_atomic_commit(state);
14356 if (ret == -EDEADLK) {
14357 drm_atomic_state_clear(state);
14358 drm_modeset_backoff(state->acquire_ctx);
14364 drm_atomic_state_free(state);
14367 #undef for_each_intel_crtc_masked
14370 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14371 * drm_atomic_helper_legacy_gamma_set() directly.
14373 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14374 u16 *red, u16 *green, u16 *blue,
14377 struct drm_device *dev = crtc->dev;
14378 struct drm_mode_config *config = &dev->mode_config;
14379 struct drm_crtc_state *state;
14382 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14387 * Make sure we update the legacy properties so this works when
14388 * atomic is not enabled.
14391 state = crtc->state;
14393 drm_object_property_set_value(&crtc->base,
14394 config->degamma_lut_property,
14395 (state->degamma_lut) ?
14396 state->degamma_lut->base.id : 0);
14398 drm_object_property_set_value(&crtc->base,
14399 config->ctm_property,
14401 state->ctm->base.id : 0);
14403 drm_object_property_set_value(&crtc->base,
14404 config->gamma_lut_property,
14405 (state->gamma_lut) ?
14406 state->gamma_lut->base.id : 0);
14411 static const struct drm_crtc_funcs intel_crtc_funcs = {
14412 .gamma_set = intel_atomic_legacy_gamma_set,
14413 .set_config = drm_atomic_helper_set_config,
14414 .set_property = drm_atomic_helper_crtc_set_property,
14415 .destroy = intel_crtc_destroy,
14416 .page_flip = intel_crtc_page_flip,
14417 .atomic_duplicate_state = intel_crtc_duplicate_state,
14418 .atomic_destroy_state = intel_crtc_destroy_state,
14422 * intel_prepare_plane_fb - Prepare fb for usage on plane
14423 * @plane: drm plane to prepare for
14424 * @fb: framebuffer to prepare for presentation
14426 * Prepares a framebuffer for usage on a display plane. Generally this
14427 * involves pinning the underlying object and updating the frontbuffer tracking
14428 * bits. Some older platforms need special physical address handling for
14431 * Must be called with struct_mutex held.
14433 * Returns 0 on success, negative error code on failure.
14436 intel_prepare_plane_fb(struct drm_plane *plane,
14437 const struct drm_plane_state *new_state)
14439 struct drm_device *dev = plane->dev;
14440 struct drm_framebuffer *fb = new_state->fb;
14441 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14442 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14443 struct reservation_object *resv;
14446 if (!obj && !old_obj)
14450 struct drm_crtc_state *crtc_state =
14451 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14453 /* Big Hammer, we also need to ensure that any pending
14454 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14455 * current scanout is retired before unpinning the old
14456 * framebuffer. Note that we rely on userspace rendering
14457 * into the buffer attached to the pipe they are waiting
14458 * on. If not, userspace generates a GPU hang with IPEHR
14459 * point to the MI_WAIT_FOR_EVENT.
14461 * This should only fail upon a hung GPU, in which case we
14462 * can safely continue.
14464 if (needs_modeset(crtc_state))
14465 ret = i915_gem_object_wait_rendering(old_obj, true);
14467 /* GPU hangs should have been swallowed by the wait */
14468 WARN_ON(ret == -EIO);
14476 /* For framebuffer backed by dmabuf, wait for fence */
14477 resv = i915_gem_object_get_dmabuf_resv(obj);
14481 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14482 MAX_SCHEDULE_TIMEOUT);
14483 if (lret == -ERESTARTSYS)
14486 WARN(lret < 0, "waiting returns %li\n", lret);
14489 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14490 INTEL_INFO(dev)->cursor_needs_physical) {
14491 int align = IS_I830(dev) ? 16 * 1024 : 256;
14492 ret = i915_gem_object_attach_phys(obj, align);
14494 DRM_DEBUG_KMS("failed to attach phys object\n");
14496 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14500 to_intel_plane_state(new_state)->wait_req =
14501 i915_gem_active_get(&obj->last_write,
14502 &obj->base.dev->struct_mutex);
14509 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14510 * @plane: drm plane to clean up for
14511 * @fb: old framebuffer that was on plane
14513 * Cleans up a framebuffer that has just been removed from a plane.
14515 * Must be called with struct_mutex held.
14518 intel_cleanup_plane_fb(struct drm_plane *plane,
14519 const struct drm_plane_state *old_state)
14521 struct drm_device *dev = plane->dev;
14522 struct intel_plane_state *old_intel_state;
14523 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14524 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14525 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14527 old_intel_state = to_intel_plane_state(old_state);
14529 if (!obj && !old_obj)
14532 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14533 !INTEL_INFO(dev)->cursor_needs_physical))
14534 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14536 i915_gem_request_assign(&intel_state->wait_req, NULL);
14537 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14541 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14544 int crtc_clock, cdclk;
14546 if (!intel_crtc || !crtc_state->base.enable)
14547 return DRM_PLANE_HELPER_NO_SCALING;
14549 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14550 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14552 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14553 return DRM_PLANE_HELPER_NO_SCALING;
14556 * skl max scale is lower of:
14557 * close to 3 but not 3, -1 is for that purpose
14561 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14567 intel_check_primary_plane(struct drm_plane *plane,
14568 struct intel_crtc_state *crtc_state,
14569 struct intel_plane_state *state)
14571 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14572 struct drm_crtc *crtc = state->base.crtc;
14573 struct drm_framebuffer *fb = state->base.fb;
14574 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14575 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14576 bool can_position = false;
14579 if (INTEL_GEN(dev_priv) >= 9) {
14580 /* use scaler when colorkey is not required */
14581 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14583 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14585 can_position = true;
14588 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14589 &state->dst, &state->clip,
14590 state->base.rotation,
14591 min_scale, max_scale,
14592 can_position, true,
14600 if (INTEL_GEN(dev_priv) >= 9) {
14601 ret = skl_check_plane_surface(state);
14609 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14610 struct drm_crtc_state *old_crtc_state)
14612 struct drm_device *dev = crtc->dev;
14613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14614 struct intel_crtc_state *old_intel_state =
14615 to_intel_crtc_state(old_crtc_state);
14616 bool modeset = needs_modeset(crtc->state);
14618 /* Perform vblank evasion around commit operation */
14619 intel_pipe_update_start(intel_crtc);
14624 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14625 intel_color_set_csc(crtc->state);
14626 intel_color_load_luts(crtc->state);
14629 if (to_intel_crtc_state(crtc->state)->update_pipe)
14630 intel_update_pipe_config(intel_crtc, old_intel_state);
14631 else if (INTEL_INFO(dev)->gen >= 9)
14632 skl_detach_scalers(intel_crtc);
14635 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14636 struct drm_crtc_state *old_crtc_state)
14638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14640 intel_pipe_update_end(intel_crtc, NULL);
14644 * intel_plane_destroy - destroy a plane
14645 * @plane: plane to destroy
14647 * Common destruction function for all types of planes (primary, cursor,
14650 void intel_plane_destroy(struct drm_plane *plane)
14655 drm_plane_cleanup(plane);
14656 kfree(to_intel_plane(plane));
14659 const struct drm_plane_funcs intel_plane_funcs = {
14660 .update_plane = drm_atomic_helper_update_plane,
14661 .disable_plane = drm_atomic_helper_disable_plane,
14662 .destroy = intel_plane_destroy,
14663 .set_property = drm_atomic_helper_plane_set_property,
14664 .atomic_get_property = intel_plane_atomic_get_property,
14665 .atomic_set_property = intel_plane_atomic_set_property,
14666 .atomic_duplicate_state = intel_plane_duplicate_state,
14667 .atomic_destroy_state = intel_plane_destroy_state,
14671 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14674 struct intel_plane *primary = NULL;
14675 struct intel_plane_state *state = NULL;
14676 const uint32_t *intel_primary_formats;
14677 unsigned int num_formats;
14680 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14684 state = intel_create_plane_state(&primary->base);
14687 primary->base.state = &state->base;
14689 primary->can_scale = false;
14690 primary->max_downscale = 1;
14691 if (INTEL_INFO(dev)->gen >= 9) {
14692 primary->can_scale = true;
14693 state->scaler_id = -1;
14695 primary->pipe = pipe;
14696 primary->plane = pipe;
14697 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14698 primary->check_plane = intel_check_primary_plane;
14699 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14700 primary->plane = !pipe;
14702 if (INTEL_INFO(dev)->gen >= 9) {
14703 intel_primary_formats = skl_primary_formats;
14704 num_formats = ARRAY_SIZE(skl_primary_formats);
14706 primary->update_plane = skylake_update_primary_plane;
14707 primary->disable_plane = skylake_disable_primary_plane;
14708 } else if (HAS_PCH_SPLIT(dev)) {
14709 intel_primary_formats = i965_primary_formats;
14710 num_formats = ARRAY_SIZE(i965_primary_formats);
14712 primary->update_plane = ironlake_update_primary_plane;
14713 primary->disable_plane = i9xx_disable_primary_plane;
14714 } else if (INTEL_INFO(dev)->gen >= 4) {
14715 intel_primary_formats = i965_primary_formats;
14716 num_formats = ARRAY_SIZE(i965_primary_formats);
14718 primary->update_plane = i9xx_update_primary_plane;
14719 primary->disable_plane = i9xx_disable_primary_plane;
14721 intel_primary_formats = i8xx_primary_formats;
14722 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14724 primary->update_plane = i9xx_update_primary_plane;
14725 primary->disable_plane = i9xx_disable_primary_plane;
14728 if (INTEL_INFO(dev)->gen >= 9)
14729 ret = drm_universal_plane_init(dev, &primary->base, 0,
14730 &intel_plane_funcs,
14731 intel_primary_formats, num_formats,
14732 DRM_PLANE_TYPE_PRIMARY,
14733 "plane 1%c", pipe_name(pipe));
14734 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14735 ret = drm_universal_plane_init(dev, &primary->base, 0,
14736 &intel_plane_funcs,
14737 intel_primary_formats, num_formats,
14738 DRM_PLANE_TYPE_PRIMARY,
14739 "primary %c", pipe_name(pipe));
14741 ret = drm_universal_plane_init(dev, &primary->base, 0,
14742 &intel_plane_funcs,
14743 intel_primary_formats, num_formats,
14744 DRM_PLANE_TYPE_PRIMARY,
14745 "plane %c", plane_name(primary->plane));
14749 if (INTEL_INFO(dev)->gen >= 4)
14750 intel_create_rotation_property(dev, primary);
14752 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14754 return &primary->base;
14763 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14765 if (!dev->mode_config.rotation_property) {
14766 unsigned long flags = BIT(DRM_ROTATE_0) |
14767 BIT(DRM_ROTATE_180);
14769 if (INTEL_INFO(dev)->gen >= 9)
14770 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14772 dev->mode_config.rotation_property =
14773 drm_mode_create_rotation_property(dev, flags);
14775 if (dev->mode_config.rotation_property)
14776 drm_object_attach_property(&plane->base.base,
14777 dev->mode_config.rotation_property,
14778 plane->base.state->rotation);
14782 intel_check_cursor_plane(struct drm_plane *plane,
14783 struct intel_crtc_state *crtc_state,
14784 struct intel_plane_state *state)
14786 struct drm_crtc *crtc = crtc_state->base.crtc;
14787 struct drm_framebuffer *fb = state->base.fb;
14788 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14789 enum pipe pipe = to_intel_plane(plane)->pipe;
14793 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14794 &state->dst, &state->clip,
14795 state->base.rotation,
14796 DRM_PLANE_HELPER_NO_SCALING,
14797 DRM_PLANE_HELPER_NO_SCALING,
14798 true, true, &state->visible);
14802 /* if we want to turn off the cursor ignore width and height */
14806 /* Check for which cursor types we support */
14807 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14808 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14809 state->base.crtc_w, state->base.crtc_h);
14813 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14814 if (obj->base.size < stride * state->base.crtc_h) {
14815 DRM_DEBUG_KMS("buffer is too small\n");
14819 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14820 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14825 * There's something wrong with the cursor on CHV pipe C.
14826 * If it straddles the left edge of the screen then
14827 * moving it away from the edge or disabling it often
14828 * results in a pipe underrun, and often that can lead to
14829 * dead pipe (constant underrun reported, and it scans
14830 * out just a solid color). To recover from that, the
14831 * display power well must be turned off and on again.
14832 * Refuse the put the cursor into that compromised position.
14834 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14835 state->visible && state->base.crtc_x < 0) {
14836 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14844 intel_disable_cursor_plane(struct drm_plane *plane,
14845 struct drm_crtc *crtc)
14847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14849 intel_crtc->cursor_addr = 0;
14850 intel_crtc_update_cursor(crtc, NULL);
14854 intel_update_cursor_plane(struct drm_plane *plane,
14855 const struct intel_crtc_state *crtc_state,
14856 const struct intel_plane_state *state)
14858 struct drm_crtc *crtc = crtc_state->base.crtc;
14859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14860 struct drm_device *dev = plane->dev;
14861 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14866 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14867 addr = i915_gem_obj_ggtt_offset(obj);
14869 addr = obj->phys_handle->busaddr;
14871 intel_crtc->cursor_addr = addr;
14872 intel_crtc_update_cursor(crtc, state);
14875 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14878 struct intel_plane *cursor = NULL;
14879 struct intel_plane_state *state = NULL;
14882 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14886 state = intel_create_plane_state(&cursor->base);
14889 cursor->base.state = &state->base;
14891 cursor->can_scale = false;
14892 cursor->max_downscale = 1;
14893 cursor->pipe = pipe;
14894 cursor->plane = pipe;
14895 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14896 cursor->check_plane = intel_check_cursor_plane;
14897 cursor->update_plane = intel_update_cursor_plane;
14898 cursor->disable_plane = intel_disable_cursor_plane;
14900 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14901 &intel_plane_funcs,
14902 intel_cursor_formats,
14903 ARRAY_SIZE(intel_cursor_formats),
14904 DRM_PLANE_TYPE_CURSOR,
14905 "cursor %c", pipe_name(pipe));
14909 if (INTEL_INFO(dev)->gen >= 4) {
14910 if (!dev->mode_config.rotation_property)
14911 dev->mode_config.rotation_property =
14912 drm_mode_create_rotation_property(dev,
14913 BIT(DRM_ROTATE_0) |
14914 BIT(DRM_ROTATE_180));
14915 if (dev->mode_config.rotation_property)
14916 drm_object_attach_property(&cursor->base.base,
14917 dev->mode_config.rotation_property,
14918 state->base.rotation);
14921 if (INTEL_INFO(dev)->gen >=9)
14922 state->scaler_id = -1;
14924 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14926 return &cursor->base;
14935 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14936 struct intel_crtc_state *crtc_state)
14939 struct intel_scaler *intel_scaler;
14940 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14942 for (i = 0; i < intel_crtc->num_scalers; i++) {
14943 intel_scaler = &scaler_state->scalers[i];
14944 intel_scaler->in_use = 0;
14945 intel_scaler->mode = PS_SCALER_MODE_DYN;
14948 scaler_state->scaler_id = -1;
14951 static void intel_crtc_init(struct drm_device *dev, int pipe)
14953 struct drm_i915_private *dev_priv = to_i915(dev);
14954 struct intel_crtc *intel_crtc;
14955 struct intel_crtc_state *crtc_state = NULL;
14956 struct drm_plane *primary = NULL;
14957 struct drm_plane *cursor = NULL;
14960 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14961 if (intel_crtc == NULL)
14964 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14967 intel_crtc->config = crtc_state;
14968 intel_crtc->base.state = &crtc_state->base;
14969 crtc_state->base.crtc = &intel_crtc->base;
14971 /* initialize shared scalers */
14972 if (INTEL_INFO(dev)->gen >= 9) {
14973 if (pipe == PIPE_C)
14974 intel_crtc->num_scalers = 1;
14976 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14978 skl_init_scalers(dev, intel_crtc, crtc_state);
14981 primary = intel_primary_plane_create(dev, pipe);
14985 cursor = intel_cursor_plane_create(dev, pipe);
14989 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14990 cursor, &intel_crtc_funcs,
14991 "pipe %c", pipe_name(pipe));
14996 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14997 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14999 intel_crtc->pipe = pipe;
15000 intel_crtc->plane = pipe;
15001 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15002 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15003 intel_crtc->plane = !pipe;
15006 intel_crtc->cursor_base = ~0;
15007 intel_crtc->cursor_cntl = ~0;
15008 intel_crtc->cursor_size = ~0;
15010 intel_crtc->wm.cxsr_allowed = true;
15012 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15013 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15014 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15015 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15017 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15019 intel_color_init(&intel_crtc->base);
15021 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15025 intel_plane_destroy(primary);
15026 intel_plane_destroy(cursor);
15031 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15033 struct drm_encoder *encoder = connector->base.encoder;
15034 struct drm_device *dev = connector->base.dev;
15036 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15038 if (!encoder || WARN_ON(!encoder->crtc))
15039 return INVALID_PIPE;
15041 return to_intel_crtc(encoder->crtc)->pipe;
15044 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15045 struct drm_file *file)
15047 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15048 struct drm_crtc *drmmode_crtc;
15049 struct intel_crtc *crtc;
15051 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15055 crtc = to_intel_crtc(drmmode_crtc);
15056 pipe_from_crtc_id->pipe = crtc->pipe;
15061 static int intel_encoder_clones(struct intel_encoder *encoder)
15063 struct drm_device *dev = encoder->base.dev;
15064 struct intel_encoder *source_encoder;
15065 int index_mask = 0;
15068 for_each_intel_encoder(dev, source_encoder) {
15069 if (encoders_cloneable(encoder, source_encoder))
15070 index_mask |= (1 << entry);
15078 static bool has_edp_a(struct drm_device *dev)
15080 struct drm_i915_private *dev_priv = to_i915(dev);
15082 if (!IS_MOBILE(dev))
15085 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15088 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15094 static bool intel_crt_present(struct drm_device *dev)
15096 struct drm_i915_private *dev_priv = to_i915(dev);
15098 if (INTEL_INFO(dev)->gen >= 9)
15101 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15104 if (IS_CHERRYVIEW(dev))
15107 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15110 /* DDI E can't be used if DDI A requires 4 lanes */
15111 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15114 if (!dev_priv->vbt.int_crt_support)
15120 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15125 if (HAS_DDI(dev_priv))
15128 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15129 * everywhere where registers can be write protected.
15131 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15136 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15137 u32 val = I915_READ(PP_CONTROL(pps_idx));
15139 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15140 I915_WRITE(PP_CONTROL(pps_idx), val);
15144 static void intel_pps_init(struct drm_i915_private *dev_priv)
15146 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15147 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15148 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15149 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15151 dev_priv->pps_mmio_base = PPS_BASE;
15153 intel_pps_unlock_regs_wa(dev_priv);
15156 static void intel_setup_outputs(struct drm_device *dev)
15158 struct drm_i915_private *dev_priv = to_i915(dev);
15159 struct intel_encoder *encoder;
15160 bool dpd_is_edp = false;
15162 intel_pps_init(dev_priv);
15165 * intel_edp_init_connector() depends on this completing first, to
15166 * prevent the registeration of both eDP and LVDS and the incorrect
15167 * sharing of the PPS.
15169 intel_lvds_init(dev);
15171 if (intel_crt_present(dev))
15172 intel_crt_init(dev);
15174 if (IS_BROXTON(dev)) {
15176 * FIXME: Broxton doesn't support port detection via the
15177 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15178 * detect the ports.
15180 intel_ddi_init(dev, PORT_A);
15181 intel_ddi_init(dev, PORT_B);
15182 intel_ddi_init(dev, PORT_C);
15184 intel_dsi_init(dev);
15185 } else if (HAS_DDI(dev)) {
15189 * Haswell uses DDI functions to detect digital outputs.
15190 * On SKL pre-D0 the strap isn't connected, so we assume
15193 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15194 /* WaIgnoreDDIAStrap: skl */
15195 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15196 intel_ddi_init(dev, PORT_A);
15198 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15200 found = I915_READ(SFUSE_STRAP);
15202 if (found & SFUSE_STRAP_DDIB_DETECTED)
15203 intel_ddi_init(dev, PORT_B);
15204 if (found & SFUSE_STRAP_DDIC_DETECTED)
15205 intel_ddi_init(dev, PORT_C);
15206 if (found & SFUSE_STRAP_DDID_DETECTED)
15207 intel_ddi_init(dev, PORT_D);
15209 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15211 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15212 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15213 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15214 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15215 intel_ddi_init(dev, PORT_E);
15217 } else if (HAS_PCH_SPLIT(dev)) {
15219 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15221 if (has_edp_a(dev))
15222 intel_dp_init(dev, DP_A, PORT_A);
15224 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15225 /* PCH SDVOB multiplex with HDMIB */
15226 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15228 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15229 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15230 intel_dp_init(dev, PCH_DP_B, PORT_B);
15233 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15234 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15236 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15237 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15239 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15240 intel_dp_init(dev, PCH_DP_C, PORT_C);
15242 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15243 intel_dp_init(dev, PCH_DP_D, PORT_D);
15244 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15245 bool has_edp, has_port;
15248 * The DP_DETECTED bit is the latched state of the DDC
15249 * SDA pin at boot. However since eDP doesn't require DDC
15250 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15251 * eDP ports may have been muxed to an alternate function.
15252 * Thus we can't rely on the DP_DETECTED bit alone to detect
15253 * eDP ports. Consult the VBT as well as DP_DETECTED to
15254 * detect eDP ports.
15256 * Sadly the straps seem to be missing sometimes even for HDMI
15257 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15258 * and VBT for the presence of the port. Additionally we can't
15259 * trust the port type the VBT declares as we've seen at least
15260 * HDMI ports that the VBT claim are DP or eDP.
15262 has_edp = intel_dp_is_edp(dev, PORT_B);
15263 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15264 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15265 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15266 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15267 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15269 has_edp = intel_dp_is_edp(dev, PORT_C);
15270 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15271 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15272 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15273 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15274 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15276 if (IS_CHERRYVIEW(dev)) {
15278 * eDP not supported on port D,
15279 * so no need to worry about it
15281 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15282 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15283 intel_dp_init(dev, CHV_DP_D, PORT_D);
15284 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15285 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15288 intel_dsi_init(dev);
15289 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15290 bool found = false;
15292 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15293 DRM_DEBUG_KMS("probing SDVOB\n");
15294 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15295 if (!found && IS_G4X(dev)) {
15296 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15297 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15300 if (!found && IS_G4X(dev))
15301 intel_dp_init(dev, DP_B, PORT_B);
15304 /* Before G4X SDVOC doesn't have its own detect register */
15306 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15307 DRM_DEBUG_KMS("probing SDVOC\n");
15308 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15311 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15314 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15315 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15318 intel_dp_init(dev, DP_C, PORT_C);
15322 (I915_READ(DP_D) & DP_DETECTED))
15323 intel_dp_init(dev, DP_D, PORT_D);
15324 } else if (IS_GEN2(dev))
15325 intel_dvo_init(dev);
15327 if (SUPPORTS_TV(dev))
15328 intel_tv_init(dev);
15330 intel_psr_init(dev);
15332 for_each_intel_encoder(dev, encoder) {
15333 encoder->base.possible_crtcs = encoder->crtc_mask;
15334 encoder->base.possible_clones =
15335 intel_encoder_clones(encoder);
15338 intel_init_pch_refclk(dev);
15340 drm_helper_move_panel_connectors_to_head(dev);
15343 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15345 struct drm_device *dev = fb->dev;
15346 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15348 drm_framebuffer_cleanup(fb);
15349 mutex_lock(&dev->struct_mutex);
15350 WARN_ON(!intel_fb->obj->framebuffer_references--);
15351 i915_gem_object_put(intel_fb->obj);
15352 mutex_unlock(&dev->struct_mutex);
15356 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15357 struct drm_file *file,
15358 unsigned int *handle)
15360 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15361 struct drm_i915_gem_object *obj = intel_fb->obj;
15363 if (obj->userptr.mm) {
15364 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15368 return drm_gem_handle_create(file, &obj->base, handle);
15371 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15372 struct drm_file *file,
15373 unsigned flags, unsigned color,
15374 struct drm_clip_rect *clips,
15375 unsigned num_clips)
15377 struct drm_device *dev = fb->dev;
15378 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15379 struct drm_i915_gem_object *obj = intel_fb->obj;
15381 mutex_lock(&dev->struct_mutex);
15382 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15383 mutex_unlock(&dev->struct_mutex);
15388 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15389 .destroy = intel_user_framebuffer_destroy,
15390 .create_handle = intel_user_framebuffer_create_handle,
15391 .dirty = intel_user_framebuffer_dirty,
15395 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15396 uint32_t pixel_format)
15398 u32 gen = INTEL_INFO(dev)->gen;
15401 int cpp = drm_format_plane_cpp(pixel_format, 0);
15403 /* "The stride in bytes must not exceed the of the size of 8K
15404 * pixels and 32K bytes."
15406 return min(8192 * cpp, 32768);
15407 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15409 } else if (gen >= 4) {
15410 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15414 } else if (gen >= 3) {
15415 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15420 /* XXX DSPC is limited to 4k tiled */
15425 static int intel_framebuffer_init(struct drm_device *dev,
15426 struct intel_framebuffer *intel_fb,
15427 struct drm_mode_fb_cmd2 *mode_cmd,
15428 struct drm_i915_gem_object *obj)
15430 struct drm_i915_private *dev_priv = to_i915(dev);
15431 unsigned int tiling = i915_gem_object_get_tiling(obj);
15433 u32 pitch_limit, stride_alignment;
15435 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15437 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15439 * If there's a fence, enforce that
15440 * the fb modifier and tiling mode match.
15442 if (tiling != I915_TILING_NONE &&
15443 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15444 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15448 if (tiling == I915_TILING_X) {
15449 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15450 } else if (tiling == I915_TILING_Y) {
15451 DRM_DEBUG("No Y tiling for legacy addfb\n");
15456 /* Passed in modifier sanity checking. */
15457 switch (mode_cmd->modifier[0]) {
15458 case I915_FORMAT_MOD_Y_TILED:
15459 case I915_FORMAT_MOD_Yf_TILED:
15460 if (INTEL_INFO(dev)->gen < 9) {
15461 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15462 mode_cmd->modifier[0]);
15465 case DRM_FORMAT_MOD_NONE:
15466 case I915_FORMAT_MOD_X_TILED:
15469 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15470 mode_cmd->modifier[0]);
15475 * gen2/3 display engine uses the fence if present,
15476 * so the tiling mode must match the fb modifier exactly.
15478 if (INTEL_INFO(dev_priv)->gen < 4 &&
15479 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15480 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15484 stride_alignment = intel_fb_stride_alignment(dev_priv,
15485 mode_cmd->modifier[0],
15486 mode_cmd->pixel_format);
15487 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15488 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15489 mode_cmd->pitches[0], stride_alignment);
15493 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15494 mode_cmd->pixel_format);
15495 if (mode_cmd->pitches[0] > pitch_limit) {
15496 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15497 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15498 "tiled" : "linear",
15499 mode_cmd->pitches[0], pitch_limit);
15504 * If there's a fence, enforce that
15505 * the fb pitch and fence stride match.
15507 if (tiling != I915_TILING_NONE &&
15508 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15509 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15510 mode_cmd->pitches[0],
15511 i915_gem_object_get_stride(obj));
15515 /* Reject formats not supported by any plane early. */
15516 switch (mode_cmd->pixel_format) {
15517 case DRM_FORMAT_C8:
15518 case DRM_FORMAT_RGB565:
15519 case DRM_FORMAT_XRGB8888:
15520 case DRM_FORMAT_ARGB8888:
15522 case DRM_FORMAT_XRGB1555:
15523 if (INTEL_INFO(dev)->gen > 3) {
15524 DRM_DEBUG("unsupported pixel format: %s\n",
15525 drm_get_format_name(mode_cmd->pixel_format));
15529 case DRM_FORMAT_ABGR8888:
15530 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15531 INTEL_INFO(dev)->gen < 9) {
15532 DRM_DEBUG("unsupported pixel format: %s\n",
15533 drm_get_format_name(mode_cmd->pixel_format));
15537 case DRM_FORMAT_XBGR8888:
15538 case DRM_FORMAT_XRGB2101010:
15539 case DRM_FORMAT_XBGR2101010:
15540 if (INTEL_INFO(dev)->gen < 4) {
15541 DRM_DEBUG("unsupported pixel format: %s\n",
15542 drm_get_format_name(mode_cmd->pixel_format));
15546 case DRM_FORMAT_ABGR2101010:
15547 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15548 DRM_DEBUG("unsupported pixel format: %s\n",
15549 drm_get_format_name(mode_cmd->pixel_format));
15553 case DRM_FORMAT_YUYV:
15554 case DRM_FORMAT_UYVY:
15555 case DRM_FORMAT_YVYU:
15556 case DRM_FORMAT_VYUY:
15557 if (INTEL_INFO(dev)->gen < 5) {
15558 DRM_DEBUG("unsupported pixel format: %s\n",
15559 drm_get_format_name(mode_cmd->pixel_format));
15564 DRM_DEBUG("unsupported pixel format: %s\n",
15565 drm_get_format_name(mode_cmd->pixel_format));
15569 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15570 if (mode_cmd->offsets[0] != 0)
15573 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15574 intel_fb->obj = obj;
15576 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15580 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15582 DRM_ERROR("framebuffer init failed %d\n", ret);
15586 intel_fb->obj->framebuffer_references++;
15591 static struct drm_framebuffer *
15592 intel_user_framebuffer_create(struct drm_device *dev,
15593 struct drm_file *filp,
15594 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15596 struct drm_framebuffer *fb;
15597 struct drm_i915_gem_object *obj;
15598 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15600 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15602 return ERR_PTR(-ENOENT);
15604 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15606 i915_gem_object_put_unlocked(obj);
15611 #ifndef CONFIG_DRM_FBDEV_EMULATION
15612 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15617 static const struct drm_mode_config_funcs intel_mode_funcs = {
15618 .fb_create = intel_user_framebuffer_create,
15619 .output_poll_changed = intel_fbdev_output_poll_changed,
15620 .atomic_check = intel_atomic_check,
15621 .atomic_commit = intel_atomic_commit,
15622 .atomic_state_alloc = intel_atomic_state_alloc,
15623 .atomic_state_clear = intel_atomic_state_clear,
15627 * intel_init_display_hooks - initialize the display modesetting hooks
15628 * @dev_priv: device private
15630 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15632 if (INTEL_INFO(dev_priv)->gen >= 9) {
15633 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15634 dev_priv->display.get_initial_plane_config =
15635 skylake_get_initial_plane_config;
15636 dev_priv->display.crtc_compute_clock =
15637 haswell_crtc_compute_clock;
15638 dev_priv->display.crtc_enable = haswell_crtc_enable;
15639 dev_priv->display.crtc_disable = haswell_crtc_disable;
15640 } else if (HAS_DDI(dev_priv)) {
15641 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15642 dev_priv->display.get_initial_plane_config =
15643 ironlake_get_initial_plane_config;
15644 dev_priv->display.crtc_compute_clock =
15645 haswell_crtc_compute_clock;
15646 dev_priv->display.crtc_enable = haswell_crtc_enable;
15647 dev_priv->display.crtc_disable = haswell_crtc_disable;
15648 } else if (HAS_PCH_SPLIT(dev_priv)) {
15649 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15650 dev_priv->display.get_initial_plane_config =
15651 ironlake_get_initial_plane_config;
15652 dev_priv->display.crtc_compute_clock =
15653 ironlake_crtc_compute_clock;
15654 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15655 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15656 } else if (IS_CHERRYVIEW(dev_priv)) {
15657 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15658 dev_priv->display.get_initial_plane_config =
15659 i9xx_get_initial_plane_config;
15660 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15661 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15662 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15663 } else if (IS_VALLEYVIEW(dev_priv)) {
15664 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15665 dev_priv->display.get_initial_plane_config =
15666 i9xx_get_initial_plane_config;
15667 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15668 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15669 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15670 } else if (IS_G4X(dev_priv)) {
15671 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15672 dev_priv->display.get_initial_plane_config =
15673 i9xx_get_initial_plane_config;
15674 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15675 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15676 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15677 } else if (IS_PINEVIEW(dev_priv)) {
15678 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15679 dev_priv->display.get_initial_plane_config =
15680 i9xx_get_initial_plane_config;
15681 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15682 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15683 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15684 } else if (!IS_GEN2(dev_priv)) {
15685 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15686 dev_priv->display.get_initial_plane_config =
15687 i9xx_get_initial_plane_config;
15688 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15689 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15690 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15692 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15693 dev_priv->display.get_initial_plane_config =
15694 i9xx_get_initial_plane_config;
15695 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15696 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15697 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15700 /* Returns the core display clock speed */
15701 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15702 dev_priv->display.get_display_clock_speed =
15703 skylake_get_display_clock_speed;
15704 else if (IS_BROXTON(dev_priv))
15705 dev_priv->display.get_display_clock_speed =
15706 broxton_get_display_clock_speed;
15707 else if (IS_BROADWELL(dev_priv))
15708 dev_priv->display.get_display_clock_speed =
15709 broadwell_get_display_clock_speed;
15710 else if (IS_HASWELL(dev_priv))
15711 dev_priv->display.get_display_clock_speed =
15712 haswell_get_display_clock_speed;
15713 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15714 dev_priv->display.get_display_clock_speed =
15715 valleyview_get_display_clock_speed;
15716 else if (IS_GEN5(dev_priv))
15717 dev_priv->display.get_display_clock_speed =
15718 ilk_get_display_clock_speed;
15719 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15720 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15721 dev_priv->display.get_display_clock_speed =
15722 i945_get_display_clock_speed;
15723 else if (IS_GM45(dev_priv))
15724 dev_priv->display.get_display_clock_speed =
15725 gm45_get_display_clock_speed;
15726 else if (IS_CRESTLINE(dev_priv))
15727 dev_priv->display.get_display_clock_speed =
15728 i965gm_get_display_clock_speed;
15729 else if (IS_PINEVIEW(dev_priv))
15730 dev_priv->display.get_display_clock_speed =
15731 pnv_get_display_clock_speed;
15732 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15733 dev_priv->display.get_display_clock_speed =
15734 g33_get_display_clock_speed;
15735 else if (IS_I915G(dev_priv))
15736 dev_priv->display.get_display_clock_speed =
15737 i915_get_display_clock_speed;
15738 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15739 dev_priv->display.get_display_clock_speed =
15740 i9xx_misc_get_display_clock_speed;
15741 else if (IS_I915GM(dev_priv))
15742 dev_priv->display.get_display_clock_speed =
15743 i915gm_get_display_clock_speed;
15744 else if (IS_I865G(dev_priv))
15745 dev_priv->display.get_display_clock_speed =
15746 i865_get_display_clock_speed;
15747 else if (IS_I85X(dev_priv))
15748 dev_priv->display.get_display_clock_speed =
15749 i85x_get_display_clock_speed;
15751 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15752 dev_priv->display.get_display_clock_speed =
15753 i830_get_display_clock_speed;
15756 if (IS_GEN5(dev_priv)) {
15757 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15758 } else if (IS_GEN6(dev_priv)) {
15759 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15760 } else if (IS_IVYBRIDGE(dev_priv)) {
15761 /* FIXME: detect B0+ stepping and use auto training */
15762 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15763 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15764 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15767 if (IS_BROADWELL(dev_priv)) {
15768 dev_priv->display.modeset_commit_cdclk =
15769 broadwell_modeset_commit_cdclk;
15770 dev_priv->display.modeset_calc_cdclk =
15771 broadwell_modeset_calc_cdclk;
15772 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15773 dev_priv->display.modeset_commit_cdclk =
15774 valleyview_modeset_commit_cdclk;
15775 dev_priv->display.modeset_calc_cdclk =
15776 valleyview_modeset_calc_cdclk;
15777 } else if (IS_BROXTON(dev_priv)) {
15778 dev_priv->display.modeset_commit_cdclk =
15779 bxt_modeset_commit_cdclk;
15780 dev_priv->display.modeset_calc_cdclk =
15781 bxt_modeset_calc_cdclk;
15782 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15783 dev_priv->display.modeset_commit_cdclk =
15784 skl_modeset_commit_cdclk;
15785 dev_priv->display.modeset_calc_cdclk =
15786 skl_modeset_calc_cdclk;
15789 switch (INTEL_INFO(dev_priv)->gen) {
15791 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15795 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15800 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15804 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15807 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15808 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15811 /* Drop through - unsupported since execlist only. */
15813 /* Default just returns -ENODEV to indicate unsupported */
15814 dev_priv->display.queue_flip = intel_default_queue_flip;
15819 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15820 * resume, or other times. This quirk makes sure that's the case for
15821 * affected systems.
15823 static void quirk_pipea_force(struct drm_device *dev)
15825 struct drm_i915_private *dev_priv = to_i915(dev);
15827 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15828 DRM_INFO("applying pipe a force quirk\n");
15831 static void quirk_pipeb_force(struct drm_device *dev)
15833 struct drm_i915_private *dev_priv = to_i915(dev);
15835 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15836 DRM_INFO("applying pipe b force quirk\n");
15840 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15842 static void quirk_ssc_force_disable(struct drm_device *dev)
15844 struct drm_i915_private *dev_priv = to_i915(dev);
15845 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15846 DRM_INFO("applying lvds SSC disable quirk\n");
15850 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15853 static void quirk_invert_brightness(struct drm_device *dev)
15855 struct drm_i915_private *dev_priv = to_i915(dev);
15856 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15857 DRM_INFO("applying inverted panel brightness quirk\n");
15860 /* Some VBT's incorrectly indicate no backlight is present */
15861 static void quirk_backlight_present(struct drm_device *dev)
15863 struct drm_i915_private *dev_priv = to_i915(dev);
15864 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15865 DRM_INFO("applying backlight present quirk\n");
15868 struct intel_quirk {
15870 int subsystem_vendor;
15871 int subsystem_device;
15872 void (*hook)(struct drm_device *dev);
15875 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15876 struct intel_dmi_quirk {
15877 void (*hook)(struct drm_device *dev);
15878 const struct dmi_system_id (*dmi_id_list)[];
15881 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15883 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15887 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15889 .dmi_id_list = &(const struct dmi_system_id[]) {
15891 .callback = intel_dmi_reverse_brightness,
15892 .ident = "NCR Corporation",
15893 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15894 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15897 { } /* terminating entry */
15899 .hook = quirk_invert_brightness,
15903 static struct intel_quirk intel_quirks[] = {
15904 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15905 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15907 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15908 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15910 /* 830 needs to leave pipe A & dpll A up */
15911 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15913 /* 830 needs to leave pipe B & dpll B up */
15914 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15916 /* Lenovo U160 cannot use SSC on LVDS */
15917 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15919 /* Sony Vaio Y cannot use SSC on LVDS */
15920 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15922 /* Acer Aspire 5734Z must invert backlight brightness */
15923 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15925 /* Acer/eMachines G725 */
15926 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15928 /* Acer/eMachines e725 */
15929 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15931 /* Acer/Packard Bell NCL20 */
15932 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15934 /* Acer Aspire 4736Z */
15935 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15937 /* Acer Aspire 5336 */
15938 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15940 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15941 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15943 /* Acer C720 Chromebook (Core i3 4005U) */
15944 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15946 /* Apple Macbook 2,1 (Core 2 T7400) */
15947 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15949 /* Apple Macbook 4,1 */
15950 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15952 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15953 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15955 /* HP Chromebook 14 (Celeron 2955U) */
15956 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15958 /* Dell Chromebook 11 */
15959 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15961 /* Dell Chromebook 11 (2015 version) */
15962 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15965 static void intel_init_quirks(struct drm_device *dev)
15967 struct pci_dev *d = dev->pdev;
15970 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15971 struct intel_quirk *q = &intel_quirks[i];
15973 if (d->device == q->device &&
15974 (d->subsystem_vendor == q->subsystem_vendor ||
15975 q->subsystem_vendor == PCI_ANY_ID) &&
15976 (d->subsystem_device == q->subsystem_device ||
15977 q->subsystem_device == PCI_ANY_ID))
15980 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15981 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15982 intel_dmi_quirks[i].hook(dev);
15986 /* Disable the VGA plane that we never use */
15987 static void i915_disable_vga(struct drm_device *dev)
15989 struct drm_i915_private *dev_priv = to_i915(dev);
15991 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15993 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15994 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15995 outb(SR01, VGA_SR_INDEX);
15996 sr1 = inb(VGA_SR_DATA);
15997 outb(sr1 | 1<<5, VGA_SR_DATA);
15998 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
16001 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16002 POSTING_READ(vga_reg);
16005 void intel_modeset_init_hw(struct drm_device *dev)
16007 struct drm_i915_private *dev_priv = to_i915(dev);
16009 intel_update_cdclk(dev);
16011 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16013 intel_init_clock_gating(dev);
16017 * Calculate what we think the watermarks should be for the state we've read
16018 * out of the hardware and then immediately program those watermarks so that
16019 * we ensure the hardware settings match our internal state.
16021 * We can calculate what we think WM's should be by creating a duplicate of the
16022 * current state (which was constructed during hardware readout) and running it
16023 * through the atomic check code to calculate new watermark values in the
16026 static void sanitize_watermarks(struct drm_device *dev)
16028 struct drm_i915_private *dev_priv = to_i915(dev);
16029 struct drm_atomic_state *state;
16030 struct drm_crtc *crtc;
16031 struct drm_crtc_state *cstate;
16032 struct drm_modeset_acquire_ctx ctx;
16036 /* Only supported on platforms that use atomic watermark design */
16037 if (!dev_priv->display.optimize_watermarks)
16041 * We need to hold connection_mutex before calling duplicate_state so
16042 * that the connector loop is protected.
16044 drm_modeset_acquire_init(&ctx, 0);
16046 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16047 if (ret == -EDEADLK) {
16048 drm_modeset_backoff(&ctx);
16050 } else if (WARN_ON(ret)) {
16054 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16055 if (WARN_ON(IS_ERR(state)))
16059 * Hardware readout is the only time we don't want to calculate
16060 * intermediate watermarks (since we don't trust the current
16063 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16065 ret = intel_atomic_check(dev, state);
16068 * If we fail here, it means that the hardware appears to be
16069 * programmed in a way that shouldn't be possible, given our
16070 * understanding of watermark requirements. This might mean a
16071 * mistake in the hardware readout code or a mistake in the
16072 * watermark calculations for a given platform. Raise a WARN
16073 * so that this is noticeable.
16075 * If this actually happens, we'll have to just leave the
16076 * BIOS-programmed watermarks untouched and hope for the best.
16078 WARN(true, "Could not determine valid watermarks for inherited state\n");
16082 /* Write calculated watermark values back */
16083 for_each_crtc_in_state(state, crtc, cstate, i) {
16084 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16086 cs->wm.need_postvbl_update = true;
16087 dev_priv->display.optimize_watermarks(cs);
16090 drm_atomic_state_free(state);
16092 drm_modeset_drop_locks(&ctx);
16093 drm_modeset_acquire_fini(&ctx);
16096 void intel_modeset_init(struct drm_device *dev)
16098 struct drm_i915_private *dev_priv = to_i915(dev);
16099 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16102 struct intel_crtc *crtc;
16104 drm_mode_config_init(dev);
16106 dev->mode_config.min_width = 0;
16107 dev->mode_config.min_height = 0;
16109 dev->mode_config.preferred_depth = 24;
16110 dev->mode_config.prefer_shadow = 1;
16112 dev->mode_config.allow_fb_modifiers = true;
16114 dev->mode_config.funcs = &intel_mode_funcs;
16116 intel_init_quirks(dev);
16118 intel_init_pm(dev);
16120 if (INTEL_INFO(dev)->num_pipes == 0)
16124 * There may be no VBT; and if the BIOS enabled SSC we can
16125 * just keep using it to avoid unnecessary flicker. Whereas if the
16126 * BIOS isn't using it, don't assume it will work even if the VBT
16127 * indicates as much.
16129 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16130 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16133 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16134 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16135 bios_lvds_use_ssc ? "en" : "dis",
16136 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16137 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16141 if (IS_GEN2(dev)) {
16142 dev->mode_config.max_width = 2048;
16143 dev->mode_config.max_height = 2048;
16144 } else if (IS_GEN3(dev)) {
16145 dev->mode_config.max_width = 4096;
16146 dev->mode_config.max_height = 4096;
16148 dev->mode_config.max_width = 8192;
16149 dev->mode_config.max_height = 8192;
16152 if (IS_845G(dev) || IS_I865G(dev)) {
16153 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16154 dev->mode_config.cursor_height = 1023;
16155 } else if (IS_GEN2(dev)) {
16156 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16157 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16159 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16160 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16163 dev->mode_config.fb_base = ggtt->mappable_base;
16165 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16166 INTEL_INFO(dev)->num_pipes,
16167 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16169 for_each_pipe(dev_priv, pipe) {
16170 intel_crtc_init(dev, pipe);
16171 for_each_sprite(dev_priv, pipe, sprite) {
16172 ret = intel_plane_init(dev, pipe, sprite);
16174 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16175 pipe_name(pipe), sprite_name(pipe, sprite), ret);
16179 intel_update_czclk(dev_priv);
16180 intel_update_cdclk(dev);
16182 intel_shared_dpll_init(dev);
16184 if (dev_priv->max_cdclk_freq == 0)
16185 intel_update_max_cdclk(dev);
16187 /* Just disable it once at startup */
16188 i915_disable_vga(dev);
16189 intel_setup_outputs(dev);
16191 drm_modeset_lock_all(dev);
16192 intel_modeset_setup_hw_state(dev);
16193 drm_modeset_unlock_all(dev);
16195 for_each_intel_crtc(dev, crtc) {
16196 struct intel_initial_plane_config plane_config = {};
16202 * Note that reserving the BIOS fb up front prevents us
16203 * from stuffing other stolen allocations like the ring
16204 * on top. This prevents some ugliness at boot time, and
16205 * can even allow for smooth boot transitions if the BIOS
16206 * fb is large enough for the active pipe configuration.
16208 dev_priv->display.get_initial_plane_config(crtc,
16212 * If the fb is shared between multiple heads, we'll
16213 * just get the first one.
16215 intel_find_initial_plane_obj(crtc, &plane_config);
16219 * Make sure hardware watermarks really match the state we read out.
16220 * Note that we need to do this after reconstructing the BIOS fb's
16221 * since the watermark calculation done here will use pstate->fb.
16223 sanitize_watermarks(dev);
16226 static void intel_enable_pipe_a(struct drm_device *dev)
16228 struct intel_connector *connector;
16229 struct drm_connector *crt = NULL;
16230 struct intel_load_detect_pipe load_detect_temp;
16231 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16233 /* We can't just switch on the pipe A, we need to set things up with a
16234 * proper mode and output configuration. As a gross hack, enable pipe A
16235 * by enabling the load detect pipe once. */
16236 for_each_intel_connector(dev, connector) {
16237 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16238 crt = &connector->base;
16246 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16247 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16251 intel_check_plane_mapping(struct intel_crtc *crtc)
16253 struct drm_device *dev = crtc->base.dev;
16254 struct drm_i915_private *dev_priv = to_i915(dev);
16257 if (INTEL_INFO(dev)->num_pipes == 1)
16260 val = I915_READ(DSPCNTR(!crtc->plane));
16262 if ((val & DISPLAY_PLANE_ENABLE) &&
16263 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16269 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16271 struct drm_device *dev = crtc->base.dev;
16272 struct intel_encoder *encoder;
16274 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16280 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
16282 struct drm_device *dev = encoder->base.dev;
16283 struct intel_connector *connector;
16285 for_each_connector_on_encoder(dev, &encoder->base, connector)
16291 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16292 enum transcoder pch_transcoder)
16294 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16295 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16298 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16300 struct drm_device *dev = crtc->base.dev;
16301 struct drm_i915_private *dev_priv = to_i915(dev);
16302 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16304 /* Clear any frame start delays used for debugging left by the BIOS */
16305 if (!transcoder_is_dsi(cpu_transcoder)) {
16306 i915_reg_t reg = PIPECONF(cpu_transcoder);
16309 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16312 /* restore vblank interrupts to correct state */
16313 drm_crtc_vblank_reset(&crtc->base);
16314 if (crtc->active) {
16315 struct intel_plane *plane;
16317 drm_crtc_vblank_on(&crtc->base);
16319 /* Disable everything but the primary plane */
16320 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16321 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16324 plane->disable_plane(&plane->base, &crtc->base);
16328 /* We need to sanitize the plane -> pipe mapping first because this will
16329 * disable the crtc (and hence change the state) if it is wrong. Note
16330 * that gen4+ has a fixed plane -> pipe mapping. */
16331 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16334 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16335 crtc->base.base.id, crtc->base.name);
16337 /* Pipe has the wrong plane attached and the plane is active.
16338 * Temporarily change the plane mapping and disable everything
16340 plane = crtc->plane;
16341 to_intel_plane_state(crtc->base.primary->state)->visible = true;
16342 crtc->plane = !plane;
16343 intel_crtc_disable_noatomic(&crtc->base);
16344 crtc->plane = plane;
16347 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16348 crtc->pipe == PIPE_A && !crtc->active) {
16349 /* BIOS forgot to enable pipe A, this mostly happens after
16350 * resume. Force-enable the pipe to fix this, the update_dpms
16351 * call below we restore the pipe to the right state, but leave
16352 * the required bits on. */
16353 intel_enable_pipe_a(dev);
16356 /* Adjust the state of the output pipe according to whether we
16357 * have active connectors/encoders. */
16358 if (crtc->active && !intel_crtc_has_encoders(crtc))
16359 intel_crtc_disable_noatomic(&crtc->base);
16361 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16363 * We start out with underrun reporting disabled to avoid races.
16364 * For correct bookkeeping mark this on active crtcs.
16366 * Also on gmch platforms we dont have any hardware bits to
16367 * disable the underrun reporting. Which means we need to start
16368 * out with underrun reporting disabled also on inactive pipes,
16369 * since otherwise we'll complain about the garbage we read when
16370 * e.g. coming up after runtime pm.
16372 * No protection against concurrent access is required - at
16373 * worst a fifo underrun happens which also sets this to false.
16375 crtc->cpu_fifo_underrun_disabled = true;
16377 * We track the PCH trancoder underrun reporting state
16378 * within the crtc. With crtc for pipe A housing the underrun
16379 * reporting state for PCH transcoder A, crtc for pipe B housing
16380 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16381 * and marking underrun reporting as disabled for the non-existing
16382 * PCH transcoders B and C would prevent enabling the south
16383 * error interrupt (see cpt_can_enable_serr_int()).
16385 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16386 crtc->pch_fifo_underrun_disabled = true;
16390 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16392 struct intel_connector *connector;
16393 struct drm_device *dev = encoder->base.dev;
16395 /* We need to check both for a crtc link (meaning that the
16396 * encoder is active and trying to read from a pipe) and the
16397 * pipe itself being active. */
16398 bool has_active_crtc = encoder->base.crtc &&
16399 to_intel_crtc(encoder->base.crtc)->active;
16401 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
16402 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16403 encoder->base.base.id,
16404 encoder->base.name);
16406 /* Connector is active, but has no active pipe. This is
16407 * fallout from our resume register restoring. Disable
16408 * the encoder manually again. */
16409 if (encoder->base.crtc) {
16410 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16411 encoder->base.base.id,
16412 encoder->base.name);
16413 encoder->disable(encoder);
16414 if (encoder->post_disable)
16415 encoder->post_disable(encoder);
16417 encoder->base.crtc = NULL;
16419 /* Inconsistent output/port/pipe state happens presumably due to
16420 * a bug in one of the get_hw_state functions. Or someplace else
16421 * in our code, like the register restore mess on resume. Clamp
16422 * things to off as a safer default. */
16423 for_each_intel_connector(dev, connector) {
16424 if (connector->encoder != encoder)
16426 connector->base.dpms = DRM_MODE_DPMS_OFF;
16427 connector->base.encoder = NULL;
16430 /* Enabled encoders without active connectors will be fixed in
16431 * the crtc fixup. */
16434 void i915_redisable_vga_power_on(struct drm_device *dev)
16436 struct drm_i915_private *dev_priv = to_i915(dev);
16437 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16439 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16440 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16441 i915_disable_vga(dev);
16445 void i915_redisable_vga(struct drm_device *dev)
16447 struct drm_i915_private *dev_priv = to_i915(dev);
16449 /* This function can be called both from intel_modeset_setup_hw_state or
16450 * at a very early point in our resume sequence, where the power well
16451 * structures are not yet restored. Since this function is at a very
16452 * paranoid "someone might have enabled VGA while we were not looking"
16453 * level, just check if the power well is enabled instead of trying to
16454 * follow the "don't touch the power well if we don't need it" policy
16455 * the rest of the driver uses. */
16456 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16459 i915_redisable_vga_power_on(dev);
16461 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16464 static bool primary_get_hw_state(struct intel_plane *plane)
16466 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16468 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16471 /* FIXME read out full plane state for all planes */
16472 static void readout_plane_state(struct intel_crtc *crtc)
16474 struct drm_plane *primary = crtc->base.primary;
16475 struct intel_plane_state *plane_state =
16476 to_intel_plane_state(primary->state);
16478 plane_state->visible = crtc->active &&
16479 primary_get_hw_state(to_intel_plane(primary));
16481 if (plane_state->visible)
16482 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16485 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16487 struct drm_i915_private *dev_priv = to_i915(dev);
16489 struct intel_crtc *crtc;
16490 struct intel_encoder *encoder;
16491 struct intel_connector *connector;
16494 dev_priv->active_crtcs = 0;
16496 for_each_intel_crtc(dev, crtc) {
16497 struct intel_crtc_state *crtc_state = crtc->config;
16500 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16501 memset(crtc_state, 0, sizeof(*crtc_state));
16502 crtc_state->base.crtc = &crtc->base;
16504 crtc_state->base.active = crtc_state->base.enable =
16505 dev_priv->display.get_pipe_config(crtc, crtc_state);
16507 crtc->base.enabled = crtc_state->base.enable;
16508 crtc->active = crtc_state->base.active;
16510 if (crtc_state->base.active) {
16511 dev_priv->active_crtcs |= 1 << crtc->pipe;
16513 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16514 pixclk = ilk_pipe_pixel_rate(crtc_state);
16515 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16516 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16518 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16520 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16521 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16522 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16525 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16527 readout_plane_state(crtc);
16529 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16530 crtc->base.base.id, crtc->base.name,
16531 crtc->active ? "enabled" : "disabled");
16534 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16535 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16537 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16538 &pll->config.hw_state);
16539 pll->config.crtc_mask = 0;
16540 for_each_intel_crtc(dev, crtc) {
16541 if (crtc->active && crtc->config->shared_dpll == pll)
16542 pll->config.crtc_mask |= 1 << crtc->pipe;
16544 pll->active_mask = pll->config.crtc_mask;
16546 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16547 pll->name, pll->config.crtc_mask, pll->on);
16550 for_each_intel_encoder(dev, encoder) {
16553 if (encoder->get_hw_state(encoder, &pipe)) {
16554 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16555 encoder->base.crtc = &crtc->base;
16556 crtc->config->output_types |= 1 << encoder->type;
16557 encoder->get_config(encoder, crtc->config);
16559 encoder->base.crtc = NULL;
16562 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16563 encoder->base.base.id,
16564 encoder->base.name,
16565 encoder->base.crtc ? "enabled" : "disabled",
16569 for_each_intel_connector(dev, connector) {
16570 if (connector->get_hw_state(connector)) {
16571 connector->base.dpms = DRM_MODE_DPMS_ON;
16573 encoder = connector->encoder;
16574 connector->base.encoder = &encoder->base;
16576 if (encoder->base.crtc &&
16577 encoder->base.crtc->state->active) {
16579 * This has to be done during hardware readout
16580 * because anything calling .crtc_disable may
16581 * rely on the connector_mask being accurate.
16583 encoder->base.crtc->state->connector_mask |=
16584 1 << drm_connector_index(&connector->base);
16585 encoder->base.crtc->state->encoder_mask |=
16586 1 << drm_encoder_index(&encoder->base);
16590 connector->base.dpms = DRM_MODE_DPMS_OFF;
16591 connector->base.encoder = NULL;
16593 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16594 connector->base.base.id,
16595 connector->base.name,
16596 connector->base.encoder ? "enabled" : "disabled");
16599 for_each_intel_crtc(dev, crtc) {
16600 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16602 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16603 if (crtc->base.state->active) {
16604 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16605 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16606 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16609 * The initial mode needs to be set in order to keep
16610 * the atomic core happy. It wants a valid mode if the
16611 * crtc's enabled, so we do the above call.
16613 * At this point some state updated by the connectors
16614 * in their ->detect() callback has not run yet, so
16615 * no recalculation can be done yet.
16617 * Even if we could do a recalculation and modeset
16618 * right now it would cause a double modeset if
16619 * fbdev or userspace chooses a different initial mode.
16621 * If that happens, someone indicated they wanted a
16622 * mode change, which means it's safe to do a full
16625 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16627 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16628 update_scanline_offset(crtc);
16631 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16635 /* Scan out the current hw modeset state,
16636 * and sanitizes it to the current state
16639 intel_modeset_setup_hw_state(struct drm_device *dev)
16641 struct drm_i915_private *dev_priv = to_i915(dev);
16643 struct intel_crtc *crtc;
16644 struct intel_encoder *encoder;
16647 intel_modeset_readout_hw_state(dev);
16649 /* HW state is read out, now we need to sanitize this mess. */
16650 for_each_intel_encoder(dev, encoder) {
16651 intel_sanitize_encoder(encoder);
16654 for_each_pipe(dev_priv, pipe) {
16655 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16656 intel_sanitize_crtc(crtc);
16657 intel_dump_pipe_config(crtc, crtc->config,
16658 "[setup_hw_state]");
16661 intel_modeset_update_connector_atomic_state(dev);
16663 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16664 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16666 if (!pll->on || pll->active_mask)
16669 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16671 pll->funcs.disable(dev_priv, pll);
16675 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16676 vlv_wm_get_hw_state(dev);
16677 else if (IS_GEN9(dev))
16678 skl_wm_get_hw_state(dev);
16679 else if (HAS_PCH_SPLIT(dev))
16680 ilk_wm_get_hw_state(dev);
16682 for_each_intel_crtc(dev, crtc) {
16683 unsigned long put_domains;
16685 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16686 if (WARN_ON(put_domains))
16687 modeset_put_power_domains(dev_priv, put_domains);
16689 intel_display_set_init_power(dev_priv, false);
16691 intel_fbc_init_pipe_state(dev_priv);
16694 void intel_display_resume(struct drm_device *dev)
16696 struct drm_i915_private *dev_priv = to_i915(dev);
16697 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16698 struct drm_modeset_acquire_ctx ctx;
16701 dev_priv->modeset_restore_state = NULL;
16703 state->acquire_ctx = &ctx;
16706 * This is a cludge because with real atomic modeset mode_config.mutex
16707 * won't be taken. Unfortunately some probed state like
16708 * audio_codec_enable is still protected by mode_config.mutex, so lock
16711 mutex_lock(&dev->mode_config.mutex);
16712 drm_modeset_acquire_init(&ctx, 0);
16715 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16716 if (ret != -EDEADLK)
16719 drm_modeset_backoff(&ctx);
16723 ret = __intel_display_resume(dev, state);
16725 drm_modeset_drop_locks(&ctx);
16726 drm_modeset_acquire_fini(&ctx);
16727 mutex_unlock(&dev->mode_config.mutex);
16730 DRM_ERROR("Restoring old state failed with %i\n", ret);
16731 drm_atomic_state_free(state);
16735 void intel_modeset_gem_init(struct drm_device *dev)
16737 struct drm_i915_private *dev_priv = to_i915(dev);
16738 struct drm_crtc *c;
16739 struct drm_i915_gem_object *obj;
16742 intel_init_gt_powersave(dev_priv);
16744 intel_modeset_init_hw(dev);
16746 intel_setup_overlay(dev_priv);
16749 * Make sure any fbs we allocated at startup are properly
16750 * pinned & fenced. When we do the allocation it's too early
16753 for_each_crtc(dev, c) {
16754 obj = intel_fb_obj(c->primary->fb);
16758 mutex_lock(&dev->struct_mutex);
16759 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16760 c->primary->state->rotation);
16761 mutex_unlock(&dev->struct_mutex);
16763 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16764 to_intel_crtc(c)->pipe);
16765 drm_framebuffer_unreference(c->primary->fb);
16766 c->primary->fb = NULL;
16767 c->primary->crtc = c->primary->state->crtc = NULL;
16768 update_state_fb(c->primary);
16769 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16774 int intel_connector_register(struct drm_connector *connector)
16776 struct intel_connector *intel_connector = to_intel_connector(connector);
16779 ret = intel_backlight_device_register(intel_connector);
16789 void intel_connector_unregister(struct drm_connector *connector)
16791 struct intel_connector *intel_connector = to_intel_connector(connector);
16793 intel_backlight_device_unregister(intel_connector);
16794 intel_panel_destroy_backlight(connector);
16797 void intel_modeset_cleanup(struct drm_device *dev)
16799 struct drm_i915_private *dev_priv = to_i915(dev);
16801 intel_disable_gt_powersave(dev_priv);
16804 * Interrupts and polling as the first thing to avoid creating havoc.
16805 * Too much stuff here (turning of connectors, ...) would
16806 * experience fancy races otherwise.
16808 intel_irq_uninstall(dev_priv);
16811 * Due to the hpd irq storm handling the hotplug work can re-arm the
16812 * poll handlers. Hence disable polling after hpd handling is shut down.
16814 drm_kms_helper_poll_fini(dev);
16816 intel_unregister_dsm_handler();
16818 intel_fbc_global_disable(dev_priv);
16820 /* flush any delayed tasks or pending work */
16821 flush_scheduled_work();
16823 drm_mode_config_cleanup(dev);
16825 intel_cleanup_overlay(dev_priv);
16827 intel_cleanup_gt_powersave(dev_priv);
16829 intel_teardown_gmbus(dev);
16832 void intel_connector_attach_encoder(struct intel_connector *connector,
16833 struct intel_encoder *encoder)
16835 connector->encoder = encoder;
16836 drm_mode_connector_attach_encoder(&connector->base,
16841 * set vga decode state - true == enable VGA decode
16843 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16845 struct drm_i915_private *dev_priv = to_i915(dev);
16846 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16849 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16850 DRM_ERROR("failed to read control word\n");
16854 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16858 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16860 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16862 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16863 DRM_ERROR("failed to write control word\n");
16870 struct intel_display_error_state {
16872 u32 power_well_driver;
16874 int num_transcoders;
16876 struct intel_cursor_error_state {
16881 } cursor[I915_MAX_PIPES];
16883 struct intel_pipe_error_state {
16884 bool power_domain_on;
16887 } pipe[I915_MAX_PIPES];
16889 struct intel_plane_error_state {
16897 } plane[I915_MAX_PIPES];
16899 struct intel_transcoder_error_state {
16900 bool power_domain_on;
16901 enum transcoder cpu_transcoder;
16914 struct intel_display_error_state *
16915 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16917 struct intel_display_error_state *error;
16918 int transcoders[] = {
16926 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16929 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16933 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16934 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16936 for_each_pipe(dev_priv, i) {
16937 error->pipe[i].power_domain_on =
16938 __intel_display_power_is_enabled(dev_priv,
16939 POWER_DOMAIN_PIPE(i));
16940 if (!error->pipe[i].power_domain_on)
16943 error->cursor[i].control = I915_READ(CURCNTR(i));
16944 error->cursor[i].position = I915_READ(CURPOS(i));
16945 error->cursor[i].base = I915_READ(CURBASE(i));
16947 error->plane[i].control = I915_READ(DSPCNTR(i));
16948 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16949 if (INTEL_GEN(dev_priv) <= 3) {
16950 error->plane[i].size = I915_READ(DSPSIZE(i));
16951 error->plane[i].pos = I915_READ(DSPPOS(i));
16953 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16954 error->plane[i].addr = I915_READ(DSPADDR(i));
16955 if (INTEL_GEN(dev_priv) >= 4) {
16956 error->plane[i].surface = I915_READ(DSPSURF(i));
16957 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16960 error->pipe[i].source = I915_READ(PIPESRC(i));
16962 if (HAS_GMCH_DISPLAY(dev_priv))
16963 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16966 /* Note: this does not include DSI transcoders. */
16967 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16968 if (HAS_DDI(dev_priv))
16969 error->num_transcoders++; /* Account for eDP. */
16971 for (i = 0; i < error->num_transcoders; i++) {
16972 enum transcoder cpu_transcoder = transcoders[i];
16974 error->transcoder[i].power_domain_on =
16975 __intel_display_power_is_enabled(dev_priv,
16976 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16977 if (!error->transcoder[i].power_domain_on)
16980 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16982 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16983 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16984 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16985 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16986 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16987 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16988 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16994 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16997 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16998 struct drm_device *dev,
16999 struct intel_display_error_state *error)
17001 struct drm_i915_private *dev_priv = to_i915(dev);
17007 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17008 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17009 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17010 error->power_well_driver);
17011 for_each_pipe(dev_priv, i) {
17012 err_printf(m, "Pipe [%d]:\n", i);
17013 err_printf(m, " Power: %s\n",
17014 onoff(error->pipe[i].power_domain_on));
17015 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17016 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17018 err_printf(m, "Plane [%d]:\n", i);
17019 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17020 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17021 if (INTEL_INFO(dev)->gen <= 3) {
17022 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17023 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17025 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17026 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17027 if (INTEL_INFO(dev)->gen >= 4) {
17028 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17029 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17032 err_printf(m, "Cursor [%d]:\n", i);
17033 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17034 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17035 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17038 for (i = 0; i < error->num_transcoders; i++) {
17039 err_printf(m, "CPU transcoder: %s\n",
17040 transcoder_name(error->transcoder[i].cpu_transcoder));
17041 err_printf(m, " Power: %s\n",
17042 onoff(error->transcoder[i].power_domain_on));
17043 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17044 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17045 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17046 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17047 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17048 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17049 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);