drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62         /**
  63          * find_pll() - Find the best values for the PLL
  64          * @limit: limits for the PLL
  65          * @crtc: current CRTC
  66          * @target: target frequency in kHz
  67          * @refclk: reference clock frequency in kHz
  68          * @match_clock: if provided, @best_clock P divider must
  69          *               match the P divider from @match_clock
  70          *               used for LVDS downclocking
  71          * @best_clock: best PLL values found
  72          *
  73          * Returns true on success, false on failure.
  74          */
  75         bool (*find_pll)(const intel_limit_t *limit,
  76                          struct drm_crtc *crtc,
  77                          int target, int refclk,
  78                          intel_clock_t *match_clock,
  79                          intel_clock_t *best_clock);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 int
  86 intel_pch_rawclk(struct drm_device *dev)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89
  90         WARN_ON(!HAS_PCH_SPLIT(dev));
  91
  92         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  93 }
  94
  95 static bool
  96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                     int target, int refclk, intel_clock_t *match_clock,
  98                     intel_clock_t *best_clock);
  99 static bool
 100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 101                         int target, int refclk, intel_clock_t *match_clock,
 102                         intel_clock_t *best_clock);
 103
 104 static bool
 105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 106                         int target, int refclk, intel_clock_t *match_clock,
 107                         intel_clock_t *best_clock);
 108
 109 static inline u32 /* units of 100MHz */
 110 intel_fdi_link_freq(struct drm_device *dev)
 111 {
 112         if (IS_GEN5(dev)) {
 113                 struct drm_i915_private *dev_priv = dev->dev_private;
 114                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 115         } else
 116                 return 27;
 117 }
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 930000, .max = 1400000 },
 122         .n = { .min = 3, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 2 },
 130         .find_pll = intel_find_best_PLL,
 131 };
 132
 133 static const intel_limit_t intel_limits_i8xx_lvds = {
 134         .dot = { .min = 25000, .max = 350000 },
 135         .vco = { .min = 930000, .max = 1400000 },
 136         .n = { .min = 3, .max = 16 },
 137         .m = { .min = 96, .max = 140 },
 138         .m1 = { .min = 18, .max = 26 },
 139         .m2 = { .min = 6, .max = 16 },
 140         .p = { .min = 4, .max = 128 },
 141         .p1 = { .min = 1, .max = 6 },
 142         .p2 = { .dot_limit = 165000,
 143                 .p2_slow = 14, .p2_fast = 7 },
 144         .find_pll = intel_find_best_PLL,
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_sdvo = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 5, .max = 80 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 200000,
 157                 .p2_slow = 10, .p2_fast = 5 },
 158         .find_pll = intel_find_best_PLL,
 159 };
 160
 161 static const intel_limit_t intel_limits_i9xx_lvds = {
 162         .dot = { .min = 20000, .max = 400000 },
 163         .vco = { .min = 1400000, .max = 2800000 },
 164         .n = { .min = 1, .max = 6 },
 165         .m = { .min = 70, .max = 120 },
 166         .m1 = { .min = 8, .max = 18 },
 167         .m2 = { .min = 3, .max = 7 },
 168         .p = { .min = 7, .max = 98 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 112000,
 171                 .p2_slow = 14, .p2_fast = 7 },
 172         .find_pll = intel_find_best_PLL,
 173 };
 174
 175
 176 static const intel_limit_t intel_limits_g4x_sdvo = {
 177         .dot = { .min = 25000, .max = 270000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 17, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 10, .max = 30 },
 184         .p1 = { .min = 1, .max = 3},
 185         .p2 = { .dot_limit = 270000,
 186                 .p2_slow = 10,
 187                 .p2_fast = 10
 188         },
 189         .find_pll = intel_g4x_find_best_PLL,
 190 };
 191
 192 static const intel_limit_t intel_limits_g4x_hdmi = {
 193         .dot = { .min = 22000, .max = 400000 },
 194         .vco = { .min = 1750000, .max = 3500000},
 195         .n = { .min = 1, .max = 4 },
 196         .m = { .min = 104, .max = 138 },
 197         .m1 = { .min = 16, .max = 23 },
 198         .m2 = { .min = 5, .max = 11 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8},
 201         .p2 = { .dot_limit = 165000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203         .find_pll = intel_g4x_find_best_PLL,
 204 };
 205
 206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 207         .dot = { .min = 20000, .max = 115000 },
 208         .vco = { .min = 1750000, .max = 3500000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 104, .max = 138 },
 211         .m1 = { .min = 17, .max = 23 },
 212         .m2 = { .min = 5, .max = 11 },
 213         .p = { .min = 28, .max = 112 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 0,
 216                 .p2_slow = 14, .p2_fast = 14
 217         },
 218         .find_pll = intel_g4x_find_best_PLL,
 219 };
 220
 221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 222         .dot = { .min = 80000, .max = 224000 },
 223         .vco = { .min = 1750000, .max = 3500000 },
 224         .n = { .min = 1, .max = 3 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 14, .max = 42 },
 229         .p1 = { .min = 2, .max = 6 },
 230         .p2 = { .dot_limit = 0,
 231                 .p2_slow = 7, .p2_fast = 7
 232         },
 233         .find_pll = intel_g4x_find_best_PLL,
 234 };
 235
 236 static const intel_limit_t intel_limits_pineview_sdvo = {
 237         .dot = { .min = 20000, .max = 400000},
 238         .vco = { .min = 1700000, .max = 3500000 },
 239         /* Pineview's Ncounter is a ring counter */
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         /* Pineview only has one combined m divider, which we treat as m2. */
 243         .m1 = { .min = 0, .max = 0 },
 244         .m2 = { .min = 0, .max = 254 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8 },
 247         .p2 = { .dot_limit = 200000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249         .find_pll = intel_find_best_PLL,
 250 };
 251
 252 static const intel_limit_t intel_limits_pineview_lvds = {
 253         .dot = { .min = 20000, .max = 400000 },
 254         .vco = { .min = 1700000, .max = 3500000 },
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         .m1 = { .min = 0, .max = 0 },
 258         .m2 = { .min = 0, .max = 254 },
 259         .p = { .min = 7, .max = 112 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 112000,
 262                 .p2_slow = 14, .p2_fast = 14 },
 263         .find_pll = intel_find_best_PLL,
 264 };
 265
 266 /* Ironlake / Sandybridge
 267  *
 268  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 269  * the range value for them is (actual_value - 2).
 270  */
 271 static const intel_limit_t intel_limits_ironlake_dac = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 1760000, .max = 3510000 },
 274         .n = { .min = 1, .max = 5 },
 275         .m = { .min = 79, .max = 127 },
 276         .m1 = { .min = 12, .max = 22 },
 277         .m2 = { .min = 5, .max = 9 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 225000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282         .find_pll = intel_g4x_find_best_PLL,
 283 };
 284
 285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 286         .dot = { .min = 25000, .max = 350000 },
 287         .vco = { .min = 1760000, .max = 3510000 },
 288         .n = { .min = 1, .max = 3 },
 289         .m = { .min = 79, .max = 118 },
 290         .m1 = { .min = 12, .max = 22 },
 291         .m2 = { .min = 5, .max = 9 },
 292         .p = { .min = 28, .max = 112 },
 293         .p1 = { .min = 2, .max = 8 },
 294         .p2 = { .dot_limit = 225000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296         .find_pll = intel_g4x_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 127 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 56 },
 307         .p1 = { .min = 2, .max = 8 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310         .find_pll = intel_g4x_find_best_PLL,
 311 };
 312
 313 /* LVDS 100mhz refclk limits. */
 314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 2 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 28, .max = 112 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 14, .p2_fast = 14 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 126 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 42 },
 336         .p1 = { .min = 2, .max = 6 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339         .find_pll = intel_g4x_find_best_PLL,
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dac = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 }, /* guess */
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353         .find_pll = intel_vlv_find_best_pll,
 354 };
 355
 356 static const intel_limit_t intel_limits_vlv_hdmi = {
 357         .dot = { .min = 25000, .max = 270000 },
 358         .vco = { .min = 4000000, .max = 6000000 },
 359         .n = { .min = 1, .max = 7 },
 360         .m = { .min = 60, .max = 300 }, /* guess */
 361         .m1 = { .min = 2, .max = 3 },
 362         .m2 = { .min = 11, .max = 156 },
 363         .p = { .min = 10, .max = 30 },
 364         .p1 = { .min = 2, .max = 3 },
 365         .p2 = { .dot_limit = 270000,
 366                 .p2_slow = 2, .p2_fast = 20 },
 367         .find_pll = intel_vlv_find_best_pll,
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv_dp = {
 371         .dot = { .min = 25000, .max = 270000 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m = { .min = 22, .max = 450 },
 375         .m1 = { .min = 2, .max = 3 },
 376         .m2 = { .min = 11, .max = 156 },
 377         .p = { .min = 10, .max = 30 },
 378         .p1 = { .min = 1, .max = 3 },
 379         .p2 = { .dot_limit = 270000,
 380                 .p2_slow = 2, .p2_fast = 20 },
 381         .find_pll = intel_vlv_find_best_pll,
 382 };
 383
 384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 385 {
 386         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 387
 388         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 389                 DRM_ERROR("DPIO idle wait timed out\n");
 390                 return 0;
 391         }
 392
 393         I915_WRITE(DPIO_REG, reg);
 394         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 395                    DPIO_BYTE);
 396         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 397                 DRM_ERROR("DPIO read wait timed out\n");
 398                 return 0;
 399         }
 400
 401         return I915_READ(DPIO_DATA);
 402 }
 403
 404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 405 {
 406         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 407
 408         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 409                 DRM_ERROR("DPIO idle wait timed out\n");
 410                 return;
 411         }
 412
 413         I915_WRITE(DPIO_DATA, val);
 414         I915_WRITE(DPIO_REG, reg);
 415         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 416                    DPIO_BYTE);
 417         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 418                 DRM_ERROR("DPIO write wait timed out\n");
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_VALLEYVIEW(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 482                         limit = &intel_limits_vlv_dac;
 483                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 484                         limit = &intel_limits_vlv_hdmi;
 485                 else
 486                         limit = &intel_limits_vlv_dp;
 487         } else if (!IS_GEN2(dev)) {
 488                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 489                         limit = &intel_limits_i9xx_lvds;
 490                 else
 491                         limit = &intel_limits_i9xx_sdvo;
 492         } else {
 493                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 494                         limit = &intel_limits_i8xx_lvds;
 495                 else
 496                         limit = &intel_limits_i8xx_dvo;
 497         }
 498         return limit;
 499 }
 500
 501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 502 static void pineview_clock(int refclk, intel_clock_t *clock)
 503 {
 504         clock->m = clock->m2 + 2;
 505         clock->p = clock->p1 * clock->p2;
 506         clock->vco = refclk * clock->m / clock->n;
 507         clock->dot = clock->vco / clock->p;
 508 }
 509
 510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 511 {
 512         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 513 }
 514
 515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 516 {
 517         if (IS_PINEVIEW(dev)) {
 518                 pineview_clock(refclk, clock);
 519                 return;
 520         }
 521         clock->m = i9xx_dpll_compute_m(clock);
 522         clock->p = clock->p1 * clock->p2;
 523         clock->vco = refclk * clock->m / (clock->n + 2);
 524         clock->dot = clock->vco / clock->p;
 525 }
 526
 527 /**
 528  * Returns whether any output on the specified pipe is of the specified type
 529  */
 530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 531 {
 532         struct drm_device *dev = crtc->dev;
 533         struct intel_encoder *encoder;
 534
 535         for_each_encoder_on_crtc(dev, crtc, encoder)
 536                 if (encoder->type == type)
 537                         return true;
 538
 539         return false;
 540 }
 541
 542 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 543 /**
 544  * Returns whether the given set of divisors are valid for a given refclk with
 545  * the given connectors.
 546  */
 547
 548 static bool intel_PLL_is_valid(struct drm_device *dev,
 549                                const intel_limit_t *limit,
 550                                const intel_clock_t *clock)
 551 {
 552         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 553                 INTELPllInvalid("p1 out of range\n");
 554         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 555                 INTELPllInvalid("p out of range\n");
 556         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 557                 INTELPllInvalid("m2 out of range\n");
 558         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 559                 INTELPllInvalid("m1 out of range\n");
 560         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 561                 INTELPllInvalid("m1 <= m2\n");
 562         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 563                 INTELPllInvalid("m out of range\n");
 564         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 565                 INTELPllInvalid("n out of range\n");
 566         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 567                 INTELPllInvalid("vco out of range\n");
 568         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 569          * connector, etc., rather than just a single range.
 570          */
 571         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 572                 INTELPllInvalid("dot out of range\n");
 573
 574         return true;
 575 }
 576
 577 static bool
 578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                     int target, int refclk, intel_clock_t *match_clock,
 580                     intel_clock_t *best_clock)
 581
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         /* m1 is always 0 in Pineview */
 611                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 612                                 break;
 613                         for (clock.n = limit->n.min;
 614                              clock.n <= limit->n.max; clock.n++) {
 615                                 for (clock.p1 = limit->p1.min;
 616                                         clock.p1 <= limit->p1.max; clock.p1++) {
 617                                         int this_err;
 618
 619                                         intel_clock(dev, refclk, &clock);
 620                                         if (!intel_PLL_is_valid(dev, limit,
 621                                                                 &clock))
 622                                                 continue;
 623                                         if (match_clock &&
 624                                             clock.p != match_clock->p)
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err) {
 629                                                 *best_clock = clock;
 630                                                 err = this_err;
 631                                         }
 632                                 }
 633                         }
 634                 }
 635         }
 636
 637         return (err != target);
 638 }
 639
 640 static bool
 641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 642                         int target, int refclk, intel_clock_t *match_clock,
 643                         intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647         int max_n;
 648         bool found;
 649         /* approximately equals target * 0.00585 */
 650         int err_most = (target >> 8) + (target >> 9);
 651         found = false;
 652
 653         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666         max_n = limit->n.max;
 667         /* based on hardware requirement, prefer smaller n to precision */
 668         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 669                 /* based on hardware requirement, prefere larger m1,m2 */
 670                 for (clock.m1 = limit->m1.max;
 671                      clock.m1 >= limit->m1.min; clock.m1--) {
 672                         for (clock.m2 = limit->m2.max;
 673                              clock.m2 >= limit->m2.min; clock.m2--) {
 674                                 for (clock.p1 = limit->p1.max;
 675                                      clock.p1 >= limit->p1.min; clock.p1--) {
 676                                         int this_err;
 677
 678                                         intel_clock(dev, refclk, &clock);
 679                                         if (!intel_PLL_is_valid(dev, limit,
 680                                                                 &clock))
 681                                                 continue;
 682
 683                                         this_err = abs(clock.dot - target);
 684                                         if (this_err < err_most) {
 685                                                 *best_clock = clock;
 686                                                 err_most = this_err;
 687                                                 max_n = clock.n;
 688                                                 found = true;
 689                                         }
 690                                 }
 691                         }
 692                 }
 693         }
 694         return found;
 695 }
 696
 697 static bool
 698 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 699                         int target, int refclk, intel_clock_t *match_clock,
 700                         intel_clock_t *best_clock)
 701 {
 702         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 703         u32 m, n, fastclk;
 704         u32 updrate, minupdate, fracbits, p;
 705         unsigned long bestppm, ppm, absppm;
 706         int dotclk, flag;
 707
 708         flag = 0;
 709         dotclk = target * 1000;
 710         bestppm = 1000000;
 711         ppm = absppm = 0;
 712         fastclk = dotclk / (2*100);
 713         updrate = 0;
 714         minupdate = 19200;
 715         fracbits = 1;
 716         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 717         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 718
 719         /* based on hardware requirement, prefer smaller n to precision */
 720         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 721                 updrate = refclk / n;
 722                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 723                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 724                                 if (p2 > 10)
 725                                         p2 = p2 - 1;
 726                                 p = p1 * p2;
 727                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 728                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 729                                         m2 = (((2*(fastclk * p * n / m1 )) +
 730                                                refclk) / (2*refclk));
 731                                         m = m1 * m2;
 732                                         vco = updrate * m;
 733                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 734                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 735                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 736                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 737                                                         bestppm = 0;
 738                                                         flag = 1;
 739                                                 }
 740                                                 if (absppm < bestppm - 10) {
 741                                                         bestppm = absppm;
 742                                                         flag = 1;
 743                                                 }
 744                                                 if (flag) {
 745                                                         bestn = n;
 746                                                         bestm1 = m1;
 747                                                         bestm2 = m2;
 748                                                         bestp1 = p1;
 749                                                         bestp2 = p2;
 750                                                         flag = 0;
 751                                                 }
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757         best_clock->n = bestn;
 758         best_clock->m1 = bestm1;
 759         best_clock->m2 = bestm2;
 760         best_clock->p1 = bestp1;
 761         best_clock->p2 = bestp2;
 762
 763         return true;
 764 }
 765
 766 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 767                                              enum pipe pipe)
 768 {
 769         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 771
 772         return intel_crtc->config.cpu_transcoder;
 773 }
 774
 775 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 776 {
 777         struct drm_i915_private *dev_priv = dev->dev_private;
 778         u32 frame, frame_reg = PIPEFRAME(pipe);
 779
 780         frame = I915_READ(frame_reg);
 781
 782         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 783                 DRM_DEBUG_KMS("vblank wait timed out\n");
 784 }
 785
 786 /**
 787  * intel_wait_for_vblank - wait for vblank on a given pipe
 788  * @dev: drm device
 789  * @pipe: pipe to wait for
 790  *
 791  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 792  * mode setting code.
 793  */
 794 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 795 {
 796         struct drm_i915_private *dev_priv = dev->dev_private;
 797         int pipestat_reg = PIPESTAT(pipe);
 798
 799         if (INTEL_INFO(dev)->gen >= 5) {
 800                 ironlake_wait_for_vblank(dev, pipe);
 801                 return;
 802         }
 803
 804         /* Clear existing vblank status. Note this will clear any other
 805          * sticky status fields as well.
 806          *
 807          * This races with i915_driver_irq_handler() with the result
 808          * that either function could miss a vblank event.  Here it is not
 809          * fatal, as we will either wait upon the next vblank interrupt or
 810          * timeout.  Generally speaking intel_wait_for_vblank() is only
 811          * called during modeset at which time the GPU should be idle and
 812          * should *not* be performing page flips and thus not waiting on
 813          * vblanks...
 814          * Currently, the result of us stealing a vblank from the irq
 815          * handler is that a single frame will be skipped during swapbuffers.
 816          */
 817         I915_WRITE(pipestat_reg,
 818                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 819
 820         /* Wait for vblank interrupt bit to set */
 821         if (wait_for(I915_READ(pipestat_reg) &
 822                      PIPE_VBLANK_INTERRUPT_STATUS,
 823                      50))
 824                 DRM_DEBUG_KMS("vblank wait timed out\n");
 825 }
 826
 827 /*
 828  * intel_wait_for_pipe_off - wait for pipe to turn off
 829  * @dev: drm device
 830  * @pipe: pipe to wait for
 831  *
 832  * After disabling a pipe, we can't wait for vblank in the usual way,
 833  * spinning on the vblank interrupt status bit, since we won't actually
 834  * see an interrupt when the pipe is disabled.
 835  *
 836  * On Gen4 and above:
 837  *   wait for the pipe register state bit to turn off
 838  *
 839  * Otherwise:
 840  *   wait for the display line value to settle (it usually
 841  *   ends up stopping at the start of the next frame).
 842  *
 843  */
 844 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 848                                                                       pipe);
 849
 850         if (INTEL_INFO(dev)->gen >= 4) {
 851                 int reg = PIPECONF(cpu_transcoder);
 852
 853                 /* Wait for the Pipe State to go off */
 854                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 855                              100))
 856                         WARN(1, "pipe_off wait timed out\n");
 857         } else {
 858                 u32 last_line, line_mask;
 859                 int reg = PIPEDSL(pipe);
 860                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 861
 862                 if (IS_GEN2(dev))
 863                         line_mask = DSL_LINEMASK_GEN2;
 864                 else
 865                         line_mask = DSL_LINEMASK_GEN3;
 866
 867                 /* Wait for the display line to settle */
 868                 do {
 869                         last_line = I915_READ(reg) & line_mask;
 870                         mdelay(5);
 871                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 872                          time_after(timeout, jiffies));
 873                 if (time_after(jiffies, timeout))
 874                         WARN(1, "pipe_off wait timed out\n");
 875         }
 876 }
 877
 878 /*
 879  * ibx_digital_port_connected - is the specified port connected?
 880  * @dev_priv: i915 private structure
 881  * @port: the port to test
 882  *
 883  * Returns true if @port is connected, false otherwise.
 884  */
 885 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 886                                 struct intel_digital_port *port)
 887 {
 888         u32 bit;
 889
 890         if (HAS_PCH_IBX(dev_priv->dev)) {
 891                 switch(port->port) {
 892                 case PORT_B:
 893                         bit = SDE_PORTB_HOTPLUG;
 894                         break;
 895                 case PORT_C:
 896                         bit = SDE_PORTC_HOTPLUG;
 897                         break;
 898                 case PORT_D:
 899                         bit = SDE_PORTD_HOTPLUG;
 900                         break;
 901                 default:
 902                         return true;
 903                 }
 904         } else {
 905                 switch(port->port) {
 906                 case PORT_B:
 907                         bit = SDE_PORTB_HOTPLUG_CPT;
 908                         break;
 909                 case PORT_C:
 910                         bit = SDE_PORTC_HOTPLUG_CPT;
 911                         break;
 912                 case PORT_D:
 913                         bit = SDE_PORTD_HOTPLUG_CPT;
 914                         break;
 915                 default:
 916                         return true;
 917                 }
 918         }
 919
 920         return I915_READ(SDEISR) & bit;
 921 }
 922
 923 static const char *state_string(bool enabled)
 924 {
 925         return enabled ? "on" : "off";
 926 }
 927
 928 /* Only for pre-ILK configs */
 929 static void assert_pll(struct drm_i915_private *dev_priv,
 930                        enum pipe pipe, bool state)
 931 {
 932         int reg;
 933         u32 val;
 934         bool cur_state;
 935
 936         reg = DPLL(pipe);
 937         val = I915_READ(reg);
 938         cur_state = !!(val & DPLL_VCO_ENABLE);
 939         WARN(cur_state != state,
 940              "PLL state assertion failure (expected %s, current %s)\n",
 941              state_string(state), state_string(cur_state));
 942 }
 943 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 944 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 945
 946 /* For ILK+ */
 947 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 948                            struct intel_pch_pll *pll,
 949                            struct intel_crtc *crtc,
 950                            bool state)
 951 {
 952         u32 val;
 953         bool cur_state;
 954
 955         if (HAS_PCH_LPT(dev_priv->dev)) {
 956                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 957                 return;
 958         }
 959
 960         if (WARN (!pll,
 961                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 962                 return;
 963
 964         val = I915_READ(pll->pll_reg);
 965         cur_state = !!(val & DPLL_VCO_ENABLE);
 966         WARN(cur_state != state,
 967              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 968              pll->pll_reg, state_string(state), state_string(cur_state), val);
 969
 970         /* Make sure the selected PLL is correctly attached to the transcoder */
 971         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 972                 u32 pch_dpll;
 973
 974                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 975                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 976                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 977                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 978                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 979                         cur_state = !!(val >> (4*crtc->pipe + 3));
 980                         WARN(cur_state != state,
 981                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 982                              pll->pll_reg == _PCH_DPLL_B,
 983                              state_string(state),
 984                              pipe_name(crtc->pipe),
 985                              val);
 986                 }
 987         }
 988 }
 989 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 990 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 991
 992 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 993                           enum pipe pipe, bool state)
 994 {
 995         int reg;
 996         u32 val;
 997         bool cur_state;
 998         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 999                                                                       pipe);
1000
1001         if (HAS_DDI(dev_priv->dev)) {
1002                 /* DDI does not have a specific FDI_TX register */
1003                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1004                 val = I915_READ(reg);
1005                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1006         } else {
1007                 reg = FDI_TX_CTL(pipe);
1008                 val = I915_READ(reg);
1009                 cur_state = !!(val & FDI_TX_ENABLE);
1010         }
1011         WARN(cur_state != state,
1012              "FDI TX state assertion failure (expected %s, current %s)\n",
1013              state_string(state), state_string(cur_state));
1014 }
1015 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1016 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1017
1018 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1019                           enum pipe pipe, bool state)
1020 {
1021         int reg;
1022         u32 val;
1023         bool cur_state;
1024
1025         reg = FDI_RX_CTL(pipe);
1026         val = I915_READ(reg);
1027         cur_state = !!(val & FDI_RX_ENABLE);
1028         WARN(cur_state != state,
1029              "FDI RX state assertion failure (expected %s, current %s)\n",
1030              state_string(state), state_string(cur_state));
1031 }
1032 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1033 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1034
1035 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1036                                       enum pipe pipe)
1037 {
1038         int reg;
1039         u32 val;
1040
1041         /* ILK FDI PLL is always enabled */
1042         if (dev_priv->info->gen == 5)
1043                 return;
1044
1045         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1046         if (HAS_DDI(dev_priv->dev))
1047                 return;
1048
1049         reg = FDI_TX_CTL(pipe);
1050         val = I915_READ(reg);
1051         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1052 }
1053
1054 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1055                                       enum pipe pipe)
1056 {
1057         int reg;
1058         u32 val;
1059
1060         reg = FDI_RX_CTL(pipe);
1061         val = I915_READ(reg);
1062         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1063 }
1064
1065 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1066                                   enum pipe pipe)
1067 {
1068         int pp_reg, lvds_reg;
1069         u32 val;
1070         enum pipe panel_pipe = PIPE_A;
1071         bool locked = true;
1072
1073         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1074                 pp_reg = PCH_PP_CONTROL;
1075                 lvds_reg = PCH_LVDS;
1076         } else {
1077                 pp_reg = PP_CONTROL;
1078                 lvds_reg = LVDS;
1079         }
1080
1081         val = I915_READ(pp_reg);
1082         if (!(val & PANEL_POWER_ON) ||
1083             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1084                 locked = false;
1085
1086         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1087                 panel_pipe = PIPE_B;
1088
1089         WARN(panel_pipe == pipe && locked,
1090              "panel assertion failure, pipe %c regs locked\n",
1091              pipe_name(pipe));
1092 }
1093
1094 void assert_pipe(struct drm_i915_private *dev_priv,
1095                  enum pipe pipe, bool state)
1096 {
1097         int reg;
1098         u32 val;
1099         bool cur_state;
1100         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1101                                                                       pipe);
1102
1103         /* if we need the pipe A quirk it must be always on */
1104         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1105                 state = true;
1106
1107         if (!intel_display_power_enabled(dev_priv->dev,
1108                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1109                 cur_state = false;
1110         } else {
1111                 reg = PIPECONF(cpu_transcoder);
1112                 val = I915_READ(reg);
1113                 cur_state = !!(val & PIPECONF_ENABLE);
1114         }
1115
1116         WARN(cur_state != state,
1117              "pipe %c assertion failure (expected %s, current %s)\n",
1118              pipe_name(pipe), state_string(state), state_string(cur_state));
1119 }
1120
1121 static void assert_plane(struct drm_i915_private *dev_priv,
1122                          enum plane plane, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127
1128         reg = DSPCNTR(plane);
1129         val = I915_READ(reg);
1130         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1131         WARN(cur_state != state,
1132              "plane %c assertion failure (expected %s, current %s)\n",
1133              plane_name(plane), state_string(state), state_string(cur_state));
1134 }
1135
1136 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1137 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1138
1139 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1140                                    enum pipe pipe)
1141 {
1142         int reg, i;
1143         u32 val;
1144         int cur_pipe;
1145
1146         /* Planes are fixed to pipes on ILK+ */
1147         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1148                 reg = DSPCNTR(pipe);
1149                 val = I915_READ(reg);
1150                 WARN((val & DISPLAY_PLANE_ENABLE),
1151                      "plane %c assertion failure, should be disabled but not\n",
1152                      plane_name(pipe));
1153                 return;
1154         }
1155
1156         /* Need to check both planes against the pipe */
1157         for (i = 0; i < 2; i++) {
1158                 reg = DSPCNTR(i);
1159                 val = I915_READ(reg);
1160                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1161                         DISPPLANE_SEL_PIPE_SHIFT;
1162                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1163                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1164                      plane_name(i), pipe_name(pipe));
1165         }
1166 }
1167
1168 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1169                                     enum pipe pipe)
1170 {
1171         int reg, i;
1172         u32 val;
1173
1174         if (!IS_VALLEYVIEW(dev_priv->dev))
1175                 return;
1176
1177         /* Need to check both planes against the pipe */
1178         for (i = 0; i < dev_priv->num_plane; i++) {
1179                 reg = SPCNTR(pipe, i);
1180                 val = I915_READ(reg);
1181                 WARN((val & SP_ENABLE),
1182                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1183                      sprite_name(pipe, i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1188 {
1189         u32 val;
1190         bool enabled;
1191
1192         if (HAS_PCH_LPT(dev_priv->dev)) {
1193                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1194                 return;
1195         }
1196
1197         val = I915_READ(PCH_DREF_CONTROL);
1198         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1199                             DREF_SUPERSPREAD_SOURCE_MASK));
1200         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1204                                            enum pipe pipe)
1205 {
1206         int reg;
1207         u32 val;
1208         bool enabled;
1209
1210         reg = PCH_TRANSCONF(pipe);
1211         val = I915_READ(reg);
1212         enabled = !!(val & TRANS_ENABLE);
1213         WARN(enabled,
1214              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1215              pipe_name(pipe));
1216 }
1217
1218 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1219                             enum pipe pipe, u32 port_sel, u32 val)
1220 {
1221         if ((val & DP_PORT_EN) == 0)
1222                 return false;
1223
1224         if (HAS_PCH_CPT(dev_priv->dev)) {
1225                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1226                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1227                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1228                         return false;
1229         } else {
1230                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1231                         return false;
1232         }
1233         return true;
1234 }
1235
1236 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1237                               enum pipe pipe, u32 val)
1238 {
1239         if ((val & SDVO_ENABLE) == 0)
1240                 return false;
1241
1242         if (HAS_PCH_CPT(dev_priv->dev)) {
1243                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1244                         return false;
1245         } else {
1246                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1247                         return false;
1248         }
1249         return true;
1250 }
1251
1252 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1253                               enum pipe pipe, u32 val)
1254 {
1255         if ((val & LVDS_PORT_EN) == 0)
1256                 return false;
1257
1258         if (HAS_PCH_CPT(dev_priv->dev)) {
1259                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1260                         return false;
1261         } else {
1262                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1263                         return false;
1264         }
1265         return true;
1266 }
1267
1268 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1269                               enum pipe pipe, u32 val)
1270 {
1271         if ((val & ADPA_DAC_ENABLE) == 0)
1272                 return false;
1273         if (HAS_PCH_CPT(dev_priv->dev)) {
1274                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1275                         return false;
1276         } else {
1277                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1278                         return false;
1279         }
1280         return true;
1281 }
1282
1283 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1284                                    enum pipe pipe, int reg, u32 port_sel)
1285 {
1286         u32 val = I915_READ(reg);
1287         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1288              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1289              reg, pipe_name(pipe));
1290
1291         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1292              && (val & DP_PIPEB_SELECT),
1293              "IBX PCH dp port still using transcoder B\n");
1294 }
1295
1296 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1297                                      enum pipe pipe, int reg)
1298 {
1299         u32 val = I915_READ(reg);
1300         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1301              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1302              reg, pipe_name(pipe));
1303
1304         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1305              && (val & SDVO_PIPE_B_SELECT),
1306              "IBX PCH hdmi port still using transcoder B\n");
1307 }
1308
1309 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1310                                       enum pipe pipe)
1311 {
1312         int reg;
1313         u32 val;
1314
1315         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1316         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1317         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1318
1319         reg = PCH_ADPA;
1320         val = I915_READ(reg);
1321         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1322              "PCH VGA enabled on transcoder %c, should be disabled\n",
1323              pipe_name(pipe));
1324
1325         reg = PCH_LVDS;
1326         val = I915_READ(reg);
1327         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1328              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1329              pipe_name(pipe));
1330
1331         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1332         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1333         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1334 }
1335
1336 /**
1337  * intel_enable_pll - enable a PLL
1338  * @dev_priv: i915 private structure
1339  * @pipe: pipe PLL to enable
1340  *
1341  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1342  * make sure the PLL reg is writable first though, since the panel write
1343  * protect mechanism may be enabled.
1344  *
1345  * Note!  This is for pre-ILK only.
1346  *
1347  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1348  */
1349 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353
1354         assert_pipe_disabled(dev_priv, pipe);
1355
1356         /* No really, not for ILK+ */
1357         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1358
1359         /* PLL is protected by panel, make sure we can write it */
1360         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1361                 assert_panel_unlocked(dev_priv, pipe);
1362
1363         reg = DPLL(pipe);
1364         val = I915_READ(reg);
1365         val |= DPLL_VCO_ENABLE;
1366
1367         /* We do this three times for luck */
1368         I915_WRITE(reg, val);
1369         POSTING_READ(reg);
1370         udelay(150); /* wait for warmup */
1371         I915_WRITE(reg, val);
1372         POSTING_READ(reg);
1373         udelay(150); /* wait for warmup */
1374         I915_WRITE(reg, val);
1375         POSTING_READ(reg);
1376         udelay(150); /* wait for warmup */
1377 }
1378
1379 /**
1380  * intel_disable_pll - disable a PLL
1381  * @dev_priv: i915 private structure
1382  * @pipe: pipe PLL to disable
1383  *
1384  * Disable the PLL for @pipe, making sure the pipe is off first.
1385  *
1386  * Note!  This is for pre-ILK only.
1387  */
1388 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1389 {
1390         int reg;
1391         u32 val;
1392
1393         /* Don't disable pipe A or pipe A PLLs if needed */
1394         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1395                 return;
1396
1397         /* Make sure the pipe isn't still relying on us */
1398         assert_pipe_disabled(dev_priv, pipe);
1399
1400         reg = DPLL(pipe);
1401         val = I915_READ(reg);
1402         val &= ~DPLL_VCO_ENABLE;
1403         I915_WRITE(reg, val);
1404         POSTING_READ(reg);
1405 }
1406
1407 /* SBI access */
1408 static void
1409 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1410                 enum intel_sbi_destination destination)
1411 {
1412         u32 tmp;
1413
1414         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1415
1416         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1417                                 100)) {
1418                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1419                 return;
1420         }
1421
1422         I915_WRITE(SBI_ADDR, (reg << 16));
1423         I915_WRITE(SBI_DATA, value);
1424
1425         if (destination == SBI_ICLK)
1426                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1427         else
1428                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1429         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1430
1431         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1432                                 100)) {
1433                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1434                 return;
1435         }
1436 }
1437
1438 static u32
1439 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1440                enum intel_sbi_destination destination)
1441 {
1442         u32 value = 0;
1443         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1444
1445         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1446                                 100)) {
1447                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1448                 return 0;
1449         }
1450
1451         I915_WRITE(SBI_ADDR, (reg << 16));
1452
1453         if (destination == SBI_ICLK)
1454                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1455         else
1456                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1457         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1458
1459         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1460                                 100)) {
1461                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1462                 return 0;
1463         }
1464
1465         return I915_READ(SBI_DATA);
1466 }
1467
1468 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1469 {
1470         u32 port_mask;
1471
1472         if (!port)
1473                 port_mask = DPLL_PORTB_READY_MASK;
1474         else
1475                 port_mask = DPLL_PORTC_READY_MASK;
1476
1477         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1478                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479                      'B' + port, I915_READ(DPLL(0)));
1480 }
1481
1482 /**
1483  * ironlake_enable_pch_pll - enable PCH PLL
1484  * @dev_priv: i915 private structure
1485  * @pipe: pipe PLL to enable
1486  *
1487  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488  * drives the transcoder clock.
1489  */
1490 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1491 {
1492         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1493         struct intel_pch_pll *pll;
1494         int reg;
1495         u32 val;
1496
1497         /* PCH PLLs only available on ILK, SNB and IVB */
1498         BUG_ON(dev_priv->info->gen < 5);
1499         pll = intel_crtc->pch_pll;
1500         if (pll == NULL)
1501                 return;
1502
1503         if (WARN_ON(pll->refcount == 0))
1504                 return;
1505
1506         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1507                       pll->pll_reg, pll->active, pll->on,
1508                       intel_crtc->base.base.id);
1509
1510         /* PCH refclock must be enabled first */
1511         assert_pch_refclk_enabled(dev_priv);
1512
1513         if (pll->active++ && pll->on) {
1514                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1515                 return;
1516         }
1517
1518         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1519
1520         reg = pll->pll_reg;
1521         val = I915_READ(reg);
1522         val |= DPLL_VCO_ENABLE;
1523         I915_WRITE(reg, val);
1524         POSTING_READ(reg);
1525         udelay(200);
1526
1527         pll->on = true;
1528 }
1529
1530 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1531 {
1532         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1533         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1534         int reg;
1535         u32 val;
1536
1537         /* PCH only available on ILK+ */
1538         BUG_ON(dev_priv->info->gen < 5);
1539         if (pll == NULL)
1540                return;
1541
1542         if (WARN_ON(pll->refcount == 0))
1543                 return;
1544
1545         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1546                       pll->pll_reg, pll->active, pll->on,
1547                       intel_crtc->base.base.id);
1548
1549         if (WARN_ON(pll->active == 0)) {
1550                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1551                 return;
1552         }
1553
1554         if (--pll->active) {
1555                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1556                 return;
1557         }
1558
1559         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1560
1561         /* Make sure transcoder isn't still depending on us */
1562         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1563
1564         reg = pll->pll_reg;
1565         val = I915_READ(reg);
1566         val &= ~DPLL_VCO_ENABLE;
1567         I915_WRITE(reg, val);
1568         POSTING_READ(reg);
1569         udelay(200);
1570
1571         pll->on = false;
1572 }
1573
1574 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1575                                            enum pipe pipe)
1576 {
1577         struct drm_device *dev = dev_priv->dev;
1578         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1579         uint32_t reg, val, pipeconf_val;
1580
1581         /* PCH only available on ILK+ */
1582         BUG_ON(dev_priv->info->gen < 5);
1583
1584         /* Make sure PCH DPLL is enabled */
1585         assert_pch_pll_enabled(dev_priv,
1586                                to_intel_crtc(crtc)->pch_pll,
1587                                to_intel_crtc(crtc));
1588
1589         /* FDI must be feeding us bits for PCH ports */
1590         assert_fdi_tx_enabled(dev_priv, pipe);
1591         assert_fdi_rx_enabled(dev_priv, pipe);
1592
1593         if (HAS_PCH_CPT(dev)) {
1594                 /* Workaround: Set the timing override bit before enabling the
1595                  * pch transcoder. */
1596                 reg = TRANS_CHICKEN2(pipe);
1597                 val = I915_READ(reg);
1598                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1599                 I915_WRITE(reg, val);
1600         }
1601
1602         reg = PCH_TRANSCONF(pipe);
1603         val = I915_READ(reg);
1604         pipeconf_val = I915_READ(PIPECONF(pipe));
1605
1606         if (HAS_PCH_IBX(dev_priv->dev)) {
1607                 /*
1608                  * make the BPC in transcoder be consistent with
1609                  * that in pipeconf reg.
1610                  */
1611                 val &= ~PIPECONF_BPC_MASK;
1612                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1613         }
1614
1615         val &= ~TRANS_INTERLACE_MASK;
1616         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1617                 if (HAS_PCH_IBX(dev_priv->dev) &&
1618                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1619                         val |= TRANS_LEGACY_INTERLACED_ILK;
1620                 else
1621                         val |= TRANS_INTERLACED;
1622         else
1623                 val |= TRANS_PROGRESSIVE;
1624
1625         I915_WRITE(reg, val | TRANS_ENABLE);
1626         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1627                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1628 }
1629
1630 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1631                                       enum transcoder cpu_transcoder)
1632 {
1633         u32 val, pipeconf_val;
1634
1635         /* PCH only available on ILK+ */
1636         BUG_ON(dev_priv->info->gen < 5);
1637
1638         /* FDI must be feeding us bits for PCH ports */
1639         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1640         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1641
1642         /* Workaround: set timing override bit. */
1643         val = I915_READ(_TRANSA_CHICKEN2);
1644         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1645         I915_WRITE(_TRANSA_CHICKEN2, val);
1646
1647         val = TRANS_ENABLE;
1648         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1649
1650         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1651             PIPECONF_INTERLACED_ILK)
1652                 val |= TRANS_INTERLACED;
1653         else
1654                 val |= TRANS_PROGRESSIVE;
1655
1656         I915_WRITE(LPT_TRANSCONF, val);
1657         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1658                 DRM_ERROR("Failed to enable PCH transcoder\n");
1659 }
1660
1661 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1662                                             enum pipe pipe)
1663 {
1664         struct drm_device *dev = dev_priv->dev;
1665         uint32_t reg, val;
1666
1667         /* FDI relies on the transcoder */
1668         assert_fdi_tx_disabled(dev_priv, pipe);
1669         assert_fdi_rx_disabled(dev_priv, pipe);
1670
1671         /* Ports must be off as well */
1672         assert_pch_ports_disabled(dev_priv, pipe);
1673
1674         reg = PCH_TRANSCONF(pipe);
1675         val = I915_READ(reg);
1676         val &= ~TRANS_ENABLE;
1677         I915_WRITE(reg, val);
1678         /* wait for PCH transcoder off, transcoder state */
1679         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1680                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1681
1682         if (!HAS_PCH_IBX(dev)) {
1683                 /* Workaround: Clear the timing override chicken bit again. */
1684                 reg = TRANS_CHICKEN2(pipe);
1685                 val = I915_READ(reg);
1686                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1687                 I915_WRITE(reg, val);
1688         }
1689 }
1690
1691 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1692 {
1693         u32 val;
1694
1695         val = I915_READ(LPT_TRANSCONF);
1696         val &= ~TRANS_ENABLE;
1697         I915_WRITE(LPT_TRANSCONF, val);
1698         /* wait for PCH transcoder off, transcoder state */
1699         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1700                 DRM_ERROR("Failed to disable PCH transcoder\n");
1701
1702         /* Workaround: clear timing override bit. */
1703         val = I915_READ(_TRANSA_CHICKEN2);
1704         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1705         I915_WRITE(_TRANSA_CHICKEN2, val);
1706 }
1707
1708 /**
1709  * intel_enable_pipe - enable a pipe, asserting requirements
1710  * @dev_priv: i915 private structure
1711  * @pipe: pipe to enable
1712  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1713  *
1714  * Enable @pipe, making sure that various hardware specific requirements
1715  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1716  *
1717  * @pipe should be %PIPE_A or %PIPE_B.
1718  *
1719  * Will wait until the pipe is actually running (i.e. first vblank) before
1720  * returning.
1721  */
1722 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1723                               bool pch_port)
1724 {
1725         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1726                                                                       pipe);
1727         enum pipe pch_transcoder;
1728         int reg;
1729         u32 val;
1730
1731         assert_planes_disabled(dev_priv, pipe);
1732         assert_sprites_disabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_LPT(dev_priv->dev))
1735                 pch_transcoder = TRANSCODER_A;
1736         else
1737                 pch_transcoder = pipe;
1738
1739         /*
1740          * A pipe without a PLL won't actually be able to drive bits from
1741          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1742          * need the check.
1743          */
1744         if (!HAS_PCH_SPLIT(dev_priv->dev))
1745                 assert_pll_enabled(dev_priv, pipe);
1746         else {
1747                 if (pch_port) {
1748                         /* if driving the PCH, we need FDI enabled */
1749                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1750                         assert_fdi_tx_pll_enabled(dev_priv,
1751                                                   (enum pipe) cpu_transcoder);
1752                 }
1753                 /* FIXME: assert CPU port conditions for SNB+ */
1754         }
1755
1756         reg = PIPECONF(cpu_transcoder);
1757         val = I915_READ(reg);
1758         if (val & PIPECONF_ENABLE)
1759                 return;
1760
1761         I915_WRITE(reg, val | PIPECONF_ENABLE);
1762         intel_wait_for_vblank(dev_priv->dev, pipe);
1763 }
1764
1765 /**
1766  * intel_disable_pipe - disable a pipe, asserting requirements
1767  * @dev_priv: i915 private structure
1768  * @pipe: pipe to disable
1769  *
1770  * Disable @pipe, making sure that various hardware specific requirements
1771  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772  *
1773  * @pipe should be %PIPE_A or %PIPE_B.
1774  *
1775  * Will wait until the pipe has shut down before returning.
1776  */
1777 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1778                                enum pipe pipe)
1779 {
1780         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1781                                                                       pipe);
1782         int reg;
1783         u32 val;
1784
1785         /*
1786          * Make sure planes won't keep trying to pump pixels to us,
1787          * or we might hang the display.
1788          */
1789         assert_planes_disabled(dev_priv, pipe);
1790         assert_sprites_disabled(dev_priv, pipe);
1791
1792         /* Don't disable pipe A or pipe A PLLs if needed */
1793         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1794                 return;
1795
1796         reg = PIPECONF(cpu_transcoder);
1797         val = I915_READ(reg);
1798         if ((val & PIPECONF_ENABLE) == 0)
1799                 return;
1800
1801         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1802         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1803 }
1804
1805 /*
1806  * Plane regs are double buffered, going from enabled->disabled needs a
1807  * trigger in order to latch.  The display address reg provides this.
1808  */
1809 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1810                                       enum plane plane)
1811 {
1812         if (dev_priv->info->gen >= 4)
1813                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1814         else
1815                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1816 }
1817
1818 /**
1819  * intel_enable_plane - enable a display plane on a given pipe
1820  * @dev_priv: i915 private structure
1821  * @plane: plane to enable
1822  * @pipe: pipe being fed
1823  *
1824  * Enable @plane on @pipe, making sure that @pipe is running first.
1825  */
1826 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1827                                enum plane plane, enum pipe pipe)
1828 {
1829         int reg;
1830         u32 val;
1831
1832         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1833         assert_pipe_enabled(dev_priv, pipe);
1834
1835         reg = DSPCNTR(plane);
1836         val = I915_READ(reg);
1837         if (val & DISPLAY_PLANE_ENABLE)
1838                 return;
1839
1840         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1841         intel_flush_display_plane(dev_priv, plane);
1842         intel_wait_for_vblank(dev_priv->dev, pipe);
1843 }
1844
1845 /**
1846  * intel_disable_plane - disable a display plane
1847  * @dev_priv: i915 private structure
1848  * @plane: plane to disable
1849  * @pipe: pipe consuming the data
1850  *
1851  * Disable @plane; should be an independent operation.
1852  */
1853 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1854                                 enum plane plane, enum pipe pipe)
1855 {
1856         int reg;
1857         u32 val;
1858
1859         reg = DSPCNTR(plane);
1860         val = I915_READ(reg);
1861         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1862                 return;
1863
1864         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1865         intel_flush_display_plane(dev_priv, plane);
1866         intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 static bool need_vtd_wa(struct drm_device *dev)
1870 {
1871 #ifdef CONFIG_INTEL_IOMMU
1872         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1873                 return true;
1874 #endif
1875         return false;
1876 }
1877
1878 int
1879 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1880                            struct drm_i915_gem_object *obj,
1881                            struct intel_ring_buffer *pipelined)
1882 {
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884         u32 alignment;
1885         int ret;
1886
1887         switch (obj->tiling_mode) {
1888         case I915_TILING_NONE:
1889                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1890                         alignment = 128 * 1024;
1891                 else if (INTEL_INFO(dev)->gen >= 4)
1892                         alignment = 4 * 1024;
1893                 else
1894                         alignment = 64 * 1024;
1895                 break;
1896         case I915_TILING_X:
1897                 /* pin() will align the object as required by fence */
1898                 alignment = 0;
1899                 break;
1900         case I915_TILING_Y:
1901                 /* Despite that we check this in framebuffer_init userspace can
1902                  * screw us over and change the tiling after the fact. Only
1903                  * pinned buffers can't change their tiling. */
1904                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1905                 return -EINVAL;
1906         default:
1907                 BUG();
1908         }
1909
1910         /* Note that the w/a also requires 64 PTE of padding following the
1911          * bo. We currently fill all unused PTE with the shadow page and so
1912          * we should always have valid PTE following the scanout preventing
1913          * the VT-d warning.
1914          */
1915         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1916                 alignment = 256 * 1024;
1917
1918         dev_priv->mm.interruptible = false;
1919         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1920         if (ret)
1921                 goto err_interruptible;
1922
1923         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1924          * fence, whereas 965+ only requires a fence if using
1925          * framebuffer compression.  For simplicity, we always install
1926          * a fence as the cost is not that onerous.
1927          */
1928         ret = i915_gem_object_get_fence(obj);
1929         if (ret)
1930                 goto err_unpin;
1931
1932         i915_gem_object_pin_fence(obj);
1933
1934         dev_priv->mm.interruptible = true;
1935         return 0;
1936
1937 err_unpin:
1938         i915_gem_object_unpin(obj);
1939 err_interruptible:
1940         dev_priv->mm.interruptible = true;
1941         return ret;
1942 }
1943
1944 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1945 {
1946         i915_gem_object_unpin_fence(obj);
1947         i915_gem_object_unpin(obj);
1948 }
1949
1950 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1951  * is assumed to be a power-of-two. */
1952 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1953                                              unsigned int tiling_mode,
1954                                              unsigned int cpp,
1955                                              unsigned int pitch)
1956 {
1957         if (tiling_mode != I915_TILING_NONE) {
1958                 unsigned int tile_rows, tiles;
1959
1960                 tile_rows = *y / 8;
1961                 *y %= 8;
1962
1963                 tiles = *x / (512/cpp);
1964                 *x %= 512/cpp;
1965
1966                 return tile_rows * pitch * 8 + tiles * 4096;
1967         } else {
1968                 unsigned int offset;
1969
1970                 offset = *y * pitch + *x * cpp;
1971                 *y = 0;
1972                 *x = (offset & 4095) / cpp;
1973                 return offset & -4096;
1974         }
1975 }
1976
1977 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978                              int x, int y)
1979 {
1980         struct drm_device *dev = crtc->dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         struct intel_framebuffer *intel_fb;
1984         struct drm_i915_gem_object *obj;
1985         int plane = intel_crtc->plane;
1986         unsigned long linear_offset;
1987         u32 dspcntr;
1988         u32 reg;
1989
1990         switch (plane) {
1991         case 0:
1992         case 1:
1993                 break;
1994         default:
1995                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1996                 return -EINVAL;
1997         }
1998
1999         intel_fb = to_intel_framebuffer(fb);
2000         obj = intel_fb->obj;
2001
2002         reg = DSPCNTR(plane);
2003         dspcntr = I915_READ(reg);
2004         /* Mask out pixel format bits in case we change it */
2005         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2006         switch (fb->pixel_format) {
2007         case DRM_FORMAT_C8:
2008                 dspcntr |= DISPPLANE_8BPP;
2009                 break;
2010         case DRM_FORMAT_XRGB1555:
2011         case DRM_FORMAT_ARGB1555:
2012                 dspcntr |= DISPPLANE_BGRX555;
2013                 break;
2014         case DRM_FORMAT_RGB565:
2015                 dspcntr |= DISPPLANE_BGRX565;
2016                 break;
2017         case DRM_FORMAT_XRGB8888:
2018         case DRM_FORMAT_ARGB8888:
2019                 dspcntr |= DISPPLANE_BGRX888;
2020                 break;
2021         case DRM_FORMAT_XBGR8888:
2022         case DRM_FORMAT_ABGR8888:
2023                 dspcntr |= DISPPLANE_RGBX888;
2024                 break;
2025         case DRM_FORMAT_XRGB2101010:
2026         case DRM_FORMAT_ARGB2101010:
2027                 dspcntr |= DISPPLANE_BGRX101010;
2028                 break;
2029         case DRM_FORMAT_XBGR2101010:
2030         case DRM_FORMAT_ABGR2101010:
2031                 dspcntr |= DISPPLANE_RGBX101010;
2032                 break;
2033         default:
2034                 BUG();
2035         }
2036
2037         if (INTEL_INFO(dev)->gen >= 4) {
2038                 if (obj->tiling_mode != I915_TILING_NONE)
2039                         dspcntr |= DISPPLANE_TILED;
2040                 else
2041                         dspcntr &= ~DISPPLANE_TILED;
2042         }
2043
2044         I915_WRITE(reg, dspcntr);
2045
2046         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2047
2048         if (INTEL_INFO(dev)->gen >= 4) {
2049                 intel_crtc->dspaddr_offset =
2050                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051                                                        fb->bits_per_pixel / 8,
2052                                                        fb->pitches[0]);
2053                 linear_offset -= intel_crtc->dspaddr_offset;
2054         } else {
2055                 intel_crtc->dspaddr_offset = linear_offset;
2056         }
2057
2058         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2059                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2060         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2061         if (INTEL_INFO(dev)->gen >= 4) {
2062                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2063                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2064                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2065                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2066         } else
2067                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2068         POSTING_READ(reg);
2069
2070         return 0;
2071 }
2072
2073 static int ironlake_update_plane(struct drm_crtc *crtc,
2074                                  struct drm_framebuffer *fb, int x, int y)
2075 {
2076         struct drm_device *dev = crtc->dev;
2077         struct drm_i915_private *dev_priv = dev->dev_private;
2078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079         struct intel_framebuffer *intel_fb;
2080         struct drm_i915_gem_object *obj;
2081         int plane = intel_crtc->plane;
2082         unsigned long linear_offset;
2083         u32 dspcntr;
2084         u32 reg;
2085
2086         switch (plane) {
2087         case 0:
2088         case 1:
2089         case 2:
2090                 break;
2091         default:
2092                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2093                 return -EINVAL;
2094         }
2095
2096         intel_fb = to_intel_framebuffer(fb);
2097         obj = intel_fb->obj;
2098
2099         reg = DSPCNTR(plane);
2100         dspcntr = I915_READ(reg);
2101         /* Mask out pixel format bits in case we change it */
2102         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2103         switch (fb->pixel_format) {
2104         case DRM_FORMAT_C8:
2105                 dspcntr |= DISPPLANE_8BPP;
2106                 break;
2107         case DRM_FORMAT_RGB565:
2108                 dspcntr |= DISPPLANE_BGRX565;
2109                 break;
2110         case DRM_FORMAT_XRGB8888:
2111         case DRM_FORMAT_ARGB8888:
2112                 dspcntr |= DISPPLANE_BGRX888;
2113                 break;
2114         case DRM_FORMAT_XBGR8888:
2115         case DRM_FORMAT_ABGR8888:
2116                 dspcntr |= DISPPLANE_RGBX888;
2117                 break;
2118         case DRM_FORMAT_XRGB2101010:
2119         case DRM_FORMAT_ARGB2101010:
2120                 dspcntr |= DISPPLANE_BGRX101010;
2121                 break;
2122         case DRM_FORMAT_XBGR2101010:
2123         case DRM_FORMAT_ABGR2101010:
2124                 dspcntr |= DISPPLANE_RGBX101010;
2125                 break;
2126         default:
2127                 BUG();
2128         }
2129
2130         if (obj->tiling_mode != I915_TILING_NONE)
2131                 dspcntr |= DISPPLANE_TILED;
2132         else
2133                 dspcntr &= ~DISPPLANE_TILED;
2134
2135         /* must disable */
2136         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2137
2138         I915_WRITE(reg, dspcntr);
2139
2140         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2141         intel_crtc->dspaddr_offset =
2142                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2143                                                fb->bits_per_pixel / 8,
2144                                                fb->pitches[0]);
2145         linear_offset -= intel_crtc->dspaddr_offset;
2146
2147         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2148                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2149         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2150         I915_MODIFY_DISPBASE(DSPSURF(plane),
2151                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2152         if (IS_HASWELL(dev)) {
2153                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2154         } else {
2155                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2156                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2157         }
2158         POSTING_READ(reg);
2159
2160         return 0;
2161 }
2162
2163 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2164 static int
2165 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2166                            int x, int y, enum mode_set_atomic state)
2167 {
2168         struct drm_device *dev = crtc->dev;
2169         struct drm_i915_private *dev_priv = dev->dev_private;
2170
2171         if (dev_priv->display.disable_fbc)
2172                 dev_priv->display.disable_fbc(dev);
2173         intel_increase_pllclock(crtc);
2174
2175         return dev_priv->display.update_plane(crtc, fb, x, y);
2176 }
2177
2178 void intel_display_handle_reset(struct drm_device *dev)
2179 {
2180         struct drm_i915_private *dev_priv = dev->dev_private;
2181         struct drm_crtc *crtc;
2182
2183         /*
2184          * Flips in the rings have been nuked by the reset,
2185          * so complete all pending flips so that user space
2186          * will get its events and not get stuck.
2187          *
2188          * Also update the base address of all primary
2189          * planes to the the last fb to make sure we're
2190          * showing the correct fb after a reset.
2191          *
2192          * Need to make two loops over the crtcs so that we
2193          * don't try to grab a crtc mutex before the
2194          * pending_flip_queue really got woken up.
2195          */
2196
2197         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2198                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199                 enum plane plane = intel_crtc->plane;
2200
2201                 intel_prepare_page_flip(dev, plane);
2202                 intel_finish_page_flip_plane(dev, plane);
2203         }
2204
2205         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2206                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207
2208                 mutex_lock(&crtc->mutex);
2209                 if (intel_crtc->active)
2210                         dev_priv->display.update_plane(crtc, crtc->fb,
2211                                                        crtc->x, crtc->y);
2212                 mutex_unlock(&crtc->mutex);
2213         }
2214 }
2215
2216 static int
2217 intel_finish_fb(struct drm_framebuffer *old_fb)
2218 {
2219         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2220         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2221         bool was_interruptible = dev_priv->mm.interruptible;
2222         int ret;
2223
2224         /* Big Hammer, we also need to ensure that any pending
2225          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2226          * current scanout is retired before unpinning the old
2227          * framebuffer.
2228          *
2229          * This should only fail upon a hung GPU, in which case we
2230          * can safely continue.
2231          */
2232         dev_priv->mm.interruptible = false;
2233         ret = i915_gem_object_finish_gpu(obj);
2234         dev_priv->mm.interruptible = was_interruptible;
2235
2236         return ret;
2237 }
2238
2239 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2240 {
2241         struct drm_device *dev = crtc->dev;
2242         struct drm_i915_master_private *master_priv;
2243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244
2245         if (!dev->primary->master)
2246                 return;
2247
2248         master_priv = dev->primary->master->driver_priv;
2249         if (!master_priv->sarea_priv)
2250                 return;
2251
2252         switch (intel_crtc->pipe) {
2253         case 0:
2254                 master_priv->sarea_priv->pipeA_x = x;
2255                 master_priv->sarea_priv->pipeA_y = y;
2256                 break;
2257         case 1:
2258                 master_priv->sarea_priv->pipeB_x = x;
2259                 master_priv->sarea_priv->pipeB_y = y;
2260                 break;
2261         default:
2262                 break;
2263         }
2264 }
2265
2266 static int
2267 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2268                     struct drm_framebuffer *fb)
2269 {
2270         struct drm_device *dev = crtc->dev;
2271         struct drm_i915_private *dev_priv = dev->dev_private;
2272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2273         struct drm_framebuffer *old_fb;
2274         int ret;
2275
2276         /* no fb bound */
2277         if (!fb) {
2278                 DRM_ERROR("No FB bound\n");
2279                 return 0;
2280         }
2281
2282         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2283                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2284                           plane_name(intel_crtc->plane),
2285                           INTEL_INFO(dev)->num_pipes);
2286                 return -EINVAL;
2287         }
2288
2289         mutex_lock(&dev->struct_mutex);
2290         ret = intel_pin_and_fence_fb_obj(dev,
2291                                          to_intel_framebuffer(fb)->obj,
2292                                          NULL);
2293         if (ret != 0) {
2294                 mutex_unlock(&dev->struct_mutex);
2295                 DRM_ERROR("pin & fence failed\n");
2296                 return ret;
2297         }
2298
2299         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2300         if (ret) {
2301                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2302                 mutex_unlock(&dev->struct_mutex);
2303                 DRM_ERROR("failed to update base address\n");
2304                 return ret;
2305         }
2306
2307         old_fb = crtc->fb;
2308         crtc->fb = fb;
2309         crtc->x = x;
2310         crtc->y = y;
2311
2312         if (old_fb) {
2313                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2314                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2315         }
2316
2317         intel_update_fbc(dev);
2318         mutex_unlock(&dev->struct_mutex);
2319
2320         intel_crtc_update_sarea_pos(crtc, x, y);
2321
2322         return 0;
2323 }
2324
2325 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2326 {
2327         struct drm_device *dev = crtc->dev;
2328         struct drm_i915_private *dev_priv = dev->dev_private;
2329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2330         int pipe = intel_crtc->pipe;
2331         u32 reg, temp;
2332
2333         /* enable normal train */
2334         reg = FDI_TX_CTL(pipe);
2335         temp = I915_READ(reg);
2336         if (IS_IVYBRIDGE(dev)) {
2337                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2338                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2339         } else {
2340                 temp &= ~FDI_LINK_TRAIN_NONE;
2341                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2342         }
2343         I915_WRITE(reg, temp);
2344
2345         reg = FDI_RX_CTL(pipe);
2346         temp = I915_READ(reg);
2347         if (HAS_PCH_CPT(dev)) {
2348                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2350         } else {
2351                 temp &= ~FDI_LINK_TRAIN_NONE;
2352                 temp |= FDI_LINK_TRAIN_NONE;
2353         }
2354         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2355
2356         /* wait one idle pattern time */
2357         POSTING_READ(reg);
2358         udelay(1000);
2359
2360         /* IVB wants error correction enabled */
2361         if (IS_IVYBRIDGE(dev))
2362                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2363                            FDI_FE_ERRC_ENABLE);
2364 }
2365
2366 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2367 {
2368         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2369 }
2370
2371 static void ivb_modeset_global_resources(struct drm_device *dev)
2372 {
2373         struct drm_i915_private *dev_priv = dev->dev_private;
2374         struct intel_crtc *pipe_B_crtc =
2375                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2376         struct intel_crtc *pipe_C_crtc =
2377                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2378         uint32_t temp;
2379
2380         /*
2381          * When everything is off disable fdi C so that we could enable fdi B
2382          * with all lanes. Note that we don't care about enabled pipes without
2383          * an enabled pch encoder.
2384          */
2385         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2386             !pipe_has_enabled_pch(pipe_C_crtc)) {
2387                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390                 temp = I915_READ(SOUTH_CHICKEN1);
2391                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393                 I915_WRITE(SOUTH_CHICKEN1, temp);
2394         }
2395 }
2396
2397 /* The FDI link training functions for ILK/Ibexpeak. */
2398 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         int plane = intel_crtc->plane;
2405         u32 reg, temp, tries;
2406
2407         /* FDI needs bits from pipe & plane first */
2408         assert_pipe_enabled(dev_priv, pipe);
2409         assert_plane_enabled(dev_priv, plane);
2410
2411         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412            for train result */
2413         reg = FDI_RX_IMR(pipe);
2414         temp = I915_READ(reg);
2415         temp &= ~FDI_RX_SYMBOL_LOCK;
2416         temp &= ~FDI_RX_BIT_LOCK;
2417         I915_WRITE(reg, temp);
2418         I915_READ(reg);
2419         udelay(150);
2420
2421         /* enable CPU FDI TX and PCH FDI RX */
2422         reg = FDI_TX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_1;
2428         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2429
2430         reg = FDI_RX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436         POSTING_READ(reg);
2437         udelay(150);
2438
2439         /* Ironlake workaround, enable clock pointer after FDI enable*/
2440         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442                    FDI_RX_PHASE_SYNC_POINTER_EN);
2443
2444         reg = FDI_RX_IIR(pipe);
2445         for (tries = 0; tries < 5; tries++) {
2446                 temp = I915_READ(reg);
2447                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449                 if ((temp & FDI_RX_BIT_LOCK)) {
2450                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2451                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452                         break;
2453                 }
2454         }
2455         if (tries == 5)
2456                 DRM_ERROR("FDI train 1 fail!\n");
2457
2458         /* Train 2 */
2459         reg = FDI_TX_CTL(pipe);
2460         temp = I915_READ(reg);
2461         temp &= ~FDI_LINK_TRAIN_NONE;
2462         temp |= FDI_LINK_TRAIN_PATTERN_2;
2463         I915_WRITE(reg, temp);
2464
2465         reg = FDI_RX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         POSTING_READ(reg);
2472         udelay(150);
2473
2474         reg = FDI_RX_IIR(pipe);
2475         for (tries = 0; tries < 5; tries++) {
2476                 temp = I915_READ(reg);
2477                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479                 if (temp & FDI_RX_SYMBOL_LOCK) {
2480                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2481                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2482                         break;
2483                 }
2484         }
2485         if (tries == 5)
2486                 DRM_ERROR("FDI train 2 fail!\n");
2487
2488         DRM_DEBUG_KMS("FDI train done\n");
2489
2490 }
2491
2492 static const int snb_b_fdi_train_param[] = {
2493         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497 };
2498
2499 /* The FDI link training functions for SNB/Cougarpoint. */
2500 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501 {
2502         struct drm_device *dev = crtc->dev;
2503         struct drm_i915_private *dev_priv = dev->dev_private;
2504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505         int pipe = intel_crtc->pipe;
2506         u32 reg, temp, i, retry;
2507
2508         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509            for train result */
2510         reg = FDI_RX_IMR(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_RX_SYMBOL_LOCK;
2513         temp &= ~FDI_RX_BIT_LOCK;
2514         I915_WRITE(reg, temp);
2515
2516         POSTING_READ(reg);
2517         udelay(150);
2518
2519         /* enable CPU FDI TX and PCH FDI RX */
2520         reg = FDI_TX_CTL(pipe);
2521         temp = I915_READ(reg);
2522         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2523         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2524         temp &= ~FDI_LINK_TRAIN_NONE;
2525         temp |= FDI_LINK_TRAIN_PATTERN_1;
2526         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527         /* SNB-B */
2528         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2529         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2530
2531         I915_WRITE(FDI_RX_MISC(pipe),
2532                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
2534         reg = FDI_RX_CTL(pipe);
2535         temp = I915_READ(reg);
2536         if (HAS_PCH_CPT(dev)) {
2537                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539         } else {
2540                 temp &= ~FDI_LINK_TRAIN_NONE;
2541                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542         }
2543         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545         POSTING_READ(reg);
2546         udelay(150);
2547
2548         for (i = 0; i < 4; i++) {
2549                 reg = FDI_TX_CTL(pipe);
2550                 temp = I915_READ(reg);
2551                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552                 temp |= snb_b_fdi_train_param[i];
2553                 I915_WRITE(reg, temp);
2554
2555                 POSTING_READ(reg);
2556                 udelay(500);
2557
2558                 for (retry = 0; retry < 5; retry++) {
2559                         reg = FDI_RX_IIR(pipe);
2560                         temp = I915_READ(reg);
2561                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562                         if (temp & FDI_RX_BIT_LOCK) {
2563                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565                                 break;
2566                         }
2567                         udelay(50);
2568                 }
2569                 if (retry < 5)
2570                         break;
2571         }
2572         if (i == 4)
2573                 DRM_ERROR("FDI train 1 fail!\n");
2574
2575         /* Train 2 */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_LINK_TRAIN_NONE;
2579         temp |= FDI_LINK_TRAIN_PATTERN_2;
2580         if (IS_GEN6(dev)) {
2581                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582                 /* SNB-B */
2583                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584         }
2585         I915_WRITE(reg, temp);
2586
2587         reg = FDI_RX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         if (HAS_PCH_CPT(dev)) {
2590                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592         } else {
2593                 temp &= ~FDI_LINK_TRAIN_NONE;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595         }
2596         I915_WRITE(reg, temp);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         for (i = 0; i < 4; i++) {
2602                 reg = FDI_TX_CTL(pipe);
2603                 temp = I915_READ(reg);
2604                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605                 temp |= snb_b_fdi_train_param[i];
2606                 I915_WRITE(reg, temp);
2607
2608                 POSTING_READ(reg);
2609                 udelay(500);
2610
2611                 for (retry = 0; retry < 5; retry++) {
2612                         reg = FDI_RX_IIR(pipe);
2613                         temp = I915_READ(reg);
2614                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615                         if (temp & FDI_RX_SYMBOL_LOCK) {
2616                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618                                 break;
2619                         }
2620                         udelay(50);
2621                 }
2622                 if (retry < 5)
2623                         break;
2624         }
2625         if (i == 4)
2626                 DRM_ERROR("FDI train 2 fail!\n");
2627
2628         DRM_DEBUG_KMS("FDI train done.\n");
2629 }
2630
2631 /* Manual link training for Ivy Bridge A0 parts */
2632 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633 {
2634         struct drm_device *dev = crtc->dev;
2635         struct drm_i915_private *dev_priv = dev->dev_private;
2636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637         int pipe = intel_crtc->pipe;
2638         u32 reg, temp, i;
2639
2640         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641            for train result */
2642         reg = FDI_RX_IMR(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~FDI_RX_SYMBOL_LOCK;
2645         temp &= ~FDI_RX_BIT_LOCK;
2646         I915_WRITE(reg, temp);
2647
2648         POSTING_READ(reg);
2649         udelay(150);
2650
2651         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652                       I915_READ(FDI_RX_IIR(pipe)));
2653
2654         /* enable CPU FDI TX and PCH FDI RX */
2655         reg = FDI_TX_CTL(pipe);
2656         temp = I915_READ(reg);
2657         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2658         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2659         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663         temp |= FDI_COMPOSITE_SYNC;
2664         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
2666         I915_WRITE(FDI_RX_MISC(pipe),
2667                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
2669         reg = FDI_RX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~FDI_LINK_TRAIN_AUTO;
2672         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2674         temp |= FDI_COMPOSITE_SYNC;
2675         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677         POSTING_READ(reg);
2678         udelay(150);
2679
2680         for (i = 0; i < 4; i++) {
2681                 reg = FDI_TX_CTL(pipe);
2682                 temp = I915_READ(reg);
2683                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684                 temp |= snb_b_fdi_train_param[i];
2685                 I915_WRITE(reg, temp);
2686
2687                 POSTING_READ(reg);
2688                 udelay(500);
2689
2690                 reg = FDI_RX_IIR(pipe);
2691                 temp = I915_READ(reg);
2692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694                 if (temp & FDI_RX_BIT_LOCK ||
2695                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2697                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2698                         break;
2699                 }
2700         }
2701         if (i == 4)
2702                 DRM_ERROR("FDI train 1 fail!\n");
2703
2704         /* Train 2 */
2705         reg = FDI_TX_CTL(pipe);
2706         temp = I915_READ(reg);
2707         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711         I915_WRITE(reg, temp);
2712
2713         reg = FDI_RX_CTL(pipe);
2714         temp = I915_READ(reg);
2715         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717         I915_WRITE(reg, temp);
2718
2719         POSTING_READ(reg);
2720         udelay(150);
2721
2722         for (i = 0; i < 4; i++) {
2723                 reg = FDI_TX_CTL(pipe);
2724                 temp = I915_READ(reg);
2725                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726                 temp |= snb_b_fdi_train_param[i];
2727                 I915_WRITE(reg, temp);
2728
2729                 POSTING_READ(reg);
2730                 udelay(500);
2731
2732                 reg = FDI_RX_IIR(pipe);
2733                 temp = I915_READ(reg);
2734                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736                 if (temp & FDI_RX_SYMBOL_LOCK) {
2737                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2738                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2739                         break;
2740                 }
2741         }
2742         if (i == 4)
2743                 DRM_ERROR("FDI train 2 fail!\n");
2744
2745         DRM_DEBUG_KMS("FDI train done.\n");
2746 }
2747
2748 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2749 {
2750         struct drm_device *dev = intel_crtc->base.dev;
2751         struct drm_i915_private *dev_priv = dev->dev_private;
2752         int pipe = intel_crtc->pipe;
2753         u32 reg, temp;
2754
2755
2756         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2757         reg = FDI_RX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2760         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2761         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2762         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764         POSTING_READ(reg);
2765         udelay(200);
2766
2767         /* Switch from Rawclk to PCDclk */
2768         temp = I915_READ(reg);
2769         I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771         POSTING_READ(reg);
2772         udelay(200);
2773
2774         /* Enable CPU FDI TX PLL, always on for Ironlake */
2775         reg = FDI_TX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2779
2780                 POSTING_READ(reg);
2781                 udelay(100);
2782         }
2783 }
2784
2785 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786 {
2787         struct drm_device *dev = intel_crtc->base.dev;
2788         struct drm_i915_private *dev_priv = dev->dev_private;
2789         int pipe = intel_crtc->pipe;
2790         u32 reg, temp;
2791
2792         /* Switch from PCDclk to Rawclk */
2793         reg = FDI_RX_CTL(pipe);
2794         temp = I915_READ(reg);
2795         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797         /* Disable CPU FDI TX PLL */
2798         reg = FDI_TX_CTL(pipe);
2799         temp = I915_READ(reg);
2800         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802         POSTING_READ(reg);
2803         udelay(100);
2804
2805         reg = FDI_RX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809         /* Wait for the clocks to turn off. */
2810         POSTING_READ(reg);
2811         udelay(100);
2812 }
2813
2814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815 {
2816         struct drm_device *dev = crtc->dev;
2817         struct drm_i915_private *dev_priv = dev->dev_private;
2818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819         int pipe = intel_crtc->pipe;
2820         u32 reg, temp;
2821
2822         /* disable CPU FDI tx and PCH FDI rx */
2823         reg = FDI_TX_CTL(pipe);
2824         temp = I915_READ(reg);
2825         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826         POSTING_READ(reg);
2827
2828         reg = FDI_RX_CTL(pipe);
2829         temp = I915_READ(reg);
2830         temp &= ~(0x7 << 16);
2831         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2832         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834         POSTING_READ(reg);
2835         udelay(100);
2836
2837         /* Ironlake workaround, disable clock pointer after downing FDI */
2838         if (HAS_PCH_IBX(dev)) {
2839                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2840         }
2841
2842         /* still set train pattern 1 */
2843         reg = FDI_TX_CTL(pipe);
2844         temp = I915_READ(reg);
2845         temp &= ~FDI_LINK_TRAIN_NONE;
2846         temp |= FDI_LINK_TRAIN_PATTERN_1;
2847         I915_WRITE(reg, temp);
2848
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         if (HAS_PCH_CPT(dev)) {
2852                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854         } else {
2855                 temp &= ~FDI_LINK_TRAIN_NONE;
2856                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857         }
2858         /* BPC in FDI rx is consistent with that in PIPECONF */
2859         temp &= ~(0x07 << 16);
2860         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861         I915_WRITE(reg, temp);
2862
2863         POSTING_READ(reg);
2864         udelay(100);
2865 }
2866
2867 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868 {
2869         struct drm_device *dev = crtc->dev;
2870         struct drm_i915_private *dev_priv = dev->dev_private;
2871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2872         unsigned long flags;
2873         bool pending;
2874
2875         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2877                 return false;
2878
2879         spin_lock_irqsave(&dev->event_lock, flags);
2880         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881         spin_unlock_irqrestore(&dev->event_lock, flags);
2882
2883         return pending;
2884 }
2885
2886 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2887 {
2888         struct drm_device *dev = crtc->dev;
2889         struct drm_i915_private *dev_priv = dev->dev_private;
2890
2891         if (crtc->fb == NULL)
2892                 return;
2893
2894         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2895
2896         wait_event(dev_priv->pending_flip_queue,
2897                    !intel_crtc_has_pending_flip(crtc));
2898
2899         mutex_lock(&dev->struct_mutex);
2900         intel_finish_fb(crtc->fb);
2901         mutex_unlock(&dev->struct_mutex);
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907         struct drm_device *dev = crtc->dev;
2908         struct drm_i915_private *dev_priv = dev->dev_private;
2909         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910         u32 temp;
2911
2912         mutex_lock(&dev_priv->dpio_lock);
2913
2914         /* It is necessary to ungate the pixclk gate prior to programming
2915          * the divisors, and gate it back when it is done.
2916          */
2917         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2918
2919         /* Disable SSCCTL */
2920         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2921                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2922                                 SBI_SSCCTL_DISABLE,
2923                         SBI_ICLK);
2924
2925         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2926         if (crtc->mode.clock == 20000) {
2927                 auxdiv = 1;
2928                 divsel = 0x41;
2929                 phaseinc = 0x20;
2930         } else {
2931                 /* The iCLK virtual clock root frequency is in MHz,
2932                  * but the crtc->mode.clock in in KHz. To get the divisors,
2933                  * it is necessary to divide one by another, so we
2934                  * convert the virtual clock precision to KHz here for higher
2935                  * precision.
2936                  */
2937                 u32 iclk_virtual_root_freq = 172800 * 1000;
2938                 u32 iclk_pi_range = 64;
2939                 u32 desired_divisor, msb_divisor_value, pi_value;
2940
2941                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2942                 msb_divisor_value = desired_divisor / iclk_pi_range;
2943                 pi_value = desired_divisor % iclk_pi_range;
2944
2945                 auxdiv = 0;
2946                 divsel = msb_divisor_value - 2;
2947                 phaseinc = pi_value;
2948         }
2949
2950         /* This should not happen with any sane values */
2951         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2952                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2953         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2954                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2955
2956         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2957                         crtc->mode.clock,
2958                         auxdiv,
2959                         divsel,
2960                         phasedir,
2961                         phaseinc);
2962
2963         /* Program SSCDIVINTPHASE6 */
2964         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2965         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2966         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2967         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2968         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2969         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2970         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2971         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2972
2973         /* Program SSCAUXDIV */
2974         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2975         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2978
2979         /* Enable modulator and associated divider */
2980         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2981         temp &= ~SBI_SSCCTL_DISABLE;
2982         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2983
2984         /* Wait for initialization time */
2985         udelay(24);
2986
2987         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2988
2989         mutex_unlock(&dev_priv->dpio_lock);
2990 }
2991
2992 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2993                                                 enum pipe pch_transcoder)
2994 {
2995         struct drm_device *dev = crtc->base.dev;
2996         struct drm_i915_private *dev_priv = dev->dev_private;
2997         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2998
2999         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3000                    I915_READ(HTOTAL(cpu_transcoder)));
3001         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3002                    I915_READ(HBLANK(cpu_transcoder)));
3003         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3004                    I915_READ(HSYNC(cpu_transcoder)));
3005
3006         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3007                    I915_READ(VTOTAL(cpu_transcoder)));
3008         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3009                    I915_READ(VBLANK(cpu_transcoder)));
3010         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3011                    I915_READ(VSYNC(cpu_transcoder)));
3012         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3013                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3014 }
3015
3016 /*
3017  * Enable PCH resources required for PCH ports:
3018  *   - PCH PLLs
3019  *   - FDI training & RX/TX
3020  *   - update transcoder timings
3021  *   - DP transcoding bits
3022  *   - transcoder
3023  */
3024 static void ironlake_pch_enable(struct drm_crtc *crtc)
3025 {
3026         struct drm_device *dev = crtc->dev;
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029         int pipe = intel_crtc->pipe;
3030         u32 reg, temp;
3031
3032         assert_pch_transcoder_disabled(dev_priv, pipe);
3033
3034         /* Write the TU size bits before fdi link training, so that error
3035          * detection works. */
3036         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3038
3039         /* For PCH output, training FDI link */
3040         dev_priv->display.fdi_link_train(crtc);
3041
3042         /* XXX: pch pll's can be enabled any time before we enable the PCH
3043          * transcoder, and we actually should do this to not upset any PCH
3044          * transcoder that already use the clock when we share it.
3045          *
3046          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047          * unconditionally resets the pll - we need that to have the right LVDS
3048          * enable sequence. */
3049         ironlake_enable_pch_pll(intel_crtc);
3050
3051         if (HAS_PCH_CPT(dev)) {
3052                 u32 sel;
3053
3054                 temp = I915_READ(PCH_DPLL_SEL);
3055                 switch (pipe) {
3056                 default:
3057                 case 0:
3058                         temp |= TRANSA_DPLL_ENABLE;
3059                         sel = TRANSA_DPLLB_SEL;
3060                         break;
3061                 case 1:
3062                         temp |= TRANSB_DPLL_ENABLE;
3063                         sel = TRANSB_DPLLB_SEL;
3064                         break;
3065                 case 2:
3066                         temp |= TRANSC_DPLL_ENABLE;
3067                         sel = TRANSC_DPLLB_SEL;
3068                         break;
3069                 }
3070                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3071                         temp |= sel;
3072                 else
3073                         temp &= ~sel;
3074                 I915_WRITE(PCH_DPLL_SEL, temp);
3075         }
3076
3077         /* set transcoder timing, panel must allow it */
3078         assert_panel_unlocked(dev_priv, pipe);
3079         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3080
3081         intel_fdi_normal_train(crtc);
3082
3083         /* For PCH DP, enable TRANS_DP_CTL */
3084         if (HAS_PCH_CPT(dev) &&
3085             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3086              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3087                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3088                 reg = TRANS_DP_CTL(pipe);
3089                 temp = I915_READ(reg);
3090                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3091                           TRANS_DP_SYNC_MASK |
3092                           TRANS_DP_BPC_MASK);
3093                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3094                          TRANS_DP_ENH_FRAMING);
3095                 temp |= bpc << 9; /* same format but at 11:9 */
3096
3097                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3098                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3099                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3100                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3101
3102                 switch (intel_trans_dp_port_sel(crtc)) {
3103                 case PCH_DP_B:
3104                         temp |= TRANS_DP_PORT_SEL_B;
3105                         break;
3106                 case PCH_DP_C:
3107                         temp |= TRANS_DP_PORT_SEL_C;
3108                         break;
3109                 case PCH_DP_D:
3110                         temp |= TRANS_DP_PORT_SEL_D;
3111                         break;
3112                 default:
3113                         BUG();
3114                 }
3115
3116                 I915_WRITE(reg, temp);
3117         }
3118
3119         ironlake_enable_pch_transcoder(dev_priv, pipe);
3120 }
3121
3122 static void lpt_pch_enable(struct drm_crtc *crtc)
3123 {
3124         struct drm_device *dev = crtc->dev;
3125         struct drm_i915_private *dev_priv = dev->dev_private;
3126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3128
3129         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3130
3131         lpt_program_iclkip(crtc);
3132
3133         /* Set transcoder timing. */
3134         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3135
3136         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3137 }
3138
3139 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3140 {
3141         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3142
3143         if (pll == NULL)
3144                 return;
3145
3146         if (pll->refcount == 0) {
3147                 WARN(1, "bad PCH PLL refcount\n");
3148                 return;
3149         }
3150
3151         --pll->refcount;
3152         intel_crtc->pch_pll = NULL;
3153 }
3154
3155 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3156 {
3157         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3158         struct intel_pch_pll *pll;
3159         int i;
3160
3161         pll = intel_crtc->pch_pll;
3162         if (pll) {
3163                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3164                               intel_crtc->base.base.id, pll->pll_reg);
3165                 goto prepare;
3166         }
3167
3168         if (HAS_PCH_IBX(dev_priv->dev)) {
3169                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3170                 i = intel_crtc->pipe;
3171                 pll = &dev_priv->pch_plls[i];
3172
3173                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3174                               intel_crtc->base.base.id, pll->pll_reg);
3175
3176                 goto found;
3177         }
3178
3179         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3180                 pll = &dev_priv->pch_plls[i];
3181
3182                 /* Only want to check enabled timings first */
3183                 if (pll->refcount == 0)
3184                         continue;
3185
3186                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3187                     fp == I915_READ(pll->fp0_reg)) {
3188                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3189                                       intel_crtc->base.base.id,
3190                                       pll->pll_reg, pll->refcount, pll->active);
3191
3192                         goto found;
3193                 }
3194         }
3195
3196         /* Ok no matching timings, maybe there's a free one? */
3197         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3198                 pll = &dev_priv->pch_plls[i];
3199                 if (pll->refcount == 0) {
3200                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3201                                       intel_crtc->base.base.id, pll->pll_reg);
3202                         goto found;
3203                 }
3204         }
3205
3206         return NULL;
3207
3208 found:
3209         intel_crtc->pch_pll = pll;
3210         pll->refcount++;
3211         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3212 prepare: /* separate function? */
3213         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3214
3215         /* Wait for the clocks to stabilize before rewriting the regs */
3216         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3217         POSTING_READ(pll->pll_reg);
3218         udelay(150);
3219
3220         I915_WRITE(pll->fp0_reg, fp);
3221         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3222         pll->on = false;
3223         return pll;
3224 }
3225
3226 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3227 {
3228         struct drm_i915_private *dev_priv = dev->dev_private;
3229         int dslreg = PIPEDSL(pipe);
3230         u32 temp;
3231
3232         temp = I915_READ(dslreg);
3233         udelay(500);
3234         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3235                 if (wait_for(I915_READ(dslreg) != temp, 5))
3236                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3237         }
3238 }
3239
3240 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3241 {
3242         struct drm_device *dev = crtc->base.dev;
3243         struct drm_i915_private *dev_priv = dev->dev_private;
3244         int pipe = crtc->pipe;
3245
3246         if (crtc->config.pch_pfit.size) {
3247                 /* Force use of hard-coded filter coefficients
3248                  * as some pre-programmed values are broken,
3249                  * e.g. x201.
3250                  */
3251                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3252                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3253                                                  PF_PIPE_SEL_IVB(pipe));
3254                 else
3255                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3256                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3257                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3258         }
3259 }
3260
3261 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3262 {
3263         struct drm_device *dev = crtc->dev;
3264         struct drm_i915_private *dev_priv = dev->dev_private;
3265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3266         struct intel_encoder *encoder;
3267         int pipe = intel_crtc->pipe;
3268         int plane = intel_crtc->plane;
3269         u32 temp;
3270
3271         WARN_ON(!crtc->enabled);
3272
3273         if (intel_crtc->active)
3274                 return;
3275
3276         intel_crtc->active = true;
3277
3278         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3279         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3280
3281         intel_update_watermarks(dev);
3282
3283         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3284                 temp = I915_READ(PCH_LVDS);
3285                 if ((temp & LVDS_PORT_EN) == 0)
3286                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3287         }
3288
3289
3290         if (intel_crtc->config.has_pch_encoder) {
3291                 /* Note: FDI PLL enabling _must_ be done before we enable the
3292                  * cpu pipes, hence this is separate from all the other fdi/pch
3293                  * enabling. */
3294                 ironlake_fdi_pll_enable(intel_crtc);
3295         } else {
3296                 assert_fdi_tx_disabled(dev_priv, pipe);
3297                 assert_fdi_rx_disabled(dev_priv, pipe);
3298         }
3299
3300         for_each_encoder_on_crtc(dev, crtc, encoder)
3301                 if (encoder->pre_enable)
3302                         encoder->pre_enable(encoder);
3303
3304         /* Enable panel fitting for LVDS */
3305         ironlake_pfit_enable(intel_crtc);
3306
3307         /*
3308          * On ILK+ LUT must be loaded before the pipe is running but with
3309          * clocks enabled
3310          */
3311         intel_crtc_load_lut(crtc);
3312
3313         intel_enable_pipe(dev_priv, pipe,
3314                           intel_crtc->config.has_pch_encoder);
3315         intel_enable_plane(dev_priv, plane, pipe);
3316
3317         if (intel_crtc->config.has_pch_encoder)
3318                 ironlake_pch_enable(crtc);
3319
3320         mutex_lock(&dev->struct_mutex);
3321         intel_update_fbc(dev);
3322         mutex_unlock(&dev->struct_mutex);
3323
3324         intel_crtc_update_cursor(crtc, true);
3325
3326         for_each_encoder_on_crtc(dev, crtc, encoder)
3327                 encoder->enable(encoder);
3328
3329         if (HAS_PCH_CPT(dev))
3330                 cpt_verify_modeset(dev, intel_crtc->pipe);
3331
3332         /*
3333          * There seems to be a race in PCH platform hw (at least on some
3334          * outputs) where an enabled pipe still completes any pageflip right
3335          * away (as if the pipe is off) instead of waiting for vblank. As soon
3336          * as the first vblank happend, everything works as expected. Hence just
3337          * wait for one vblank before returning to avoid strange things
3338          * happening.
3339          */
3340         intel_wait_for_vblank(dev, intel_crtc->pipe);
3341 }
3342
3343 static void haswell_crtc_enable(struct drm_crtc *crtc)
3344 {
3345         struct drm_device *dev = crtc->dev;
3346         struct drm_i915_private *dev_priv = dev->dev_private;
3347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348         struct intel_encoder *encoder;
3349         int pipe = intel_crtc->pipe;
3350         int plane = intel_crtc->plane;
3351
3352         WARN_ON(!crtc->enabled);
3353
3354         if (intel_crtc->active)
3355                 return;
3356
3357         intel_crtc->active = true;
3358
3359         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3360         if (intel_crtc->config.has_pch_encoder)
3361                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3362
3363         intel_update_watermarks(dev);
3364
3365         if (intel_crtc->config.has_pch_encoder)
3366                 dev_priv->display.fdi_link_train(crtc);
3367
3368         for_each_encoder_on_crtc(dev, crtc, encoder)
3369                 if (encoder->pre_enable)
3370                         encoder->pre_enable(encoder);
3371
3372         intel_ddi_enable_pipe_clock(intel_crtc);
3373
3374         /* Enable panel fitting for eDP */
3375         ironlake_pfit_enable(intel_crtc);
3376
3377         /*
3378          * On ILK+ LUT must be loaded before the pipe is running but with
3379          * clocks enabled
3380          */
3381         intel_crtc_load_lut(crtc);
3382
3383         intel_ddi_set_pipe_settings(crtc);
3384         intel_ddi_enable_transcoder_func(crtc);
3385
3386         intel_enable_pipe(dev_priv, pipe,
3387                           intel_crtc->config.has_pch_encoder);
3388         intel_enable_plane(dev_priv, plane, pipe);
3389
3390         if (intel_crtc->config.has_pch_encoder)
3391                 lpt_pch_enable(crtc);
3392
3393         mutex_lock(&dev->struct_mutex);
3394         intel_update_fbc(dev);
3395         mutex_unlock(&dev->struct_mutex);
3396
3397         intel_crtc_update_cursor(crtc, true);
3398
3399         for_each_encoder_on_crtc(dev, crtc, encoder)
3400                 encoder->enable(encoder);
3401
3402         /*
3403          * There seems to be a race in PCH platform hw (at least on some
3404          * outputs) where an enabled pipe still completes any pageflip right
3405          * away (as if the pipe is off) instead of waiting for vblank. As soon
3406          * as the first vblank happend, everything works as expected. Hence just
3407          * wait for one vblank before returning to avoid strange things
3408          * happening.
3409          */
3410         intel_wait_for_vblank(dev, intel_crtc->pipe);
3411 }
3412
3413 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3414 {
3415         struct drm_device *dev = crtc->base.dev;
3416         struct drm_i915_private *dev_priv = dev->dev_private;
3417         int pipe = crtc->pipe;
3418
3419         /* To avoid upsetting the power well on haswell only disable the pfit if
3420          * it's in use. The hw state code will make sure we get this right. */
3421         if (crtc->config.pch_pfit.size) {
3422                 I915_WRITE(PF_CTL(pipe), 0);
3423                 I915_WRITE(PF_WIN_POS(pipe), 0);
3424                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3425         }
3426 }
3427
3428 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3429 {
3430         struct drm_device *dev = crtc->dev;
3431         struct drm_i915_private *dev_priv = dev->dev_private;
3432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433         struct intel_encoder *encoder;
3434         int pipe = intel_crtc->pipe;
3435         int plane = intel_crtc->plane;
3436         u32 reg, temp;
3437
3438
3439         if (!intel_crtc->active)
3440                 return;
3441
3442         for_each_encoder_on_crtc(dev, crtc, encoder)
3443                 encoder->disable(encoder);
3444
3445         intel_crtc_wait_for_pending_flips(crtc);
3446         drm_vblank_off(dev, pipe);
3447         intel_crtc_update_cursor(crtc, false);
3448
3449         intel_disable_plane(dev_priv, plane, pipe);
3450
3451         if (dev_priv->cfb_plane == plane)
3452                 intel_disable_fbc(dev);
3453
3454         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3455         intel_disable_pipe(dev_priv, pipe);
3456
3457         ironlake_pfit_disable(intel_crtc);
3458
3459         for_each_encoder_on_crtc(dev, crtc, encoder)
3460                 if (encoder->post_disable)
3461                         encoder->post_disable(encoder);
3462
3463         ironlake_fdi_disable(crtc);
3464
3465         ironlake_disable_pch_transcoder(dev_priv, pipe);
3466         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3467
3468         if (HAS_PCH_CPT(dev)) {
3469                 /* disable TRANS_DP_CTL */
3470                 reg = TRANS_DP_CTL(pipe);
3471                 temp = I915_READ(reg);
3472                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3473                 temp |= TRANS_DP_PORT_SEL_NONE;
3474                 I915_WRITE(reg, temp);
3475
3476                 /* disable DPLL_SEL */
3477                 temp = I915_READ(PCH_DPLL_SEL);
3478                 switch (pipe) {
3479                 case 0:
3480                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3481                         break;
3482                 case 1:
3483                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3484                         break;
3485                 case 2:
3486                         /* C shares PLL A or B */
3487                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3488                         break;
3489                 default:
3490                         BUG(); /* wtf */
3491                 }
3492                 I915_WRITE(PCH_DPLL_SEL, temp);
3493         }
3494
3495         /* disable PCH DPLL */
3496         intel_disable_pch_pll(intel_crtc);
3497
3498         ironlake_fdi_pll_disable(intel_crtc);
3499
3500         intel_crtc->active = false;
3501         intel_update_watermarks(dev);
3502
3503         mutex_lock(&dev->struct_mutex);
3504         intel_update_fbc(dev);
3505         mutex_unlock(&dev->struct_mutex);
3506 }
3507
3508 static void haswell_crtc_disable(struct drm_crtc *crtc)
3509 {
3510         struct drm_device *dev = crtc->dev;
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513         struct intel_encoder *encoder;
3514         int pipe = intel_crtc->pipe;
3515         int plane = intel_crtc->plane;
3516         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3517
3518         if (!intel_crtc->active)
3519                 return;
3520
3521         for_each_encoder_on_crtc(dev, crtc, encoder)
3522                 encoder->disable(encoder);
3523
3524         intel_crtc_wait_for_pending_flips(crtc);
3525         drm_vblank_off(dev, pipe);
3526         intel_crtc_update_cursor(crtc, false);
3527
3528         /* FBC must be disabled before disabling the plane on HSW. */
3529         if (dev_priv->cfb_plane == plane)
3530                 intel_disable_fbc(dev);
3531
3532         intel_disable_plane(dev_priv, plane, pipe);
3533
3534         if (intel_crtc->config.has_pch_encoder)
3535                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3536         intel_disable_pipe(dev_priv, pipe);
3537
3538         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3539
3540         ironlake_pfit_disable(intel_crtc);
3541
3542         intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544         for_each_encoder_on_crtc(dev, crtc, encoder)
3545                 if (encoder->post_disable)
3546                         encoder->post_disable(encoder);
3547
3548         if (intel_crtc->config.has_pch_encoder) {
3549                 lpt_disable_pch_transcoder(dev_priv);
3550                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3551                 intel_ddi_fdi_disable(crtc);
3552         }
3553
3554         intel_crtc->active = false;
3555         intel_update_watermarks(dev);
3556
3557         mutex_lock(&dev->struct_mutex);
3558         intel_update_fbc(dev);
3559         mutex_unlock(&dev->struct_mutex);
3560 }
3561
3562 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 {
3564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565         intel_put_pch_pll(intel_crtc);
3566 }
3567
3568 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 {
3570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571
3572         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3573          * start using it. */
3574         intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3575
3576         intel_ddi_put_crtc_pll(crtc);
3577 }
3578
3579 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 {
3581         if (!enable && intel_crtc->overlay) {
3582                 struct drm_device *dev = intel_crtc->base.dev;
3583                 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585                 mutex_lock(&dev->struct_mutex);
3586                 dev_priv->mm.interruptible = false;
3587                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588                 dev_priv->mm.interruptible = true;
3589                 mutex_unlock(&dev->struct_mutex);
3590         }
3591
3592         /* Let userspace switch the overlay on again. In most cases userspace
3593          * has to recompute where to put it anyway.
3594          */
3595 }
3596
3597 /**
3598  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599  * cursor plane briefly if not already running after enabling the display
3600  * plane.
3601  * This workaround avoids occasional blank screens when self refresh is
3602  * enabled.
3603  */
3604 static void
3605 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606 {
3607         u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609         if ((cntl & CURSOR_MODE) == 0) {
3610                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614                 intel_wait_for_vblank(dev_priv->dev, pipe);
3615                 I915_WRITE(CURCNTR(pipe), cntl);
3616                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618         }
3619 }
3620
3621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->base.dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc_config *pipe_config = &crtc->config;
3626
3627         if (!crtc->config.gmch_pfit.control)
3628                 return;
3629
3630         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631         assert_pipe_disabled(dev_priv, crtc->pipe);
3632
3633         /*
3634          * Enable automatic panel scaling so that non-native modes
3635          * fill the screen.  The panel fitter should only be
3636          * adjusted whilst the pipe is disabled, according to
3637          * register description and PRM.
3638          */
3639         DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3640                       pipe_config->gmch_pfit.control,
3641                       pipe_config->gmch_pfit.pgm_ratios);
3642
3643         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3645
3646         /* Border color in case we don't scale up to the full screen. Black by
3647          * default, change to something else for debugging. */
3648         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3649 }
3650
3651 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3652 {
3653         struct drm_device *dev = crtc->dev;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656         struct intel_encoder *encoder;
3657         int pipe = intel_crtc->pipe;
3658         int plane = intel_crtc->plane;
3659
3660         WARN_ON(!crtc->enabled);
3661
3662         if (intel_crtc->active)
3663                 return;
3664
3665         intel_crtc->active = true;
3666         intel_update_watermarks(dev);
3667
3668         mutex_lock(&dev_priv->dpio_lock);
3669
3670         for_each_encoder_on_crtc(dev, crtc, encoder)
3671                 if (encoder->pre_pll_enable)
3672                         encoder->pre_pll_enable(encoder);
3673
3674         intel_enable_pll(dev_priv, pipe);
3675
3676         for_each_encoder_on_crtc(dev, crtc, encoder)
3677                 if (encoder->pre_enable)
3678                         encoder->pre_enable(encoder);
3679
3680         /* VLV wants encoder enabling _before_ the pipe is up. */
3681         for_each_encoder_on_crtc(dev, crtc, encoder)
3682                 encoder->enable(encoder);
3683
3684         /* Enable panel fitting for eDP */
3685         i9xx_pfit_enable(intel_crtc);
3686
3687         intel_enable_pipe(dev_priv, pipe, false);
3688         intel_enable_plane(dev_priv, plane, pipe);
3689
3690         intel_crtc_load_lut(crtc);
3691         intel_update_fbc(dev);
3692
3693         /* Give the overlay scaler a chance to enable if it's on this pipe */
3694         intel_crtc_dpms_overlay(intel_crtc, true);
3695         intel_crtc_update_cursor(crtc, true);
3696
3697         mutex_unlock(&dev_priv->dpio_lock);
3698 }
3699
3700 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3701 {
3702         struct drm_device *dev = crtc->dev;
3703         struct drm_i915_private *dev_priv = dev->dev_private;
3704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705         struct intel_encoder *encoder;
3706         int pipe = intel_crtc->pipe;
3707         int plane = intel_crtc->plane;
3708
3709         WARN_ON(!crtc->enabled);
3710
3711         if (intel_crtc->active)
3712                 return;
3713
3714         intel_crtc->active = true;
3715         intel_update_watermarks(dev);
3716
3717         intel_enable_pll(dev_priv, pipe);
3718
3719         for_each_encoder_on_crtc(dev, crtc, encoder)
3720                 if (encoder->pre_enable)
3721                         encoder->pre_enable(encoder);
3722
3723         /* Enable panel fitting for LVDS */
3724         i9xx_pfit_enable(intel_crtc);
3725
3726         intel_enable_pipe(dev_priv, pipe, false);
3727         intel_enable_plane(dev_priv, plane, pipe);
3728         if (IS_G4X(dev))
3729                 g4x_fixup_plane(dev_priv, pipe);
3730
3731         intel_crtc_load_lut(crtc);
3732         intel_update_fbc(dev);
3733
3734         /* Give the overlay scaler a chance to enable if it's on this pipe */
3735         intel_crtc_dpms_overlay(intel_crtc, true);
3736         intel_crtc_update_cursor(crtc, true);
3737
3738         for_each_encoder_on_crtc(dev, crtc, encoder)
3739                 encoder->enable(encoder);
3740 }
3741
3742 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3743 {
3744         struct drm_device *dev = crtc->base.dev;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746
3747         if (!crtc->config.gmch_pfit.control)
3748                 return;
3749
3750         assert_pipe_disabled(dev_priv, crtc->pipe);
3751
3752         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3753                          I915_READ(PFIT_CONTROL));
3754         I915_WRITE(PFIT_CONTROL, 0);
3755 }
3756
3757 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3758 {
3759         struct drm_device *dev = crtc->dev;
3760         struct drm_i915_private *dev_priv = dev->dev_private;
3761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762         struct intel_encoder *encoder;
3763         int pipe = intel_crtc->pipe;
3764         int plane = intel_crtc->plane;
3765
3766         if (!intel_crtc->active)
3767                 return;
3768
3769         for_each_encoder_on_crtc(dev, crtc, encoder)
3770                 encoder->disable(encoder);
3771
3772         /* Give the overlay scaler a chance to disable if it's on this pipe */
3773         intel_crtc_wait_for_pending_flips(crtc);
3774         drm_vblank_off(dev, pipe);
3775         intel_crtc_dpms_overlay(intel_crtc, false);
3776         intel_crtc_update_cursor(crtc, false);
3777
3778         if (dev_priv->cfb_plane == plane)
3779                 intel_disable_fbc(dev);
3780
3781         intel_disable_plane(dev_priv, plane, pipe);
3782         intel_disable_pipe(dev_priv, pipe);
3783
3784         i9xx_pfit_disable(intel_crtc);
3785
3786         for_each_encoder_on_crtc(dev, crtc, encoder)
3787                 if (encoder->post_disable)
3788                         encoder->post_disable(encoder);
3789
3790         intel_disable_pll(dev_priv, pipe);
3791
3792         intel_crtc->active = false;
3793         intel_update_fbc(dev);
3794         intel_update_watermarks(dev);
3795 }
3796
3797 static void i9xx_crtc_off(struct drm_crtc *crtc)
3798 {
3799 }
3800
3801 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3802                                     bool enabled)
3803 {
3804         struct drm_device *dev = crtc->dev;
3805         struct drm_i915_master_private *master_priv;
3806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807         int pipe = intel_crtc->pipe;
3808
3809         if (!dev->primary->master)
3810                 return;
3811
3812         master_priv = dev->primary->master->driver_priv;
3813         if (!master_priv->sarea_priv)
3814                 return;
3815
3816         switch (pipe) {
3817         case 0:
3818                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3819                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3820                 break;
3821         case 1:
3822                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3823                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3824                 break;
3825         default:
3826                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3827                 break;
3828         }
3829 }
3830
3831 /**
3832  * Sets the power management mode of the pipe and plane.
3833  */
3834 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3835 {
3836         struct drm_device *dev = crtc->dev;
3837         struct drm_i915_private *dev_priv = dev->dev_private;
3838         struct intel_encoder *intel_encoder;
3839         bool enable = false;
3840
3841         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3842                 enable |= intel_encoder->connectors_active;
3843
3844         if (enable)
3845                 dev_priv->display.crtc_enable(crtc);
3846         else
3847                 dev_priv->display.crtc_disable(crtc);
3848
3849         intel_crtc_update_sarea(crtc, enable);
3850 }
3851
3852 static void intel_crtc_disable(struct drm_crtc *crtc)
3853 {
3854         struct drm_device *dev = crtc->dev;
3855         struct drm_connector *connector;
3856         struct drm_i915_private *dev_priv = dev->dev_private;
3857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3858
3859         /* crtc should still be enabled when we disable it. */
3860         WARN_ON(!crtc->enabled);
3861
3862         dev_priv->display.crtc_disable(crtc);
3863         intel_crtc->eld_vld = false;
3864         intel_crtc_update_sarea(crtc, false);
3865         dev_priv->display.off(crtc);
3866
3867         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3868         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3869
3870         if (crtc->fb) {
3871                 mutex_lock(&dev->struct_mutex);
3872                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3873                 mutex_unlock(&dev->struct_mutex);
3874                 crtc->fb = NULL;
3875         }
3876
3877         /* Update computed state. */
3878         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3879                 if (!connector->encoder || !connector->encoder->crtc)
3880                         continue;
3881
3882                 if (connector->encoder->crtc != crtc)
3883                         continue;
3884
3885                 connector->dpms = DRM_MODE_DPMS_OFF;
3886                 to_intel_encoder(connector->encoder)->connectors_active = false;
3887         }
3888 }
3889
3890 void intel_modeset_disable(struct drm_device *dev)
3891 {
3892         struct drm_crtc *crtc;
3893
3894         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3895                 if (crtc->enabled)
3896                         intel_crtc_disable(crtc);
3897         }
3898 }
3899
3900 void intel_encoder_destroy(struct drm_encoder *encoder)
3901 {
3902         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3903
3904         drm_encoder_cleanup(encoder);
3905         kfree(intel_encoder);
3906 }
3907
3908 /* Simple dpms helper for encodres with just one connector, no cloning and only
3909  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3910  * state of the entire output pipe. */
3911 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3912 {
3913         if (mode == DRM_MODE_DPMS_ON) {
3914                 encoder->connectors_active = true;
3915
3916                 intel_crtc_update_dpms(encoder->base.crtc);
3917         } else {
3918                 encoder->connectors_active = false;
3919
3920                 intel_crtc_update_dpms(encoder->base.crtc);
3921         }
3922 }
3923
3924 /* Cross check the actual hw state with our own modeset state tracking (and it's
3925  * internal consistency). */
3926 static void intel_connector_check_state(struct intel_connector *connector)
3927 {
3928         if (connector->get_hw_state(connector)) {
3929                 struct intel_encoder *encoder = connector->encoder;
3930                 struct drm_crtc *crtc;
3931                 bool encoder_enabled;
3932                 enum pipe pipe;
3933
3934                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3935                               connector->base.base.id,
3936                               drm_get_connector_name(&connector->base));
3937
3938                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3939                      "wrong connector dpms state\n");
3940                 WARN(connector->base.encoder != &encoder->base,
3941                      "active connector not linked to encoder\n");
3942                 WARN(!encoder->connectors_active,
3943                      "encoder->connectors_active not set\n");
3944
3945                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3946                 WARN(!encoder_enabled, "encoder not enabled\n");
3947                 if (WARN_ON(!encoder->base.crtc))
3948                         return;
3949
3950                 crtc = encoder->base.crtc;
3951
3952                 WARN(!crtc->enabled, "crtc not enabled\n");
3953                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3954                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3955                      "encoder active on the wrong pipe\n");
3956         }
3957 }
3958
3959 /* Even simpler default implementation, if there's really no special case to
3960  * consider. */
3961 void intel_connector_dpms(struct drm_connector *connector, int mode)
3962 {
3963         struct intel_encoder *encoder = intel_attached_encoder(connector);
3964
3965         /* All the simple cases only support two dpms states. */
3966         if (mode != DRM_MODE_DPMS_ON)
3967                 mode = DRM_MODE_DPMS_OFF;
3968
3969         if (mode == connector->dpms)
3970                 return;
3971
3972         connector->dpms = mode;
3973
3974         /* Only need to change hw state when actually enabled */
3975         if (encoder->base.crtc)
3976                 intel_encoder_dpms(encoder, mode);
3977         else
3978                 WARN_ON(encoder->connectors_active != false);
3979
3980         intel_modeset_check_state(connector->dev);
3981 }
3982
3983 /* Simple connector->get_hw_state implementation for encoders that support only
3984  * one connector and no cloning and hence the encoder state determines the state
3985  * of the connector. */
3986 bool intel_connector_get_hw_state(struct intel_connector *connector)
3987 {
3988         enum pipe pipe = 0;
3989         struct intel_encoder *encoder = connector->encoder;
3990
3991         return encoder->get_hw_state(encoder, &pipe);
3992 }
3993
3994 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3995                                      struct intel_crtc_config *pipe_config)
3996 {
3997         struct drm_i915_private *dev_priv = dev->dev_private;
3998         struct intel_crtc *pipe_B_crtc =
3999                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4000
4001         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4002                       pipe_name(pipe), pipe_config->fdi_lanes);
4003         if (pipe_config->fdi_lanes > 4) {
4004                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4005                               pipe_name(pipe), pipe_config->fdi_lanes);
4006                 return false;
4007         }
4008
4009         if (IS_HASWELL(dev)) {
4010                 if (pipe_config->fdi_lanes > 2) {
4011                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4012                                       pipe_config->fdi_lanes);
4013                         return false;
4014                 } else {
4015                         return true;
4016                 }
4017         }
4018
4019         if (INTEL_INFO(dev)->num_pipes == 2)
4020                 return true;
4021
4022         /* Ivybridge 3 pipe is really complicated */
4023         switch (pipe) {
4024         case PIPE_A:
4025                 return true;
4026         case PIPE_B:
4027                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4028                     pipe_config->fdi_lanes > 2) {
4029                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030                                       pipe_name(pipe), pipe_config->fdi_lanes);
4031                         return false;
4032                 }
4033                 return true;
4034         case PIPE_C:
4035                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4036                     pipe_B_crtc->config.fdi_lanes <= 2) {
4037                         if (pipe_config->fdi_lanes > 2) {
4038                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4039                                               pipe_name(pipe), pipe_config->fdi_lanes);
4040                                 return false;
4041                         }
4042                 } else {
4043                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4044                         return false;
4045                 }
4046                 return true;
4047         default:
4048                 BUG();
4049         }
4050 }
4051
4052 #define RETRY 1
4053 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4054                                        struct intel_crtc_config *pipe_config)
4055 {
4056         struct drm_device *dev = intel_crtc->base.dev;
4057         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4058         int target_clock, lane, link_bw;
4059         bool setup_ok, needs_recompute = false;
4060
4061 retry:
4062         /* FDI is a binary signal running at ~2.7GHz, encoding
4063          * each output octet as 10 bits. The actual frequency
4064          * is stored as a divider into a 100MHz clock, and the
4065          * mode pixel clock is stored in units of 1KHz.
4066          * Hence the bw of each lane in terms of the mode signal
4067          * is:
4068          */
4069         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4070
4071         if (pipe_config->pixel_target_clock)
4072                 target_clock = pipe_config->pixel_target_clock;
4073         else
4074                 target_clock = adjusted_mode->clock;
4075
4076         lane = ironlake_get_lanes_required(target_clock, link_bw,
4077                                            pipe_config->pipe_bpp);
4078
4079         pipe_config->fdi_lanes = lane;
4080
4081         if (pipe_config->pixel_multiplier > 1)
4082                 link_bw *= pipe_config->pixel_multiplier;
4083         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4084                                link_bw, &pipe_config->fdi_m_n);
4085
4086         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4087                                             intel_crtc->pipe, pipe_config);
4088         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4089                 pipe_config->pipe_bpp -= 2*3;
4090                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4091                               pipe_config->pipe_bpp);
4092                 needs_recompute = true;
4093                 pipe_config->bw_constrained = true;
4094
4095                 goto retry;
4096         }
4097
4098         if (needs_recompute)
4099                 return RETRY;
4100
4101         return setup_ok ? 0 : -EINVAL;
4102 }
4103
4104 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4105                                      struct intel_crtc_config *pipe_config)
4106 {
4107         struct drm_device *dev = crtc->dev;
4108         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4109
4110         if (HAS_PCH_SPLIT(dev)) {
4111                 /* FDI link clock is fixed at 2.7G */
4112                 if (pipe_config->requested_mode.clock * 3
4113                     > IRONLAKE_FDI_FREQ * 4)
4114                         return -EINVAL;
4115         }
4116
4117         /* All interlaced capable intel hw wants timings in frames. Note though
4118          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4119          * timings, so we need to be careful not to clobber these.*/
4120         if (!pipe_config->timings_set)
4121                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4122
4123         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4124          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4125          */
4126         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4127                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4128                 return -EINVAL;
4129
4130         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4131                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4132         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4133                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4134                  * for lvds. */
4135                 pipe_config->pipe_bpp = 8*3;
4136         }
4137
4138         if (pipe_config->has_pch_encoder)
4139                 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4140
4141         return 0;
4142 }
4143
4144 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4145 {
4146         return 400000; /* FIXME */
4147 }
4148
4149 static int i945_get_display_clock_speed(struct drm_device *dev)
4150 {
4151         return 400000;
4152 }
4153
4154 static int i915_get_display_clock_speed(struct drm_device *dev)
4155 {
4156         return 333000;
4157 }
4158
4159 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4160 {
4161         return 200000;
4162 }
4163
4164 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4165 {
4166         u16 gcfgc = 0;
4167
4168         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4169
4170         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4171                 return 133000;
4172         else {
4173                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4174                 case GC_DISPLAY_CLOCK_333_MHZ:
4175                         return 333000;
4176                 default:
4177                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4178                         return 190000;
4179                 }
4180         }
4181 }
4182
4183 static int i865_get_display_clock_speed(struct drm_device *dev)
4184 {
4185         return 266000;
4186 }
4187
4188 static int i855_get_display_clock_speed(struct drm_device *dev)
4189 {
4190         u16 hpllcc = 0;
4191         /* Assume that the hardware is in the high speed state.  This
4192          * should be the default.
4193          */
4194         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4195         case GC_CLOCK_133_200:
4196         case GC_CLOCK_100_200:
4197                 return 200000;
4198         case GC_CLOCK_166_250:
4199                 return 250000;
4200         case GC_CLOCK_100_133:
4201                 return 133000;
4202         }
4203
4204         /* Shouldn't happen */
4205         return 0;
4206 }
4207
4208 static int i830_get_display_clock_speed(struct drm_device *dev)
4209 {
4210         return 133000;
4211 }
4212
4213 static void
4214 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4215 {
4216         while (*num > DATA_LINK_M_N_MASK ||
4217                *den > DATA_LINK_M_N_MASK) {
4218                 *num >>= 1;
4219                 *den >>= 1;
4220         }
4221 }
4222
4223 static void compute_m_n(unsigned int m, unsigned int n,
4224                         uint32_t *ret_m, uint32_t *ret_n)
4225 {
4226         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4227         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4228         intel_reduce_m_n_ratio(ret_m, ret_n);
4229 }
4230
4231 void
4232 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4233                        int pixel_clock, int link_clock,
4234                        struct intel_link_m_n *m_n)
4235 {
4236         m_n->tu = 64;
4237
4238         compute_m_n(bits_per_pixel * pixel_clock,
4239                     link_clock * nlanes * 8,
4240                     &m_n->gmch_m, &m_n->gmch_n);
4241
4242         compute_m_n(pixel_clock, link_clock,
4243                     &m_n->link_m, &m_n->link_n);
4244 }
4245
4246 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4247 {
4248         if (i915_panel_use_ssc >= 0)
4249                 return i915_panel_use_ssc != 0;
4250         return dev_priv->vbt.lvds_use_ssc
4251                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4252 }
4253
4254 static int vlv_get_refclk(struct drm_crtc *crtc)
4255 {
4256         struct drm_device *dev = crtc->dev;
4257         struct drm_i915_private *dev_priv = dev->dev_private;
4258         int refclk = 27000; /* for DP & HDMI */
4259
4260         return 100000; /* only one validated so far */
4261
4262         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4263                 refclk = 96000;
4264         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4265                 if (intel_panel_use_ssc(dev_priv))
4266                         refclk = 100000;
4267                 else
4268                         refclk = 96000;
4269         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4270                 refclk = 100000;
4271         }
4272
4273         return refclk;
4274 }
4275
4276 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4277 {
4278         struct drm_device *dev = crtc->dev;
4279         struct drm_i915_private *dev_priv = dev->dev_private;
4280         int refclk;
4281
4282         if (IS_VALLEYVIEW(dev)) {
4283                 refclk = vlv_get_refclk(crtc);
4284         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4285             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4286                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4287                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4288                               refclk / 1000);
4289         } else if (!IS_GEN2(dev)) {
4290                 refclk = 96000;
4291         } else {
4292                 refclk = 48000;
4293         }
4294
4295         return refclk;
4296 }
4297
4298 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4299 {
4300         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4301 }
4302
4303 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4304 {
4305         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4306 }
4307
4308 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4309                                      intel_clock_t *reduced_clock)
4310 {
4311         struct drm_device *dev = crtc->base.dev;
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         int pipe = crtc->pipe;
4314         u32 fp, fp2 = 0;
4315
4316         if (IS_PINEVIEW(dev)) {
4317                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4318                 if (reduced_clock)
4319                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4320         } else {
4321                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4322                 if (reduced_clock)
4323                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4324         }
4325
4326         I915_WRITE(FP0(pipe), fp);
4327
4328         crtc->lowfreq_avail = false;
4329         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4330             reduced_clock && i915_powersave) {
4331                 I915_WRITE(FP1(pipe), fp2);
4332                 crtc->lowfreq_avail = true;
4333         } else {
4334                 I915_WRITE(FP1(pipe), fp);
4335         }
4336 }
4337
4338 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4339 {
4340         u32 reg_val;
4341
4342         /*
4343          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4344          * and set it to a reasonable value instead.
4345          */
4346         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4347         reg_val &= 0xffffff00;
4348         reg_val |= 0x00000030;
4349         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4350
4351         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4352         reg_val &= 0x8cffffff;
4353         reg_val = 0x8c000000;
4354         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4355
4356         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4357         reg_val &= 0xffffff00;
4358         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4359
4360         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4361         reg_val &= 0x00ffffff;
4362         reg_val |= 0xb0000000;
4363         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4364 }
4365
4366 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4367                                          struct intel_link_m_n *m_n)
4368 {
4369         struct drm_device *dev = crtc->base.dev;
4370         struct drm_i915_private *dev_priv = dev->dev_private;
4371         int pipe = crtc->pipe;
4372
4373         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4374         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4375         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4376         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4377 }
4378
4379 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4380                                          struct intel_link_m_n *m_n)
4381 {
4382         struct drm_device *dev = crtc->base.dev;
4383         struct drm_i915_private *dev_priv = dev->dev_private;
4384         int pipe = crtc->pipe;
4385         enum transcoder transcoder = crtc->config.cpu_transcoder;
4386
4387         if (INTEL_INFO(dev)->gen >= 5) {
4388                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4389                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4390                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4391                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4392         } else {
4393                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4394                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4395                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4396                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4397         }
4398 }
4399
4400 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4401 {
4402         if (crtc->config.has_pch_encoder)
4403                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4404         else
4405                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4406 }
4407
4408 static void vlv_update_pll(struct intel_crtc *crtc)
4409 {
4410         struct drm_device *dev = crtc->base.dev;
4411         struct drm_i915_private *dev_priv = dev->dev_private;
4412         struct drm_display_mode *adjusted_mode =
4413                 &crtc->config.adjusted_mode;
4414         struct intel_encoder *encoder;
4415         int pipe = crtc->pipe;
4416         u32 dpll, mdiv;
4417         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4418         bool is_hdmi;
4419         u32 coreclk, reg_val, dpll_md;
4420
4421         mutex_lock(&dev_priv->dpio_lock);
4422
4423         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4424
4425         bestn = crtc->config.dpll.n;
4426         bestm1 = crtc->config.dpll.m1;
4427         bestm2 = crtc->config.dpll.m2;
4428         bestp1 = crtc->config.dpll.p1;
4429         bestp2 = crtc->config.dpll.p2;
4430
4431         /* See eDP HDMI DPIO driver vbios notes doc */
4432
4433         /* PLL B needs special handling */
4434         if (pipe)
4435                 vlv_pllb_recal_opamp(dev_priv);
4436
4437         /* Set up Tx target for periodic Rcomp update */
4438         intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4439
4440         /* Disable target IRef on PLL */
4441         reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4442         reg_val &= 0x00ffffff;
4443         intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4444
4445         /* Disable fast lock */
4446         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4447
4448         /* Set idtafcrecal before PLL is enabled */
4449         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4450         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4451         mdiv |= ((bestn << DPIO_N_SHIFT));
4452         mdiv |= (1 << DPIO_K_SHIFT);
4453
4454         /*
4455          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4456          * but we don't support that).
4457          * Note: don't use the DAC post divider as it seems unstable.
4458          */
4459         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4460         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4461
4462         mdiv |= DPIO_ENABLE_CALIBRATION;
4463         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4464
4465         /* Set HBR and RBR LPF coefficients */
4466         if (adjusted_mode->clock == 162000 ||
4467             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4468                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4469                                  0x005f0021);
4470         else
4471                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4472                                  0x00d0000f);
4473
4474         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4475             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4476                 /* Use SSC source */
4477                 if (!pipe)
4478                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4479                                          0x0df40000);
4480                 else
4481                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4482                                          0x0df70000);
4483         } else { /* HDMI or VGA */
4484                 /* Use bend source */
4485                 if (!pipe)
4486                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4487                                          0x0df70000);
4488                 else
4489                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4490                                          0x0df40000);
4491         }
4492
4493         coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4494         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4495         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4496             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4497                 coreclk |= 0x01000000;
4498         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4499
4500         intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4501
4502         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4503                 if (encoder->pre_pll_enable)
4504                         encoder->pre_pll_enable(encoder);
4505
4506         /* Enable DPIO clock input */
4507         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4508                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4509         if (pipe)
4510                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4511
4512         dpll |= DPLL_VCO_ENABLE;
4513         I915_WRITE(DPLL(pipe), dpll);
4514         POSTING_READ(DPLL(pipe));
4515         udelay(150);
4516
4517         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4518                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4519
4520         dpll_md = 0;
4521         if (crtc->config.pixel_multiplier > 1) {
4522                 dpll_md = (crtc->config.pixel_multiplier - 1)
4523                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4524         }
4525         I915_WRITE(DPLL_MD(pipe), dpll_md);
4526         POSTING_READ(DPLL_MD(pipe));
4527
4528         if (crtc->config.has_dp_encoder)
4529                 intel_dp_set_m_n(crtc);
4530
4531         mutex_unlock(&dev_priv->dpio_lock);
4532 }
4533
4534 static void i9xx_update_pll(struct intel_crtc *crtc,
4535                             intel_clock_t *reduced_clock,
4536                             int num_connectors)
4537 {
4538         struct drm_device *dev = crtc->base.dev;
4539         struct drm_i915_private *dev_priv = dev->dev_private;
4540         struct intel_encoder *encoder;
4541         int pipe = crtc->pipe;
4542         u32 dpll;
4543         bool is_sdvo;
4544         struct dpll *clock = &crtc->config.dpll;
4545
4546         i9xx_update_pll_dividers(crtc, reduced_clock);
4547
4548         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4549                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4550
4551         dpll = DPLL_VGA_MODE_DIS;
4552
4553         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4554                 dpll |= DPLLB_MODE_LVDS;
4555         else
4556                 dpll |= DPLLB_MODE_DAC_SERIAL;
4557
4558         if ((crtc->config.pixel_multiplier > 1) &&
4559             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4560                 dpll |= (crtc->config.pixel_multiplier - 1)
4561                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4562         }
4563
4564         if (is_sdvo)
4565                 dpll |= DPLL_DVO_HIGH_SPEED;
4566
4567         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4568                 dpll |= DPLL_DVO_HIGH_SPEED;
4569
4570         /* compute bitmask from p1 value */
4571         if (IS_PINEVIEW(dev))
4572                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4573         else {
4574                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4575                 if (IS_G4X(dev) && reduced_clock)
4576                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4577         }
4578         switch (clock->p2) {
4579         case 5:
4580                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4581                 break;
4582         case 7:
4583                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4584                 break;
4585         case 10:
4586                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4587                 break;
4588         case 14:
4589                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4590                 break;
4591         }
4592         if (INTEL_INFO(dev)->gen >= 4)
4593                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4594
4595         if (crtc->config.sdvo_tv_clock)
4596                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4597         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4598                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4599                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4600         else
4601                 dpll |= PLL_REF_INPUT_DREFCLK;
4602
4603         dpll |= DPLL_VCO_ENABLE;
4604         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4605         POSTING_READ(DPLL(pipe));
4606         udelay(150);
4607
4608         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4609                 if (encoder->pre_pll_enable)
4610                         encoder->pre_pll_enable(encoder);
4611
4612         if (crtc->config.has_dp_encoder)
4613                 intel_dp_set_m_n(crtc);
4614
4615         I915_WRITE(DPLL(pipe), dpll);
4616
4617         /* Wait for the clocks to stabilize. */
4618         POSTING_READ(DPLL(pipe));
4619         udelay(150);
4620
4621         if (INTEL_INFO(dev)->gen >= 4) {
4622                 u32 dpll_md = 0;
4623                 if (crtc->config.pixel_multiplier > 1) {
4624                         dpll_md = (crtc->config.pixel_multiplier - 1)
4625                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4626                 }
4627                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4628         } else {
4629                 /* The pixel multiplier can only be updated once the
4630                  * DPLL is enabled and the clocks are stable.
4631                  *
4632                  * So write it again.
4633                  */
4634                 I915_WRITE(DPLL(pipe), dpll);
4635         }
4636 }
4637
4638 static void i8xx_update_pll(struct intel_crtc *crtc,
4639                             struct drm_display_mode *adjusted_mode,
4640                             intel_clock_t *reduced_clock,
4641                             int num_connectors)
4642 {
4643         struct drm_device *dev = crtc->base.dev;
4644         struct drm_i915_private *dev_priv = dev->dev_private;
4645         struct intel_encoder *encoder;
4646         int pipe = crtc->pipe;
4647         u32 dpll;
4648         struct dpll *clock = &crtc->config.dpll;
4649
4650         i9xx_update_pll_dividers(crtc, reduced_clock);
4651
4652         dpll = DPLL_VGA_MODE_DIS;
4653
4654         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4655                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4656         } else {
4657                 if (clock->p1 == 2)
4658                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4659                 else
4660                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4661                 if (clock->p2 == 4)
4662                         dpll |= PLL_P2_DIVIDE_BY_4;
4663         }
4664
4665         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4666                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4667                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4668         else
4669                 dpll |= PLL_REF_INPUT_DREFCLK;
4670
4671         dpll |= DPLL_VCO_ENABLE;
4672         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4673         POSTING_READ(DPLL(pipe));
4674         udelay(150);
4675
4676         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4677                 if (encoder->pre_pll_enable)
4678                         encoder->pre_pll_enable(encoder);
4679
4680         I915_WRITE(DPLL(pipe), dpll);
4681
4682         /* Wait for the clocks to stabilize. */
4683         POSTING_READ(DPLL(pipe));
4684         udelay(150);
4685
4686         /* The pixel multiplier can only be updated once the
4687          * DPLL is enabled and the clocks are stable.
4688          *
4689          * So write it again.
4690          */
4691         I915_WRITE(DPLL(pipe), dpll);
4692 }
4693
4694 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4695                                    struct drm_display_mode *mode,
4696                                    struct drm_display_mode *adjusted_mode)
4697 {
4698         struct drm_device *dev = intel_crtc->base.dev;
4699         struct drm_i915_private *dev_priv = dev->dev_private;
4700         enum pipe pipe = intel_crtc->pipe;
4701         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4702         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4703
4704         /* We need to be careful not to changed the adjusted mode, for otherwise
4705          * the hw state checker will get angry at the mismatch. */
4706         crtc_vtotal = adjusted_mode->crtc_vtotal;
4707         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4708
4709         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4710                 /* the chip adds 2 halflines automatically */
4711                 crtc_vtotal -= 1;
4712                 crtc_vblank_end -= 1;
4713                 vsyncshift = adjusted_mode->crtc_hsync_start
4714                              - adjusted_mode->crtc_htotal / 2;
4715         } else {
4716                 vsyncshift = 0;
4717         }
4718
4719         if (INTEL_INFO(dev)->gen > 3)
4720                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4721
4722         I915_WRITE(HTOTAL(cpu_transcoder),
4723                    (adjusted_mode->crtc_hdisplay - 1) |
4724                    ((adjusted_mode->crtc_htotal - 1) << 16));
4725         I915_WRITE(HBLANK(cpu_transcoder),
4726                    (adjusted_mode->crtc_hblank_start - 1) |
4727                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4728         I915_WRITE(HSYNC(cpu_transcoder),
4729                    (adjusted_mode->crtc_hsync_start - 1) |
4730                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4731
4732         I915_WRITE(VTOTAL(cpu_transcoder),
4733                    (adjusted_mode->crtc_vdisplay - 1) |
4734                    ((crtc_vtotal - 1) << 16));
4735         I915_WRITE(VBLANK(cpu_transcoder),
4736                    (adjusted_mode->crtc_vblank_start - 1) |
4737                    ((crtc_vblank_end - 1) << 16));
4738         I915_WRITE(VSYNC(cpu_transcoder),
4739                    (adjusted_mode->crtc_vsync_start - 1) |
4740                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4741
4742         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4743          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4744          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4745          * bits. */
4746         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4747             (pipe == PIPE_B || pipe == PIPE_C))
4748                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4749
4750         /* pipesrc controls the size that is scaled from, which should
4751          * always be the user's requested size.
4752          */
4753         I915_WRITE(PIPESRC(pipe),
4754                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4755 }
4756
4757 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4758                                    struct intel_crtc_config *pipe_config)
4759 {
4760         struct drm_device *dev = crtc->base.dev;
4761         struct drm_i915_private *dev_priv = dev->dev_private;
4762         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4763         uint32_t tmp;
4764
4765         tmp = I915_READ(HTOTAL(cpu_transcoder));
4766         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4767         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4768         tmp = I915_READ(HBLANK(cpu_transcoder));
4769         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4770         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4771         tmp = I915_READ(HSYNC(cpu_transcoder));
4772         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4773         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4774
4775         tmp = I915_READ(VTOTAL(cpu_transcoder));
4776         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4777         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4778         tmp = I915_READ(VBLANK(cpu_transcoder));
4779         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4780         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4781         tmp = I915_READ(VSYNC(cpu_transcoder));
4782         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4783         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4784
4785         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4786                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4787                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4788                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4789         }
4790
4791         tmp = I915_READ(PIPESRC(crtc->pipe));
4792         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4793         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4794 }
4795
4796 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4797 {
4798         struct drm_device *dev = intel_crtc->base.dev;
4799         struct drm_i915_private *dev_priv = dev->dev_private;
4800         uint32_t pipeconf;
4801
4802         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4803
4804         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4805                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4806                  * core speed.
4807                  *
4808                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4809                  * pipe == 0 check?
4810                  */
4811                 if (intel_crtc->config.requested_mode.clock >
4812                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4813                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4814                 else
4815                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4816         }
4817
4818         /* only g4x and later have fancy bpc/dither controls */
4819         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4820                 pipeconf &= ~(PIPECONF_BPC_MASK |
4821                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4822
4823                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4824                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4825                         pipeconf |= PIPECONF_DITHER_EN |
4826                                     PIPECONF_DITHER_TYPE_SP;
4827
4828                 switch (intel_crtc->config.pipe_bpp) {
4829                 case 18:
4830                         pipeconf |= PIPECONF_6BPC;
4831                         break;
4832                 case 24:
4833                         pipeconf |= PIPECONF_8BPC;
4834                         break;
4835                 case 30:
4836                         pipeconf |= PIPECONF_10BPC;
4837                         break;
4838                 default:
4839                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4840                         BUG();
4841                 }
4842         }
4843
4844         if (HAS_PIPE_CXSR(dev)) {
4845                 if (intel_crtc->lowfreq_avail) {
4846                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4847                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4848                 } else {
4849                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4850                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4851                 }
4852         }
4853
4854         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4855         if (!IS_GEN2(dev) &&
4856             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4857                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4858         else
4859                 pipeconf |= PIPECONF_PROGRESSIVE;
4860
4861         if (IS_VALLEYVIEW(dev)) {
4862                 if (intel_crtc->config.limited_color_range)
4863                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4864                 else
4865                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4866         }
4867
4868         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4869         POSTING_READ(PIPECONF(intel_crtc->pipe));
4870 }
4871
4872 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4873                               int x, int y,
4874                               struct drm_framebuffer *fb)
4875 {
4876         struct drm_device *dev = crtc->dev;
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879         struct drm_display_mode *adjusted_mode =
4880                 &intel_crtc->config.adjusted_mode;
4881         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4882         int pipe = intel_crtc->pipe;
4883         int plane = intel_crtc->plane;
4884         int refclk, num_connectors = 0;
4885         intel_clock_t clock, reduced_clock;
4886         u32 dspcntr;
4887         bool ok, has_reduced_clock = false;
4888         bool is_lvds = false;
4889         struct intel_encoder *encoder;
4890         const intel_limit_t *limit;
4891         int ret;
4892
4893         for_each_encoder_on_crtc(dev, crtc, encoder) {
4894                 switch (encoder->type) {
4895                 case INTEL_OUTPUT_LVDS:
4896                         is_lvds = true;
4897                         break;
4898                 }
4899
4900                 num_connectors++;
4901         }
4902
4903         refclk = i9xx_get_refclk(crtc, num_connectors);
4904
4905         /*
4906          * Returns a set of divisors for the desired target clock with the given
4907          * refclk, or FALSE.  The returned values represent the clock equation:
4908          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4909          */
4910         limit = intel_limit(crtc, refclk);
4911         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4912                              &clock);
4913         if (!ok) {
4914                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4915                 return -EINVAL;
4916         }
4917
4918         /* Ensure that the cursor is valid for the new mode before changing... */
4919         intel_crtc_update_cursor(crtc, true);
4920
4921         if (is_lvds && dev_priv->lvds_downclock_avail) {
4922                 /*
4923                  * Ensure we match the reduced clock's P to the target clock.
4924                  * If the clocks don't match, we can't switch the display clock
4925                  * by using the FP0/FP1. In such case we will disable the LVDS
4926                  * downclock feature.
4927                 */
4928                 has_reduced_clock = limit->find_pll(limit, crtc,
4929                                                     dev_priv->lvds_downclock,
4930                                                     refclk,
4931                                                     &clock,
4932                                                     &reduced_clock);
4933         }
4934         /* Compat-code for transition, will disappear. */
4935         if (!intel_crtc->config.clock_set) {
4936                 intel_crtc->config.dpll.n = clock.n;
4937                 intel_crtc->config.dpll.m1 = clock.m1;
4938                 intel_crtc->config.dpll.m2 = clock.m2;
4939                 intel_crtc->config.dpll.p1 = clock.p1;
4940                 intel_crtc->config.dpll.p2 = clock.p2;
4941         }
4942
4943         if (IS_GEN2(dev))
4944                 i8xx_update_pll(intel_crtc, adjusted_mode,
4945                                 has_reduced_clock ? &reduced_clock : NULL,
4946                                 num_connectors);
4947         else if (IS_VALLEYVIEW(dev))
4948                 vlv_update_pll(intel_crtc);
4949         else
4950                 i9xx_update_pll(intel_crtc,
4951                                 has_reduced_clock ? &reduced_clock : NULL,
4952                                 num_connectors);
4953
4954         /* Set up the display plane register */
4955         dspcntr = DISPPLANE_GAMMA_ENABLE;
4956
4957         if (!IS_VALLEYVIEW(dev)) {
4958                 if (pipe == 0)
4959                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4960                 else
4961                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4962         }
4963
4964         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4965         drm_mode_debug_printmodeline(mode);
4966
4967         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4968
4969         /* pipesrc and dspsize control the size that is scaled from,
4970          * which should always be the user's requested size.
4971          */
4972         I915_WRITE(DSPSIZE(plane),
4973                    ((mode->vdisplay - 1) << 16) |
4974                    (mode->hdisplay - 1));
4975         I915_WRITE(DSPPOS(plane), 0);
4976
4977         i9xx_set_pipeconf(intel_crtc);
4978
4979         I915_WRITE(DSPCNTR(plane), dspcntr);
4980         POSTING_READ(DSPCNTR(plane));
4981
4982         ret = intel_pipe_set_base(crtc, x, y, fb);
4983
4984         intel_update_watermarks(dev);
4985
4986         return ret;
4987 }
4988
4989 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4990                                  struct intel_crtc_config *pipe_config)
4991 {
4992         struct drm_device *dev = crtc->base.dev;
4993         struct drm_i915_private *dev_priv = dev->dev_private;
4994         uint32_t tmp;
4995
4996         tmp = I915_READ(PFIT_CONTROL);
4997
4998         if (INTEL_INFO(dev)->gen < 4) {
4999                 if (crtc->pipe != PIPE_B)
5000                         return;
5001
5002                 /* gen2/3 store dither state in pfit control, needs to match */
5003                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
5004         } else {
5005                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5006                         return;
5007         }
5008
5009         if (!(tmp & PFIT_ENABLE))
5010                 return;
5011
5012         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
5013         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5014         if (INTEL_INFO(dev)->gen < 5)
5015                 pipe_config->gmch_pfit.lvds_border_bits =
5016                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5017 }
5018
5019 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5020                                  struct intel_crtc_config *pipe_config)
5021 {
5022         struct drm_device *dev = crtc->base.dev;
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024         uint32_t tmp;
5025
5026         tmp = I915_READ(PIPECONF(crtc->pipe));
5027         if (!(tmp & PIPECONF_ENABLE))
5028                 return false;
5029
5030         intel_get_pipe_timings(crtc, pipe_config);
5031
5032         i9xx_get_pfit_config(crtc, pipe_config);
5033
5034         return true;
5035 }
5036
5037 static void ironlake_init_pch_refclk(struct drm_device *dev)
5038 {
5039         struct drm_i915_private *dev_priv = dev->dev_private;
5040         struct drm_mode_config *mode_config = &dev->mode_config;
5041         struct intel_encoder *encoder;
5042         u32 val, final;
5043         bool has_lvds = false;
5044         bool has_cpu_edp = false;
5045         bool has_panel = false;
5046         bool has_ck505 = false;
5047         bool can_ssc = false;
5048
5049         /* We need to take the global config into account */
5050         list_for_each_entry(encoder, &mode_config->encoder_list,
5051                             base.head) {
5052                 switch (encoder->type) {
5053                 case INTEL_OUTPUT_LVDS:
5054                         has_panel = true;
5055                         has_lvds = true;
5056                         break;
5057                 case INTEL_OUTPUT_EDP:
5058                         has_panel = true;
5059                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5060                                 has_cpu_edp = true;
5061                         break;
5062                 }
5063         }
5064
5065         if (HAS_PCH_IBX(dev)) {
5066                 has_ck505 = dev_priv->vbt.display_clock_mode;
5067                 can_ssc = has_ck505;
5068         } else {
5069                 has_ck505 = false;
5070                 can_ssc = true;
5071         }
5072
5073         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5074                       has_panel, has_lvds, has_ck505);
5075
5076         /* Ironlake: try to setup display ref clock before DPLL
5077          * enabling. This is only under driver's control after
5078          * PCH B stepping, previous chipset stepping should be
5079          * ignoring this setting.
5080          */
5081         val = I915_READ(PCH_DREF_CONTROL);
5082
5083         /* As we must carefully and slowly disable/enable each source in turn,
5084          * compute the final state we want first and check if we need to
5085          * make any changes at all.
5086          */
5087         final = val;
5088         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5089         if (has_ck505)
5090                 final |= DREF_NONSPREAD_CK505_ENABLE;
5091         else
5092                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5093
5094         final &= ~DREF_SSC_SOURCE_MASK;
5095         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5096         final &= ~DREF_SSC1_ENABLE;
5097
5098         if (has_panel) {
5099                 final |= DREF_SSC_SOURCE_ENABLE;
5100
5101                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5102                         final |= DREF_SSC1_ENABLE;
5103
5104                 if (has_cpu_edp) {
5105                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5106                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5107                         else
5108                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5109                 } else
5110                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5111         } else {
5112                 final |= DREF_SSC_SOURCE_DISABLE;
5113                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5114         }
5115
5116         if (final == val)
5117                 return;
5118
5119         /* Always enable nonspread source */
5120         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5121
5122         if (has_ck505)
5123                 val |= DREF_NONSPREAD_CK505_ENABLE;
5124         else
5125                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5126
5127         if (has_panel) {
5128                 val &= ~DREF_SSC_SOURCE_MASK;
5129                 val |= DREF_SSC_SOURCE_ENABLE;
5130
5131                 /* SSC must be turned on before enabling the CPU output  */
5132                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5133                         DRM_DEBUG_KMS("Using SSC on panel\n");
5134                         val |= DREF_SSC1_ENABLE;
5135                 } else
5136                         val &= ~DREF_SSC1_ENABLE;
5137
5138                 /* Get SSC going before enabling the outputs */
5139                 I915_WRITE(PCH_DREF_CONTROL, val);
5140                 POSTING_READ(PCH_DREF_CONTROL);
5141                 udelay(200);
5142
5143                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5144
5145                 /* Enable CPU source on CPU attached eDP */
5146                 if (has_cpu_edp) {
5147                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5148                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5149                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5150                         }
5151                         else
5152                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5153                 } else
5154                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5155
5156                 I915_WRITE(PCH_DREF_CONTROL, val);
5157                 POSTING_READ(PCH_DREF_CONTROL);
5158                 udelay(200);
5159         } else {
5160                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5161
5162                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5163
5164                 /* Turn off CPU output */
5165                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5166
5167                 I915_WRITE(PCH_DREF_CONTROL, val);
5168                 POSTING_READ(PCH_DREF_CONTROL);
5169                 udelay(200);
5170
5171                 /* Turn off the SSC source */
5172                 val &= ~DREF_SSC_SOURCE_MASK;
5173                 val |= DREF_SSC_SOURCE_DISABLE;
5174
5175                 /* Turn off SSC1 */
5176                 val &= ~DREF_SSC1_ENABLE;
5177
5178                 I915_WRITE(PCH_DREF_CONTROL, val);
5179                 POSTING_READ(PCH_DREF_CONTROL);
5180                 udelay(200);
5181         }
5182
5183         BUG_ON(val != final);
5184 }
5185
5186 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5187 static void lpt_init_pch_refclk(struct drm_device *dev)
5188 {
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190         struct drm_mode_config *mode_config = &dev->mode_config;
5191         struct intel_encoder *encoder;
5192         bool has_vga = false;
5193         bool is_sdv = false;
5194         u32 tmp;
5195
5196         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5197                 switch (encoder->type) {
5198                 case INTEL_OUTPUT_ANALOG:
5199                         has_vga = true;
5200                         break;
5201                 }
5202         }
5203
5204         if (!has_vga)
5205                 return;
5206
5207         mutex_lock(&dev_priv->dpio_lock);
5208
5209         /* XXX: Rip out SDV support once Haswell ships for real. */
5210         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5211                 is_sdv = true;
5212
5213         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5214         tmp &= ~SBI_SSCCTL_DISABLE;
5215         tmp |= SBI_SSCCTL_PATHALT;
5216         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5217
5218         udelay(24);
5219
5220         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5221         tmp &= ~SBI_SSCCTL_PATHALT;
5222         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5223
5224         if (!is_sdv) {
5225                 tmp = I915_READ(SOUTH_CHICKEN2);
5226                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5227                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5228
5229                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5230                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5231                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5232
5233                 tmp = I915_READ(SOUTH_CHICKEN2);
5234                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5235                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5236
5237                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5238                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5239                                        100))
5240                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5241         }
5242
5243         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5244         tmp &= ~(0xFF << 24);
5245         tmp |= (0x12 << 24);
5246         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5247
5248         if (is_sdv) {
5249                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5250                 tmp |= 0x7FFF;
5251                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5252         }
5253
5254         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5255         tmp |= (1 << 11);
5256         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5257
5258         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5259         tmp |= (1 << 11);
5260         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5261
5262         if (is_sdv) {
5263                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5264                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5265                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5266
5267                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5268                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5269                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5270
5271                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5272                 tmp |= (0x3F << 8);
5273                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5274
5275                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5276                 tmp |= (0x3F << 8);
5277                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5278         }
5279
5280         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5281         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5282         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5283
5284         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5285         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5286         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5287
5288         if (!is_sdv) {
5289                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5290                 tmp &= ~(7 << 13);
5291                 tmp |= (5 << 13);
5292                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5293
5294                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5295                 tmp &= ~(7 << 13);
5296                 tmp |= (5 << 13);
5297                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5298         }
5299
5300         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5301         tmp &= ~0xFF;
5302         tmp |= 0x1C;
5303         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5304
5305         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5306         tmp &= ~0xFF;
5307         tmp |= 0x1C;
5308         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5309
5310         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5311         tmp &= ~(0xFF << 16);
5312         tmp |= (0x1C << 16);
5313         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5314
5315         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5316         tmp &= ~(0xFF << 16);
5317         tmp |= (0x1C << 16);
5318         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5319
5320         if (!is_sdv) {
5321                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5322                 tmp |= (1 << 27);
5323                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5324
5325                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5326                 tmp |= (1 << 27);
5327                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5328
5329                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5330                 tmp &= ~(0xF << 28);
5331                 tmp |= (4 << 28);
5332                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5333
5334                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5335                 tmp &= ~(0xF << 28);
5336                 tmp |= (4 << 28);
5337                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5338         }
5339
5340         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5341         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5342         tmp |= SBI_DBUFF0_ENABLE;
5343         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5344
5345         mutex_unlock(&dev_priv->dpio_lock);
5346 }
5347
5348 /*
5349  * Initialize reference clocks when the driver loads
5350  */
5351 void intel_init_pch_refclk(struct drm_device *dev)
5352 {
5353         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5354                 ironlake_init_pch_refclk(dev);
5355         else if (HAS_PCH_LPT(dev))
5356                 lpt_init_pch_refclk(dev);
5357 }
5358
5359 static int ironlake_get_refclk(struct drm_crtc *crtc)
5360 {
5361         struct drm_device *dev = crtc->dev;
5362         struct drm_i915_private *dev_priv = dev->dev_private;
5363         struct intel_encoder *encoder;
5364         int num_connectors = 0;
5365         bool is_lvds = false;
5366
5367         for_each_encoder_on_crtc(dev, crtc, encoder) {
5368                 switch (encoder->type) {
5369                 case INTEL_OUTPUT_LVDS:
5370                         is_lvds = true;
5371                         break;
5372                 }
5373                 num_connectors++;
5374         }
5375
5376         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5377                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5378                               dev_priv->vbt.lvds_ssc_freq);
5379                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5380         }
5381
5382         return 120000;
5383 }
5384
5385 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5386 {
5387         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5389         int pipe = intel_crtc->pipe;
5390         uint32_t val;
5391
5392         val = I915_READ(PIPECONF(pipe));
5393
5394         val &= ~PIPECONF_BPC_MASK;
5395         switch (intel_crtc->config.pipe_bpp) {
5396         case 18:
5397                 val |= PIPECONF_6BPC;
5398                 break;
5399         case 24:
5400                 val |= PIPECONF_8BPC;
5401                 break;
5402         case 30:
5403                 val |= PIPECONF_10BPC;
5404                 break;
5405         case 36:
5406                 val |= PIPECONF_12BPC;
5407                 break;
5408         default:
5409                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5410                 BUG();
5411         }
5412
5413         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5414         if (intel_crtc->config.dither)
5415                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5416
5417         val &= ~PIPECONF_INTERLACE_MASK;
5418         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5419                 val |= PIPECONF_INTERLACED_ILK;
5420         else
5421                 val |= PIPECONF_PROGRESSIVE;
5422
5423         if (intel_crtc->config.limited_color_range)
5424                 val |= PIPECONF_COLOR_RANGE_SELECT;
5425         else
5426                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5427
5428         I915_WRITE(PIPECONF(pipe), val);
5429         POSTING_READ(PIPECONF(pipe));
5430 }
5431
5432 /*
5433  * Set up the pipe CSC unit.
5434  *
5435  * Currently only full range RGB to limited range RGB conversion
5436  * is supported, but eventually this should handle various
5437  * RGB<->YCbCr scenarios as well.
5438  */
5439 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5440 {
5441         struct drm_device *dev = crtc->dev;
5442         struct drm_i915_private *dev_priv = dev->dev_private;
5443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5444         int pipe = intel_crtc->pipe;
5445         uint16_t coeff = 0x7800; /* 1.0 */
5446
5447         /*
5448          * TODO: Check what kind of values actually come out of the pipe
5449          * with these coeff/postoff values and adjust to get the best
5450          * accuracy. Perhaps we even need to take the bpc value into
5451          * consideration.
5452          */
5453
5454         if (intel_crtc->config.limited_color_range)
5455                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5456
5457         /*
5458          * GY/GU and RY/RU should be the other way around according
5459          * to BSpec, but reality doesn't agree. Just set them up in
5460          * a way that results in the correct picture.
5461          */
5462         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5463         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5464
5465         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5466         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5467
5468         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5469         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5470
5471         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5472         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5473         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5474
5475         if (INTEL_INFO(dev)->gen > 6) {
5476                 uint16_t postoff = 0;
5477
5478                 if (intel_crtc->config.limited_color_range)
5479                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5480
5481                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5482                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5483                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5484
5485                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5486         } else {
5487                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5488
5489                 if (intel_crtc->config.limited_color_range)
5490                         mode |= CSC_BLACK_SCREEN_OFFSET;
5491
5492                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5493         }
5494 }
5495
5496 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5497 {
5498         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5500         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5501         uint32_t val;
5502
5503         val = I915_READ(PIPECONF(cpu_transcoder));
5504
5505         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5506         if (intel_crtc->config.dither)
5507                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5508
5509         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5510         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5511                 val |= PIPECONF_INTERLACED_ILK;
5512         else
5513                 val |= PIPECONF_PROGRESSIVE;
5514
5515         I915_WRITE(PIPECONF(cpu_transcoder), val);
5516         POSTING_READ(PIPECONF(cpu_transcoder));
5517 }
5518
5519 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5520                                     struct drm_display_mode *adjusted_mode,
5521                                     intel_clock_t *clock,
5522                                     bool *has_reduced_clock,
5523                                     intel_clock_t *reduced_clock)
5524 {
5525         struct drm_device *dev = crtc->dev;
5526         struct drm_i915_private *dev_priv = dev->dev_private;
5527         struct intel_encoder *intel_encoder;
5528         int refclk;
5529         const intel_limit_t *limit;
5530         bool ret, is_lvds = false;
5531
5532         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5533                 switch (intel_encoder->type) {
5534                 case INTEL_OUTPUT_LVDS:
5535                         is_lvds = true;
5536                         break;
5537                 }
5538         }
5539
5540         refclk = ironlake_get_refclk(crtc);
5541
5542         /*
5543          * Returns a set of divisors for the desired target clock with the given
5544          * refclk, or FALSE.  The returned values represent the clock equation:
5545          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5546          */
5547         limit = intel_limit(crtc, refclk);
5548         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5549                               clock);
5550         if (!ret)
5551                 return false;
5552
5553         if (is_lvds && dev_priv->lvds_downclock_avail) {
5554                 /*
5555                  * Ensure we match the reduced clock's P to the target clock.
5556                  * If the clocks don't match, we can't switch the display clock
5557                  * by using the FP0/FP1. In such case we will disable the LVDS
5558                  * downclock feature.
5559                 */
5560                 *has_reduced_clock = limit->find_pll(limit, crtc,
5561                                                      dev_priv->lvds_downclock,
5562                                                      refclk,
5563                                                      clock,
5564                                                      reduced_clock);
5565         }
5566
5567         return true;
5568 }
5569
5570 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5571 {
5572         struct drm_i915_private *dev_priv = dev->dev_private;
5573         uint32_t temp;
5574
5575         temp = I915_READ(SOUTH_CHICKEN1);
5576         if (temp & FDI_BC_BIFURCATION_SELECT)
5577                 return;
5578
5579         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5580         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5581
5582         temp |= FDI_BC_BIFURCATION_SELECT;
5583         DRM_DEBUG_KMS("enabling fdi C rx\n");
5584         I915_WRITE(SOUTH_CHICKEN1, temp);
5585         POSTING_READ(SOUTH_CHICKEN1);
5586 }
5587
5588 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5589 {
5590         struct drm_device *dev = intel_crtc->base.dev;
5591         struct drm_i915_private *dev_priv = dev->dev_private;
5592
5593         switch (intel_crtc->pipe) {
5594         case PIPE_A:
5595                 break;
5596         case PIPE_B:
5597                 if (intel_crtc->config.fdi_lanes > 2)
5598                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5599                 else
5600                         cpt_enable_fdi_bc_bifurcation(dev);
5601
5602                 break;
5603         case PIPE_C:
5604                 cpt_enable_fdi_bc_bifurcation(dev);
5605
5606                 break;
5607         default:
5608                 BUG();
5609         }
5610 }
5611
5612 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5613 {
5614         /*
5615          * Account for spread spectrum to avoid
5616          * oversubscribing the link. Max center spread
5617          * is 2.5%; use 5% for safety's sake.
5618          */
5619         u32 bps = target_clock * bpp * 21 / 20;
5620         return bps / (link_bw * 8) + 1;
5621 }
5622
5623 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5624 {
5625         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5626 }
5627
5628 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5629                                       u32 *fp,
5630                                       intel_clock_t *reduced_clock, u32 *fp2)
5631 {
5632         struct drm_crtc *crtc = &intel_crtc->base;
5633         struct drm_device *dev = crtc->dev;
5634         struct drm_i915_private *dev_priv = dev->dev_private;
5635         struct intel_encoder *intel_encoder;
5636         uint32_t dpll;
5637         int factor, num_connectors = 0;
5638         bool is_lvds = false, is_sdvo = false;
5639
5640         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5641                 switch (intel_encoder->type) {
5642                 case INTEL_OUTPUT_LVDS:
5643                         is_lvds = true;
5644                         break;
5645                 case INTEL_OUTPUT_SDVO:
5646                 case INTEL_OUTPUT_HDMI:
5647                         is_sdvo = true;
5648                         break;
5649                 }
5650
5651                 num_connectors++;
5652         }
5653
5654         /* Enable autotuning of the PLL clock (if permissible) */
5655         factor = 21;
5656         if (is_lvds) {
5657                 if ((intel_panel_use_ssc(dev_priv) &&
5658                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5659                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5660                         factor = 25;
5661         } else if (intel_crtc->config.sdvo_tv_clock)
5662                 factor = 20;
5663
5664         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5665                 *fp |= FP_CB_TUNE;
5666
5667         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5668                 *fp2 |= FP_CB_TUNE;
5669
5670         dpll = 0;
5671
5672         if (is_lvds)
5673                 dpll |= DPLLB_MODE_LVDS;
5674         else
5675                 dpll |= DPLLB_MODE_DAC_SERIAL;
5676
5677         if (intel_crtc->config.pixel_multiplier > 1) {
5678                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5679                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5680         }
5681
5682         if (is_sdvo)
5683                 dpll |= DPLL_DVO_HIGH_SPEED;
5684         if (intel_crtc->config.has_dp_encoder)
5685                 dpll |= DPLL_DVO_HIGH_SPEED;
5686
5687         /* compute bitmask from p1 value */
5688         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5689         /* also FPA1 */
5690         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5691
5692         switch (intel_crtc->config.dpll.p2) {
5693         case 5:
5694                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5695                 break;
5696         case 7:
5697                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5698                 break;
5699         case 10:
5700                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5701                 break;
5702         case 14:
5703                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5704                 break;
5705         }
5706
5707         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5708                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5709         else
5710                 dpll |= PLL_REF_INPUT_DREFCLK;
5711
5712         return dpll;
5713 }
5714
5715 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5716                                   int x, int y,
5717                                   struct drm_framebuffer *fb)
5718 {
5719         struct drm_device *dev = crtc->dev;
5720         struct drm_i915_private *dev_priv = dev->dev_private;
5721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5722         struct drm_display_mode *adjusted_mode =
5723                 &intel_crtc->config.adjusted_mode;
5724         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5725         int pipe = intel_crtc->pipe;
5726         int plane = intel_crtc->plane;
5727         int num_connectors = 0;
5728         intel_clock_t clock, reduced_clock;
5729         u32 dpll = 0, fp = 0, fp2 = 0;
5730         bool ok, has_reduced_clock = false;
5731         bool is_lvds = false;
5732         struct intel_encoder *encoder;
5733         int ret;
5734
5735         for_each_encoder_on_crtc(dev, crtc, encoder) {
5736                 switch (encoder->type) {
5737                 case INTEL_OUTPUT_LVDS:
5738                         is_lvds = true;
5739                         break;
5740                 }
5741
5742                 num_connectors++;
5743         }
5744
5745         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5746              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5747
5748         intel_crtc->config.cpu_transcoder = pipe;
5749
5750         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5751                                      &has_reduced_clock, &reduced_clock);
5752         if (!ok) {
5753                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5754                 return -EINVAL;
5755         }
5756         /* Compat-code for transition, will disappear. */
5757         if (!intel_crtc->config.clock_set) {
5758                 intel_crtc->config.dpll.n = clock.n;
5759                 intel_crtc->config.dpll.m1 = clock.m1;
5760                 intel_crtc->config.dpll.m2 = clock.m2;
5761                 intel_crtc->config.dpll.p1 = clock.p1;
5762                 intel_crtc->config.dpll.p2 = clock.p2;
5763         }
5764
5765         /* Ensure that the cursor is valid for the new mode before changing... */
5766         intel_crtc_update_cursor(crtc, true);
5767
5768         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5769         drm_mode_debug_printmodeline(mode);
5770
5771         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5772         if (intel_crtc->config.has_pch_encoder) {
5773                 struct intel_pch_pll *pll;
5774
5775                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5776                 if (has_reduced_clock)
5777                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5778
5779                 dpll = ironlake_compute_dpll(intel_crtc,
5780                                              &fp, &reduced_clock,
5781                                              has_reduced_clock ? &fp2 : NULL);
5782
5783                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5784                 if (pll == NULL) {
5785                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5786                                          pipe_name(pipe));
5787                         return -EINVAL;
5788                 }
5789         } else
5790                 intel_put_pch_pll(intel_crtc);
5791
5792         if (intel_crtc->config.has_dp_encoder)
5793                 intel_dp_set_m_n(intel_crtc);
5794
5795         for_each_encoder_on_crtc(dev, crtc, encoder)
5796                 if (encoder->pre_pll_enable)
5797                         encoder->pre_pll_enable(encoder);
5798
5799         if (intel_crtc->pch_pll) {
5800                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5801
5802                 /* Wait for the clocks to stabilize. */
5803                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5804                 udelay(150);
5805
5806                 /* The pixel multiplier can only be updated once the
5807                  * DPLL is enabled and the clocks are stable.
5808                  *
5809                  * So write it again.
5810                  */
5811                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5812         }
5813
5814         intel_crtc->lowfreq_avail = false;
5815         if (intel_crtc->pch_pll) {
5816                 if (is_lvds && has_reduced_clock && i915_powersave) {
5817                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5818                         intel_crtc->lowfreq_avail = true;
5819                 } else {
5820                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5821                 }
5822         }
5823
5824         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5825
5826         if (intel_crtc->config.has_pch_encoder) {
5827                 intel_cpu_transcoder_set_m_n(intel_crtc,
5828                                              &intel_crtc->config.fdi_m_n);
5829         }
5830
5831         if (IS_IVYBRIDGE(dev))
5832                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5833
5834         ironlake_set_pipeconf(crtc);
5835
5836         /* Set up the display plane register */
5837         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5838         POSTING_READ(DSPCNTR(plane));
5839
5840         ret = intel_pipe_set_base(crtc, x, y, fb);
5841
5842         intel_update_watermarks(dev);
5843
5844         return ret;
5845 }
5846
5847 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5848                                         struct intel_crtc_config *pipe_config)
5849 {
5850         struct drm_device *dev = crtc->base.dev;
5851         struct drm_i915_private *dev_priv = dev->dev_private;
5852         enum transcoder transcoder = pipe_config->cpu_transcoder;
5853
5854         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5855         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5856         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5857                                         & ~TU_SIZE_MASK;
5858         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5859         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5860                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5861 }
5862
5863 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5864                                      struct intel_crtc_config *pipe_config)
5865 {
5866         struct drm_device *dev = crtc->base.dev;
5867         struct drm_i915_private *dev_priv = dev->dev_private;
5868         uint32_t tmp;
5869
5870         tmp = I915_READ(PF_CTL(crtc->pipe));
5871
5872         if (tmp & PF_ENABLE) {
5873                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5874                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5875         }
5876 }
5877
5878 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5879                                      struct intel_crtc_config *pipe_config)
5880 {
5881         struct drm_device *dev = crtc->base.dev;
5882         struct drm_i915_private *dev_priv = dev->dev_private;
5883         uint32_t tmp;
5884
5885         tmp = I915_READ(PIPECONF(crtc->pipe));
5886         if (!(tmp & PIPECONF_ENABLE))
5887                 return false;
5888
5889         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5890                 pipe_config->has_pch_encoder = true;
5891
5892                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5893                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5894                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5895
5896                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5897         }
5898
5899         intel_get_pipe_timings(crtc, pipe_config);
5900
5901         ironlake_get_pfit_config(crtc, pipe_config);
5902
5903         return true;
5904 }
5905
5906 static void haswell_modeset_global_resources(struct drm_device *dev)
5907 {
5908         bool enable = false;
5909         struct intel_crtc *crtc;
5910         struct intel_encoder *encoder;
5911
5912         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5913                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5914                         enable = true;
5915                 /* XXX: Should check for edp transcoder here, but thanks to init
5916                  * sequence that's not yet available. Just in case desktop eDP
5917                  * on PORT D is possible on haswell, too. */
5918                 /* Even the eDP panel fitter is outside the always-on well. */
5919                 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5920                         enable = true;
5921         }
5922
5923         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5924                             base.head) {
5925                 if (encoder->type != INTEL_OUTPUT_EDP &&
5926                     encoder->connectors_active)
5927                         enable = true;
5928         }
5929
5930         intel_set_power_well(dev, enable);
5931 }
5932
5933 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5934                                  int x, int y,
5935                                  struct drm_framebuffer *fb)
5936 {
5937         struct drm_device *dev = crtc->dev;
5938         struct drm_i915_private *dev_priv = dev->dev_private;
5939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5940         struct drm_display_mode *adjusted_mode =
5941                 &intel_crtc->config.adjusted_mode;
5942         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5943         int pipe = intel_crtc->pipe;
5944         int plane = intel_crtc->plane;
5945         int num_connectors = 0;
5946         bool is_cpu_edp = false;
5947         struct intel_encoder *encoder;
5948         int ret;
5949
5950         for_each_encoder_on_crtc(dev, crtc, encoder) {
5951                 switch (encoder->type) {
5952                 case INTEL_OUTPUT_EDP:
5953                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5954                                 is_cpu_edp = true;
5955                         break;
5956                 }
5957
5958                 num_connectors++;
5959         }
5960
5961         if (is_cpu_edp)
5962                 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5963         else
5964                 intel_crtc->config.cpu_transcoder = pipe;
5965
5966         /* We are not sure yet this won't happen. */
5967         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5968              INTEL_PCH_TYPE(dev));
5969
5970         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5971              num_connectors, pipe_name(pipe));
5972
5973         WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5974                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5975
5976         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5977
5978         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5979                 return -EINVAL;
5980
5981         /* Ensure that the cursor is valid for the new mode before changing... */
5982         intel_crtc_update_cursor(crtc, true);
5983
5984         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5985         drm_mode_debug_printmodeline(mode);
5986
5987         if (intel_crtc->config.has_dp_encoder)
5988                 intel_dp_set_m_n(intel_crtc);
5989
5990         intel_crtc->lowfreq_avail = false;
5991
5992         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5993
5994         if (intel_crtc->config.has_pch_encoder) {
5995                 intel_cpu_transcoder_set_m_n(intel_crtc,
5996                                              &intel_crtc->config.fdi_m_n);
5997         }
5998
5999         haswell_set_pipeconf(crtc);
6000
6001         intel_set_pipe_csc(crtc);
6002
6003         /* Set up the display plane register */
6004         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6005         POSTING_READ(DSPCNTR(plane));
6006
6007         ret = intel_pipe_set_base(crtc, x, y, fb);
6008
6009         intel_update_watermarks(dev);
6010
6011         return ret;
6012 }
6013
6014 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6015                                     struct intel_crtc_config *pipe_config)
6016 {
6017         struct drm_device *dev = crtc->base.dev;
6018         struct drm_i915_private *dev_priv = dev->dev_private;
6019         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6020         enum intel_display_power_domain pfit_domain;
6021         uint32_t tmp;
6022
6023         if (!intel_display_power_enabled(dev,
6024                         POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6025                 return false;
6026
6027         tmp = I915_READ(PIPECONF(cpu_transcoder));
6028         if (!(tmp & PIPECONF_ENABLE))
6029                 return false;
6030
6031         /*
6032          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6033          * DDI E. So just check whether this pipe is wired to DDI E and whether
6034          * the PCH transcoder is on.
6035          */
6036         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6037         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6038             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6039                 pipe_config->has_pch_encoder = true;
6040
6041                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6042                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6043                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6044
6045                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6046         }
6047
6048         intel_get_pipe_timings(crtc, pipe_config);
6049
6050         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6051         if (intel_display_power_enabled(dev, pfit_domain))
6052                 ironlake_get_pfit_config(crtc, pipe_config);
6053
6054         return true;
6055 }
6056
6057 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6058                                int x, int y,
6059                                struct drm_framebuffer *fb)
6060 {
6061         struct drm_device *dev = crtc->dev;
6062         struct drm_i915_private *dev_priv = dev->dev_private;
6063         struct drm_encoder_helper_funcs *encoder_funcs;
6064         struct intel_encoder *encoder;
6065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6066         struct drm_display_mode *adjusted_mode =
6067                 &intel_crtc->config.adjusted_mode;
6068         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6069         int pipe = intel_crtc->pipe;
6070         int ret;
6071
6072         drm_vblank_pre_modeset(dev, pipe);
6073
6074         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6075
6076         drm_vblank_post_modeset(dev, pipe);
6077
6078         if (ret != 0)
6079                 return ret;
6080
6081         for_each_encoder_on_crtc(dev, crtc, encoder) {
6082                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6083                         encoder->base.base.id,
6084                         drm_get_encoder_name(&encoder->base),
6085                         mode->base.id, mode->name);
6086                 if (encoder->mode_set) {
6087                         encoder->mode_set(encoder);
6088                 } else {
6089                         encoder_funcs = encoder->base.helper_private;
6090                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6091                 }
6092         }
6093
6094         return 0;
6095 }
6096
6097 static bool intel_eld_uptodate(struct drm_connector *connector,
6098                                int reg_eldv, uint32_t bits_eldv,
6099                                int reg_elda, uint32_t bits_elda,
6100                                int reg_edid)
6101 {
6102         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6103         uint8_t *eld = connector->eld;
6104         uint32_t i;
6105
6106         i = I915_READ(reg_eldv);
6107         i &= bits_eldv;
6108
6109         if (!eld[0])
6110                 return !i;
6111
6112         if (!i)
6113                 return false;
6114
6115         i = I915_READ(reg_elda);
6116         i &= ~bits_elda;
6117         I915_WRITE(reg_elda, i);
6118
6119         for (i = 0; i < eld[2]; i++)
6120                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6121                         return false;
6122
6123         return true;
6124 }
6125
6126 static void g4x_write_eld(struct drm_connector *connector,
6127                           struct drm_crtc *crtc)
6128 {
6129         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6130         uint8_t *eld = connector->eld;
6131         uint32_t eldv;
6132         uint32_t len;
6133         uint32_t i;
6134
6135         i = I915_READ(G4X_AUD_VID_DID);
6136
6137         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6138                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6139         else
6140                 eldv = G4X_ELDV_DEVCTG;
6141
6142         if (intel_eld_uptodate(connector,
6143                                G4X_AUD_CNTL_ST, eldv,
6144                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6145                                G4X_HDMIW_HDMIEDID))
6146                 return;
6147
6148         i = I915_READ(G4X_AUD_CNTL_ST);
6149         i &= ~(eldv | G4X_ELD_ADDR);
6150         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6151         I915_WRITE(G4X_AUD_CNTL_ST, i);
6152
6153         if (!eld[0])
6154                 return;
6155
6156         len = min_t(uint8_t, eld[2], len);
6157         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6158         for (i = 0; i < len; i++)
6159                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6160
6161         i = I915_READ(G4X_AUD_CNTL_ST);
6162         i |= eldv;
6163         I915_WRITE(G4X_AUD_CNTL_ST, i);
6164 }
6165
6166 static void haswell_write_eld(struct drm_connector *connector,
6167                                      struct drm_crtc *crtc)
6168 {
6169         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6170         uint8_t *eld = connector->eld;
6171         struct drm_device *dev = crtc->dev;
6172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6173         uint32_t eldv;
6174         uint32_t i;
6175         int len;
6176         int pipe = to_intel_crtc(crtc)->pipe;
6177         int tmp;
6178
6179         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6180         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6181         int aud_config = HSW_AUD_CFG(pipe);
6182         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6183
6184
6185         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6186
6187         /* Audio output enable */
6188         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6189         tmp = I915_READ(aud_cntrl_st2);
6190         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6191         I915_WRITE(aud_cntrl_st2, tmp);
6192
6193         /* Wait for 1 vertical blank */
6194         intel_wait_for_vblank(dev, pipe);
6195
6196         /* Set ELD valid state */
6197         tmp = I915_READ(aud_cntrl_st2);
6198         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6199         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6200         I915_WRITE(aud_cntrl_st2, tmp);
6201         tmp = I915_READ(aud_cntrl_st2);
6202         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6203
6204         /* Enable HDMI mode */
6205         tmp = I915_READ(aud_config);
6206         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6207         /* clear N_programing_enable and N_value_index */
6208         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6209         I915_WRITE(aud_config, tmp);
6210
6211         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6212
6213         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6214         intel_crtc->eld_vld = true;
6215
6216         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6217                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6218                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6219                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6220         } else
6221                 I915_WRITE(aud_config, 0);
6222
6223         if (intel_eld_uptodate(connector,
6224                                aud_cntrl_st2, eldv,
6225                                aud_cntl_st, IBX_ELD_ADDRESS,
6226                                hdmiw_hdmiedid))
6227                 return;
6228
6229         i = I915_READ(aud_cntrl_st2);
6230         i &= ~eldv;
6231         I915_WRITE(aud_cntrl_st2, i);
6232
6233         if (!eld[0])
6234                 return;
6235
6236         i = I915_READ(aud_cntl_st);
6237         i &= ~IBX_ELD_ADDRESS;
6238         I915_WRITE(aud_cntl_st, i);
6239         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6240         DRM_DEBUG_DRIVER("port num:%d\n", i);
6241
6242         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6243         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6244         for (i = 0; i < len; i++)
6245                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6246
6247         i = I915_READ(aud_cntrl_st2);
6248         i |= eldv;
6249         I915_WRITE(aud_cntrl_st2, i);
6250
6251 }
6252
6253 static void ironlake_write_eld(struct drm_connector *connector,
6254                                      struct drm_crtc *crtc)
6255 {
6256         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6257         uint8_t *eld = connector->eld;
6258         uint32_t eldv;
6259         uint32_t i;
6260         int len;
6261         int hdmiw_hdmiedid;
6262         int aud_config;
6263         int aud_cntl_st;
6264         int aud_cntrl_st2;
6265         int pipe = to_intel_crtc(crtc)->pipe;
6266
6267         if (HAS_PCH_IBX(connector->dev)) {
6268                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6269                 aud_config = IBX_AUD_CFG(pipe);
6270                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6271                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6272         } else {
6273                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6274                 aud_config = CPT_AUD_CFG(pipe);
6275                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6276                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6277         }
6278
6279         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6280
6281         i = I915_READ(aud_cntl_st);
6282         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6283         if (!i) {
6284                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6285                 /* operate blindly on all ports */
6286                 eldv = IBX_ELD_VALIDB;
6287                 eldv |= IBX_ELD_VALIDB << 4;
6288                 eldv |= IBX_ELD_VALIDB << 8;
6289         } else {
6290                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6291                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6292         }
6293
6294         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6295                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6296                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6297                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6298         } else
6299                 I915_WRITE(aud_config, 0);
6300
6301         if (intel_eld_uptodate(connector,
6302                                aud_cntrl_st2, eldv,
6303                                aud_cntl_st, IBX_ELD_ADDRESS,
6304                                hdmiw_hdmiedid))
6305                 return;
6306
6307         i = I915_READ(aud_cntrl_st2);
6308         i &= ~eldv;
6309         I915_WRITE(aud_cntrl_st2, i);
6310
6311         if (!eld[0])
6312                 return;
6313
6314         i = I915_READ(aud_cntl_st);
6315         i &= ~IBX_ELD_ADDRESS;
6316         I915_WRITE(aud_cntl_st, i);
6317
6318         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6319         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6320         for (i = 0; i < len; i++)
6321                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6322
6323         i = I915_READ(aud_cntrl_st2);
6324         i |= eldv;
6325         I915_WRITE(aud_cntrl_st2, i);
6326 }
6327
6328 void intel_write_eld(struct drm_encoder *encoder,
6329                      struct drm_display_mode *mode)
6330 {
6331         struct drm_crtc *crtc = encoder->crtc;
6332         struct drm_connector *connector;
6333         struct drm_device *dev = encoder->dev;
6334         struct drm_i915_private *dev_priv = dev->dev_private;
6335
6336         connector = drm_select_eld(encoder, mode);
6337         if (!connector)
6338                 return;
6339
6340         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6341                          connector->base.id,
6342                          drm_get_connector_name(connector),
6343                          connector->encoder->base.id,
6344                          drm_get_encoder_name(connector->encoder));
6345
6346         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6347
6348         if (dev_priv->display.write_eld)
6349                 dev_priv->display.write_eld(connector, crtc);
6350 }
6351
6352 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6353 void intel_crtc_load_lut(struct drm_crtc *crtc)
6354 {
6355         struct drm_device *dev = crtc->dev;
6356         struct drm_i915_private *dev_priv = dev->dev_private;
6357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358         int palreg = PALETTE(intel_crtc->pipe);
6359         int i;
6360
6361         /* The clocks have to be on to load the palette. */
6362         if (!crtc->enabled || !intel_crtc->active)
6363                 return;
6364
6365         /* use legacy palette for Ironlake */
6366         if (HAS_PCH_SPLIT(dev))
6367                 palreg = LGC_PALETTE(intel_crtc->pipe);
6368
6369         for (i = 0; i < 256; i++) {
6370                 I915_WRITE(palreg + 4 * i,
6371                            (intel_crtc->lut_r[i] << 16) |
6372                            (intel_crtc->lut_g[i] << 8) |
6373                            intel_crtc->lut_b[i]);
6374         }
6375 }
6376
6377 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6378 {
6379         struct drm_device *dev = crtc->dev;
6380         struct drm_i915_private *dev_priv = dev->dev_private;
6381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382         bool visible = base != 0;
6383         u32 cntl;
6384
6385         if (intel_crtc->cursor_visible == visible)
6386                 return;
6387
6388         cntl = I915_READ(_CURACNTR);
6389         if (visible) {
6390                 /* On these chipsets we can only modify the base whilst
6391                  * the cursor is disabled.
6392                  */
6393                 I915_WRITE(_CURABASE, base);
6394
6395                 cntl &= ~(CURSOR_FORMAT_MASK);
6396                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6397                 cntl |= CURSOR_ENABLE |
6398                         CURSOR_GAMMA_ENABLE |
6399                         CURSOR_FORMAT_ARGB;
6400         } else
6401                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6402         I915_WRITE(_CURACNTR, cntl);
6403
6404         intel_crtc->cursor_visible = visible;
6405 }
6406
6407 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6408 {
6409         struct drm_device *dev = crtc->dev;
6410         struct drm_i915_private *dev_priv = dev->dev_private;
6411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6412         int pipe = intel_crtc->pipe;
6413         bool visible = base != 0;
6414
6415         if (intel_crtc->cursor_visible != visible) {
6416                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6417                 if (base) {
6418                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6419                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6420                         cntl |= pipe << 28; /* Connect to correct pipe */
6421                 } else {
6422                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6423                         cntl |= CURSOR_MODE_DISABLE;
6424                 }
6425                 I915_WRITE(CURCNTR(pipe), cntl);
6426
6427                 intel_crtc->cursor_visible = visible;
6428         }
6429         /* and commit changes on next vblank */
6430         I915_WRITE(CURBASE(pipe), base);
6431 }
6432
6433 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6434 {
6435         struct drm_device *dev = crtc->dev;
6436         struct drm_i915_private *dev_priv = dev->dev_private;
6437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6438         int pipe = intel_crtc->pipe;
6439         bool visible = base != 0;
6440
6441         if (intel_crtc->cursor_visible != visible) {
6442                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6443                 if (base) {
6444                         cntl &= ~CURSOR_MODE;
6445                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6446                 } else {
6447                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6448                         cntl |= CURSOR_MODE_DISABLE;
6449                 }
6450                 if (IS_HASWELL(dev))
6451                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6452                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6453
6454                 intel_crtc->cursor_visible = visible;
6455         }
6456         /* and commit changes on next vblank */
6457         I915_WRITE(CURBASE_IVB(pipe), base);
6458 }
6459
6460 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6461 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6462                                      bool on)
6463 {
6464         struct drm_device *dev = crtc->dev;
6465         struct drm_i915_private *dev_priv = dev->dev_private;
6466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6467         int pipe = intel_crtc->pipe;
6468         int x = intel_crtc->cursor_x;
6469         int y = intel_crtc->cursor_y;
6470         u32 base, pos;
6471         bool visible;
6472
6473         pos = 0;
6474
6475         if (on && crtc->enabled && crtc->fb) {
6476                 base = intel_crtc->cursor_addr;
6477                 if (x > (int) crtc->fb->width)
6478                         base = 0;
6479
6480                 if (y > (int) crtc->fb->height)
6481                         base = 0;
6482         } else
6483                 base = 0;
6484
6485         if (x < 0) {
6486                 if (x + intel_crtc->cursor_width < 0)
6487                         base = 0;
6488
6489                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6490                 x = -x;
6491         }
6492         pos |= x << CURSOR_X_SHIFT;
6493
6494         if (y < 0) {
6495                 if (y + intel_crtc->cursor_height < 0)
6496                         base = 0;
6497
6498                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6499                 y = -y;
6500         }
6501         pos |= y << CURSOR_Y_SHIFT;
6502
6503         visible = base != 0;
6504         if (!visible && !intel_crtc->cursor_visible)
6505                 return;
6506
6507         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6508                 I915_WRITE(CURPOS_IVB(pipe), pos);
6509                 ivb_update_cursor(crtc, base);
6510         } else {
6511                 I915_WRITE(CURPOS(pipe), pos);
6512                 if (IS_845G(dev) || IS_I865G(dev))
6513                         i845_update_cursor(crtc, base);
6514                 else
6515                         i9xx_update_cursor(crtc, base);
6516         }
6517 }
6518
6519 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6520                                  struct drm_file *file,
6521                                  uint32_t handle,
6522                                  uint32_t width, uint32_t height)
6523 {
6524         struct drm_device *dev = crtc->dev;
6525         struct drm_i915_private *dev_priv = dev->dev_private;
6526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6527         struct drm_i915_gem_object *obj;
6528         uint32_t addr;
6529         int ret;
6530
6531         /* if we want to turn off the cursor ignore width and height */
6532         if (!handle) {
6533                 DRM_DEBUG_KMS("cursor off\n");
6534                 addr = 0;
6535                 obj = NULL;
6536                 mutex_lock(&dev->struct_mutex);
6537                 goto finish;
6538         }
6539
6540         /* Currently we only support 64x64 cursors */
6541         if (width != 64 || height != 64) {
6542                 DRM_ERROR("we currently only support 64x64 cursors\n");
6543                 return -EINVAL;
6544         }
6545
6546         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6547         if (&obj->base == NULL)
6548                 return -ENOENT;
6549
6550         if (obj->base.size < width * height * 4) {
6551                 DRM_ERROR("buffer is to small\n");
6552                 ret = -ENOMEM;
6553                 goto fail;
6554         }
6555
6556         /* we only need to pin inside GTT if cursor is non-phy */
6557         mutex_lock(&dev->struct_mutex);
6558         if (!dev_priv->info->cursor_needs_physical) {
6559                 unsigned alignment;
6560
6561                 if (obj->tiling_mode) {
6562                         DRM_ERROR("cursor cannot be tiled\n");
6563                         ret = -EINVAL;
6564                         goto fail_locked;
6565                 }
6566
6567                 /* Note that the w/a also requires 2 PTE of padding following
6568                  * the bo. We currently fill all unused PTE with the shadow
6569                  * page and so we should always have valid PTE following the
6570                  * cursor preventing the VT-d warning.
6571                  */
6572                 alignment = 0;
6573                 if (need_vtd_wa(dev))
6574                         alignment = 64*1024;
6575
6576                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6577                 if (ret) {
6578                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6579                         goto fail_locked;
6580                 }
6581
6582                 ret = i915_gem_object_put_fence(obj);
6583                 if (ret) {
6584                         DRM_ERROR("failed to release fence for cursor");
6585                         goto fail_unpin;
6586                 }
6587
6588                 addr = obj->gtt_offset;
6589         } else {
6590                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6591                 ret = i915_gem_attach_phys_object(dev, obj,
6592                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6593                                                   align);
6594                 if (ret) {
6595                         DRM_ERROR("failed to attach phys object\n");
6596                         goto fail_locked;
6597                 }
6598                 addr = obj->phys_obj->handle->busaddr;
6599         }
6600
6601         if (IS_GEN2(dev))
6602                 I915_WRITE(CURSIZE, (height << 12) | width);
6603
6604  finish:
6605         if (intel_crtc->cursor_bo) {
6606                 if (dev_priv->info->cursor_needs_physical) {
6607                         if (intel_crtc->cursor_bo != obj)
6608                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6609                 } else
6610                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6611                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6612         }
6613
6614         mutex_unlock(&dev->struct_mutex);
6615
6616         intel_crtc->cursor_addr = addr;
6617         intel_crtc->cursor_bo = obj;
6618         intel_crtc->cursor_width = width;
6619         intel_crtc->cursor_height = height;
6620
6621         intel_crtc_update_cursor(crtc, true);
6622
6623         return 0;
6624 fail_unpin:
6625         i915_gem_object_unpin(obj);
6626 fail_locked:
6627         mutex_unlock(&dev->struct_mutex);
6628 fail:
6629         drm_gem_object_unreference_unlocked(&obj->base);
6630         return ret;
6631 }
6632
6633 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6634 {
6635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6636
6637         intel_crtc->cursor_x = x;
6638         intel_crtc->cursor_y = y;
6639
6640         intel_crtc_update_cursor(crtc, true);
6641
6642         return 0;
6643 }
6644
6645 /** Sets the color ramps on behalf of RandR */
6646 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6647                                  u16 blue, int regno)
6648 {
6649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650
6651         intel_crtc->lut_r[regno] = red >> 8;
6652         intel_crtc->lut_g[regno] = green >> 8;
6653         intel_crtc->lut_b[regno] = blue >> 8;
6654 }
6655
6656 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6657                              u16 *blue, int regno)
6658 {
6659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6660
6661         *red = intel_crtc->lut_r[regno] << 8;
6662         *green = intel_crtc->lut_g[regno] << 8;
6663         *blue = intel_crtc->lut_b[regno] << 8;
6664 }
6665
6666 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6667                                  u16 *blue, uint32_t start, uint32_t size)
6668 {
6669         int end = (start + size > 256) ? 256 : start + size, i;
6670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6671
6672         for (i = start; i < end; i++) {
6673                 intel_crtc->lut_r[i] = red[i] >> 8;
6674                 intel_crtc->lut_g[i] = green[i] >> 8;
6675                 intel_crtc->lut_b[i] = blue[i] >> 8;
6676         }
6677
6678         intel_crtc_load_lut(crtc);
6679 }
6680
6681 /* VESA 640x480x72Hz mode to set on the pipe */
6682 static struct drm_display_mode load_detect_mode = {
6683         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6684                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6685 };
6686
6687 static struct drm_framebuffer *
6688 intel_framebuffer_create(struct drm_device *dev,
6689                          struct drm_mode_fb_cmd2 *mode_cmd,
6690                          struct drm_i915_gem_object *obj)
6691 {
6692         struct intel_framebuffer *intel_fb;
6693         int ret;
6694
6695         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6696         if (!intel_fb) {
6697                 drm_gem_object_unreference_unlocked(&obj->base);
6698                 return ERR_PTR(-ENOMEM);
6699         }
6700
6701         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6702         if (ret) {
6703                 drm_gem_object_unreference_unlocked(&obj->base);
6704                 kfree(intel_fb);
6705                 return ERR_PTR(ret);
6706         }
6707
6708         return &intel_fb->base;
6709 }
6710
6711 static u32
6712 intel_framebuffer_pitch_for_width(int width, int bpp)
6713 {
6714         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6715         return ALIGN(pitch, 64);
6716 }
6717
6718 static u32
6719 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6720 {
6721         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6722         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6723 }
6724
6725 static struct drm_framebuffer *
6726 intel_framebuffer_create_for_mode(struct drm_device *dev,
6727                                   struct drm_display_mode *mode,
6728                                   int depth, int bpp)
6729 {
6730         struct drm_i915_gem_object *obj;
6731         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6732
6733         obj = i915_gem_alloc_object(dev,
6734                                     intel_framebuffer_size_for_mode(mode, bpp));
6735         if (obj == NULL)
6736                 return ERR_PTR(-ENOMEM);
6737
6738         mode_cmd.width = mode->hdisplay;
6739         mode_cmd.height = mode->vdisplay;
6740         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6741                                                                 bpp);
6742         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6743
6744         return intel_framebuffer_create(dev, &mode_cmd, obj);
6745 }
6746
6747 static struct drm_framebuffer *
6748 mode_fits_in_fbdev(struct drm_device *dev,
6749                    struct drm_display_mode *mode)
6750 {
6751         struct drm_i915_private *dev_priv = dev->dev_private;
6752         struct drm_i915_gem_object *obj;
6753         struct drm_framebuffer *fb;
6754
6755         if (dev_priv->fbdev == NULL)
6756                 return NULL;
6757
6758         obj = dev_priv->fbdev->ifb.obj;
6759         if (obj == NULL)
6760                 return NULL;
6761
6762         fb = &dev_priv->fbdev->ifb.base;
6763         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6764                                                                fb->bits_per_pixel))
6765                 return NULL;
6766
6767         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6768                 return NULL;
6769
6770         return fb;
6771 }
6772
6773 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6774                                 struct drm_display_mode *mode,
6775                                 struct intel_load_detect_pipe *old)
6776 {
6777         struct intel_crtc *intel_crtc;
6778         struct intel_encoder *intel_encoder =
6779                 intel_attached_encoder(connector);
6780         struct drm_crtc *possible_crtc;
6781         struct drm_encoder *encoder = &intel_encoder->base;
6782         struct drm_crtc *crtc = NULL;
6783         struct drm_device *dev = encoder->dev;
6784         struct drm_framebuffer *fb;
6785         int i = -1;
6786
6787         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6788                       connector->base.id, drm_get_connector_name(connector),
6789                       encoder->base.id, drm_get_encoder_name(encoder));
6790
6791         /*
6792          * Algorithm gets a little messy:
6793          *
6794          *   - if the connector already has an assigned crtc, use it (but make
6795          *     sure it's on first)
6796          *
6797          *   - try to find the first unused crtc that can drive this connector,
6798          *     and use that if we find one
6799          */
6800
6801         /* See if we already have a CRTC for this connector */
6802         if (encoder->crtc) {
6803                 crtc = encoder->crtc;
6804
6805                 mutex_lock(&crtc->mutex);
6806
6807                 old->dpms_mode = connector->dpms;
6808                 old->load_detect_temp = false;
6809
6810                 /* Make sure the crtc and connector are running */
6811                 if (connector->dpms != DRM_MODE_DPMS_ON)
6812                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6813
6814                 return true;
6815         }
6816
6817         /* Find an unused one (if possible) */
6818         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6819                 i++;
6820                 if (!(encoder->possible_crtcs & (1 << i)))
6821                         continue;
6822                 if (!possible_crtc->enabled) {
6823                         crtc = possible_crtc;
6824                         break;
6825                 }
6826         }
6827
6828         /*
6829          * If we didn't find an unused CRTC, don't use any.
6830          */
6831         if (!crtc) {
6832                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6833                 return false;
6834         }
6835
6836         mutex_lock(&crtc->mutex);
6837         intel_encoder->new_crtc = to_intel_crtc(crtc);
6838         to_intel_connector(connector)->new_encoder = intel_encoder;
6839
6840         intel_crtc = to_intel_crtc(crtc);
6841         old->dpms_mode = connector->dpms;
6842         old->load_detect_temp = true;
6843         old->release_fb = NULL;
6844
6845         if (!mode)
6846                 mode = &load_detect_mode;
6847
6848         /* We need a framebuffer large enough to accommodate all accesses
6849          * that the plane may generate whilst we perform load detection.
6850          * We can not rely on the fbcon either being present (we get called
6851          * during its initialisation to detect all boot displays, or it may
6852          * not even exist) or that it is large enough to satisfy the
6853          * requested mode.
6854          */
6855         fb = mode_fits_in_fbdev(dev, mode);
6856         if (fb == NULL) {
6857                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6858                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6859                 old->release_fb = fb;
6860         } else
6861                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6862         if (IS_ERR(fb)) {
6863                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6864                 mutex_unlock(&crtc->mutex);
6865                 return false;
6866         }
6867
6868         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6869                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6870                 if (old->release_fb)
6871                         old->release_fb->funcs->destroy(old->release_fb);
6872                 mutex_unlock(&crtc->mutex);
6873                 return false;
6874         }
6875
6876         /* let the connector get through one full cycle before testing */
6877         intel_wait_for_vblank(dev, intel_crtc->pipe);
6878         return true;
6879 }
6880
6881 void intel_release_load_detect_pipe(struct drm_connector *connector,
6882                                     struct intel_load_detect_pipe *old)
6883 {
6884         struct intel_encoder *intel_encoder =
6885                 intel_attached_encoder(connector);
6886         struct drm_encoder *encoder = &intel_encoder->base;
6887         struct drm_crtc *crtc = encoder->crtc;
6888
6889         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6890                       connector->base.id, drm_get_connector_name(connector),
6891                       encoder->base.id, drm_get_encoder_name(encoder));
6892
6893         if (old->load_detect_temp) {
6894                 to_intel_connector(connector)->new_encoder = NULL;
6895                 intel_encoder->new_crtc = NULL;
6896                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6897
6898                 if (old->release_fb) {
6899                         drm_framebuffer_unregister_private(old->release_fb);
6900                         drm_framebuffer_unreference(old->release_fb);
6901                 }
6902
6903                 mutex_unlock(&crtc->mutex);
6904                 return;
6905         }
6906
6907         /* Switch crtc and encoder back off if necessary */
6908         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6909                 connector->funcs->dpms(connector, old->dpms_mode);
6910
6911         mutex_unlock(&crtc->mutex);
6912 }
6913
6914 /* Returns the clock of the currently programmed mode of the given pipe. */
6915 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6916 {
6917         struct drm_i915_private *dev_priv = dev->dev_private;
6918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6919         int pipe = intel_crtc->pipe;
6920         u32 dpll = I915_READ(DPLL(pipe));
6921         u32 fp;
6922         intel_clock_t clock;
6923
6924         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6925                 fp = I915_READ(FP0(pipe));
6926         else
6927                 fp = I915_READ(FP1(pipe));
6928
6929         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6930         if (IS_PINEVIEW(dev)) {
6931                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6932                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6933         } else {
6934                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6935                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6936         }
6937
6938         if (!IS_GEN2(dev)) {
6939                 if (IS_PINEVIEW(dev))
6940                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6941                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6942                 else
6943                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6944                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6945
6946                 switch (dpll & DPLL_MODE_MASK) {
6947                 case DPLLB_MODE_DAC_SERIAL:
6948                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6949                                 5 : 10;
6950                         break;
6951                 case DPLLB_MODE_LVDS:
6952                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6953                                 7 : 14;
6954                         break;
6955                 default:
6956                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6957                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6958                         return 0;
6959                 }
6960
6961                 /* XXX: Handle the 100Mhz refclk */
6962                 intel_clock(dev, 96000, &clock);
6963         } else {
6964                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6965
6966                 if (is_lvds) {
6967                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6968                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6969                         clock.p2 = 14;
6970
6971                         if ((dpll & PLL_REF_INPUT_MASK) ==
6972                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6973                                 /* XXX: might not be 66MHz */
6974                                 intel_clock(dev, 66000, &clock);
6975                         } else
6976                                 intel_clock(dev, 48000, &clock);
6977                 } else {
6978                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6979                                 clock.p1 = 2;
6980                         else {
6981                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6982                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6983                         }
6984                         if (dpll & PLL_P2_DIVIDE_BY_4)
6985                                 clock.p2 = 4;
6986                         else
6987                                 clock.p2 = 2;
6988
6989                         intel_clock(dev, 48000, &clock);
6990                 }
6991         }
6992
6993         /* XXX: It would be nice to validate the clocks, but we can't reuse
6994          * i830PllIsValid() because it relies on the xf86_config connector
6995          * configuration being accurate, which it isn't necessarily.
6996          */
6997
6998         return clock.dot;
6999 }
7000
7001 /** Returns the currently programmed mode of the given pipe. */
7002 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7003                                              struct drm_crtc *crtc)
7004 {
7005         struct drm_i915_private *dev_priv = dev->dev_private;
7006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7008         struct drm_display_mode *mode;
7009         int htot = I915_READ(HTOTAL(cpu_transcoder));
7010         int hsync = I915_READ(HSYNC(cpu_transcoder));
7011         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7012         int vsync = I915_READ(VSYNC(cpu_transcoder));
7013
7014         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7015         if (!mode)
7016                 return NULL;
7017
7018         mode->clock = intel_crtc_clock_get(dev, crtc);
7019         mode->hdisplay = (htot & 0xffff) + 1;
7020         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7021         mode->hsync_start = (hsync & 0xffff) + 1;
7022         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7023         mode->vdisplay = (vtot & 0xffff) + 1;
7024         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7025         mode->vsync_start = (vsync & 0xffff) + 1;
7026         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7027
7028         drm_mode_set_name(mode);
7029
7030         return mode;
7031 }
7032
7033 static void intel_increase_pllclock(struct drm_crtc *crtc)
7034 {
7035         struct drm_device *dev = crtc->dev;
7036         drm_i915_private_t *dev_priv = dev->dev_private;
7037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7038         int pipe = intel_crtc->pipe;
7039         int dpll_reg = DPLL(pipe);
7040         int dpll;
7041
7042         if (HAS_PCH_SPLIT(dev))
7043                 return;
7044
7045         if (!dev_priv->lvds_downclock_avail)
7046                 return;
7047
7048         dpll = I915_READ(dpll_reg);
7049         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7050                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7051
7052                 assert_panel_unlocked(dev_priv, pipe);
7053
7054                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7055                 I915_WRITE(dpll_reg, dpll);
7056                 intel_wait_for_vblank(dev, pipe);
7057
7058                 dpll = I915_READ(dpll_reg);
7059                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7060                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7061         }
7062 }
7063
7064 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7065 {
7066         struct drm_device *dev = crtc->dev;
7067         drm_i915_private_t *dev_priv = dev->dev_private;
7068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7069
7070         if (HAS_PCH_SPLIT(dev))
7071                 return;
7072
7073         if (!dev_priv->lvds_downclock_avail)
7074                 return;
7075
7076         /*
7077          * Since this is called by a timer, we should never get here in
7078          * the manual case.
7079          */
7080         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7081                 int pipe = intel_crtc->pipe;
7082                 int dpll_reg = DPLL(pipe);
7083                 int dpll;
7084
7085                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7086
7087                 assert_panel_unlocked(dev_priv, pipe);
7088
7089                 dpll = I915_READ(dpll_reg);
7090                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7091                 I915_WRITE(dpll_reg, dpll);
7092                 intel_wait_for_vblank(dev, pipe);
7093                 dpll = I915_READ(dpll_reg);
7094                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7095                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7096         }
7097
7098 }
7099
7100 void intel_mark_busy(struct drm_device *dev)
7101 {
7102         i915_update_gfx_val(dev->dev_private);
7103 }
7104
7105 void intel_mark_idle(struct drm_device *dev)
7106 {
7107         struct drm_crtc *crtc;
7108
7109         if (!i915_powersave)
7110                 return;
7111
7112         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7113                 if (!crtc->fb)
7114                         continue;
7115
7116                 intel_decrease_pllclock(crtc);
7117         }
7118 }
7119
7120 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7121 {
7122         struct drm_device *dev = obj->base.dev;
7123         struct drm_crtc *crtc;
7124
7125         if (!i915_powersave)
7126                 return;
7127
7128         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7129                 if (!crtc->fb)
7130                         continue;
7131
7132                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7133                         intel_increase_pllclock(crtc);
7134         }
7135 }
7136
7137 static void intel_crtc_destroy(struct drm_crtc *crtc)
7138 {
7139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140         struct drm_device *dev = crtc->dev;
7141         struct intel_unpin_work *work;
7142         unsigned long flags;
7143
7144         spin_lock_irqsave(&dev->event_lock, flags);
7145         work = intel_crtc->unpin_work;
7146         intel_crtc->unpin_work = NULL;
7147         spin_unlock_irqrestore(&dev->event_lock, flags);
7148
7149         if (work) {
7150                 cancel_work_sync(&work->work);
7151                 kfree(work);
7152         }
7153
7154         drm_crtc_cleanup(crtc);
7155
7156         kfree(intel_crtc);
7157 }
7158
7159 static void intel_unpin_work_fn(struct work_struct *__work)
7160 {
7161         struct intel_unpin_work *work =
7162                 container_of(__work, struct intel_unpin_work, work);
7163         struct drm_device *dev = work->crtc->dev;
7164
7165         mutex_lock(&dev->struct_mutex);
7166         intel_unpin_fb_obj(work->old_fb_obj);
7167         drm_gem_object_unreference(&work->pending_flip_obj->base);
7168         drm_gem_object_unreference(&work->old_fb_obj->base);
7169
7170         intel_update_fbc(dev);
7171         mutex_unlock(&dev->struct_mutex);
7172
7173         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7174         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7175
7176         kfree(work);
7177 }
7178
7179 static void do_intel_finish_page_flip(struct drm_device *dev,
7180                                       struct drm_crtc *crtc)
7181 {
7182         drm_i915_private_t *dev_priv = dev->dev_private;
7183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7184         struct intel_unpin_work *work;
7185         unsigned long flags;
7186
7187         /* Ignore early vblank irqs */
7188         if (intel_crtc == NULL)
7189                 return;
7190
7191         spin_lock_irqsave(&dev->event_lock, flags);
7192         work = intel_crtc->unpin_work;
7193
7194         /* Ensure we don't miss a work->pending update ... */
7195         smp_rmb();
7196
7197         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7198                 spin_unlock_irqrestore(&dev->event_lock, flags);
7199                 return;
7200         }
7201
7202         /* and that the unpin work is consistent wrt ->pending. */
7203         smp_rmb();
7204
7205         intel_crtc->unpin_work = NULL;
7206
7207         if (work->event)
7208                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7209
7210         drm_vblank_put(dev, intel_crtc->pipe);
7211
7212         spin_unlock_irqrestore(&dev->event_lock, flags);
7213
7214         wake_up_all(&dev_priv->pending_flip_queue);
7215
7216         queue_work(dev_priv->wq, &work->work);
7217
7218         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7219 }
7220
7221 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7222 {
7223         drm_i915_private_t *dev_priv = dev->dev_private;
7224         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7225
7226         do_intel_finish_page_flip(dev, crtc);
7227 }
7228
7229 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7230 {
7231         drm_i915_private_t *dev_priv = dev->dev_private;
7232         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7233
7234         do_intel_finish_page_flip(dev, crtc);
7235 }
7236
7237 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7238 {
7239         drm_i915_private_t *dev_priv = dev->dev_private;
7240         struct intel_crtc *intel_crtc =
7241                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7242         unsigned long flags;
7243
7244         /* NB: An MMIO update of the plane base pointer will also
7245          * generate a page-flip completion irq, i.e. every modeset
7246          * is also accompanied by a spurious intel_prepare_page_flip().
7247          */
7248         spin_lock_irqsave(&dev->event_lock, flags);
7249         if (intel_crtc->unpin_work)
7250                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7251         spin_unlock_irqrestore(&dev->event_lock, flags);
7252 }
7253
7254 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7255 {
7256         /* Ensure that the work item is consistent when activating it ... */
7257         smp_wmb();
7258         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7259         /* and that it is marked active as soon as the irq could fire. */
7260         smp_wmb();
7261 }
7262
7263 static int intel_gen2_queue_flip(struct drm_device *dev,
7264                                  struct drm_crtc *crtc,
7265                                  struct drm_framebuffer *fb,
7266                                  struct drm_i915_gem_object *obj)
7267 {
7268         struct drm_i915_private *dev_priv = dev->dev_private;
7269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270         u32 flip_mask;
7271         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7272         int ret;
7273
7274         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7275         if (ret)
7276                 goto err;
7277
7278         ret = intel_ring_begin(ring, 6);
7279         if (ret)
7280                 goto err_unpin;
7281
7282         /* Can't queue multiple flips, so wait for the previous
7283          * one to finish before executing the next.
7284          */
7285         if (intel_crtc->plane)
7286                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7287         else
7288                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7289         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7290         intel_ring_emit(ring, MI_NOOP);
7291         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7292                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7293         intel_ring_emit(ring, fb->pitches[0]);
7294         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7295         intel_ring_emit(ring, 0); /* aux display base address, unused */
7296
7297         intel_mark_page_flip_active(intel_crtc);
7298         intel_ring_advance(ring);
7299         return 0;
7300
7301 err_unpin:
7302         intel_unpin_fb_obj(obj);
7303 err:
7304         return ret;
7305 }
7306
7307 static int intel_gen3_queue_flip(struct drm_device *dev,
7308                                  struct drm_crtc *crtc,
7309                                  struct drm_framebuffer *fb,
7310                                  struct drm_i915_gem_object *obj)
7311 {
7312         struct drm_i915_private *dev_priv = dev->dev_private;
7313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314         u32 flip_mask;
7315         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7316         int ret;
7317
7318         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7319         if (ret)
7320                 goto err;
7321
7322         ret = intel_ring_begin(ring, 6);
7323         if (ret)
7324                 goto err_unpin;
7325
7326         if (intel_crtc->plane)
7327                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7328         else
7329                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7330         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7331         intel_ring_emit(ring, MI_NOOP);
7332         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7333                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7334         intel_ring_emit(ring, fb->pitches[0]);
7335         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7336         intel_ring_emit(ring, MI_NOOP);
7337
7338         intel_mark_page_flip_active(intel_crtc);
7339         intel_ring_advance(ring);
7340         return 0;
7341
7342 err_unpin:
7343         intel_unpin_fb_obj(obj);
7344 err:
7345         return ret;
7346 }
7347
7348 static int intel_gen4_queue_flip(struct drm_device *dev,
7349                                  struct drm_crtc *crtc,
7350                                  struct drm_framebuffer *fb,
7351                                  struct drm_i915_gem_object *obj)
7352 {
7353         struct drm_i915_private *dev_priv = dev->dev_private;
7354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7355         uint32_t pf, pipesrc;
7356         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7357         int ret;
7358
7359         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7360         if (ret)
7361                 goto err;
7362
7363         ret = intel_ring_begin(ring, 4);
7364         if (ret)
7365                 goto err_unpin;
7366
7367         /* i965+ uses the linear or tiled offsets from the
7368          * Display Registers (which do not change across a page-flip)
7369          * so we need only reprogram the base address.
7370          */
7371         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7372                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7373         intel_ring_emit(ring, fb->pitches[0]);
7374         intel_ring_emit(ring,
7375                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7376                         obj->tiling_mode);
7377
7378         /* XXX Enabling the panel-fitter across page-flip is so far
7379          * untested on non-native modes, so ignore it for now.
7380          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7381          */
7382         pf = 0;
7383         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7384         intel_ring_emit(ring, pf | pipesrc);
7385
7386         intel_mark_page_flip_active(intel_crtc);
7387         intel_ring_advance(ring);
7388         return 0;
7389
7390 err_unpin:
7391         intel_unpin_fb_obj(obj);
7392 err:
7393         return ret;
7394 }
7395
7396 static int intel_gen6_queue_flip(struct drm_device *dev,
7397                                  struct drm_crtc *crtc,
7398                                  struct drm_framebuffer *fb,
7399                                  struct drm_i915_gem_object *obj)
7400 {
7401         struct drm_i915_private *dev_priv = dev->dev_private;
7402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7403         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7404         uint32_t pf, pipesrc;
7405         int ret;
7406
7407         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7408         if (ret)
7409                 goto err;
7410
7411         ret = intel_ring_begin(ring, 4);
7412         if (ret)
7413                 goto err_unpin;
7414
7415         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7416                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7417         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7418         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7419
7420         /* Contrary to the suggestions in the documentation,
7421          * "Enable Panel Fitter" does not seem to be required when page
7422          * flipping with a non-native mode, and worse causes a normal
7423          * modeset to fail.
7424          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7425          */
7426         pf = 0;
7427         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7428         intel_ring_emit(ring, pf | pipesrc);
7429
7430         intel_mark_page_flip_active(intel_crtc);
7431         intel_ring_advance(ring);
7432         return 0;
7433
7434 err_unpin:
7435         intel_unpin_fb_obj(obj);
7436 err:
7437         return ret;
7438 }
7439
7440 /*
7441  * On gen7 we currently use the blit ring because (in early silicon at least)
7442  * the render ring doesn't give us interrpts for page flip completion, which
7443  * means clients will hang after the first flip is queued.  Fortunately the
7444  * blit ring generates interrupts properly, so use it instead.
7445  */
7446 static int intel_gen7_queue_flip(struct drm_device *dev,
7447                                  struct drm_crtc *crtc,
7448                                  struct drm_framebuffer *fb,
7449                                  struct drm_i915_gem_object *obj)
7450 {
7451         struct drm_i915_private *dev_priv = dev->dev_private;
7452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7453         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7454         uint32_t plane_bit = 0;
7455         int ret;
7456
7457         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7458         if (ret)
7459                 goto err;
7460
7461         switch(intel_crtc->plane) {
7462         case PLANE_A:
7463                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7464                 break;
7465         case PLANE_B:
7466                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7467                 break;
7468         case PLANE_C:
7469                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7470                 break;
7471         default:
7472                 WARN_ONCE(1, "unknown plane in flip command\n");
7473                 ret = -ENODEV;
7474                 goto err_unpin;
7475         }
7476
7477         ret = intel_ring_begin(ring, 4);
7478         if (ret)
7479                 goto err_unpin;
7480
7481         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7482         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7483         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7484         intel_ring_emit(ring, (MI_NOOP));
7485
7486         intel_mark_page_flip_active(intel_crtc);
7487         intel_ring_advance(ring);
7488         return 0;
7489
7490 err_unpin:
7491         intel_unpin_fb_obj(obj);
7492 err:
7493         return ret;
7494 }
7495
7496 static int intel_default_queue_flip(struct drm_device *dev,
7497                                     struct drm_crtc *crtc,
7498                                     struct drm_framebuffer *fb,
7499                                     struct drm_i915_gem_object *obj)
7500 {
7501         return -ENODEV;
7502 }
7503
7504 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7505                                 struct drm_framebuffer *fb,
7506                                 struct drm_pending_vblank_event *event)
7507 {
7508         struct drm_device *dev = crtc->dev;
7509         struct drm_i915_private *dev_priv = dev->dev_private;
7510         struct drm_framebuffer *old_fb = crtc->fb;
7511         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7513         struct intel_unpin_work *work;
7514         unsigned long flags;
7515         int ret;
7516
7517         /* Can't change pixel format via MI display flips. */
7518         if (fb->pixel_format != crtc->fb->pixel_format)
7519                 return -EINVAL;
7520
7521         /*
7522          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7523          * Note that pitch changes could also affect these register.
7524          */
7525         if (INTEL_INFO(dev)->gen > 3 &&
7526             (fb->offsets[0] != crtc->fb->offsets[0] ||
7527              fb->pitches[0] != crtc->fb->pitches[0]))
7528                 return -EINVAL;
7529
7530         work = kzalloc(sizeof *work, GFP_KERNEL);
7531         if (work == NULL)
7532                 return -ENOMEM;
7533
7534         work->event = event;
7535         work->crtc = crtc;
7536         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7537         INIT_WORK(&work->work, intel_unpin_work_fn);
7538
7539         ret = drm_vblank_get(dev, intel_crtc->pipe);
7540         if (ret)
7541                 goto free_work;
7542
7543         /* We borrow the event spin lock for protecting unpin_work */
7544         spin_lock_irqsave(&dev->event_lock, flags);
7545         if (intel_crtc->unpin_work) {
7546                 spin_unlock_irqrestore(&dev->event_lock, flags);
7547                 kfree(work);
7548                 drm_vblank_put(dev, intel_crtc->pipe);
7549
7550                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7551                 return -EBUSY;
7552         }
7553         intel_crtc->unpin_work = work;
7554         spin_unlock_irqrestore(&dev->event_lock, flags);
7555
7556         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7557                 flush_workqueue(dev_priv->wq);
7558
7559         ret = i915_mutex_lock_interruptible(dev);
7560         if (ret)
7561                 goto cleanup;
7562
7563         /* Reference the objects for the scheduled work. */
7564         drm_gem_object_reference(&work->old_fb_obj->base);
7565         drm_gem_object_reference(&obj->base);
7566
7567         crtc->fb = fb;
7568
7569         work->pending_flip_obj = obj;
7570
7571         work->enable_stall_check = true;
7572
7573         atomic_inc(&intel_crtc->unpin_work_count);
7574         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7575
7576         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7577         if (ret)
7578                 goto cleanup_pending;
7579
7580         intel_disable_fbc(dev);
7581         intel_mark_fb_busy(obj);
7582         mutex_unlock(&dev->struct_mutex);
7583
7584         trace_i915_flip_request(intel_crtc->plane, obj);
7585
7586         return 0;
7587
7588 cleanup_pending:
7589         atomic_dec(&intel_crtc->unpin_work_count);
7590         crtc->fb = old_fb;
7591         drm_gem_object_unreference(&work->old_fb_obj->base);
7592         drm_gem_object_unreference(&obj->base);
7593         mutex_unlock(&dev->struct_mutex);
7594
7595 cleanup:
7596         spin_lock_irqsave(&dev->event_lock, flags);
7597         intel_crtc->unpin_work = NULL;
7598         spin_unlock_irqrestore(&dev->event_lock, flags);
7599
7600         drm_vblank_put(dev, intel_crtc->pipe);
7601 free_work:
7602         kfree(work);
7603
7604         return ret;
7605 }
7606
7607 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7608         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7609         .load_lut = intel_crtc_load_lut,
7610 };
7611
7612 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7613 {
7614         struct intel_encoder *other_encoder;
7615         struct drm_crtc *crtc = &encoder->new_crtc->base;
7616
7617         if (WARN_ON(!crtc))
7618                 return false;
7619
7620         list_for_each_entry(other_encoder,
7621                             &crtc->dev->mode_config.encoder_list,
7622                             base.head) {
7623
7624                 if (&other_encoder->new_crtc->base != crtc ||
7625                     encoder == other_encoder)
7626                         continue;
7627                 else
7628                         return true;
7629         }
7630
7631         return false;
7632 }
7633
7634 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7635                                   struct drm_crtc *crtc)
7636 {
7637         struct drm_device *dev;
7638         struct drm_crtc *tmp;
7639         int crtc_mask = 1;
7640
7641         WARN(!crtc, "checking null crtc?\n");
7642
7643         dev = crtc->dev;
7644
7645         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7646                 if (tmp == crtc)
7647                         break;
7648                 crtc_mask <<= 1;
7649         }
7650
7651         if (encoder->possible_crtcs & crtc_mask)
7652                 return true;
7653         return false;
7654 }
7655
7656 /**
7657  * intel_modeset_update_staged_output_state
7658  *
7659  * Updates the staged output configuration state, e.g. after we've read out the
7660  * current hw state.
7661  */
7662 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7663 {
7664         struct intel_encoder *encoder;
7665         struct intel_connector *connector;
7666
7667         list_for_each_entry(connector, &dev->mode_config.connector_list,
7668                             base.head) {
7669                 connector->new_encoder =
7670                         to_intel_encoder(connector->base.encoder);
7671         }
7672
7673         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7674                             base.head) {
7675                 encoder->new_crtc =
7676                         to_intel_crtc(encoder->base.crtc);
7677         }
7678 }
7679
7680 /**
7681  * intel_modeset_commit_output_state
7682  *
7683  * This function copies the stage display pipe configuration to the real one.
7684  */
7685 static void intel_modeset_commit_output_state(struct drm_device *dev)
7686 {
7687         struct intel_encoder *encoder;
7688         struct intel_connector *connector;
7689
7690         list_for_each_entry(connector, &dev->mode_config.connector_list,
7691                             base.head) {
7692                 connector->base.encoder = &connector->new_encoder->base;
7693         }
7694
7695         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7696                             base.head) {
7697                 encoder->base.crtc = &encoder->new_crtc->base;
7698         }
7699 }
7700
7701 static int
7702 pipe_config_set_bpp(struct drm_crtc *crtc,
7703                     struct drm_framebuffer *fb,
7704                     struct intel_crtc_config *pipe_config)
7705 {
7706         struct drm_device *dev = crtc->dev;
7707         struct drm_connector *connector;
7708         int bpp;
7709
7710         switch (fb->pixel_format) {
7711         case DRM_FORMAT_C8:
7712                 bpp = 8*3; /* since we go through a colormap */
7713                 break;
7714         case DRM_FORMAT_XRGB1555:
7715         case DRM_FORMAT_ARGB1555:
7716                 /* checked in intel_framebuffer_init already */
7717                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7718                         return -EINVAL;
7719         case DRM_FORMAT_RGB565:
7720                 bpp = 6*3; /* min is 18bpp */
7721                 break;
7722         case DRM_FORMAT_XBGR8888:
7723         case DRM_FORMAT_ABGR8888:
7724                 /* checked in intel_framebuffer_init already */
7725                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7726                         return -EINVAL;
7727         case DRM_FORMAT_XRGB8888:
7728         case DRM_FORMAT_ARGB8888:
7729                 bpp = 8*3;
7730                 break;
7731         case DRM_FORMAT_XRGB2101010:
7732         case DRM_FORMAT_ARGB2101010:
7733         case DRM_FORMAT_XBGR2101010:
7734         case DRM_FORMAT_ABGR2101010:
7735                 /* checked in intel_framebuffer_init already */
7736                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7737                         return -EINVAL;
7738                 bpp = 10*3;
7739                 break;
7740         /* TODO: gen4+ supports 16 bpc floating point, too. */
7741         default:
7742                 DRM_DEBUG_KMS("unsupported depth\n");
7743                 return -EINVAL;
7744         }
7745
7746         pipe_config->pipe_bpp = bpp;
7747
7748         /* Clamp display bpp to EDID value */
7749         list_for_each_entry(connector, &dev->mode_config.connector_list,
7750                             head) {
7751                 if (connector->encoder && connector->encoder->crtc != crtc)
7752                         continue;
7753
7754                 /* Don't use an invalid EDID bpc value */
7755                 if (connector->display_info.bpc &&
7756                     connector->display_info.bpc * 3 < bpp) {
7757                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7758                                       bpp, connector->display_info.bpc*3);
7759                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7760                 }
7761
7762                 /* Clamp bpp to 8 on screens without EDID 1.4 */
7763                 if (connector->display_info.bpc == 0 && bpp > 24) {
7764                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7765                                       bpp);
7766                         pipe_config->pipe_bpp = 24;
7767                 }
7768         }
7769
7770         return bpp;
7771 }
7772
7773 static struct intel_crtc_config *
7774 intel_modeset_pipe_config(struct drm_crtc *crtc,
7775                           struct drm_framebuffer *fb,
7776                           struct drm_display_mode *mode)
7777 {
7778         struct drm_device *dev = crtc->dev;
7779         struct drm_encoder_helper_funcs *encoder_funcs;
7780         struct intel_encoder *encoder;
7781         struct intel_crtc_config *pipe_config;
7782         int plane_bpp, ret = -EINVAL;
7783         bool retry = true;
7784
7785         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7786         if (!pipe_config)
7787                 return ERR_PTR(-ENOMEM);
7788
7789         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7790         drm_mode_copy(&pipe_config->requested_mode, mode);
7791
7792         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7793         if (plane_bpp < 0)
7794                 goto fail;
7795
7796 encoder_retry:
7797         /* Pass our mode to the connectors and the CRTC to give them a chance to
7798          * adjust it according to limitations or connector properties, and also
7799          * a chance to reject the mode entirely.
7800          */
7801         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7802                             base.head) {
7803
7804                 if (&encoder->new_crtc->base != crtc)
7805                         continue;
7806
7807                 if (encoder->compute_config) {
7808                         if (!(encoder->compute_config(encoder, pipe_config))) {
7809                                 DRM_DEBUG_KMS("Encoder config failure\n");
7810                                 goto fail;
7811                         }
7812
7813                         continue;
7814                 }
7815
7816                 encoder_funcs = encoder->base.helper_private;
7817                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7818                                                 &pipe_config->requested_mode,
7819                                                 &pipe_config->adjusted_mode))) {
7820                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7821                         goto fail;
7822                 }
7823         }
7824
7825         ret = intel_crtc_compute_config(crtc, pipe_config);
7826         if (ret < 0) {
7827                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7828                 goto fail;
7829         }
7830
7831         if (ret == RETRY) {
7832                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7833                         ret = -EINVAL;
7834                         goto fail;
7835                 }
7836
7837                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7838                 retry = false;
7839                 goto encoder_retry;
7840         }
7841
7842         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7843
7844         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7845         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7846                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7847
7848         return pipe_config;
7849 fail:
7850         kfree(pipe_config);
7851         return ERR_PTR(ret);
7852 }
7853
7854 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7855  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7856 static void
7857 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7858                              unsigned *prepare_pipes, unsigned *disable_pipes)
7859 {
7860         struct intel_crtc *intel_crtc;
7861         struct drm_device *dev = crtc->dev;
7862         struct intel_encoder *encoder;
7863         struct intel_connector *connector;
7864         struct drm_crtc *tmp_crtc;
7865
7866         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7867
7868         /* Check which crtcs have changed outputs connected to them, these need
7869          * to be part of the prepare_pipes mask. We don't (yet) support global
7870          * modeset across multiple crtcs, so modeset_pipes will only have one
7871          * bit set at most. */
7872         list_for_each_entry(connector, &dev->mode_config.connector_list,
7873                             base.head) {
7874                 if (connector->base.encoder == &connector->new_encoder->base)
7875                         continue;
7876
7877                 if (connector->base.encoder) {
7878                         tmp_crtc = connector->base.encoder->crtc;
7879
7880                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7881                 }
7882
7883                 if (connector->new_encoder)
7884                         *prepare_pipes |=
7885                                 1 << connector->new_encoder->new_crtc->pipe;
7886         }
7887
7888         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7889                             base.head) {
7890                 if (encoder->base.crtc == &encoder->new_crtc->base)
7891                         continue;
7892
7893                 if (encoder->base.crtc) {
7894                         tmp_crtc = encoder->base.crtc;
7895
7896                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7897                 }
7898
7899                 if (encoder->new_crtc)
7900                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7901         }
7902
7903         /* Check for any pipes that will be fully disabled ... */
7904         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7905                             base.head) {
7906                 bool used = false;
7907
7908                 /* Don't try to disable disabled crtcs. */
7909                 if (!intel_crtc->base.enabled)
7910                         continue;
7911
7912                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7913                                     base.head) {
7914                         if (encoder->new_crtc == intel_crtc)
7915                                 used = true;
7916                 }
7917
7918                 if (!used)
7919                         *disable_pipes |= 1 << intel_crtc->pipe;
7920         }
7921
7922
7923         /* set_mode is also used to update properties on life display pipes. */
7924         intel_crtc = to_intel_crtc(crtc);
7925         if (crtc->enabled)
7926                 *prepare_pipes |= 1 << intel_crtc->pipe;
7927
7928         /*
7929          * For simplicity do a full modeset on any pipe where the output routing
7930          * changed. We could be more clever, but that would require us to be
7931          * more careful with calling the relevant encoder->mode_set functions.
7932          */
7933         if (*prepare_pipes)
7934                 *modeset_pipes = *prepare_pipes;
7935
7936         /* ... and mask these out. */
7937         *modeset_pipes &= ~(*disable_pipes);
7938         *prepare_pipes &= ~(*disable_pipes);
7939
7940         /*
7941          * HACK: We don't (yet) fully support global modesets. intel_set_config
7942          * obies this rule, but the modeset restore mode of
7943          * intel_modeset_setup_hw_state does not.
7944          */
7945         *modeset_pipes &= 1 << intel_crtc->pipe;
7946         *prepare_pipes &= 1 << intel_crtc->pipe;
7947
7948         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7949                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7950 }
7951
7952 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7953 {
7954         struct drm_encoder *encoder;
7955         struct drm_device *dev = crtc->dev;
7956
7957         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7958                 if (encoder->crtc == crtc)
7959                         return true;
7960
7961         return false;
7962 }
7963
7964 static void
7965 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7966 {
7967         struct intel_encoder *intel_encoder;
7968         struct intel_crtc *intel_crtc;
7969         struct drm_connector *connector;
7970
7971         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7972                             base.head) {
7973                 if (!intel_encoder->base.crtc)
7974                         continue;
7975
7976                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7977
7978                 if (prepare_pipes & (1 << intel_crtc->pipe))
7979                         intel_encoder->connectors_active = false;
7980         }
7981
7982         intel_modeset_commit_output_state(dev);
7983
7984         /* Update computed state. */
7985         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7986                             base.head) {
7987                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7988         }
7989
7990         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7991                 if (!connector->encoder || !connector->encoder->crtc)
7992                         continue;
7993
7994                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7995
7996                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7997                         struct drm_property *dpms_property =
7998                                 dev->mode_config.dpms_property;
7999
8000                         connector->dpms = DRM_MODE_DPMS_ON;
8001                         drm_object_property_set_value(&connector->base,
8002                                                          dpms_property,
8003                                                          DRM_MODE_DPMS_ON);
8004
8005                         intel_encoder = to_intel_encoder(connector->encoder);
8006                         intel_encoder->connectors_active = true;
8007                 }
8008         }
8009
8010 }
8011
8012 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8013         list_for_each_entry((intel_crtc), \
8014                             &(dev)->mode_config.crtc_list, \
8015                             base.head) \
8016                 if (mask & (1 <<(intel_crtc)->pipe))
8017
8018 static bool
8019 intel_pipe_config_compare(struct drm_device *dev,
8020                           struct intel_crtc_config *current_config,
8021                           struct intel_crtc_config *pipe_config)
8022 {
8023 #define PIPE_CONF_CHECK_I(name) \
8024         if (current_config->name != pipe_config->name) { \
8025                 DRM_ERROR("mismatch in " #name " " \
8026                           "(expected %i, found %i)\n", \
8027                           current_config->name, \
8028                           pipe_config->name); \
8029                 return false; \
8030         }
8031
8032 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8033         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8034                 DRM_ERROR("mismatch in " #name " " \
8035                           "(expected %i, found %i)\n", \
8036                           current_config->name & (mask), \
8037                           pipe_config->name & (mask)); \
8038                 return false; \
8039         }
8040
8041         PIPE_CONF_CHECK_I(has_pch_encoder);
8042         PIPE_CONF_CHECK_I(fdi_lanes);
8043         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8044         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8045         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8046         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8047         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8048
8049         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8050         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8051         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8052         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8053         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8054         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8055
8056         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8057         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8058         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8059         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8060         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8061         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8062
8063         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8064                               DRM_MODE_FLAG_INTERLACE);
8065
8066         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8067                               DRM_MODE_FLAG_PHSYNC);
8068         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8069                               DRM_MODE_FLAG_NHSYNC);
8070         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8071                               DRM_MODE_FLAG_PVSYNC);
8072         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8073                               DRM_MODE_FLAG_NVSYNC);
8074
8075         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8076         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8077
8078         PIPE_CONF_CHECK_I(gmch_pfit.control);
8079         /* pfit ratios are autocomputed by the hw on gen4+ */
8080         if (INTEL_INFO(dev)->gen < 4)
8081                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8082         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8083         PIPE_CONF_CHECK_I(pch_pfit.pos);
8084         PIPE_CONF_CHECK_I(pch_pfit.size);
8085
8086 #undef PIPE_CONF_CHECK_I
8087 #undef PIPE_CONF_CHECK_FLAGS
8088
8089         return true;
8090 }
8091
8092 void
8093 intel_modeset_check_state(struct drm_device *dev)
8094 {
8095         drm_i915_private_t *dev_priv = dev->dev_private;
8096         struct intel_crtc *crtc;
8097         struct intel_encoder *encoder;
8098         struct intel_connector *connector;
8099         struct intel_crtc_config pipe_config;
8100
8101         list_for_each_entry(connector, &dev->mode_config.connector_list,
8102                             base.head) {
8103                 /* This also checks the encoder/connector hw state with the
8104                  * ->get_hw_state callbacks. */
8105                 intel_connector_check_state(connector);
8106
8107                 WARN(&connector->new_encoder->base != connector->base.encoder,
8108                      "connector's staged encoder doesn't match current encoder\n");
8109         }
8110
8111         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8112                             base.head) {
8113                 bool enabled = false;
8114                 bool active = false;
8115                 enum pipe pipe, tracked_pipe;
8116
8117                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8118                               encoder->base.base.id,
8119                               drm_get_encoder_name(&encoder->base));
8120
8121                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8122                      "encoder's stage crtc doesn't match current crtc\n");
8123                 WARN(encoder->connectors_active && !encoder->base.crtc,
8124                      "encoder's active_connectors set, but no crtc\n");
8125
8126                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8127                                     base.head) {
8128                         if (connector->base.encoder != &encoder->base)
8129                                 continue;
8130                         enabled = true;
8131                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8132                                 active = true;
8133                 }
8134                 WARN(!!encoder->base.crtc != enabled,
8135                      "encoder's enabled state mismatch "
8136                      "(expected %i, found %i)\n",
8137                      !!encoder->base.crtc, enabled);
8138                 WARN(active && !encoder->base.crtc,
8139                      "active encoder with no crtc\n");
8140
8141                 WARN(encoder->connectors_active != active,
8142                      "encoder's computed active state doesn't match tracked active state "
8143                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8144
8145                 active = encoder->get_hw_state(encoder, &pipe);
8146                 WARN(active != encoder->connectors_active,
8147                      "encoder's hw state doesn't match sw tracking "
8148                      "(expected %i, found %i)\n",
8149                      encoder->connectors_active, active);
8150
8151                 if (!encoder->base.crtc)
8152                         continue;
8153
8154                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8155                 WARN(active && pipe != tracked_pipe,
8156                      "active encoder's pipe doesn't match"
8157                      "(expected %i, found %i)\n",
8158                      tracked_pipe, pipe);
8159
8160         }
8161
8162         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8163                             base.head) {
8164                 bool enabled = false;
8165                 bool active = false;
8166
8167                 memset(&pipe_config, 0, sizeof(pipe_config));
8168
8169                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8170                               crtc->base.base.id);
8171
8172                 WARN(crtc->active && !crtc->base.enabled,
8173                      "active crtc, but not enabled in sw tracking\n");
8174
8175                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8176                                     base.head) {
8177                         if (encoder->base.crtc != &crtc->base)
8178                                 continue;
8179                         enabled = true;
8180                         if (encoder->connectors_active)
8181                                 active = true;
8182                         if (encoder->get_config)
8183                                 encoder->get_config(encoder, &pipe_config);
8184                 }
8185                 WARN(active != crtc->active,
8186                      "crtc's computed active state doesn't match tracked active state "
8187                      "(expected %i, found %i)\n", active, crtc->active);
8188                 WARN(enabled != crtc->base.enabled,
8189                      "crtc's computed enabled state doesn't match tracked enabled state "
8190                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8191
8192                 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8193                 active = dev_priv->display.get_pipe_config(crtc,
8194                                                            &pipe_config);
8195                 WARN(crtc->active != active,
8196                      "crtc active state doesn't match with hw state "
8197                      "(expected %i, found %i)\n", crtc->active, active);
8198
8199                 WARN(active &&
8200                      !intel_pipe_config_compare(dev, &crtc->config, &pipe_config),
8201                      "pipe state doesn't match!\n");
8202         }
8203 }
8204
8205 static int __intel_set_mode(struct drm_crtc *crtc,
8206                             struct drm_display_mode *mode,
8207                             int x, int y, struct drm_framebuffer *fb)
8208 {
8209         struct drm_device *dev = crtc->dev;
8210         drm_i915_private_t *dev_priv = dev->dev_private;
8211         struct drm_display_mode *saved_mode, *saved_hwmode;
8212         struct intel_crtc_config *pipe_config = NULL;
8213         struct intel_crtc *intel_crtc;
8214         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8215         int ret = 0;
8216
8217         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8218         if (!saved_mode)
8219                 return -ENOMEM;
8220         saved_hwmode = saved_mode + 1;
8221
8222         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8223                                      &prepare_pipes, &disable_pipes);
8224
8225         *saved_hwmode = crtc->hwmode;
8226         *saved_mode = crtc->mode;
8227
8228         /* Hack: Because we don't (yet) support global modeset on multiple
8229          * crtcs, we don't keep track of the new mode for more than one crtc.
8230          * Hence simply check whether any bit is set in modeset_pipes in all the
8231          * pieces of code that are not yet converted to deal with mutliple crtcs
8232          * changing their mode at the same time. */
8233         if (modeset_pipes) {
8234                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8235                 if (IS_ERR(pipe_config)) {
8236                         ret = PTR_ERR(pipe_config);
8237                         pipe_config = NULL;
8238
8239                         goto out;
8240                 }
8241         }
8242
8243         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8244                 intel_crtc_disable(&intel_crtc->base);
8245
8246         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8247                 if (intel_crtc->base.enabled)
8248                         dev_priv->display.crtc_disable(&intel_crtc->base);
8249         }
8250
8251         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8252          * to set it here already despite that we pass it down the callchain.
8253          */
8254         if (modeset_pipes) {
8255                 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8256                 crtc->mode = *mode;
8257                 /* mode_set/enable/disable functions rely on a correct pipe
8258                  * config. */
8259                 to_intel_crtc(crtc)->config = *pipe_config;
8260                 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8261         }
8262
8263         /* Only after disabling all output pipelines that will be changed can we
8264          * update the the output configuration. */
8265         intel_modeset_update_state(dev, prepare_pipes);
8266
8267         if (dev_priv->display.modeset_global_resources)
8268                 dev_priv->display.modeset_global_resources(dev);
8269
8270         /* Set up the DPLL and any encoders state that needs to adjust or depend
8271          * on the DPLL.
8272          */
8273         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8274                 ret = intel_crtc_mode_set(&intel_crtc->base,
8275                                           x, y, fb);
8276                 if (ret)
8277                         goto done;
8278         }
8279
8280         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8281         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8282                 dev_priv->display.crtc_enable(&intel_crtc->base);
8283
8284         if (modeset_pipes) {
8285                 /* Store real post-adjustment hardware mode. */
8286                 crtc->hwmode = pipe_config->adjusted_mode;
8287
8288                 /* Calculate and store various constants which
8289                  * are later needed by vblank and swap-completion
8290                  * timestamping. They are derived from true hwmode.
8291                  */
8292                 drm_calc_timestamping_constants(crtc);
8293         }
8294
8295         /* FIXME: add subpixel order */
8296 done:
8297         if (ret && crtc->enabled) {
8298                 crtc->hwmode = *saved_hwmode;
8299                 crtc->mode = *saved_mode;
8300         }
8301
8302 out:
8303         kfree(pipe_config);
8304         kfree(saved_mode);
8305         return ret;
8306 }
8307
8308 int intel_set_mode(struct drm_crtc *crtc,
8309                      struct drm_display_mode *mode,
8310                      int x, int y, struct drm_framebuffer *fb)
8311 {
8312         int ret;
8313
8314         ret = __intel_set_mode(crtc, mode, x, y, fb);
8315
8316         if (ret == 0)
8317                 intel_modeset_check_state(crtc->dev);
8318
8319         return ret;
8320 }
8321
8322 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8323 {
8324         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8325 }
8326
8327 #undef for_each_intel_crtc_masked
8328
8329 static void intel_set_config_free(struct intel_set_config *config)
8330 {
8331         if (!config)
8332                 return;
8333
8334         kfree(config->save_connector_encoders);
8335         kfree(config->save_encoder_crtcs);
8336         kfree(config);
8337 }
8338
8339 static int intel_set_config_save_state(struct drm_device *dev,
8340                                        struct intel_set_config *config)
8341 {
8342         struct drm_encoder *encoder;
8343         struct drm_connector *connector;
8344         int count;
8345
8346         config->save_encoder_crtcs =
8347                 kcalloc(dev->mode_config.num_encoder,
8348                         sizeof(struct drm_crtc *), GFP_KERNEL);
8349         if (!config->save_encoder_crtcs)
8350                 return -ENOMEM;
8351
8352         config->save_connector_encoders =
8353                 kcalloc(dev->mode_config.num_connector,
8354                         sizeof(struct drm_encoder *), GFP_KERNEL);
8355         if (!config->save_connector_encoders)
8356                 return -ENOMEM;
8357
8358         /* Copy data. Note that driver private data is not affected.
8359          * Should anything bad happen only the expected state is
8360          * restored, not the drivers personal bookkeeping.
8361          */
8362         count = 0;
8363         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8364                 config->save_encoder_crtcs[count++] = encoder->crtc;
8365         }
8366
8367         count = 0;
8368         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8369                 config->save_connector_encoders[count++] = connector->encoder;
8370         }
8371
8372         return 0;
8373 }
8374
8375 static void intel_set_config_restore_state(struct drm_device *dev,
8376                                            struct intel_set_config *config)
8377 {
8378         struct intel_encoder *encoder;
8379         struct intel_connector *connector;
8380         int count;
8381
8382         count = 0;
8383         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8384                 encoder->new_crtc =
8385                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8386         }
8387
8388         count = 0;
8389         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8390                 connector->new_encoder =
8391                         to_intel_encoder(config->save_connector_encoders[count++]);
8392         }
8393 }
8394
8395 static void
8396 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8397                                       struct intel_set_config *config)
8398 {
8399
8400         /* We should be able to check here if the fb has the same properties
8401          * and then just flip_or_move it */
8402         if (set->crtc->fb != set->fb) {
8403                 /* If we have no fb then treat it as a full mode set */
8404                 if (set->crtc->fb == NULL) {
8405                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8406                         config->mode_changed = true;
8407                 } else if (set->fb == NULL) {
8408                         config->mode_changed = true;
8409                 } else if (set->fb->pixel_format !=
8410                            set->crtc->fb->pixel_format) {
8411                         config->mode_changed = true;
8412                 } else
8413                         config->fb_changed = true;
8414         }
8415
8416         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8417                 config->fb_changed = true;
8418
8419         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8420                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8421                 drm_mode_debug_printmodeline(&set->crtc->mode);
8422                 drm_mode_debug_printmodeline(set->mode);
8423                 config->mode_changed = true;
8424         }
8425 }
8426
8427 static int
8428 intel_modeset_stage_output_state(struct drm_device *dev,
8429                                  struct drm_mode_set *set,
8430                                  struct intel_set_config *config)
8431 {
8432         struct drm_crtc *new_crtc;
8433         struct intel_connector *connector;
8434         struct intel_encoder *encoder;
8435         int count, ro;
8436
8437         /* The upper layers ensure that we either disable a crtc or have a list
8438          * of connectors. For paranoia, double-check this. */
8439         WARN_ON(!set->fb && (set->num_connectors != 0));
8440         WARN_ON(set->fb && (set->num_connectors == 0));
8441
8442         count = 0;
8443         list_for_each_entry(connector, &dev->mode_config.connector_list,
8444                             base.head) {
8445                 /* Otherwise traverse passed in connector list and get encoders
8446                  * for them. */
8447                 for (ro = 0; ro < set->num_connectors; ro++) {
8448                         if (set->connectors[ro] == &connector->base) {
8449                                 connector->new_encoder = connector->encoder;
8450                                 break;
8451                         }
8452                 }
8453
8454                 /* If we disable the crtc, disable all its connectors. Also, if
8455                  * the connector is on the changing crtc but not on the new
8456                  * connector list, disable it. */
8457                 if ((!set->fb || ro == set->num_connectors) &&
8458                     connector->base.encoder &&
8459                     connector->base.encoder->crtc == set->crtc) {
8460                         connector->new_encoder = NULL;
8461
8462                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8463                                 connector->base.base.id,
8464                                 drm_get_connector_name(&connector->base));
8465                 }
8466
8467
8468                 if (&connector->new_encoder->base != connector->base.encoder) {
8469                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8470                         config->mode_changed = true;
8471                 }
8472         }
8473         /* connector->new_encoder is now updated for all connectors. */
8474
8475         /* Update crtc of enabled connectors. */
8476         count = 0;
8477         list_for_each_entry(connector, &dev->mode_config.connector_list,
8478                             base.head) {
8479                 if (!connector->new_encoder)
8480                         continue;
8481
8482                 new_crtc = connector->new_encoder->base.crtc;
8483
8484                 for (ro = 0; ro < set->num_connectors; ro++) {
8485                         if (set->connectors[ro] == &connector->base)
8486                                 new_crtc = set->crtc;
8487                 }
8488
8489                 /* Make sure the new CRTC will work with the encoder */
8490                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8491                                            new_crtc)) {
8492                         return -EINVAL;
8493                 }
8494                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8495
8496                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8497                         connector->base.base.id,
8498                         drm_get_connector_name(&connector->base),
8499                         new_crtc->base.id);
8500         }
8501
8502         /* Check for any encoders that needs to be disabled. */
8503         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8504                             base.head) {
8505                 list_for_each_entry(connector,
8506                                     &dev->mode_config.connector_list,
8507                                     base.head) {
8508                         if (connector->new_encoder == encoder) {
8509                                 WARN_ON(!connector->new_encoder->new_crtc);
8510
8511                                 goto next_encoder;
8512                         }
8513                 }
8514                 encoder->new_crtc = NULL;
8515 next_encoder:
8516                 /* Only now check for crtc changes so we don't miss encoders
8517                  * that will be disabled. */
8518                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8519                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8520                         config->mode_changed = true;
8521                 }
8522         }
8523         /* Now we've also updated encoder->new_crtc for all encoders. */
8524
8525         return 0;
8526 }
8527
8528 static int intel_crtc_set_config(struct drm_mode_set *set)
8529 {
8530         struct drm_device *dev;
8531         struct drm_mode_set save_set;
8532         struct intel_set_config *config;
8533         int ret;
8534
8535         BUG_ON(!set);
8536         BUG_ON(!set->crtc);
8537         BUG_ON(!set->crtc->helper_private);
8538
8539         /* Enforce sane interface api - has been abused by the fb helper. */
8540         BUG_ON(!set->mode && set->fb);
8541         BUG_ON(set->fb && set->num_connectors == 0);
8542
8543         if (set->fb) {
8544                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8545                                 set->crtc->base.id, set->fb->base.id,
8546                                 (int)set->num_connectors, set->x, set->y);
8547         } else {
8548                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8549         }
8550
8551         dev = set->crtc->dev;
8552
8553         ret = -ENOMEM;
8554         config = kzalloc(sizeof(*config), GFP_KERNEL);
8555         if (!config)
8556                 goto out_config;
8557
8558         ret = intel_set_config_save_state(dev, config);
8559         if (ret)
8560                 goto out_config;
8561
8562         save_set.crtc = set->crtc;
8563         save_set.mode = &set->crtc->mode;
8564         save_set.x = set->crtc->x;
8565         save_set.y = set->crtc->y;
8566         save_set.fb = set->crtc->fb;
8567
8568         /* Compute whether we need a full modeset, only an fb base update or no
8569          * change at all. In the future we might also check whether only the
8570          * mode changed, e.g. for LVDS where we only change the panel fitter in
8571          * such cases. */
8572         intel_set_config_compute_mode_changes(set, config);
8573
8574         ret = intel_modeset_stage_output_state(dev, set, config);
8575         if (ret)
8576                 goto fail;
8577
8578         if (config->mode_changed) {
8579                 if (set->mode) {
8580                         DRM_DEBUG_KMS("attempting to set mode from"
8581                                         " userspace\n");
8582                         drm_mode_debug_printmodeline(set->mode);
8583                 }
8584
8585                 ret = intel_set_mode(set->crtc, set->mode,
8586                                      set->x, set->y, set->fb);
8587                 if (ret) {
8588                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8589                                   set->crtc->base.id, ret);
8590                         goto fail;
8591                 }
8592         } else if (config->fb_changed) {
8593                 intel_crtc_wait_for_pending_flips(set->crtc);
8594
8595                 ret = intel_pipe_set_base(set->crtc,
8596                                           set->x, set->y, set->fb);
8597         }
8598
8599         intel_set_config_free(config);
8600
8601         return 0;
8602
8603 fail:
8604         intel_set_config_restore_state(dev, config);
8605
8606         /* Try to restore the config */
8607         if (config->mode_changed &&
8608             intel_set_mode(save_set.crtc, save_set.mode,
8609                            save_set.x, save_set.y, save_set.fb))
8610                 DRM_ERROR("failed to restore config after modeset failure\n");
8611
8612 out_config:
8613         intel_set_config_free(config);
8614         return ret;
8615 }
8616
8617 static const struct drm_crtc_funcs intel_crtc_funcs = {
8618         .cursor_set = intel_crtc_cursor_set,
8619         .cursor_move = intel_crtc_cursor_move,
8620         .gamma_set = intel_crtc_gamma_set,
8621         .set_config = intel_crtc_set_config,
8622         .destroy = intel_crtc_destroy,
8623         .page_flip = intel_crtc_page_flip,
8624 };
8625
8626 static void intel_cpu_pll_init(struct drm_device *dev)
8627 {
8628         if (HAS_DDI(dev))
8629                 intel_ddi_pll_init(dev);
8630 }
8631
8632 static void intel_pch_pll_init(struct drm_device *dev)
8633 {
8634         drm_i915_private_t *dev_priv = dev->dev_private;
8635         int i;
8636
8637         if (dev_priv->num_pch_pll == 0) {
8638                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8639                 return;
8640         }
8641
8642         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8643                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8644                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8645                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8646         }
8647 }
8648
8649 static void intel_crtc_init(struct drm_device *dev, int pipe)
8650 {
8651         drm_i915_private_t *dev_priv = dev->dev_private;
8652         struct intel_crtc *intel_crtc;
8653         int i;
8654
8655         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8656         if (intel_crtc == NULL)
8657                 return;
8658
8659         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8660
8661         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8662         for (i = 0; i < 256; i++) {
8663                 intel_crtc->lut_r[i] = i;
8664                 intel_crtc->lut_g[i] = i;
8665                 intel_crtc->lut_b[i] = i;
8666         }
8667
8668         /* Swap pipes & planes for FBC on pre-965 */
8669         intel_crtc->pipe = pipe;
8670         intel_crtc->plane = pipe;
8671         intel_crtc->config.cpu_transcoder = pipe;
8672         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8673                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8674                 intel_crtc->plane = !pipe;
8675         }
8676
8677         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8678                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8679         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8680         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8681
8682         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8683 }
8684
8685 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8686                                 struct drm_file *file)
8687 {
8688         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8689         struct drm_mode_object *drmmode_obj;
8690         struct intel_crtc *crtc;
8691
8692         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8693                 return -ENODEV;
8694
8695         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8696                         DRM_MODE_OBJECT_CRTC);
8697
8698         if (!drmmode_obj) {
8699                 DRM_ERROR("no such CRTC id\n");
8700                 return -EINVAL;
8701         }
8702
8703         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8704         pipe_from_crtc_id->pipe = crtc->pipe;
8705
8706         return 0;
8707 }
8708
8709 static int intel_encoder_clones(struct intel_encoder *encoder)
8710 {
8711         struct drm_device *dev = encoder->base.dev;
8712         struct intel_encoder *source_encoder;
8713         int index_mask = 0;
8714         int entry = 0;
8715
8716         list_for_each_entry(source_encoder,
8717                             &dev->mode_config.encoder_list, base.head) {
8718
8719                 if (encoder == source_encoder)
8720                         index_mask |= (1 << entry);
8721
8722                 /* Intel hw has only one MUX where enocoders could be cloned. */
8723                 if (encoder->cloneable && source_encoder->cloneable)
8724                         index_mask |= (1 << entry);
8725
8726                 entry++;
8727         }
8728
8729         return index_mask;
8730 }
8731
8732 static bool has_edp_a(struct drm_device *dev)
8733 {
8734         struct drm_i915_private *dev_priv = dev->dev_private;
8735
8736         if (!IS_MOBILE(dev))
8737                 return false;
8738
8739         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8740                 return false;
8741
8742         if (IS_GEN5(dev) &&
8743             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8744                 return false;
8745
8746         return true;
8747 }
8748
8749 static void intel_setup_outputs(struct drm_device *dev)
8750 {
8751         struct drm_i915_private *dev_priv = dev->dev_private;
8752         struct intel_encoder *encoder;
8753         bool dpd_is_edp = false;
8754         bool has_lvds;
8755
8756         has_lvds = intel_lvds_init(dev);
8757         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8758                 /* disable the panel fitter on everything but LVDS */
8759                 I915_WRITE(PFIT_CONTROL, 0);
8760         }
8761
8762         if (!IS_ULT(dev))
8763                 intel_crt_init(dev);
8764
8765         if (HAS_DDI(dev)) {
8766                 int found;
8767
8768                 /* Haswell uses DDI functions to detect digital outputs */
8769                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8770                 /* DDI A only supports eDP */
8771                 if (found)
8772                         intel_ddi_init(dev, PORT_A);
8773
8774                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8775                  * register */
8776                 found = I915_READ(SFUSE_STRAP);
8777
8778                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8779                         intel_ddi_init(dev, PORT_B);
8780                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8781                         intel_ddi_init(dev, PORT_C);
8782                 if (found & SFUSE_STRAP_DDID_DETECTED)
8783                         intel_ddi_init(dev, PORT_D);
8784         } else if (HAS_PCH_SPLIT(dev)) {
8785                 int found;
8786                 dpd_is_edp = intel_dpd_is_edp(dev);
8787
8788                 if (has_edp_a(dev))
8789                         intel_dp_init(dev, DP_A, PORT_A);
8790
8791                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8792                         /* PCH SDVOB multiplex with HDMIB */
8793                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8794                         if (!found)
8795                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8796                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8797                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8798                 }
8799
8800                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8801                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8802
8803                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8804                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8805
8806                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8807                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8808
8809                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8810                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8811         } else if (IS_VALLEYVIEW(dev)) {
8812                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8813                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8814                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8815
8816                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8817                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8818                                         PORT_B);
8819                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8820                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8821                 }
8822         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8823                 bool found = false;
8824
8825                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8826                         DRM_DEBUG_KMS("probing SDVOB\n");
8827                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8828                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8829                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8830                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8831                         }
8832
8833                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8834                                 intel_dp_init(dev, DP_B, PORT_B);
8835                 }
8836
8837                 /* Before G4X SDVOC doesn't have its own detect register */
8838
8839                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8840                         DRM_DEBUG_KMS("probing SDVOC\n");
8841                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8842                 }
8843
8844                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8845
8846                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8847                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8848                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8849                         }
8850                         if (SUPPORTS_INTEGRATED_DP(dev))
8851                                 intel_dp_init(dev, DP_C, PORT_C);
8852                 }
8853
8854                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8855                     (I915_READ(DP_D) & DP_DETECTED))
8856                         intel_dp_init(dev, DP_D, PORT_D);
8857         } else if (IS_GEN2(dev))
8858                 intel_dvo_init(dev);
8859
8860         if (SUPPORTS_TV(dev))
8861                 intel_tv_init(dev);
8862
8863         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8864                 encoder->base.possible_crtcs = encoder->crtc_mask;
8865                 encoder->base.possible_clones =
8866                         intel_encoder_clones(encoder);
8867         }
8868
8869         intel_init_pch_refclk(dev);
8870
8871         drm_helper_move_panel_connectors_to_head(dev);
8872 }
8873
8874 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8875 {
8876         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8877
8878         drm_framebuffer_cleanup(fb);
8879         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8880
8881         kfree(intel_fb);
8882 }
8883
8884 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8885                                                 struct drm_file *file,
8886                                                 unsigned int *handle)
8887 {
8888         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8889         struct drm_i915_gem_object *obj = intel_fb->obj;
8890
8891         return drm_gem_handle_create(file, &obj->base, handle);
8892 }
8893
8894 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8895         .destroy = intel_user_framebuffer_destroy,
8896         .create_handle = intel_user_framebuffer_create_handle,
8897 };
8898
8899 int intel_framebuffer_init(struct drm_device *dev,
8900                            struct intel_framebuffer *intel_fb,
8901                            struct drm_mode_fb_cmd2 *mode_cmd,
8902                            struct drm_i915_gem_object *obj)
8903 {
8904         int ret;
8905
8906         if (obj->tiling_mode == I915_TILING_Y) {
8907                 DRM_DEBUG("hardware does not support tiling Y\n");
8908                 return -EINVAL;
8909         }
8910
8911         if (mode_cmd->pitches[0] & 63) {
8912                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8913                           mode_cmd->pitches[0]);
8914                 return -EINVAL;
8915         }
8916
8917         /* FIXME <= Gen4 stride limits are bit unclear */
8918         if (mode_cmd->pitches[0] > 32768) {
8919                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8920                           mode_cmd->pitches[0]);
8921                 return -EINVAL;
8922         }
8923
8924         if (obj->tiling_mode != I915_TILING_NONE &&
8925             mode_cmd->pitches[0] != obj->stride) {
8926                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8927                           mode_cmd->pitches[0], obj->stride);
8928                 return -EINVAL;
8929         }
8930
8931         /* Reject formats not supported by any plane early. */
8932         switch (mode_cmd->pixel_format) {
8933         case DRM_FORMAT_C8:
8934         case DRM_FORMAT_RGB565:
8935         case DRM_FORMAT_XRGB8888:
8936         case DRM_FORMAT_ARGB8888:
8937                 break;
8938         case DRM_FORMAT_XRGB1555:
8939         case DRM_FORMAT_ARGB1555:
8940                 if (INTEL_INFO(dev)->gen > 3) {
8941                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8942                         return -EINVAL;
8943                 }
8944                 break;
8945         case DRM_FORMAT_XBGR8888:
8946         case DRM_FORMAT_ABGR8888:
8947         case DRM_FORMAT_XRGB2101010:
8948         case DRM_FORMAT_ARGB2101010:
8949         case DRM_FORMAT_XBGR2101010:
8950         case DRM_FORMAT_ABGR2101010:
8951                 if (INTEL_INFO(dev)->gen < 4) {
8952                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8953                         return -EINVAL;
8954                 }
8955                 break;
8956         case DRM_FORMAT_YUYV:
8957         case DRM_FORMAT_UYVY:
8958         case DRM_FORMAT_YVYU:
8959         case DRM_FORMAT_VYUY:
8960                 if (INTEL_INFO(dev)->gen < 5) {
8961                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8962                         return -EINVAL;
8963                 }
8964                 break;
8965         default:
8966                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8967                 return -EINVAL;
8968         }
8969
8970         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8971         if (mode_cmd->offsets[0] != 0)
8972                 return -EINVAL;
8973
8974         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8975         intel_fb->obj = obj;
8976
8977         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8978         if (ret) {
8979                 DRM_ERROR("framebuffer init failed %d\n", ret);
8980                 return ret;
8981         }
8982
8983         return 0;
8984 }
8985
8986 static struct drm_framebuffer *
8987 intel_user_framebuffer_create(struct drm_device *dev,
8988                               struct drm_file *filp,
8989                               struct drm_mode_fb_cmd2 *mode_cmd)
8990 {
8991         struct drm_i915_gem_object *obj;
8992
8993         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8994                                                 mode_cmd->handles[0]));
8995         if (&obj->base == NULL)
8996                 return ERR_PTR(-ENOENT);
8997
8998         return intel_framebuffer_create(dev, mode_cmd, obj);
8999 }
9000
9001 static const struct drm_mode_config_funcs intel_mode_funcs = {
9002         .fb_create = intel_user_framebuffer_create,
9003         .output_poll_changed = intel_fb_output_poll_changed,
9004 };
9005
9006 /* Set up chip specific display functions */
9007 static void intel_init_display(struct drm_device *dev)
9008 {
9009         struct drm_i915_private *dev_priv = dev->dev_private;
9010
9011         if (HAS_DDI(dev)) {
9012                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9013                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9014                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9015                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9016                 dev_priv->display.off = haswell_crtc_off;
9017                 dev_priv->display.update_plane = ironlake_update_plane;
9018         } else if (HAS_PCH_SPLIT(dev)) {
9019                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9020                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9021                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9022                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9023                 dev_priv->display.off = ironlake_crtc_off;
9024                 dev_priv->display.update_plane = ironlake_update_plane;
9025         } else if (IS_VALLEYVIEW(dev)) {
9026                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9027                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9028                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9029                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9030                 dev_priv->display.off = i9xx_crtc_off;
9031                 dev_priv->display.update_plane = i9xx_update_plane;
9032         } else {
9033                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9034                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9035                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9036                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9037                 dev_priv->display.off = i9xx_crtc_off;
9038                 dev_priv->display.update_plane = i9xx_update_plane;
9039         }
9040
9041         /* Returns the core display clock speed */
9042         if (IS_VALLEYVIEW(dev))
9043                 dev_priv->display.get_display_clock_speed =
9044                         valleyview_get_display_clock_speed;
9045         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9046                 dev_priv->display.get_display_clock_speed =
9047                         i945_get_display_clock_speed;
9048         else if (IS_I915G(dev))
9049                 dev_priv->display.get_display_clock_speed =
9050                         i915_get_display_clock_speed;
9051         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9052                 dev_priv->display.get_display_clock_speed =
9053                         i9xx_misc_get_display_clock_speed;
9054         else if (IS_I915GM(dev))
9055                 dev_priv->display.get_display_clock_speed =
9056                         i915gm_get_display_clock_speed;
9057         else if (IS_I865G(dev))
9058                 dev_priv->display.get_display_clock_speed =
9059                         i865_get_display_clock_speed;
9060         else if (IS_I85X(dev))
9061                 dev_priv->display.get_display_clock_speed =
9062                         i855_get_display_clock_speed;
9063         else /* 852, 830 */
9064                 dev_priv->display.get_display_clock_speed =
9065                         i830_get_display_clock_speed;
9066
9067         if (HAS_PCH_SPLIT(dev)) {
9068                 if (IS_GEN5(dev)) {
9069                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9070                         dev_priv->display.write_eld = ironlake_write_eld;
9071                 } else if (IS_GEN6(dev)) {
9072                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9073                         dev_priv->display.write_eld = ironlake_write_eld;
9074                 } else if (IS_IVYBRIDGE(dev)) {
9075                         /* FIXME: detect B0+ stepping and use auto training */
9076                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9077                         dev_priv->display.write_eld = ironlake_write_eld;
9078                         dev_priv->display.modeset_global_resources =
9079                                 ivb_modeset_global_resources;
9080                 } else if (IS_HASWELL(dev)) {
9081                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9082                         dev_priv->display.write_eld = haswell_write_eld;
9083                         dev_priv->display.modeset_global_resources =
9084                                 haswell_modeset_global_resources;
9085                 }
9086         } else if (IS_G4X(dev)) {
9087                 dev_priv->display.write_eld = g4x_write_eld;
9088         }
9089
9090         /* Default just returns -ENODEV to indicate unsupported */
9091         dev_priv->display.queue_flip = intel_default_queue_flip;
9092
9093         switch (INTEL_INFO(dev)->gen) {
9094         case 2:
9095                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9096                 break;
9097
9098         case 3:
9099                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9100                 break;
9101
9102         case 4:
9103         case 5:
9104                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9105                 break;
9106
9107         case 6:
9108                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9109                 break;
9110         case 7:
9111                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9112                 break;
9113         }
9114 }
9115
9116 /*
9117  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9118  * resume, or other times.  This quirk makes sure that's the case for
9119  * affected systems.
9120  */
9121 static void quirk_pipea_force(struct drm_device *dev)
9122 {
9123         struct drm_i915_private *dev_priv = dev->dev_private;
9124
9125         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9126         DRM_INFO("applying pipe a force quirk\n");
9127 }
9128
9129 /*
9130  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9131  */
9132 static void quirk_ssc_force_disable(struct drm_device *dev)
9133 {
9134         struct drm_i915_private *dev_priv = dev->dev_private;
9135         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9136         DRM_INFO("applying lvds SSC disable quirk\n");
9137 }
9138
9139 /*
9140  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9141  * brightness value
9142  */
9143 static void quirk_invert_brightness(struct drm_device *dev)
9144 {
9145         struct drm_i915_private *dev_priv = dev->dev_private;
9146         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9147         DRM_INFO("applying inverted panel brightness quirk\n");
9148 }
9149
9150 struct intel_quirk {
9151         int device;
9152         int subsystem_vendor;
9153         int subsystem_device;
9154         void (*hook)(struct drm_device *dev);
9155 };
9156
9157 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9158 struct intel_dmi_quirk {
9159         void (*hook)(struct drm_device *dev);
9160         const struct dmi_system_id (*dmi_id_list)[];
9161 };
9162
9163 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9164 {
9165         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9166         return 1;
9167 }
9168
9169 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9170         {
9171                 .dmi_id_list = &(const struct dmi_system_id[]) {
9172                         {
9173                                 .callback = intel_dmi_reverse_brightness,
9174                                 .ident = "NCR Corporation",
9175                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9176                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9177                                 },
9178                         },
9179                         { }  /* terminating entry */
9180                 },
9181                 .hook = quirk_invert_brightness,
9182         },
9183 };
9184
9185 static struct intel_quirk intel_quirks[] = {
9186         /* HP Mini needs pipe A force quirk (LP: #322104) */
9187         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9188
9189         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9190         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9191
9192         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9193         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9194
9195         /* 830/845 need to leave pipe A & dpll A up */
9196         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9197         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9198
9199         /* Lenovo U160 cannot use SSC on LVDS */
9200         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9201
9202         /* Sony Vaio Y cannot use SSC on LVDS */
9203         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9204
9205         /* Acer Aspire 5734Z must invert backlight brightness */
9206         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9207
9208         /* Acer/eMachines G725 */
9209         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9210
9211         /* Acer/eMachines e725 */
9212         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9213
9214         /* Acer/Packard Bell NCL20 */
9215         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9216
9217         /* Acer Aspire 4736Z */
9218         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9219 };
9220
9221 static void intel_init_quirks(struct drm_device *dev)
9222 {
9223         struct pci_dev *d = dev->pdev;
9224         int i;
9225
9226         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9227                 struct intel_quirk *q = &intel_quirks[i];
9228
9229                 if (d->device == q->device &&
9230                     (d->subsystem_vendor == q->subsystem_vendor ||
9231                      q->subsystem_vendor == PCI_ANY_ID) &&
9232                     (d->subsystem_device == q->subsystem_device ||
9233                      q->subsystem_device == PCI_ANY_ID))
9234                         q->hook(dev);
9235         }
9236         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9237                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9238                         intel_dmi_quirks[i].hook(dev);
9239         }
9240 }
9241
9242 /* Disable the VGA plane that we never use */
9243 static void i915_disable_vga(struct drm_device *dev)
9244 {
9245         struct drm_i915_private *dev_priv = dev->dev_private;
9246         u8 sr1;
9247         u32 vga_reg = i915_vgacntrl_reg(dev);
9248
9249         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9250         outb(SR01, VGA_SR_INDEX);
9251         sr1 = inb(VGA_SR_DATA);
9252         outb(sr1 | 1<<5, VGA_SR_DATA);
9253         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9254         udelay(300);
9255
9256         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9257         POSTING_READ(vga_reg);
9258 }
9259
9260 void intel_modeset_init_hw(struct drm_device *dev)
9261 {
9262         intel_init_power_well(dev);
9263
9264         intel_prepare_ddi(dev);
9265
9266         intel_init_clock_gating(dev);
9267
9268         mutex_lock(&dev->struct_mutex);
9269         intel_enable_gt_powersave(dev);
9270         mutex_unlock(&dev->struct_mutex);
9271 }
9272
9273 void intel_modeset_suspend_hw(struct drm_device *dev)
9274 {
9275         intel_suspend_hw(dev);
9276 }
9277
9278 void intel_modeset_init(struct drm_device *dev)
9279 {
9280         struct drm_i915_private *dev_priv = dev->dev_private;
9281         int i, j, ret;
9282
9283         drm_mode_config_init(dev);
9284
9285         dev->mode_config.min_width = 0;
9286         dev->mode_config.min_height = 0;
9287
9288         dev->mode_config.preferred_depth = 24;
9289         dev->mode_config.prefer_shadow = 1;
9290
9291         dev->mode_config.funcs = &intel_mode_funcs;
9292
9293         intel_init_quirks(dev);
9294
9295         intel_init_pm(dev);
9296
9297         if (INTEL_INFO(dev)->num_pipes == 0)
9298                 return;
9299
9300         intel_init_display(dev);
9301
9302         if (IS_GEN2(dev)) {
9303                 dev->mode_config.max_width = 2048;
9304                 dev->mode_config.max_height = 2048;
9305         } else if (IS_GEN3(dev)) {
9306                 dev->mode_config.max_width = 4096;
9307                 dev->mode_config.max_height = 4096;
9308         } else {
9309                 dev->mode_config.max_width = 8192;
9310                 dev->mode_config.max_height = 8192;
9311         }
9312         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9313
9314         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9315                       INTEL_INFO(dev)->num_pipes,
9316                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9317
9318         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9319                 intel_crtc_init(dev, i);
9320                 for (j = 0; j < dev_priv->num_plane; j++) {
9321                         ret = intel_plane_init(dev, i, j);
9322                         if (ret)
9323                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9324                                               pipe_name(i), sprite_name(i, j), ret);
9325                 }
9326         }
9327
9328         intel_cpu_pll_init(dev);
9329         intel_pch_pll_init(dev);
9330
9331         /* Just disable it once at startup */
9332         i915_disable_vga(dev);
9333         intel_setup_outputs(dev);
9334
9335         /* Just in case the BIOS is doing something questionable. */
9336         intel_disable_fbc(dev);
9337 }
9338
9339 static void
9340 intel_connector_break_all_links(struct intel_connector *connector)
9341 {
9342         connector->base.dpms = DRM_MODE_DPMS_OFF;
9343         connector->base.encoder = NULL;
9344         connector->encoder->connectors_active = false;
9345         connector->encoder->base.crtc = NULL;
9346 }
9347
9348 static void intel_enable_pipe_a(struct drm_device *dev)
9349 {
9350         struct intel_connector *connector;
9351         struct drm_connector *crt = NULL;
9352         struct intel_load_detect_pipe load_detect_temp;
9353
9354         /* We can't just switch on the pipe A, we need to set things up with a
9355          * proper mode and output configuration. As a gross hack, enable pipe A
9356          * by enabling the load detect pipe once. */
9357         list_for_each_entry(connector,
9358                             &dev->mode_config.connector_list,
9359                             base.head) {
9360                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9361                         crt = &connector->base;
9362                         break;
9363                 }
9364         }
9365
9366         if (!crt)
9367                 return;
9368
9369         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9370                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9371
9372
9373 }
9374
9375 static bool
9376 intel_check_plane_mapping(struct intel_crtc *crtc)
9377 {
9378         struct drm_device *dev = crtc->base.dev;
9379         struct drm_i915_private *dev_priv = dev->dev_private;
9380         u32 reg, val;
9381
9382         if (INTEL_INFO(dev)->num_pipes == 1)
9383                 return true;
9384
9385         reg = DSPCNTR(!crtc->plane);
9386         val = I915_READ(reg);
9387
9388         if ((val & DISPLAY_PLANE_ENABLE) &&
9389             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9390                 return false;
9391
9392         return true;
9393 }
9394
9395 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9396 {
9397         struct drm_device *dev = crtc->base.dev;
9398         struct drm_i915_private *dev_priv = dev->dev_private;
9399         u32 reg;
9400
9401         /* Clear any frame start delays used for debugging left by the BIOS */
9402         reg = PIPECONF(crtc->config.cpu_transcoder);
9403         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9404
9405         /* We need to sanitize the plane -> pipe mapping first because this will
9406          * disable the crtc (and hence change the state) if it is wrong. Note
9407          * that gen4+ has a fixed plane -> pipe mapping.  */
9408         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9409                 struct intel_connector *connector;
9410                 bool plane;
9411
9412                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9413                               crtc->base.base.id);
9414
9415                 /* Pipe has the wrong plane attached and the plane is active.
9416                  * Temporarily change the plane mapping and disable everything
9417                  * ...  */
9418                 plane = crtc->plane;
9419                 crtc->plane = !plane;
9420                 dev_priv->display.crtc_disable(&crtc->base);
9421                 crtc->plane = plane;
9422
9423                 /* ... and break all links. */
9424                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9425                                     base.head) {
9426                         if (connector->encoder->base.crtc != &crtc->base)
9427                                 continue;
9428
9429                         intel_connector_break_all_links(connector);
9430                 }
9431
9432                 WARN_ON(crtc->active);
9433                 crtc->base.enabled = false;
9434         }
9435
9436         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9437             crtc->pipe == PIPE_A && !crtc->active) {
9438                 /* BIOS forgot to enable pipe A, this mostly happens after
9439                  * resume. Force-enable the pipe to fix this, the update_dpms
9440                  * call below we restore the pipe to the right state, but leave
9441                  * the required bits on. */
9442                 intel_enable_pipe_a(dev);
9443         }
9444
9445         /* Adjust the state of the output pipe according to whether we
9446          * have active connectors/encoders. */
9447         intel_crtc_update_dpms(&crtc->base);
9448
9449         if (crtc->active != crtc->base.enabled) {
9450                 struct intel_encoder *encoder;
9451
9452                 /* This can happen either due to bugs in the get_hw_state
9453                  * functions or because the pipe is force-enabled due to the
9454                  * pipe A quirk. */
9455                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9456                               crtc->base.base.id,
9457                               crtc->base.enabled ? "enabled" : "disabled",
9458                               crtc->active ? "enabled" : "disabled");
9459
9460                 crtc->base.enabled = crtc->active;
9461
9462                 /* Because we only establish the connector -> encoder ->
9463                  * crtc links if something is active, this means the
9464                  * crtc is now deactivated. Break the links. connector
9465                  * -> encoder links are only establish when things are
9466                  *  actually up, hence no need to break them. */
9467                 WARN_ON(crtc->active);
9468
9469                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9470                         WARN_ON(encoder->connectors_active);
9471                         encoder->base.crtc = NULL;
9472                 }
9473         }
9474 }
9475
9476 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9477 {
9478         struct intel_connector *connector;
9479         struct drm_device *dev = encoder->base.dev;
9480
9481         /* We need to check both for a crtc link (meaning that the
9482          * encoder is active and trying to read from a pipe) and the
9483          * pipe itself being active. */
9484         bool has_active_crtc = encoder->base.crtc &&
9485                 to_intel_crtc(encoder->base.crtc)->active;
9486
9487         if (encoder->connectors_active && !has_active_crtc) {
9488                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9489                               encoder->base.base.id,
9490                               drm_get_encoder_name(&encoder->base));
9491
9492                 /* Connector is active, but has no active pipe. This is
9493                  * fallout from our resume register restoring. Disable
9494                  * the encoder manually again. */
9495                 if (encoder->base.crtc) {
9496                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9497                                       encoder->base.base.id,
9498                                       drm_get_encoder_name(&encoder->base));
9499                         encoder->disable(encoder);
9500                 }
9501
9502                 /* Inconsistent output/port/pipe state happens presumably due to
9503                  * a bug in one of the get_hw_state functions. Or someplace else
9504                  * in our code, like the register restore mess on resume. Clamp
9505                  * things to off as a safer default. */
9506                 list_for_each_entry(connector,
9507                                     &dev->mode_config.connector_list,
9508                                     base.head) {
9509                         if (connector->encoder != encoder)
9510                                 continue;
9511
9512                         intel_connector_break_all_links(connector);
9513                 }
9514         }
9515         /* Enabled encoders without active connectors will be fixed in
9516          * the crtc fixup. */
9517 }
9518
9519 void i915_redisable_vga(struct drm_device *dev)
9520 {
9521         struct drm_i915_private *dev_priv = dev->dev_private;
9522         u32 vga_reg = i915_vgacntrl_reg(dev);
9523
9524         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9525                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9526                 i915_disable_vga(dev);
9527         }
9528 }
9529
9530 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9531  * and i915 state tracking structures. */
9532 void intel_modeset_setup_hw_state(struct drm_device *dev,
9533                                   bool force_restore)
9534 {
9535         struct drm_i915_private *dev_priv = dev->dev_private;
9536         enum pipe pipe;
9537         u32 tmp;
9538         struct drm_plane *plane;
9539         struct intel_crtc *crtc;
9540         struct intel_encoder *encoder;
9541         struct intel_connector *connector;
9542
9543         if (HAS_DDI(dev)) {
9544                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9545
9546                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9547                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9548                         case TRANS_DDI_EDP_INPUT_A_ON:
9549                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9550                                 pipe = PIPE_A;
9551                                 break;
9552                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9553                                 pipe = PIPE_B;
9554                                 break;
9555                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9556                                 pipe = PIPE_C;
9557                                 break;
9558                         default:
9559                                 /* A bogus value has been programmed, disable
9560                                  * the transcoder */
9561                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9562                                 intel_ddi_disable_transcoder_func(dev_priv,
9563                                                 TRANSCODER_EDP);
9564                                 goto setup_pipes;
9565                         }
9566
9567                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9568                         crtc->config.cpu_transcoder = TRANSCODER_EDP;
9569
9570                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9571                                       pipe_name(pipe));
9572                 }
9573         }
9574
9575 setup_pipes:
9576         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9577                             base.head) {
9578                 enum transcoder tmp = crtc->config.cpu_transcoder;
9579                 memset(&crtc->config, 0, sizeof(crtc->config));
9580                 crtc->config.cpu_transcoder = tmp;
9581
9582                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9583                                                                  &crtc->config);
9584
9585                 crtc->base.enabled = crtc->active;
9586
9587                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9588                               crtc->base.base.id,
9589                               crtc->active ? "enabled" : "disabled");
9590         }
9591
9592         if (HAS_DDI(dev))
9593                 intel_ddi_setup_hw_pll_state(dev);
9594
9595         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9596                             base.head) {
9597                 pipe = 0;
9598
9599                 if (encoder->get_hw_state(encoder, &pipe)) {
9600                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9601                         encoder->base.crtc = &crtc->base;
9602                         if (encoder->get_config)
9603                                 encoder->get_config(encoder, &crtc->config);
9604                 } else {
9605                         encoder->base.crtc = NULL;
9606                 }
9607
9608                 encoder->connectors_active = false;
9609                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9610                               encoder->base.base.id,
9611                               drm_get_encoder_name(&encoder->base),
9612                               encoder->base.crtc ? "enabled" : "disabled",
9613                               pipe);
9614         }
9615
9616         list_for_each_entry(connector, &dev->mode_config.connector_list,
9617                             base.head) {
9618                 if (connector->get_hw_state(connector)) {
9619                         connector->base.dpms = DRM_MODE_DPMS_ON;
9620                         connector->encoder->connectors_active = true;
9621                         connector->base.encoder = &connector->encoder->base;
9622                 } else {
9623                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9624                         connector->base.encoder = NULL;
9625                 }
9626                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9627                               connector->base.base.id,
9628                               drm_get_connector_name(&connector->base),
9629                               connector->base.encoder ? "enabled" : "disabled");
9630         }
9631
9632         /* HW state is read out, now we need to sanitize this mess. */
9633         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9634                             base.head) {
9635                 intel_sanitize_encoder(encoder);
9636         }
9637
9638         for_each_pipe(pipe) {
9639                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9640                 intel_sanitize_crtc(crtc);
9641         }
9642
9643         if (force_restore) {
9644                 /*
9645                  * We need to use raw interfaces for restoring state to avoid
9646                  * checking (bogus) intermediate states.
9647                  */
9648                 for_each_pipe(pipe) {
9649                         struct drm_crtc *crtc =
9650                                 dev_priv->pipe_to_crtc_mapping[pipe];
9651
9652                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9653                                          crtc->fb);
9654                 }
9655                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9656                         intel_plane_restore(plane);
9657
9658                 i915_redisable_vga(dev);
9659         } else {
9660                 intel_modeset_update_staged_output_state(dev);
9661         }
9662
9663         intel_modeset_check_state(dev);
9664
9665         drm_mode_config_reset(dev);
9666 }
9667
9668 void intel_modeset_gem_init(struct drm_device *dev)
9669 {
9670         intel_modeset_init_hw(dev);
9671
9672         intel_setup_overlay(dev);
9673
9674         intel_modeset_setup_hw_state(dev, false);
9675 }
9676
9677 void intel_modeset_cleanup(struct drm_device *dev)
9678 {
9679         struct drm_i915_private *dev_priv = dev->dev_private;
9680         struct drm_crtc *crtc;
9681         struct intel_crtc *intel_crtc;
9682
9683         /*
9684          * Interrupts and polling as the first thing to avoid creating havoc.
9685          * Too much stuff here (turning of rps, connectors, ...) would
9686          * experience fancy races otherwise.
9687          */
9688         drm_irq_uninstall(dev);
9689         cancel_work_sync(&dev_priv->hotplug_work);
9690         /*
9691          * Due to the hpd irq storm handling the hotplug work can re-arm the
9692          * poll handlers. Hence disable polling after hpd handling is shut down.
9693          */
9694         drm_kms_helper_poll_fini(dev);
9695
9696         mutex_lock(&dev->struct_mutex);
9697
9698         intel_unregister_dsm_handler();
9699
9700         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9701                 /* Skip inactive CRTCs */
9702                 if (!crtc->fb)
9703                         continue;
9704
9705                 intel_crtc = to_intel_crtc(crtc);
9706                 intel_increase_pllclock(crtc);
9707         }
9708
9709         intel_disable_fbc(dev);
9710
9711         intel_disable_gt_powersave(dev);
9712
9713         ironlake_teardown_rc6(dev);
9714
9715         mutex_unlock(&dev->struct_mutex);
9716
9717         /* flush any delayed tasks or pending work */
9718         flush_scheduled_work();
9719
9720         /* destroy backlight, if any, before the connectors */
9721         intel_panel_destroy_backlight(dev);
9722
9723         drm_mode_config_cleanup(dev);
9724
9725         intel_cleanup_overlay(dev);
9726 }
9727
9728 /*
9729  * Return which encoder is currently attached for connector.
9730  */
9731 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9732 {
9733         return &intel_attached_encoder(connector)->base;
9734 }
9735
9736 void intel_connector_attach_encoder(struct intel_connector *connector,
9737                                     struct intel_encoder *encoder)
9738 {
9739         connector->encoder = encoder;
9740         drm_mode_connector_attach_encoder(&connector->base,
9741                                           &encoder->base);
9742 }
9743
9744 /*
9745  * set vga decode state - true == enable VGA decode
9746  */
9747 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9748 {
9749         struct drm_i915_private *dev_priv = dev->dev_private;
9750         u16 gmch_ctrl;
9751
9752         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9753         if (state)
9754                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9755         else
9756                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9757         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9758         return 0;
9759 }
9760
9761 #ifdef CONFIG_DEBUG_FS
9762 #include <linux/seq_file.h>
9763
9764 struct intel_display_error_state {
9765
9766         u32 power_well_driver;
9767
9768         struct intel_cursor_error_state {
9769                 u32 control;
9770                 u32 position;
9771                 u32 base;
9772                 u32 size;
9773         } cursor[I915_MAX_PIPES];
9774
9775         struct intel_pipe_error_state {
9776                 enum transcoder cpu_transcoder;
9777                 u32 conf;
9778                 u32 source;
9779
9780                 u32 htotal;
9781                 u32 hblank;
9782                 u32 hsync;
9783                 u32 vtotal;
9784                 u32 vblank;
9785                 u32 vsync;
9786         } pipe[I915_MAX_PIPES];
9787
9788         struct intel_plane_error_state {
9789                 u32 control;
9790                 u32 stride;
9791                 u32 size;
9792                 u32 pos;
9793                 u32 addr;
9794                 u32 surface;
9795                 u32 tile_offset;
9796         } plane[I915_MAX_PIPES];
9797 };
9798
9799 struct intel_display_error_state *
9800 intel_display_capture_error_state(struct drm_device *dev)
9801 {
9802         drm_i915_private_t *dev_priv = dev->dev_private;
9803         struct intel_display_error_state *error;
9804         enum transcoder cpu_transcoder;
9805         int i;
9806
9807         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9808         if (error == NULL)
9809                 return NULL;
9810
9811         if (HAS_POWER_WELL(dev))
9812                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9813
9814         for_each_pipe(i) {
9815                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9816                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9817
9818                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9819                         error->cursor[i].control = I915_READ(CURCNTR(i));
9820                         error->cursor[i].position = I915_READ(CURPOS(i));
9821                         error->cursor[i].base = I915_READ(CURBASE(i));
9822                 } else {
9823                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9824                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9825                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9826                 }
9827
9828                 error->plane[i].control = I915_READ(DSPCNTR(i));
9829                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9830                 if (INTEL_INFO(dev)->gen <= 3) {
9831                         error->plane[i].size = I915_READ(DSPSIZE(i));
9832                         error->plane[i].pos = I915_READ(DSPPOS(i));
9833                 }
9834                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9835                         error->plane[i].addr = I915_READ(DSPADDR(i));
9836                 if (INTEL_INFO(dev)->gen >= 4) {
9837                         error->plane[i].surface = I915_READ(DSPSURF(i));
9838                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9839                 }
9840
9841                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9842                 error->pipe[i].source = I915_READ(PIPESRC(i));
9843                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9844                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9845                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9846                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9847                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9848                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9849         }
9850
9851         /* In the code above we read the registers without checking if the power
9852          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9853          * prevent the next I915_WRITE from detecting it and printing an error
9854          * message. */
9855         if (HAS_POWER_WELL(dev))
9856                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9857
9858         return error;
9859 }
9860
9861 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9862
9863 void
9864 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9865                                 struct drm_device *dev,
9866                                 struct intel_display_error_state *error)
9867 {
9868         int i;
9869
9870         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9871         if (HAS_POWER_WELL(dev))
9872                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9873                            error->power_well_driver);
9874         for_each_pipe(i) {
9875                 err_printf(m, "Pipe [%d]:\n", i);
9876                 err_printf(m, "  CPU transcoder: %c\n",
9877                            transcoder_name(error->pipe[i].cpu_transcoder));
9878                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9879                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9880                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9881                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9882                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9883                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9884                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9885                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9886
9887                 err_printf(m, "Plane [%d]:\n", i);
9888                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9889                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9890                 if (INTEL_INFO(dev)->gen <= 3) {
9891                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9892                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9893                 }
9894                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9895                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9896                 if (INTEL_INFO(dev)->gen >= 4) {
9897                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9898                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9899                 }
9900
9901                 err_printf(m, "Cursor [%d]:\n", i);
9902                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9903                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9904                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9905         }
9906 }
9907 #endif