2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
28 #include <uapi/drm/i915_drm.h>
30 #include "intel_step.h"
32 #include "display/intel_display_device.h"
34 #include "gt/intel_engine_types.h"
35 #include "gt/intel_context_types.h"
36 #include "gt/intel_sseu.h"
38 #include "gem/i915_gem_object_types.h"
41 struct drm_i915_private;
42 struct intel_gt_definition;
44 /* Keep in gen based order, and chronological order within a gen */
46 INTEL_PLATFORM_UNINITIALIZED = 0,
100 * Subplatform bits share the same namespace per parent platform. In other words
101 * it is fine for the same bit to be used on multiple parent platforms.
104 #define INTEL_SUBPLATFORM_BITS (3)
105 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
107 /* HSW/BDW/SKL/KBL/CFL */
108 #define INTEL_SUBPLATFORM_ULT (0)
109 #define INTEL_SUBPLATFORM_ULX (1)
112 #define INTEL_SUBPLATFORM_PORTF (0)
115 #define INTEL_SUBPLATFORM_UY (0)
118 #define INTEL_SUBPLATFORM_G10 0
119 #define INTEL_SUBPLATFORM_G11 1
120 #define INTEL_SUBPLATFORM_G12 2
123 #define INTEL_SUBPLATFORM_RPL 0
127 * As #define INTEL_SUBPLATFORM_RPL 0 will apply
128 * here too, SUBPLATFORM_N will have different
131 #define INTEL_SUBPLATFORM_N 1
132 #define INTEL_SUBPLATFORM_RPLU 2
135 #define INTEL_SUBPLATFORM_M 0
136 #define INTEL_SUBPLATFORM_P 1
138 enum intel_ppgtt_type {
139 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
140 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
141 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
144 #define DEV_INFO_FOR_EACH_FLAG(func) \
147 func(require_force_probe); \
149 /* Keep has_* in alphabetical order */ \
150 func(has_64bit_reloc); \
151 func(has_64k_pages); \
152 func(gpu_reset_clobbers_display); \
153 func(has_reset_engine); \
154 func(has_3d_pipeline); \
156 func(has_flat_ccs); \
157 func(has_global_mocs); \
160 func(has_heci_pxp); \
161 func(has_heci_gscfi); \
162 func(has_guc_deprivilege); \
163 func(has_l3_ccs_read); \
166 func(has_logical_ring_contexts); \
167 func(has_logical_ring_elsq); \
168 func(has_media_ratio_mode); \
169 func(has_mslice_steering); \
170 func(has_oa_bpc_reporting); \
171 func(has_oa_slice_contrib_limits); \
173 func(has_one_eu_per_fuse_bit); \
178 func(has_runtime_pm); \
180 func(has_coherent_ggtt); \
181 func(tuning_thread_rr_after_dep); \
182 func(unfenced_needs_alignment); \
183 func(hws_needs_physical);
185 struct intel_ip_version {
191 struct intel_runtime_info {
193 * Single "graphics" IP version that represents
194 * render, compute and copy behavior.
197 struct intel_ip_version ip;
200 struct intel_ip_version ip;
204 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
205 * single runtime conditionals, and also to provide groundwork for
206 * future per platform, or per SKU build optimizations.
208 * Array can be extended when necessary if the corresponding
209 * BUILD_BUG_ON is hit.
211 u32 platform_mask[2];
217 struct intel_step_info step;
219 unsigned int page_sizes; /* page sizes supported by the HW */
221 enum intel_ppgtt_type ppgtt_type;
222 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
227 struct intel_device_info {
228 enum intel_platform platform;
230 unsigned int dma_mask_size; /* available DMA address bits */
232 const struct intel_gt_definition *extra_gt_list;
234 u8 gt; /* GT number, 0 if undefined */
236 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
237 u32 memory_regions; /* regions supported by the HW */
239 #define DEFINE_FLAG(name) u8 name:1
240 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
243 const struct intel_display_device_info *display;
246 * Initial runtime info. Do not access outside of i915_driver_create().
248 const struct intel_runtime_info __runtime;
250 u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];
254 struct intel_driver_caps {
255 unsigned int scheduler;
256 bool has_logical_contexts:1;
259 const char *intel_platform_name(enum intel_platform platform);
261 void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id,
262 const struct intel_device_info *match_info);
263 void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
264 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
266 void intel_device_info_print(const struct intel_device_info *info,
267 const struct intel_runtime_info *runtime,
268 struct drm_printer *p);
270 void intel_driver_caps_print(const struct intel_driver_caps *caps,
271 struct drm_printer *p);