drivers/gpu/drm/i915/intel_device_info.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/string_helpers.h>
  26
  27 #include <drm/drm_print.h>
  28 #include <drm/i915_pciids.h>
  29
  30 #include "display/intel_cdclk.h"
  31 #include "display/intel_de.h"
  32 #include "intel_device_info.h"
  33 #include "i915_drv.h"
  34 #include "i915_utils.h"
  35
  36 #define PLATFORM_NAME(x) [INTEL_##x] = #x
  37 static const char * const platform_names[] = {
  38         PLATFORM_NAME(I830),
  39         PLATFORM_NAME(I845G),
  40         PLATFORM_NAME(I85X),
  41         PLATFORM_NAME(I865G),
  42         PLATFORM_NAME(I915G),
  43         PLATFORM_NAME(I915GM),
  44         PLATFORM_NAME(I945G),
  45         PLATFORM_NAME(I945GM),
  46         PLATFORM_NAME(G33),
  47         PLATFORM_NAME(PINEVIEW),
  48         PLATFORM_NAME(I965G),
  49         PLATFORM_NAME(I965GM),
  50         PLATFORM_NAME(G45),
  51         PLATFORM_NAME(GM45),
  52         PLATFORM_NAME(IRONLAKE),
  53         PLATFORM_NAME(SANDYBRIDGE),
  54         PLATFORM_NAME(IVYBRIDGE),
  55         PLATFORM_NAME(VALLEYVIEW),
  56         PLATFORM_NAME(HASWELL),
  57         PLATFORM_NAME(BROADWELL),
  58         PLATFORM_NAME(CHERRYVIEW),
  59         PLATFORM_NAME(SKYLAKE),
  60         PLATFORM_NAME(BROXTON),
  61         PLATFORM_NAME(KABYLAKE),
  62         PLATFORM_NAME(GEMINILAKE),
  63         PLATFORM_NAME(COFFEELAKE),
  64         PLATFORM_NAME(COMETLAKE),
  65         PLATFORM_NAME(ICELAKE),
  66         PLATFORM_NAME(ELKHARTLAKE),
  67         PLATFORM_NAME(JASPERLAKE),
  68         PLATFORM_NAME(TIGERLAKE),
  69         PLATFORM_NAME(ROCKETLAKE),
  70         PLATFORM_NAME(DG1),
  71         PLATFORM_NAME(ALDERLAKE_S),
  72         PLATFORM_NAME(ALDERLAKE_P),
  73         PLATFORM_NAME(XEHPSDV),
  74         PLATFORM_NAME(DG2),
  75         PLATFORM_NAME(PONTEVECCHIO),
  76         PLATFORM_NAME(METEORLAKE),
  77 };
  78 #undef PLATFORM_NAME
  79
  80 const char *intel_platform_name(enum intel_platform platform)
  81 {
  82         BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  83
  84         if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  85                          platform_names[platform] == NULL))
  86                 return "<unknown>";
  87
  88         return platform_names[platform];
  89 }
  90
  91 void intel_device_info_print(const struct intel_device_info *info,
  92                              const struct intel_runtime_info *runtime,
  93                              struct drm_printer *p)
  94 {
  95         if (runtime->graphics.rel)
  96                 drm_printf(p, "graphics version: %u.%02u\n", runtime->graphics.ver,
  97                            runtime->graphics.rel);
  98         else
  99                 drm_printf(p, "graphics version: %u\n", runtime->graphics.ver);
 100
 101         if (info->media.rel)
 102                 drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel);
 103         else
 104                 drm_printf(p, "media version: %u\n", info->media.ver);
 105
 106         if (info->display.rel)
 107                 drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel);
 108         else
 109                 drm_printf(p, "display version: %u\n", info->display.ver);
 110
 111         drm_printf(p, "gt: %d\n", info->gt);
 112         drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
 113         drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
 114         drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
 115         drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
 116         drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
 117         drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
 118
 119 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
 120         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 121 #undef PRINT_FLAG
 122
 123         drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
 124
 125 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
 126         DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
 127 #undef PRINT_FLAG
 128
 129         drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 130 }
 131
 132 #undef INTEL_VGA_DEVICE
 133 #define INTEL_VGA_DEVICE(id, info) (id)
 134
 135 static const u16 subplatform_ult_ids[] = {
 136         INTEL_HSW_ULT_GT1_IDS(0),
 137         INTEL_HSW_ULT_GT2_IDS(0),
 138         INTEL_HSW_ULT_GT3_IDS(0),
 139         INTEL_BDW_ULT_GT1_IDS(0),
 140         INTEL_BDW_ULT_GT2_IDS(0),
 141         INTEL_BDW_ULT_GT3_IDS(0),
 142         INTEL_BDW_ULT_RSVD_IDS(0),
 143         INTEL_SKL_ULT_GT1_IDS(0),
 144         INTEL_SKL_ULT_GT2_IDS(0),
 145         INTEL_SKL_ULT_GT3_IDS(0),
 146         INTEL_KBL_ULT_GT1_IDS(0),
 147         INTEL_KBL_ULT_GT2_IDS(0),
 148         INTEL_KBL_ULT_GT3_IDS(0),
 149         INTEL_CFL_U_GT2_IDS(0),
 150         INTEL_CFL_U_GT3_IDS(0),
 151         INTEL_WHL_U_GT1_IDS(0),
 152         INTEL_WHL_U_GT2_IDS(0),
 153         INTEL_WHL_U_GT3_IDS(0),
 154         INTEL_CML_U_GT1_IDS(0),
 155         INTEL_CML_U_GT2_IDS(0),
 156 };
 157
 158 static const u16 subplatform_ulx_ids[] = {
 159         INTEL_HSW_ULX_GT1_IDS(0),
 160         INTEL_HSW_ULX_GT2_IDS(0),
 161         INTEL_BDW_ULX_GT1_IDS(0),
 162         INTEL_BDW_ULX_GT2_IDS(0),
 163         INTEL_BDW_ULX_GT3_IDS(0),
 164         INTEL_BDW_ULX_RSVD_IDS(0),
 165         INTEL_SKL_ULX_GT1_IDS(0),
 166         INTEL_SKL_ULX_GT2_IDS(0),
 167         INTEL_KBL_ULX_GT1_IDS(0),
 168         INTEL_KBL_ULX_GT2_IDS(0),
 169         INTEL_AML_KBL_GT2_IDS(0),
 170         INTEL_AML_CFL_GT2_IDS(0),
 171 };
 172
 173 static const u16 subplatform_portf_ids[] = {
 174         INTEL_ICL_PORT_F_IDS(0),
 175 };
 176
 177 static const u16 subplatform_uy_ids[] = {
 178         INTEL_TGL_12_GT2_IDS(0),
 179 };
 180
 181 static const u16 subplatform_n_ids[] = {
 182         INTEL_ADLN_IDS(0),
 183 };
 184
 185 static const u16 subplatform_rpl_ids[] = {
 186         INTEL_RPLS_IDS(0),
 187         INTEL_RPLP_IDS(0),
 188 };
 189
 190 static const u16 subplatform_g10_ids[] = {
 191         INTEL_DG2_G10_IDS(0),
 192         INTEL_ATS_M150_IDS(0),
 193 };
 194
 195 static const u16 subplatform_g11_ids[] = {
 196         INTEL_DG2_G11_IDS(0),
 197         INTEL_ATS_M75_IDS(0),
 198 };
 199
 200 static const u16 subplatform_g12_ids[] = {
 201         INTEL_DG2_G12_IDS(0),
 202 };
 203
 204 static const u16 subplatform_m_ids[] = {
 205         INTEL_MTL_M_IDS(0),
 206 };
 207
 208 static const u16 subplatform_p_ids[] = {
 209         INTEL_MTL_P_IDS(0),
 210 };
 211
 212 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 213 {
 214         for (; num; num--, p++) {
 215                 if (*p == id)
 216                         return true;
 217         }
 218
 219         return false;
 220 }
 221
 222 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 223 {
 224         const struct intel_device_info *info = INTEL_INFO(i915);
 225         const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
 226         const unsigned int pi = __platform_mask_index(rinfo, info->platform);
 227         const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
 228         u16 devid = INTEL_DEVID(i915);
 229         u32 mask = 0;
 230
 231         /* Make sure IS_<platform> checks are working. */
 232         RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
 233
 234         /* Find and mark subplatform bits based on the PCI device id. */
 235         if (find_devid(devid, subplatform_ult_ids,
 236                        ARRAY_SIZE(subplatform_ult_ids))) {
 237                 mask = BIT(INTEL_SUBPLATFORM_ULT);
 238         } else if (find_devid(devid, subplatform_ulx_ids,
 239                               ARRAY_SIZE(subplatform_ulx_ids))) {
 240                 mask = BIT(INTEL_SUBPLATFORM_ULX);
 241                 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
 242                         /* ULX machines are also considered ULT. */
 243                         mask |= BIT(INTEL_SUBPLATFORM_ULT);
 244                 }
 245         } else if (find_devid(devid, subplatform_portf_ids,
 246                               ARRAY_SIZE(subplatform_portf_ids))) {
 247                 mask = BIT(INTEL_SUBPLATFORM_PORTF);
 248         } else if (find_devid(devid, subplatform_uy_ids,
 249                            ARRAY_SIZE(subplatform_uy_ids))) {
 250                 mask = BIT(INTEL_SUBPLATFORM_UY);
 251         } else if (find_devid(devid, subplatform_n_ids,
 252                                 ARRAY_SIZE(subplatform_n_ids))) {
 253                 mask = BIT(INTEL_SUBPLATFORM_N);
 254         } else if (find_devid(devid, subplatform_rpl_ids,
 255                               ARRAY_SIZE(subplatform_rpl_ids))) {
 256                 mask = BIT(INTEL_SUBPLATFORM_RPL);
 257         } else if (find_devid(devid, subplatform_g10_ids,
 258                               ARRAY_SIZE(subplatform_g10_ids))) {
 259                 mask = BIT(INTEL_SUBPLATFORM_G10);
 260         } else if (find_devid(devid, subplatform_g11_ids,
 261                               ARRAY_SIZE(subplatform_g11_ids))) {
 262                 mask = BIT(INTEL_SUBPLATFORM_G11);
 263         } else if (find_devid(devid, subplatform_g12_ids,
 264                               ARRAY_SIZE(subplatform_g12_ids))) {
 265                 mask = BIT(INTEL_SUBPLATFORM_G12);
 266         } else if (find_devid(devid, subplatform_m_ids,
 267                               ARRAY_SIZE(subplatform_m_ids))) {
 268                 mask = BIT(INTEL_SUBPLATFORM_M);
 269         } else if (find_devid(devid, subplatform_p_ids,
 270                               ARRAY_SIZE(subplatform_p_ids))) {
 271                 mask = BIT(INTEL_SUBPLATFORM_P);
 272         }
 273
 274         GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
 275
 276         RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 277 }
 278
 279 /**
 280  * intel_device_info_runtime_init - initialize runtime info
 281  * @dev_priv: the i915 device
 282  *
 283  * Determine various intel_device_info fields at runtime.
 284  *
 285  * Use it when either:
 286  *   - it's judged too laborious to fill n static structures with the limit
 287  *     when a simple if statement does the job,
 288  *   - run-time checks (eg read fuse/strap registers) are needed.
 289  *
 290  * This function needs to be called:
 291  *   - after the MMIO has been setup as we are reading registers,
 292  *   - after the PCH has been detected,
 293  *   - before the first usage of the fields it can tweak.
 294  */
 295 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 296 {
 297         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 298         struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 299         enum pipe pipe;
 300
 301         /* Wa_14011765242: adl-s A0,A1 */
 302         if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 303                 for_each_pipe(dev_priv, pipe)
 304                         runtime->num_scalers[pipe] = 0;
 305         else if (DISPLAY_VER(dev_priv) >= 11) {
 306                 for_each_pipe(dev_priv, pipe)
 307                         runtime->num_scalers[pipe] = 2;
 308         } else if (DISPLAY_VER(dev_priv) >= 9) {
 309                 runtime->num_scalers[PIPE_A] = 2;
 310                 runtime->num_scalers[PIPE_B] = 2;
 311                 runtime->num_scalers[PIPE_C] = 1;
 312         }
 313
 314         BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 315
 316         if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 317                 for_each_pipe(dev_priv, pipe)
 318                         runtime->num_sprites[pipe] = 4;
 319         else if (DISPLAY_VER(dev_priv) >= 11)
 320                 for_each_pipe(dev_priv, pipe)
 321                         runtime->num_sprites[pipe] = 6;
 322         else if (DISPLAY_VER(dev_priv) == 10)
 323                 for_each_pipe(dev_priv, pipe)
 324                         runtime->num_sprites[pipe] = 3;
 325         else if (IS_BROXTON(dev_priv)) {
 326                 /*
 327                  * Skylake and Broxton currently don't expose the topmost plane as its
 328                  * use is exclusive with the legacy cursor and we only want to expose
 329                  * one of those, not both. Until we can safely expose the topmost plane
 330                  * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 331                  * we don't expose the topmost plane at all to prevent ABI breakage
 332                  * down the line.
 333                  */
 334
 335                 runtime->num_sprites[PIPE_A] = 2;
 336                 runtime->num_sprites[PIPE_B] = 2;
 337                 runtime->num_sprites[PIPE_C] = 1;
 338         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 339                 for_each_pipe(dev_priv, pipe)
 340                         runtime->num_sprites[pipe] = 2;
 341         } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 342                 for_each_pipe(dev_priv, pipe)
 343                         runtime->num_sprites[pipe] = 1;
 344         }
 345
 346         if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
 347             HAS_PCH_SPLIT(dev_priv)) {
 348                 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
 349                 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
 350
 351                 /*
 352                  * SFUSE_STRAP is supposed to have a bit signalling the display
 353                  * is fused off. Unfortunately it seems that, at least in
 354                  * certain cases, fused off display means that PCH display
 355                  * reads don't land anywhere. In that case, we read 0s.
 356                  *
 357                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 358                  * should be set when taking over after the firmware.
 359                  */
 360                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 361                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 362                     (HAS_PCH_CPT(dev_priv) &&
 363                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 364                         drm_info(&dev_priv->drm,
 365                                  "Display fused off, disabling\n");
 366                         runtime->pipe_mask = 0;
 367                         runtime->cpu_transcoder_mask = 0;
 368                         runtime->fbc_mask = 0;
 369                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 370                         drm_info(&dev_priv->drm, "PipeC fused off\n");
 371                         runtime->pipe_mask &= ~BIT(PIPE_C);
 372                         runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 373                 }
 374         } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
 375                 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 376
 377                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
 378                         runtime->pipe_mask &= ~BIT(PIPE_A);
 379                         runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
 380                         runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
 381                 }
 382                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
 383                         runtime->pipe_mask &= ~BIT(PIPE_B);
 384                         runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
 385                 }
 386                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
 387                         runtime->pipe_mask &= ~BIT(PIPE_C);
 388                         runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 389                 }
 390
 391                 if (DISPLAY_VER(dev_priv) >= 12 &&
 392                     (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 393                         runtime->pipe_mask &= ~BIT(PIPE_D);
 394                         runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
 395                 }
 396
 397                 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
 398                         info->display.has_hdcp = 0;
 399
 400                 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
 401                         runtime->fbc_mask = 0;
 402
 403                 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
 404                         info->display.has_dmc = 0;
 405
 406                 if (DISPLAY_VER(dev_priv) >= 10 &&
 407                     (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
 408                         info->display.has_dsc = 0;
 409         }
 410
 411         if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
 412                 drm_info(&dev_priv->drm,
 413                          "Disabling ppGTT for VT-d support\n");
 414                 runtime->ppgtt_type = INTEL_PPGTT_NONE;
 415         }
 416
 417         runtime->rawclk_freq = intel_read_rawclk(dev_priv);
 418         drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
 419
 420         if (!HAS_DISPLAY(dev_priv)) {
 421                 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
 422                                                    DRIVER_ATOMIC);
 423                 memset(&info->display, 0, sizeof(info->display));
 424                 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
 425                 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
 426         }
 427 }
 428
 429 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 430                              struct drm_printer *p)
 431 {
 432         drm_printf(p, "Has logical contexts? %s\n",
 433                    str_yes_no(caps->has_logical_contexts));
 434         drm_printf(p, "scheduler: %x\n", caps->scheduler);
 435 }