2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 void intel_device_info_dump(struct drm_i915_private *dev_priv)
29 const struct intel_device_info *info = &dev_priv->info;
31 #define PRINT_S(name) "%s"
33 #define PRINT_FLAG(name) info->name ? #name "," : ""
35 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
36 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
38 dev_priv->drm.pdev->device,
39 dev_priv->drm.pdev->revision,
40 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
47 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
49 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
52 fuse = I915_READ(CHV_FUSE_GT);
54 sseu->slice_mask = BIT(0);
56 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
57 sseu->subslice_mask |= BIT(0);
58 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
59 CHV_FGT_EU_DIS_SS0_R1_MASK);
60 sseu->eu_total += 8 - hweight32(eu_dis);
63 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
64 sseu->subslice_mask |= BIT(1);
65 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
66 CHV_FGT_EU_DIS_SS1_R1_MASK);
67 sseu->eu_total += 8 - hweight32(eu_dis);
71 * CHV expected to always have a uniform distribution of EU
74 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
75 sseu->eu_total / sseu_subslice_total(sseu) :
78 * CHV supports subslice power gating on devices with more than
79 * one subslice, and supports EU power gating on devices with
80 * more than one EU pair per subslice.
82 sseu->has_slice_pg = 0;
83 sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
84 sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
87 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
89 struct intel_device_info *info = mkwrite_device_info(dev_priv);
90 struct sseu_dev_info *sseu = &info->sseu;
91 int s_max = 3, ss_max = 4, eu_max = 8;
93 u32 fuse2, eu_disable;
96 fuse2 = I915_READ(GEN8_FUSE2);
97 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
100 * The subslice disable field is global, i.e. it applies
101 * to each of the enabled slices.
103 sseu->subslice_mask = (1 << ss_max) - 1;
104 sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
105 GEN9_F2_SS_DIS_SHIFT);
108 * Iterate through enabled slices and subslices to
109 * count the total enabled EU.
111 for (s = 0; s < s_max; s++) {
112 if (!(sseu->slice_mask & BIT(s)))
113 /* skip disabled slice */
116 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
117 for (ss = 0; ss < ss_max; ss++) {
120 if (!(sseu->subslice_mask & BIT(ss)))
121 /* skip disabled subslice */
124 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
128 * Record which subslice(s) has(have) 7 EUs. we
129 * can tune the hash used to spread work among
130 * subslices if they are unbalanced.
133 sseu->subslice_7eu[s] |= BIT(ss);
135 sseu->eu_total += eu_per_ss;
140 * SKL is expected to always have a uniform distribution
141 * of EU across subslices with the exception that any one
142 * EU in any one subslice may be fused off for die
143 * recovery. BXT is expected to be perfectly uniform in EU
146 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
147 DIV_ROUND_UP(sseu->eu_total,
148 sseu_subslice_total(sseu)) : 0;
150 * SKL supports slice power gating on devices with more than
151 * one slice, and supports EU power gating on devices with
152 * more than one EU pair per subslice. BXT supports subslice
153 * power gating on devices with more than one subslice, and
154 * supports EU power gating on devices with more than one EU
158 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
159 hweight8(sseu->slice_mask) > 1;
160 sseu->has_subslice_pg =
161 IS_BROXTON(dev_priv) && sseu_subslice_total(sseu) > 1;
162 sseu->has_eu_pg = sseu->eu_per_subslice > 2;
164 if (IS_BROXTON(dev_priv)) {
165 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss)))
167 * There is a HW issue in 2x6 fused down parts that requires
168 * Pooled EU to be enabled as a WA. The pool configuration
169 * changes depending upon which subslice is fused down. This
170 * doesn't affect if the device has all 3 subslices enabled.
172 /* WaEnablePooledEuFor2x6:bxt */
173 info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) ||
174 (hweight8(sseu->subslice_mask) == 2 &&
175 INTEL_REVID(dev_priv) < BXT_REVID_C0));
177 sseu->min_eu_in_pool = 0;
178 if (info->has_pooled_eu) {
179 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
180 sseu->min_eu_in_pool = 3;
181 else if (IS_SS_DISABLED(1))
182 sseu->min_eu_in_pool = 6;
184 sseu->min_eu_in_pool = 9;
186 #undef IS_SS_DISABLED
190 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
192 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
193 const int s_max = 3, ss_max = 3, eu_max = 8;
195 u32 fuse2, eu_disable[s_max];
197 fuse2 = I915_READ(GEN8_FUSE2);
198 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
200 * The subslice disable field is global, i.e. it applies
201 * to each of the enabled slices.
203 sseu->subslice_mask = BIT(ss_max) - 1;
204 sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
205 GEN8_F2_SS_DIS_SHIFT);
207 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
208 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
209 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
210 (32 - GEN8_EU_DIS0_S1_SHIFT));
211 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
212 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
213 (32 - GEN8_EU_DIS1_S2_SHIFT));
216 * Iterate through enabled slices and subslices to
217 * count the total enabled EU.
219 for (s = 0; s < s_max; s++) {
220 if (!(sseu->slice_mask & BIT(s)))
221 /* skip disabled slice */
224 for (ss = 0; ss < ss_max; ss++) {
227 if (!(sseu->subslice_mask & BIT(ss)))
228 /* skip disabled subslice */
231 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
234 * Record which subslices have 7 EUs.
236 if (eu_max - n_disabled == 7)
237 sseu->subslice_7eu[s] |= 1 << ss;
239 sseu->eu_total += eu_max - n_disabled;
244 * BDW is expected to always have a uniform distribution of EU across
245 * subslices with the exception that any one EU in any one subslice may
246 * be fused off for die recovery.
248 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
249 DIV_ROUND_UP(sseu->eu_total,
250 sseu_subslice_total(sseu)) : 0;
253 * BDW supports slice power gating on devices with more than
256 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
257 sseu->has_subslice_pg = 0;
262 * Determine various intel_device_info fields at runtime.
264 * Use it when either:
265 * - it's judged too laborious to fill n static structures with the limit
266 * when a simple if statement does the job,
267 * - run-time checks (eg read fuse/strap registers) are needed.
269 * This function needs to be called:
270 * - after the MMIO has been setup as we are reading registers,
271 * - after the PCH has been detected,
272 * - before the first usage of the fields it can tweak.
274 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
276 struct intel_device_info *info = mkwrite_device_info(dev_priv);
280 * Skylake and Broxton currently don't expose the topmost plane as its
281 * use is exclusive with the legacy cursor and we only want to expose
282 * one of those, not both. Until we can safely expose the topmost plane
283 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
284 * we don't expose the topmost plane at all to prevent ABI breakage
287 if (IS_BROXTON(dev_priv)) {
288 info->num_sprites[PIPE_A] = 2;
289 info->num_sprites[PIPE_B] = 2;
290 info->num_sprites[PIPE_C] = 1;
291 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
292 for_each_pipe(dev_priv, pipe)
293 info->num_sprites[pipe] = 2;
295 for_each_pipe(dev_priv, pipe)
296 info->num_sprites[pipe] = 1;
298 if (i915.disable_display) {
299 DRM_INFO("Display disabled (module parameter)\n");
301 } else if (info->num_pipes > 0 &&
302 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
303 HAS_PCH_SPLIT(dev_priv)) {
304 u32 fuse_strap = I915_READ(FUSE_STRAP);
305 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
308 * SFUSE_STRAP is supposed to have a bit signalling the display
309 * is fused off. Unfortunately it seems that, at least in
310 * certain cases, fused off display means that PCH display
311 * reads don't land anywhere. In that case, we read 0s.
313 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
314 * should be set when taking over after the firmware.
316 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
317 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
318 (dev_priv->pch_type == PCH_CPT &&
319 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
320 DRM_INFO("Display fused off, disabling\n");
322 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
323 DRM_INFO("PipeC fused off\n");
324 info->num_pipes -= 1;
326 } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
327 u32 dfsm = I915_READ(SKL_DFSM);
328 u8 disabled_mask = 0;
332 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
333 disabled_mask |= BIT(PIPE_A);
334 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
335 disabled_mask |= BIT(PIPE_B);
336 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
337 disabled_mask |= BIT(PIPE_C);
339 num_bits = hweight8(disabled_mask);
341 switch (disabled_mask) {
344 case BIT(PIPE_A) | BIT(PIPE_B):
345 case BIT(PIPE_A) | BIT(PIPE_C):
352 if (num_bits > info->num_pipes || invalid)
353 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
356 info->num_pipes -= num_bits;
359 /* Initialize slice/subslice/EU info */
360 if (IS_CHERRYVIEW(dev_priv))
361 cherryview_sseu_info_init(dev_priv);
362 else if (IS_BROADWELL(dev_priv))
363 broadwell_sseu_info_init(dev_priv);
364 else if (INTEL_INFO(dev_priv)->gen >= 9)
365 gen9_sseu_info_init(dev_priv);
367 info->has_snoop = !info->has_llc;
369 /* Snooping is broken on BXT A stepping. */
370 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
371 info->has_snoop = false;
373 DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
374 DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
375 DRM_DEBUG_DRIVER("subslice total: %u\n",
376 sseu_subslice_total(&info->sseu));
377 DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask);
378 DRM_DEBUG_DRIVER("subslice per slice: %u\n",
379 hweight8(info->sseu.subslice_mask));
380 DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total);
381 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice);
382 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
383 info->sseu.has_slice_pg ? "y" : "n");
384 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
385 info->sseu.has_subslice_pg ? "y" : "n");
386 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
387 info->sseu.has_eu_pg ? "y" : "n");