drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         enum intel_display_power_domain power_domain;
  73         u32 tmp;
  74         bool ret;
  75
  76         power_domain = intel_display_port_power_domain(encoder);
  77         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  78                 return false;
  79
  80         ret = false;
  81
  82         tmp = I915_READ(crt->adpa_reg);
  83
  84         if (!(tmp & ADPA_DAC_ENABLE))
  85                 goto out;
  86
  87         if (HAS_PCH_CPT(dev))
  88                 *pipe = PORT_TO_PIPE_CPT(tmp);
  89         else
  90                 *pipe = PORT_TO_PIPE(tmp);
  91
  92         ret = true;
  93 out:
  94         intel_display_power_put(dev_priv, power_domain);
  95
  96         return ret;
  97 }
  98
  99 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 100 {
 101         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 102         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 103         u32 tmp, flags = 0;
 104
 105         tmp = I915_READ(crt->adpa_reg);
 106
 107         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 108                 flags |= DRM_MODE_FLAG_PHSYNC;
 109         else
 110                 flags |= DRM_MODE_FLAG_NHSYNC;
 111
 112         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 113                 flags |= DRM_MODE_FLAG_PVSYNC;
 114         else
 115                 flags |= DRM_MODE_FLAG_NVSYNC;
 116
 117         return flags;
 118 }
 119
 120 static void intel_crt_get_config(struct intel_encoder *encoder,
 121                                  struct intel_crtc_state *pipe_config)
 122 {
 123         struct drm_device *dev = encoder->base.dev;
 124         int dotclock;
 125
 126         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 127
 128         dotclock = pipe_config->port_clock;
 129
 130         if (HAS_PCH_SPLIT(dev))
 131                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 132
 133         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 134 }
 135
 136 static void hsw_crt_get_config(struct intel_encoder *encoder,
 137                                struct intel_crtc_state *pipe_config)
 138 {
 139         intel_ddi_get_config(encoder, pipe_config);
 140
 141         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 142                                               DRM_MODE_FLAG_NHSYNC |
 143                                               DRM_MODE_FLAG_PVSYNC |
 144                                               DRM_MODE_FLAG_NVSYNC);
 145         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 146 }
 147
 148 /* Note: The caller is required to filter out dpms modes not supported by the
 149  * platform. */
 150 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
 151 {
 152         struct drm_device *dev = encoder->base.dev;
 153         struct drm_i915_private *dev_priv = dev->dev_private;
 154         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 155         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 156         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 157         u32 adpa;
 158
 159         if (INTEL_INFO(dev)->gen >= 5)
 160                 adpa = ADPA_HOTPLUG_BITS;
 161         else
 162                 adpa = 0;
 163
 164         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 165                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 166         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 167                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 168
 169         /* For CPT allow 3 pipe config, for others just use A or B */
 170         if (HAS_PCH_LPT(dev))
 171                 ; /* Those bits don't exist here */
 172         else if (HAS_PCH_CPT(dev))
 173                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 174         else if (crtc->pipe == 0)
 175                 adpa |= ADPA_PIPE_A_SELECT;
 176         else
 177                 adpa |= ADPA_PIPE_B_SELECT;
 178
 179         if (!HAS_PCH_SPLIT(dev))
 180                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 181
 182         switch (mode) {
 183         case DRM_MODE_DPMS_ON:
 184                 adpa |= ADPA_DAC_ENABLE;
 185                 break;
 186         case DRM_MODE_DPMS_STANDBY:
 187                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 188                 break;
 189         case DRM_MODE_DPMS_SUSPEND:
 190                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 191                 break;
 192         case DRM_MODE_DPMS_OFF:
 193                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 194                 break;
 195         }
 196
 197         I915_WRITE(crt->adpa_reg, adpa);
 198 }
 199
 200 static void intel_disable_crt(struct intel_encoder *encoder)
 201 {
 202         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 203 }
 204
 205 static void pch_disable_crt(struct intel_encoder *encoder)
 206 {
 207 }
 208
 209 static void pch_post_disable_crt(struct intel_encoder *encoder)
 210 {
 211         intel_disable_crt(encoder);
 212 }
 213
 214 static void intel_enable_crt(struct intel_encoder *encoder)
 215 {
 216         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON);
 217 }
 218
 219 static enum drm_mode_status
 220 intel_crt_mode_valid(struct drm_connector *connector,
 221                      struct drm_display_mode *mode)
 222 {
 223         struct drm_device *dev = connector->dev;
 224         int max_dotclk = to_i915(dev)->max_dotclk_freq;
 225
 226         int max_clock = 0;
 227         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 228                 return MODE_NO_DBLESCAN;
 229
 230         if (mode->clock < 25000)
 231                 return MODE_CLOCK_LOW;
 232
 233         if (IS_GEN2(dev))
 234                 max_clock = 350000;
 235         else
 236                 max_clock = 400000;
 237         if (mode->clock > max_clock)
 238                 return MODE_CLOCK_HIGH;
 239
 240         if (mode->clock > max_dotclk)
 241                 return MODE_CLOCK_HIGH;
 242
 243         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 244         if (HAS_PCH_LPT(dev) &&
 245             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 246                 return MODE_CLOCK_HIGH;
 247
 248         return MODE_OK;
 249 }
 250
 251 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 252                                      struct intel_crtc_state *pipe_config)
 253 {
 254         struct drm_device *dev = encoder->base.dev;
 255
 256         if (HAS_PCH_SPLIT(dev))
 257                 pipe_config->has_pch_encoder = true;
 258
 259         /* LPT FDI RX only supports 8bpc. */
 260         if (HAS_PCH_LPT(dev))
 261                 pipe_config->pipe_bpp = 24;
 262
 263         /* FDI must always be 2.7 GHz */
 264         if (HAS_DDI(dev)) {
 265                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 266                 pipe_config->port_clock = 135000 * 2;
 267
 268                 pipe_config->dpll_hw_state.wrpll = 0;
 269                 pipe_config->dpll_hw_state.spll =
 270                         SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 271         }
 272
 273         return true;
 274 }
 275
 276 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 277 {
 278         struct drm_device *dev = connector->dev;
 279         struct intel_crt *crt = intel_attached_crt(connector);
 280         struct drm_i915_private *dev_priv = dev->dev_private;
 281         u32 adpa;
 282         bool ret;
 283
 284         /* The first time through, trigger an explicit detection cycle */
 285         if (crt->force_hotplug_required) {
 286                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
 287                 u32 save_adpa;
 288
 289                 crt->force_hotplug_required = 0;
 290
 291                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 292                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 293
 294                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 295                 if (turn_off_dac)
 296                         adpa &= ~ADPA_DAC_ENABLE;
 297
 298                 I915_WRITE(crt->adpa_reg, adpa);
 299
 300                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 301                              1000))
 302                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 303
 304                 if (turn_off_dac) {
 305                         I915_WRITE(crt->adpa_reg, save_adpa);
 306                         POSTING_READ(crt->adpa_reg);
 307                 }
 308         }
 309
 310         /* Check the status to see if both blue and green are on now */
 311         adpa = I915_READ(crt->adpa_reg);
 312         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 313                 ret = true;
 314         else
 315                 ret = false;
 316         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 317
 318         return ret;
 319 }
 320
 321 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 322 {
 323         struct drm_device *dev = connector->dev;
 324         struct intel_crt *crt = intel_attached_crt(connector);
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         u32 adpa;
 327         bool ret;
 328         u32 save_adpa;
 329
 330         save_adpa = adpa = I915_READ(crt->adpa_reg);
 331         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 332
 333         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 334
 335         I915_WRITE(crt->adpa_reg, adpa);
 336
 337         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 338                      1000)) {
 339                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 340                 I915_WRITE(crt->adpa_reg, save_adpa);
 341         }
 342
 343         /* Check the status to see if both blue and green are on now */
 344         adpa = I915_READ(crt->adpa_reg);
 345         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 346                 ret = true;
 347         else
 348                 ret = false;
 349
 350         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 351
 352         return ret;
 353 }
 354
 355 /**
 356  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 357  *
 358  * Not for i915G/i915GM
 359  *
 360  * \return true if CRT is connected.
 361  * \return false if CRT is disconnected.
 362  */
 363 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 364 {
 365         struct drm_device *dev = connector->dev;
 366         struct drm_i915_private *dev_priv = dev->dev_private;
 367         u32 stat;
 368         bool ret = false;
 369         int i, tries = 0;
 370
 371         if (HAS_PCH_SPLIT(dev))
 372                 return intel_ironlake_crt_detect_hotplug(connector);
 373
 374         if (IS_VALLEYVIEW(dev))
 375                 return valleyview_crt_detect_hotplug(connector);
 376
 377         /*
 378          * On 4 series desktop, CRT detect sequence need to be done twice
 379          * to get a reliable result.
 380          */
 381
 382         if (IS_G4X(dev) && !IS_GM45(dev))
 383                 tries = 2;
 384         else
 385                 tries = 1;
 386
 387         for (i = 0; i < tries ; i++) {
 388                 /* turn on the FORCE_DETECT */
 389                 i915_hotplug_interrupt_update(dev_priv,
 390                                               CRT_HOTPLUG_FORCE_DETECT,
 391                                               CRT_HOTPLUG_FORCE_DETECT);
 392                 /* wait for FORCE_DETECT to go off */
 393                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
 394                               CRT_HOTPLUG_FORCE_DETECT) == 0,
 395                              1000))
 396                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 397         }
 398
 399         stat = I915_READ(PORT_HOTPLUG_STAT);
 400         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 401                 ret = true;
 402
 403         /* clear the interrupt we just generated, if any */
 404         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 405
 406         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 407
 408         return ret;
 409 }
 410
 411 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 412                                 struct i2c_adapter *i2c)
 413 {
 414         struct edid *edid;
 415
 416         edid = drm_get_edid(connector, i2c);
 417
 418         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 419                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 420                 intel_gmbus_force_bit(i2c, true);
 421                 edid = drm_get_edid(connector, i2c);
 422                 intel_gmbus_force_bit(i2c, false);
 423         }
 424
 425         return edid;
 426 }
 427
 428 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 429 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 430                                 struct i2c_adapter *adapter)
 431 {
 432         struct edid *edid;
 433         int ret;
 434
 435         edid = intel_crt_get_edid(connector, adapter);
 436         if (!edid)
 437                 return 0;
 438
 439         ret = intel_connector_update_modes(connector, edid);
 440         kfree(edid);
 441
 442         return ret;
 443 }
 444
 445 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 446 {
 447         struct intel_crt *crt = intel_attached_crt(connector);
 448         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
 449         struct edid *edid;
 450         struct i2c_adapter *i2c;
 451
 452         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 453
 454         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 455         edid = intel_crt_get_edid(connector, i2c);
 456
 457         if (edid) {
 458                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 459
 460                 /*
 461                  * This may be a DVI-I connector with a shared DDC
 462                  * link between analog and digital outputs, so we
 463                  * have to check the EDID input spec of the attached device.
 464                  */
 465                 if (!is_digital) {
 466                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 467                         return true;
 468                 }
 469
 470                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 471         } else {
 472                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 473         }
 474
 475         kfree(edid);
 476
 477         return false;
 478 }
 479
 480 static enum drm_connector_status
 481 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 482 {
 483         struct drm_device *dev = crt->base.base.dev;
 484         struct drm_i915_private *dev_priv = dev->dev_private;
 485         uint32_t save_bclrpat;
 486         uint32_t save_vtotal;
 487         uint32_t vtotal, vactive;
 488         uint32_t vsample;
 489         uint32_t vblank, vblank_start, vblank_end;
 490         uint32_t dsl;
 491         i915_reg_t bclrpat_reg, vtotal_reg,
 492                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 493         uint8_t st00;
 494         enum drm_connector_status status;
 495
 496         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 497
 498         bclrpat_reg = BCLRPAT(pipe);
 499         vtotal_reg = VTOTAL(pipe);
 500         vblank_reg = VBLANK(pipe);
 501         vsync_reg = VSYNC(pipe);
 502         pipeconf_reg = PIPECONF(pipe);
 503         pipe_dsl_reg = PIPEDSL(pipe);
 504
 505         save_bclrpat = I915_READ(bclrpat_reg);
 506         save_vtotal = I915_READ(vtotal_reg);
 507         vblank = I915_READ(vblank_reg);
 508
 509         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 510         vactive = (save_vtotal & 0x7ff) + 1;
 511
 512         vblank_start = (vblank & 0xfff) + 1;
 513         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 514
 515         /* Set the border color to purple. */
 516         I915_WRITE(bclrpat_reg, 0x500050);
 517
 518         if (!IS_GEN2(dev)) {
 519                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 520                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 521                 POSTING_READ(pipeconf_reg);
 522                 /* Wait for next Vblank to substitue
 523                  * border color for Color info */
 524                 intel_wait_for_vblank(dev, pipe);
 525                 st00 = I915_READ8(_VGA_MSR_WRITE);
 526                 status = ((st00 & (1 << 4)) != 0) ?
 527                         connector_status_connected :
 528                         connector_status_disconnected;
 529
 530                 I915_WRITE(pipeconf_reg, pipeconf);
 531         } else {
 532                 bool restore_vblank = false;
 533                 int count, detect;
 534
 535                 /*
 536                 * If there isn't any border, add some.
 537                 * Yes, this will flicker
 538                 */
 539                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 540                         uint32_t vsync = I915_READ(vsync_reg);
 541                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 542
 543                         vblank_start = vsync_start;
 544                         I915_WRITE(vblank_reg,
 545                                    (vblank_start - 1) |
 546                                    ((vblank_end - 1) << 16));
 547                         restore_vblank = true;
 548                 }
 549                 /* sample in the vertical border, selecting the larger one */
 550                 if (vblank_start - vactive >= vtotal - vblank_end)
 551                         vsample = (vblank_start + vactive) >> 1;
 552                 else
 553                         vsample = (vtotal + vblank_end) >> 1;
 554
 555                 /*
 556                  * Wait for the border to be displayed
 557                  */
 558                 while (I915_READ(pipe_dsl_reg) >= vactive)
 559                         ;
 560                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 561                         ;
 562                 /*
 563                  * Watch ST00 for an entire scanline
 564                  */
 565                 detect = 0;
 566                 count = 0;
 567                 do {
 568                         count++;
 569                         /* Read the ST00 VGA status register */
 570                         st00 = I915_READ8(_VGA_MSR_WRITE);
 571                         if (st00 & (1 << 4))
 572                                 detect++;
 573                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 574
 575                 /* restore vblank if necessary */
 576                 if (restore_vblank)
 577                         I915_WRITE(vblank_reg, vblank);
 578                 /*
 579                  * If more than 3/4 of the scanline detected a monitor,
 580                  * then it is assumed to be present. This works even on i830,
 581                  * where there isn't any way to force the border color across
 582                  * the screen
 583                  */
 584                 status = detect * 4 > count * 3 ?
 585                          connector_status_connected :
 586                          connector_status_disconnected;
 587         }
 588
 589         /* Restore previous settings */
 590         I915_WRITE(bclrpat_reg, save_bclrpat);
 591
 592         return status;
 593 }
 594
 595 static enum drm_connector_status
 596 intel_crt_detect(struct drm_connector *connector, bool force)
 597 {
 598         struct drm_device *dev = connector->dev;
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         struct intel_crt *crt = intel_attached_crt(connector);
 601         struct intel_encoder *intel_encoder = &crt->base;
 602         enum intel_display_power_domain power_domain;
 603         enum drm_connector_status status;
 604         struct intel_load_detect_pipe tmp;
 605         struct drm_modeset_acquire_ctx ctx;
 606
 607         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 608                       connector->base.id, connector->name,
 609                       force);
 610
 611         power_domain = intel_display_port_power_domain(intel_encoder);
 612         intel_display_power_get(dev_priv, power_domain);
 613
 614         if (I915_HAS_HOTPLUG(dev)) {
 615                 /* We can not rely on the HPD pin always being correctly wired
 616                  * up, for example many KVM do not pass it through, and so
 617                  * only trust an assertion that the monitor is connected.
 618                  */
 619                 if (intel_crt_detect_hotplug(connector)) {
 620                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 621                         status = connector_status_connected;
 622                         goto out;
 623                 } else
 624                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 625         }
 626
 627         if (intel_crt_detect_ddc(connector)) {
 628                 status = connector_status_connected;
 629                 goto out;
 630         }
 631
 632         /* Load detection is broken on HPD capable machines. Whoever wants a
 633          * broken monitor (without edid) to work behind a broken kvm (that fails
 634          * to have the right resistors for HP detection) needs to fix this up.
 635          * For now just bail out. */
 636         if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
 637                 status = connector_status_disconnected;
 638                 goto out;
 639         }
 640
 641         if (!force) {
 642                 status = connector->status;
 643                 goto out;
 644         }
 645
 646         drm_modeset_acquire_init(&ctx, 0);
 647
 648         /* for pre-945g platforms use load detect */
 649         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
 650                 if (intel_crt_detect_ddc(connector))
 651                         status = connector_status_connected;
 652                 else if (INTEL_INFO(dev)->gen < 4)
 653                         status = intel_crt_load_detect(crt,
 654                                 to_intel_crtc(connector->state->crtc)->pipe);
 655                 else
 656                         status = connector_status_unknown;
 657                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
 658         } else
 659                 status = connector_status_unknown;
 660
 661         drm_modeset_drop_locks(&ctx);
 662         drm_modeset_acquire_fini(&ctx);
 663
 664 out:
 665         intel_display_power_put(dev_priv, power_domain);
 666         return status;
 667 }
 668
 669 static void intel_crt_destroy(struct drm_connector *connector)
 670 {
 671         drm_connector_cleanup(connector);
 672         kfree(connector);
 673 }
 674
 675 static int intel_crt_get_modes(struct drm_connector *connector)
 676 {
 677         struct drm_device *dev = connector->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         struct intel_crt *crt = intel_attached_crt(connector);
 680         struct intel_encoder *intel_encoder = &crt->base;
 681         enum intel_display_power_domain power_domain;
 682         int ret;
 683         struct i2c_adapter *i2c;
 684
 685         power_domain = intel_display_port_power_domain(intel_encoder);
 686         intel_display_power_get(dev_priv, power_domain);
 687
 688         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 689         ret = intel_crt_ddc_get_modes(connector, i2c);
 690         if (ret || !IS_G4X(dev))
 691                 goto out;
 692
 693         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 694         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 695         ret = intel_crt_ddc_get_modes(connector, i2c);
 696
 697 out:
 698         intel_display_power_put(dev_priv, power_domain);
 699
 700         return ret;
 701 }
 702
 703 static int intel_crt_set_property(struct drm_connector *connector,
 704                                   struct drm_property *property,
 705                                   uint64_t value)
 706 {
 707         return 0;
 708 }
 709
 710 static void intel_crt_reset(struct drm_connector *connector)
 711 {
 712         struct drm_device *dev = connector->dev;
 713         struct drm_i915_private *dev_priv = dev->dev_private;
 714         struct intel_crt *crt = intel_attached_crt(connector);
 715
 716         if (INTEL_INFO(dev)->gen >= 5) {
 717                 u32 adpa;
 718
 719                 adpa = I915_READ(crt->adpa_reg);
 720                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 721                 adpa |= ADPA_HOTPLUG_BITS;
 722                 I915_WRITE(crt->adpa_reg, adpa);
 723                 POSTING_READ(crt->adpa_reg);
 724
 725                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 726                 crt->force_hotplug_required = 1;
 727         }
 728
 729 }
 730
 731 /*
 732  * Routines for controlling stuff on the analog port
 733  */
 734
 735 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 736         .reset = intel_crt_reset,
 737         .dpms = drm_atomic_helper_connector_dpms,
 738         .detect = intel_crt_detect,
 739         .fill_modes = drm_helper_probe_single_connector_modes,
 740         .destroy = intel_crt_destroy,
 741         .set_property = intel_crt_set_property,
 742         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 743         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 744         .atomic_get_property = intel_connector_atomic_get_property,
 745 };
 746
 747 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 748         .mode_valid = intel_crt_mode_valid,
 749         .get_modes = intel_crt_get_modes,
 750         .best_encoder = intel_best_encoder,
 751 };
 752
 753 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 754         .destroy = intel_encoder_destroy,
 755 };
 756
 757 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
 758 {
 759         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
 760         return 1;
 761 }
 762
 763 static const struct dmi_system_id intel_no_crt[] = {
 764         {
 765                 .callback = intel_no_crt_dmi_callback,
 766                 .ident = "ACER ZGB",
 767                 .matches = {
 768                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 769                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 770                 },
 771         },
 772         {
 773                 .callback = intel_no_crt_dmi_callback,
 774                 .ident = "DELL XPS 8700",
 775                 .matches = {
 776                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 777                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
 778                 },
 779         },
 780         { }
 781 };
 782
 783 void intel_crt_init(struct drm_device *dev)
 784 {
 785         struct drm_connector *connector;
 786         struct intel_crt *crt;
 787         struct intel_connector *intel_connector;
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         i915_reg_t adpa_reg;
 790         u32 adpa;
 791
 792         /* Skip machines without VGA that falsely report hotplug events */
 793         if (dmi_check_system(intel_no_crt))
 794                 return;
 795
 796         if (HAS_PCH_SPLIT(dev))
 797                 adpa_reg = PCH_ADPA;
 798         else if (IS_VALLEYVIEW(dev))
 799                 adpa_reg = VLV_ADPA;
 800         else
 801                 adpa_reg = ADPA;
 802
 803         adpa = I915_READ(adpa_reg);
 804         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 805                 /*
 806                  * On some machines (some IVB at least) CRT can be
 807                  * fused off, but there's no known fuse bit to
 808                  * indicate that. On these machine the ADPA register
 809                  * works normally, except the DAC enable bit won't
 810                  * take. So the only way to tell is attempt to enable
 811                  * it and see what happens.
 812                  */
 813                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 814                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 815                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 816                         return;
 817                 I915_WRITE(adpa_reg, adpa);
 818         }
 819
 820         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 821         if (!crt)
 822                 return;
 823
 824         intel_connector = intel_connector_alloc();
 825         if (!intel_connector) {
 826                 kfree(crt);
 827                 return;
 828         }
 829
 830         connector = &intel_connector->base;
 831         crt->connector = intel_connector;
 832         drm_connector_init(dev, &intel_connector->base,
 833                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 834
 835         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 836                          DRM_MODE_ENCODER_DAC, NULL);
 837
 838         intel_connector_attach_encoder(intel_connector, &crt->base);
 839
 840         crt->base.type = INTEL_OUTPUT_ANALOG;
 841         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 842         if (IS_I830(dev))
 843                 crt->base.crtc_mask = (1 << 0);
 844         else
 845                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 846
 847         if (IS_GEN2(dev))
 848                 connector->interlace_allowed = 0;
 849         else
 850                 connector->interlace_allowed = 1;
 851         connector->doublescan_allowed = 0;
 852
 853         crt->adpa_reg = adpa_reg;
 854
 855         crt->base.compute_config = intel_crt_compute_config;
 856         if (HAS_PCH_SPLIT(dev)) {
 857                 crt->base.disable = pch_disable_crt;
 858                 crt->base.post_disable = pch_post_disable_crt;
 859         } else {
 860                 crt->base.disable = intel_disable_crt;
 861         }
 862         crt->base.enable = intel_enable_crt;
 863         if (I915_HAS_HOTPLUG(dev))
 864                 crt->base.hpd_pin = HPD_CRT;
 865         if (HAS_DDI(dev)) {
 866                 crt->base.get_config = hsw_crt_get_config;
 867                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 868         } else {
 869                 crt->base.get_config = intel_crt_get_config;
 870                 crt->base.get_hw_state = intel_crt_get_hw_state;
 871         }
 872         intel_connector->get_hw_state = intel_connector_get_hw_state;
 873         intel_connector->unregister = intel_connector_unregister;
 874
 875         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 876
 877         drm_connector_register(connector);
 878
 879         if (!I915_HAS_HOTPLUG(dev))
 880                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 881
 882         /*
 883          * Configure the automatic hotplug detection stuff
 884          */
 885         crt->force_hotplug_required = 0;
 886
 887         /*
 888          * TODO: find a proper way to discover whether we need to set the the
 889          * polarity and link reversal bits or not, instead of relying on the
 890          * BIOS.
 891          */
 892         if (HAS_PCH_LPT(dev)) {
 893                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 894                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
 895
 896                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
 897         }
 898
 899         intel_crt_reset(connector);
 900 }