drivers/gpu/drm/i915/icl_dsi.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *   Madhav Chauhan <madhav.chauhan@intel.com>
  25  *   Jani Nikula <jani.nikula@intel.com>
  26  */
  27
  28 #include <drm/drm_mipi_dsi.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include "intel_dsi.h"
  31
  32 static inline int header_credits_available(struct drm_i915_private *dev_priv,
  33                                            enum transcoder dsi_trans)
  34 {
  35         return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  36                 >> FREE_HEADER_CREDIT_SHIFT;
  37 }
  38
  39 static inline int payload_credits_available(struct drm_i915_private *dev_priv,
  40                                             enum transcoder dsi_trans)
  41 {
  42         return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  43                 >> FREE_PLOAD_CREDIT_SHIFT;
  44 }
  45
  46 static void wait_for_header_credits(struct drm_i915_private *dev_priv,
  47                                     enum transcoder dsi_trans)
  48 {
  49         if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
  50                         MAX_HEADER_CREDIT, 100))
  51                 DRM_ERROR("DSI header credits not released\n");
  52 }
  53
  54 static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
  55                                      enum transcoder dsi_trans)
  56 {
  57         if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
  58                         MAX_PLOAD_CREDIT, 100))
  59                 DRM_ERROR("DSI payload credits not released\n");
  60 }
  61
  62 static enum transcoder dsi_port_to_transcoder(enum port port)
  63 {
  64         if (port == PORT_A)
  65                 return TRANSCODER_DSI_0;
  66         else
  67                 return TRANSCODER_DSI_1;
  68 }
  69
  70 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
  71 {
  72         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  73         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  74         struct mipi_dsi_device *dsi;
  75         enum port port;
  76         enum transcoder dsi_trans;
  77         int ret;
  78
  79         /* wait for header/payload credits to be released */
  80         for_each_dsi_port(port, intel_dsi->ports) {
  81                 dsi_trans = dsi_port_to_transcoder(port);
  82                 wait_for_header_credits(dev_priv, dsi_trans);
  83                 wait_for_payload_credits(dev_priv, dsi_trans);
  84         }
  85
  86         /* send nop DCS command */
  87         for_each_dsi_port(port, intel_dsi->ports) {
  88                 dsi = intel_dsi->dsi_hosts[port]->device;
  89                 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
  90                 dsi->channel = 0;
  91                 ret = mipi_dsi_dcs_nop(dsi);
  92                 if (ret < 0)
  93                         DRM_ERROR("error sending DCS NOP command\n");
  94         }
  95
  96         /* wait for header credits to be released */
  97         for_each_dsi_port(port, intel_dsi->ports) {
  98                 dsi_trans = dsi_port_to_transcoder(port);
  99                 wait_for_header_credits(dev_priv, dsi_trans);
 100         }
 101
 102         /* wait for LP TX in progress bit to be cleared */
 103         for_each_dsi_port(port, intel_dsi->ports) {
 104                 dsi_trans = dsi_port_to_transcoder(port);
 105                 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
 106                                   LPTX_IN_PROGRESS), 20))
 107                         DRM_ERROR("LPTX bit not cleared\n");
 108         }
 109 }
 110
 111 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
 112                                u32 len)
 113 {
 114         struct intel_dsi *intel_dsi = host->intel_dsi;
 115         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 116         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 117         int free_credits;
 118         int i, j;
 119
 120         for (i = 0; i < len; i += 4) {
 121                 u32 tmp = 0;
 122
 123                 free_credits = payload_credits_available(dev_priv, dsi_trans);
 124                 if (free_credits < 1) {
 125                         DRM_ERROR("Payload credit not available\n");
 126                         return false;
 127                 }
 128
 129                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 130                         tmp |= *data++ << 8 * j;
 131
 132                 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
 133         }
 134
 135         return true;
 136 }
 137
 138 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 139                             struct mipi_dsi_packet pkt, bool enable_lpdt)
 140 {
 141         struct intel_dsi *intel_dsi = host->intel_dsi;
 142         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 143         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 144         u32 tmp;
 145         int free_credits;
 146
 147         /* check if header credit available */
 148         free_credits = header_credits_available(dev_priv, dsi_trans);
 149         if (free_credits < 1) {
 150                 DRM_ERROR("send pkt header failed, not enough hdr credits\n");
 151                 return -1;
 152         }
 153
 154         tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
 155
 156         if (pkt.payload)
 157                 tmp |= PAYLOAD_PRESENT;
 158         else
 159                 tmp &= ~PAYLOAD_PRESENT;
 160
 161         tmp &= ~VBLANK_FENCE;
 162
 163         if (enable_lpdt)
 164                 tmp |= LP_DATA_TRANSFER;
 165
 166         tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 167         tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
 168         tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
 169         tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
 170         tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
 171         I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
 172
 173         return 0;
 174 }
 175
 176 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 177                               struct mipi_dsi_packet pkt)
 178 {
 179         /* payload queue can accept *256 bytes*, check limit */
 180         if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
 181                 DRM_ERROR("payload size exceeds max queue limit\n");
 182                 return -1;
 183         }
 184
 185         /* load data into command payload queue */
 186         if (!add_payld_to_queue(host, pkt.payload,
 187                                 pkt.payload_length)) {
 188                 DRM_ERROR("adding payload to queue failed\n");
 189                 return -1;
 190         }
 191
 192         return 0;
 193 }
 194
 195 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 196 {
 197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 198         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 199         enum port port;
 200         u32 tmp;
 201         int lane;
 202
 203         for_each_dsi_port(port, intel_dsi->ports) {
 204
 205                 /*
 206                  * Program voltage swing and pre-emphasis level values as per
 207                  * table in BSPEC under DDI buffer programing
 208                  */
 209                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 210                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 211                 tmp |= SCALING_MODE_SEL(0x2);
 212                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 213                 tmp |= RTERM_SELECT(0x6);
 214                 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
 215
 216                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
 217                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 218                 tmp |= SCALING_MODE_SEL(0x2);
 219                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 220                 tmp |= RTERM_SELECT(0x6);
 221                 I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
 222
 223                 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
 224                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 225                          RCOMP_SCALAR_MASK);
 226                 tmp |= SWING_SEL_UPPER(0x2);
 227                 tmp |= SWING_SEL_LOWER(0x2);
 228                 tmp |= RCOMP_SCALAR(0x98);
 229                 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
 230
 231                 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
 232                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 233                          RCOMP_SCALAR_MASK);
 234                 tmp |= SWING_SEL_UPPER(0x2);
 235                 tmp |= SWING_SEL_LOWER(0x2);
 236                 tmp |= RCOMP_SCALAR(0x98);
 237                 I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
 238
 239                 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
 240                 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 241                          CURSOR_COEFF_MASK);
 242                 tmp |= POST_CURSOR_1(0x0);
 243                 tmp |= POST_CURSOR_2(0x0);
 244                 tmp |= CURSOR_COEFF(0x3f);
 245                 I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
 246
 247                 for (lane = 0; lane <= 3; lane++) {
 248                         /* Bspec: must not use GRP register for write */
 249                         tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
 250                         tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 251                                  CURSOR_COEFF_MASK);
 252                         tmp |= POST_CURSOR_1(0x0);
 253                         tmp |= POST_CURSOR_2(0x0);
 254                         tmp |= CURSOR_COEFF(0x3f);
 255                         I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
 256                 }
 257         }
 258 }
 259
 260 static void configure_dual_link_mode(struct intel_encoder *encoder,
 261                                      const struct intel_crtc_state *pipe_config)
 262 {
 263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 264         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 265         u32 dss_ctl1;
 266
 267         dss_ctl1 = I915_READ(DSS_CTL1);
 268         dss_ctl1 |= SPLITTER_ENABLE;
 269         dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 270         dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 271
 272         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 273                 const struct drm_display_mode *adjusted_mode =
 274                                         &pipe_config->base.adjusted_mode;
 275                 u32 dss_ctl2;
 276                 u16 hactive = adjusted_mode->crtc_hdisplay;
 277                 u16 dl_buffer_depth;
 278
 279                 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 280                 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 281
 282                 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 283                         DRM_ERROR("DL buffer depth exceed max value\n");
 284
 285                 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 286                 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 287                 dss_ctl2 = I915_READ(DSS_CTL2);
 288                 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
 289                 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 290                 I915_WRITE(DSS_CTL2, dss_ctl2);
 291         } else {
 292                 /* Interleave */
 293                 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 294         }
 295
 296         I915_WRITE(DSS_CTL1, dss_ctl1);
 297 }
 298
 299 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 300 {
 301         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 302         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 303         enum port port;
 304         u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 305         u32 afe_clk_khz; /* 8X Clock */
 306         u32 esc_clk_div_m;
 307
 308         afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
 309                                         intel_dsi->lane_count);
 310
 311         esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 312
 313         for_each_dsi_port(port, intel_dsi->ports) {
 314                 I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
 315                            esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 316                 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
 317         }
 318
 319         for_each_dsi_port(port, intel_dsi->ports) {
 320                 I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
 321                            esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 322                 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
 323         }
 324 }
 325
 326 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 327 {
 328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 329         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 330         enum port port;
 331         u32 tmp;
 332
 333         for_each_dsi_port(port, intel_dsi->ports) {
 334                 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
 335                 tmp |= COMBO_PHY_MODE_DSI;
 336                 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
 337         }
 338
 339         for_each_dsi_port(port, intel_dsi->ports) {
 340                 intel_dsi->io_wakeref[port] =
 341                         intel_display_power_get(dev_priv,
 342                                                 port == PORT_A ?
 343                                                 POWER_DOMAIN_PORT_DDI_A_IO :
 344                                                 POWER_DOMAIN_PORT_DDI_B_IO);
 345         }
 346 }
 347
 348 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 349 {
 350         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 351         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 352         enum port port;
 353         u32 tmp;
 354         u32 lane_mask;
 355
 356         switch (intel_dsi->lane_count) {
 357         case 1:
 358                 lane_mask = PWR_DOWN_LN_3_1_0;
 359                 break;
 360         case 2:
 361                 lane_mask = PWR_DOWN_LN_3_1;
 362                 break;
 363         case 3:
 364                 lane_mask = PWR_DOWN_LN_3;
 365                 break;
 366         case 4:
 367         default:
 368                 lane_mask = PWR_UP_ALL_LANES;
 369                 break;
 370         }
 371
 372         for_each_dsi_port(port, intel_dsi->ports) {
 373                 tmp = I915_READ(ICL_PORT_CL_DW10(port));
 374                 tmp &= ~PWR_DOWN_LN_MASK;
 375                 I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
 376         }
 377 }
 378
 379 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 380 {
 381         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 382         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 383         enum port port;
 384         u32 tmp;
 385         int lane;
 386
 387         /* Step 4b(i) set loadgen select for transmit and aux lanes */
 388         for_each_dsi_port(port, intel_dsi->ports) {
 389                 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
 390                 tmp &= ~LOADGEN_SELECT;
 391                 I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
 392                 for (lane = 0; lane <= 3; lane++) {
 393                         tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
 394                         tmp &= ~LOADGEN_SELECT;
 395                         if (lane != 2)
 396                                 tmp |= LOADGEN_SELECT;
 397                         I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
 398                 }
 399         }
 400
 401         /* Step 4b(ii) set latency optimization for transmit and aux lanes */
 402         for_each_dsi_port(port, intel_dsi->ports) {
 403                 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
 404                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 405                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 406                 I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
 407                 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
 408                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 409                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 410                 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
 411         }
 412
 413 }
 414
 415 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 416 {
 417         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 418         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 419         u32 tmp;
 420         enum port port;
 421
 422         /* clear common keeper enable bit */
 423         for_each_dsi_port(port, intel_dsi->ports) {
 424                 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
 425                 tmp &= ~COMMON_KEEPER_EN;
 426                 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
 427                 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
 428                 tmp &= ~COMMON_KEEPER_EN;
 429                 I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
 430         }
 431
 432         /*
 433          * Set SUS Clock Config bitfield to 11b
 434          * Note: loadgen select program is done
 435          * as part of lane phy sequence configuration
 436          */
 437         for_each_dsi_port(port, intel_dsi->ports) {
 438                 tmp = I915_READ(ICL_PORT_CL_DW5(port));
 439                 tmp |= SUS_CLOCK_CONFIG;
 440                 I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
 441         }
 442
 443         /* Clear training enable to change swing values */
 444         for_each_dsi_port(port, intel_dsi->ports) {
 445                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 446                 tmp &= ~TX_TRAINING_EN;
 447                 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
 448                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
 449                 tmp &= ~TX_TRAINING_EN;
 450                 I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
 451         }
 452
 453         /* Program swing and de-emphasis */
 454         dsi_program_swing_and_deemphasis(encoder);
 455
 456         /* Set training enable to trigger update */
 457         for_each_dsi_port(port, intel_dsi->ports) {
 458                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 459                 tmp |= TX_TRAINING_EN;
 460                 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
 461                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
 462                 tmp |= TX_TRAINING_EN;
 463                 I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
 464         }
 465 }
 466
 467 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 468 {
 469         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 470         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 471         u32 tmp;
 472         enum port port;
 473
 474         for_each_dsi_port(port, intel_dsi->ports) {
 475                 tmp = I915_READ(DDI_BUF_CTL(port));
 476                 tmp |= DDI_BUF_CTL_ENABLE;
 477                 I915_WRITE(DDI_BUF_CTL(port), tmp);
 478
 479                 if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
 480                                   DDI_BUF_IS_IDLE),
 481                                   500))
 482                         DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
 483         }
 484 }
 485
 486 static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 487 {
 488         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 489         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 490         u32 tmp;
 491         enum port port;
 492
 493         /* Program T-INIT master registers */
 494         for_each_dsi_port(port, intel_dsi->ports) {
 495                 tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
 496                 tmp &= ~MASTER_INIT_TIMER_MASK;
 497                 tmp |= intel_dsi->init_count;
 498                 I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
 499         }
 500
 501         /* Program DPHY clock lanes timings */
 502         for_each_dsi_port(port, intel_dsi->ports) {
 503                 I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
 504
 505                 /* shadow register inside display core */
 506                 I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
 507         }
 508
 509         /* Program DPHY data lanes timings */
 510         for_each_dsi_port(port, intel_dsi->ports) {
 511                 I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
 512                            intel_dsi->dphy_data_lane_reg);
 513
 514                 /* shadow register inside display core */
 515                 I915_WRITE(DSI_DATA_TIMING_PARAM(port),
 516                            intel_dsi->dphy_data_lane_reg);
 517         }
 518
 519         /*
 520          * If DSI link operating at or below an 800 MHz,
 521          * TA_SURE should be override and programmed to
 522          * a value '0' inside TA_PARAM_REGISTERS otherwise
 523          * leave all fields at HW default values.
 524          */
 525         if (intel_dsi_bitrate(intel_dsi) <= 800000) {
 526                 for_each_dsi_port(port, intel_dsi->ports) {
 527                         tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
 528                         tmp &= ~TA_SURE_MASK;
 529                         tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 530                         I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
 531
 532                         /* shadow register inside display core */
 533                         tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
 534                         tmp &= ~TA_SURE_MASK;
 535                         tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 536                         I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
 537                 }
 538         }
 539 }
 540
 541 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 542 {
 543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 544         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 545         u32 tmp;
 546         enum port port;
 547
 548         mutex_lock(&dev_priv->dpll_lock);
 549         tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 550         for_each_dsi_port(port, intel_dsi->ports) {
 551                 tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 552         }
 553
 554         I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
 555         mutex_unlock(&dev_priv->dpll_lock);
 556 }
 557
 558 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 559 {
 560         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 561         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 562         u32 tmp;
 563         enum port port;
 564
 565         mutex_lock(&dev_priv->dpll_lock);
 566         tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 567         for_each_dsi_port(port, intel_dsi->ports) {
 568                 tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 569         }
 570
 571         I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
 572         mutex_unlock(&dev_priv->dpll_lock);
 573 }
 574
 575 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 576                               const struct intel_crtc_state *crtc_state)
 577 {
 578         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 579         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 580         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 581         enum port port;
 582         u32 val;
 583
 584         mutex_lock(&dev_priv->dpll_lock);
 585
 586         val = I915_READ(DPCLKA_CFGCR0_ICL);
 587         for_each_dsi_port(port, intel_dsi->ports) {
 588                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 589                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 590         }
 591         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 592         POSTING_READ(DPCLKA_CFGCR0_ICL);
 593
 594         mutex_unlock(&dev_priv->dpll_lock);
 595 }
 596
 597 static void
 598 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 599                                const struct intel_crtc_state *pipe_config)
 600 {
 601         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 602         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 603         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 604         enum pipe pipe = intel_crtc->pipe;
 605         u32 tmp;
 606         enum port port;
 607         enum transcoder dsi_trans;
 608
 609         for_each_dsi_port(port, intel_dsi->ports) {
 610                 dsi_trans = dsi_port_to_transcoder(port);
 611                 tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
 612
 613                 if (intel_dsi->eotp_pkt)
 614                         tmp &= ~EOTP_DISABLED;
 615                 else
 616                         tmp |= EOTP_DISABLED;
 617
 618                 /* enable link calibration if freq > 1.5Gbps */
 619                 if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
 620                         tmp &= ~LINK_CALIBRATION_MASK;
 621                         tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 622                 }
 623
 624                 /* configure continuous clock */
 625                 tmp &= ~CONTINUOUS_CLK_MASK;
 626                 if (intel_dsi->clock_stop)
 627                         tmp |= CLK_ENTER_LP_AFTER_DATA;
 628                 else
 629                         tmp |= CLK_HS_CONTINUOUS;
 630
 631                 /* configure buffer threshold limit to minimum */
 632                 tmp &= ~PIX_BUF_THRESHOLD_MASK;
 633                 tmp |= PIX_BUF_THRESHOLD_1_4;
 634
 635                 /* set virtual channel to '0' */
 636                 tmp &= ~PIX_VIRT_CHAN_MASK;
 637                 tmp |= PIX_VIRT_CHAN(0);
 638
 639                 /* program BGR transmission */
 640                 if (intel_dsi->bgr_enabled)
 641                         tmp |= BGR_TRANSMISSION;
 642
 643                 /* select pixel format */
 644                 tmp &= ~PIX_FMT_MASK;
 645                 switch (intel_dsi->pixel_format) {
 646                 default:
 647                         MISSING_CASE(intel_dsi->pixel_format);
 648                         /* fallthrough */
 649                 case MIPI_DSI_FMT_RGB565:
 650                         tmp |= PIX_FMT_RGB565;
 651                         break;
 652                 case MIPI_DSI_FMT_RGB666_PACKED:
 653                         tmp |= PIX_FMT_RGB666_PACKED;
 654                         break;
 655                 case MIPI_DSI_FMT_RGB666:
 656                         tmp |= PIX_FMT_RGB666_LOOSE;
 657                         break;
 658                 case MIPI_DSI_FMT_RGB888:
 659                         tmp |= PIX_FMT_RGB888;
 660                         break;
 661                 }
 662
 663                 /* program DSI operation mode */
 664                 if (is_vid_mode(intel_dsi)) {
 665                         tmp &= ~OP_MODE_MASK;
 666                         switch (intel_dsi->video_mode_format) {
 667                         default:
 668                                 MISSING_CASE(intel_dsi->video_mode_format);
 669                                 /* fallthrough */
 670                         case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
 671                                 tmp |= VIDEO_MODE_SYNC_EVENT;
 672                                 break;
 673                         case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
 674                                 tmp |= VIDEO_MODE_SYNC_PULSE;
 675                                 break;
 676                         }
 677                 }
 678
 679                 I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 680         }
 681
 682         /* enable port sync mode if dual link */
 683         if (intel_dsi->dual_link) {
 684                 for_each_dsi_port(port, intel_dsi->ports) {
 685                         dsi_trans = dsi_port_to_transcoder(port);
 686                         tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
 687                         tmp |= PORT_SYNC_MODE_ENABLE;
 688                         I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
 689                 }
 690
 691                 /* configure stream splitting */
 692                 configure_dual_link_mode(encoder, pipe_config);
 693         }
 694
 695         for_each_dsi_port(port, intel_dsi->ports) {
 696                 dsi_trans = dsi_port_to_transcoder(port);
 697
 698                 /* select data lane width */
 699                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
 700                 tmp &= ~DDI_PORT_WIDTH_MASK;
 701                 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 702
 703                 /* select input pipe */
 704                 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 705                 switch (pipe) {
 706                 default:
 707                         MISSING_CASE(pipe);
 708                         /* fallthrough */
 709                 case PIPE_A:
 710                         tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 711                         break;
 712                 case PIPE_B:
 713                         tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 714                         break;
 715                 case PIPE_C:
 716                         tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 717                         break;
 718                 }
 719
 720                 /* enable DDI buffer */
 721                 tmp |= TRANS_DDI_FUNC_ENABLE;
 722                 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
 723         }
 724
 725         /* wait for link ready */
 726         for_each_dsi_port(port, intel_dsi->ports) {
 727                 dsi_trans = dsi_port_to_transcoder(port);
 728                 if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
 729                                 LINK_READY), 2500))
 730                         DRM_ERROR("DSI link not ready\n");
 731         }
 732 }
 733
 734 static void
 735 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 736                                  const struct intel_crtc_state *pipe_config)
 737 {
 738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 739         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 740         const struct drm_display_mode *adjusted_mode =
 741                                         &pipe_config->base.adjusted_mode;
 742         enum port port;
 743         enum transcoder dsi_trans;
 744         /* horizontal timings */
 745         u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 746         u16 hfront_porch, hback_porch;
 747         /* vertical timings */
 748         u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 749
 750         hactive = adjusted_mode->crtc_hdisplay;
 751         htotal = adjusted_mode->crtc_htotal;
 752         hsync_start = adjusted_mode->crtc_hsync_start;
 753         hsync_end = adjusted_mode->crtc_hsync_end;
 754         hsync_size  = hsync_end - hsync_start;
 755         hfront_porch = (adjusted_mode->crtc_hsync_start -
 756                         adjusted_mode->crtc_hdisplay);
 757         hback_porch = (adjusted_mode->crtc_htotal -
 758                        adjusted_mode->crtc_hsync_end);
 759         vactive = adjusted_mode->crtc_vdisplay;
 760         vtotal = adjusted_mode->crtc_vtotal;
 761         vsync_start = adjusted_mode->crtc_vsync_start;
 762         vsync_end = adjusted_mode->crtc_vsync_end;
 763         vsync_shift = hsync_start - htotal / 2;
 764
 765         if (intel_dsi->dual_link) {
 766                 hactive /= 2;
 767                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 768                         hactive += intel_dsi->pixel_overlap;
 769                 htotal /= 2;
 770         }
 771
 772         /* minimum hactive as per bspec: 256 pixels */
 773         if (adjusted_mode->crtc_hdisplay < 256)
 774                 DRM_ERROR("hactive is less then 256 pixels\n");
 775
 776         /* if RGB666 format, then hactive must be multiple of 4 pixels */
 777         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 778                 DRM_ERROR("hactive pixels are not multiple of 4\n");
 779
 780         /* program TRANS_HTOTAL register */
 781         for_each_dsi_port(port, intel_dsi->ports) {
 782                 dsi_trans = dsi_port_to_transcoder(port);
 783                 I915_WRITE(HTOTAL(dsi_trans),
 784                            (hactive - 1) | ((htotal - 1) << 16));
 785         }
 786
 787         /* TRANS_HSYNC register to be programmed only for video mode */
 788         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
 789                 if (intel_dsi->video_mode_format ==
 790                     VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 791                         /* BSPEC: hsync size should be atleast 16 pixels */
 792                         if (hsync_size < 16)
 793                                 DRM_ERROR("hsync size < 16 pixels\n");
 794                 }
 795
 796                 if (hback_porch < 16)
 797                         DRM_ERROR("hback porch < 16 pixels\n");
 798
 799                 if (intel_dsi->dual_link) {
 800                         hsync_start /= 2;
 801                         hsync_end /= 2;
 802                 }
 803
 804                 for_each_dsi_port(port, intel_dsi->ports) {
 805                         dsi_trans = dsi_port_to_transcoder(port);
 806                         I915_WRITE(HSYNC(dsi_trans),
 807                                    (hsync_start - 1) | ((hsync_end - 1) << 16));
 808                 }
 809         }
 810
 811         /* program TRANS_VTOTAL register */
 812         for_each_dsi_port(port, intel_dsi->ports) {
 813                 dsi_trans = dsi_port_to_transcoder(port);
 814                 /*
 815                  * FIXME: Programing this by assuming progressive mode, since
 816                  * non-interlaced info from VBT is not saved inside
 817                  * struct drm_display_mode.
 818                  * For interlace mode: program required pixel minus 2
 819                  */
 820                 I915_WRITE(VTOTAL(dsi_trans),
 821                            (vactive - 1) | ((vtotal - 1) << 16));
 822         }
 823
 824         if (vsync_end < vsync_start || vsync_end > vtotal)
 825                 DRM_ERROR("Invalid vsync_end value\n");
 826
 827         if (vsync_start < vactive)
 828                 DRM_ERROR("vsync_start less than vactive\n");
 829
 830         /* program TRANS_VSYNC register */
 831         for_each_dsi_port(port, intel_dsi->ports) {
 832                 dsi_trans = dsi_port_to_transcoder(port);
 833                 I915_WRITE(VSYNC(dsi_trans),
 834                            (vsync_start - 1) | ((vsync_end - 1) << 16));
 835         }
 836
 837         /*
 838          * FIXME: It has to be programmed only for interlaced
 839          * modes. Put the check condition here once interlaced
 840          * info available as described above.
 841          * program TRANS_VSYNCSHIFT register
 842          */
 843         for_each_dsi_port(port, intel_dsi->ports) {
 844                 dsi_trans = dsi_port_to_transcoder(port);
 845                 I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
 846         }
 847 }
 848
 849 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 850 {
 851         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 852         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 853         enum port port;
 854         enum transcoder dsi_trans;
 855         u32 tmp;
 856
 857         for_each_dsi_port(port, intel_dsi->ports) {
 858                 dsi_trans = dsi_port_to_transcoder(port);
 859                 tmp = I915_READ(PIPECONF(dsi_trans));
 860                 tmp |= PIPECONF_ENABLE;
 861                 I915_WRITE(PIPECONF(dsi_trans), tmp);
 862
 863                 /* wait for transcoder to be enabled */
 864                 if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
 865                                             I965_PIPECONF_ACTIVE,
 866                                             I965_PIPECONF_ACTIVE, 10))
 867                         DRM_ERROR("DSI transcoder not enabled\n");
 868         }
 869 }
 870
 871 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 872 {
 873         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 874         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 875         enum port port;
 876         enum transcoder dsi_trans;
 877         u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
 878
 879         /*
 880          * escape clock count calculation:
 881          * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
 882          * UI (nsec) = (10^6)/Bitrate
 883          * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
 884          * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
 885          */
 886         divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
 887         mul = 8 * 1000000;
 888         hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
 889                                      divisor);
 890         lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
 891         ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
 892
 893         for_each_dsi_port(port, intel_dsi->ports) {
 894                 dsi_trans = dsi_port_to_transcoder(port);
 895
 896                 /* program hst_tx_timeout */
 897                 tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
 898                 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
 899                 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
 900                 I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
 901
 902                 /* FIXME: DSI_CALIB_TO */
 903
 904                 /* program lp_rx_host timeout */
 905                 tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
 906                 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
 907                 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
 908                 I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
 909
 910                 /* FIXME: DSI_PWAIT_TO */
 911
 912                 /* program turn around timeout */
 913                 tmp = I915_READ(DSI_TA_TO(dsi_trans));
 914                 tmp &= ~TA_TIMEOUT_VALUE_MASK;
 915                 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
 916                 I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
 917         }
 918 }
 919
 920 static void
 921 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 922                               const struct intel_crtc_state *pipe_config)
 923 {
 924         /* step 4a: power up all lanes of the DDI used by DSI */
 925         gen11_dsi_power_up_lanes(encoder);
 926
 927         /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
 928         gen11_dsi_config_phy_lanes_sequence(encoder);
 929
 930         /* step 4c: configure voltage swing and skew */
 931         gen11_dsi_voltage_swing_program_seq(encoder);
 932
 933         /* enable DDI buffer */
 934         gen11_dsi_enable_ddi_buffer(encoder);
 935
 936         /* setup D-PHY timings */
 937         gen11_dsi_setup_dphy_timings(encoder);
 938
 939         /* step 4h: setup DSI protocol timeouts */
 940         gen11_dsi_setup_timeouts(encoder);
 941
 942         /* Step (4h, 4i, 4j, 4k): Configure transcoder */
 943         gen11_dsi_configure_transcoder(encoder, pipe_config);
 944
 945         /* Step 4l: Gate DDI clocks */
 946         gen11_dsi_gate_clocks(encoder);
 947 }
 948
 949 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 950 {
 951         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 952         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 953         struct mipi_dsi_device *dsi;
 954         enum port port;
 955         enum transcoder dsi_trans;
 956         u32 tmp;
 957         int ret;
 958
 959         /* set maximum return packet size */
 960         for_each_dsi_port(port, intel_dsi->ports) {
 961                 dsi_trans = dsi_port_to_transcoder(port);
 962
 963                 /*
 964                  * FIXME: This uses the number of DW's currently in the payload
 965                  * receive queue. This is probably not what we want here.
 966                  */
 967                 tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
 968                 tmp &= NUMBER_RX_PLOAD_DW_MASK;
 969                 /* multiply "Number Rx Payload DW" by 4 to get max value */
 970                 tmp = tmp * 4;
 971                 dsi = intel_dsi->dsi_hosts[port]->device;
 972                 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
 973                 if (ret < 0)
 974                         DRM_ERROR("error setting max return pkt size%d\n", tmp);
 975         }
 976
 977         /* panel power on related mipi dsi vbt sequences */
 978         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 979         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 980         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 981         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 982         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 983
 984         /* ensure all panel commands dispatched before enabling transcoder */
 985         wait_for_cmds_dispatched_to_panel(encoder);
 986 }
 987
 988 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
 989                                      const struct intel_crtc_state *pipe_config,
 990                                      const struct drm_connector_state *conn_state)
 991 {
 992         /* step2: enable IO power */
 993         gen11_dsi_enable_io_power(encoder);
 994
 995         /* step3: enable DSI PLL */
 996         gen11_dsi_program_esc_clk_div(encoder);
 997 }
 998
 999 static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
1000                                  const struct intel_crtc_state *pipe_config,
1001                                  const struct drm_connector_state *conn_state)
1002 {
1003         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1004
1005         /* step3b */
1006         gen11_dsi_map_pll(encoder, pipe_config);
1007
1008         /* step4: enable DSI port and DPHY */
1009         gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1010
1011         /* step5: program and powerup panel */
1012         gen11_dsi_powerup_panel(encoder);
1013
1014         /* step6c: configure transcoder timings */
1015         gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1016
1017         /* step6d: enable dsi transcoder */
1018         gen11_dsi_enable_transcoder(encoder);
1019
1020         /* step7: enable backlight */
1021         intel_panel_enable_backlight(pipe_config, conn_state);
1022         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1023 }
1024
1025 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1026 {
1027         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1028         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1029         enum port port;
1030         enum transcoder dsi_trans;
1031         u32 tmp;
1032
1033         for_each_dsi_port(port, intel_dsi->ports) {
1034                 dsi_trans = dsi_port_to_transcoder(port);
1035
1036                 /* disable transcoder */
1037                 tmp = I915_READ(PIPECONF(dsi_trans));
1038                 tmp &= ~PIPECONF_ENABLE;
1039                 I915_WRITE(PIPECONF(dsi_trans), tmp);
1040
1041                 /* wait for transcoder to be disabled */
1042                 if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
1043                                             I965_PIPECONF_ACTIVE, 0, 50))
1044                         DRM_ERROR("DSI trancoder not disabled\n");
1045         }
1046 }
1047
1048 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1049 {
1050         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1051
1052         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1053         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1054         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1055
1056         /* ensure cmds dispatched to panel */
1057         wait_for_cmds_dispatched_to_panel(encoder);
1058 }
1059
1060 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1061 {
1062         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1063         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1064         enum port port;
1065         enum transcoder dsi_trans;
1066         u32 tmp;
1067
1068         /* put dsi link in ULPS */
1069         for_each_dsi_port(port, intel_dsi->ports) {
1070                 dsi_trans = dsi_port_to_transcoder(port);
1071                 tmp = I915_READ(DSI_LP_MSG(dsi_trans));
1072                 tmp |= LINK_ENTER_ULPS;
1073                 tmp &= ~LINK_ULPS_TYPE_LP11;
1074                 I915_WRITE(DSI_LP_MSG(dsi_trans), tmp);
1075
1076                 if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) &
1077                                 LINK_IN_ULPS),
1078                                 10))
1079                         DRM_ERROR("DSI link not in ULPS\n");
1080         }
1081
1082         /* disable ddi function */
1083         for_each_dsi_port(port, intel_dsi->ports) {
1084                 dsi_trans = dsi_port_to_transcoder(port);
1085                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1086                 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1087                 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1088         }
1089
1090         /* disable port sync mode if dual link */
1091         if (intel_dsi->dual_link) {
1092                 for_each_dsi_port(port, intel_dsi->ports) {
1093                         dsi_trans = dsi_port_to_transcoder(port);
1094                         tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
1095                         tmp &= ~PORT_SYNC_MODE_ENABLE;
1096                         I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1097                 }
1098         }
1099 }
1100
1101 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1102 {
1103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1104         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1105         u32 tmp;
1106         enum port port;
1107
1108         gen11_dsi_ungate_clocks(encoder);
1109         for_each_dsi_port(port, intel_dsi->ports) {
1110                 tmp = I915_READ(DDI_BUF_CTL(port));
1111                 tmp &= ~DDI_BUF_CTL_ENABLE;
1112                 I915_WRITE(DDI_BUF_CTL(port), tmp);
1113
1114                 if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) &
1115                                  DDI_BUF_IS_IDLE),
1116                                  8))
1117                         DRM_ERROR("DDI port:%c buffer not idle\n",
1118                                   port_name(port));
1119         }
1120         gen11_dsi_ungate_clocks(encoder);
1121 }
1122
1123 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1124 {
1125         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1126         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1127         enum port port;
1128         u32 tmp;
1129
1130         for_each_dsi_port(port, intel_dsi->ports) {
1131                 intel_wakeref_t wakeref;
1132
1133                 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1134                 if (wakeref) {
1135                         intel_display_power_put(dev_priv,
1136                                                 port == PORT_A ?
1137                                                 POWER_DOMAIN_PORT_DDI_A_IO :
1138                                                 POWER_DOMAIN_PORT_DDI_B_IO,
1139                                                 wakeref);
1140                 }
1141         }
1142
1143         /* set mode to DDI */
1144         for_each_dsi_port(port, intel_dsi->ports) {
1145                 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
1146                 tmp &= ~COMBO_PHY_MODE_DSI;
1147                 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
1148         }
1149 }
1150
1151 static void gen11_dsi_disable(struct intel_encoder *encoder,
1152                               const struct intel_crtc_state *old_crtc_state,
1153                               const struct drm_connector_state *old_conn_state)
1154 {
1155         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1156
1157         /* step1: turn off backlight */
1158         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1159         intel_panel_disable_backlight(old_conn_state);
1160
1161         /* step2d,e: disable transcoder and wait */
1162         gen11_dsi_disable_transcoder(encoder);
1163
1164         /* step2f,g: powerdown panel */
1165         gen11_dsi_powerdown_panel(encoder);
1166
1167         /* step2h,i,j: deconfig trancoder */
1168         gen11_dsi_deconfigure_trancoder(encoder);
1169
1170         /* step3: disable port */
1171         gen11_dsi_disable_port(encoder);
1172
1173         /* step4: disable IO power */
1174         gen11_dsi_disable_io_power(encoder);
1175 }
1176
1177 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1178                                  struct intel_crtc_state *pipe_config)
1179 {
1180         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1181         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1182         u32 pll_id;
1183
1184         /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
1185         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1186         pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1187         pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
1188         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1189 }
1190
1191 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1192                                     struct intel_crtc_state *pipe_config,
1193                                     struct drm_connector_state *conn_state)
1194 {
1195         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1196                                                    base);
1197         struct intel_connector *intel_connector = intel_dsi->attached_connector;
1198         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1199         const struct drm_display_mode *fixed_mode =
1200                                         intel_connector->panel.fixed_mode;
1201         struct drm_display_mode *adjusted_mode =
1202                                         &pipe_config->base.adjusted_mode;
1203
1204         intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1205         intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
1206
1207         adjusted_mode->flags = 0;
1208
1209         /* Dual link goes to trancoder DSI'0' */
1210         if (intel_dsi->ports == BIT(PORT_B))
1211                 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1212         else
1213                 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1214
1215         pipe_config->clock_set = true;
1216         pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
1217
1218         return 0;
1219 }
1220
1221 static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1222                                        struct intel_crtc_state *crtc_state)
1223 {
1224         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1225         u64 domains = 0;
1226         enum port port;
1227
1228         for_each_dsi_port(port, intel_dsi->ports)
1229                 if (port == PORT_A)
1230                         domains |= BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO);
1231                 else
1232                         domains |= BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO);
1233
1234         return domains;
1235 }
1236
1237 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1238                                    enum pipe *pipe)
1239 {
1240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1241         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1242         enum transcoder dsi_trans;
1243         intel_wakeref_t wakeref;
1244         enum port port;
1245         bool ret = false;
1246         u32 tmp;
1247
1248         wakeref = intel_display_power_get_if_enabled(dev_priv,
1249                                                      encoder->power_domain);
1250         if (!wakeref)
1251                 return false;
1252
1253         for_each_dsi_port(port, intel_dsi->ports) {
1254                 dsi_trans = dsi_port_to_transcoder(port);
1255                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1256                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1257                 case TRANS_DDI_EDP_INPUT_A_ON:
1258                         *pipe = PIPE_A;
1259                         break;
1260                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1261                         *pipe = PIPE_B;
1262                         break;
1263                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1264                         *pipe = PIPE_C;
1265                         break;
1266                 default:
1267                         DRM_ERROR("Invalid PIPE input\n");
1268                         goto out;
1269                 }
1270
1271                 tmp = I915_READ(PIPECONF(dsi_trans));
1272                 ret = tmp & PIPECONF_ENABLE;
1273         }
1274 out:
1275         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1276         return ret;
1277 }
1278
1279 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1280 {
1281         intel_encoder_destroy(encoder);
1282 }
1283
1284 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1285         .destroy = gen11_dsi_encoder_destroy,
1286 };
1287
1288 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1289         .late_register = intel_connector_register,
1290         .early_unregister = intel_connector_unregister,
1291         .destroy = intel_connector_destroy,
1292         .fill_modes = drm_helper_probe_single_connector_modes,
1293         .atomic_get_property = intel_digital_connector_atomic_get_property,
1294         .atomic_set_property = intel_digital_connector_atomic_set_property,
1295         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1296         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1297 };
1298
1299 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1300         .get_modes = intel_dsi_get_modes,
1301         .mode_valid = intel_dsi_mode_valid,
1302         .atomic_check = intel_digital_connector_atomic_check,
1303 };
1304
1305 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1306                                  struct mipi_dsi_device *dsi)
1307 {
1308         return 0;
1309 }
1310
1311 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1312                                  struct mipi_dsi_device *dsi)
1313 {
1314         return 0;
1315 }
1316
1317 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1318                                        const struct mipi_dsi_msg *msg)
1319 {
1320         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1321         struct mipi_dsi_packet dsi_pkt;
1322         ssize_t ret;
1323         bool enable_lpdt = false;
1324
1325         ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1326         if (ret < 0)
1327                 return ret;
1328
1329         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1330                 enable_lpdt = true;
1331
1332         /* send packet header */
1333         ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1334         if (ret < 0)
1335                 return ret;
1336
1337         /* only long packet contains payload */
1338         if (mipi_dsi_packet_format_is_long(msg->type)) {
1339                 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1340                 if (ret < 0)
1341                         return ret;
1342         }
1343
1344         //TODO: add payload receive code if needed
1345
1346         ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1347
1348         return ret;
1349 }
1350
1351 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1352         .attach = gen11_dsi_host_attach,
1353         .detach = gen11_dsi_host_detach,
1354         .transfer = gen11_dsi_host_transfer,
1355 };
1356
1357 void icl_dsi_init(struct drm_i915_private *dev_priv)
1358 {
1359         struct drm_device *dev = &dev_priv->drm;
1360         struct intel_dsi *intel_dsi;
1361         struct intel_encoder *encoder;
1362         struct intel_connector *intel_connector;
1363         struct drm_connector *connector;
1364         struct drm_display_mode *scan, *fixed_mode = NULL;
1365         enum port port;
1366
1367         if (!intel_bios_is_dsi_present(dev_priv, &port))
1368                 return;
1369
1370         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1371         if (!intel_dsi)
1372                 return;
1373
1374         intel_connector = intel_connector_alloc();
1375         if (!intel_connector) {
1376                 kfree(intel_dsi);
1377                 return;
1378         }
1379
1380         encoder = &intel_dsi->base;
1381         intel_dsi->attached_connector = intel_connector;
1382         connector = &intel_connector->base;
1383
1384         /* register DSI encoder with DRM subsystem */
1385         drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
1386                          DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1387
1388         encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1389         encoder->pre_enable = gen11_dsi_pre_enable;
1390         encoder->disable = gen11_dsi_disable;
1391         encoder->port = port;
1392         encoder->get_config = gen11_dsi_get_config;
1393         encoder->update_pipe = intel_panel_update_backlight;
1394         encoder->compute_config = gen11_dsi_compute_config;
1395         encoder->get_hw_state = gen11_dsi_get_hw_state;
1396         encoder->type = INTEL_OUTPUT_DSI;
1397         encoder->cloneable = 0;
1398         encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1399         encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1400         encoder->get_power_domains = gen11_dsi_get_power_domains;
1401
1402         /* register DSI connector with DRM subsystem */
1403         drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
1404                            DRM_MODE_CONNECTOR_DSI);
1405         drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1406         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1407         connector->interlace_allowed = false;
1408         connector->doublescan_allowed = false;
1409         intel_connector->get_hw_state = intel_connector_get_hw_state;
1410
1411         /* attach connector to encoder */
1412         intel_connector_attach_encoder(intel_connector, encoder);
1413
1414         /* fill mode info from VBT */
1415         mutex_lock(&dev->mode_config.mutex);
1416         intel_dsi_vbt_get_modes(intel_dsi);
1417         list_for_each_entry(scan, &connector->probed_modes, head) {
1418                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1419                         fixed_mode = drm_mode_duplicate(dev, scan);
1420                         break;
1421                 }
1422         }
1423         mutex_unlock(&dev->mode_config.mutex);
1424
1425         if (!fixed_mode) {
1426                 DRM_ERROR("DSI fixed mode info missing\n");
1427                 goto err;
1428         }
1429
1430         connector->display_info.width_mm = fixed_mode->width_mm;
1431         connector->display_info.height_mm = fixed_mode->height_mm;
1432         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1433         intel_panel_setup_backlight(connector, INVALID_PIPE);
1434
1435
1436         if (dev_priv->vbt.dsi.config->dual_link)
1437                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1438         else
1439                 intel_dsi->ports = BIT(port);
1440
1441         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1442         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1443
1444         for_each_dsi_port(port, intel_dsi->ports) {
1445                 struct intel_dsi_host *host;
1446
1447                 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
1448                 if (!host)
1449                         goto err;
1450
1451                 intel_dsi->dsi_hosts[port] = host;
1452         }
1453
1454         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1455                 DRM_DEBUG_KMS("no device found\n");
1456                 goto err;
1457         }
1458
1459         return;
1460
1461 err:
1462         drm_encoder_cleanup(&encoder->base);
1463         kfree(intel_dsi);
1464         kfree(intel_connector);
1465 }