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25 #include <linux/dma-fence-array.h>
26 #include <linux/dma-fence-chain.h>
27 #include <linux/irq_work.h>
28 #include <linux/prefetch.h>
29 #include <linux/sched.h>
30 #include <linux/sched/clock.h>
31 #include <linux/sched/signal.h>
32 #include <linux/sched/mm.h>
34 #include "gem/i915_gem_context.h"
35 #include "gt/intel_breadcrumbs.h"
36 #include "gt/intel_context.h"
37 #include "gt/intel_engine.h"
38 #include "gt/intel_engine_heartbeat.h"
39 #include "gt/intel_engine_regs.h"
40 #include "gt/intel_gpu_commands.h"
41 #include "gt/intel_reset.h"
42 #include "gt/intel_ring.h"
43 #include "gt/intel_rps.h"
45 #include "i915_active.h"
46 #include "i915_config.h"
47 #include "i915_deps.h"
48 #include "i915_driver.h"
50 #include "i915_trace.h"
54 struct i915_sw_fence *fence;
55 struct i915_request *signal;
58 static struct kmem_cache *slab_requests;
59 static struct kmem_cache *slab_execute_cbs;
61 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
63 return dev_name(to_request(fence)->i915->drm.dev);
66 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
68 const struct i915_gem_context *ctx;
71 * The timeline struct (as part of the ppgtt underneath a context)
72 * may be freed when the request is no longer in use by the GPU.
73 * We could extend the life of a context to beyond that of all
74 * fences, possibly keeping the hw resource around indefinitely,
75 * or we just give them a false name. Since
76 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
77 * lie seems justifiable.
79 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
82 ctx = i915_request_gem_context(to_request(fence));
84 return "[" DRIVER_NAME "]";
89 static bool i915_fence_signaled(struct dma_fence *fence)
91 return i915_request_completed(to_request(fence));
94 static bool i915_fence_enable_signaling(struct dma_fence *fence)
96 return i915_request_enable_breadcrumb(to_request(fence));
99 static signed long i915_fence_wait(struct dma_fence *fence,
103 return i915_request_wait_timeout(to_request(fence),
104 interruptible | I915_WAIT_PRIORITY,
108 struct kmem_cache *i915_request_slab_cache(void)
110 return slab_requests;
113 static void i915_fence_release(struct dma_fence *fence)
115 struct i915_request *rq = to_request(fence);
117 GEM_BUG_ON(rq->guc_prio != GUC_PRIO_INIT &&
118 rq->guc_prio != GUC_PRIO_FINI);
120 i915_request_free_capture_list(fetch_and_zero(&rq->capture_list));
122 i915_vma_resource_put(rq->batch_res);
123 rq->batch_res = NULL;
127 * The request is put onto a RCU freelist (i.e. the address
128 * is immediately reused), mark the fences as being freed now.
129 * Otherwise the debugobjects for the fences are only marked as
130 * freed when the slab cache itself is freed, and so we would get
131 * caught trying to reuse dead objects.
133 i915_sw_fence_fini(&rq->submit);
134 i915_sw_fence_fini(&rq->semaphore);
137 * Keep one request on each engine for reserved use under mempressure.
139 * We do not hold a reference to the engine here and so have to be
140 * very careful in what rq->engine we poke. The virtual engine is
141 * referenced via the rq->context and we released that ref during
142 * i915_request_retire(), ergo we must not dereference a virtual
143 * engine here. Not that we would want to, as the only consumer of
144 * the reserved engine->request_pool is the power management parking,
145 * which must-not-fail, and that is only run on the physical engines.
147 * Since the request must have been executed to be have completed,
148 * we know that it will have been processed by the HW and will
149 * not be unsubmitted again, so rq->engine and rq->execution_mask
150 * at this point is stable. rq->execution_mask will be a single
151 * bit if the last and _only_ engine it could execution on was a
152 * physical engine, if it's multiple bits then it started on and
153 * could still be on a virtual engine. Thus if the mask is not a
154 * power-of-two we assume that rq->engine may still be a virtual
155 * engine and so a dangling invalid pointer that we cannot dereference
157 * For example, consider the flow of a bonded request through a virtual
158 * engine. The request is created with a wide engine mask (all engines
159 * that we might execute on). On processing the bond, the request mask
160 * is reduced to one or more engines. If the request is subsequently
161 * bound to a single engine, it will then be constrained to only
162 * execute on that engine and never returned to the virtual engine
163 * after timeslicing away, see __unwind_incomplete_requests(). Thus we
164 * know that if the rq->execution_mask is a single bit, rq->engine
165 * can be a physical engine with the exact corresponding mask.
167 if (is_power_of_2(rq->execution_mask) &&
168 !cmpxchg(&rq->engine->request_pool, NULL, rq))
171 kmem_cache_free(slab_requests, rq);
174 const struct dma_fence_ops i915_fence_ops = {
175 .get_driver_name = i915_fence_get_driver_name,
176 .get_timeline_name = i915_fence_get_timeline_name,
177 .enable_signaling = i915_fence_enable_signaling,
178 .signaled = i915_fence_signaled,
179 .wait = i915_fence_wait,
180 .release = i915_fence_release,
183 static void irq_execute_cb(struct irq_work *wrk)
185 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
187 i915_sw_fence_complete(cb->fence);
188 kmem_cache_free(slab_execute_cbs, cb);
191 static __always_inline void
192 __notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk))
194 struct execute_cb *cb, *cn;
196 if (llist_empty(&rq->execute_cb))
199 llist_for_each_entry_safe(cb, cn,
200 llist_del_all(&rq->execute_cb),
205 static void __notify_execute_cb_irq(struct i915_request *rq)
207 __notify_execute_cb(rq, irq_work_queue);
210 static bool irq_work_imm(struct irq_work *wrk)
216 void i915_request_notify_execute_cb_imm(struct i915_request *rq)
218 __notify_execute_cb(rq, irq_work_imm);
221 static void __i915_request_fill(struct i915_request *rq, u8 val)
223 void *vaddr = rq->ring->vaddr;
227 if (rq->postfix < head) {
228 memset(vaddr + head, val, rq->ring->size - head);
231 memset(vaddr + head, val, rq->postfix - head);
235 * i915_request_active_engine
236 * @rq: request to inspect
237 * @active: pointer in which to return the active engine
239 * Fills the currently active engine to the @active pointer if the request
240 * is active and still not completed.
242 * Returns true if request was active or false otherwise.
245 i915_request_active_engine(struct i915_request *rq,
246 struct intel_engine_cs **active)
248 struct intel_engine_cs *engine, *locked;
252 * Serialise with __i915_request_submit() so that it sees
253 * is-banned?, or we know the request is already inflight.
255 * Note that rq->engine is unstable, and so we double
256 * check that we have acquired the lock on the final engine.
258 locked = READ_ONCE(rq->engine);
259 spin_lock_irq(&locked->sched_engine->lock);
260 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
261 spin_unlock(&locked->sched_engine->lock);
263 spin_lock(&locked->sched_engine->lock);
266 if (i915_request_is_active(rq)) {
267 if (!__i915_request_is_complete(rq))
272 spin_unlock_irq(&locked->sched_engine->lock);
277 static void __rq_init_watchdog(struct i915_request *rq)
279 rq->watchdog.timer.function = NULL;
282 static enum hrtimer_restart __rq_watchdog_expired(struct hrtimer *hrtimer)
284 struct i915_request *rq =
285 container_of(hrtimer, struct i915_request, watchdog.timer);
286 struct intel_gt *gt = rq->engine->gt;
288 if (!i915_request_completed(rq)) {
289 if (llist_add(&rq->watchdog.link, >->watchdog.list))
290 queue_work(gt->i915->unordered_wq, >->watchdog.work);
292 i915_request_put(rq);
295 return HRTIMER_NORESTART;
298 static void __rq_arm_watchdog(struct i915_request *rq)
300 struct i915_request_watchdog *wdg = &rq->watchdog;
301 struct intel_context *ce = rq->context;
303 if (!ce->watchdog.timeout_us)
306 i915_request_get(rq);
308 hrtimer_init(&wdg->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
309 wdg->timer.function = __rq_watchdog_expired;
310 hrtimer_start_range_ns(&wdg->timer,
311 ns_to_ktime(ce->watchdog.timeout_us *
317 static void __rq_cancel_watchdog(struct i915_request *rq)
319 struct i915_request_watchdog *wdg = &rq->watchdog;
321 if (wdg->timer.function && hrtimer_try_to_cancel(&wdg->timer) > 0)
322 i915_request_put(rq);
325 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
328 * i915_request_free_capture_list - Free a capture list
329 * @capture: Pointer to the first list item or NULL
332 void i915_request_free_capture_list(struct i915_capture_list *capture)
335 struct i915_capture_list *next = capture->next;
337 i915_vma_resource_put(capture->vma_res);
343 #define assert_capture_list_is_null(_rq) GEM_BUG_ON((_rq)->capture_list)
345 #define clear_capture_list(_rq) ((_rq)->capture_list = NULL)
349 #define i915_request_free_capture_list(_a) do {} while (0)
351 #define assert_capture_list_is_null(_a) do {} while (0)
353 #define clear_capture_list(_rq) do {} while (0)
357 bool i915_request_retire(struct i915_request *rq)
359 if (!__i915_request_is_complete(rq))
364 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
365 trace_i915_request_retire(rq);
366 i915_request_mark_complete(rq);
368 __rq_cancel_watchdog(rq);
371 * We know the GPU must have read the request to have
372 * sent us the seqno + interrupt, so use the position
373 * of tail of the request to update the last known position
376 * Note this requires that we are always called in request
379 GEM_BUG_ON(!list_is_first(&rq->link,
380 &i915_request_timeline(rq)->requests));
381 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
382 /* Poison before we release our space in the ring */
383 __i915_request_fill(rq, POISON_FREE);
384 rq->ring->head = rq->postfix;
386 if (!i915_request_signaled(rq)) {
387 spin_lock_irq(&rq->lock);
388 dma_fence_signal_locked(&rq->fence);
389 spin_unlock_irq(&rq->lock);
392 if (test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags))
393 intel_rps_dec_waiters(&rq->engine->gt->rps);
396 * We only loosely track inflight requests across preemption,
397 * and so we may find ourselves attempting to retire a _completed_
398 * request that we have removed from the HW and put back on a run
401 * As we set I915_FENCE_FLAG_ACTIVE on the request, this should be
402 * after removing the breadcrumb and signaling it, so that we do not
403 * inadvertently attach the breadcrumb to a completed request.
405 rq->engine->remove_active_request(rq);
406 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
408 __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
410 intel_context_exit(rq->context);
411 intel_context_unpin(rq->context);
413 i915_sched_node_fini(&rq->sched);
414 i915_request_put(rq);
419 void i915_request_retire_upto(struct i915_request *rq)
421 struct intel_timeline * const tl = i915_request_timeline(rq);
422 struct i915_request *tmp;
425 GEM_BUG_ON(!__i915_request_is_complete(rq));
428 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
429 GEM_BUG_ON(!i915_request_completed(tmp));
430 } while (i915_request_retire(tmp) && tmp != rq);
433 static struct i915_request * const *
434 __engine_active(struct intel_engine_cs *engine)
436 return READ_ONCE(engine->execlists.active);
439 static bool __request_in_flight(const struct i915_request *signal)
441 struct i915_request * const *port, *rq;
442 bool inflight = false;
444 if (!i915_request_is_ready(signal))
448 * Even if we have unwound the request, it may still be on
449 * the GPU (preempt-to-busy). If that request is inside an
450 * unpreemptible critical section, it will not be removed. Some
451 * GPU functions may even be stuck waiting for the paired request
452 * (__await_execution) to be submitted and cannot be preempted
453 * until the bond is executing.
455 * As we know that there are always preemption points between
456 * requests, we know that only the currently executing request
457 * may be still active even though we have cleared the flag.
458 * However, we can't rely on our tracking of ELSP[0] to know
459 * which request is currently active and so maybe stuck, as
460 * the tracking maybe an event behind. Instead assume that
461 * if the context is still inflight, then it is still active
462 * even if the active flag has been cleared.
464 * To further complicate matters, if there a pending promotion, the HW
465 * may either perform a context switch to the second inflight execlists,
466 * or it may switch to the pending set of execlists. In the case of the
467 * latter, it may send the ACK and we process the event copying the
468 * pending[] over top of inflight[], _overwriting_ our *active. Since
469 * this implies the HW is arbitrating and not struck in *active, we do
470 * not worry about complete accuracy, but we do require no read/write
471 * tearing of the pointer [the read of the pointer must be valid, even
472 * as the array is being overwritten, for which we require the writes
475 * Note that the read of *execlists->active may race with the promotion
476 * of execlists->pending[] to execlists->inflight[], overwritting
477 * the value at *execlists->active. This is fine. The promotion implies
478 * that we received an ACK from the HW, and so the context is not
479 * stuck -- if we do not see ourselves in *active, the inflight status
480 * is valid. If instead we see ourselves being copied into *active,
481 * we are inflight and may signal the callback.
483 if (!intel_context_inflight(signal->context))
487 for (port = __engine_active(signal->engine);
488 (rq = READ_ONCE(*port)); /* may race with promotion of pending[] */
490 if (rq->context == signal->context) {
491 inflight = i915_seqno_passed(rq->fence.seqno,
492 signal->fence.seqno);
502 __await_execution(struct i915_request *rq,
503 struct i915_request *signal,
506 struct execute_cb *cb;
508 if (i915_request_is_active(signal))
511 cb = kmem_cache_alloc(slab_execute_cbs, gfp);
515 cb->fence = &rq->submit;
516 i915_sw_fence_await(cb->fence);
517 init_irq_work(&cb->work, irq_execute_cb);
520 * Register the callback first, then see if the signaler is already
521 * active. This ensures that if we race with the
522 * __notify_execute_cb from i915_request_submit() and we are not
523 * included in that list, we get a second bite of the cherry and
524 * execute it ourselves. After this point, a future
525 * i915_request_submit() will notify us.
527 * In i915_request_retire() we set the ACTIVE bit on a completed
528 * request (then flush the execute_cb). So by registering the
529 * callback first, then checking the ACTIVE bit, we serialise with
530 * the completed/retired request.
532 if (llist_add(&cb->work.node.llist, &signal->execute_cb)) {
533 if (i915_request_is_active(signal) ||
534 __request_in_flight(signal))
535 i915_request_notify_execute_cb_imm(signal);
541 static bool fatal_error(int error)
544 case 0: /* not an error! */
545 case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
546 case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
553 void __i915_request_skip(struct i915_request *rq)
555 GEM_BUG_ON(!fatal_error(rq->fence.error));
557 if (rq->infix == rq->postfix)
560 RQ_TRACE(rq, "error: %d\n", rq->fence.error);
563 * As this request likely depends on state from the lost
564 * context, clear out all the user operations leaving the
565 * breadcrumb at the end (so we get the fence notifications).
567 __i915_request_fill(rq, 0);
568 rq->infix = rq->postfix;
571 bool i915_request_set_error_once(struct i915_request *rq, int error)
575 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
577 if (i915_request_signaled(rq))
580 old = READ_ONCE(rq->fence.error);
582 if (fatal_error(old))
584 } while (!try_cmpxchg(&rq->fence.error, &old, error));
589 struct i915_request *i915_request_mark_eio(struct i915_request *rq)
591 if (__i915_request_is_complete(rq))
594 GEM_BUG_ON(i915_request_signaled(rq));
596 /* As soon as the request is completed, it may be retired */
597 rq = i915_request_get(rq);
599 i915_request_set_error_once(rq, -EIO);
600 i915_request_mark_complete(rq);
605 bool __i915_request_submit(struct i915_request *request)
607 struct intel_engine_cs *engine = request->engine;
610 RQ_TRACE(request, "\n");
612 lockdep_assert_held(&engine->sched_engine->lock);
615 * With the advent of preempt-to-busy, we frequently encounter
616 * requests that we have unsubmitted from HW, but left running
617 * until the next ack and so have completed in the meantime. On
618 * resubmission of that completed request, we can skip
619 * updating the payload, and execlists can even skip submitting
622 * We must remove the request from the caller's priority queue,
623 * and the caller must only call us when the request is in their
624 * priority queue, under the sched_engine->lock. This ensures that the
625 * request has *not* yet been retired and we can safely move
626 * the request into the engine->active.list where it will be
627 * dropped upon retiring. (Otherwise if resubmit a *retired*
628 * request, this would be a horrible use-after-free.)
630 if (__i915_request_is_complete(request)) {
631 list_del_init(&request->sched.link);
635 if (unlikely(!intel_context_is_schedulable(request->context)))
636 i915_request_set_error_once(request, -EIO);
638 if (unlikely(fatal_error(request->fence.error)))
639 __i915_request_skip(request);
642 * Are we using semaphores when the gpu is already saturated?
644 * Using semaphores incurs a cost in having the GPU poll a
645 * memory location, busywaiting for it to change. The continual
646 * memory reads can have a noticeable impact on the rest of the
647 * system with the extra bus traffic, stalling the cpu as it too
648 * tries to access memory across the bus (perf stat -e bus-cycles).
650 * If we installed a semaphore on this request and we only submit
651 * the request after the signaler completed, that indicates the
652 * system is overloaded and using semaphores at this time only
653 * increases the amount of work we are doing. If so, we disable
654 * further use of semaphores until we are idle again, whence we
655 * optimistically try again.
657 if (request->sched.semaphores &&
658 i915_sw_fence_signaled(&request->semaphore))
659 engine->saturated |= request->sched.semaphores;
661 engine->emit_fini_breadcrumb(request,
662 request->ring->vaddr + request->postfix);
664 trace_i915_request_execute(request);
665 if (engine->bump_serial)
666 engine->bump_serial(engine);
672 GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
673 engine->add_active_request(request);
675 clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
676 set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
679 * XXX Rollback bonded-execution on __i915_request_unsubmit()?
681 * In the future, perhaps when we have an active time-slicing scheduler,
682 * it will be interesting to unsubmit parallel execution and remove
683 * busywaits from the GPU until their master is restarted. This is
684 * quite hairy, we have to carefully rollback the fence and do a
685 * preempt-to-idle cycle on the target engine, all the while the
686 * master execute_cb may refire.
688 __notify_execute_cb_irq(request);
690 /* We may be recursing from the signal callback of another i915 fence */
691 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
692 i915_request_enable_breadcrumb(request);
697 void i915_request_submit(struct i915_request *request)
699 struct intel_engine_cs *engine = request->engine;
702 /* Will be called from irq-context when using foreign fences. */
703 spin_lock_irqsave(&engine->sched_engine->lock, flags);
705 __i915_request_submit(request);
707 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
710 void __i915_request_unsubmit(struct i915_request *request)
712 struct intel_engine_cs *engine = request->engine;
715 * Only unwind in reverse order, required so that the per-context list
716 * is kept in seqno/ring order.
718 RQ_TRACE(request, "\n");
720 lockdep_assert_held(&engine->sched_engine->lock);
723 * Before we remove this breadcrumb from the signal list, we have
724 * to ensure that a concurrent dma_fence_enable_signaling() does not
725 * attach itself. We first mark the request as no longer active and
726 * make sure that is visible to other cores, and then remove the
727 * breadcrumb if attached.
729 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
730 clear_bit_unlock(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
731 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
732 i915_request_cancel_breadcrumb(request);
734 /* We've already spun, don't charge on resubmitting. */
735 if (request->sched.semaphores && __i915_request_has_started(request))
736 request->sched.semaphores = 0;
739 * We don't need to wake_up any waiters on request->execute, they
740 * will get woken by any other event or us re-adding this request
741 * to the engine timeline (__i915_request_submit()). The waiters
742 * should be quite adapt at finding that the request now has a new
743 * global_seqno to the one they went to sleep on.
747 void i915_request_unsubmit(struct i915_request *request)
749 struct intel_engine_cs *engine = request->engine;
752 /* Will be called from irq-context when using foreign fences. */
753 spin_lock_irqsave(&engine->sched_engine->lock, flags);
755 __i915_request_unsubmit(request);
757 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
760 void i915_request_cancel(struct i915_request *rq, int error)
762 if (!i915_request_set_error_once(rq, error))
765 set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags);
767 intel_context_cancel_request(rq->context, rq);
771 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
773 struct i915_request *request =
774 container_of(fence, typeof(*request), submit);
778 trace_i915_request_submit(request);
780 if (unlikely(fence->error))
781 i915_request_set_error_once(request, fence->error);
783 __rq_arm_watchdog(request);
786 * We need to serialize use of the submit_request() callback
787 * with its hotplugging performed during an emergency
788 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
789 * critical section in order to force i915_gem_set_wedged() to
790 * wait until the submit_request() is completed before
794 request->engine->submit_request(request);
799 i915_request_put(request);
807 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
809 struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
816 i915_request_put(rq);
823 static void retire_requests(struct intel_timeline *tl)
825 struct i915_request *rq, *rn;
827 list_for_each_entry_safe(rq, rn, &tl->requests, link)
828 if (!i915_request_retire(rq))
832 static noinline struct i915_request *
833 request_alloc_slow(struct intel_timeline *tl,
834 struct i915_request **rsvd,
837 struct i915_request *rq;
839 /* If we cannot wait, dip into our reserves */
840 if (!gfpflags_allow_blocking(gfp)) {
841 rq = xchg(rsvd, NULL);
842 if (!rq) /* Use the normal failure path for one final WARN */
848 if (list_empty(&tl->requests))
851 /* Move our oldest request to the slab-cache (if not in use!) */
852 rq = list_first_entry(&tl->requests, typeof(*rq), link);
853 i915_request_retire(rq);
855 rq = kmem_cache_alloc(slab_requests,
856 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
860 /* Ratelimit ourselves to prevent oom from malicious clients */
861 rq = list_last_entry(&tl->requests, typeof(*rq), link);
862 cond_synchronize_rcu(rq->rcustate);
864 /* Retire our old requests in the hope that we free some */
868 return kmem_cache_alloc(slab_requests, gfp);
871 static void __i915_request_ctor(void *arg)
873 struct i915_request *rq = arg;
875 spin_lock_init(&rq->lock);
876 i915_sched_node_init(&rq->sched);
877 i915_sw_fence_init(&rq->submit, submit_notify);
878 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
880 clear_capture_list(rq);
881 rq->batch_res = NULL;
883 init_llist_head(&rq->execute_cb);
886 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
887 #define clear_batch_ptr(_rq) ((_rq)->batch = NULL)
889 #define clear_batch_ptr(_a) do {} while (0)
892 struct i915_request *
893 __i915_request_create(struct intel_context *ce, gfp_t gfp)
895 struct intel_timeline *tl = ce->timeline;
896 struct i915_request *rq;
902 /* Check that the caller provided an already pinned context */
903 __intel_context_pin(ce);
906 * Beware: Dragons be flying overhead.
908 * We use RCU to look up requests in flight. The lookups may
909 * race with the request being allocated from the slab freelist.
910 * That is the request we are writing to here, may be in the process
911 * of being read by __i915_active_request_get_rcu(). As such,
912 * we have to be very careful when overwriting the contents. During
913 * the RCU lookup, we change chase the request->engine pointer,
914 * read the request->global_seqno and increment the reference count.
916 * The reference count is incremented atomically. If it is zero,
917 * the lookup knows the request is unallocated and complete. Otherwise,
918 * it is either still in use, or has been reallocated and reset
919 * with dma_fence_init(). This increment is safe for release as we
920 * check that the request we have a reference to and matches the active
923 * Before we increment the refcount, we chase the request->engine
924 * pointer. We must not call kmem_cache_zalloc() or else we set
925 * that pointer to NULL and cause a crash during the lookup. If
926 * we see the request is completed (based on the value of the
927 * old engine and seqno), the lookup is complete and reports NULL.
928 * If we decide the request is not completed (new engine or seqno),
929 * then we grab a reference and double check that it is still the
930 * active request - which it won't be and restart the lookup.
932 * Do not use kmem_cache_zalloc() here!
934 rq = kmem_cache_alloc(slab_requests,
935 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
937 rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp);
945 rq->engine = ce->engine;
947 rq->execution_mask = ce->engine->mask;
948 rq->i915 = ce->engine->i915;
950 ret = intel_timeline_get_seqno(tl, rq, &seqno);
954 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
955 tl->fence_context, seqno);
957 RCU_INIT_POINTER(rq->timeline, tl);
958 rq->hwsp_seqno = tl->hwsp_seqno;
959 GEM_BUG_ON(__i915_request_is_complete(rq));
961 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
963 rq->guc_prio = GUC_PRIO_INIT;
965 /* We bump the ref for the fence chain */
966 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
967 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
969 i915_sched_node_reinit(&rq->sched);
971 /* No zalloc, everything must be cleared after use */
973 __rq_init_watchdog(rq);
974 assert_capture_list_is_null(rq);
975 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
976 GEM_BUG_ON(rq->batch_res);
979 * Reserve space in the ring buffer for all the commands required to
980 * eventually emit this request. This is to guarantee that the
981 * i915_request_add() call can't fail. Note that the reserve may need
982 * to be redone if the request is not actually submitted straight
983 * away, e.g. because a GPU scheduler has deferred it.
985 * Note that due to how we add reserved_space to intel_ring_begin()
986 * we need to double our request to ensure that if we need to wrap
987 * around inside i915_request_add() there is sufficient space at
988 * the beginning of the ring as well.
991 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
994 * Record the position of the start of the request so that
995 * should we detect the updated seqno part-way through the
996 * GPU processing the request, we never over-estimate the
997 * position of the head.
999 rq->head = rq->ring->emit;
1001 ret = rq->engine->request_alloc(rq);
1005 rq->infix = rq->ring->emit; /* end of header; start of user payload */
1007 intel_context_mark_active(ce);
1008 list_add_tail_rcu(&rq->link, &tl->requests);
1013 ce->ring->emit = rq->head;
1015 /* Make sure we didn't add ourselves to external state before freeing */
1016 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
1017 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
1020 kmem_cache_free(slab_requests, rq);
1022 intel_context_unpin(ce);
1023 return ERR_PTR(ret);
1026 struct i915_request *
1027 i915_request_create(struct intel_context *ce)
1029 struct i915_request *rq;
1030 struct intel_timeline *tl;
1032 tl = intel_context_timeline_lock(ce);
1034 return ERR_CAST(tl);
1036 /* Move our oldest request to the slab-cache (if not in use!) */
1037 rq = list_first_entry(&tl->requests, typeof(*rq), link);
1038 if (!list_is_last(&rq->link, &tl->requests))
1039 i915_request_retire(rq);
1041 intel_context_enter(ce);
1042 rq = __i915_request_create(ce, GFP_KERNEL);
1043 intel_context_exit(ce); /* active reference transferred to request */
1047 /* Check that we do not interrupt ourselves with a new request */
1048 rq->cookie = lockdep_pin_lock(&tl->mutex);
1053 intel_context_timeline_unlock(tl);
1058 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
1060 struct dma_fence *fence;
1063 if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
1066 if (i915_request_started(signal))
1070 * The caller holds a reference on @signal, but we do not serialise
1071 * against it being retired and removed from the lists.
1073 * We do not hold a reference to the request before @signal, and
1074 * so must be very careful to ensure that it is not _recycled_ as
1075 * we follow the link backwards.
1080 struct list_head *pos = READ_ONCE(signal->link.prev);
1081 struct i915_request *prev;
1083 /* Confirm signal has not been retired, the link is valid */
1084 if (unlikely(__i915_request_has_started(signal)))
1087 /* Is signal the earliest request on its timeline? */
1088 if (pos == &rcu_dereference(signal->timeline)->requests)
1092 * Peek at the request before us in the timeline. That
1093 * request will only be valid before it is retired, so
1094 * after acquiring a reference to it, confirm that it is
1095 * still part of the signaler's timeline.
1097 prev = list_entry(pos, typeof(*prev), link);
1098 if (!i915_request_get_rcu(prev))
1101 /* After the strong barrier, confirm prev is still attached */
1102 if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
1103 i915_request_put(prev);
1107 fence = &prev->fence;
1114 if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
1115 err = i915_sw_fence_await_dma_fence(&rq->submit,
1118 dma_fence_put(fence);
1123 static intel_engine_mask_t
1124 already_busywaiting(struct i915_request *rq)
1127 * Polling a semaphore causes bus traffic, delaying other users of
1128 * both the GPU and CPU. We want to limit the impact on others,
1129 * while taking advantage of early submission to reduce GPU
1130 * latency. Therefore we restrict ourselves to not using more
1131 * than one semaphore from each source, and not using a semaphore
1132 * if we have detected the engine is saturated (i.e. would not be
1133 * submitted early and cause bus traffic reading an already passed
1136 * See the are-we-too-late? check in __i915_request_submit().
1138 return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
1142 __emit_semaphore_wait(struct i915_request *to,
1143 struct i915_request *from,
1146 const int has_token = GRAPHICS_VER(to->engine->i915) >= 12;
1151 GEM_BUG_ON(GRAPHICS_VER(to->engine->i915) < 8);
1152 GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
1154 /* We need to pin the signaler's HWSP until we are finished reading. */
1155 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
1163 cs = intel_ring_begin(to, len);
1168 * Using greater-than-or-equal here means we have to worry
1169 * about seqno wraparound. To side step that issue, we swap
1170 * the timeline HWSP upon wrapping, so that everyone listening
1171 * for the old (pre-wrap) values do not see the much smaller
1172 * (post-wrap) values than they were expecting (and so wait
1175 *cs++ = (MI_SEMAPHORE_WAIT |
1176 MI_SEMAPHORE_GLOBAL_GTT |
1178 MI_SEMAPHORE_SAD_GTE_SDD) +
1181 *cs++ = hwsp_offset;
1188 intel_ring_advance(to, cs);
1193 can_use_semaphore_wait(struct i915_request *to, struct i915_request *from)
1195 return to->engine->gt->ggtt == from->engine->gt->ggtt;
1199 emit_semaphore_wait(struct i915_request *to,
1200 struct i915_request *from,
1203 const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
1204 struct i915_sw_fence *wait = &to->submit;
1206 if (!can_use_semaphore_wait(to, from))
1209 if (!intel_context_use_semaphores(to->context))
1212 if (i915_request_has_initial_breadcrumb(to))
1216 * If this or its dependents are waiting on an external fence
1217 * that may fail catastrophically, then we want to avoid using
1218 * semaphores as they bypass the fence signaling metadata, and we
1219 * lose the fence->error propagation.
1221 if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN)
1224 /* Just emit the first semaphore we see as request space is limited. */
1225 if (already_busywaiting(to) & mask)
1228 if (i915_request_await_start(to, from) < 0)
1231 /* Only submit our spinner after the signaler is running! */
1232 if (__await_execution(to, from, gfp))
1235 if (__emit_semaphore_wait(to, from, from->fence.seqno))
1238 to->sched.semaphores |= mask;
1239 wait = &to->semaphore;
1242 return i915_sw_fence_await_dma_fence(wait,
1247 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1248 struct dma_fence *fence)
1250 return __intel_timeline_sync_is_later(tl,
1255 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1256 const struct dma_fence *fence)
1258 return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1262 __i915_request_await_execution(struct i915_request *to,
1263 struct i915_request *from)
1267 GEM_BUG_ON(intel_context_is_barrier(from->context));
1269 /* Submit both requests at the same time */
1270 err = __await_execution(to, from, I915_FENCE_GFP);
1274 /* Squash repeated depenendices to the same timelines */
1275 if (intel_timeline_sync_has_start(i915_request_timeline(to),
1280 * Wait until the start of this request.
1282 * The execution cb fires when we submit the request to HW. But in
1283 * many cases this may be long before the request itself is ready to
1284 * run (consider that we submit 2 requests for the same context, where
1285 * the request of interest is behind an indefinite spinner). So we hook
1286 * up to both to reduce our queues and keep the execution lag minimised
1287 * in the worst case, though we hope that the await_start is elided.
1289 err = i915_request_await_start(to, from);
1294 * Ensure both start together [after all semaphores in signal]
1296 * Now that we are queued to the HW at roughly the same time (thanks
1297 * to the execute cb) and are ready to run at roughly the same time
1298 * (thanks to the await start), our signaler may still be indefinitely
1299 * delayed by waiting on a semaphore from a remote engine. If our
1300 * signaler depends on a semaphore, so indirectly do we, and we do not
1301 * want to start our payload until our signaler also starts theirs.
1304 * However, there is also a second condition for which we need to wait
1305 * for the precise start of the signaler. Consider that the signaler
1306 * was submitted in a chain of requests following another context
1307 * (with just an ordinary intra-engine fence dependency between the
1308 * two). In this case the signaler is queued to HW, but not for
1309 * immediate execution, and so we must wait until it reaches the
1312 if (can_use_semaphore_wait(to, from) &&
1313 intel_engine_has_semaphores(to->engine) &&
1314 !i915_request_has_initial_breadcrumb(to)) {
1315 err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1320 /* Couple the dependency tree for PI on this exposed to->fence */
1321 if (to->engine->sched_engine->schedule) {
1322 err = i915_sched_node_add_dependency(&to->sched,
1324 I915_DEPENDENCY_WEAK);
1329 return intel_timeline_sync_set_start(i915_request_timeline(to),
1333 static void mark_external(struct i915_request *rq)
1336 * The downside of using semaphores is that we lose metadata passing
1337 * along the signaling chain. This is particularly nasty when we
1338 * need to pass along a fatal error such as EFAULT or EDEADLK. For
1339 * fatal errors we want to scrub the request before it is executed,
1340 * which means that we cannot preload the request onto HW and have
1341 * it wait upon a semaphore.
1343 rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN;
1347 __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1350 return i915_sw_fence_await_dma_fence(&rq->submit, fence,
1351 i915_fence_context_timeout(rq->i915,
1357 i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1359 struct dma_fence *iter;
1362 if (!to_dma_fence_chain(fence))
1363 return __i915_request_await_external(rq, fence);
1365 dma_fence_chain_for_each(iter, fence) {
1366 struct dma_fence_chain *chain = to_dma_fence_chain(iter);
1368 if (!dma_fence_is_i915(chain->fence)) {
1369 err = __i915_request_await_external(rq, iter);
1373 err = i915_request_await_dma_fence(rq, chain->fence);
1378 dma_fence_put(iter);
1382 static inline bool is_parallel_rq(struct i915_request *rq)
1384 return intel_context_is_parallel(rq->context);
1387 static inline struct intel_context *request_to_parent(struct i915_request *rq)
1389 return intel_context_to_parent(rq->context);
1392 static bool is_same_parallel_context(struct i915_request *to,
1393 struct i915_request *from)
1395 if (is_parallel_rq(to))
1396 return request_to_parent(to) == request_to_parent(from);
1402 i915_request_await_execution(struct i915_request *rq,
1403 struct dma_fence *fence)
1405 struct dma_fence **child = &fence;
1406 unsigned int nchild = 1;
1409 if (dma_fence_is_array(fence)) {
1410 struct dma_fence_array *array = to_dma_fence_array(fence);
1412 /* XXX Error for signal-on-any fence arrays */
1414 child = array->fences;
1415 nchild = array->num_fences;
1416 GEM_BUG_ON(!nchild);
1421 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1424 if (fence->context == rq->fence.context)
1428 * We don't squash repeated fence dependencies here as we
1429 * want to run our callback in all cases.
1432 if (dma_fence_is_i915(fence)) {
1433 if (is_same_parallel_context(rq, to_request(fence)))
1435 ret = __i915_request_await_execution(rq,
1438 ret = i915_request_await_external(rq, fence);
1448 await_request_submit(struct i915_request *to, struct i915_request *from)
1451 * If we are waiting on a virtual engine, then it may be
1452 * constrained to execute on a single engine *prior* to submission.
1453 * When it is submitted, it will be first submitted to the virtual
1454 * engine and then passed to the physical engine. We cannot allow
1455 * the waiter to be submitted immediately to the physical engine
1456 * as it may then bypass the virtual request.
1458 if (to->engine == READ_ONCE(from->engine))
1459 return i915_sw_fence_await_sw_fence_gfp(&to->submit,
1463 return __i915_request_await_execution(to, from);
1467 i915_request_await_request(struct i915_request *to, struct i915_request *from)
1471 GEM_BUG_ON(to == from);
1472 GEM_BUG_ON(to->timeline == from->timeline);
1474 if (i915_request_completed(from)) {
1475 i915_sw_fence_set_error_once(&to->submit, from->fence.error);
1479 if (to->engine->sched_engine->schedule) {
1480 ret = i915_sched_node_add_dependency(&to->sched,
1482 I915_DEPENDENCY_EXTERNAL);
1487 if (!intel_engine_uses_guc(to->engine) &&
1488 is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask)))
1489 ret = await_request_submit(to, from);
1491 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1499 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1501 struct dma_fence **child = &fence;
1502 unsigned int nchild = 1;
1506 * Note that if the fence-array was created in signal-on-any mode,
1507 * we should *not* decompose it into its individual fences. However,
1508 * we don't currently store which mode the fence-array is operating
1509 * in. Fortunately, the only user of signal-on-any is private to
1510 * amdgpu and we should not see any incoming fence-array from
1511 * sync-file being in signal-on-any mode.
1513 if (dma_fence_is_array(fence)) {
1514 struct dma_fence_array *array = to_dma_fence_array(fence);
1516 child = array->fences;
1517 nchild = array->num_fences;
1518 GEM_BUG_ON(!nchild);
1523 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1527 * Requests on the same timeline are explicitly ordered, along
1528 * with their dependencies, by i915_request_add() which ensures
1529 * that requests are submitted in-order through each ring.
1531 if (fence->context == rq->fence.context)
1534 /* Squash repeated waits to the same timelines */
1535 if (fence->context &&
1536 intel_timeline_sync_is_later(i915_request_timeline(rq),
1540 if (dma_fence_is_i915(fence)) {
1541 if (is_same_parallel_context(rq, to_request(fence)))
1543 ret = i915_request_await_request(rq, to_request(fence));
1545 ret = i915_request_await_external(rq, fence);
1550 /* Record the latest fence used against each timeline */
1552 intel_timeline_sync_set(i915_request_timeline(rq),
1560 * i915_request_await_deps - set this request to (async) wait upon a struct
1561 * i915_deps dma_fence collection
1562 * @rq: request we are wishing to use
1563 * @deps: The struct i915_deps containing the dependencies.
1565 * Returns 0 if successful, negative error code on error.
1567 int i915_request_await_deps(struct i915_request *rq, const struct i915_deps *deps)
1571 for (i = 0; i < deps->num_deps; ++i) {
1572 err = i915_request_await_dma_fence(rq, deps->fences[i]);
1581 * i915_request_await_object - set this request to (async) wait upon a bo
1582 * @to: request we are wishing to use
1583 * @obj: object which may be in use on another ring.
1584 * @write: whether the wait is on behalf of a writer
1586 * This code is meant to abstract object synchronization with the GPU.
1587 * Conceptually we serialise writes between engines inside the GPU.
1588 * We only allow one engine to write into a buffer at any time, but
1589 * multiple readers. To ensure each has a coherent view of memory, we must:
1591 * - If there is an outstanding write request to the object, the new
1592 * request must wait for it to complete (either CPU or in hw, requests
1593 * on the same ring will be naturally ordered).
1595 * - If we are a write request (pending_write_domain is set), the new
1596 * request must wait for outstanding read requests to complete.
1598 * Returns 0 if successful, else propagates up the lower layer error.
1601 i915_request_await_object(struct i915_request *to,
1602 struct drm_i915_gem_object *obj,
1605 struct dma_resv_iter cursor;
1606 struct dma_fence *fence;
1609 dma_resv_for_each_fence(&cursor, obj->base.resv,
1610 dma_resv_usage_rw(write), fence) {
1611 ret = i915_request_await_dma_fence(to, fence);
1619 static void i915_request_await_huc(struct i915_request *rq)
1621 struct intel_huc *huc = &rq->context->engine->gt->uc.huc;
1623 /* don't stall kernel submissions! */
1624 if (!rcu_access_pointer(rq->context->gem_context))
1627 if (intel_huc_wait_required(huc))
1628 i915_sw_fence_await_sw_fence(&rq->submit,
1629 &huc->delayed_load.fence,
1633 static struct i915_request *
1634 __i915_request_ensure_parallel_ordering(struct i915_request *rq,
1635 struct intel_timeline *timeline)
1637 struct i915_request *prev;
1639 GEM_BUG_ON(!is_parallel_rq(rq));
1641 prev = request_to_parent(rq)->parallel.last_rq;
1643 if (!__i915_request_is_complete(prev)) {
1644 i915_sw_fence_await_sw_fence(&rq->submit,
1648 if (rq->engine->sched_engine->schedule)
1649 __i915_sched_node_add_dependency(&rq->sched,
1654 i915_request_put(prev);
1657 request_to_parent(rq)->parallel.last_rq = i915_request_get(rq);
1660 * Users have to put a reference potentially got by
1661 * __i915_active_fence_set() to the returned request
1662 * when no longer needed
1664 return to_request(__i915_active_fence_set(&timeline->last_request,
1668 static struct i915_request *
1669 __i915_request_ensure_ordering(struct i915_request *rq,
1670 struct intel_timeline *timeline)
1672 struct i915_request *prev;
1674 GEM_BUG_ON(is_parallel_rq(rq));
1676 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1679 if (prev && !__i915_request_is_complete(prev)) {
1680 bool uses_guc = intel_engine_uses_guc(rq->engine);
1681 bool pow2 = is_power_of_2(READ_ONCE(prev->engine)->mask |
1683 bool same_context = prev->context == rq->context;
1686 * The requests are supposed to be kept in order. However,
1687 * we need to be wary in case the timeline->last_request
1688 * is used as a barrier for external modification to this
1691 GEM_BUG_ON(same_context &&
1692 i915_seqno_passed(prev->fence.seqno,
1695 if ((same_context && uses_guc) || (!uses_guc && pow2))
1696 i915_sw_fence_await_sw_fence(&rq->submit,
1700 __i915_sw_fence_await_dma_fence(&rq->submit,
1703 if (rq->engine->sched_engine->schedule)
1704 __i915_sched_node_add_dependency(&rq->sched,
1711 * Users have to put the reference to prev potentially got
1712 * by __i915_active_fence_set() when no longer needed
1717 static struct i915_request *
1718 __i915_request_add_to_timeline(struct i915_request *rq)
1720 struct intel_timeline *timeline = i915_request_timeline(rq);
1721 struct i915_request *prev;
1724 * Media workloads may require HuC, so stall them until HuC loading is
1725 * complete. Note that HuC not being loaded when a user submission
1726 * arrives can only happen when HuC is loaded via GSC and in that case
1727 * we still expect the window between us starting to accept submissions
1728 * and HuC loading completion to be small (a few hundred ms).
1730 if (rq->engine->class == VIDEO_DECODE_CLASS)
1731 i915_request_await_huc(rq);
1734 * Dependency tracking and request ordering along the timeline
1735 * is special cased so that we can eliminate redundant ordering
1736 * operations while building the request (we know that the timeline
1737 * itself is ordered, and here we guarantee it).
1739 * As we know we will need to emit tracking along the timeline,
1740 * we embed the hooks into our request struct -- at the cost of
1741 * having to have specialised no-allocation interfaces (which will
1742 * be beneficial elsewhere).
1744 * A second benefit to open-coding i915_request_await_request is
1745 * that we can apply a slight variant of the rules specialised
1746 * for timelines that jump between engines (such as virtual engines).
1747 * If we consider the case of virtual engine, we must emit a dma-fence
1748 * to prevent scheduling of the second request until the first is
1749 * complete (to maximise our greedy late load balancing) and this
1750 * precludes optimising to use semaphores serialisation of a single
1751 * timeline across engines.
1753 * We do not order parallel submission requests on the timeline as each
1754 * parallel submission context has its own timeline and the ordering
1755 * rules for parallel requests are that they must be submitted in the
1756 * order received from the execbuf IOCTL. So rather than using the
1757 * timeline we store a pointer to last request submitted in the
1758 * relationship in the gem context and insert a submission fence
1759 * between that request and request passed into this function or
1760 * alternatively we use completion fence if gem context has a single
1761 * timeline and this is the first submission of an execbuf IOCTL.
1763 if (likely(!is_parallel_rq(rq)))
1764 prev = __i915_request_ensure_ordering(rq, timeline);
1766 prev = __i915_request_ensure_parallel_ordering(rq, timeline);
1768 i915_request_put(prev);
1771 * Make sure that no request gazumped us - if it was allocated after
1772 * our i915_request_alloc() and called __i915_request_add() before
1773 * us, the timeline will hold its seqno which is later than ours.
1775 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1781 * NB: This function is not allowed to fail. Doing so would mean the the
1782 * request is not being tracked for completion but the work itself is
1783 * going to happen on the hardware. This would be a Bad Thing(tm).
1785 struct i915_request *__i915_request_commit(struct i915_request *rq)
1787 struct intel_engine_cs *engine = rq->engine;
1788 struct intel_ring *ring = rq->ring;
1794 * To ensure that this call will not fail, space for its emissions
1795 * should already have been reserved in the ring buffer. Let the ring
1796 * know that it is time to use that space up.
1798 GEM_BUG_ON(rq->reserved_space > ring->space);
1799 rq->reserved_space = 0;
1800 rq->emitted_jiffies = jiffies;
1803 * Record the position of the start of the breadcrumb so that
1804 * should we detect the updated seqno part-way through the
1805 * GPU processing the request, we never over-estimate the
1806 * position of the ring's HEAD.
1808 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1809 GEM_BUG_ON(IS_ERR(cs));
1810 rq->postfix = intel_ring_offset(rq, cs);
1812 return __i915_request_add_to_timeline(rq);
1815 void __i915_request_queue_bh(struct i915_request *rq)
1817 i915_sw_fence_commit(&rq->semaphore);
1818 i915_sw_fence_commit(&rq->submit);
1821 void __i915_request_queue(struct i915_request *rq,
1822 const struct i915_sched_attr *attr)
1825 * Let the backend know a new request has arrived that may need
1826 * to adjust the existing execution schedule due to a high priority
1827 * request - i.e. we may want to preempt the current request in order
1828 * to run a high priority dependency chain *before* we can execute this
1831 * This is called before the request is ready to run so that we can
1832 * decide whether to preempt the entire chain so that it is ready to
1833 * run at the earliest possible convenience.
1835 if (attr && rq->engine->sched_engine->schedule)
1836 rq->engine->sched_engine->schedule(rq, attr);
1839 __i915_request_queue_bh(rq);
1840 local_bh_enable(); /* kick tasklets */
1843 void i915_request_add(struct i915_request *rq)
1845 struct intel_timeline * const tl = i915_request_timeline(rq);
1846 struct i915_sched_attr attr = {};
1847 struct i915_gem_context *ctx;
1849 lockdep_assert_held(&tl->mutex);
1850 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1852 trace_i915_request_add(rq);
1853 __i915_request_commit(rq);
1855 /* XXX placeholder for selftests */
1857 ctx = rcu_dereference(rq->context->gem_context);
1862 __i915_request_queue(rq, &attr);
1864 mutex_unlock(&tl->mutex);
1867 static unsigned long local_clock_ns(unsigned int *cpu)
1872 * Cheaply and approximately convert from nanoseconds to microseconds.
1873 * The result and subsequent calculations are also defined in the same
1874 * approximate microseconds units. The principal source of timing
1875 * error here is from the simple truncation.
1877 * Note that local_clock() is only defined wrt to the current CPU;
1878 * the comparisons are no longer valid if we switch CPUs. Instead of
1879 * blocking preemption for the entire busywait, we can detect the CPU
1880 * switch and use that as indicator of system load and a reason to
1881 * stop busywaiting, see busywait_stop().
1890 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1892 unsigned int this_cpu;
1894 if (time_after(local_clock_ns(&this_cpu), timeout))
1897 return this_cpu != cpu;
1900 static bool __i915_spin_request(struct i915_request * const rq, int state)
1902 unsigned long timeout_ns;
1906 * Only wait for the request if we know it is likely to complete.
1908 * We don't track the timestamps around requests, nor the average
1909 * request length, so we do not have a good indicator that this
1910 * request will complete within the timeout. What we do know is the
1911 * order in which requests are executed by the context and so we can
1912 * tell if the request has been started. If the request is not even
1913 * running yet, it is a fair assumption that it will not complete
1914 * within our relatively short timeout.
1916 if (!i915_request_is_running(rq))
1920 * When waiting for high frequency requests, e.g. during synchronous
1921 * rendering split between the CPU and GPU, the finite amount of time
1922 * required to set up the irq and wait upon it limits the response
1923 * rate. By busywaiting on the request completion for a short while we
1924 * can service the high frequency waits as quick as possible. However,
1925 * if it is a slow request, we want to sleep as quickly as possible.
1926 * The tradeoff between waiting and sleeping is roughly the time it
1927 * takes to sleep on a request, on the order of a microsecond.
1930 timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1931 timeout_ns += local_clock_ns(&cpu);
1933 if (dma_fence_is_signaled(&rq->fence))
1936 if (signal_pending_state(state, current))
1939 if (busywait_stop(timeout_ns, cpu))
1943 } while (!need_resched());
1948 struct request_wait {
1949 struct dma_fence_cb cb;
1950 struct task_struct *tsk;
1953 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1955 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1957 wake_up_process(fetch_and_zero(&wait->tsk));
1961 * i915_request_wait_timeout - wait until execution of request has finished
1962 * @rq: the request to wait upon
1963 * @flags: how to wait
1964 * @timeout: how long to wait in jiffies
1966 * i915_request_wait_timeout() waits for the request to be completed, for a
1967 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1970 * Returns the remaining time (in jiffies) if the request completed, which may
1971 * be zero if the request is unfinished after the timeout expires.
1972 * If the timeout is 0, it will return 1 if the fence is signaled.
1974 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1975 * pending before the request completes.
1977 * NOTE: This function has the same wait semantics as dma-fence.
1979 long i915_request_wait_timeout(struct i915_request *rq,
1983 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1984 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1985 struct request_wait wait;
1988 GEM_BUG_ON(timeout < 0);
1990 if (dma_fence_is_signaled(&rq->fence))
1991 return timeout ?: 1;
1996 trace_i915_request_wait_begin(rq, flags);
1999 * We must never wait on the GPU while holding a lock as we
2000 * may need to perform a GPU reset. So while we don't need to
2001 * serialise wait/reset with an explicit lock, we do want
2002 * lockdep to detect potential dependency cycles.
2004 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
2007 * Optimistic spin before touching IRQs.
2009 * We may use a rather large value here to offset the penalty of
2010 * switching away from the active task. Frequently, the client will
2011 * wait upon an old swapbuffer to throttle itself to remain within a
2012 * frame of the gpu. If the client is running in lockstep with the gpu,
2013 * then it should not be waiting long at all, and a sleep now will incur
2014 * extra scheduler latency in producing the next frame. To try to
2015 * avoid adding the cost of enabling/disabling the interrupt to the
2016 * short wait, we first spin to see if the request would have completed
2017 * in the time taken to setup the interrupt.
2019 * We need upto 5us to enable the irq, and upto 20us to hide the
2020 * scheduler latency of a context switch, ignoring the secondary
2021 * impacts from a context switch such as cache eviction.
2023 * The scheme used for low-latency IO is called "hybrid interrupt
2024 * polling". The suggestion there is to sleep until just before you
2025 * expect to be woken by the device interrupt and then poll for its
2026 * completion. That requires having a good predictor for the request
2027 * duration, which we currently lack.
2029 if (CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT &&
2030 __i915_spin_request(rq, state))
2034 * This client is about to stall waiting for the GPU. In many cases
2035 * this is undesirable and limits the throughput of the system, as
2036 * many clients cannot continue processing user input/output whilst
2037 * blocked. RPS autotuning may take tens of milliseconds to respond
2038 * to the GPU load and thus incurs additional latency for the client.
2039 * We can circumvent that by promoting the GPU frequency to maximum
2040 * before we sleep. This makes the GPU throttle up much more quickly
2041 * (good for benchmarks and user experience, e.g. window animations),
2042 * but at a cost of spending more power processing the workload
2043 * (bad for battery).
2045 if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
2046 intel_rps_boost(rq);
2049 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
2053 * Flush the submission tasklet, but only if it may help this request.
2055 * We sometimes experience some latency between the HW interrupts and
2056 * tasklet execution (mostly due to ksoftirqd latency, but it can also
2057 * be due to lazy CS events), so lets run the tasklet manually if there
2058 * is a chance it may submit this request. If the request is not ready
2059 * to run, as it is waiting for other fences to be signaled, flushing
2060 * the tasklet is busy work without any advantage for this client.
2062 * If the HW is being lazy, this is the last chance before we go to
2063 * sleep to catch any pending events. We will check periodically in
2064 * the heartbeat to flush the submission tasklets as a last resort
2067 if (i915_request_is_ready(rq))
2068 __intel_engine_flush_submission(rq->engine, false);
2071 set_current_state(state);
2073 if (dma_fence_is_signaled(&rq->fence))
2076 if (signal_pending_state(state, current)) {
2077 timeout = -ERESTARTSYS;
2086 timeout = io_schedule_timeout(timeout);
2088 __set_current_state(TASK_RUNNING);
2090 if (READ_ONCE(wait.tsk))
2091 dma_fence_remove_callback(&rq->fence, &wait.cb);
2092 GEM_BUG_ON(!list_empty(&wait.cb.node));
2095 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
2096 trace_i915_request_wait_end(rq);
2101 * i915_request_wait - wait until execution of request has finished
2102 * @rq: the request to wait upon
2103 * @flags: how to wait
2104 * @timeout: how long to wait in jiffies
2106 * i915_request_wait() waits for the request to be completed, for a
2107 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
2110 * Returns the remaining time (in jiffies) if the request completed, which may
2111 * be zero or -ETIME if the request is unfinished after the timeout expires.
2112 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
2113 * pending before the request completes.
2115 * NOTE: This function behaves differently from dma-fence wait semantics for
2116 * timeout = 0. It returns 0 on success, and -ETIME if not signaled.
2118 long i915_request_wait(struct i915_request *rq,
2122 long ret = i915_request_wait_timeout(rq, flags, timeout);
2127 if (ret > 0 && !timeout)
2133 static int print_sched_attr(const struct i915_sched_attr *attr,
2134 char *buf, int x, int len)
2136 if (attr->priority == I915_PRIORITY_INVALID)
2139 x += snprintf(buf + x, len - x,
2140 " prio=%d", attr->priority);
2145 static char queue_status(const struct i915_request *rq)
2147 if (i915_request_is_active(rq))
2150 if (i915_request_is_ready(rq))
2151 return intel_engine_is_virtual(rq->engine) ? 'V' : 'R';
2156 static const char *run_status(const struct i915_request *rq)
2158 if (__i915_request_is_complete(rq))
2161 if (__i915_request_has_started(rq))
2164 if (!i915_sw_fence_signaled(&rq->semaphore))
2170 static const char *fence_status(const struct i915_request *rq)
2172 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
2175 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
2181 void i915_request_show(struct drm_printer *m,
2182 const struct i915_request *rq,
2186 const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence);
2191 * The prefix is used to show the queue status, for which we use
2192 * the following flags:
2195 * - initial status upon being submitted by the user
2197 * - the request is not ready for execution as it is waiting
2198 * for external fences
2201 * - all fences the request was waiting on have been signaled,
2202 * and the request is now ready for execution and will be
2203 * in a backend queue
2205 * - a ready request may still need to wait on semaphores
2209 * - same as ready, but queued over multiple backends
2212 * - the request has been transferred from the backend queue and
2213 * submitted for execution on HW
2215 * - a completed request may still be regarded as executing, its
2216 * status may not be updated until it is retired and removed
2220 x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
2222 drm_printf(m, "%s%.*s%c %llx:%lld%s%s %s @ %dms: %s\n",
2223 prefix, indent, " ",
2225 rq->fence.context, rq->fence.seqno,
2229 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
2233 static bool engine_match_ring(struct intel_engine_cs *engine, struct i915_request *rq)
2235 u32 ring = ENGINE_READ(engine, RING_START);
2237 return ring == i915_ggtt_offset(rq->ring->vma);
2240 static bool match_ring(struct i915_request *rq)
2242 struct intel_engine_cs *engine;
2246 if (!intel_engine_is_virtual(rq->engine))
2247 return engine_match_ring(rq->engine, rq);
2251 while ((engine = intel_engine_get_sibling(rq->engine, i++))) {
2252 found = engine_match_ring(engine, rq);
2260 enum i915_request_state i915_test_request_state(struct i915_request *rq)
2262 if (i915_request_completed(rq))
2263 return I915_REQUEST_COMPLETE;
2265 if (!i915_request_started(rq))
2266 return I915_REQUEST_PENDING;
2269 return I915_REQUEST_ACTIVE;
2271 return I915_REQUEST_QUEUED;
2274 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2275 #include "selftests/mock_request.c"
2276 #include "selftests/i915_request.c"
2279 void i915_request_module_exit(void)
2281 kmem_cache_destroy(slab_execute_cbs);
2282 kmem_cache_destroy(slab_requests);
2285 int __init i915_request_module_init(void)
2288 kmem_cache_create("i915_request",
2289 sizeof(struct i915_request),
2290 __alignof__(struct i915_request),
2291 SLAB_HWCACHE_ALIGN |
2292 SLAB_RECLAIM_ACCOUNT |
2293 SLAB_TYPESAFE_BY_RCU,
2294 __i915_request_ctor);
2298 slab_execute_cbs = KMEM_CACHE(execute_cb,
2299 SLAB_HWCACHE_ALIGN |
2300 SLAB_RECLAIM_ACCOUNT |
2301 SLAB_TYPESAFE_BY_RCU);
2302 if (!slab_execute_cbs)
2308 kmem_cache_destroy(slab_requests);