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24 * Robert Bragg <robert@sixbynine.org>
29 * DOC: i915 Perf Overview
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
106 * - The perf based OA PMU driver broke some significant design assumptions:
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
194 #include <linux/anon_inodes.h>
195 #include <linux/nospec.h>
196 #include <linux/sizes.h>
197 #include <linux/uuid.h>
199 #include "gem/i915_gem_context.h"
200 #include "gem/i915_gem_internal.h"
201 #include "gt/intel_engine_pm.h"
202 #include "gt/intel_engine_regs.h"
203 #include "gt/intel_engine_user.h"
204 #include "gt/intel_execlists_submission.h"
205 #include "gt/intel_gpu_commands.h"
206 #include "gt/intel_gt.h"
207 #include "gt/intel_gt_clock_utils.h"
208 #include "gt/intel_gt_mcr.h"
209 #include "gt/intel_gt_regs.h"
210 #include "gt/intel_lrc.h"
211 #include "gt/intel_lrc_reg.h"
212 #include "gt/intel_rc6.h"
213 #include "gt/intel_ring.h"
214 #include "gt/uc/intel_guc_slpc.h"
216 #include "i915_drv.h"
217 #include "i915_file_private.h"
218 #include "i915_perf.h"
219 #include "i915_perf_oa_regs.h"
220 #include "i915_reg.h"
222 /* HW requires this to be a power of two, between 128k and 16M, though driver
223 * is currently generally designed assuming the largest 16M size is used such
224 * that the overflow cases are unlikely in normal operation.
226 #define OA_BUFFER_SIZE SZ_16M
228 #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
231 * DOC: OA Tail Pointer Race
233 * There's a HW race condition between OA unit tail pointer register updates and
234 * writes to memory whereby the tail pointer can sometimes get ahead of what's
235 * been written out to the OA buffer so far (in terms of what's visible to the
238 * Although this can be observed explicitly while copying reports to userspace
239 * by checking for a zeroed report-id field in tail reports, we want to account
240 * for this earlier, as part of the oa_buffer_check_unlocked to avoid lots of
241 * redundant read() attempts.
243 * We workaround this issue in oa_buffer_check_unlocked() by reading the reports
244 * in the OA buffer, starting from the tail reported by the HW until we find a
245 * report with its first 2 dwords not 0 meaning its previous report is
246 * completely in memory and ready to be read. Those dwords are also set to 0
247 * once read and the whole buffer is cleared upon OA buffer initialization. The
248 * first dword is the reason for this report while the second is the timestamp,
249 * making the chances of having those 2 fields at 0 fairly unlikely. A more
250 * detailed explanation is available in oa_buffer_check_unlocked().
252 * Most of the implementation details for this workaround are in
253 * oa_buffer_check_unlocked() and _append_oa_reports()
255 * Note for posterity: previously the driver used to define an effective tail
256 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
257 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
258 * This was flawed considering that the OA unit may also automatically generate
259 * non-periodic reports (such as on context switch) or the OA unit may be
260 * enabled without any periodic sampling.
262 #define OA_TAIL_MARGIN_NSEC 100000ULL
263 #define INVALID_TAIL_PTR 0xffffffff
265 /* The default frequency for checking whether the OA unit has written new
266 * reports to the circular OA buffer...
268 #define DEFAULT_POLL_FREQUENCY_HZ 200
269 #define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
271 /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
272 static u32 i915_perf_stream_paranoid = true;
274 /* The maximum exponent the hardware accepts is 63 (essentially it selects one
275 * of the 64bit timestamp bits to trigger reports from) but there's currently
276 * no known use case for sampling as infrequently as once per 47 thousand years.
278 * Since the timestamps included in OA reports are only 32bits it seems
279 * reasonable to limit the OA exponent where it's still possible to account for
280 * overflow in OA report timestamps.
282 #define OA_EXPONENT_MAX 31
284 #define INVALID_CTX_ID 0xffffffff
286 /* On Gen8+ automatically triggered OA reports include a 'reason' field... */
287 #define OAREPORT_REASON_MASK 0x3f
288 #define OAREPORT_REASON_MASK_EXTENDED 0x7f
289 #define OAREPORT_REASON_SHIFT 19
290 #define OAREPORT_REASON_TIMER (1<<0)
291 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
292 #define OAREPORT_REASON_CLK_RATIO (1<<5)
294 #define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
296 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
298 * The highest sampling frequency we can theoretically program the OA unit
299 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
301 * Initialized just before we register the sysctl parameter.
303 static int oa_sample_rate_hard_limit;
305 /* Theoretically we can program the OA unit to sample every 160ns but don't
306 * allow that by default unless root...
308 * The default threshold of 100000Hz is based on perf's similar
309 * kernel.perf_event_max_sample_rate sysctl parameter.
311 static u32 i915_oa_max_sample_rate = 100000;
313 /* XXX: beware if future OA HW adds new report formats that the current
314 * code assumes all reports have a power-of-two size and ~(size - 1) can
315 * be used as a mask to align the OA tail pointer.
317 static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
318 [I915_OA_FORMAT_A13] = { 0, 64 },
319 [I915_OA_FORMAT_A29] = { 1, 128 },
320 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
321 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
322 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
323 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
324 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
325 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
326 [I915_OA_FORMAT_A12] = { 0, 64 },
327 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
328 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
329 [I915_OAR_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
330 [I915_OA_FORMAT_A24u40_A14u32_B8_C8] = { 5, 256 },
331 [I915_OAM_FORMAT_MPEC8u64_B8_C8] = { 1, 192, TYPE_OAM, HDR_64_BIT },
332 [I915_OAM_FORMAT_MPEC8u32_B8_C8] = { 2, 128, TYPE_OAM, HDR_64_BIT },
335 static const u32 mtl_oa_base[] = {
336 [PERF_GROUP_OAM_SAMEDIA_0] = 0x393000,
339 #define SAMPLE_OA_REPORT (1<<0)
342 * struct perf_open_properties - for validated properties given to open a stream
343 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
344 * @single_context: Whether a single or all gpu contexts should be monitored
345 * @hold_preemption: Whether the preemption is disabled for the filtered
347 * @ctx_handle: A gem ctx handle for use with @single_context
348 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
349 * @oa_format: An OA unit HW report format
350 * @oa_periodic: Whether to enable periodic OA unit sampling
351 * @oa_period_exponent: The OA unit sampling period is derived from this
352 * @engine: The engine (typically rcs0) being monitored by the OA unit
353 * @has_sseu: Whether @sseu was specified by userspace
354 * @sseu: internal SSEU configuration computed either from the userspace
355 * specified configuration in the opening parameters or a default value
356 * (see get_default_sseu_config())
357 * @poll_oa_period: The period in nanoseconds at which the CPU will check for OA
360 * As read_properties_unlocked() enumerates and validates the properties given
361 * to open a stream of metrics the configuration is built up in the structure
362 * which starts out zero initialized.
364 struct perf_open_properties {
367 u64 single_context:1;
368 u64 hold_preemption:1;
371 /* OA sampling state */
375 int oa_period_exponent;
377 struct intel_engine_cs *engine;
380 struct intel_sseu sseu;
385 struct i915_oa_config_bo {
386 struct llist_node node;
388 struct i915_oa_config *oa_config;
389 struct i915_vma *vma;
392 static struct ctl_table_header *sysctl_header;
394 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
396 void i915_oa_config_release(struct kref *ref)
398 struct i915_oa_config *oa_config =
399 container_of(ref, typeof(*oa_config), ref);
401 kfree(oa_config->flex_regs);
402 kfree(oa_config->b_counter_regs);
403 kfree(oa_config->mux_regs);
405 kfree_rcu(oa_config, rcu);
408 struct i915_oa_config *
409 i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
411 struct i915_oa_config *oa_config;
414 oa_config = idr_find(&perf->metrics_idr, metrics_set);
416 oa_config = i915_oa_config_get(oa_config);
422 static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
424 i915_oa_config_put(oa_bo->oa_config);
425 i915_vma_put(oa_bo->vma);
430 struct i915_perf_regs *__oa_regs(struct i915_perf_stream *stream)
432 return &stream->engine->oa_group->regs;
435 static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
437 struct intel_uncore *uncore = stream->uncore;
439 return intel_uncore_read(uncore, __oa_regs(stream)->oa_tail_ptr) &
440 GEN12_OAG_OATAILPTR_MASK;
443 static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
445 struct intel_uncore *uncore = stream->uncore;
447 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
450 static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
452 struct intel_uncore *uncore = stream->uncore;
453 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
455 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
458 #define oa_report_header_64bit(__s) \
459 ((__s)->oa_buffer.format->header == HDR_64_BIT)
461 static u64 oa_report_id(struct i915_perf_stream *stream, void *report)
463 return oa_report_header_64bit(stream) ? *(u64 *)report : *(u32 *)report;
466 static u64 oa_report_reason(struct i915_perf_stream *stream, void *report)
468 return (oa_report_id(stream, report) >> OAREPORT_REASON_SHIFT) &
469 (GRAPHICS_VER(stream->perf->i915) == 12 ?
470 OAREPORT_REASON_MASK_EXTENDED :
471 OAREPORT_REASON_MASK);
474 static void oa_report_id_clear(struct i915_perf_stream *stream, u32 *report)
476 if (oa_report_header_64bit(stream))
482 static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report)
484 return !(oa_report_id(stream, report) &
485 stream->perf->gen8_valid_ctx_bit);
488 static u64 oa_timestamp(struct i915_perf_stream *stream, void *report)
490 return oa_report_header_64bit(stream) ?
491 *((u64 *)report + 1) :
492 *((u32 *)report + 1);
495 static void oa_timestamp_clear(struct i915_perf_stream *stream, u32 *report)
497 if (oa_report_header_64bit(stream))
498 *(u64 *)&report[2] = 0;
503 static u32 oa_context_id(struct i915_perf_stream *stream, u32 *report)
505 u32 ctx_id = oa_report_header_64bit(stream) ? report[4] : report[2];
507 return ctx_id & stream->specific_ctx_id_mask;
510 static void oa_context_id_squash(struct i915_perf_stream *stream, u32 *report)
512 if (oa_report_header_64bit(stream))
513 report[4] = INVALID_CTX_ID;
515 report[2] = INVALID_CTX_ID;
519 * oa_buffer_check_unlocked - check for data and update tail ptr state
520 * @stream: i915 stream instance
522 * This is either called via fops (for blocking reads in user ctx) or the poll
523 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
524 * if there is data available for userspace to read.
526 * This function is central to providing a workaround for the OA unit tail
527 * pointer having a race with respect to what data is visible to the CPU.
528 * It is responsible for reading tail pointers from the hardware and giving
529 * the pointers time to 'age' before they are made available for reading.
530 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
532 * Besides returning true when there is data available to read() this function
533 * also updates the tail in the oa_buffer object.
535 * Note: It's safe to read OA config state here unlocked, assuming that this is
536 * only called while the stream is enabled, while the global OA configuration
539 * Returns: %true if the OA buffer contains data, else %false
541 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
543 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
544 int report_size = stream->oa_buffer.format->size;
545 u32 head, tail, read_tail;
549 u32 partial_report_size;
551 /* We have to consider the (unlikely) possibility that read() errors
552 * could result in an OA buffer reset which might reset the head and
555 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
557 hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
559 /* The tail pointer increases in 64 byte increments, not in report_size
560 * steps. Also the report size may not be a power of 2. Compute
561 * potentially partially landed report in the OA buffer
563 partial_report_size = OA_TAKEN(hw_tail, stream->oa_buffer.tail);
564 partial_report_size %= report_size;
566 /* Subtract partial amount off the tail */
567 hw_tail = OA_TAKEN(hw_tail, partial_report_size);
569 /* NB: The head we observe here might effectively be a little
570 * out of date. If a read() is in progress, the head could be
571 * anywhere between this head and stream->oa_buffer.tail.
573 head = stream->oa_buffer.head - gtt_offset;
574 read_tail = stream->oa_buffer.tail - gtt_offset;
578 /* Walk the stream backward until we find a report with report
579 * id and timestmap not at 0. Since the circular buffer pointers
580 * progress by increments of 64 bytes and that reports can be up
581 * to 256 bytes long, we can't tell whether a report has fully
582 * landed in memory before the report id and timestamp of the
583 * following report have effectively landed.
585 * This is assuming that the writes of the OA unit land in
586 * memory in the order they were written to.
587 * If not : (╯°□°)╯︵ ┻━┻
589 while (OA_TAKEN(tail, read_tail) >= report_size) {
590 void *report = stream->oa_buffer.vaddr + tail;
592 if (oa_report_id(stream, report) ||
593 oa_timestamp(stream, report))
596 tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
599 if (OA_TAKEN(hw_tail, tail) > report_size &&
600 __ratelimit(&stream->perf->tail_pointer_race))
601 drm_notice(&stream->uncore->i915->drm,
602 "unlanded report(s) head=0x%x tail=0x%x hw_tail=0x%x\n",
603 head, tail, hw_tail);
605 stream->oa_buffer.tail = gtt_offset + tail;
607 pollin = OA_TAKEN(stream->oa_buffer.tail,
608 stream->oa_buffer.head) >= report_size;
610 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
616 * append_oa_status - Appends a status record to a userspace read() buffer.
617 * @stream: An i915-perf stream opened for OA metrics
618 * @buf: destination buffer given by userspace
619 * @count: the number of bytes userspace wants to read
620 * @offset: (inout): the current position for writing into @buf
621 * @type: The kind of status to report to userspace
623 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
624 * into the userspace read() buffer.
626 * The @buf @offset will only be updated on success.
628 * Returns: 0 on success, negative error code on failure.
630 static int append_oa_status(struct i915_perf_stream *stream,
634 enum drm_i915_perf_record_type type)
636 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
638 if ((count - *offset) < header.size)
641 if (copy_to_user(buf + *offset, &header, sizeof(header)))
644 (*offset) += header.size;
650 * append_oa_sample - Copies single OA report into userspace read() buffer.
651 * @stream: An i915-perf stream opened for OA metrics
652 * @buf: destination buffer given by userspace
653 * @count: the number of bytes userspace wants to read
654 * @offset: (inout): the current position for writing into @buf
655 * @report: A single OA report to (optionally) include as part of the sample
657 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
658 * properties when opening a stream, tracked as `stream->sample_flags`. This
659 * function copies the requested components of a single sample to the given
662 * The @buf @offset will only be updated on success.
664 * Returns: 0 on success, negative error code on failure.
666 static int append_oa_sample(struct i915_perf_stream *stream,
672 int report_size = stream->oa_buffer.format->size;
673 struct drm_i915_perf_record_header header;
674 int report_size_partial;
677 header.type = DRM_I915_PERF_RECORD_SAMPLE;
679 header.size = stream->sample_size;
681 if ((count - *offset) < header.size)
685 if (copy_to_user(buf, &header, sizeof(header)))
687 buf += sizeof(header);
689 oa_buf_end = stream->oa_buffer.vaddr + OA_BUFFER_SIZE;
690 report_size_partial = oa_buf_end - report;
692 if (report_size_partial < report_size) {
693 if (copy_to_user(buf, report, report_size_partial))
695 buf += report_size_partial;
697 if (copy_to_user(buf, stream->oa_buffer.vaddr,
698 report_size - report_size_partial))
700 } else if (copy_to_user(buf, report, report_size)) {
704 (*offset) += header.size;
710 * gen8_append_oa_reports - Copies all buffered OA reports into
711 * userspace read() buffer.
712 * @stream: An i915-perf stream opened for OA metrics
713 * @buf: destination buffer given by userspace
714 * @count: the number of bytes userspace wants to read
715 * @offset: (inout): the current position for writing into @buf
717 * Notably any error condition resulting in a short read (-%ENOSPC or
718 * -%EFAULT) will be returned even though one or more records may
719 * have been successfully copied. In this case it's up to the caller
720 * to decide if the error should be squashed before returning to
723 * Note: reports are consumed from the head, and appended to the
724 * tail, so the tail chases the head?... If you think that's mad
725 * and back-to-front you're not alone, but this follows the
726 * Gen PRM naming convention.
728 * Returns: 0 on success, negative error code on failure.
730 static int gen8_append_oa_reports(struct i915_perf_stream *stream,
735 struct intel_uncore *uncore = stream->uncore;
736 int report_size = stream->oa_buffer.format->size;
737 u8 *oa_buf_base = stream->oa_buffer.vaddr;
738 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
739 u32 mask = (OA_BUFFER_SIZE - 1);
740 size_t start_offset = *offset;
745 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
748 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
750 head = stream->oa_buffer.head;
751 tail = stream->oa_buffer.tail;
753 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
756 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
757 * while indexing relative to oa_buf_base.
763 * An out of bounds or misaligned head or tail pointer implies a driver
764 * bug since we validate + align the tail pointers we read from the
765 * hardware and we are in full control of the head pointer which should
766 * only be incremented by multiples of the report size.
768 if (drm_WARN_ONCE(&uncore->i915->drm,
769 head > OA_BUFFER_SIZE ||
770 tail > OA_BUFFER_SIZE,
771 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
777 OA_TAKEN(tail, head);
778 head = (head + report_size) & mask) {
779 u8 *report = oa_buf_base + head;
780 u32 *report32 = (void *)report;
785 * The reason field includes flags identifying what
786 * triggered this specific report (mostly timer
787 * triggered or e.g. due to a context switch).
789 * In MMIO triggered reports, some platforms do not set the
790 * reason bit in this field and it is valid to have a reason
793 reason = oa_report_reason(stream, report);
794 ctx_id = oa_context_id(stream, report32);
797 * Squash whatever is in the CTX_ID field if it's marked as
798 * invalid to be sure we avoid false-positive, single-context
801 * Note: that we don't clear the valid_ctx_bit so userspace can
802 * understand that the ID has been squashed by the kernel.
804 if (oa_report_ctx_invalid(stream, report)) {
805 ctx_id = INVALID_CTX_ID;
806 oa_context_id_squash(stream, report32);
810 * NB: For Gen 8 the OA unit no longer supports clock gating
811 * off for a specific context and the kernel can't securely
812 * stop the counters from updating as system-wide / global
815 * Automatic reports now include a context ID so reports can be
816 * filtered on the cpu but it's not worth trying to
817 * automatically subtract/hide counter progress for other
818 * contexts while filtering since we can't stop userspace
819 * issuing MI_REPORT_PERF_COUNT commands which would still
820 * provide a side-band view of the real values.
822 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
823 * to normalize counters for a single filtered context then it
824 * needs be forwarded bookend context-switch reports so that it
825 * can track switches in between MI_REPORT_PERF_COUNT commands
826 * and can itself subtract/ignore the progress of counters
827 * associated with other contexts. Note that the hardware
828 * automatically triggers reports when switching to a new
829 * context which are tagged with the ID of the newly active
830 * context. To avoid the complexity (and likely fragility) of
831 * reading ahead while parsing reports to try and minimize
832 * forwarding redundant context switch reports (i.e. between
833 * other, unrelated contexts) we simply elect to forward them
836 * We don't rely solely on the reason field to identify context
837 * switches since it's not-uncommon for periodic samples to
838 * identify a switch before any 'context switch' report.
841 stream->specific_ctx_id == ctx_id ||
842 stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
843 reason & OAREPORT_REASON_CTX_SWITCH) {
846 * While filtering for a single context we avoid
847 * leaking the IDs of other contexts.
850 stream->specific_ctx_id != ctx_id) {
851 oa_context_id_squash(stream, report32);
854 ret = append_oa_sample(stream, buf, count, offset,
859 stream->oa_buffer.last_ctx_id = ctx_id;
862 if (is_power_of_2(report_size)) {
864 * Clear out the report id and timestamp as a means
865 * to detect unlanded reports.
867 oa_report_id_clear(stream, report32);
868 oa_timestamp_clear(stream, report32);
870 u8 *oa_buf_end = stream->oa_buffer.vaddr +
872 u32 part = oa_buf_end - (u8 *)report32;
874 /* Zero out the entire report */
875 if (report_size <= part) {
876 memset(report32, 0, report_size);
878 memset(report32, 0, part);
879 memset(oa_buf_base, 0, report_size - part);
884 if (start_offset != *offset) {
885 i915_reg_t oaheadptr;
887 oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
888 __oa_regs(stream)->oa_head_ptr :
891 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
894 * We removed the gtt_offset for the copy loop above, indexing
895 * relative to oa_buf_base so put back here...
898 intel_uncore_write(uncore, oaheadptr,
899 head & GEN12_OAG_OAHEADPTR_MASK);
900 stream->oa_buffer.head = head;
902 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
909 * gen8_oa_read - copy status records then buffered OA reports
910 * @stream: An i915-perf stream opened for OA metrics
911 * @buf: destination buffer given by userspace
912 * @count: the number of bytes userspace wants to read
913 * @offset: (inout): the current position for writing into @buf
915 * Checks OA unit status registers and if necessary appends corresponding
916 * status records for userspace (such as for a buffer full condition) and then
917 * initiate appending any buffered OA reports.
919 * Updates @offset according to the number of bytes successfully copied into
920 * the userspace buffer.
922 * NB: some data may be successfully copied to the userspace buffer
923 * even if an error is returned, and this is reflected in the
926 * Returns: zero on success or a negative error code
928 static int gen8_oa_read(struct i915_perf_stream *stream,
933 struct intel_uncore *uncore = stream->uncore;
935 i915_reg_t oastatus_reg;
938 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
941 oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
942 __oa_regs(stream)->oa_status :
945 oastatus = intel_uncore_read(uncore, oastatus_reg);
948 * We treat OABUFFER_OVERFLOW as a significant error:
950 * Although theoretically we could handle this more gracefully
951 * sometimes, some Gens don't correctly suppress certain
952 * automatically triggered reports in this condition and so we
953 * have to assume that old reports are now being trampled
956 * Considering how we don't currently give userspace control
957 * over the OA buffer size and always configure a large 16MB
958 * buffer, then a buffer overflow does anyway likely indicate
959 * that something has gone quite badly wrong.
961 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
962 ret = append_oa_status(stream, buf, count, offset,
963 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
967 drm_dbg(&stream->perf->i915->drm,
968 "OA buffer overflow (exponent = %d): force restart\n",
969 stream->period_exponent);
971 stream->perf->ops.oa_disable(stream);
972 stream->perf->ops.oa_enable(stream);
975 * Note: .oa_enable() is expected to re-init the oabuffer and
976 * reset GEN8_OASTATUS for us
978 oastatus = intel_uncore_read(uncore, oastatus_reg);
981 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
982 ret = append_oa_status(stream, buf, count, offset,
983 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
987 intel_uncore_rmw(uncore, oastatus_reg,
988 GEN8_OASTATUS_COUNTER_OVERFLOW |
989 GEN8_OASTATUS_REPORT_LOST,
990 IS_GRAPHICS_VER(uncore->i915, 8, 11) ?
991 (GEN8_OASTATUS_HEAD_POINTER_WRAP |
992 GEN8_OASTATUS_TAIL_POINTER_WRAP) : 0);
995 return gen8_append_oa_reports(stream, buf, count, offset);
999 * gen7_append_oa_reports - Copies all buffered OA reports into
1000 * userspace read() buffer.
1001 * @stream: An i915-perf stream opened for OA metrics
1002 * @buf: destination buffer given by userspace
1003 * @count: the number of bytes userspace wants to read
1004 * @offset: (inout): the current position for writing into @buf
1006 * Notably any error condition resulting in a short read (-%ENOSPC or
1007 * -%EFAULT) will be returned even though one or more records may
1008 * have been successfully copied. In this case it's up to the caller
1009 * to decide if the error should be squashed before returning to
1012 * Note: reports are consumed from the head, and appended to the
1013 * tail, so the tail chases the head?... If you think that's mad
1014 * and back-to-front you're not alone, but this follows the
1015 * Gen PRM naming convention.
1017 * Returns: 0 on success, negative error code on failure.
1019 static int gen7_append_oa_reports(struct i915_perf_stream *stream,
1024 struct intel_uncore *uncore = stream->uncore;
1025 int report_size = stream->oa_buffer.format->size;
1026 u8 *oa_buf_base = stream->oa_buffer.vaddr;
1027 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1028 u32 mask = (OA_BUFFER_SIZE - 1);
1029 size_t start_offset = *offset;
1030 unsigned long flags;
1034 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
1037 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1039 head = stream->oa_buffer.head;
1040 tail = stream->oa_buffer.tail;
1042 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1044 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
1045 * while indexing relative to oa_buf_base.
1050 /* An out of bounds or misaligned head or tail pointer implies a driver
1051 * bug since we validate + align the tail pointers we read from the
1052 * hardware and we are in full control of the head pointer which should
1053 * only be incremented by multiples of the report size (notably also
1054 * all a power of two).
1056 if (drm_WARN_ONCE(&uncore->i915->drm,
1057 head > OA_BUFFER_SIZE || head % report_size ||
1058 tail > OA_BUFFER_SIZE || tail % report_size,
1059 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
1065 OA_TAKEN(tail, head);
1066 head = (head + report_size) & mask) {
1067 u8 *report = oa_buf_base + head;
1068 u32 *report32 = (void *)report;
1070 /* All the report sizes factor neatly into the buffer
1071 * size so we never expect to see a report split
1072 * between the beginning and end of the buffer.
1074 * Given the initial alignment check a misalignment
1075 * here would imply a driver bug that would result
1078 if (drm_WARN_ON(&uncore->i915->drm,
1079 (OA_BUFFER_SIZE - head) < report_size)) {
1080 drm_err(&uncore->i915->drm,
1081 "Spurious OA head ptr: non-integral report offset\n");
1085 /* The report-ID field for periodic samples includes
1086 * some undocumented flags related to what triggered
1087 * the report and is never expected to be zero so we
1088 * can check that the report isn't invalid before
1089 * copying it to userspace...
1091 if (report32[0] == 0) {
1092 if (__ratelimit(&stream->perf->spurious_report_rs))
1093 drm_notice(&uncore->i915->drm,
1094 "Skipping spurious, invalid OA report\n");
1098 ret = append_oa_sample(stream, buf, count, offset, report);
1102 /* Clear out the first 2 dwords as a mean to detect unlanded
1109 if (start_offset != *offset) {
1110 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1112 /* We removed the gtt_offset for the copy loop above, indexing
1113 * relative to oa_buf_base so put back here...
1117 intel_uncore_write(uncore, GEN7_OASTATUS2,
1118 (head & GEN7_OASTATUS2_HEAD_MASK) |
1119 GEN7_OASTATUS2_MEM_SELECT_GGTT);
1120 stream->oa_buffer.head = head;
1122 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1129 * gen7_oa_read - copy status records then buffered OA reports
1130 * @stream: An i915-perf stream opened for OA metrics
1131 * @buf: destination buffer given by userspace
1132 * @count: the number of bytes userspace wants to read
1133 * @offset: (inout): the current position for writing into @buf
1135 * Checks Gen 7 specific OA unit status registers and if necessary appends
1136 * corresponding status records for userspace (such as for a buffer full
1137 * condition) and then initiate appending any buffered OA reports.
1139 * Updates @offset according to the number of bytes successfully copied into
1140 * the userspace buffer.
1142 * Returns: zero on success or a negative error code
1144 static int gen7_oa_read(struct i915_perf_stream *stream,
1149 struct intel_uncore *uncore = stream->uncore;
1153 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
1156 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1158 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1159 * bits while the OA unit is enabled (while the tail pointer
1160 * may be updated asynchronously) so we ignore status bits
1161 * that have already been reported to userspace.
1163 oastatus1 &= ~stream->perf->gen7_latched_oastatus1;
1165 /* We treat OABUFFER_OVERFLOW as a significant error:
1167 * - The status can be interpreted to mean that the buffer is
1168 * currently full (with a higher precedence than OA_TAKEN()
1169 * which will start to report a near-empty buffer after an
1170 * overflow) but it's awkward that we can't clear the status
1171 * on Haswell, so without a reset we won't be able to catch
1174 * - Since it also implies the HW has started overwriting old
1175 * reports it may also affect our sanity checks for invalid
1176 * reports when copying to userspace that assume new reports
1177 * are being written to cleared memory.
1179 * - In the future we may want to introduce a flight recorder
1180 * mode where the driver will automatically maintain a safe
1181 * guard band between head/tail, avoiding this overflow
1182 * condition, but we avoid the added driver complexity for
1185 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1186 ret = append_oa_status(stream, buf, count, offset,
1187 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1191 drm_dbg(&stream->perf->i915->drm,
1192 "OA buffer overflow (exponent = %d): force restart\n",
1193 stream->period_exponent);
1195 stream->perf->ops.oa_disable(stream);
1196 stream->perf->ops.oa_enable(stream);
1198 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1201 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1202 ret = append_oa_status(stream, buf, count, offset,
1203 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1206 stream->perf->gen7_latched_oastatus1 |=
1207 GEN7_OASTATUS1_REPORT_LOST;
1210 return gen7_append_oa_reports(stream, buf, count, offset);
1214 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1215 * @stream: An i915-perf stream opened for OA metrics
1217 * Called when userspace tries to read() from a blocking stream FD opened
1218 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1219 * OA buffer and wakes us.
1221 * Note: it's acceptable to have this return with some false positives
1222 * since any subsequent read handling will return -EAGAIN if there isn't
1223 * really data ready for userspace yet.
1225 * Returns: zero on success or a negative error code
1227 static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1229 /* We would wait indefinitely if periodic sampling is not enabled */
1230 if (!stream->periodic)
1233 return wait_event_interruptible(stream->poll_wq,
1234 oa_buffer_check_unlocked(stream));
1238 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1239 * @stream: An i915-perf stream opened for OA metrics
1240 * @file: An i915 perf stream file
1241 * @wait: poll() state table
1243 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1244 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1245 * when it sees data ready to read in the circular OA buffer.
1247 static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1251 poll_wait(file, &stream->poll_wq, wait);
1255 * i915_oa_read - just calls through to &i915_oa_ops->read
1256 * @stream: An i915-perf stream opened for OA metrics
1257 * @buf: destination buffer given by userspace
1258 * @count: the number of bytes userspace wants to read
1259 * @offset: (inout): the current position for writing into @buf
1261 * Updates @offset according to the number of bytes successfully copied into
1262 * the userspace buffer.
1264 * Returns: zero on success or a negative error code
1266 static int i915_oa_read(struct i915_perf_stream *stream,
1271 return stream->perf->ops.read(stream, buf, count, offset);
1274 static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
1276 struct i915_gem_engines_iter it;
1277 struct i915_gem_context *ctx = stream->ctx;
1278 struct intel_context *ce;
1279 struct i915_gem_ww_ctx ww;
1282 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1283 if (ce->engine != stream->engine) /* first match! */
1289 i915_gem_context_unlock_engines(ctx);
1292 return ERR_PTR(err);
1294 i915_gem_ww_ctx_init(&ww, true);
1297 * As the ID is the gtt offset of the context's vma we
1298 * pin the vma to ensure the ID remains fixed.
1300 err = intel_context_pin_ww(ce, &ww);
1301 if (err == -EDEADLK) {
1302 err = i915_gem_ww_ctx_backoff(&ww);
1306 i915_gem_ww_ctx_fini(&ww);
1309 return ERR_PTR(err);
1311 stream->pinned_ctx = ce;
1312 return stream->pinned_ctx;
1316 __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
1320 cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1321 if (GRAPHICS_VER(rq->i915) >= 8)
1324 cs = intel_ring_begin(rq, 4);
1329 *cs++ = i915_mmio_reg_offset(reg);
1330 *cs++ = ggtt_offset;
1333 intel_ring_advance(rq, cs);
1339 __read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
1341 struct i915_request *rq;
1344 rq = i915_request_create(ce);
1348 i915_request_get(rq);
1350 err = __store_reg_to_mem(rq, reg, ggtt_offset);
1352 i915_request_add(rq);
1353 if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
1356 i915_request_put(rq);
1362 gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
1364 struct i915_vma *scratch;
1368 scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
1369 if (IS_ERR(scratch))
1370 return PTR_ERR(scratch);
1372 err = i915_vma_sync(scratch);
1376 err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
1377 i915_ggtt_offset(scratch));
1381 val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
1388 i915_gem_object_unpin_map(scratch->obj);
1391 i915_vma_unpin_and_release(&scratch, 0);
1396 * For execlist mode of submission, pick an unused context id
1397 * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
1398 * XXX_MAX_CONTEXT_HW_ID is used by idle context
1400 * For GuC mode of submission read context id from the upper dword of the
1401 * EXECLIST_STATUS register. Note that we read this value only once and expect
1402 * that the value stays fixed for the entire OA use case. There are cases where
1403 * GuC KMD implementation may deregister a context to reuse it's context id, but
1404 * we prevent that from happening to the OA context by pinning it.
1406 static int gen12_get_render_context_id(struct i915_perf_stream *stream)
1411 if (intel_engine_uses_guc(stream->engine)) {
1412 ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, &ctx_id);
1416 mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
1417 (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
1418 } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
1419 ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
1420 (XEHP_SW_CTX_ID_SHIFT - 32);
1422 mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
1423 (XEHP_SW_CTX_ID_SHIFT - 32);
1425 ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
1426 (GEN11_SW_CTX_ID_SHIFT - 32);
1428 mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
1429 (GEN11_SW_CTX_ID_SHIFT - 32);
1431 stream->specific_ctx_id = ctx_id & mask;
1432 stream->specific_ctx_id_mask = mask;
1437 static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
1440 u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
1444 for (; idx < len; idx += 2) {
1445 if (state[idx] == reg) {
1455 static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
1457 u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
1458 u32 *state = ce->lrc_reg_state;
1460 if (drm_WARN_ON(&ce->engine->i915->drm, !state))
1463 for (offset = 0; offset < len; ) {
1464 if (IS_MI_LRI_CMD(state[offset])) {
1466 * We expect reg-value pairs in MI_LRI command, so
1467 * MI_LRI_LEN() should be even, if not, issue a warning.
1469 drm_WARN_ON(&ce->engine->i915->drm,
1470 MI_LRI_LEN(state[offset]) & 0x1);
1472 if (oa_find_reg_in_lri(state, reg, &offset, len))
1479 return offset < len ? offset : U32_MAX;
1482 static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
1484 i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
1485 struct i915_perf *perf = &ce->engine->i915->perf;
1486 u32 offset = perf->ctx_oactxctrl_offset;
1488 /* Do this only once. Failure is stored as offset of U32_MAX */
1492 offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
1493 perf->ctx_oactxctrl_offset = offset;
1495 drm_dbg(&ce->engine->i915->drm,
1496 "%s oa ctx control at 0x%08x dword offset\n",
1497 ce->engine->name, offset);
1500 return offset && offset != U32_MAX ? 0 : -ENODEV;
1503 static bool engine_supports_mi_query(struct intel_engine_cs *engine)
1505 return engine->class == RENDER_CLASS;
1509 * oa_get_render_ctx_id - determine and hold ctx hw id
1510 * @stream: An i915-perf stream opened for OA metrics
1512 * Determine the render context hw id, and ensure it remains fixed for the
1513 * lifetime of the stream. This ensures that we don't have to worry about
1514 * updating the context ID in OACONTROL on the fly.
1516 * Returns: zero on success or a negative error code
1518 static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1520 struct intel_context *ce;
1523 ce = oa_pin_context(stream);
1527 if (engine_supports_mi_query(stream->engine) &&
1528 HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
1530 * We are enabling perf query here. If we don't find the context
1531 * offset here, just return an error.
1533 ret = set_oa_ctx_ctrl_offset(ce);
1535 intel_context_unpin(ce);
1536 drm_err(&stream->perf->i915->drm,
1537 "Enabling perf query failed for %s\n",
1538 stream->engine->name);
1543 switch (GRAPHICS_VER(ce->engine->i915)) {
1546 * On Haswell we don't do any post processing of the reports
1547 * and don't need to use the mask.
1549 stream->specific_ctx_id = i915_ggtt_offset(ce->state);
1550 stream->specific_ctx_id_mask = 0;
1556 if (intel_engine_uses_guc(ce->engine)) {
1558 * When using GuC, the context descriptor we write in
1559 * i915 is read by GuC and rewritten before it's
1560 * actually written into the hardware. The LRCA is
1561 * what is put into the context id field of the
1562 * context descriptor by GuC. Because it's aligned to
1563 * a page, the lower 12bits are always at 0 and
1564 * dropped by GuC. They won't be part of the context
1565 * ID in the OA reports, so squash those lower bits.
1567 stream->specific_ctx_id = ce->lrc.lrca >> 12;
1570 * GuC uses the top bit to signal proxy submission, so
1573 stream->specific_ctx_id_mask =
1574 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1576 stream->specific_ctx_id_mask =
1577 (1U << GEN8_CTX_ID_WIDTH) - 1;
1578 stream->specific_ctx_id = stream->specific_ctx_id_mask;
1584 ret = gen12_get_render_context_id(stream);
1588 MISSING_CASE(GRAPHICS_VER(ce->engine->i915));
1591 ce->tag = stream->specific_ctx_id;
1593 drm_dbg(&stream->perf->i915->drm,
1594 "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1595 stream->specific_ctx_id,
1596 stream->specific_ctx_id_mask);
1602 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1603 * @stream: An i915-perf stream opened for OA metrics
1605 * In case anything needed doing to ensure the context HW ID would remain valid
1606 * for the lifetime of the stream, then that can be undone here.
1608 static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1610 struct intel_context *ce;
1612 ce = fetch_and_zero(&stream->pinned_ctx);
1614 ce->tag = 0; /* recomputed on next submission after parking */
1615 intel_context_unpin(ce);
1618 stream->specific_ctx_id = INVALID_CTX_ID;
1619 stream->specific_ctx_id_mask = 0;
1623 free_oa_buffer(struct i915_perf_stream *stream)
1625 i915_vma_unpin_and_release(&stream->oa_buffer.vma,
1626 I915_VMA_RELEASE_MAP);
1628 stream->oa_buffer.vaddr = NULL;
1632 free_oa_configs(struct i915_perf_stream *stream)
1634 struct i915_oa_config_bo *oa_bo, *tmp;
1636 i915_oa_config_put(stream->oa_config);
1637 llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
1638 free_oa_config_bo(oa_bo);
1642 free_noa_wait(struct i915_perf_stream *stream)
1644 i915_vma_unpin_and_release(&stream->noa_wait, 0);
1647 static bool engine_supports_oa(const struct intel_engine_cs *engine)
1649 return engine->oa_group;
1652 static bool engine_supports_oa_format(struct intel_engine_cs *engine, int type)
1654 return engine->oa_group && engine->oa_group->type == type;
1657 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1659 struct i915_perf *perf = stream->perf;
1660 struct intel_gt *gt = stream->engine->gt;
1661 struct i915_perf_group *g = stream->engine->oa_group;
1663 if (WARN_ON(stream != g->exclusive_stream))
1667 * Unset exclusive_stream first, it will be checked while disabling
1668 * the metric set on gen8+.
1670 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
1672 WRITE_ONCE(g->exclusive_stream, NULL);
1673 perf->ops.disable_metric_set(stream);
1675 free_oa_buffer(stream);
1678 * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.
1680 if (stream->override_gucrc)
1681 drm_WARN_ON(>->i915->drm,
1682 intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc));
1684 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
1685 intel_engine_pm_put(stream->engine);
1688 oa_put_render_ctx_id(stream);
1690 free_oa_configs(stream);
1691 free_noa_wait(stream);
1693 if (perf->spurious_report_rs.missed) {
1694 drm_notice(>->i915->drm,
1695 "%d spurious OA report notices suppressed due to ratelimiting\n",
1696 perf->spurious_report_rs.missed);
1700 static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
1702 struct intel_uncore *uncore = stream->uncore;
1703 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1704 unsigned long flags;
1706 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1708 /* Pre-DevBDW: OABUFFER must be set with counters off,
1709 * before OASTATUS1, but after OASTATUS2
1711 intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */
1712 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT);
1713 stream->oa_buffer.head = gtt_offset;
1715 intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset);
1717 intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */
1718 gtt_offset | OABUFFER_SIZE_16M);
1720 /* Mark that we need updated tail pointers to read from... */
1721 stream->oa_buffer.tail = gtt_offset;
1723 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1725 /* On Haswell we have to track which OASTATUS1 flags we've
1726 * already seen since they can't be cleared while periodic
1727 * sampling is enabled.
1729 stream->perf->gen7_latched_oastatus1 = 0;
1731 /* NB: although the OA buffer will initially be allocated
1732 * zeroed via shmfs (and so this memset is redundant when
1733 * first allocating), we may re-init the OA buffer, either
1734 * when re-enabling a stream or in error/reset paths.
1736 * The reason we clear the buffer for each re-init is for the
1737 * sanity check in gen7_append_oa_reports() that looks at the
1738 * report-id field to make sure it's non-zero which relies on
1739 * the assumption that new reports are being written to zeroed
1742 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1745 static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
1747 struct intel_uncore *uncore = stream->uncore;
1748 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1749 unsigned long flags;
1751 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1753 intel_uncore_write(uncore, GEN8_OASTATUS, 0);
1754 intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset);
1755 stream->oa_buffer.head = gtt_offset;
1757 intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0);
1762 * "This MMIO must be set before the OATAILPTR
1763 * register and after the OAHEADPTR register. This is
1764 * to enable proper functionality of the overflow
1767 intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
1768 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1769 intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1771 /* Mark that we need updated tail pointers to read from... */
1772 stream->oa_buffer.tail = gtt_offset;
1775 * Reset state used to recognise context switches, affecting which
1776 * reports we will forward to userspace while filtering for a single
1779 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1781 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1784 * NB: although the OA buffer will initially be allocated
1785 * zeroed via shmfs (and so this memset is redundant when
1786 * first allocating), we may re-init the OA buffer, either
1787 * when re-enabling a stream or in error/reset paths.
1789 * The reason we clear the buffer for each re-init is for the
1790 * sanity check in gen8_append_oa_reports() that looks at the
1791 * reason field to make sure it's non-zero which relies on
1792 * the assumption that new reports are being written to zeroed
1795 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1798 static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
1800 struct intel_uncore *uncore = stream->uncore;
1801 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1802 unsigned long flags;
1804 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1806 intel_uncore_write(uncore, __oa_regs(stream)->oa_status, 0);
1807 intel_uncore_write(uncore, __oa_regs(stream)->oa_head_ptr,
1808 gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
1809 stream->oa_buffer.head = gtt_offset;
1814 * "This MMIO must be set before the OATAILPTR
1815 * register and after the OAHEADPTR register. This is
1816 * to enable proper functionality of the overflow
1819 intel_uncore_write(uncore, __oa_regs(stream)->oa_buffer, gtt_offset |
1820 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1821 intel_uncore_write(uncore, __oa_regs(stream)->oa_tail_ptr,
1822 gtt_offset & GEN12_OAG_OATAILPTR_MASK);
1824 /* Mark that we need updated tail pointers to read from... */
1825 stream->oa_buffer.tail = gtt_offset;
1828 * Reset state used to recognise context switches, affecting which
1829 * reports we will forward to userspace while filtering for a single
1832 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1834 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1837 * NB: although the OA buffer will initially be allocated
1838 * zeroed via shmfs (and so this memset is redundant when
1839 * first allocating), we may re-init the OA buffer, either
1840 * when re-enabling a stream or in error/reset paths.
1842 * The reason we clear the buffer for each re-init is for the
1843 * sanity check in gen8_append_oa_reports() that looks at the
1844 * reason field to make sure it's non-zero which relies on
1845 * the assumption that new reports are being written to zeroed
1848 memset(stream->oa_buffer.vaddr, 0,
1849 stream->oa_buffer.vma->size);
1852 static int alloc_oa_buffer(struct i915_perf_stream *stream)
1854 struct drm_i915_private *i915 = stream->perf->i915;
1855 struct intel_gt *gt = stream->engine->gt;
1856 struct drm_i915_gem_object *bo;
1857 struct i915_vma *vma;
1860 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.vma))
1863 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1864 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1866 bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE);
1868 drm_err(&i915->drm, "Failed to allocate OA buffer\n");
1872 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1874 /* PreHSW required 512K alignment, HSW requires 16M */
1875 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1882 * PreHSW required 512K alignment.
1883 * HSW and onwards, align to requested size of OA buffer.
1885 ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
1887 drm_err(>->i915->drm, "Failed to pin OA buffer %d\n", ret);
1891 stream->oa_buffer.vma = vma;
1893 stream->oa_buffer.vaddr =
1894 i915_gem_object_pin_map_unlocked(bo, I915_MAP_WB);
1895 if (IS_ERR(stream->oa_buffer.vaddr)) {
1896 ret = PTR_ERR(stream->oa_buffer.vaddr);
1903 __i915_vma_unpin(vma);
1906 i915_gem_object_put(bo);
1908 stream->oa_buffer.vaddr = NULL;
1909 stream->oa_buffer.vma = NULL;
1914 static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
1915 bool save, i915_reg_t reg, u32 offset,
1921 cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
1922 cmd |= MI_SRM_LRM_GLOBAL_GTT;
1923 if (GRAPHICS_VER(stream->perf->i915) >= 8)
1926 for (d = 0; d < dword_count; d++) {
1928 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1929 *cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
1936 static int alloc_noa_wait(struct i915_perf_stream *stream)
1938 struct drm_i915_private *i915 = stream->perf->i915;
1939 struct intel_gt *gt = stream->engine->gt;
1940 struct drm_i915_gem_object *bo;
1941 struct i915_vma *vma;
1942 const u64 delay_ticks = 0xffffffffffffffff -
1943 intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
1944 atomic64_read(&stream->perf->noa_programming_delay));
1945 const u32 base = stream->engine->mmio_base;
1946 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
1947 u32 *batch, *ts0, *cs, *jump;
1948 struct i915_gem_ww_ctx ww;
1958 i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
1959 MI_PREDICATE_RESULT_2_ENGINE(base) :
1960 MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
1963 * gt->scratch was being used to save/restore the GPR registers, but on
1964 * MTL the scratch uses stolen lmem. An MI_SRM to this memory region
1965 * causes an engine hang. Instead allocate an additional page here to
1966 * save/restore GPR registers
1968 bo = i915_gem_object_create_internal(i915, 8192);
1971 "Failed to allocate NOA wait batchbuffer\n");
1975 i915_gem_ww_ctx_init(&ww, true);
1977 ret = i915_gem_object_lock(bo, &ww);
1982 * We pin in GGTT because we jump into this buffer now because
1983 * multiple OA config BOs will have a jump to this address and it
1984 * needs to be fixed during the lifetime of the i915/perf stream.
1986 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1992 ret = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
1996 batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
1997 if (IS_ERR(batch)) {
1998 ret = PTR_ERR(batch);
2002 stream->noa_wait = vma;
2004 #define GPR_SAVE_OFFSET 4096
2005 #define PREDICATE_SAVE_OFFSET 4160
2007 /* Save registers. */
2008 for (i = 0; i < N_CS_GPR; i++)
2009 cs = save_restore_register(
2010 stream, cs, true /* save */, CS_GPR(i),
2011 GPR_SAVE_OFFSET + 8 * i, 2);
2012 cs = save_restore_register(
2013 stream, cs, true /* save */, mi_predicate_result,
2014 PREDICATE_SAVE_OFFSET, 1);
2016 /* First timestamp snapshot location. */
2020 * Initial snapshot of the timestamp register to implement the wait.
2021 * We work with 32b values, so clear out the top 32b bits of the
2022 * register because the ALU works 64bits.
2024 *cs++ = MI_LOAD_REGISTER_IMM(1);
2025 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
2027 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2028 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
2029 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
2032 * This is the location we're going to jump back into until the
2033 * required amount of time has passed.
2038 * Take another snapshot of the timestamp register. Take care to clear
2039 * up the top 32bits of CS_GPR(1) as we're using it for other
2042 *cs++ = MI_LOAD_REGISTER_IMM(1);
2043 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
2045 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2046 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
2047 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
2050 * Do a diff between the 2 timestamps and store the result back into
2054 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
2055 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
2056 *cs++ = MI_MATH_SUB;
2057 *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);
2058 *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
2061 * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
2062 * timestamp have rolled over the 32bits) into the predicate register
2063 * to be used for the predicated jump.
2065 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2066 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
2067 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
2069 if (HAS_MI_SET_PREDICATE(i915))
2070 *cs++ = MI_SET_PREDICATE | 1;
2072 /* Restart from the beginning if we had timestamps roll over. */
2073 *cs++ = (GRAPHICS_VER(i915) < 8 ?
2074 MI_BATCH_BUFFER_START :
2075 MI_BATCH_BUFFER_START_GEN8) |
2077 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
2080 if (HAS_MI_SET_PREDICATE(i915))
2081 *cs++ = MI_SET_PREDICATE;
2084 * Now add the diff between to previous timestamps and add it to :
2085 * (((1 * << 64) - 1) - delay_ns)
2087 * When the Carry Flag contains 1 this means the elapsed time is
2088 * longer than the expected delay, and we can exit the wait loop.
2090 *cs++ = MI_LOAD_REGISTER_IMM(2);
2091 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));
2092 *cs++ = lower_32_bits(delay_ticks);
2093 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;
2094 *cs++ = upper_32_bits(delay_ticks);
2097 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));
2098 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));
2099 *cs++ = MI_MATH_ADD;
2100 *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
2102 *cs++ = MI_ARB_CHECK;
2105 * Transfer the result into the predicate register to be used for the
2108 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2109 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
2110 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
2112 if (HAS_MI_SET_PREDICATE(i915))
2113 *cs++ = MI_SET_PREDICATE | 1;
2115 /* Predicate the jump. */
2116 *cs++ = (GRAPHICS_VER(i915) < 8 ?
2117 MI_BATCH_BUFFER_START :
2118 MI_BATCH_BUFFER_START_GEN8) |
2120 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
2123 if (HAS_MI_SET_PREDICATE(i915))
2124 *cs++ = MI_SET_PREDICATE;
2126 /* Restore registers. */
2127 for (i = 0; i < N_CS_GPR; i++)
2128 cs = save_restore_register(
2129 stream, cs, false /* restore */, CS_GPR(i),
2130 GPR_SAVE_OFFSET + 8 * i, 2);
2131 cs = save_restore_register(
2132 stream, cs, false /* restore */, mi_predicate_result,
2133 PREDICATE_SAVE_OFFSET, 1);
2135 /* And return to the ring. */
2136 *cs++ = MI_BATCH_BUFFER_END;
2138 GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));
2140 i915_gem_object_flush_map(bo);
2141 __i915_gem_object_release_map(bo);
2146 i915_vma_unpin_and_release(&vma, 0);
2148 if (ret == -EDEADLK) {
2149 ret = i915_gem_ww_ctx_backoff(&ww);
2153 i915_gem_ww_ctx_fini(&ww);
2155 i915_gem_object_put(bo);
2159 static u32 *write_cs_mi_lri(u32 *cs,
2160 const struct i915_oa_reg *reg_data,
2165 for (i = 0; i < n_regs; i++) {
2166 if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
2167 u32 n_lri = min_t(u32,
2169 MI_LOAD_REGISTER_IMM_MAX_REGS);
2171 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
2173 *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
2174 *cs++ = reg_data[i].value;
2180 static int num_lri_dwords(int num_regs)
2185 count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
2186 count += num_regs * 2;
2192 static struct i915_oa_config_bo *
2193 alloc_oa_config_buffer(struct i915_perf_stream *stream,
2194 struct i915_oa_config *oa_config)
2196 struct drm_i915_gem_object *obj;
2197 struct i915_oa_config_bo *oa_bo;
2198 struct i915_gem_ww_ctx ww;
2199 size_t config_length = 0;
2203 oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
2205 return ERR_PTR(-ENOMEM);
2207 config_length += num_lri_dwords(oa_config->mux_regs_len);
2208 config_length += num_lri_dwords(oa_config->b_counter_regs_len);
2209 config_length += num_lri_dwords(oa_config->flex_regs_len);
2210 config_length += 3; /* MI_BATCH_BUFFER_START */
2211 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
2213 obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
2219 i915_gem_ww_ctx_init(&ww, true);
2221 err = i915_gem_object_lock(obj, &ww);
2225 cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
2231 cs = write_cs_mi_lri(cs,
2232 oa_config->mux_regs,
2233 oa_config->mux_regs_len);
2234 cs = write_cs_mi_lri(cs,
2235 oa_config->b_counter_regs,
2236 oa_config->b_counter_regs_len);
2237 cs = write_cs_mi_lri(cs,
2238 oa_config->flex_regs,
2239 oa_config->flex_regs_len);
2241 /* Jump into the active wait. */
2242 *cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?
2243 MI_BATCH_BUFFER_START :
2244 MI_BATCH_BUFFER_START_GEN8);
2245 *cs++ = i915_ggtt_offset(stream->noa_wait);
2248 i915_gem_object_flush_map(obj);
2249 __i915_gem_object_release_map(obj);
2251 oa_bo->vma = i915_vma_instance(obj,
2252 &stream->engine->gt->ggtt->vm,
2254 if (IS_ERR(oa_bo->vma)) {
2255 err = PTR_ERR(oa_bo->vma);
2259 oa_bo->oa_config = i915_oa_config_get(oa_config);
2260 llist_add(&oa_bo->node, &stream->oa_config_bos);
2263 if (err == -EDEADLK) {
2264 err = i915_gem_ww_ctx_backoff(&ww);
2268 i915_gem_ww_ctx_fini(&ww);
2271 i915_gem_object_put(obj);
2275 return ERR_PTR(err);
2280 static struct i915_vma *
2281 get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
2283 struct i915_oa_config_bo *oa_bo;
2286 * Look for the buffer in the already allocated BOs attached
2289 llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) {
2290 if (oa_bo->oa_config == oa_config &&
2291 memcmp(oa_bo->oa_config->uuid,
2293 sizeof(oa_config->uuid)) == 0)
2297 oa_bo = alloc_oa_config_buffer(stream, oa_config);
2299 return ERR_CAST(oa_bo);
2302 return i915_vma_get(oa_bo->vma);
2306 emit_oa_config(struct i915_perf_stream *stream,
2307 struct i915_oa_config *oa_config,
2308 struct intel_context *ce,
2309 struct i915_active *active)
2311 struct i915_request *rq;
2312 struct i915_vma *vma;
2313 struct i915_gem_ww_ctx ww;
2316 vma = get_oa_vma(stream, oa_config);
2318 return PTR_ERR(vma);
2320 i915_gem_ww_ctx_init(&ww, true);
2322 err = i915_gem_object_lock(vma->obj, &ww);
2326 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
2330 intel_engine_pm_get(ce->engine);
2331 rq = i915_request_create(ce);
2332 intel_engine_pm_put(ce->engine);
2338 if (!IS_ERR_OR_NULL(active)) {
2339 /* After all individual context modifications */
2340 err = i915_request_await_active(rq, active,
2341 I915_ACTIVE_AWAIT_ACTIVE);
2343 goto err_add_request;
2345 err = i915_active_add_request(active, rq);
2347 goto err_add_request;
2350 err = i915_vma_move_to_active(vma, rq, 0);
2352 goto err_add_request;
2354 err = rq->engine->emit_bb_start(rq,
2355 i915_vma_offset(vma), 0,
2356 I915_DISPATCH_SECURE);
2358 goto err_add_request;
2361 i915_request_add(rq);
2363 i915_vma_unpin(vma);
2365 if (err == -EDEADLK) {
2366 err = i915_gem_ww_ctx_backoff(&ww);
2371 i915_gem_ww_ctx_fini(&ww);
2376 static struct intel_context *oa_context(struct i915_perf_stream *stream)
2378 return stream->pinned_ctx ?: stream->engine->kernel_context;
2382 hsw_enable_metric_set(struct i915_perf_stream *stream,
2383 struct i915_active *active)
2385 struct intel_uncore *uncore = stream->uncore;
2390 * OA unit is using “crclk” for its functionality. When trunk
2391 * level clock gating takes place, OA clock would be gated,
2392 * unable to count the events from non-render clock domain.
2393 * Render clock gating must be disabled when OA is enabled to
2394 * count the events from non-render domain. Unit level clock
2395 * gating for RCS should also be disabled.
2397 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2398 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
2399 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2400 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
2402 return emit_oa_config(stream,
2403 stream->oa_config, oa_context(stream),
2407 static void hsw_disable_metric_set(struct i915_perf_stream *stream)
2409 struct intel_uncore *uncore = stream->uncore;
2411 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2412 GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
2413 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2414 0, GEN7_DOP_CLOCK_GATE_ENABLE);
2416 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2419 static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
2422 u32 mmio = i915_mmio_reg_offset(reg);
2426 * This arbitrary default will select the 'EU FPU0 Pipeline
2427 * Active' event. In the future it's anticipated that there
2428 * will be an explicit 'No Event' we can select, but not yet...
2433 for (i = 0; i < oa_config->flex_regs_len; i++) {
2434 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2435 return oa_config->flex_regs[i].value;
2441 * NB: It must always remain pointer safe to run this even if the OA unit
2442 * has been disabled.
2444 * It's fine to put out-of-date values into these per-context registers
2445 * in the case that the OA unit has been disabled.
2448 gen8_update_reg_state_unlocked(const struct intel_context *ce,
2449 const struct i915_perf_stream *stream)
2451 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2452 u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2453 /* The MMIO offsets for Flex EU registers aren't contiguous */
2454 static const i915_reg_t flex_regs[] = {
2463 u32 *reg_state = ce->lrc_reg_state;
2466 reg_state[ctx_oactxctrl + 1] =
2467 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2468 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2469 GEN8_OA_COUNTER_RESUME;
2471 for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
2472 reg_state[ctx_flexeu0 + i * 2 + 1] =
2473 oa_config_flex_reg(stream->oa_config, flex_regs[i]);
2483 gen8_store_flex(struct i915_request *rq,
2484 struct intel_context *ce,
2485 const struct flex *flex, unsigned int count)
2490 cs = intel_ring_begin(rq, 4 * count);
2494 offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;
2496 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
2497 *cs++ = offset + flex->offset * sizeof(u32);
2499 *cs++ = flex->value;
2500 } while (flex++, --count);
2502 intel_ring_advance(rq, cs);
2508 gen8_load_flex(struct i915_request *rq,
2509 struct intel_context *ce,
2510 const struct flex *flex, unsigned int count)
2514 GEM_BUG_ON(!count || count > 63);
2516 cs = intel_ring_begin(rq, 2 * count + 2);
2520 *cs++ = MI_LOAD_REGISTER_IMM(count);
2522 *cs++ = i915_mmio_reg_offset(flex->reg);
2523 *cs++ = flex->value;
2524 } while (flex++, --count);
2527 intel_ring_advance(rq, cs);
2532 static int gen8_modify_context(struct intel_context *ce,
2533 const struct flex *flex, unsigned int count)
2535 struct i915_request *rq;
2538 rq = intel_engine_create_kernel_request(ce->engine);
2542 /* Serialise with the remote context */
2543 err = intel_context_prepare_remote_request(ce, rq);
2545 err = gen8_store_flex(rq, ce, flex, count);
2547 i915_request_add(rq);
2552 gen8_modify_self(struct intel_context *ce,
2553 const struct flex *flex, unsigned int count,
2554 struct i915_active *active)
2556 struct i915_request *rq;
2559 intel_engine_pm_get(ce->engine);
2560 rq = i915_request_create(ce);
2561 intel_engine_pm_put(ce->engine);
2565 if (!IS_ERR_OR_NULL(active)) {
2566 err = i915_active_add_request(active, rq);
2568 goto err_add_request;
2571 err = gen8_load_flex(rq, ce, flex, count);
2573 goto err_add_request;
2576 i915_request_add(rq);
2580 static int gen8_configure_context(struct i915_perf_stream *stream,
2581 struct i915_gem_context *ctx,
2582 struct flex *flex, unsigned int count)
2584 struct i915_gem_engines_iter it;
2585 struct intel_context *ce;
2588 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2589 GEM_BUG_ON(ce == ce->engine->kernel_context);
2591 if (ce->engine->class != RENDER_CLASS)
2594 /* Otherwise OA settings will be set upon first use */
2595 if (!intel_context_pin_if_active(ce))
2598 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
2599 err = gen8_modify_context(ce, flex, count);
2601 intel_context_unpin(ce);
2605 i915_gem_context_unlock_engines(ctx);
2610 static int gen12_configure_oar_context(struct i915_perf_stream *stream,
2611 struct i915_active *active)
2614 struct intel_context *ce = stream->pinned_ctx;
2615 u32 format = stream->oa_buffer.format->format;
2616 u32 offset = stream->perf->ctx_oactxctrl_offset;
2617 struct flex regs_context[] = {
2621 active ? GEN8_OA_COUNTER_RESUME : 0,
2624 /* Offsets in regs_lri are not used since this configuration is only
2625 * applied using LRI. Initialize the correct offsets for posterity.
2627 #define GEN12_OAR_OACONTROL_OFFSET 0x5B0
2628 struct flex regs_lri[] = {
2630 GEN12_OAR_OACONTROL,
2631 GEN12_OAR_OACONTROL_OFFSET + 1,
2632 (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
2633 (active ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0)
2636 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2637 CTX_CONTEXT_CONTROL,
2638 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2640 GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2645 /* Modify the context image of pinned context with regs_context */
2646 err = intel_context_lock_pinned(ce);
2650 err = gen8_modify_context(ce, regs_context,
2651 ARRAY_SIZE(regs_context));
2652 intel_context_unlock_pinned(ce);
2656 /* Apply regs_lri using LRI with pinned context */
2657 return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), active);
2661 * Manages updating the per-context aspects of the OA stream
2662 * configuration across all contexts.
2664 * The awkward consideration here is that OACTXCONTROL controls the
2665 * exponent for periodic sampling which is primarily used for system
2666 * wide profiling where we'd like a consistent sampling period even in
2667 * the face of context switches.
2669 * Our approach of updating the register state context (as opposed to
2670 * say using a workaround batch buffer) ensures that the hardware
2671 * won't automatically reload an out-of-date timer exponent even
2672 * transiently before a WA BB could be parsed.
2674 * This function needs to:
2675 * - Ensure the currently running context's per-context OA state is
2677 * - Ensure that all existing contexts will have the correct per-context
2678 * OA state if they are scheduled for use.
2679 * - Ensure any new contexts will be initialized with the correct
2680 * per-context OA state.
2682 * Note: it's only the RCS/Render context that has any OA state.
2683 * Note: the first flex register passed must always be R_PWR_CLK_STATE
2686 oa_configure_all_contexts(struct i915_perf_stream *stream,
2689 struct i915_active *active)
2691 struct drm_i915_private *i915 = stream->perf->i915;
2692 struct intel_engine_cs *engine;
2693 struct intel_gt *gt = stream->engine->gt;
2694 struct i915_gem_context *ctx, *cn;
2697 lockdep_assert_held(>->perf.lock);
2700 * The OA register config is setup through the context image. This image
2701 * might be written to by the GPU on context switch (in particular on
2702 * lite-restore). This means we can't safely update a context's image,
2703 * if this context is scheduled/submitted to run on the GPU.
2705 * We could emit the OA register config through the batch buffer but
2706 * this might leave small interval of time where the OA unit is
2707 * configured at an invalid sampling period.
2709 * Note that since we emit all requests from a single ring, there
2710 * is still an implicit global barrier here that may cause a high
2711 * priority context to wait for an otherwise independent low priority
2712 * context. Contexts idle at the time of reconfiguration are not
2713 * trapped behind the barrier.
2715 spin_lock(&i915->gem.contexts.lock);
2716 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
2717 if (!kref_get_unless_zero(&ctx->ref))
2720 spin_unlock(&i915->gem.contexts.lock);
2722 err = gen8_configure_context(stream, ctx, regs, num_regs);
2724 i915_gem_context_put(ctx);
2728 spin_lock(&i915->gem.contexts.lock);
2729 list_safe_reset_next(ctx, cn, link);
2730 i915_gem_context_put(ctx);
2732 spin_unlock(&i915->gem.contexts.lock);
2735 * After updating all other contexts, we need to modify ourselves.
2736 * If we don't modify the kernel_context, we do not get events while
2739 for_each_uabi_engine(engine, i915) {
2740 struct intel_context *ce = engine->kernel_context;
2742 if (engine->class != RENDER_CLASS)
2745 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
2747 err = gen8_modify_self(ce, regs, num_regs, active);
2756 gen12_configure_all_contexts(struct i915_perf_stream *stream,
2757 const struct i915_oa_config *oa_config,
2758 struct i915_active *active)
2760 struct flex regs[] = {
2762 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2763 CTX_R_PWR_CLK_STATE,
2767 if (stream->engine->class != RENDER_CLASS)
2770 return oa_configure_all_contexts(stream,
2771 regs, ARRAY_SIZE(regs),
2776 lrc_configure_all_contexts(struct i915_perf_stream *stream,
2777 const struct i915_oa_config *oa_config,
2778 struct i915_active *active)
2780 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2781 /* The MMIO offsets for Flex EU registers aren't contiguous */
2782 const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2783 #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
2784 struct flex regs[] = {
2786 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2787 CTX_R_PWR_CLK_STATE,
2793 { EU_PERF_CNTL0, ctx_flexeuN(0) },
2794 { EU_PERF_CNTL1, ctx_flexeuN(1) },
2795 { EU_PERF_CNTL2, ctx_flexeuN(2) },
2796 { EU_PERF_CNTL3, ctx_flexeuN(3) },
2797 { EU_PERF_CNTL4, ctx_flexeuN(4) },
2798 { EU_PERF_CNTL5, ctx_flexeuN(5) },
2799 { EU_PERF_CNTL6, ctx_flexeuN(6) },
2805 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2806 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2807 GEN8_OA_COUNTER_RESUME;
2809 for (i = 2; i < ARRAY_SIZE(regs); i++)
2810 regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
2812 return oa_configure_all_contexts(stream,
2813 regs, ARRAY_SIZE(regs),
2818 gen8_enable_metric_set(struct i915_perf_stream *stream,
2819 struct i915_active *active)
2821 struct intel_uncore *uncore = stream->uncore;
2822 struct i915_oa_config *oa_config = stream->oa_config;
2826 * We disable slice/unslice clock ratio change reports on SKL since
2827 * they are too noisy. The HW generates a lot of redundant reports
2828 * where the ratio hasn't really changed causing a lot of redundant
2829 * work to processes and increasing the chances we'll hit buffer
2832 * Although we don't currently use the 'disable overrun' OABUFFER
2833 * feature it's worth noting that clock ratio reports have to be
2834 * disabled before considering to use that feature since the HW doesn't
2835 * correctly block these reports.
2837 * Currently none of the high-level metrics we have depend on knowing
2838 * this ratio to normalize.
2840 * Note: This register is not power context saved and restored, but
2841 * that's OK considering that we disable RC6 while the OA unit is
2844 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
2845 * be read back from automatically triggered reports, as part of the
2848 if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
2849 intel_uncore_write(uncore, GEN8_OA_DEBUG,
2850 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2851 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2855 * Update all contexts prior writing the mux configurations as we need
2856 * to make sure all slices/subslices are ON before writing to NOA
2859 ret = lrc_configure_all_contexts(stream, oa_config, active);
2863 return emit_oa_config(stream,
2864 stream->oa_config, oa_context(stream),
2868 static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2870 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2871 (stream->sample_flags & SAMPLE_OA_REPORT) ?
2872 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2876 gen12_enable_metric_set(struct i915_perf_stream *stream,
2877 struct i915_active *active)
2879 struct drm_i915_private *i915 = stream->perf->i915;
2880 struct intel_uncore *uncore = stream->uncore;
2881 struct i915_oa_config *oa_config = stream->oa_config;
2882 bool periodic = stream->periodic;
2883 u32 period_exponent = stream->period_exponent;
2888 * Wa_1508761755:xehpsdv, dg2
2889 * EU NOA signals behave incorrectly if EU clock gating is enabled.
2890 * Disable thread stall DOP gating and EU DOP gating.
2892 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2893 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2894 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
2895 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2896 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
2899 intel_uncore_write(uncore, __oa_regs(stream)->oa_debug,
2900 /* Disable clk ratio reports, like previous Gens. */
2901 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2902 GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2904 * If the user didn't require OA reports, instruct
2905 * the hardware not to emit ctx switch reports.
2907 oag_report_ctx_switches(stream));
2909 intel_uncore_write(uncore, __oa_regs(stream)->oa_ctx_ctrl, periodic ?
2910 (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
2911 GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
2912 (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
2916 * Initialize Super Queue Internal Cnt Register
2917 * Set PMON Enable in order to collect valid metrics.
2918 * Enable byets per clock reporting in OA for XEHPSDV onward.
2920 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
2921 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
2923 intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
2926 * Update all contexts prior writing the mux configurations as we need
2927 * to make sure all slices/subslices are ON before writing to NOA
2930 ret = gen12_configure_all_contexts(stream, oa_config, active);
2935 * For Gen12, performance counters are context
2936 * saved/restored. Only enable it for the context that
2940 ret = gen12_configure_oar_context(stream, active);
2945 return emit_oa_config(stream,
2946 stream->oa_config, oa_context(stream),
2950 static void gen8_disable_metric_set(struct i915_perf_stream *stream)
2952 struct intel_uncore *uncore = stream->uncore;
2954 /* Reset all contexts' slices/subslices configurations. */
2955 lrc_configure_all_contexts(stream, NULL, NULL);
2957 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2960 static void gen11_disable_metric_set(struct i915_perf_stream *stream)
2962 struct intel_uncore *uncore = stream->uncore;
2964 /* Reset all contexts' slices/subslices configurations. */
2965 lrc_configure_all_contexts(stream, NULL, NULL);
2967 /* Make sure we disable noa to save power. */
2968 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2971 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
2973 struct intel_uncore *uncore = stream->uncore;
2974 struct drm_i915_private *i915 = stream->perf->i915;
2978 * Wa_1508761755:xehpsdv, dg2
2979 * Enable thread stall DOP gating and EU DOP gating.
2981 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2982 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2983 _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
2984 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2985 _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
2988 /* Reset all contexts' slices/subslices configurations. */
2989 gen12_configure_all_contexts(stream, NULL, NULL);
2991 /* disable the context save/restore or OAR counters */
2993 gen12_configure_oar_context(stream, NULL);
2995 /* Make sure we disable noa to save power. */
2996 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2998 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
2999 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
3001 /* Reset PMON Enable to save power. */
3002 intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
3005 static void gen7_oa_enable(struct i915_perf_stream *stream)
3007 struct intel_uncore *uncore = stream->uncore;
3008 struct i915_gem_context *ctx = stream->ctx;
3009 u32 ctx_id = stream->specific_ctx_id;
3010 bool periodic = stream->periodic;
3011 u32 period_exponent = stream->period_exponent;
3012 u32 report_format = stream->oa_buffer.format->format;
3015 * Reset buf pointers so we don't forward reports from before now.
3017 * Think carefully if considering trying to avoid this, since it
3018 * also ensures status flags and the buffer itself are cleared
3019 * in error paths, and we have checks for invalid reports based
3020 * on the assumption that certain fields are written to zeroed
3021 * memory which this helps maintains.
3023 gen7_init_oa_buffer(stream);
3025 intel_uncore_write(uncore, GEN7_OACONTROL,
3026 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
3028 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
3029 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
3030 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
3031 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
3032 GEN7_OACONTROL_ENABLE);
3035 static void gen8_oa_enable(struct i915_perf_stream *stream)
3037 struct intel_uncore *uncore = stream->uncore;
3038 u32 report_format = stream->oa_buffer.format->format;
3041 * Reset buf pointers so we don't forward reports from before now.
3043 * Think carefully if considering trying to avoid this, since it
3044 * also ensures status flags and the buffer itself are cleared
3045 * in error paths, and we have checks for invalid reports based
3046 * on the assumption that certain fields are written to zeroed
3047 * memory which this helps maintains.
3049 gen8_init_oa_buffer(stream);
3052 * Note: we don't rely on the hardware to perform single context
3053 * filtering and instead filter on the cpu based on the context-id
3056 intel_uncore_write(uncore, GEN8_OACONTROL,
3057 (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) |
3058 GEN8_OA_COUNTER_ENABLE);
3061 static void gen12_oa_enable(struct i915_perf_stream *stream)
3063 const struct i915_perf_regs *regs;
3067 * If we don't want OA reports from the OA buffer, then we don't even
3068 * need to program the OAG unit.
3070 if (!(stream->sample_flags & SAMPLE_OA_REPORT))
3073 gen12_init_oa_buffer(stream);
3075 regs = __oa_regs(stream);
3076 val = (stream->oa_buffer.format->format << regs->oa_ctrl_counter_format_shift) |
3077 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE;
3079 intel_uncore_write(stream->uncore, regs->oa_ctrl, val);
3083 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
3084 * @stream: An i915 perf stream opened for OA metrics
3086 * [Re]enables hardware periodic sampling according to the period configured
3087 * when opening the stream. This also starts a hrtimer that will periodically
3088 * check for data in the circular OA buffer for notifying userspace (e.g.
3089 * during a read() or poll()).
3091 static void i915_oa_stream_enable(struct i915_perf_stream *stream)
3093 stream->pollin = false;
3095 stream->perf->ops.oa_enable(stream);
3097 if (stream->sample_flags & SAMPLE_OA_REPORT)
3098 hrtimer_start(&stream->poll_check_timer,
3099 ns_to_ktime(stream->poll_oa_period),
3100 HRTIMER_MODE_REL_PINNED);
3103 static void gen7_oa_disable(struct i915_perf_stream *stream)
3105 struct intel_uncore *uncore = stream->uncore;
3107 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
3108 if (intel_wait_for_register(uncore,
3109 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
3111 drm_err(&stream->perf->i915->drm,
3112 "wait for OA to be disabled timed out\n");
3115 static void gen8_oa_disable(struct i915_perf_stream *stream)
3117 struct intel_uncore *uncore = stream->uncore;
3119 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
3120 if (intel_wait_for_register(uncore,
3121 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
3123 drm_err(&stream->perf->i915->drm,
3124 "wait for OA to be disabled timed out\n");
3127 static void gen12_oa_disable(struct i915_perf_stream *stream)
3129 struct intel_uncore *uncore = stream->uncore;
3131 intel_uncore_write(uncore, __oa_regs(stream)->oa_ctrl, 0);
3132 if (intel_wait_for_register(uncore,
3133 __oa_regs(stream)->oa_ctrl,
3134 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
3136 drm_err(&stream->perf->i915->drm,
3137 "wait for OA to be disabled timed out\n");
3139 intel_uncore_write(uncore, GEN12_OA_TLB_INV_CR, 1);
3140 if (intel_wait_for_register(uncore,
3141 GEN12_OA_TLB_INV_CR,
3144 drm_err(&stream->perf->i915->drm,
3145 "wait for OA tlb invalidate timed out\n");
3149 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
3150 * @stream: An i915 perf stream opened for OA metrics
3152 * Stops the OA unit from periodically writing counter reports into the
3153 * circular OA buffer. This also stops the hrtimer that periodically checks for
3154 * data in the circular OA buffer, for notifying userspace.
3156 static void i915_oa_stream_disable(struct i915_perf_stream *stream)
3158 stream->perf->ops.oa_disable(stream);
3160 if (stream->sample_flags & SAMPLE_OA_REPORT)
3161 hrtimer_cancel(&stream->poll_check_timer);
3164 static const struct i915_perf_stream_ops i915_oa_stream_ops = {
3165 .destroy = i915_oa_stream_destroy,
3166 .enable = i915_oa_stream_enable,
3167 .disable = i915_oa_stream_disable,
3168 .wait_unlocked = i915_oa_wait_unlocked,
3169 .poll_wait = i915_oa_poll_wait,
3170 .read = i915_oa_read,
3173 static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
3175 struct i915_active *active;
3178 active = i915_active_create();
3182 err = stream->perf->ops.enable_metric_set(stream, active);
3184 __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
3186 i915_active_put(active);
3191 get_default_sseu_config(struct intel_sseu *out_sseu,
3192 struct intel_engine_cs *engine)
3194 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
3196 *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
3198 if (GRAPHICS_VER(engine->i915) == 11) {
3200 * We only need subslice count so it doesn't matter which ones
3201 * we select - just turn off low bits in the amount of half of
3202 * all available subslices per slice.
3204 out_sseu->subslice_mask =
3205 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
3206 out_sseu->slice_mask = 0x1;
3211 get_sseu_config(struct intel_sseu *out_sseu,
3212 struct intel_engine_cs *engine,
3213 const struct drm_i915_gem_context_param_sseu *drm_sseu)
3215 if (drm_sseu->engine.engine_class != engine->uabi_class ||
3216 drm_sseu->engine.engine_instance != engine->uabi_instance)
3219 return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
3223 * OA timestamp frequency = CS timestamp frequency in most platforms. On some
3224 * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
3225 * cases, return the adjusted CS timestamp frequency to the user.
3227 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
3230 * Wa_18013179988:dg2
3231 * Wa_14015846243:mtl
3233 if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
3234 intel_wakeref_t wakeref;
3237 with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
3238 reg = intel_uncore_read(to_gt(i915)->uncore, RPM_CONFIG0);
3240 shift = REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
3243 return to_gt(i915)->clock_frequency << (3 - shift);
3246 return to_gt(i915)->clock_frequency;
3250 * i915_oa_stream_init - validate combined props for OA stream and init
3251 * @stream: An i915 perf stream
3252 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
3253 * @props: The property state that configures stream (individually validated)
3255 * While read_properties_unlocked() validates properties in isolation it
3256 * doesn't ensure that the combination necessarily makes sense.
3258 * At this point it has been determined that userspace wants a stream of
3259 * OA metrics, but still we need to further validate the combined
3260 * properties are OK.
3262 * If the configuration makes sense then we can allocate memory for
3263 * a circular OA buffer and apply the requested metric set configuration.
3265 * Returns: zero on success or a negative error code.
3267 static int i915_oa_stream_init(struct i915_perf_stream *stream,
3268 struct drm_i915_perf_open_param *param,
3269 struct perf_open_properties *props)
3271 struct drm_i915_private *i915 = stream->perf->i915;
3272 struct i915_perf *perf = stream->perf;
3273 struct i915_perf_group *g;
3274 struct intel_gt *gt;
3277 if (!props->engine) {
3278 drm_dbg(&stream->perf->i915->drm,
3279 "OA engine not specified\n");
3282 gt = props->engine->gt;
3283 g = props->engine->oa_group;
3286 * If the sysfs metrics/ directory wasn't registered for some
3287 * reason then don't let userspace try their luck with config
3290 if (!perf->metrics_kobj) {
3291 drm_dbg(&stream->perf->i915->drm,
3292 "OA metrics weren't advertised via sysfs\n");
3296 if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
3297 (GRAPHICS_VER(perf->i915) < 12 || !stream->ctx)) {
3298 drm_dbg(&stream->perf->i915->drm,
3299 "Only OA report sampling supported\n");
3303 if (!perf->ops.enable_metric_set) {
3304 drm_dbg(&stream->perf->i915->drm,
3305 "OA unit not supported\n");
3310 * To avoid the complexity of having to accurately filter
3311 * counter reports and marshal to the appropriate client
3312 * we currently only allow exclusive access
3314 if (g->exclusive_stream) {
3315 drm_dbg(&stream->perf->i915->drm,
3316 "OA unit already in use\n");
3320 if (!props->oa_format) {
3321 drm_dbg(&stream->perf->i915->drm,
3322 "OA report format not specified\n");
3326 stream->engine = props->engine;
3327 stream->uncore = stream->engine->gt->uncore;
3329 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
3331 stream->oa_buffer.format = &perf->oa_formats[props->oa_format];
3332 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format->size == 0))
3335 stream->sample_flags = props->sample_flags;
3336 stream->sample_size += stream->oa_buffer.format->size;
3338 stream->hold_preemption = props->hold_preemption;
3340 stream->periodic = props->oa_periodic;
3341 if (stream->periodic)
3342 stream->period_exponent = props->oa_period_exponent;
3345 ret = oa_get_render_ctx_id(stream);
3347 drm_dbg(&stream->perf->i915->drm,
3348 "Invalid context id to filter with\n");
3353 ret = alloc_noa_wait(stream);
3355 drm_dbg(&stream->perf->i915->drm,
3356 "Unable to allocate NOA wait batch buffer\n");
3357 goto err_noa_wait_alloc;
3360 stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set);
3361 if (!stream->oa_config) {
3362 drm_dbg(&stream->perf->i915->drm,
3363 "Invalid OA config id=%i\n", props->metrics_set);
3368 /* PRM - observability performance counters:
3370 * OACONTROL, performance counter enable, note:
3372 * "When this bit is set, in order to have coherent counts,
3373 * RC6 power state and trunk clock gating must be disabled.
3374 * This can be achieved by programming MMIO registers as
3375 * 0xA094=0 and 0xA090[31]=1"
3377 * In our case we are expecting that taking pm + FORCEWAKE
3378 * references will effectively disable RC6.
3380 intel_engine_pm_get(stream->engine);
3381 intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
3384 * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes
3385 * OA to lose the configuration state. Prevent this by overriding GUCRC
3388 if (intel_uc_uses_guc_rc(>->uc) &&
3389 (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
3390 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {
3391 ret = intel_guc_slpc_override_gucrc_mode(>->uc.guc.slpc,
3392 SLPC_GUCRC_MODE_GUCRC_NO_RC6);
3394 drm_dbg(&stream->perf->i915->drm,
3395 "Unable to override gucrc mode\n");
3399 stream->override_gucrc = true;
3402 ret = alloc_oa_buffer(stream);
3404 goto err_oa_buf_alloc;
3406 stream->ops = &i915_oa_stream_ops;
3408 stream->engine->gt->perf.sseu = props->sseu;
3409 WRITE_ONCE(g->exclusive_stream, stream);
3411 ret = i915_perf_stream_enable_sync(stream);
3413 drm_dbg(&stream->perf->i915->drm,
3414 "Unable to enable metric set\n");
3418 drm_dbg(&stream->perf->i915->drm,
3419 "opening stream oa config uuid=%s\n",
3420 stream->oa_config->uuid);
3422 hrtimer_init(&stream->poll_check_timer,
3423 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3424 stream->poll_check_timer.function = oa_poll_check_timer_cb;
3425 init_waitqueue_head(&stream->poll_wq);
3426 spin_lock_init(&stream->oa_buffer.ptr_lock);
3427 mutex_init(&stream->lock);
3432 WRITE_ONCE(g->exclusive_stream, NULL);
3433 perf->ops.disable_metric_set(stream);
3435 free_oa_buffer(stream);
3438 if (stream->override_gucrc)
3439 intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc);
3442 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
3443 intel_engine_pm_put(stream->engine);
3445 free_oa_configs(stream);
3448 free_noa_wait(stream);
3452 oa_put_render_ctx_id(stream);
3457 void i915_oa_init_reg_state(const struct intel_context *ce,
3458 const struct intel_engine_cs *engine)
3460 struct i915_perf_stream *stream;
3462 if (engine->class != RENDER_CLASS)
3465 /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
3466 stream = READ_ONCE(engine->oa_group->exclusive_stream);
3467 if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
3468 gen8_update_reg_state_unlocked(ce, stream);
3472 * i915_perf_read - handles read() FOP for i915 perf stream FDs
3473 * @file: An i915 perf stream file
3474 * @buf: destination buffer given by userspace
3475 * @count: the number of bytes userspace wants to read
3476 * @ppos: (inout) file seek position (unused)
3478 * The entry point for handling a read() on a stream file descriptor from
3479 * userspace. Most of the work is left to the i915_perf_read_locked() and
3480 * &i915_perf_stream_ops->read but to save having stream implementations (of
3481 * which we might have multiple later) we handle blocking read here.
3483 * We can also consistently treat trying to read from a disabled stream
3484 * as an IO error so implementations can assume the stream is enabled
3487 * Returns: The number of bytes copied or a negative error code on failure.
3489 static ssize_t i915_perf_read(struct file *file,
3494 struct i915_perf_stream *stream = file->private_data;
3498 /* To ensure it's handled consistently we simply treat all reads of a
3499 * disabled stream as an error. In particular it might otherwise lead
3500 * to a deadlock for blocking file descriptors...
3502 if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
3505 if (!(file->f_flags & O_NONBLOCK)) {
3506 /* There's the small chance of false positives from
3507 * stream->ops->wait_unlocked.
3509 * E.g. with single context filtering since we only wait until
3510 * oabuffer has >= 1 report we don't immediately know whether
3511 * any reports really belong to the current context
3514 ret = stream->ops->wait_unlocked(stream);
3518 mutex_lock(&stream->lock);
3519 ret = stream->ops->read(stream, buf, count, &offset);
3520 mutex_unlock(&stream->lock);
3521 } while (!offset && !ret);
3523 mutex_lock(&stream->lock);
3524 ret = stream->ops->read(stream, buf, count, &offset);
3525 mutex_unlock(&stream->lock);
3528 /* We allow the poll checking to sometimes report false positive EPOLLIN
3529 * events where we might actually report EAGAIN on read() if there's
3530 * not really any data available. In this situation though we don't
3531 * want to enter a busy loop between poll() reporting a EPOLLIN event
3532 * and read() returning -EAGAIN. Clearing the oa.pollin state here
3533 * effectively ensures we back off until the next hrtimer callback
3534 * before reporting another EPOLLIN event.
3535 * The exception to this is if ops->read() returned -ENOSPC which means
3536 * that more OA data is available than could fit in the user provided
3537 * buffer. In this case we want the next poll() call to not block.
3540 stream->pollin = false;
3542 /* Possible values for ret are 0, -EFAULT, -ENOSPC, -EIO, ... */
3543 return offset ?: (ret ?: -EAGAIN);
3546 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
3548 struct i915_perf_stream *stream =
3549 container_of(hrtimer, typeof(*stream), poll_check_timer);
3551 if (oa_buffer_check_unlocked(stream)) {
3552 stream->pollin = true;
3553 wake_up(&stream->poll_wq);
3556 hrtimer_forward_now(hrtimer,
3557 ns_to_ktime(stream->poll_oa_period));
3559 return HRTIMER_RESTART;
3563 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
3564 * @stream: An i915 perf stream
3565 * @file: An i915 perf stream file
3566 * @wait: poll() state table
3568 * For handling userspace polling on an i915 perf stream, this calls through to
3569 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
3570 * will be woken for new stream data.
3572 * Returns: any poll events that are ready without sleeping
3574 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
3578 __poll_t events = 0;
3580 stream->ops->poll_wait(stream, file, wait);
3582 /* Note: we don't explicitly check whether there's something to read
3583 * here since this path may be very hot depending on what else
3584 * userspace is polling, or on the timeout in use. We rely solely on
3585 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
3595 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
3596 * @file: An i915 perf stream file
3597 * @wait: poll() state table
3599 * For handling userspace polling on an i915 perf stream, this ensures
3600 * poll_wait() gets called with a wait queue that will be woken for new stream
3603 * Note: Implementation deferred to i915_perf_poll_locked()
3605 * Returns: any poll events that are ready without sleeping
3607 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
3609 struct i915_perf_stream *stream = file->private_data;
3612 mutex_lock(&stream->lock);
3613 ret = i915_perf_poll_locked(stream, file, wait);
3614 mutex_unlock(&stream->lock);
3620 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
3621 * @stream: A disabled i915 perf stream
3623 * [Re]enables the associated capture of data for this stream.
3625 * If a stream was previously enabled then there's currently no intention
3626 * to provide userspace any guarantee about the preservation of previously
3629 static void i915_perf_enable_locked(struct i915_perf_stream *stream)
3631 if (stream->enabled)
3634 /* Allow stream->ops->enable() to refer to this */
3635 stream->enabled = true;
3637 if (stream->ops->enable)
3638 stream->ops->enable(stream);
3640 if (stream->hold_preemption)
3641 intel_context_set_nopreempt(stream->pinned_ctx);
3645 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
3646 * @stream: An enabled i915 perf stream
3648 * Disables the associated capture of data for this stream.
3650 * The intention is that disabling an re-enabling a stream will ideally be
3651 * cheaper than destroying and re-opening a stream with the same configuration,
3652 * though there are no formal guarantees about what state or buffered data
3653 * must be retained between disabling and re-enabling a stream.
3655 * Note: while a stream is disabled it's considered an error for userspace
3656 * to attempt to read from the stream (-EIO).
3658 static void i915_perf_disable_locked(struct i915_perf_stream *stream)
3660 if (!stream->enabled)
3663 /* Allow stream->ops->disable() to refer to this */
3664 stream->enabled = false;
3666 if (stream->hold_preemption)
3667 intel_context_clear_nopreempt(stream->pinned_ctx);
3669 if (stream->ops->disable)
3670 stream->ops->disable(stream);
3673 static long i915_perf_config_locked(struct i915_perf_stream *stream,
3674 unsigned long metrics_set)
3676 struct i915_oa_config *config;
3677 long ret = stream->oa_config->id;
3679 config = i915_perf_get_oa_config(stream->perf, metrics_set);
3683 if (config != stream->oa_config) {
3687 * If OA is bound to a specific context, emit the
3688 * reconfiguration inline from that context. The update
3689 * will then be ordered with respect to submission on that
3692 * When set globally, we use a low priority kernel context,
3693 * so it will effectively take effect when idle.
3695 err = emit_oa_config(stream, config, oa_context(stream), NULL);
3697 config = xchg(&stream->oa_config, config);
3702 i915_oa_config_put(config);
3708 * i915_perf_ioctl_locked - support ioctl() usage with i915 perf stream FDs
3709 * @stream: An i915 perf stream
3710 * @cmd: the ioctl request
3711 * @arg: the ioctl data
3713 * Returns: zero on success or a negative error code. Returns -EINVAL for
3714 * an unknown ioctl request.
3716 static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
3721 case I915_PERF_IOCTL_ENABLE:
3722 i915_perf_enable_locked(stream);
3724 case I915_PERF_IOCTL_DISABLE:
3725 i915_perf_disable_locked(stream);
3727 case I915_PERF_IOCTL_CONFIG:
3728 return i915_perf_config_locked(stream, arg);
3735 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3736 * @file: An i915 perf stream file
3737 * @cmd: the ioctl request
3738 * @arg: the ioctl data
3740 * Implementation deferred to i915_perf_ioctl_locked().
3742 * Returns: zero on success or a negative error code. Returns -EINVAL for
3743 * an unknown ioctl request.
3745 static long i915_perf_ioctl(struct file *file,
3749 struct i915_perf_stream *stream = file->private_data;
3752 mutex_lock(&stream->lock);
3753 ret = i915_perf_ioctl_locked(stream, cmd, arg);
3754 mutex_unlock(&stream->lock);
3760 * i915_perf_destroy_locked - destroy an i915 perf stream
3761 * @stream: An i915 perf stream
3763 * Frees all resources associated with the given i915 perf @stream, disabling
3764 * any associated data capture in the process.
3766 * Note: The >->perf.lock mutex has been taken to serialize
3767 * with any non-file-operation driver hooks.
3769 static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
3771 if (stream->enabled)
3772 i915_perf_disable_locked(stream);
3774 if (stream->ops->destroy)
3775 stream->ops->destroy(stream);
3778 i915_gem_context_put(stream->ctx);
3784 * i915_perf_release - handles userspace close() of a stream file
3785 * @inode: anonymous inode associated with file
3786 * @file: An i915 perf stream file
3788 * Cleans up any resources associated with an open i915 perf stream file.
3790 * NB: close() can't really fail from the userspace point of view.
3792 * Returns: zero on success or a negative error code.
3794 static int i915_perf_release(struct inode *inode, struct file *file)
3796 struct i915_perf_stream *stream = file->private_data;
3797 struct i915_perf *perf = stream->perf;
3798 struct intel_gt *gt = stream->engine->gt;
3801 * Within this call, we know that the fd is being closed and we have no
3802 * other user of stream->lock. Use the perf lock to destroy the stream
3805 mutex_lock(>->perf.lock);
3806 i915_perf_destroy_locked(stream);
3807 mutex_unlock(>->perf.lock);
3809 /* Release the reference the perf stream kept on the driver. */
3810 drm_dev_put(&perf->i915->drm);
3816 static const struct file_operations fops = {
3817 .owner = THIS_MODULE,
3818 .llseek = no_llseek,
3819 .release = i915_perf_release,
3820 .poll = i915_perf_poll,
3821 .read = i915_perf_read,
3822 .unlocked_ioctl = i915_perf_ioctl,
3823 /* Our ioctl have no arguments, so it's safe to use the same function
3824 * to handle 32bits compatibility.
3826 .compat_ioctl = i915_perf_ioctl,
3831 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
3832 * @perf: i915 perf instance
3833 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
3834 * @props: individually validated u64 property value pairs
3837 * See i915_perf_ioctl_open() for interface details.
3839 * Implements further stream config validation and stream initialization on
3840 * behalf of i915_perf_open_ioctl() with the >->perf.lock mutex
3841 * taken to serialize with any non-file-operation driver hooks.
3843 * Note: at this point the @props have only been validated in isolation and
3844 * it's still necessary to validate that the combination of properties makes
3847 * In the case where userspace is interested in OA unit metrics then further
3848 * config validation and stream initialization details will be handled by
3849 * i915_oa_stream_init(). The code here should only validate config state that
3850 * will be relevant to all stream types / backends.
3852 * Returns: zero on success or a negative error code.
3855 i915_perf_open_ioctl_locked(struct i915_perf *perf,
3856 struct drm_i915_perf_open_param *param,
3857 struct perf_open_properties *props,
3858 struct drm_file *file)
3860 struct i915_gem_context *specific_ctx = NULL;
3861 struct i915_perf_stream *stream = NULL;
3862 unsigned long f_flags = 0;
3863 bool privileged_op = true;
3867 if (props->single_context) {
3868 u32 ctx_handle = props->ctx_handle;
3869 struct drm_i915_file_private *file_priv = file->driver_priv;
3871 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
3872 if (IS_ERR(specific_ctx)) {
3873 drm_dbg(&perf->i915->drm,
3874 "Failed to look up context with ID %u for opening perf stream\n",
3876 ret = PTR_ERR(specific_ctx);
3882 * On Haswell the OA unit supports clock gating off for a specific
3883 * context and in this mode there's no visibility of metrics for the
3884 * rest of the system, which we consider acceptable for a
3885 * non-privileged client.
3887 * For Gen8->11 the OA unit no longer supports clock gating off for a
3888 * specific context and the kernel can't securely stop the counters
3889 * from updating as system-wide / global values. Even though we can
3890 * filter reports based on the included context ID we can't block
3891 * clients from seeing the raw / global counter values via
3892 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
3893 * enable the OA unit by default.
3895 * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
3896 * per context basis. So we can relax requirements there if the user
3897 * doesn't request global stream access (i.e. query based sampling
3898 * using MI_RECORD_PERF_COUNT.
3900 if (IS_HASWELL(perf->i915) && specific_ctx)
3901 privileged_op = false;
3902 else if (GRAPHICS_VER(perf->i915) == 12 && specific_ctx &&
3903 (props->sample_flags & SAMPLE_OA_REPORT) == 0)
3904 privileged_op = false;
3906 if (props->hold_preemption) {
3907 if (!props->single_context) {
3908 drm_dbg(&perf->i915->drm,
3909 "preemption disable with no context\n");
3913 privileged_op = true;
3917 * Asking for SSEU configuration is a priviliged operation.
3919 if (props->has_sseu)
3920 privileged_op = true;
3922 get_default_sseu_config(&props->sseu, props->engine);
3924 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
3925 * we check a dev.i915.perf_stream_paranoid sysctl option
3926 * to determine if it's ok to access system wide OA counters
3927 * without CAP_PERFMON or CAP_SYS_ADMIN privileges.
3929 if (privileged_op &&
3930 i915_perf_stream_paranoid && !perfmon_capable()) {
3931 drm_dbg(&perf->i915->drm,
3932 "Insufficient privileges to open i915 perf stream\n");
3937 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
3943 stream->perf = perf;
3944 stream->ctx = specific_ctx;
3945 stream->poll_oa_period = props->poll_oa_period;
3947 ret = i915_oa_stream_init(stream, param, props);
3951 /* we avoid simply assigning stream->sample_flags = props->sample_flags
3952 * to have _stream_init check the combination of sample flags more
3953 * thoroughly, but still this is the expected result at this point.
3955 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
3960 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
3961 f_flags |= O_CLOEXEC;
3962 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
3963 f_flags |= O_NONBLOCK;
3965 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
3966 if (stream_fd < 0) {
3971 if (!(param->flags & I915_PERF_FLAG_DISABLED))
3972 i915_perf_enable_locked(stream);
3974 /* Take a reference on the driver that will be kept with stream_fd
3975 * until its release.
3977 drm_dev_get(&perf->i915->drm);
3982 if (stream->ops->destroy)
3983 stream->ops->destroy(stream);
3988 i915_gem_context_put(specific_ctx);
3993 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
3995 u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
3996 u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
3998 return div_u64(nom + den - 1, den);
4001 static __always_inline bool
4002 oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
4004 return test_bit(format, perf->format_mask);
4007 static __always_inline void
4008 oa_format_add(struct i915_perf *perf, enum drm_i915_oa_format format)
4010 __set_bit(format, perf->format_mask);
4014 * read_properties_unlocked - validate + copy userspace stream open properties
4015 * @perf: i915 perf instance
4016 * @uprops: The array of u64 key value pairs given by userspace
4017 * @n_props: The number of key value pairs expected in @uprops
4018 * @props: The stream configuration built up while validating properties
4020 * Note this function only validates properties in isolation it doesn't
4021 * validate that the combination of properties makes sense or that all
4022 * properties necessary for a particular kind of stream have been set.
4024 * Note that there currently aren't any ordering requirements for properties so
4025 * we shouldn't validate or assume anything about ordering here. This doesn't
4026 * rule out defining new properties with ordering requirements in the future.
4028 static int read_properties_unlocked(struct i915_perf *perf,
4031 struct perf_open_properties *props)
4033 struct drm_i915_gem_context_param_sseu user_sseu;
4034 const struct i915_oa_format *f;
4035 u64 __user *uprop = uprops;
4036 bool config_instance = false;
4037 bool config_class = false;
4038 bool config_sseu = false;
4043 memset(props, 0, sizeof(struct perf_open_properties));
4044 props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
4046 /* Considering that ID = 0 is reserved and assuming that we don't
4047 * (currently) expect any configurations to ever specify duplicate
4048 * values for a particular property ID then the last _PROP_MAX value is
4049 * one greater than the maximum number of properties we expect to get
4052 if (!n_props || n_props >= DRM_I915_PERF_PROP_MAX) {
4053 drm_dbg(&perf->i915->drm,
4054 "Invalid number of i915 perf properties given\n");
4058 /* Defaults when class:instance is not passed */
4059 class = I915_ENGINE_CLASS_RENDER;
4062 for (i = 0; i < n_props; i++) {
4063 u64 oa_period, oa_freq_hz;
4066 ret = get_user(id, uprop);
4070 ret = get_user(value, uprop + 1);
4074 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
4075 drm_dbg(&perf->i915->drm,
4076 "Unknown i915 perf property ID\n");
4080 switch ((enum drm_i915_perf_property_id)id) {
4081 case DRM_I915_PERF_PROP_CTX_HANDLE:
4082 props->single_context = 1;
4083 props->ctx_handle = value;
4085 case DRM_I915_PERF_PROP_SAMPLE_OA:
4087 props->sample_flags |= SAMPLE_OA_REPORT;
4089 case DRM_I915_PERF_PROP_OA_METRICS_SET:
4091 drm_dbg(&perf->i915->drm,
4092 "Unknown OA metric set ID\n");
4095 props->metrics_set = value;
4097 case DRM_I915_PERF_PROP_OA_FORMAT:
4098 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
4099 drm_dbg(&perf->i915->drm,
4100 "Out-of-range OA report format %llu\n",
4104 if (!oa_format_valid(perf, value)) {
4105 drm_dbg(&perf->i915->drm,
4106 "Unsupported OA report format %llu\n",
4110 props->oa_format = value;
4112 case DRM_I915_PERF_PROP_OA_EXPONENT:
4113 if (value > OA_EXPONENT_MAX) {
4114 drm_dbg(&perf->i915->drm,
4115 "OA timer exponent too high (> %u)\n",
4120 /* Theoretically we can program the OA unit to sample
4121 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
4122 * for BXT. We don't allow such high sampling
4123 * frequencies by default unless root.
4126 BUILD_BUG_ON(sizeof(oa_period) != 8);
4127 oa_period = oa_exponent_to_ns(perf, value);
4129 /* This check is primarily to ensure that oa_period <=
4130 * UINT32_MAX (before passing to do_div which only
4131 * accepts a u32 denominator), but we can also skip
4132 * checking anything < 1Hz which implicitly can't be
4133 * limited via an integer oa_max_sample_rate.
4135 if (oa_period <= NSEC_PER_SEC) {
4136 u64 tmp = NSEC_PER_SEC;
4137 do_div(tmp, oa_period);
4142 if (oa_freq_hz > i915_oa_max_sample_rate && !perfmon_capable()) {
4143 drm_dbg(&perf->i915->drm,
4144 "OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
4145 i915_oa_max_sample_rate);
4149 props->oa_periodic = true;
4150 props->oa_period_exponent = value;
4152 case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
4153 props->hold_preemption = !!value;
4155 case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
4156 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
4157 drm_dbg(&perf->i915->drm,
4158 "SSEU config not supported on gfx %x\n",
4159 GRAPHICS_VER_FULL(perf->i915));
4163 if (copy_from_user(&user_sseu,
4164 u64_to_user_ptr(value),
4165 sizeof(user_sseu))) {
4166 drm_dbg(&perf->i915->drm,
4167 "Unable to copy global sseu parameter\n");
4173 case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
4174 if (value < 100000 /* 100us */) {
4175 drm_dbg(&perf->i915->drm,
4176 "OA availability timer too small (%lluns < 100us)\n",
4180 props->poll_oa_period = value;
4182 case DRM_I915_PERF_PROP_OA_ENGINE_CLASS:
4184 config_class = true;
4186 case DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE:
4187 instance = (u8)value;
4188 config_instance = true;
4198 if ((config_class && !config_instance) ||
4199 (config_instance && !config_class)) {
4200 drm_dbg(&perf->i915->drm,
4201 "OA engine-class and engine-instance parameters must be passed together\n");
4205 props->engine = intel_engine_lookup_user(perf->i915, class, instance);
4206 if (!props->engine) {
4207 drm_dbg(&perf->i915->drm,
4208 "OA engine class and instance invalid %d:%d\n",
4213 if (!engine_supports_oa(props->engine)) {
4214 drm_dbg(&perf->i915->drm,
4215 "Engine not supported by OA %d:%d\n",
4221 * Wa_14017512683: mtl[a0..c0): Use of OAM must be preceded with Media
4222 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
4223 * does not work as expected.
4225 if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
4226 props->engine->oa_group->type == TYPE_OAM &&
4227 intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
4228 drm_dbg(&perf->i915->drm,
4229 "OAM requires media C6 to be disabled in BIOS\n");
4233 i = array_index_nospec(props->oa_format, I915_OA_FORMAT_MAX);
4234 f = &perf->oa_formats[i];
4235 if (!engine_supports_oa_format(props->engine, f->type)) {
4236 drm_dbg(&perf->i915->drm,
4237 "Invalid OA format %d for class %d\n",
4238 f->type, props->engine->class);
4243 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
4245 drm_dbg(&perf->i915->drm,
4246 "Invalid SSEU configuration\n");
4249 props->has_sseu = true;
4256 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
4258 * @data: ioctl data copied from userspace (unvalidated)
4261 * Validates the stream open parameters given by userspace including flags
4262 * and an array of u64 key, value pair properties.
4264 * Very little is assumed up front about the nature of the stream being
4265 * opened (for instance we don't assume it's for periodic OA unit metrics). An
4266 * i915-perf stream is expected to be a suitable interface for other forms of
4267 * buffered data written by the GPU besides periodic OA metrics.
4269 * Note we copy the properties from userspace outside of the i915 perf
4270 * mutex to avoid an awkward lockdep with mmap_lock.
4272 * Most of the implementation details are handled by
4273 * i915_perf_open_ioctl_locked() after taking the >->perf.lock
4274 * mutex for serializing with any non-file-operation driver hooks.
4276 * Return: A newly opened i915 Perf stream file descriptor or negative
4277 * error code on failure.
4279 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
4280 struct drm_file *file)
4282 struct i915_perf *perf = &to_i915(dev)->perf;
4283 struct drm_i915_perf_open_param *param = data;
4284 struct intel_gt *gt;
4285 struct perf_open_properties props;
4286 u32 known_open_flags;
4290 drm_dbg(&perf->i915->drm,
4291 "i915 perf interface not available for this system\n");
4295 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
4296 I915_PERF_FLAG_FD_NONBLOCK |
4297 I915_PERF_FLAG_DISABLED;
4298 if (param->flags & ~known_open_flags) {
4299 drm_dbg(&perf->i915->drm,
4300 "Unknown drm_i915_perf_open_param flag\n");
4304 ret = read_properties_unlocked(perf,
4305 u64_to_user_ptr(param->properties_ptr),
4306 param->num_properties,
4311 gt = props.engine->gt;
4313 mutex_lock(>->perf.lock);
4314 ret = i915_perf_open_ioctl_locked(perf, param, &props, file);
4315 mutex_unlock(>->perf.lock);
4321 * i915_perf_register - exposes i915-perf to userspace
4322 * @i915: i915 device instance
4324 * In particular OA metric sets are advertised under a sysfs metrics/
4325 * directory allowing userspace to enumerate valid IDs that can be
4326 * used to open an i915-perf stream.
4328 void i915_perf_register(struct drm_i915_private *i915)
4330 struct i915_perf *perf = &i915->perf;
4331 struct intel_gt *gt = to_gt(i915);
4336 /* To be sure we're synchronized with an attempted
4337 * i915_perf_open_ioctl(); considering that we register after
4338 * being exposed to userspace.
4340 mutex_lock(>->perf.lock);
4342 perf->metrics_kobj =
4343 kobject_create_and_add("metrics",
4344 &i915->drm.primary->kdev->kobj);
4346 mutex_unlock(>->perf.lock);
4350 * i915_perf_unregister - hide i915-perf from userspace
4351 * @i915: i915 device instance
4353 * i915-perf state cleanup is split up into an 'unregister' and
4354 * 'deinit' phase where the interface is first hidden from
4355 * userspace by i915_perf_unregister() before cleaning up
4356 * remaining state in i915_perf_fini().
4358 void i915_perf_unregister(struct drm_i915_private *i915)
4360 struct i915_perf *perf = &i915->perf;
4362 if (!perf->metrics_kobj)
4365 kobject_put(perf->metrics_kobj);
4366 perf->metrics_kobj = NULL;
4369 static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
4371 static const i915_reg_t flex_eu_regs[] = {
4382 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
4383 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
4389 static bool reg_in_range_table(u32 addr, const struct i915_range *table)
4391 while (table->start || table->end) {
4392 if (addr >= table->start && addr <= table->end)
4401 #define REG_EQUAL(addr, mmio) \
4402 ((addr) == i915_mmio_reg_offset(mmio))
4404 static const struct i915_range gen7_oa_b_counters[] = {
4405 { .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
4406 { .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
4407 { .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
4411 static const struct i915_range gen12_oa_b_counters[] = {
4412 { .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
4413 { .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
4414 { .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8] */
4415 { .start = 0xd940, .end = 0xd97c }, /* GEN12_OAG_CEC[0-7][0-1] */
4416 { .start = 0xdc00, .end = 0xdc3c }, /* GEN12_OAG_SCEC[0-7][0-1] */
4417 { .start = 0xdc40, .end = 0xdc40 }, /* GEN12_OAG_SPCTR_CNF */
4418 { .start = 0xdc44, .end = 0xdc44 }, /* GEN12_OAA_DBG_REG */
4422 static const struct i915_range mtl_oam_b_counters[] = {
4423 { .start = 0x393000, .end = 0x39301c }, /* GEN12_OAM_STARTTRIG1[1-8] */
4424 { .start = 0x393020, .end = 0x39303c }, /* GEN12_OAM_REPORTTRIG1[1-8] */
4425 { .start = 0x393040, .end = 0x39307c }, /* GEN12_OAM_CEC[0-7][0-1] */
4426 { .start = 0x393200, .end = 0x39323C }, /* MPES[0-7] */
4430 static const struct i915_range xehp_oa_b_counters[] = {
4431 { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
4432 { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */
4436 static const struct i915_range gen7_oa_mux_regs[] = {
4437 { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */
4438 { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
4439 { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
4443 static const struct i915_range hsw_oa_mux_regs[] = {
4444 { .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
4445 { .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
4446 { .start = 0x25100, .end = 0x2ff90 },
4450 static const struct i915_range chv_oa_mux_regs[] = {
4451 { .start = 0x182300, .end = 0x1823a4 },
4455 static const struct i915_range gen8_oa_mux_regs[] = {
4456 { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
4457 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4461 static const struct i915_range gen11_oa_mux_regs[] = {
4462 { .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
4466 static const struct i915_range gen12_oa_mux_regs[] = {
4467 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4468 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4469 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
4470 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
4471 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4477 * 0x20cc is repurposed on MTL, so use a separate array for MTL.
4479 static const struct i915_range mtl_oa_mux_regs[] = {
4480 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4481 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4482 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
4483 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
4484 { .start = 0x38d100, .end = 0x38d114}, /* VISACTL */
4488 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4490 return reg_in_range_table(addr, gen7_oa_b_counters);
4493 static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4495 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4496 reg_in_range_table(addr, gen8_oa_mux_regs);
4499 static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4501 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4502 reg_in_range_table(addr, gen8_oa_mux_regs) ||
4503 reg_in_range_table(addr, gen11_oa_mux_regs);
4506 static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4508 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4509 reg_in_range_table(addr, hsw_oa_mux_regs);
4512 static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4514 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4515 reg_in_range_table(addr, chv_oa_mux_regs);
4518 static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4520 return reg_in_range_table(addr, gen12_oa_b_counters);
4523 static bool mtl_is_valid_oam_b_counter_addr(struct i915_perf *perf, u32 addr)
4525 if (HAS_OAM(perf->i915) &&
4526 GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
4527 return reg_in_range_table(addr, mtl_oam_b_counters);
4532 static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4534 return reg_in_range_table(addr, xehp_oa_b_counters) ||
4535 reg_in_range_table(addr, gen12_oa_b_counters) ||
4536 mtl_is_valid_oam_b_counter_addr(perf, addr);
4539 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4541 if (IS_METEORLAKE(perf->i915))
4542 return reg_in_range_table(addr, mtl_oa_mux_regs);
4544 return reg_in_range_table(addr, gen12_oa_mux_regs);
4547 static u32 mask_reg_value(u32 reg, u32 val)
4549 /* HALF_SLICE_CHICKEN2 is programmed with a the
4550 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
4551 * programmed by userspace doesn't change this.
4553 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
4554 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
4556 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
4557 * indicated by its name and a bunch of selection fields used by OA
4560 if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
4561 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
4566 static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf,
4567 bool (*is_valid)(struct i915_perf *perf, u32 addr),
4571 struct i915_oa_reg *oa_regs;
4578 /* No is_valid function means we're not allowing any register to be programmed. */
4579 GEM_BUG_ON(!is_valid);
4581 return ERR_PTR(-EINVAL);
4583 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
4585 return ERR_PTR(-ENOMEM);
4587 for (i = 0; i < n_regs; i++) {
4590 err = get_user(addr, regs);
4594 if (!is_valid(perf, addr)) {
4595 drm_dbg(&perf->i915->drm,
4596 "Invalid oa_reg address: %X\n", addr);
4601 err = get_user(value, regs + 1);
4605 oa_regs[i].addr = _MMIO(addr);
4606 oa_regs[i].value = mask_reg_value(addr, value);
4615 return ERR_PTR(err);
4618 static ssize_t show_dynamic_id(struct kobject *kobj,
4619 struct kobj_attribute *attr,
4622 struct i915_oa_config *oa_config =
4623 container_of(attr, typeof(*oa_config), sysfs_metric_id);
4625 return sprintf(buf, "%d\n", oa_config->id);
4628 static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf,
4629 struct i915_oa_config *oa_config)
4631 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
4632 oa_config->sysfs_metric_id.attr.name = "id";
4633 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
4634 oa_config->sysfs_metric_id.show = show_dynamic_id;
4635 oa_config->sysfs_metric_id.store = NULL;
4637 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
4638 oa_config->attrs[1] = NULL;
4640 oa_config->sysfs_metric.name = oa_config->uuid;
4641 oa_config->sysfs_metric.attrs = oa_config->attrs;
4643 return sysfs_create_group(perf->metrics_kobj,
4644 &oa_config->sysfs_metric);
4648 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
4650 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
4651 * userspace (unvalidated)
4654 * Validates the submitted OA register to be saved into a new OA config that
4655 * can then be used for programming the OA unit and its NOA network.
4657 * Returns: A new allocated config number to be used with the perf open ioctl
4658 * or a negative error code on failure.
4660 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
4661 struct drm_file *file)
4663 struct i915_perf *perf = &to_i915(dev)->perf;
4664 struct drm_i915_perf_oa_config *args = data;
4665 struct i915_oa_config *oa_config, *tmp;
4666 struct i915_oa_reg *regs;
4670 drm_dbg(&perf->i915->drm,
4671 "i915 perf interface not available for this system\n");
4675 if (!perf->metrics_kobj) {
4676 drm_dbg(&perf->i915->drm,
4677 "OA metrics weren't advertised via sysfs\n");
4681 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4682 drm_dbg(&perf->i915->drm,
4683 "Insufficient privileges to add i915 OA config\n");
4687 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
4688 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
4689 (!args->flex_regs_ptr || !args->n_flex_regs)) {
4690 drm_dbg(&perf->i915->drm,
4691 "No OA registers given\n");
4695 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
4697 drm_dbg(&perf->i915->drm,
4698 "Failed to allocate memory for the OA config\n");
4702 oa_config->perf = perf;
4703 kref_init(&oa_config->ref);
4705 if (!uuid_is_valid(args->uuid)) {
4706 drm_dbg(&perf->i915->drm,
4707 "Invalid uuid format for OA config\n");
4712 /* Last character in oa_config->uuid will be 0 because oa_config is
4715 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
4717 oa_config->mux_regs_len = args->n_mux_regs;
4718 regs = alloc_oa_regs(perf,
4719 perf->ops.is_valid_mux_reg,
4720 u64_to_user_ptr(args->mux_regs_ptr),
4724 drm_dbg(&perf->i915->drm,
4725 "Failed to create OA config for mux_regs\n");
4726 err = PTR_ERR(regs);
4729 oa_config->mux_regs = regs;
4731 oa_config->b_counter_regs_len = args->n_boolean_regs;
4732 regs = alloc_oa_regs(perf,
4733 perf->ops.is_valid_b_counter_reg,
4734 u64_to_user_ptr(args->boolean_regs_ptr),
4735 args->n_boolean_regs);
4738 drm_dbg(&perf->i915->drm,
4739 "Failed to create OA config for b_counter_regs\n");
4740 err = PTR_ERR(regs);
4743 oa_config->b_counter_regs = regs;
4745 if (GRAPHICS_VER(perf->i915) < 8) {
4746 if (args->n_flex_regs != 0) {
4751 oa_config->flex_regs_len = args->n_flex_regs;
4752 regs = alloc_oa_regs(perf,
4753 perf->ops.is_valid_flex_reg,
4754 u64_to_user_ptr(args->flex_regs_ptr),
4758 drm_dbg(&perf->i915->drm,
4759 "Failed to create OA config for flex_regs\n");
4760 err = PTR_ERR(regs);
4763 oa_config->flex_regs = regs;
4766 err = mutex_lock_interruptible(&perf->metrics_lock);
4770 /* We shouldn't have too many configs, so this iteration shouldn't be
4773 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
4774 if (!strcmp(tmp->uuid, oa_config->uuid)) {
4775 drm_dbg(&perf->i915->drm,
4776 "OA config already exists with this uuid\n");
4782 err = create_dynamic_oa_sysfs_entry(perf, oa_config);
4784 drm_dbg(&perf->i915->drm,
4785 "Failed to create sysfs entry for OA config\n");
4789 /* Config id 0 is invalid, id 1 for kernel stored test config. */
4790 oa_config->id = idr_alloc(&perf->metrics_idr,
4793 if (oa_config->id < 0) {
4794 drm_dbg(&perf->i915->drm,
4795 "Failed to create sysfs entry for OA config\n");
4796 err = oa_config->id;
4801 drm_dbg(&perf->i915->drm,
4802 "Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4803 mutex_unlock(&perf->metrics_lock);
4808 mutex_unlock(&perf->metrics_lock);
4810 i915_oa_config_put(oa_config);
4811 drm_dbg(&perf->i915->drm,
4812 "Failed to add new OA config\n");
4817 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
4819 * @data: ioctl data (pointer to u64 integer) copied from userspace
4822 * Configs can be removed while being used, the will stop appearing in sysfs
4823 * and their content will be freed when the stream using the config is closed.
4825 * Returns: 0 on success or a negative error code on failure.
4827 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
4828 struct drm_file *file)
4830 struct i915_perf *perf = &to_i915(dev)->perf;
4832 struct i915_oa_config *oa_config;
4836 drm_dbg(&perf->i915->drm,
4837 "i915 perf interface not available for this system\n");
4841 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4842 drm_dbg(&perf->i915->drm,
4843 "Insufficient privileges to remove i915 OA config\n");
4847 ret = mutex_lock_interruptible(&perf->metrics_lock);
4851 oa_config = idr_find(&perf->metrics_idr, *arg);
4853 drm_dbg(&perf->i915->drm,
4854 "Failed to remove unknown OA config\n");
4859 GEM_BUG_ON(*arg != oa_config->id);
4861 sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric);
4863 idr_remove(&perf->metrics_idr, *arg);
4865 mutex_unlock(&perf->metrics_lock);
4867 drm_dbg(&perf->i915->drm,
4868 "Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
4870 i915_oa_config_put(oa_config);
4875 mutex_unlock(&perf->metrics_lock);
4879 static struct ctl_table oa_table[] = {
4881 .procname = "perf_stream_paranoid",
4882 .data = &i915_perf_stream_paranoid,
4883 .maxlen = sizeof(i915_perf_stream_paranoid),
4885 .proc_handler = proc_dointvec_minmax,
4886 .extra1 = SYSCTL_ZERO,
4887 .extra2 = SYSCTL_ONE,
4890 .procname = "oa_max_sample_rate",
4891 .data = &i915_oa_max_sample_rate,
4892 .maxlen = sizeof(i915_oa_max_sample_rate),
4894 .proc_handler = proc_dointvec_minmax,
4895 .extra1 = SYSCTL_ZERO,
4896 .extra2 = &oa_sample_rate_hard_limit,
4901 static u32 num_perf_groups_per_gt(struct intel_gt *gt)
4906 static u32 __oam_engine_group(struct intel_engine_cs *engine)
4908 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) {
4910 * There's 1 SAMEDIA gt and 1 OAM per SAMEDIA gt. All media slices
4911 * within the gt use the same OAM. All MTL SKUs list 1 SA MEDIA.
4913 drm_WARN_ON(&engine->i915->drm,
4914 engine->gt->type != GT_MEDIA);
4916 return PERF_GROUP_OAM_SAMEDIA_0;
4919 return PERF_GROUP_INVALID;
4922 static u32 __oa_engine_group(struct intel_engine_cs *engine)
4924 switch (engine->class) {
4926 return PERF_GROUP_OAG;
4928 case VIDEO_DECODE_CLASS:
4929 case VIDEO_ENHANCEMENT_CLASS:
4930 return __oam_engine_group(engine);
4933 return PERF_GROUP_INVALID;
4937 static struct i915_perf_regs __oam_regs(u32 base)
4939 return (struct i915_perf_regs) {
4941 GEN12_OAM_HEAD_POINTER(base),
4942 GEN12_OAM_TAIL_POINTER(base),
4943 GEN12_OAM_BUFFER(base),
4944 GEN12_OAM_CONTEXT_CONTROL(base),
4945 GEN12_OAM_CONTROL(base),
4946 GEN12_OAM_DEBUG(base),
4947 GEN12_OAM_STATUS(base),
4948 GEN12_OAM_CONTROL_COUNTER_FORMAT_SHIFT,
4952 static struct i915_perf_regs __oag_regs(void)
4954 return (struct i915_perf_regs) {
4956 GEN12_OAG_OAHEADPTR,
4957 GEN12_OAG_OATAILPTR,
4959 GEN12_OAG_OAGLBCTXCTRL,
4960 GEN12_OAG_OACONTROL,
4963 GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT,
4967 static void oa_init_groups(struct intel_gt *gt)
4969 int i, num_groups = gt->perf.num_perf_groups;
4971 for (i = 0; i < num_groups; i++) {
4972 struct i915_perf_group *g = >->perf.group[i];
4974 /* Fused off engines can result in a group with num_engines == 0 */
4975 if (g->num_engines == 0)
4978 if (i == PERF_GROUP_OAG && gt->type != GT_MEDIA) {
4979 g->regs = __oag_regs();
4981 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {
4982 g->regs = __oam_regs(mtl_oa_base[i]);
4988 static int oa_init_gt(struct intel_gt *gt)
4990 u32 num_groups = num_perf_groups_per_gt(gt);
4991 struct intel_engine_cs *engine;
4992 struct i915_perf_group *g;
4993 intel_engine_mask_t tmp;
4995 g = kcalloc(num_groups, sizeof(*g), GFP_KERNEL);
4999 for_each_engine_masked(engine, gt, ALL_ENGINES, tmp) {
5000 u32 index = __oa_engine_group(engine);
5002 engine->oa_group = NULL;
5003 if (index < num_groups) {
5004 g[index].num_engines++;
5005 engine->oa_group = &g[index];
5009 gt->perf.num_perf_groups = num_groups;
5017 static int oa_init_engine_groups(struct i915_perf *perf)
5019 struct intel_gt *gt;
5022 for_each_gt(gt, perf->i915, i) {
5023 ret = oa_init_gt(gt);
5031 static void oa_init_supported_formats(struct i915_perf *perf)
5033 struct drm_i915_private *i915 = perf->i915;
5034 enum intel_platform platform = INTEL_INFO(i915)->platform;
5038 oa_format_add(perf, I915_OA_FORMAT_A13);
5039 oa_format_add(perf, I915_OA_FORMAT_A13);
5040 oa_format_add(perf, I915_OA_FORMAT_A29);
5041 oa_format_add(perf, I915_OA_FORMAT_A13_B8_C8);
5042 oa_format_add(perf, I915_OA_FORMAT_B4_C8);
5043 oa_format_add(perf, I915_OA_FORMAT_A45_B8_C8);
5044 oa_format_add(perf, I915_OA_FORMAT_B4_C8_A16);
5045 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
5048 case INTEL_BROADWELL:
5049 case INTEL_CHERRYVIEW:
5052 case INTEL_KABYLAKE:
5053 case INTEL_GEMINILAKE:
5054 case INTEL_COFFEELAKE:
5055 case INTEL_COMETLAKE:
5057 case INTEL_ELKHARTLAKE:
5058 case INTEL_JASPERLAKE:
5059 case INTEL_TIGERLAKE:
5060 case INTEL_ROCKETLAKE:
5062 case INTEL_ALDERLAKE_S:
5063 case INTEL_ALDERLAKE_P:
5064 oa_format_add(perf, I915_OA_FORMAT_A12);
5065 oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
5066 oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
5067 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
5071 oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
5072 oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
5075 case INTEL_METEORLAKE:
5076 oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
5077 oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
5078 oa_format_add(perf, I915_OAM_FORMAT_MPEC8u64_B8_C8);
5079 oa_format_add(perf, I915_OAM_FORMAT_MPEC8u32_B8_C8);
5083 MISSING_CASE(platform);
5087 static void i915_perf_init_info(struct drm_i915_private *i915)
5089 struct i915_perf *perf = &i915->perf;
5091 switch (GRAPHICS_VER(i915)) {
5093 perf->ctx_oactxctrl_offset = 0x120;
5094 perf->ctx_flexeu0_offset = 0x2ce;
5095 perf->gen8_valid_ctx_bit = BIT(25);
5098 perf->ctx_oactxctrl_offset = 0x128;
5099 perf->ctx_flexeu0_offset = 0x3de;
5100 perf->gen8_valid_ctx_bit = BIT(16);
5103 perf->ctx_oactxctrl_offset = 0x124;
5104 perf->ctx_flexeu0_offset = 0x78e;
5105 perf->gen8_valid_ctx_bit = BIT(16);
5108 perf->gen8_valid_ctx_bit = BIT(16);
5110 * Calculate offset at runtime in oa_pin_context for gen12 and
5111 * cache the value in perf->ctx_oactxctrl_offset.
5115 MISSING_CASE(GRAPHICS_VER(i915));
5120 * i915_perf_init - initialize i915-perf state on module bind
5121 * @i915: i915 device instance
5123 * Initializes i915-perf state without exposing anything to userspace.
5125 * Note: i915-perf initialization is split into an 'init' and 'register'
5126 * phase with the i915_perf_register() exposing state to userspace.
5128 int i915_perf_init(struct drm_i915_private *i915)
5130 struct i915_perf *perf = &i915->perf;
5132 perf->oa_formats = oa_formats;
5133 if (IS_HASWELL(i915)) {
5134 perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
5135 perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
5136 perf->ops.is_valid_flex_reg = NULL;
5137 perf->ops.enable_metric_set = hsw_enable_metric_set;
5138 perf->ops.disable_metric_set = hsw_disable_metric_set;
5139 perf->ops.oa_enable = gen7_oa_enable;
5140 perf->ops.oa_disable = gen7_oa_disable;
5141 perf->ops.read = gen7_oa_read;
5142 perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
5143 } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
5144 /* Note: that although we could theoretically also support the
5145 * legacy ringbuffer mode on BDW (and earlier iterations of
5146 * this driver, before upstreaming did this) it didn't seem
5147 * worth the complexity to maintain now that BDW+ enable
5148 * execlist mode by default.
5150 perf->ops.read = gen8_oa_read;
5151 i915_perf_init_info(i915);
5153 if (IS_GRAPHICS_VER(i915, 8, 9)) {
5154 perf->ops.is_valid_b_counter_reg =
5155 gen7_is_valid_b_counter_addr;
5156 perf->ops.is_valid_mux_reg =
5157 gen8_is_valid_mux_addr;
5158 perf->ops.is_valid_flex_reg =
5159 gen8_is_valid_flex_addr;
5161 if (IS_CHERRYVIEW(i915)) {
5162 perf->ops.is_valid_mux_reg =
5163 chv_is_valid_mux_addr;
5166 perf->ops.oa_enable = gen8_oa_enable;
5167 perf->ops.oa_disable = gen8_oa_disable;
5168 perf->ops.enable_metric_set = gen8_enable_metric_set;
5169 perf->ops.disable_metric_set = gen8_disable_metric_set;
5170 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
5171 } else if (GRAPHICS_VER(i915) == 11) {
5172 perf->ops.is_valid_b_counter_reg =
5173 gen7_is_valid_b_counter_addr;
5174 perf->ops.is_valid_mux_reg =
5175 gen11_is_valid_mux_addr;
5176 perf->ops.is_valid_flex_reg =
5177 gen8_is_valid_flex_addr;
5179 perf->ops.oa_enable = gen8_oa_enable;
5180 perf->ops.oa_disable = gen8_oa_disable;
5181 perf->ops.enable_metric_set = gen8_enable_metric_set;
5182 perf->ops.disable_metric_set = gen11_disable_metric_set;
5183 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
5184 } else if (GRAPHICS_VER(i915) == 12) {
5185 perf->ops.is_valid_b_counter_reg =
5186 HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?
5187 xehp_is_valid_b_counter_addr :
5188 gen12_is_valid_b_counter_addr;
5189 perf->ops.is_valid_mux_reg =
5190 gen12_is_valid_mux_addr;
5191 perf->ops.is_valid_flex_reg =
5192 gen8_is_valid_flex_addr;
5194 perf->ops.oa_enable = gen12_oa_enable;
5195 perf->ops.oa_disable = gen12_oa_disable;
5196 perf->ops.enable_metric_set = gen12_enable_metric_set;
5197 perf->ops.disable_metric_set = gen12_disable_metric_set;
5198 perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
5202 if (perf->ops.enable_metric_set) {
5203 struct intel_gt *gt;
5206 for_each_gt(gt, i915, i)
5207 mutex_init(>->perf.lock);
5209 /* Choose a representative limit */
5210 oa_sample_rate_hard_limit = to_gt(i915)->clock_frequency / 2;
5212 mutex_init(&perf->metrics_lock);
5213 idr_init_base(&perf->metrics_idr, 1);
5215 /* We set up some ratelimit state to potentially throttle any
5216 * _NOTES about spurious, invalid OA reports which we don't
5217 * forward to userspace.
5219 * We print a _NOTE about any throttling when closing the
5220 * stream instead of waiting until driver _fini which no one
5223 * Using the same limiting factors as printk_ratelimit()
5225 ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10);
5226 /* Since we use a DRM_NOTE for spurious reports it would be
5227 * inconsistent to let __ratelimit() automatically print a
5228 * warning for throttling.
5230 ratelimit_set_flags(&perf->spurious_report_rs,
5231 RATELIMIT_MSG_ON_RELEASE);
5233 ratelimit_state_init(&perf->tail_pointer_race,
5235 ratelimit_set_flags(&perf->tail_pointer_race,
5236 RATELIMIT_MSG_ON_RELEASE);
5238 atomic64_set(&perf->noa_programming_delay,
5239 500 * 1000 /* 500us */);
5243 ret = oa_init_engine_groups(perf);
5246 "OA initialization failed %d\n", ret);
5250 oa_init_supported_formats(perf);
5256 static int destroy_config(int id, void *p, void *data)
5258 i915_oa_config_put(p);
5262 int i915_perf_sysctl_register(void)
5264 sysctl_header = register_sysctl("dev/i915", oa_table);
5268 void i915_perf_sysctl_unregister(void)
5270 unregister_sysctl_table(sysctl_header);
5274 * i915_perf_fini - Counter part to i915_perf_init()
5275 * @i915: i915 device instance
5277 void i915_perf_fini(struct drm_i915_private *i915)
5279 struct i915_perf *perf = &i915->perf;
5280 struct intel_gt *gt;
5286 for_each_gt(gt, perf->i915, i)
5287 kfree(gt->perf.group);
5289 idr_for_each(&perf->metrics_idr, destroy_config, perf);
5290 idr_destroy(&perf->metrics_idr);
5292 memset(&perf->ops, 0, sizeof(perf->ops));
5297 * i915_perf_ioctl_version - Version of the i915-perf subsystem
5298 * @i915: The i915 device
5300 * This version number is used by userspace to detect available features.
5302 int i915_perf_ioctl_version(struct drm_i915_private *i915)
5305 * 1: Initial version
5306 * I915_PERF_IOCTL_ENABLE
5307 * I915_PERF_IOCTL_DISABLE
5309 * 2: Added runtime modification of OA config.
5310 * I915_PERF_IOCTL_CONFIG
5312 * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
5313 * preemption on a particular context so that performance data is
5314 * accessible from a delta of MI_RPC reports without looking at the
5317 * 4: Add DRM_I915_PERF_PROP_ALLOWED_SSEU to limit what contexts can
5318 * be run for the duration of the performance recording based on
5319 * their SSEU configuration.
5321 * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
5322 * interval for the hrtimer used to check for OA data.
5324 * 6: Add DRM_I915_PERF_PROP_OA_ENGINE_CLASS and
5325 * DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE
5327 * 7: Add support for video decode and enhancement classes.
5331 * Wa_14017512683: mtl[a0..c0): Use of OAM must be preceded with Media
5332 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
5333 * to indicate that OA media is not supported.
5335 if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
5336 struct intel_gt *gt;
5339 for_each_gt(gt, i915, i) {
5340 if (gt->type == GT_MEDIA &&
5341 intel_check_bios_c6_setup(>->rc6))
5349 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5350 #include "selftests/i915_perf.c"