2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vga_switcheroo.h>
28 #include <drm/drm_drv.h>
29 #include <drm/i915_pciids.h>
31 #include "display/intel_fbdev.h"
34 #include "i915_perf.h"
35 #include "i915_globals.h"
36 #include "i915_selftest.h"
38 #define PLATFORM(x) .platform = (x)
39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
41 #define I845_PIPE_OFFSETS \
43 [TRANSCODER_A] = PIPE_A_OFFSET, \
46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
49 #define I9XX_PIPE_OFFSETS \
51 [TRANSCODER_A] = PIPE_A_OFFSET, \
52 [TRANSCODER_B] = PIPE_B_OFFSET, \
55 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
56 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
59 #define IVB_PIPE_OFFSETS \
61 [TRANSCODER_A] = PIPE_A_OFFSET, \
62 [TRANSCODER_B] = PIPE_B_OFFSET, \
63 [TRANSCODER_C] = PIPE_C_OFFSET, \
66 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
67 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
68 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
71 #define HSW_PIPE_OFFSETS \
73 [TRANSCODER_A] = PIPE_A_OFFSET, \
74 [TRANSCODER_B] = PIPE_B_OFFSET, \
75 [TRANSCODER_C] = PIPE_C_OFFSET, \
76 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
82 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
85 #define CHV_PIPE_OFFSETS \
87 [TRANSCODER_A] = PIPE_A_OFFSET, \
88 [TRANSCODER_B] = PIPE_B_OFFSET, \
89 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
94 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
97 #define I845_CURSOR_OFFSETS \
99 [PIPE_A] = CURSOR_A_OFFSET, \
102 #define I9XX_CURSOR_OFFSETS \
103 .cursor_offsets = { \
104 [PIPE_A] = CURSOR_A_OFFSET, \
105 [PIPE_B] = CURSOR_B_OFFSET, \
108 #define CHV_CURSOR_OFFSETS \
109 .cursor_offsets = { \
110 [PIPE_A] = CURSOR_A_OFFSET, \
111 [PIPE_B] = CURSOR_B_OFFSET, \
112 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
115 #define IVB_CURSOR_OFFSETS \
116 .cursor_offsets = { \
117 [PIPE_A] = CURSOR_A_OFFSET, \
118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
119 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
122 #define TGL_CURSOR_OFFSETS \
123 .cursor_offsets = { \
124 [PIPE_A] = CURSOR_A_OFFSET, \
125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
127 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
130 #define I9XX_COLORS \
131 .color = { .gamma_lut_size = 256 }
132 #define I965_COLORS \
133 .color = { .gamma_lut_size = 129, \
134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
137 .color = { .gamma_lut_size = 1024 }
139 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
141 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
146 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
147 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
148 DRM_COLOR_LUT_EQUAL_CHANNELS, \
151 /* Keep in gen based order, and chronological order within a gen */
153 #define GEN_DEFAULT_PAGE_SIZES \
154 .page_sizes = I915_GTT_PAGE_SIZE_4K
156 #define GEN_DEFAULT_REGIONS \
157 .memory_regions = REGION_SMEM | REGION_STOLEN
159 #define I830_FEATURES \
162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
163 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
164 .display.has_overlay = 1, \
165 .display.cursor_needs_physical = 1, \
166 .display.overlay_needs_physical = 1, \
167 .display.has_gmch = 1, \
168 .gpu_reset_clobbers_display = true, \
169 .hws_needs_physical = 1, \
170 .unfenced_needs_alignment = 1, \
171 .platform_engine_mask = BIT(RCS0), \
173 .has_coherent_ggtt = false, \
174 .dma_mask_size = 32, \
176 I9XX_CURSOR_OFFSETS, \
178 GEN_DEFAULT_PAGE_SIZES, \
181 #define I845_FEATURES \
183 .pipe_mask = BIT(PIPE_A), \
184 .cpu_transcoder_mask = BIT(TRANSCODER_A), \
185 .display.has_overlay = 1, \
186 .display.overlay_needs_physical = 1, \
187 .display.has_gmch = 1, \
188 .gpu_reset_clobbers_display = true, \
189 .hws_needs_physical = 1, \
190 .unfenced_needs_alignment = 1, \
191 .platform_engine_mask = BIT(RCS0), \
193 .has_coherent_ggtt = false, \
194 .dma_mask_size = 32, \
196 I845_CURSOR_OFFSETS, \
198 GEN_DEFAULT_PAGE_SIZES, \
201 static const struct intel_device_info i830_info = {
203 PLATFORM(INTEL_I830),
206 static const struct intel_device_info i845g_info = {
208 PLATFORM(INTEL_I845G),
211 static const struct intel_device_info i85x_info = {
213 PLATFORM(INTEL_I85X),
214 .display.has_fbc = 1,
217 static const struct intel_device_info i865g_info = {
219 PLATFORM(INTEL_I865G),
220 .display.has_fbc = 1,
223 #define GEN3_FEATURES \
225 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
226 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
227 .display.has_gmch = 1, \
228 .gpu_reset_clobbers_display = true, \
229 .platform_engine_mask = BIT(RCS0), \
231 .has_coherent_ggtt = true, \
232 .dma_mask_size = 32, \
234 I9XX_CURSOR_OFFSETS, \
236 GEN_DEFAULT_PAGE_SIZES, \
239 static const struct intel_device_info i915g_info = {
241 PLATFORM(INTEL_I915G),
242 .has_coherent_ggtt = false,
243 .display.cursor_needs_physical = 1,
244 .display.has_overlay = 1,
245 .display.overlay_needs_physical = 1,
246 .hws_needs_physical = 1,
247 .unfenced_needs_alignment = 1,
250 static const struct intel_device_info i915gm_info = {
252 PLATFORM(INTEL_I915GM),
254 .display.cursor_needs_physical = 1,
255 .display.has_overlay = 1,
256 .display.overlay_needs_physical = 1,
257 .display.supports_tv = 1,
258 .display.has_fbc = 1,
259 .hws_needs_physical = 1,
260 .unfenced_needs_alignment = 1,
263 static const struct intel_device_info i945g_info = {
265 PLATFORM(INTEL_I945G),
266 .display.has_hotplug = 1,
267 .display.cursor_needs_physical = 1,
268 .display.has_overlay = 1,
269 .display.overlay_needs_physical = 1,
270 .hws_needs_physical = 1,
271 .unfenced_needs_alignment = 1,
274 static const struct intel_device_info i945gm_info = {
276 PLATFORM(INTEL_I945GM),
278 .display.has_hotplug = 1,
279 .display.cursor_needs_physical = 1,
280 .display.has_overlay = 1,
281 .display.overlay_needs_physical = 1,
282 .display.supports_tv = 1,
283 .display.has_fbc = 1,
284 .hws_needs_physical = 1,
285 .unfenced_needs_alignment = 1,
288 static const struct intel_device_info g33_info = {
291 .display.has_hotplug = 1,
292 .display.has_overlay = 1,
296 static const struct intel_device_info pnv_g_info = {
298 PLATFORM(INTEL_PINEVIEW),
299 .display.has_hotplug = 1,
300 .display.has_overlay = 1,
304 static const struct intel_device_info pnv_m_info = {
306 PLATFORM(INTEL_PINEVIEW),
308 .display.has_hotplug = 1,
309 .display.has_overlay = 1,
313 #define GEN4_FEATURES \
315 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
316 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
317 .display.has_hotplug = 1, \
318 .display.has_gmch = 1, \
319 .gpu_reset_clobbers_display = true, \
320 .platform_engine_mask = BIT(RCS0), \
322 .has_coherent_ggtt = true, \
323 .dma_mask_size = 36, \
325 I9XX_CURSOR_OFFSETS, \
327 GEN_DEFAULT_PAGE_SIZES, \
330 static const struct intel_device_info i965g_info = {
332 PLATFORM(INTEL_I965G),
333 .display.has_overlay = 1,
334 .hws_needs_physical = 1,
338 static const struct intel_device_info i965gm_info = {
340 PLATFORM(INTEL_I965GM),
342 .display.has_fbc = 1,
343 .display.has_overlay = 1,
344 .display.supports_tv = 1,
345 .hws_needs_physical = 1,
349 static const struct intel_device_info g45_info = {
352 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
353 .gpu_reset_clobbers_display = false,
356 static const struct intel_device_info gm45_info = {
358 PLATFORM(INTEL_GM45),
360 .display.has_fbc = 1,
361 .display.supports_tv = 1,
362 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
363 .gpu_reset_clobbers_display = false,
366 #define GEN5_FEATURES \
368 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
369 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
370 .display.has_hotplug = 1, \
371 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
373 .has_coherent_ggtt = true, \
374 /* ilk does support rc6, but we do not implement [power] contexts */ \
376 .dma_mask_size = 36, \
378 I9XX_CURSOR_OFFSETS, \
380 GEN_DEFAULT_PAGE_SIZES, \
383 static const struct intel_device_info ilk_d_info = {
385 PLATFORM(INTEL_IRONLAKE),
388 static const struct intel_device_info ilk_m_info = {
390 PLATFORM(INTEL_IRONLAKE),
393 .display.has_fbc = 1,
396 #define GEN6_FEATURES \
398 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
399 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
400 .display.has_hotplug = 1, \
401 .display.has_fbc = 1, \
402 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
403 .has_coherent_ggtt = true, \
408 .dma_mask_size = 40, \
409 .ppgtt_type = INTEL_PPGTT_ALIASING, \
412 I9XX_CURSOR_OFFSETS, \
414 GEN_DEFAULT_PAGE_SIZES, \
417 #define SNB_D_PLATFORM \
419 PLATFORM(INTEL_SANDYBRIDGE)
421 static const struct intel_device_info snb_d_gt1_info = {
426 static const struct intel_device_info snb_d_gt2_info = {
431 #define SNB_M_PLATFORM \
433 PLATFORM(INTEL_SANDYBRIDGE), \
437 static const struct intel_device_info snb_m_gt1_info = {
442 static const struct intel_device_info snb_m_gt2_info = {
447 #define GEN7_FEATURES \
449 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
450 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
451 .display.has_hotplug = 1, \
452 .display.has_fbc = 1, \
453 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
454 .has_coherent_ggtt = true, \
458 .has_reset_engine = true, \
460 .dma_mask_size = 40, \
461 .ppgtt_type = INTEL_PPGTT_ALIASING, \
464 IVB_CURSOR_OFFSETS, \
466 GEN_DEFAULT_PAGE_SIZES, \
469 #define IVB_D_PLATFORM \
471 PLATFORM(INTEL_IVYBRIDGE), \
474 static const struct intel_device_info ivb_d_gt1_info = {
479 static const struct intel_device_info ivb_d_gt2_info = {
484 #define IVB_M_PLATFORM \
486 PLATFORM(INTEL_IVYBRIDGE), \
490 static const struct intel_device_info ivb_m_gt1_info = {
495 static const struct intel_device_info ivb_m_gt2_info = {
500 static const struct intel_device_info ivb_q_info = {
502 PLATFORM(INTEL_IVYBRIDGE),
504 .pipe_mask = 0, /* legal, last one wins */
505 .cpu_transcoder_mask = 0,
509 static const struct intel_device_info vlv_info = {
510 PLATFORM(INTEL_VALLEYVIEW),
513 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
514 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
517 .has_reset_engine = true,
519 .display.has_gmch = 1,
520 .display.has_hotplug = 1,
522 .ppgtt_type = INTEL_PPGTT_ALIASING,
525 .has_coherent_ggtt = false,
526 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
527 .display_mmio_offset = VLV_DISPLAY_BASE,
531 GEN_DEFAULT_PAGE_SIZES,
535 #define G75_FEATURES \
537 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
538 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
539 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
540 .display.has_ddi = 1, \
541 .display.has_fpga_dbg = 1, \
542 .display.has_psr = 1, \
543 .display.has_psr_hw_tracking = 1, \
544 .display.has_dp_mst = 1, \
545 .has_rc6p = 0 /* RC6p removed-by HSW */, \
549 #define HSW_PLATFORM \
551 PLATFORM(INTEL_HASWELL), \
554 static const struct intel_device_info hsw_gt1_info = {
559 static const struct intel_device_info hsw_gt2_info = {
564 static const struct intel_device_info hsw_gt3_info = {
569 #define GEN8_FEATURES \
572 .has_logical_ring_contexts = 1, \
573 .dma_mask_size = 39, \
574 .ppgtt_type = INTEL_PPGTT_FULL, \
578 #define BDW_PLATFORM \
580 PLATFORM(INTEL_BROADWELL)
582 static const struct intel_device_info bdw_gt1_info = {
587 static const struct intel_device_info bdw_gt2_info = {
592 static const struct intel_device_info bdw_rsvd_info = {
595 /* According to the device ID those devices are GT3, they were
596 * previously treated as not GT3, keep it like that.
600 static const struct intel_device_info bdw_gt3_info = {
603 .platform_engine_mask =
604 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
607 static const struct intel_device_info chv_info = {
608 PLATFORM(INTEL_CHERRYVIEW),
610 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
611 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
612 .display.has_hotplug = 1,
614 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
615 .has_64bit_reloc = 1,
619 .has_logical_ring_contexts = 1,
620 .display.has_gmch = 1,
622 .ppgtt_type = INTEL_PPGTT_FULL,
624 .has_reset_engine = 1,
626 .has_coherent_ggtt = false,
627 .display_mmio_offset = VLV_DISPLAY_BASE,
631 GEN_DEFAULT_PAGE_SIZES,
635 #define GEN9_DEFAULT_PAGE_SIZES \
636 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
637 I915_GTT_PAGE_SIZE_64K
639 #define GEN9_FEATURES \
642 GEN9_DEFAULT_PAGE_SIZES, \
643 .display.has_csr = 1, \
645 .display.has_hdcp = 1, \
646 .display.has_ipc = 1, \
648 .num_supported_dbuf_slices = 1
650 #define SKL_PLATFORM \
652 PLATFORM(INTEL_SKYLAKE)
654 static const struct intel_device_info skl_gt1_info = {
659 static const struct intel_device_info skl_gt2_info = {
664 #define SKL_GT3_PLUS_PLATFORM \
666 .platform_engine_mask = \
667 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
670 static const struct intel_device_info skl_gt3_info = {
671 SKL_GT3_PLUS_PLATFORM,
675 static const struct intel_device_info skl_gt4_info = {
676 SKL_GT3_PLUS_PLATFORM,
680 #define GEN9_LP_FEATURES \
683 .num_supported_dbuf_slices = 1, \
684 .display.has_hotplug = 1, \
685 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
686 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
687 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
688 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
689 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
690 .has_64bit_reloc = 1, \
691 .display.has_ddi = 1, \
692 .display.has_fpga_dbg = 1, \
693 .display.has_fbc = 1, \
694 .display.has_hdcp = 1, \
695 .display.has_psr = 1, \
696 .display.has_psr_hw_tracking = 1, \
697 .has_runtime_pm = 1, \
698 .display.has_csr = 1, \
701 .display.has_dp_mst = 1, \
702 .has_logical_ring_contexts = 1, \
704 .dma_mask_size = 39, \
705 .ppgtt_type = INTEL_PPGTT_FULL, \
707 .has_reset_engine = 1, \
709 .has_coherent_ggtt = false, \
710 .display.has_ipc = 1, \
712 IVB_CURSOR_OFFSETS, \
714 GEN9_DEFAULT_PAGE_SIZES, \
717 static const struct intel_device_info bxt_info = {
719 PLATFORM(INTEL_BROXTON),
723 static const struct intel_device_info glk_info = {
725 PLATFORM(INTEL_GEMINILAKE),
730 #define KBL_PLATFORM \
732 PLATFORM(INTEL_KABYLAKE)
734 static const struct intel_device_info kbl_gt1_info = {
739 static const struct intel_device_info kbl_gt2_info = {
744 static const struct intel_device_info kbl_gt3_info = {
747 .platform_engine_mask =
748 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
751 #define CFL_PLATFORM \
753 PLATFORM(INTEL_COFFEELAKE)
755 static const struct intel_device_info cfl_gt1_info = {
760 static const struct intel_device_info cfl_gt2_info = {
765 static const struct intel_device_info cfl_gt3_info = {
768 .platform_engine_mask =
769 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
772 #define CML_PLATFORM \
774 PLATFORM(INTEL_COMETLAKE)
776 static const struct intel_device_info cml_gt1_info = {
781 static const struct intel_device_info cml_gt2_info = {
786 #define GEN10_FEATURES \
790 .display.has_dsc = 1, \
791 .has_coherent_ggtt = false, \
794 static const struct intel_device_info cnl_info = {
796 PLATFORM(INTEL_CANNONLAKE),
800 #define GEN11_DEFAULT_PAGE_SIZES \
801 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
802 I915_GTT_PAGE_SIZE_64K | \
803 I915_GTT_PAGE_SIZE_2M
805 #define GEN11_FEATURES \
807 GEN11_DEFAULT_PAGE_SIZES, \
808 .abox_mask = BIT(0), \
809 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
810 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
811 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
813 [TRANSCODER_A] = PIPE_A_OFFSET, \
814 [TRANSCODER_B] = PIPE_B_OFFSET, \
815 [TRANSCODER_C] = PIPE_C_OFFSET, \
816 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
817 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
818 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
821 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
822 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
823 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
824 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
825 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
826 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
830 .num_supported_dbuf_slices = 2, \
831 .has_logical_ring_elsq = 1, \
832 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
834 static const struct intel_device_info icl_info = {
836 PLATFORM(INTEL_ICELAKE),
837 .platform_engine_mask =
838 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
841 static const struct intel_device_info ehl_info = {
843 PLATFORM(INTEL_ELKHARTLAKE),
844 .require_force_probe = 1,
845 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
849 static const struct intel_device_info jsl_info = {
851 PLATFORM(INTEL_JASPERLAKE),
852 .require_force_probe = 1,
853 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
857 #define GEN12_FEATURES \
860 .abox_mask = GENMASK(2, 1), \
861 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
862 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
863 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
864 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
866 [TRANSCODER_A] = PIPE_A_OFFSET, \
867 [TRANSCODER_B] = PIPE_B_OFFSET, \
868 [TRANSCODER_C] = PIPE_C_OFFSET, \
869 [TRANSCODER_D] = PIPE_D_OFFSET, \
870 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
871 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
874 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
875 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
876 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
877 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
878 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
879 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
881 TGL_CURSOR_OFFSETS, \
882 .has_global_mocs = 1, \
885 static const struct intel_device_info tgl_info = {
887 PLATFORM(INTEL_TIGERLAKE),
888 .display.has_modular_fia = 1,
889 .platform_engine_mask =
890 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
893 static const struct intel_device_info rkl_info = {
895 PLATFORM(INTEL_ROCKETLAKE),
897 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
898 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
900 .display.has_hti = 1,
901 .display.has_psr_hw_tracking = 0,
902 .platform_engine_mask =
903 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
906 #define GEN12_DGFX_FEATURES \
908 .memory_regions = REGION_SMEM | REGION_LMEM, \
909 .has_master_unit_irq = 1, \
914 static const struct intel_device_info dg1_info __maybe_unused = {
917 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
918 .require_force_probe = 1,
919 .platform_engine_mask =
920 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
921 BIT(VCS0) | BIT(VCS2),
926 static const struct intel_device_info adl_s_info = {
928 PLATFORM(INTEL_ALDERLAKE_S),
929 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
930 .require_force_probe = 1,
931 .display.has_hti = 1,
932 .display.has_psr_hw_tracking = 0,
933 .platform_engine_mask =
934 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
942 * Make sure any device matches here are from most specific to most
943 * general. For example, since the Quanta match is based on the subsystem
944 * and subvendor IDs, we need it to come before the more general IVB
945 * PCI ID matches, otherwise we'll use the wrong info struct above.
947 static const struct pci_device_id pciidlist[] = {
948 INTEL_I830_IDS(&i830_info),
949 INTEL_I845G_IDS(&i845g_info),
950 INTEL_I85X_IDS(&i85x_info),
951 INTEL_I865G_IDS(&i865g_info),
952 INTEL_I915G_IDS(&i915g_info),
953 INTEL_I915GM_IDS(&i915gm_info),
954 INTEL_I945G_IDS(&i945g_info),
955 INTEL_I945GM_IDS(&i945gm_info),
956 INTEL_I965G_IDS(&i965g_info),
957 INTEL_G33_IDS(&g33_info),
958 INTEL_I965GM_IDS(&i965gm_info),
959 INTEL_GM45_IDS(&gm45_info),
960 INTEL_G45_IDS(&g45_info),
961 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
962 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
963 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
964 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
965 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
966 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
967 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
968 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
969 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
970 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
971 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
972 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
973 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
974 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
975 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
976 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
977 INTEL_VLV_IDS(&vlv_info),
978 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
979 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
980 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
981 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
982 INTEL_CHV_IDS(&chv_info),
983 INTEL_SKL_GT1_IDS(&skl_gt1_info),
984 INTEL_SKL_GT2_IDS(&skl_gt2_info),
985 INTEL_SKL_GT3_IDS(&skl_gt3_info),
986 INTEL_SKL_GT4_IDS(&skl_gt4_info),
987 INTEL_BXT_IDS(&bxt_info),
988 INTEL_GLK_IDS(&glk_info),
989 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
990 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
991 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
992 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
993 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
994 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
995 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
996 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
997 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
998 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
999 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1000 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1001 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1002 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1003 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1004 INTEL_CML_GT1_IDS(&cml_gt1_info),
1005 INTEL_CML_GT2_IDS(&cml_gt2_info),
1006 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1007 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1008 INTEL_CNL_IDS(&cnl_info),
1009 INTEL_ICL_11_IDS(&icl_info),
1010 INTEL_EHL_IDS(&ehl_info),
1011 INTEL_JSL_IDS(&jsl_info),
1012 INTEL_TGL_12_IDS(&tgl_info),
1013 INTEL_RKL_IDS(&rkl_info),
1014 INTEL_ADLS_IDS(&adl_s_info),
1017 MODULE_DEVICE_TABLE(pci, pciidlist);
1019 static void i915_pci_remove(struct pci_dev *pdev)
1021 struct drm_i915_private *i915;
1023 i915 = pci_get_drvdata(pdev);
1024 if (!i915) /* driver load aborted, nothing to cleanup */
1027 i915_driver_remove(i915);
1028 pci_set_drvdata(pdev, NULL);
1031 /* is device_id present in comma separated list of ids */
1032 static bool force_probe(u16 device_id, const char *devices)
1037 if (!devices || !*devices)
1040 /* match everything */
1041 if (strcmp(devices, "*") == 0)
1044 s = kstrdup(devices, GFP_KERNEL);
1048 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1051 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1062 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1064 struct intel_device_info *intel_info =
1065 (struct intel_device_info *) ent->driver_data;
1068 if (intel_info->require_force_probe &&
1069 !force_probe(pdev->device, i915_modparams.force_probe)) {
1070 dev_info(&pdev->dev,
1071 "Your graphics device %04x is not properly supported by the driver in this\n"
1072 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1073 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1074 "or (recommended) check for kernel updates.\n",
1075 pdev->device, pdev->device, pdev->device);
1079 /* Only bind to function 0 of the device. Early generations
1080 * used function 1 as a placeholder for multi-head. This causes
1081 * us confusion instead, especially on the systems where both
1082 * functions have the same PCI-ID!
1084 if (PCI_FUNC(pdev->devfn))
1088 * apple-gmux is needed on dual GPU MacBook Pro
1089 * to probe the panel if we're the inactive GPU.
1091 if (vga_switcheroo_client_probe_defer(pdev))
1092 return -EPROBE_DEFER;
1094 err = i915_driver_probe(pdev, ent);
1098 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1099 i915_pci_remove(pdev);
1103 err = i915_live_selftests(pdev);
1105 i915_pci_remove(pdev);
1106 return err > 0 ? -ENOTTY : err;
1109 err = i915_perf_selftests(pdev);
1111 i915_pci_remove(pdev);
1112 return err > 0 ? -ENOTTY : err;
1118 static void i915_pci_shutdown(struct pci_dev *pdev)
1120 struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1122 i915_driver_shutdown(i915);
1125 static struct pci_driver i915_pci_driver = {
1126 .name = DRIVER_NAME,
1127 .id_table = pciidlist,
1128 .probe = i915_pci_probe,
1129 .remove = i915_pci_remove,
1130 .shutdown = i915_pci_shutdown,
1131 .driver.pm = &i915_pm_ops,
1134 static int __init i915_init(void)
1136 bool use_kms = true;
1139 err = i915_globals_init();
1143 err = i915_mock_selftests();
1145 return err > 0 ? 0 : err;
1148 * Enable KMS by default, unless explicitly overriden by
1149 * either the i915.modeset prarameter or by the
1150 * vga_text_mode_force boot option.
1153 if (i915_modparams.modeset == 0)
1156 if (vgacon_text_force() && i915_modparams.modeset == -1)
1160 /* Silently fail loading to not upset userspace. */
1161 DRM_DEBUG_DRIVER("KMS disabled.\n");
1167 err = pci_register_driver(&i915_pci_driver);
1173 i915_perf_sysctl_register();
1177 static void __exit i915_exit(void)
1179 if (!i915_pci_driver.driver.owner)
1182 i915_perf_sysctl_unregister();
1183 pci_unregister_driver(&i915_pci_driver);
1184 i915_globals_exit();
1188 module_init(i915_init);
1189 module_exit(i915_exit);
1191 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1192 MODULE_AUTHOR("Intel Corporation");
1194 MODULE_DESCRIPTION(DRIVER_DESC);
1195 MODULE_LICENSE("GPL and additional rights");