drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_color_mgmt.h>
  26 #include <drm/drm_drv.h>
  27 #include <drm/i915_pciids.h>
  28
  29 #include "i915_driver.h"
  30 #include "i915_drv.h"
  31 #include "i915_pci.h"
  32 #include "i915_reg.h"
  33 #include "intel_pci_config.h"
  34
  35 #define PLATFORM(x) .platform = (x)
  36 #define GEN(x) \
  37         .__runtime.graphics.ver = (x), \
  38         .media.ver = (x), \
  39         .display.ver = (x)
  40
  41 #define I845_PIPE_OFFSETS \
  42         .display.pipe_offsets = { \
  43                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  44         }, \
  45         .display.trans_offsets = { \
  46                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  47         }
  48
  49 #define I9XX_PIPE_OFFSETS \
  50         .display.pipe_offsets = { \
  51                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  52                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  53         }, \
  54         .display.trans_offsets = { \
  55                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  56                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  57         }
  58
  59 #define IVB_PIPE_OFFSETS \
  60         .display.pipe_offsets = { \
  61                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  62                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  63                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  64         }, \
  65         .display.trans_offsets = { \
  66                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  67                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  68                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  69         }
  70
  71 #define HSW_PIPE_OFFSETS \
  72         .display.pipe_offsets = { \
  73                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  74                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  75                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  76                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  77         }, \
  78         .display.trans_offsets = { \
  79                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  80                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  81                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  82                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  83         }
  84
  85 #define CHV_PIPE_OFFSETS \
  86         .display.pipe_offsets = { \
  87                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  88                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  89                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  90         }, \
  91         .display.trans_offsets = { \
  92                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  93                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  94                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  95         }
  96
  97 #define I845_CURSOR_OFFSETS \
  98         .display.cursor_offsets = { \
  99                 [PIPE_A] = CURSOR_A_OFFSET, \
 100         }
 101
 102 #define I9XX_CURSOR_OFFSETS \
 103         .display.cursor_offsets = { \
 104                 [PIPE_A] = CURSOR_A_OFFSET, \
 105                 [PIPE_B] = CURSOR_B_OFFSET, \
 106         }
 107
 108 #define CHV_CURSOR_OFFSETS \
 109         .display.cursor_offsets = { \
 110                 [PIPE_A] = CURSOR_A_OFFSET, \
 111                 [PIPE_B] = CURSOR_B_OFFSET, \
 112                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 113         }
 114
 115 #define IVB_CURSOR_OFFSETS \
 116         .display.cursor_offsets = { \
 117                 [PIPE_A] = CURSOR_A_OFFSET, \
 118                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 119                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 120         }
 121
 122 #define TGL_CURSOR_OFFSETS \
 123         .display.cursor_offsets = { \
 124                 [PIPE_A] = CURSOR_A_OFFSET, \
 125                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 126                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 127                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 128         }
 129
 130 #define I9XX_COLORS \
 131         .display.color = { .gamma_lut_size = 256 }
 132 #define I965_COLORS \
 133         .display.color = { .gamma_lut_size = 129, \
 134                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 135         }
 136 #define ILK_COLORS \
 137         .display.color = { .gamma_lut_size = 1024 }
 138 #define IVB_COLORS \
 139         .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 140 #define CHV_COLORS \
 141         .display.color = { \
 142                 .degamma_lut_size = 65, .gamma_lut_size = 257, \
 143                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 144                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 145         }
 146 #define GLK_COLORS \
 147         .display.color = { \
 148                 .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 149                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 150                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 151         }
 152 #define ICL_COLORS \
 153         .display.color = { \
 154                 .degamma_lut_size = 33, .gamma_lut_size = 262145, \
 155                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 156                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 157                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 158         }
 159
 160 /* Keep in gen based order, and chronological order within a gen */
 161
 162 #define GEN_DEFAULT_PAGE_SIZES \
 163         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
 164
 165 #define GEN_DEFAULT_REGIONS \
 166         .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 167
 168 #define I830_FEATURES \
 169         GEN(2), \
 170         .is_mobile = 1, \
 171         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 172         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 173         .display.has_overlay = 1, \
 174         .display.cursor_needs_physical = 1, \
 175         .display.overlay_needs_physical = 1, \
 176         .display.has_gmch = 1, \
 177         .gpu_reset_clobbers_display = true, \
 178         .has_3d_pipeline = 1, \
 179         .hws_needs_physical = 1, \
 180         .unfenced_needs_alignment = 1, \
 181         .__runtime.platform_engine_mask = BIT(RCS0), \
 182         .has_snoop = true, \
 183         .has_coherent_ggtt = false, \
 184         .dma_mask_size = 32, \
 185         I9XX_PIPE_OFFSETS, \
 186         I9XX_CURSOR_OFFSETS, \
 187         I9XX_COLORS, \
 188         GEN_DEFAULT_PAGE_SIZES, \
 189         GEN_DEFAULT_REGIONS
 190
 191 #define I845_FEATURES \
 192         GEN(2), \
 193         .display.pipe_mask = BIT(PIPE_A), \
 194         .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
 195         .display.has_overlay = 1, \
 196         .display.overlay_needs_physical = 1, \
 197         .display.has_gmch = 1, \
 198         .has_3d_pipeline = 1, \
 199         .gpu_reset_clobbers_display = true, \
 200         .hws_needs_physical = 1, \
 201         .unfenced_needs_alignment = 1, \
 202         .__runtime.platform_engine_mask = BIT(RCS0), \
 203         .has_snoop = true, \
 204         .has_coherent_ggtt = false, \
 205         .dma_mask_size = 32, \
 206         I845_PIPE_OFFSETS, \
 207         I845_CURSOR_OFFSETS, \
 208         I9XX_COLORS, \
 209         GEN_DEFAULT_PAGE_SIZES, \
 210         GEN_DEFAULT_REGIONS
 211
 212 static const struct intel_device_info i830_info = {
 213         I830_FEATURES,
 214         PLATFORM(INTEL_I830),
 215 };
 216
 217 static const struct intel_device_info i845g_info = {
 218         I845_FEATURES,
 219         PLATFORM(INTEL_I845G),
 220 };
 221
 222 static const struct intel_device_info i85x_info = {
 223         I830_FEATURES,
 224         PLATFORM(INTEL_I85X),
 225         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 226 };
 227
 228 static const struct intel_device_info i865g_info = {
 229         I845_FEATURES,
 230         PLATFORM(INTEL_I865G),
 231         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 232 };
 233
 234 #define GEN3_FEATURES \
 235         GEN(3), \
 236         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 237         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 238         .display.has_gmch = 1, \
 239         .gpu_reset_clobbers_display = true, \
 240         .__runtime.platform_engine_mask = BIT(RCS0), \
 241         .has_3d_pipeline = 1, \
 242         .has_snoop = true, \
 243         .has_coherent_ggtt = true, \
 244         .dma_mask_size = 32, \
 245         I9XX_PIPE_OFFSETS, \
 246         I9XX_CURSOR_OFFSETS, \
 247         I9XX_COLORS, \
 248         GEN_DEFAULT_PAGE_SIZES, \
 249         GEN_DEFAULT_REGIONS
 250
 251 static const struct intel_device_info i915g_info = {
 252         GEN3_FEATURES,
 253         PLATFORM(INTEL_I915G),
 254         .has_coherent_ggtt = false,
 255         .display.cursor_needs_physical = 1,
 256         .display.has_overlay = 1,
 257         .display.overlay_needs_physical = 1,
 258         .hws_needs_physical = 1,
 259         .unfenced_needs_alignment = 1,
 260 };
 261
 262 static const struct intel_device_info i915gm_info = {
 263         GEN3_FEATURES,
 264         PLATFORM(INTEL_I915GM),
 265         .is_mobile = 1,
 266         .display.cursor_needs_physical = 1,
 267         .display.has_overlay = 1,
 268         .display.overlay_needs_physical = 1,
 269         .display.supports_tv = 1,
 270         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 271         .hws_needs_physical = 1,
 272         .unfenced_needs_alignment = 1,
 273 };
 274
 275 static const struct intel_device_info i945g_info = {
 276         GEN3_FEATURES,
 277         PLATFORM(INTEL_I945G),
 278         .display.has_hotplug = 1,
 279         .display.cursor_needs_physical = 1,
 280         .display.has_overlay = 1,
 281         .display.overlay_needs_physical = 1,
 282         .hws_needs_physical = 1,
 283         .unfenced_needs_alignment = 1,
 284 };
 285
 286 static const struct intel_device_info i945gm_info = {
 287         GEN3_FEATURES,
 288         PLATFORM(INTEL_I945GM),
 289         .is_mobile = 1,
 290         .display.has_hotplug = 1,
 291         .display.cursor_needs_physical = 1,
 292         .display.has_overlay = 1,
 293         .display.overlay_needs_physical = 1,
 294         .display.supports_tv = 1,
 295         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 296         .hws_needs_physical = 1,
 297         .unfenced_needs_alignment = 1,
 298 };
 299
 300 static const struct intel_device_info g33_info = {
 301         GEN3_FEATURES,
 302         PLATFORM(INTEL_G33),
 303         .display.has_hotplug = 1,
 304         .display.has_overlay = 1,
 305         .dma_mask_size = 36,
 306 };
 307
 308 static const struct intel_device_info pnv_g_info = {
 309         GEN3_FEATURES,
 310         PLATFORM(INTEL_PINEVIEW),
 311         .display.has_hotplug = 1,
 312         .display.has_overlay = 1,
 313         .dma_mask_size = 36,
 314 };
 315
 316 static const struct intel_device_info pnv_m_info = {
 317         GEN3_FEATURES,
 318         PLATFORM(INTEL_PINEVIEW),
 319         .is_mobile = 1,
 320         .display.has_hotplug = 1,
 321         .display.has_overlay = 1,
 322         .dma_mask_size = 36,
 323 };
 324
 325 #define GEN4_FEATURES \
 326         GEN(4), \
 327         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 328         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 329         .display.has_hotplug = 1, \
 330         .display.has_gmch = 1, \
 331         .gpu_reset_clobbers_display = true, \
 332         .__runtime.platform_engine_mask = BIT(RCS0), \
 333         .has_3d_pipeline = 1, \
 334         .has_snoop = true, \
 335         .has_coherent_ggtt = true, \
 336         .dma_mask_size = 36, \
 337         I9XX_PIPE_OFFSETS, \
 338         I9XX_CURSOR_OFFSETS, \
 339         I965_COLORS, \
 340         GEN_DEFAULT_PAGE_SIZES, \
 341         GEN_DEFAULT_REGIONS
 342
 343 static const struct intel_device_info i965g_info = {
 344         GEN4_FEATURES,
 345         PLATFORM(INTEL_I965G),
 346         .display.has_overlay = 1,
 347         .hws_needs_physical = 1,
 348         .has_snoop = false,
 349 };
 350
 351 static const struct intel_device_info i965gm_info = {
 352         GEN4_FEATURES,
 353         PLATFORM(INTEL_I965GM),
 354         .is_mobile = 1,
 355         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 356         .display.has_overlay = 1,
 357         .display.supports_tv = 1,
 358         .hws_needs_physical = 1,
 359         .has_snoop = false,
 360 };
 361
 362 static const struct intel_device_info g45_info = {
 363         GEN4_FEATURES,
 364         PLATFORM(INTEL_G45),
 365         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 366         .gpu_reset_clobbers_display = false,
 367 };
 368
 369 static const struct intel_device_info gm45_info = {
 370         GEN4_FEATURES,
 371         PLATFORM(INTEL_GM45),
 372         .is_mobile = 1,
 373         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 374         .display.supports_tv = 1,
 375         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 376         .gpu_reset_clobbers_display = false,
 377 };
 378
 379 #define GEN5_FEATURES \
 380         GEN(5), \
 381         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 382         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 383         .display.has_hotplug = 1, \
 384         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 385         .has_3d_pipeline = 1, \
 386         .has_snoop = true, \
 387         .has_coherent_ggtt = true, \
 388         /* ilk does support rc6, but we do not implement [power] contexts */ \
 389         .has_rc6 = 0, \
 390         .dma_mask_size = 36, \
 391         I9XX_PIPE_OFFSETS, \
 392         I9XX_CURSOR_OFFSETS, \
 393         ILK_COLORS, \
 394         GEN_DEFAULT_PAGE_SIZES, \
 395         GEN_DEFAULT_REGIONS
 396
 397 static const struct intel_device_info ilk_d_info = {
 398         GEN5_FEATURES,
 399         PLATFORM(INTEL_IRONLAKE),
 400 };
 401
 402 static const struct intel_device_info ilk_m_info = {
 403         GEN5_FEATURES,
 404         PLATFORM(INTEL_IRONLAKE),
 405         .is_mobile = 1,
 406         .has_rps = true,
 407         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 408 };
 409
 410 #define GEN6_FEATURES \
 411         GEN(6), \
 412         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 413         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 414         .display.has_hotplug = 1, \
 415         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 416         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 417         .has_3d_pipeline = 1, \
 418         .has_coherent_ggtt = true, \
 419         .has_llc = 1, \
 420         .has_rc6 = 1, \
 421         .has_rc6p = 1, \
 422         .has_rps = true, \
 423         .dma_mask_size = 40, \
 424         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 425         .__runtime.ppgtt_size = 31, \
 426         I9XX_PIPE_OFFSETS, \
 427         I9XX_CURSOR_OFFSETS, \
 428         ILK_COLORS, \
 429         GEN_DEFAULT_PAGE_SIZES, \
 430         GEN_DEFAULT_REGIONS
 431
 432 #define SNB_D_PLATFORM \
 433         GEN6_FEATURES, \
 434         PLATFORM(INTEL_SANDYBRIDGE)
 435
 436 static const struct intel_device_info snb_d_gt1_info = {
 437         SNB_D_PLATFORM,
 438         .gt = 1,
 439 };
 440
 441 static const struct intel_device_info snb_d_gt2_info = {
 442         SNB_D_PLATFORM,
 443         .gt = 2,
 444 };
 445
 446 #define SNB_M_PLATFORM \
 447         GEN6_FEATURES, \
 448         PLATFORM(INTEL_SANDYBRIDGE), \
 449         .is_mobile = 1
 450
 451
 452 static const struct intel_device_info snb_m_gt1_info = {
 453         SNB_M_PLATFORM,
 454         .gt = 1,
 455 };
 456
 457 static const struct intel_device_info snb_m_gt2_info = {
 458         SNB_M_PLATFORM,
 459         .gt = 2,
 460 };
 461
 462 #define GEN7_FEATURES  \
 463         GEN(7), \
 464         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 465         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 466         .display.has_hotplug = 1, \
 467         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 468         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 469         .has_3d_pipeline = 1, \
 470         .has_coherent_ggtt = true, \
 471         .has_llc = 1, \
 472         .has_rc6 = 1, \
 473         .has_rc6p = 1, \
 474         .has_reset_engine = true, \
 475         .has_rps = true, \
 476         .dma_mask_size = 40, \
 477         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 478         .__runtime.ppgtt_size = 31, \
 479         IVB_PIPE_OFFSETS, \
 480         IVB_CURSOR_OFFSETS, \
 481         IVB_COLORS, \
 482         GEN_DEFAULT_PAGE_SIZES, \
 483         GEN_DEFAULT_REGIONS
 484
 485 #define IVB_D_PLATFORM \
 486         GEN7_FEATURES, \
 487         PLATFORM(INTEL_IVYBRIDGE), \
 488         .has_l3_dpf = 1
 489
 490 static const struct intel_device_info ivb_d_gt1_info = {
 491         IVB_D_PLATFORM,
 492         .gt = 1,
 493 };
 494
 495 static const struct intel_device_info ivb_d_gt2_info = {
 496         IVB_D_PLATFORM,
 497         .gt = 2,
 498 };
 499
 500 #define IVB_M_PLATFORM \
 501         GEN7_FEATURES, \
 502         PLATFORM(INTEL_IVYBRIDGE), \
 503         .is_mobile = 1, \
 504         .has_l3_dpf = 1
 505
 506 static const struct intel_device_info ivb_m_gt1_info = {
 507         IVB_M_PLATFORM,
 508         .gt = 1,
 509 };
 510
 511 static const struct intel_device_info ivb_m_gt2_info = {
 512         IVB_M_PLATFORM,
 513         .gt = 2,
 514 };
 515
 516 static const struct intel_device_info ivb_q_info = {
 517         GEN7_FEATURES,
 518         PLATFORM(INTEL_IVYBRIDGE),
 519         .gt = 2,
 520         .display.pipe_mask = 0, /* legal, last one wins */
 521         .display.cpu_transcoder_mask = 0,
 522         .has_l3_dpf = 1,
 523 };
 524
 525 static const struct intel_device_info vlv_info = {
 526         PLATFORM(INTEL_VALLEYVIEW),
 527         GEN(7),
 528         .is_lp = 1,
 529         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 530         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 531         .has_runtime_pm = 1,
 532         .has_rc6 = 1,
 533         .has_reset_engine = true,
 534         .has_rps = true,
 535         .display.has_gmch = 1,
 536         .display.has_hotplug = 1,
 537         .dma_mask_size = 40,
 538         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
 539         .__runtime.ppgtt_size = 31,
 540         .has_snoop = true,
 541         .has_coherent_ggtt = false,
 542         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 543         .display.mmio_offset = VLV_DISPLAY_BASE,
 544         I9XX_PIPE_OFFSETS,
 545         I9XX_CURSOR_OFFSETS,
 546         I965_COLORS,
 547         GEN_DEFAULT_PAGE_SIZES,
 548         GEN_DEFAULT_REGIONS,
 549 };
 550
 551 #define G75_FEATURES  \
 552         GEN7_FEATURES, \
 553         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 554         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 555                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 556         .display.has_ddi = 1, \
 557         .display.has_fpga_dbg = 1, \
 558         .display.has_dp_mst = 1, \
 559         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 560         HSW_PIPE_OFFSETS, \
 561         .has_runtime_pm = 1
 562
 563 #define HSW_PLATFORM \
 564         G75_FEATURES, \
 565         PLATFORM(INTEL_HASWELL), \
 566         .has_l3_dpf = 1
 567
 568 static const struct intel_device_info hsw_gt1_info = {
 569         HSW_PLATFORM,
 570         .gt = 1,
 571 };
 572
 573 static const struct intel_device_info hsw_gt2_info = {
 574         HSW_PLATFORM,
 575         .gt = 2,
 576 };
 577
 578 static const struct intel_device_info hsw_gt3_info = {
 579         HSW_PLATFORM,
 580         .gt = 3,
 581 };
 582
 583 #define GEN8_FEATURES \
 584         G75_FEATURES, \
 585         GEN(8), \
 586         .has_logical_ring_contexts = 1, \
 587         .dma_mask_size = 39, \
 588         .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
 589         .__runtime.ppgtt_size = 48, \
 590         .has_64bit_reloc = 1
 591
 592 #define BDW_PLATFORM \
 593         GEN8_FEATURES, \
 594         PLATFORM(INTEL_BROADWELL)
 595
 596 static const struct intel_device_info bdw_gt1_info = {
 597         BDW_PLATFORM,
 598         .gt = 1,
 599 };
 600
 601 static const struct intel_device_info bdw_gt2_info = {
 602         BDW_PLATFORM,
 603         .gt = 2,
 604 };
 605
 606 static const struct intel_device_info bdw_rsvd_info = {
 607         BDW_PLATFORM,
 608         .gt = 3,
 609         /* According to the device ID those devices are GT3, they were
 610          * previously treated as not GT3, keep it like that.
 611          */
 612 };
 613
 614 static const struct intel_device_info bdw_gt3_info = {
 615         BDW_PLATFORM,
 616         .gt = 3,
 617         .__runtime.platform_engine_mask =
 618                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 619 };
 620
 621 static const struct intel_device_info chv_info = {
 622         PLATFORM(INTEL_CHERRYVIEW),
 623         GEN(8),
 624         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 625         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 626         .display.has_hotplug = 1,
 627         .is_lp = 1,
 628         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 629         .has_64bit_reloc = 1,
 630         .has_runtime_pm = 1,
 631         .has_rc6 = 1,
 632         .has_rps = true,
 633         .has_logical_ring_contexts = 1,
 634         .display.has_gmch = 1,
 635         .dma_mask_size = 39,
 636         .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
 637         .__runtime.ppgtt_size = 32,
 638         .has_reset_engine = 1,
 639         .has_snoop = true,
 640         .has_coherent_ggtt = false,
 641         .display.mmio_offset = VLV_DISPLAY_BASE,
 642         CHV_PIPE_OFFSETS,
 643         CHV_CURSOR_OFFSETS,
 644         CHV_COLORS,
 645         GEN_DEFAULT_PAGE_SIZES,
 646         GEN_DEFAULT_REGIONS,
 647 };
 648
 649 #define GEN9_DEFAULT_PAGE_SIZES \
 650         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 651                 I915_GTT_PAGE_SIZE_64K
 652
 653 #define GEN9_FEATURES \
 654         GEN8_FEATURES, \
 655         GEN(9), \
 656         GEN9_DEFAULT_PAGE_SIZES, \
 657         .display.has_dmc = 1, \
 658         .has_gt_uc = 1, \
 659         .display.has_hdcp = 1, \
 660         .display.has_ipc = 1, \
 661         .display.has_psr = 1, \
 662         .display.has_psr_hw_tracking = 1, \
 663         .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 664         .display.dbuf.slice_mask = BIT(DBUF_S1)
 665
 666 #define SKL_PLATFORM \
 667         GEN9_FEATURES, \
 668         PLATFORM(INTEL_SKYLAKE)
 669
 670 static const struct intel_device_info skl_gt1_info = {
 671         SKL_PLATFORM,
 672         .gt = 1,
 673 };
 674
 675 static const struct intel_device_info skl_gt2_info = {
 676         SKL_PLATFORM,
 677         .gt = 2,
 678 };
 679
 680 #define SKL_GT3_PLUS_PLATFORM \
 681         SKL_PLATFORM, \
 682         .__runtime.platform_engine_mask = \
 683                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 684
 685
 686 static const struct intel_device_info skl_gt3_info = {
 687         SKL_GT3_PLUS_PLATFORM,
 688         .gt = 3,
 689 };
 690
 691 static const struct intel_device_info skl_gt4_info = {
 692         SKL_GT3_PLUS_PLATFORM,
 693         .gt = 4,
 694 };
 695
 696 #define GEN9_LP_FEATURES \
 697         GEN(9), \
 698         .is_lp = 1, \
 699         .display.dbuf.slice_mask = BIT(DBUF_S1), \
 700         .display.has_hotplug = 1, \
 701         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 702         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 703         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 704                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 705                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 706         .has_3d_pipeline = 1, \
 707         .has_64bit_reloc = 1, \
 708         .display.has_ddi = 1, \
 709         .display.has_fpga_dbg = 1, \
 710         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 711         .display.has_hdcp = 1, \
 712         .display.has_psr = 1, \
 713         .display.has_psr_hw_tracking = 1, \
 714         .has_runtime_pm = 1, \
 715         .display.has_dmc = 1, \
 716         .has_rc6 = 1, \
 717         .has_rps = true, \
 718         .display.has_dp_mst = 1, \
 719         .has_logical_ring_contexts = 1, \
 720         .has_gt_uc = 1, \
 721         .dma_mask_size = 39, \
 722         .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
 723         .__runtime.ppgtt_size = 48, \
 724         .has_reset_engine = 1, \
 725         .has_snoop = true, \
 726         .has_coherent_ggtt = false, \
 727         .display.has_ipc = 1, \
 728         HSW_PIPE_OFFSETS, \
 729         IVB_CURSOR_OFFSETS, \
 730         IVB_COLORS, \
 731         GEN9_DEFAULT_PAGE_SIZES, \
 732         GEN_DEFAULT_REGIONS
 733
 734 static const struct intel_device_info bxt_info = {
 735         GEN9_LP_FEATURES,
 736         PLATFORM(INTEL_BROXTON),
 737         .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 738 };
 739
 740 static const struct intel_device_info glk_info = {
 741         GEN9_LP_FEATURES,
 742         PLATFORM(INTEL_GEMINILAKE),
 743         .display.ver = 10,
 744         .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 745         GLK_COLORS,
 746 };
 747
 748 #define KBL_PLATFORM \
 749         GEN9_FEATURES, \
 750         PLATFORM(INTEL_KABYLAKE)
 751
 752 static const struct intel_device_info kbl_gt1_info = {
 753         KBL_PLATFORM,
 754         .gt = 1,
 755 };
 756
 757 static const struct intel_device_info kbl_gt2_info = {
 758         KBL_PLATFORM,
 759         .gt = 2,
 760 };
 761
 762 static const struct intel_device_info kbl_gt3_info = {
 763         KBL_PLATFORM,
 764         .gt = 3,
 765         .__runtime.platform_engine_mask =
 766                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 767 };
 768
 769 #define CFL_PLATFORM \
 770         GEN9_FEATURES, \
 771         PLATFORM(INTEL_COFFEELAKE)
 772
 773 static const struct intel_device_info cfl_gt1_info = {
 774         CFL_PLATFORM,
 775         .gt = 1,
 776 };
 777
 778 static const struct intel_device_info cfl_gt2_info = {
 779         CFL_PLATFORM,
 780         .gt = 2,
 781 };
 782
 783 static const struct intel_device_info cfl_gt3_info = {
 784         CFL_PLATFORM,
 785         .gt = 3,
 786         .__runtime.platform_engine_mask =
 787                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 788 };
 789
 790 #define CML_PLATFORM \
 791         GEN9_FEATURES, \
 792         PLATFORM(INTEL_COMETLAKE)
 793
 794 static const struct intel_device_info cml_gt1_info = {
 795         CML_PLATFORM,
 796         .gt = 1,
 797 };
 798
 799 static const struct intel_device_info cml_gt2_info = {
 800         CML_PLATFORM,
 801         .gt = 2,
 802 };
 803
 804 #define GEN11_DEFAULT_PAGE_SIZES \
 805         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 806                 I915_GTT_PAGE_SIZE_64K |                \
 807                 I915_GTT_PAGE_SIZE_2M
 808
 809 #define GEN11_FEATURES \
 810         GEN9_FEATURES, \
 811         GEN11_DEFAULT_PAGE_SIZES, \
 812         .display.abox_mask = BIT(0), \
 813         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 814                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 815                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 816         .display.pipe_offsets = { \
 817                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 818                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 819                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 820                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 821                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 822                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 823         }, \
 824         .display.trans_offsets = { \
 825                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 826                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 827                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 828                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 829                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 830                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 831         }, \
 832         GEN(11), \
 833         ICL_COLORS, \
 834         .display.dbuf.size = 2048, \
 835         .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 836         .display.has_dsc = 1, \
 837         .has_coherent_ggtt = false, \
 838         .has_logical_ring_elsq = 1
 839
 840 static const struct intel_device_info icl_info = {
 841         GEN11_FEATURES,
 842         PLATFORM(INTEL_ICELAKE),
 843         .__runtime.platform_engine_mask =
 844                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 845 };
 846
 847 static const struct intel_device_info ehl_info = {
 848         GEN11_FEATURES,
 849         PLATFORM(INTEL_ELKHARTLAKE),
 850         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 851         .__runtime.ppgtt_size = 36,
 852 };
 853
 854 static const struct intel_device_info jsl_info = {
 855         GEN11_FEATURES,
 856         PLATFORM(INTEL_JASPERLAKE),
 857         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 858         .__runtime.ppgtt_size = 36,
 859 };
 860
 861 #define GEN12_FEATURES \
 862         GEN11_FEATURES, \
 863         GEN(12), \
 864         .display.abox_mask = GENMASK(2, 1), \
 865         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 866         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 867                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 868                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 869         .display.pipe_offsets = { \
 870                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 871                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 872                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 873                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 874                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 875                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 876         }, \
 877         .display.trans_offsets = { \
 878                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 879                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 880                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 881                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 882                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 883                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 884         }, \
 885         TGL_CURSOR_OFFSETS, \
 886         .has_global_mocs = 1, \
 887         .has_pxp = 1, \
 888         .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
 889
 890 static const struct intel_device_info tgl_info = {
 891         GEN12_FEATURES,
 892         PLATFORM(INTEL_TIGERLAKE),
 893         .display.has_modular_fia = 1,
 894         .__runtime.platform_engine_mask =
 895                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 896 };
 897
 898 static const struct intel_device_info rkl_info = {
 899         GEN12_FEATURES,
 900         PLATFORM(INTEL_ROCKETLAKE),
 901         .display.abox_mask = BIT(0),
 902         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 903         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 904                 BIT(TRANSCODER_C),
 905         .display.has_hti = 1,
 906         .display.has_psr_hw_tracking = 0,
 907         .__runtime.platform_engine_mask =
 908                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 909 };
 910
 911 #define DGFX_FEATURES \
 912         .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
 913         .has_llc = 0, \
 914         .has_pxp = 0, \
 915         .has_snoop = 1, \
 916         .is_dgfx = 1, \
 917         .has_heci_gscfi = 1
 918
 919 static const struct intel_device_info dg1_info = {
 920         GEN12_FEATURES,
 921         DGFX_FEATURES,
 922         .__runtime.graphics.rel = 10,
 923         PLATFORM(INTEL_DG1),
 924         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 925         .require_force_probe = 1,
 926         .__runtime.platform_engine_mask =
 927                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 928                 BIT(VCS0) | BIT(VCS2),
 929         /* Wa_16011227922 */
 930         .__runtime.ppgtt_size = 47,
 931 };
 932
 933 static const struct intel_device_info adl_s_info = {
 934         GEN12_FEATURES,
 935         PLATFORM(INTEL_ALDERLAKE_S),
 936         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 937         .display.has_hti = 1,
 938         .display.has_psr_hw_tracking = 0,
 939         .__runtime.platform_engine_mask =
 940                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 941         .dma_mask_size = 39,
 942 };
 943
 944 #define XE_LPD_FEATURES \
 945         .display.abox_mask = GENMASK(1, 0),                                     \
 946         .display.color = {                                                      \
 947                 .degamma_lut_size = 128, .gamma_lut_size = 1024,                \
 948                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |             \
 949                                      DRM_COLOR_LUT_EQUAL_CHANNELS,              \
 950         },                                                                      \
 951         .display.dbuf.size = 4096,                                              \
 952         .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
 953                 BIT(DBUF_S4),                                                   \
 954         .display.has_ddi = 1,                                                   \
 955         .display.has_dmc = 1,                                                   \
 956         .display.has_dp_mst = 1,                                                \
 957         .display.has_dsb = 1,                                                   \
 958         .display.has_dsc = 1,                                                   \
 959         .__runtime.fbc_mask = BIT(INTEL_FBC_A),                                 \
 960         .display.has_fpga_dbg = 1,                                              \
 961         .display.has_hdcp = 1,                                                  \
 962         .display.has_hotplug = 1,                                               \
 963         .display.has_ipc = 1,                                                   \
 964         .display.has_psr = 1,                                                   \
 965         .display.ver = 13,                                                      \
 966         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
 967         .display.pipe_offsets = {                                               \
 968                 [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
 969                 [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
 970                 [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
 971                 [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
 972                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,                          \
 973                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,                          \
 974         },                                                                      \
 975         .display.trans_offsets = {                                              \
 976                 [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
 977                 [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
 978                 [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
 979                 [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
 980                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,                    \
 981                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,                    \
 982         },                                                                      \
 983         TGL_CURSOR_OFFSETS
 984
 985 static const struct intel_device_info adl_p_info = {
 986         GEN12_FEATURES,
 987         XE_LPD_FEATURES,
 988         PLATFORM(INTEL_ALDERLAKE_P),
 989         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 990                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
 991                                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 992         .display.has_cdclk_crawl = 1,
 993         .display.has_modular_fia = 1,
 994         .display.has_psr_hw_tracking = 0,
 995         .__runtime.platform_engine_mask =
 996                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 997         .__runtime.ppgtt_size = 48,
 998         .dma_mask_size = 39,
 999 };
1000
1001 #undef GEN
1002
1003 #define XE_HP_PAGE_SIZES \
1004         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
1005                 I915_GTT_PAGE_SIZE_64K |                \
1006                 I915_GTT_PAGE_SIZE_2M
1007
1008 #define XE_HP_FEATURES \
1009         .__runtime.graphics.ver = 12, \
1010         .__runtime.graphics.rel = 50, \
1011         XE_HP_PAGE_SIZES, \
1012         .dma_mask_size = 46, \
1013         .has_3d_pipeline = 1, \
1014         .has_64bit_reloc = 1, \
1015         .has_flat_ccs = 1, \
1016         .has_global_mocs = 1, \
1017         .has_gt_uc = 1, \
1018         .has_llc = 1, \
1019         .has_logical_ring_contexts = 1, \
1020         .has_logical_ring_elsq = 1, \
1021         .has_mslice_steering = 1, \
1022         .has_rc6 = 1, \
1023         .has_reset_engine = 1, \
1024         .has_rps = 1, \
1025         .has_runtime_pm = 1, \
1026         .__runtime.ppgtt_size = 48, \
1027         .__runtime.ppgtt_type = INTEL_PPGTT_FULL
1028
1029 #define XE_HPM_FEATURES \
1030         .media.ver = 12, \
1031         .media.rel = 50
1032
1033 __maybe_unused
1034 static const struct intel_device_info xehpsdv_info = {
1035         XE_HP_FEATURES,
1036         XE_HPM_FEATURES,
1037         DGFX_FEATURES,
1038         PLATFORM(INTEL_XEHPSDV),
1039         .display = { },
1040         .has_64k_pages = 1,
1041         .needs_compact_pt = 1,
1042         .has_media_ratio_mode = 1,
1043         .__runtime.platform_engine_mask =
1044                 BIT(RCS0) | BIT(BCS0) |
1045                 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1046                 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1047                 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1048                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1049         .require_force_probe = 1,
1050 };
1051
1052 #define DG2_FEATURES \
1053         XE_HP_FEATURES, \
1054         XE_HPM_FEATURES, \
1055         DGFX_FEATURES, \
1056         .__runtime.graphics.rel = 55, \
1057         .media.rel = 55, \
1058         PLATFORM(INTEL_DG2), \
1059         .has_4tile = 1, \
1060         .has_64k_pages = 1, \
1061         .has_guc_deprivilege = 1, \
1062         .has_heci_pxp = 1, \
1063         .needs_compact_pt = 1, \
1064         .has_media_ratio_mode = 1, \
1065         .__runtime.platform_engine_mask = \
1066                 BIT(RCS0) | BIT(BCS0) | \
1067                 BIT(VECS0) | BIT(VECS1) | \
1068                 BIT(VCS0) | BIT(VCS2) | \
1069                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1070
1071 static const struct intel_device_info dg2_info = {
1072         DG2_FEATURES,
1073         XE_LPD_FEATURES,
1074         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1075                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1076         .require_force_probe = 1,
1077 };
1078
1079 static const struct intel_device_info ats_m_info = {
1080         DG2_FEATURES,
1081         .display = { 0 },
1082         .require_force_probe = 1,
1083 };
1084
1085 #define XE_HPC_FEATURES \
1086         XE_HP_FEATURES, \
1087         .dma_mask_size = 52, \
1088         .has_3d_pipeline = 0, \
1089         .has_guc_deprivilege = 1, \
1090         .has_l3_ccs_read = 1, \
1091         .has_mslice_steering = 0, \
1092         .has_one_eu_per_fuse_bit = 1
1093
1094 __maybe_unused
1095 static const struct intel_device_info pvc_info = {
1096         XE_HPC_FEATURES,
1097         XE_HPM_FEATURES,
1098         DGFX_FEATURES,
1099         .__runtime.graphics.rel = 60,
1100         .media.rel = 60,
1101         PLATFORM(INTEL_PONTEVECCHIO),
1102         .display = { 0 },
1103         .has_flat_ccs = 0,
1104         .__runtime.platform_engine_mask =
1105                 BIT(BCS0) |
1106                 BIT(VCS0) |
1107                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1108         .require_force_probe = 1,
1109 };
1110
1111 #define XE_LPDP_FEATURES        \
1112         XE_LPD_FEATURES,        \
1113         .display.ver = 14,      \
1114         .display.has_cdclk_crawl = 1, \
1115         .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
1116
1117 __maybe_unused
1118 static const struct intel_device_info mtl_info = {
1119         XE_HP_FEATURES,
1120         XE_LPDP_FEATURES,
1121         /*
1122          * Real graphics IP version will be obtained from hardware GMD_ID
1123          * register.  Value provided here is just for sanity checking.
1124          */
1125         .__runtime.graphics.ver = 12,
1126         .__runtime.graphics.rel = 70,
1127         .media.ver = 13,
1128         PLATFORM(INTEL_METEORLAKE),
1129         .display.has_modular_fia = 1,
1130         .has_flat_ccs = 0,
1131         .has_snoop = 1,
1132         .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
1133         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
1134         .require_force_probe = 1,
1135 };
1136
1137 #undef PLATFORM
1138
1139 /*
1140  * Make sure any device matches here are from most specific to most
1141  * general.  For example, since the Quanta match is based on the subsystem
1142  * and subvendor IDs, we need it to come before the more general IVB
1143  * PCI ID matches, otherwise we'll use the wrong info struct above.
1144  */
1145 static const struct pci_device_id pciidlist[] = {
1146         INTEL_I830_IDS(&i830_info),
1147         INTEL_I845G_IDS(&i845g_info),
1148         INTEL_I85X_IDS(&i85x_info),
1149         INTEL_I865G_IDS(&i865g_info),
1150         INTEL_I915G_IDS(&i915g_info),
1151         INTEL_I915GM_IDS(&i915gm_info),
1152         INTEL_I945G_IDS(&i945g_info),
1153         INTEL_I945GM_IDS(&i945gm_info),
1154         INTEL_I965G_IDS(&i965g_info),
1155         INTEL_G33_IDS(&g33_info),
1156         INTEL_I965GM_IDS(&i965gm_info),
1157         INTEL_GM45_IDS(&gm45_info),
1158         INTEL_G45_IDS(&g45_info),
1159         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1160         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1161         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1162         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1163         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1164         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1165         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1166         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1167         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1168         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1169         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1170         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1171         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1172         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1173         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1174         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1175         INTEL_VLV_IDS(&vlv_info),
1176         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1177         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1178         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1179         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1180         INTEL_CHV_IDS(&chv_info),
1181         INTEL_SKL_GT1_IDS(&skl_gt1_info),
1182         INTEL_SKL_GT2_IDS(&skl_gt2_info),
1183         INTEL_SKL_GT3_IDS(&skl_gt3_info),
1184         INTEL_SKL_GT4_IDS(&skl_gt4_info),
1185         INTEL_BXT_IDS(&bxt_info),
1186         INTEL_GLK_IDS(&glk_info),
1187         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1188         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1189         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1190         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1191         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1192         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1193         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1194         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1195         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1196         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1197         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1198         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1199         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1200         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1201         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1202         INTEL_CML_GT1_IDS(&cml_gt1_info),
1203         INTEL_CML_GT2_IDS(&cml_gt2_info),
1204         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1205         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1206         INTEL_ICL_11_IDS(&icl_info),
1207         INTEL_EHL_IDS(&ehl_info),
1208         INTEL_JSL_IDS(&jsl_info),
1209         INTEL_TGL_12_IDS(&tgl_info),
1210         INTEL_RKL_IDS(&rkl_info),
1211         INTEL_ADLS_IDS(&adl_s_info),
1212         INTEL_ADLP_IDS(&adl_p_info),
1213         INTEL_ADLN_IDS(&adl_p_info),
1214         INTEL_DG1_IDS(&dg1_info),
1215         INTEL_RPLS_IDS(&adl_s_info),
1216         INTEL_RPLP_IDS(&adl_p_info),
1217         INTEL_DG2_IDS(&dg2_info),
1218         INTEL_ATS_M_IDS(&ats_m_info),
1219         INTEL_MTL_IDS(&mtl_info),
1220         {0, 0, 0}
1221 };
1222 MODULE_DEVICE_TABLE(pci, pciidlist);
1223
1224 static void i915_pci_remove(struct pci_dev *pdev)
1225 {
1226         struct drm_i915_private *i915;
1227
1228         i915 = pci_get_drvdata(pdev);
1229         if (!i915) /* driver load aborted, nothing to cleanup */
1230                 return;
1231
1232         i915_driver_remove(i915);
1233         pci_set_drvdata(pdev, NULL);
1234 }
1235
1236 /* is device_id present in comma separated list of ids */
1237 static bool force_probe(u16 device_id, const char *devices)
1238 {
1239         char *s, *p, *tok;
1240         bool ret;
1241
1242         if (!devices || !*devices)
1243                 return false;
1244
1245         /* match everything */
1246         if (strcmp(devices, "*") == 0)
1247                 return true;
1248
1249         s = kstrdup(devices, GFP_KERNEL);
1250         if (!s)
1251                 return false;
1252
1253         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1254                 u16 val;
1255
1256                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1257                         ret = true;
1258                         break;
1259                 }
1260         }
1261
1262         kfree(s);
1263
1264         return ret;
1265 }
1266
1267 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
1268 {
1269         if (!pci_resource_flags(pdev, bar))
1270                 return false;
1271
1272         if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
1273                 return false;
1274
1275         if (!pci_resource_len(pdev, bar))
1276                 return false;
1277
1278         return true;
1279 }
1280
1281 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
1282 {
1283         int gttmmaddr_bar = intel_info->__runtime.graphics.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
1284
1285         return i915_pci_resource_valid(pdev, gttmmaddr_bar);
1286 }
1287
1288 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1289 {
1290         struct intel_device_info *intel_info =
1291                 (struct intel_device_info *) ent->driver_data;
1292         int err;
1293
1294         if (intel_info->require_force_probe &&
1295             !force_probe(pdev->device, i915_modparams.force_probe)) {
1296                 dev_info(&pdev->dev,
1297                          "Your graphics device %04x is not properly supported by the driver in this\n"
1298                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1299                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1300                          "or (recommended) check for kernel updates.\n",
1301                          pdev->device, pdev->device, pdev->device);
1302                 return -ENODEV;
1303         }
1304
1305         /* Only bind to function 0 of the device. Early generations
1306          * used function 1 as a placeholder for multi-head. This causes
1307          * us confusion instead, especially on the systems where both
1308          * functions have the same PCI-ID!
1309          */
1310         if (PCI_FUNC(pdev->devfn))
1311                 return -ENODEV;
1312
1313         if (!intel_mmio_bar_valid(pdev, intel_info))
1314                 return -ENXIO;
1315
1316         /* Detect if we need to wait for other drivers early on */
1317         if (intel_modeset_probe_defer(pdev))
1318                 return -EPROBE_DEFER;
1319
1320         err = i915_driver_probe(pdev, ent);
1321         if (err)
1322                 return err;
1323
1324         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1325                 i915_pci_remove(pdev);
1326                 return -ENODEV;
1327         }
1328
1329         err = i915_live_selftests(pdev);
1330         if (err) {
1331                 i915_pci_remove(pdev);
1332                 return err > 0 ? -ENOTTY : err;
1333         }
1334
1335         err = i915_perf_selftests(pdev);
1336         if (err) {
1337                 i915_pci_remove(pdev);
1338                 return err > 0 ? -ENOTTY : err;
1339         }
1340
1341         return 0;
1342 }
1343
1344 static void i915_pci_shutdown(struct pci_dev *pdev)
1345 {
1346         struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1347
1348         i915_driver_shutdown(i915);
1349 }
1350
1351 static struct pci_driver i915_pci_driver = {
1352         .name = DRIVER_NAME,
1353         .id_table = pciidlist,
1354         .probe = i915_pci_probe,
1355         .remove = i915_pci_remove,
1356         .shutdown = i915_pci_shutdown,
1357         .driver.pm = &i915_pm_ops,
1358 };
1359
1360 int i915_pci_register_driver(void)
1361 {
1362         return pci_register_driver(&i915_pci_driver);
1363 }
1364
1365 void i915_pci_unregister_driver(void)
1366 {
1367         pci_unregister_driver(&i915_pci_driver);
1368 }