drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vga_switcheroo.h>
  27
  28 #include <drm/drm_drv.h>
  29 #include <drm/i915_pciids.h>
  30
  31 #include "display/intel_fbdev.h"
  32
  33 #include "i915_drv.h"
  34 #include "i915_perf.h"
  35 #include "i915_globals.h"
  36 #include "i915_selftest.h"
  37
  38 #define PLATFORM(x) .platform = (x)
  39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.version = (x)
  40
  41 #define I845_PIPE_OFFSETS \
  42         .pipe_offsets = { \
  43                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  44         }, \
  45         .trans_offsets = { \
  46                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  47         }
  48
  49 #define I9XX_PIPE_OFFSETS \
  50         .pipe_offsets = { \
  51                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  52                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  53         }, \
  54         .trans_offsets = { \
  55                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  56                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  57         }
  58
  59 #define IVB_PIPE_OFFSETS \
  60         .pipe_offsets = { \
  61                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  62                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  63                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  64         }, \
  65         .trans_offsets = { \
  66                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  67                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  68                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  69         }
  70
  71 #define HSW_PIPE_OFFSETS \
  72         .pipe_offsets = { \
  73                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  74                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  75                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  76                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  77         }, \
  78         .trans_offsets = { \
  79                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  80                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  81                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  82                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  83         }
  84
  85 #define CHV_PIPE_OFFSETS \
  86         .pipe_offsets = { \
  87                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  88                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  89                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  90         }, \
  91         .trans_offsets = { \
  92                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  93                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  94                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  95         }
  96
  97 #define I845_CURSOR_OFFSETS \
  98         .cursor_offsets = { \
  99                 [PIPE_A] = CURSOR_A_OFFSET, \
 100         }
 101
 102 #define I9XX_CURSOR_OFFSETS \
 103         .cursor_offsets = { \
 104                 [PIPE_A] = CURSOR_A_OFFSET, \
 105                 [PIPE_B] = CURSOR_B_OFFSET, \
 106         }
 107
 108 #define CHV_CURSOR_OFFSETS \
 109         .cursor_offsets = { \
 110                 [PIPE_A] = CURSOR_A_OFFSET, \
 111                 [PIPE_B] = CURSOR_B_OFFSET, \
 112                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 113         }
 114
 115 #define IVB_CURSOR_OFFSETS \
 116         .cursor_offsets = { \
 117                 [PIPE_A] = CURSOR_A_OFFSET, \
 118                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 119                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 120         }
 121
 122 #define TGL_CURSOR_OFFSETS \
 123         .cursor_offsets = { \
 124                 [PIPE_A] = CURSOR_A_OFFSET, \
 125                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 126                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 127                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 128         }
 129
 130 #define I9XX_COLORS \
 131         .color = { .gamma_lut_size = 256 }
 132 #define I965_COLORS \
 133         .color = { .gamma_lut_size = 129, \
 134                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 135         }
 136 #define ILK_COLORS \
 137         .color = { .gamma_lut_size = 1024 }
 138 #define IVB_COLORS \
 139         .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 140 #define CHV_COLORS \
 141         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
 142                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 143                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 144         }
 145 #define GLK_COLORS \
 146         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 147                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 148                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 149         }
 150
 151 /* Keep in gen based order, and chronological order within a gen */
 152
 153 #define GEN_DEFAULT_PAGE_SIZES \
 154         .page_sizes = I915_GTT_PAGE_SIZE_4K
 155
 156 #define GEN_DEFAULT_REGIONS \
 157         .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 158
 159 #define I830_FEATURES \
 160         GEN(2), \
 161         .is_mobile = 1, \
 162         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 163         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 164         .display.has_overlay = 1, \
 165         .display.cursor_needs_physical = 1, \
 166         .display.overlay_needs_physical = 1, \
 167         .display.has_gmch = 1, \
 168         .gpu_reset_clobbers_display = true, \
 169         .hws_needs_physical = 1, \
 170         .unfenced_needs_alignment = 1, \
 171         .platform_engine_mask = BIT(RCS0), \
 172         .has_snoop = true, \
 173         .has_coherent_ggtt = false, \
 174         .dma_mask_size = 32, \
 175         I9XX_PIPE_OFFSETS, \
 176         I9XX_CURSOR_OFFSETS, \
 177         I9XX_COLORS, \
 178         GEN_DEFAULT_PAGE_SIZES, \
 179         GEN_DEFAULT_REGIONS
 180
 181 #define I845_FEATURES \
 182         GEN(2), \
 183         .pipe_mask = BIT(PIPE_A), \
 184         .cpu_transcoder_mask = BIT(TRANSCODER_A), \
 185         .display.has_overlay = 1, \
 186         .display.overlay_needs_physical = 1, \
 187         .display.has_gmch = 1, \
 188         .gpu_reset_clobbers_display = true, \
 189         .hws_needs_physical = 1, \
 190         .unfenced_needs_alignment = 1, \
 191         .platform_engine_mask = BIT(RCS0), \
 192         .has_snoop = true, \
 193         .has_coherent_ggtt = false, \
 194         .dma_mask_size = 32, \
 195         I845_PIPE_OFFSETS, \
 196         I845_CURSOR_OFFSETS, \
 197         I9XX_COLORS, \
 198         GEN_DEFAULT_PAGE_SIZES, \
 199         GEN_DEFAULT_REGIONS
 200
 201 static const struct intel_device_info i830_info = {
 202         I830_FEATURES,
 203         PLATFORM(INTEL_I830),
 204 };
 205
 206 static const struct intel_device_info i845g_info = {
 207         I845_FEATURES,
 208         PLATFORM(INTEL_I845G),
 209 };
 210
 211 static const struct intel_device_info i85x_info = {
 212         I830_FEATURES,
 213         PLATFORM(INTEL_I85X),
 214         .display.has_fbc = 1,
 215 };
 216
 217 static const struct intel_device_info i865g_info = {
 218         I845_FEATURES,
 219         PLATFORM(INTEL_I865G),
 220         .display.has_fbc = 1,
 221 };
 222
 223 #define GEN3_FEATURES \
 224         GEN(3), \
 225         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 226         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 227         .display.has_gmch = 1, \
 228         .gpu_reset_clobbers_display = true, \
 229         .platform_engine_mask = BIT(RCS0), \
 230         .has_snoop = true, \
 231         .has_coherent_ggtt = true, \
 232         .dma_mask_size = 32, \
 233         I9XX_PIPE_OFFSETS, \
 234         I9XX_CURSOR_OFFSETS, \
 235         I9XX_COLORS, \
 236         GEN_DEFAULT_PAGE_SIZES, \
 237         GEN_DEFAULT_REGIONS
 238
 239 static const struct intel_device_info i915g_info = {
 240         GEN3_FEATURES,
 241         PLATFORM(INTEL_I915G),
 242         .has_coherent_ggtt = false,
 243         .display.cursor_needs_physical = 1,
 244         .display.has_overlay = 1,
 245         .display.overlay_needs_physical = 1,
 246         .hws_needs_physical = 1,
 247         .unfenced_needs_alignment = 1,
 248 };
 249
 250 static const struct intel_device_info i915gm_info = {
 251         GEN3_FEATURES,
 252         PLATFORM(INTEL_I915GM),
 253         .is_mobile = 1,
 254         .display.cursor_needs_physical = 1,
 255         .display.has_overlay = 1,
 256         .display.overlay_needs_physical = 1,
 257         .display.supports_tv = 1,
 258         .display.has_fbc = 1,
 259         .hws_needs_physical = 1,
 260         .unfenced_needs_alignment = 1,
 261 };
 262
 263 static const struct intel_device_info i945g_info = {
 264         GEN3_FEATURES,
 265         PLATFORM(INTEL_I945G),
 266         .display.has_hotplug = 1,
 267         .display.cursor_needs_physical = 1,
 268         .display.has_overlay = 1,
 269         .display.overlay_needs_physical = 1,
 270         .hws_needs_physical = 1,
 271         .unfenced_needs_alignment = 1,
 272 };
 273
 274 static const struct intel_device_info i945gm_info = {
 275         GEN3_FEATURES,
 276         PLATFORM(INTEL_I945GM),
 277         .is_mobile = 1,
 278         .display.has_hotplug = 1,
 279         .display.cursor_needs_physical = 1,
 280         .display.has_overlay = 1,
 281         .display.overlay_needs_physical = 1,
 282         .display.supports_tv = 1,
 283         .display.has_fbc = 1,
 284         .hws_needs_physical = 1,
 285         .unfenced_needs_alignment = 1,
 286 };
 287
 288 static const struct intel_device_info g33_info = {
 289         GEN3_FEATURES,
 290         PLATFORM(INTEL_G33),
 291         .display.has_hotplug = 1,
 292         .display.has_overlay = 1,
 293         .dma_mask_size = 36,
 294 };
 295
 296 static const struct intel_device_info pnv_g_info = {
 297         GEN3_FEATURES,
 298         PLATFORM(INTEL_PINEVIEW),
 299         .display.has_hotplug = 1,
 300         .display.has_overlay = 1,
 301         .dma_mask_size = 36,
 302 };
 303
 304 static const struct intel_device_info pnv_m_info = {
 305         GEN3_FEATURES,
 306         PLATFORM(INTEL_PINEVIEW),
 307         .is_mobile = 1,
 308         .display.has_hotplug = 1,
 309         .display.has_overlay = 1,
 310         .dma_mask_size = 36,
 311 };
 312
 313 #define GEN4_FEATURES \
 314         GEN(4), \
 315         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 316         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 317         .display.has_hotplug = 1, \
 318         .display.has_gmch = 1, \
 319         .gpu_reset_clobbers_display = true, \
 320         .platform_engine_mask = BIT(RCS0), \
 321         .has_snoop = true, \
 322         .has_coherent_ggtt = true, \
 323         .dma_mask_size = 36, \
 324         I9XX_PIPE_OFFSETS, \
 325         I9XX_CURSOR_OFFSETS, \
 326         I965_COLORS, \
 327         GEN_DEFAULT_PAGE_SIZES, \
 328         GEN_DEFAULT_REGIONS
 329
 330 static const struct intel_device_info i965g_info = {
 331         GEN4_FEATURES,
 332         PLATFORM(INTEL_I965G),
 333         .display.has_overlay = 1,
 334         .hws_needs_physical = 1,
 335         .has_snoop = false,
 336 };
 337
 338 static const struct intel_device_info i965gm_info = {
 339         GEN4_FEATURES,
 340         PLATFORM(INTEL_I965GM),
 341         .is_mobile = 1,
 342         .display.has_fbc = 1,
 343         .display.has_overlay = 1,
 344         .display.supports_tv = 1,
 345         .hws_needs_physical = 1,
 346         .has_snoop = false,
 347 };
 348
 349 static const struct intel_device_info g45_info = {
 350         GEN4_FEATURES,
 351         PLATFORM(INTEL_G45),
 352         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 353         .gpu_reset_clobbers_display = false,
 354 };
 355
 356 static const struct intel_device_info gm45_info = {
 357         GEN4_FEATURES,
 358         PLATFORM(INTEL_GM45),
 359         .is_mobile = 1,
 360         .display.has_fbc = 1,
 361         .display.supports_tv = 1,
 362         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 363         .gpu_reset_clobbers_display = false,
 364 };
 365
 366 #define GEN5_FEATURES \
 367         GEN(5), \
 368         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 369         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 370         .display.has_hotplug = 1, \
 371         .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 372         .has_snoop = true, \
 373         .has_coherent_ggtt = true, \
 374         /* ilk does support rc6, but we do not implement [power] contexts */ \
 375         .has_rc6 = 0, \
 376         .dma_mask_size = 36, \
 377         I9XX_PIPE_OFFSETS, \
 378         I9XX_CURSOR_OFFSETS, \
 379         ILK_COLORS, \
 380         GEN_DEFAULT_PAGE_SIZES, \
 381         GEN_DEFAULT_REGIONS
 382
 383 static const struct intel_device_info ilk_d_info = {
 384         GEN5_FEATURES,
 385         PLATFORM(INTEL_IRONLAKE),
 386 };
 387
 388 static const struct intel_device_info ilk_m_info = {
 389         GEN5_FEATURES,
 390         PLATFORM(INTEL_IRONLAKE),
 391         .is_mobile = 1,
 392         .has_rps = true,
 393         .display.has_fbc = 1,
 394 };
 395
 396 #define GEN6_FEATURES \
 397         GEN(6), \
 398         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 399         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 400         .display.has_hotplug = 1, \
 401         .display.has_fbc = 1, \
 402         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 403         .has_coherent_ggtt = true, \
 404         .has_llc = 1, \
 405         .has_rc6 = 1, \
 406         .has_rc6p = 1, \
 407         .has_rps = true, \
 408         .dma_mask_size = 40, \
 409         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 410         .ppgtt_size = 31, \
 411         I9XX_PIPE_OFFSETS, \
 412         I9XX_CURSOR_OFFSETS, \
 413         ILK_COLORS, \
 414         GEN_DEFAULT_PAGE_SIZES, \
 415         GEN_DEFAULT_REGIONS
 416
 417 #define SNB_D_PLATFORM \
 418         GEN6_FEATURES, \
 419         PLATFORM(INTEL_SANDYBRIDGE)
 420
 421 static const struct intel_device_info snb_d_gt1_info = {
 422         SNB_D_PLATFORM,
 423         .gt = 1,
 424 };
 425
 426 static const struct intel_device_info snb_d_gt2_info = {
 427         SNB_D_PLATFORM,
 428         .gt = 2,
 429 };
 430
 431 #define SNB_M_PLATFORM \
 432         GEN6_FEATURES, \
 433         PLATFORM(INTEL_SANDYBRIDGE), \
 434         .is_mobile = 1
 435
 436
 437 static const struct intel_device_info snb_m_gt1_info = {
 438         SNB_M_PLATFORM,
 439         .gt = 1,
 440 };
 441
 442 static const struct intel_device_info snb_m_gt2_info = {
 443         SNB_M_PLATFORM,
 444         .gt = 2,
 445 };
 446
 447 #define GEN7_FEATURES  \
 448         GEN(7), \
 449         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 450         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 451         .display.has_hotplug = 1, \
 452         .display.has_fbc = 1, \
 453         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 454         .has_coherent_ggtt = true, \
 455         .has_llc = 1, \
 456         .has_rc6 = 1, \
 457         .has_rc6p = 1, \
 458         .has_reset_engine = true, \
 459         .has_rps = true, \
 460         .dma_mask_size = 40, \
 461         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 462         .ppgtt_size = 31, \
 463         IVB_PIPE_OFFSETS, \
 464         IVB_CURSOR_OFFSETS, \
 465         IVB_COLORS, \
 466         GEN_DEFAULT_PAGE_SIZES, \
 467         GEN_DEFAULT_REGIONS
 468
 469 #define IVB_D_PLATFORM \
 470         GEN7_FEATURES, \
 471         PLATFORM(INTEL_IVYBRIDGE), \
 472         .has_l3_dpf = 1
 473
 474 static const struct intel_device_info ivb_d_gt1_info = {
 475         IVB_D_PLATFORM,
 476         .gt = 1,
 477 };
 478
 479 static const struct intel_device_info ivb_d_gt2_info = {
 480         IVB_D_PLATFORM,
 481         .gt = 2,
 482 };
 483
 484 #define IVB_M_PLATFORM \
 485         GEN7_FEATURES, \
 486         PLATFORM(INTEL_IVYBRIDGE), \
 487         .is_mobile = 1, \
 488         .has_l3_dpf = 1
 489
 490 static const struct intel_device_info ivb_m_gt1_info = {
 491         IVB_M_PLATFORM,
 492         .gt = 1,
 493 };
 494
 495 static const struct intel_device_info ivb_m_gt2_info = {
 496         IVB_M_PLATFORM,
 497         .gt = 2,
 498 };
 499
 500 static const struct intel_device_info ivb_q_info = {
 501         GEN7_FEATURES,
 502         PLATFORM(INTEL_IVYBRIDGE),
 503         .gt = 2,
 504         .pipe_mask = 0, /* legal, last one wins */
 505         .cpu_transcoder_mask = 0,
 506         .has_l3_dpf = 1,
 507 };
 508
 509 static const struct intel_device_info vlv_info = {
 510         PLATFORM(INTEL_VALLEYVIEW),
 511         GEN(7),
 512         .is_lp = 1,
 513         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 514         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 515         .has_runtime_pm = 1,
 516         .has_rc6 = 1,
 517         .has_reset_engine = true,
 518         .has_rps = true,
 519         .display.has_gmch = 1,
 520         .display.has_hotplug = 1,
 521         .dma_mask_size = 40,
 522         .ppgtt_type = INTEL_PPGTT_ALIASING,
 523         .ppgtt_size = 31,
 524         .has_snoop = true,
 525         .has_coherent_ggtt = false,
 526         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 527         .display_mmio_offset = VLV_DISPLAY_BASE,
 528         I9XX_PIPE_OFFSETS,
 529         I9XX_CURSOR_OFFSETS,
 530         I965_COLORS,
 531         GEN_DEFAULT_PAGE_SIZES,
 532         GEN_DEFAULT_REGIONS,
 533 };
 534
 535 #define G75_FEATURES  \
 536         GEN7_FEATURES, \
 537         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 538         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 539                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 540         .display.has_ddi = 1, \
 541         .display.has_fpga_dbg = 1, \
 542         .display.has_psr = 1, \
 543         .display.has_psr_hw_tracking = 1, \
 544         .display.has_dp_mst = 1, \
 545         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 546         HSW_PIPE_OFFSETS, \
 547         .has_runtime_pm = 1
 548
 549 #define HSW_PLATFORM \
 550         G75_FEATURES, \
 551         PLATFORM(INTEL_HASWELL), \
 552         .has_l3_dpf = 1
 553
 554 static const struct intel_device_info hsw_gt1_info = {
 555         HSW_PLATFORM,
 556         .gt = 1,
 557 };
 558
 559 static const struct intel_device_info hsw_gt2_info = {
 560         HSW_PLATFORM,
 561         .gt = 2,
 562 };
 563
 564 static const struct intel_device_info hsw_gt3_info = {
 565         HSW_PLATFORM,
 566         .gt = 3,
 567 };
 568
 569 #define GEN8_FEATURES \
 570         G75_FEATURES, \
 571         GEN(8), \
 572         .has_logical_ring_contexts = 1, \
 573         .dma_mask_size = 39, \
 574         .ppgtt_type = INTEL_PPGTT_FULL, \
 575         .ppgtt_size = 48, \
 576         .has_64bit_reloc = 1
 577
 578 #define BDW_PLATFORM \
 579         GEN8_FEATURES, \
 580         PLATFORM(INTEL_BROADWELL)
 581
 582 static const struct intel_device_info bdw_gt1_info = {
 583         BDW_PLATFORM,
 584         .gt = 1,
 585 };
 586
 587 static const struct intel_device_info bdw_gt2_info = {
 588         BDW_PLATFORM,
 589         .gt = 2,
 590 };
 591
 592 static const struct intel_device_info bdw_rsvd_info = {
 593         BDW_PLATFORM,
 594         .gt = 3,
 595         /* According to the device ID those devices are GT3, they were
 596          * previously treated as not GT3, keep it like that.
 597          */
 598 };
 599
 600 static const struct intel_device_info bdw_gt3_info = {
 601         BDW_PLATFORM,
 602         .gt = 3,
 603         .platform_engine_mask =
 604                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 605 };
 606
 607 static const struct intel_device_info chv_info = {
 608         PLATFORM(INTEL_CHERRYVIEW),
 609         GEN(8),
 610         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 611         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 612         .display.has_hotplug = 1,
 613         .is_lp = 1,
 614         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 615         .has_64bit_reloc = 1,
 616         .has_runtime_pm = 1,
 617         .has_rc6 = 1,
 618         .has_rps = true,
 619         .has_logical_ring_contexts = 1,
 620         .display.has_gmch = 1,
 621         .dma_mask_size = 39,
 622         .ppgtt_type = INTEL_PPGTT_FULL,
 623         .ppgtt_size = 32,
 624         .has_reset_engine = 1,
 625         .has_snoop = true,
 626         .has_coherent_ggtt = false,
 627         .display_mmio_offset = VLV_DISPLAY_BASE,
 628         CHV_PIPE_OFFSETS,
 629         CHV_CURSOR_OFFSETS,
 630         CHV_COLORS,
 631         GEN_DEFAULT_PAGE_SIZES,
 632         GEN_DEFAULT_REGIONS,
 633 };
 634
 635 #define GEN9_DEFAULT_PAGE_SIZES \
 636         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 637                       I915_GTT_PAGE_SIZE_64K
 638
 639 #define GEN9_FEATURES \
 640         GEN8_FEATURES, \
 641         GEN(9), \
 642         GEN9_DEFAULT_PAGE_SIZES, \
 643         .display.has_csr = 1, \
 644         .has_gt_uc = 1, \
 645         .display.has_hdcp = 1, \
 646         .display.has_ipc = 1, \
 647         .ddb_size = 896, \
 648         .num_supported_dbuf_slices = 1
 649
 650 #define SKL_PLATFORM \
 651         GEN9_FEATURES, \
 652         PLATFORM(INTEL_SKYLAKE)
 653
 654 static const struct intel_device_info skl_gt1_info = {
 655         SKL_PLATFORM,
 656         .gt = 1,
 657 };
 658
 659 static const struct intel_device_info skl_gt2_info = {
 660         SKL_PLATFORM,
 661         .gt = 2,
 662 };
 663
 664 #define SKL_GT3_PLUS_PLATFORM \
 665         SKL_PLATFORM, \
 666         .platform_engine_mask = \
 667                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 668
 669
 670 static const struct intel_device_info skl_gt3_info = {
 671         SKL_GT3_PLUS_PLATFORM,
 672         .gt = 3,
 673 };
 674
 675 static const struct intel_device_info skl_gt4_info = {
 676         SKL_GT3_PLUS_PLATFORM,
 677         .gt = 4,
 678 };
 679
 680 #define GEN9_LP_FEATURES \
 681         GEN(9), \
 682         .is_lp = 1, \
 683         .num_supported_dbuf_slices = 1, \
 684         .display.has_hotplug = 1, \
 685         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 686         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 687         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 688                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 689                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 690         .has_64bit_reloc = 1, \
 691         .display.has_ddi = 1, \
 692         .display.has_fpga_dbg = 1, \
 693         .display.has_fbc = 1, \
 694         .display.has_hdcp = 1, \
 695         .display.has_psr = 1, \
 696         .display.has_psr_hw_tracking = 1, \
 697         .has_runtime_pm = 1, \
 698         .display.has_csr = 1, \
 699         .has_rc6 = 1, \
 700         .has_rps = true, \
 701         .display.has_dp_mst = 1, \
 702         .has_logical_ring_contexts = 1, \
 703         .has_gt_uc = 1, \
 704         .dma_mask_size = 39, \
 705         .ppgtt_type = INTEL_PPGTT_FULL, \
 706         .ppgtt_size = 48, \
 707         .has_reset_engine = 1, \
 708         .has_snoop = true, \
 709         .has_coherent_ggtt = false, \
 710         .display.has_ipc = 1, \
 711         HSW_PIPE_OFFSETS, \
 712         IVB_CURSOR_OFFSETS, \
 713         IVB_COLORS, \
 714         GEN9_DEFAULT_PAGE_SIZES, \
 715         GEN_DEFAULT_REGIONS
 716
 717 static const struct intel_device_info bxt_info = {
 718         GEN9_LP_FEATURES,
 719         PLATFORM(INTEL_BROXTON),
 720         .ddb_size = 512,
 721 };
 722
 723 static const struct intel_device_info glk_info = {
 724         GEN9_LP_FEATURES,
 725         PLATFORM(INTEL_GEMINILAKE),
 726         .display.version = 10,
 727         .ddb_size = 1024,
 728         GLK_COLORS,
 729 };
 730
 731 #define KBL_PLATFORM \
 732         GEN9_FEATURES, \
 733         PLATFORM(INTEL_KABYLAKE)
 734
 735 static const struct intel_device_info kbl_gt1_info = {
 736         KBL_PLATFORM,
 737         .gt = 1,
 738 };
 739
 740 static const struct intel_device_info kbl_gt2_info = {
 741         KBL_PLATFORM,
 742         .gt = 2,
 743 };
 744
 745 static const struct intel_device_info kbl_gt3_info = {
 746         KBL_PLATFORM,
 747         .gt = 3,
 748         .platform_engine_mask =
 749                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 750 };
 751
 752 #define CFL_PLATFORM \
 753         GEN9_FEATURES, \
 754         PLATFORM(INTEL_COFFEELAKE)
 755
 756 static const struct intel_device_info cfl_gt1_info = {
 757         CFL_PLATFORM,
 758         .gt = 1,
 759 };
 760
 761 static const struct intel_device_info cfl_gt2_info = {
 762         CFL_PLATFORM,
 763         .gt = 2,
 764 };
 765
 766 static const struct intel_device_info cfl_gt3_info = {
 767         CFL_PLATFORM,
 768         .gt = 3,
 769         .platform_engine_mask =
 770                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 771 };
 772
 773 #define CML_PLATFORM \
 774         GEN9_FEATURES, \
 775         PLATFORM(INTEL_COMETLAKE)
 776
 777 static const struct intel_device_info cml_gt1_info = {
 778         CML_PLATFORM,
 779         .gt = 1,
 780 };
 781
 782 static const struct intel_device_info cml_gt2_info = {
 783         CML_PLATFORM,
 784         .gt = 2,
 785 };
 786
 787 #define GEN10_FEATURES \
 788         GEN9_FEATURES, \
 789         GEN(10), \
 790         .ddb_size = 1024, \
 791         .display.has_dsc = 1, \
 792         .has_coherent_ggtt = false, \
 793         GLK_COLORS
 794
 795 static const struct intel_device_info cnl_info = {
 796         GEN10_FEATURES,
 797         PLATFORM(INTEL_CANNONLAKE),
 798         .gt = 2,
 799 };
 800
 801 #define GEN11_DEFAULT_PAGE_SIZES \
 802         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 803                       I915_GTT_PAGE_SIZE_64K | \
 804                       I915_GTT_PAGE_SIZE_2M
 805
 806 #define GEN11_FEATURES \
 807         GEN10_FEATURES, \
 808         GEN11_DEFAULT_PAGE_SIZES, \
 809         .abox_mask = BIT(0), \
 810         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 811                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 812                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 813         .pipe_offsets = { \
 814                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 815                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 816                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 817                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 818                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 819                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 820         }, \
 821         .trans_offsets = { \
 822                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 823                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 824                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 825                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 826                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 827                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 828         }, \
 829         GEN(11), \
 830         .ddb_size = 2048, \
 831         .num_supported_dbuf_slices = 2, \
 832         .has_logical_ring_elsq = 1, \
 833         .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
 834
 835 static const struct intel_device_info icl_info = {
 836         GEN11_FEATURES,
 837         PLATFORM(INTEL_ICELAKE),
 838         .platform_engine_mask =
 839                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 840 };
 841
 842 static const struct intel_device_info ehl_info = {
 843         GEN11_FEATURES,
 844         PLATFORM(INTEL_ELKHARTLAKE),
 845         .require_force_probe = 1,
 846         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 847         .ppgtt_size = 36,
 848 };
 849
 850 static const struct intel_device_info jsl_info = {
 851         GEN11_FEATURES,
 852         PLATFORM(INTEL_JASPERLAKE),
 853         .require_force_probe = 1,
 854         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 855         .ppgtt_size = 36,
 856 };
 857
 858 #define GEN12_FEATURES \
 859         GEN11_FEATURES, \
 860         GEN(12), \
 861         .abox_mask = GENMASK(2, 1), \
 862         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 863         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 864                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 865                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 866         .pipe_offsets = { \
 867                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 868                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 869                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 870                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 871                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 872                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 873         }, \
 874         .trans_offsets = { \
 875                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 876                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 877                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 878                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 879                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 880                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 881         }, \
 882         TGL_CURSOR_OFFSETS, \
 883         .has_global_mocs = 1, \
 884         .display.has_dsb = 1
 885
 886 static const struct intel_device_info tgl_info = {
 887         GEN12_FEATURES,
 888         PLATFORM(INTEL_TIGERLAKE),
 889         .display.has_modular_fia = 1,
 890         .platform_engine_mask =
 891                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 892 };
 893
 894 static const struct intel_device_info rkl_info = {
 895         GEN12_FEATURES,
 896         PLATFORM(INTEL_ROCKETLAKE),
 897         .abox_mask = BIT(0),
 898         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 899         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 900                 BIT(TRANSCODER_C),
 901         .display.has_hti = 1,
 902         .display.has_psr_hw_tracking = 0,
 903         .platform_engine_mask =
 904                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 905 };
 906
 907 #define GEN12_DGFX_FEATURES \
 908         GEN12_FEATURES, \
 909         .memory_regions = REGION_SMEM | REGION_LMEM, \
 910         .has_master_unit_irq = 1, \
 911         .has_llc = 0, \
 912         .has_snoop = 1, \
 913         .is_dgfx = 1
 914
 915 static const struct intel_device_info dg1_info __maybe_unused = {
 916         GEN12_DGFX_FEATURES,
 917         PLATFORM(INTEL_DG1),
 918         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 919         .require_force_probe = 1,
 920         .platform_engine_mask =
 921                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 922                 BIT(VCS0) | BIT(VCS2),
 923         /* Wa_16011227922 */
 924         .ppgtt_size = 47,
 925 };
 926
 927 static const struct intel_device_info adl_s_info = {
 928         GEN12_FEATURES,
 929         PLATFORM(INTEL_ALDERLAKE_S),
 930         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 931         .require_force_probe = 1,
 932         .display.has_hti = 1,
 933         .display.has_psr_hw_tracking = 0,
 934         .platform_engine_mask =
 935                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 936         .dma_mask_size = 46,
 937 };
 938
 939 #undef GEN
 940 #undef PLATFORM
 941
 942 /*
 943  * Make sure any device matches here are from most specific to most
 944  * general.  For example, since the Quanta match is based on the subsystem
 945  * and subvendor IDs, we need it to come before the more general IVB
 946  * PCI ID matches, otherwise we'll use the wrong info struct above.
 947  */
 948 static const struct pci_device_id pciidlist[] = {
 949         INTEL_I830_IDS(&i830_info),
 950         INTEL_I845G_IDS(&i845g_info),
 951         INTEL_I85X_IDS(&i85x_info),
 952         INTEL_I865G_IDS(&i865g_info),
 953         INTEL_I915G_IDS(&i915g_info),
 954         INTEL_I915GM_IDS(&i915gm_info),
 955         INTEL_I945G_IDS(&i945g_info),
 956         INTEL_I945GM_IDS(&i945gm_info),
 957         INTEL_I965G_IDS(&i965g_info),
 958         INTEL_G33_IDS(&g33_info),
 959         INTEL_I965GM_IDS(&i965gm_info),
 960         INTEL_GM45_IDS(&gm45_info),
 961         INTEL_G45_IDS(&g45_info),
 962         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
 963         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
 964         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
 965         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
 966         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
 967         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
 968         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
 969         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
 970         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
 971         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
 972         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
 973         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
 974         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
 975         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
 976         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
 977         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
 978         INTEL_VLV_IDS(&vlv_info),
 979         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
 980         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
 981         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
 982         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
 983         INTEL_CHV_IDS(&chv_info),
 984         INTEL_SKL_GT1_IDS(&skl_gt1_info),
 985         INTEL_SKL_GT2_IDS(&skl_gt2_info),
 986         INTEL_SKL_GT3_IDS(&skl_gt3_info),
 987         INTEL_SKL_GT4_IDS(&skl_gt4_info),
 988         INTEL_BXT_IDS(&bxt_info),
 989         INTEL_GLK_IDS(&glk_info),
 990         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
 991         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
 992         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
 993         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
 994         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
 995         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
 996         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
 997         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
 998         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
 999         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1000         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1001         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1002         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1003         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1004         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1005         INTEL_CML_GT1_IDS(&cml_gt1_info),
1006         INTEL_CML_GT2_IDS(&cml_gt2_info),
1007         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1008         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1009         INTEL_CNL_IDS(&cnl_info),
1010         INTEL_ICL_11_IDS(&icl_info),
1011         INTEL_EHL_IDS(&ehl_info),
1012         INTEL_JSL_IDS(&jsl_info),
1013         INTEL_TGL_12_IDS(&tgl_info),
1014         INTEL_RKL_IDS(&rkl_info),
1015         INTEL_ADLS_IDS(&adl_s_info),
1016         {0, 0, 0}
1017 };
1018 MODULE_DEVICE_TABLE(pci, pciidlist);
1019
1020 static void i915_pci_remove(struct pci_dev *pdev)
1021 {
1022         struct drm_i915_private *i915;
1023
1024         i915 = pci_get_drvdata(pdev);
1025         if (!i915) /* driver load aborted, nothing to cleanup */
1026                 return;
1027
1028         i915_driver_remove(i915);
1029         pci_set_drvdata(pdev, NULL);
1030 }
1031
1032 /* is device_id present in comma separated list of ids */
1033 static bool force_probe(u16 device_id, const char *devices)
1034 {
1035         char *s, *p, *tok;
1036         bool ret;
1037
1038         if (!devices || !*devices)
1039                 return false;
1040
1041         /* match everything */
1042         if (strcmp(devices, "*") == 0)
1043                 return true;
1044
1045         s = kstrdup(devices, GFP_KERNEL);
1046         if (!s)
1047                 return false;
1048
1049         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1050                 u16 val;
1051
1052                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1053                         ret = true;
1054                         break;
1055                 }
1056         }
1057
1058         kfree(s);
1059
1060         return ret;
1061 }
1062
1063 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1064 {
1065         struct intel_device_info *intel_info =
1066                 (struct intel_device_info *) ent->driver_data;
1067         int err;
1068
1069         if (intel_info->require_force_probe &&
1070             !force_probe(pdev->device, i915_modparams.force_probe)) {
1071                 dev_info(&pdev->dev,
1072                          "Your graphics device %04x is not properly supported by the driver in this\n"
1073                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1074                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1075                          "or (recommended) check for kernel updates.\n",
1076                          pdev->device, pdev->device, pdev->device);
1077                 return -ENODEV;
1078         }
1079
1080         /* Only bind to function 0 of the device. Early generations
1081          * used function 1 as a placeholder for multi-head. This causes
1082          * us confusion instead, especially on the systems where both
1083          * functions have the same PCI-ID!
1084          */
1085         if (PCI_FUNC(pdev->devfn))
1086                 return -ENODEV;
1087
1088         /*
1089          * apple-gmux is needed on dual GPU MacBook Pro
1090          * to probe the panel if we're the inactive GPU.
1091          */
1092         if (vga_switcheroo_client_probe_defer(pdev))
1093                 return -EPROBE_DEFER;
1094
1095         err = i915_driver_probe(pdev, ent);
1096         if (err)
1097                 return err;
1098
1099         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1100                 i915_pci_remove(pdev);
1101                 return -ENODEV;
1102         }
1103
1104         err = i915_live_selftests(pdev);
1105         if (err) {
1106                 i915_pci_remove(pdev);
1107                 return err > 0 ? -ENOTTY : err;
1108         }
1109
1110         err = i915_perf_selftests(pdev);
1111         if (err) {
1112                 i915_pci_remove(pdev);
1113                 return err > 0 ? -ENOTTY : err;
1114         }
1115
1116         return 0;
1117 }
1118
1119 static void i915_pci_shutdown(struct pci_dev *pdev)
1120 {
1121         struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1122
1123         i915_driver_shutdown(i915);
1124 }
1125
1126 static struct pci_driver i915_pci_driver = {
1127         .name = DRIVER_NAME,
1128         .id_table = pciidlist,
1129         .probe = i915_pci_probe,
1130         .remove = i915_pci_remove,
1131         .shutdown = i915_pci_shutdown,
1132         .driver.pm = &i915_pm_ops,
1133 };
1134
1135 static int __init i915_init(void)
1136 {
1137         bool use_kms = true;
1138         int err;
1139
1140         err = i915_globals_init();
1141         if (err)
1142                 return err;
1143
1144         err = i915_mock_selftests();
1145         if (err)
1146                 return err > 0 ? 0 : err;
1147
1148         /*
1149          * Enable KMS by default, unless explicitly overriden by
1150          * either the i915.modeset prarameter or by the
1151          * vga_text_mode_force boot option.
1152          */
1153
1154         if (i915_modparams.modeset == 0)
1155                 use_kms = false;
1156
1157         if (vgacon_text_force() && i915_modparams.modeset == -1)
1158                 use_kms = false;
1159
1160         if (!use_kms) {
1161                 /* Silently fail loading to not upset userspace. */
1162                 DRM_DEBUG_DRIVER("KMS disabled.\n");
1163                 return 0;
1164         }
1165
1166         i915_pmu_init();
1167
1168         err = pci_register_driver(&i915_pci_driver);
1169         if (err) {
1170                 i915_pmu_exit();
1171                 return err;
1172         }
1173
1174         i915_perf_sysctl_register();
1175         return 0;
1176 }
1177
1178 static void __exit i915_exit(void)
1179 {
1180         if (!i915_pci_driver.driver.owner)
1181                 return;
1182
1183         i915_perf_sysctl_unregister();
1184         pci_unregister_driver(&i915_pci_driver);
1185         i915_globals_exit();
1186         i915_pmu_exit();
1187 }
1188
1189 module_init(i915_init);
1190 module_exit(i915_exit);
1191
1192 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1193 MODULE_AUTHOR("Intel Corporation");
1194
1195 MODULE_DESCRIPTION(DRIVER_DESC);
1196 MODULE_LICENSE("GPL and additional rights");