1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
83 /* For display hotplug interrupt */
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
87 assert_spin_locked(&dev_priv->irq_lock);
89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
105 assert_spin_locked(&dev_priv->irq_lock);
107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
130 assert_spin_locked(&dev_priv->irq_lock);
132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
148 ilk_update_gt_irq(dev_priv, mask, mask);
151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
153 ilk_update_gt_irq(dev_priv, mask, 0);
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
168 assert_spin_locked(&dev_priv->irq_lock);
170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
178 new_val = dev_priv->pm_irq_mask;
179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
185 POSTING_READ(GEN6_PMIMR);
189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 snb_update_pm_irq(dev_priv, mask, mask);
194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
196 snb_update_pm_irq(dev_priv, mask, 0);
199 static bool ivb_can_enable_err_int(struct drm_device *dev)
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
205 assert_spin_locked(&dev_priv->irq_lock);
207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
210 if (crtc->cpu_fifo_underrun_disabled)
217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
221 struct intel_crtc *crtc;
223 assert_spin_locked(&dev_priv->irq_lock);
225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
228 if (crtc->pch_fifo_underrun_disabled)
235 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
236 enum pipe pipe, bool enable)
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
240 DE_PIPEB_FIFO_UNDERRUN;
243 ironlake_enable_display_irq(dev_priv, bit);
245 ironlake_disable_display_irq(dev_priv, bit);
248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
249 enum pipe pipe, bool enable)
251 struct drm_i915_private *dev_priv = dev->dev_private;
253 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
255 if (!ivb_can_enable_err_int(dev))
258 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
260 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
262 /* Change the state _after_ we've read out the current one. */
263 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
266 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
274 enum pipe pipe, bool enable)
276 struct drm_i915_private *dev_priv = dev->dev_private;
278 assert_spin_locked(&dev_priv->irq_lock);
281 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
283 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
284 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
285 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
289 * ibx_display_interrupt_update - update SDEIMR
290 * @dev_priv: driver private
291 * @interrupt_mask: mask of interrupt bits to update
292 * @enabled_irq_mask: mask of interrupt bits to enable
294 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
295 uint32_t interrupt_mask,
296 uint32_t enabled_irq_mask)
298 uint32_t sdeimr = I915_READ(SDEIMR);
299 sdeimr &= ~interrupt_mask;
300 sdeimr |= (~enabled_irq_mask & interrupt_mask);
302 assert_spin_locked(&dev_priv->irq_lock);
304 if (dev_priv->pc8.irqs_disabled &&
305 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
306 WARN(1, "IRQs disabled\n");
307 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
308 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
313 I915_WRITE(SDEIMR, sdeimr);
314 POSTING_READ(SDEIMR);
316 #define ibx_enable_display_interrupt(dev_priv, bits) \
317 ibx_display_interrupt_update((dev_priv), (bits), (bits))
318 #define ibx_disable_display_interrupt(dev_priv, bits) \
319 ibx_display_interrupt_update((dev_priv), (bits), 0)
321 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
322 enum transcoder pch_transcoder,
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
327 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
330 ibx_enable_display_interrupt(dev_priv, bit);
332 ibx_disable_display_interrupt(dev_priv, bit);
335 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
336 enum transcoder pch_transcoder,
339 struct drm_i915_private *dev_priv = dev->dev_private;
343 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
345 if (!cpt_can_enable_serr_int(dev))
348 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
350 uint32_t tmp = I915_READ(SERR_INT);
351 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
353 /* Change the state _after_ we've read out the current one. */
354 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
357 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
358 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
359 transcoder_name(pch_transcoder));
365 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
368 * @enable: true if we want to report FIFO underrun errors, false otherwise
370 * This function makes us disable or enable CPU fifo underruns for a specific
371 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
372 * reporting for one pipe may also disable all the other CPU error interruts for
373 * the other pipes, due to the fact that there's just one interrupt mask/enable
374 * bit for all the pipes.
376 * Returns the previous state of underrun reporting.
378 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
379 enum pipe pipe, bool enable)
381 struct drm_i915_private *dev_priv = dev->dev_private;
382 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
387 spin_lock_irqsave(&dev_priv->irq_lock, flags);
389 ret = !intel_crtc->cpu_fifo_underrun_disabled;
394 intel_crtc->cpu_fifo_underrun_disabled = !enable;
396 if (IS_GEN5(dev) || IS_GEN6(dev))
397 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
398 else if (IS_GEN7(dev))
399 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
400 else if (IS_GEN8(dev))
401 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
404 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
409 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
411 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
412 * @enable: true if we want to report FIFO underrun errors, false otherwise
414 * This function makes us disable or enable PCH fifo underruns for a specific
415 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
416 * underrun reporting for one transcoder may also disable all the other PCH
417 * error interruts for the other transcoders, due to the fact that there's just
418 * one interrupt mask/enable bit for all the transcoders.
420 * Returns the previous state of underrun reporting.
422 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
423 enum transcoder pch_transcoder,
426 struct drm_i915_private *dev_priv = dev->dev_private;
427 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
433 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
434 * has only one pch transcoder A that all pipes can use. To avoid racy
435 * pch transcoder -> pipe lookups from interrupt code simply store the
436 * underrun statistics in crtc A. Since we never expose this anywhere
437 * nor use it outside of the fifo underrun code here using the "wrong"
438 * crtc on LPT won't cause issues.
441 spin_lock_irqsave(&dev_priv->irq_lock, flags);
443 ret = !intel_crtc->pch_fifo_underrun_disabled;
448 intel_crtc->pch_fifo_underrun_disabled = !enable;
450 if (HAS_PCH_IBX(dev))
451 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
453 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
456 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
462 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
464 u32 reg = PIPESTAT(pipe);
465 u32 pipestat = I915_READ(reg) & 0x7fff0000;
467 assert_spin_locked(&dev_priv->irq_lock);
469 if ((pipestat & mask) == mask)
472 /* Enable the interrupt, clear any pending status */
473 pipestat |= mask | (mask >> 16);
474 I915_WRITE(reg, pipestat);
479 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
481 u32 reg = PIPESTAT(pipe);
482 u32 pipestat = I915_READ(reg) & 0x7fff0000;
484 assert_spin_locked(&dev_priv->irq_lock);
486 if ((pipestat & mask) == 0)
490 I915_WRITE(reg, pipestat);
495 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
497 static void i915_enable_asle_pipestat(struct drm_device *dev)
499 drm_i915_private_t *dev_priv = dev->dev_private;
500 unsigned long irqflags;
502 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
507 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
508 if (INTEL_INFO(dev)->gen >= 4)
509 i915_enable_pipestat(dev_priv, PIPE_A,
510 PIPE_LEGACY_BLC_EVENT_ENABLE);
512 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
516 * i915_pipe_enabled - check if a pipe is enabled
518 * @pipe: pipe to check
520 * Reading certain registers when the pipe is disabled can hang the chip.
521 * Use this routine to make sure the PLL is running and the pipe is active
522 * before reading such registers if unsure.
525 i915_pipe_enabled(struct drm_device *dev, int pipe)
527 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
529 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
530 /* Locking is horribly broken here, but whatever. */
531 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
534 return intel_crtc->active;
536 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
540 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
542 /* Gen2 doesn't have a hardware frame counter */
546 /* Called from drm generic code, passed a 'crtc', which
547 * we use as a pipe index
549 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
551 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
552 unsigned long high_frame;
553 unsigned long low_frame;
554 u32 high1, high2, low, pixel, vbl_start;
556 if (!i915_pipe_enabled(dev, pipe)) {
557 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
558 "pipe %c\n", pipe_name(pipe));
562 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
563 struct intel_crtc *intel_crtc =
564 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
565 const struct drm_display_mode *mode =
566 &intel_crtc->config.adjusted_mode;
568 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
570 enum transcoder cpu_transcoder = (enum transcoder) pipe;
573 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
574 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
579 high_frame = PIPEFRAME(pipe);
580 low_frame = PIPEFRAMEPIXEL(pipe);
583 * High & low register fields aren't synchronized, so make sure
584 * we get a low value that's stable across two reads of the high
588 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
589 low = I915_READ(low_frame);
590 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
591 } while (high1 != high2);
593 high1 >>= PIPE_FRAME_HIGH_SHIFT;
594 pixel = low & PIPE_PIXEL_MASK;
595 low >>= PIPE_FRAME_LOW_SHIFT;
598 * The frame counter increments at beginning of active.
599 * Cook up a vblank counter by also checking the pixel
600 * counter against vblank start.
602 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
605 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
608 int reg = PIPE_FRMCOUNT_GM45(pipe);
610 if (!i915_pipe_enabled(dev, pipe)) {
611 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
612 "pipe %c\n", pipe_name(pipe));
616 return I915_READ(reg);
619 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
620 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
622 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
624 struct drm_i915_private *dev_priv = dev->dev_private;
628 if (INTEL_INFO(dev)->gen >= 8) {
629 status = GEN8_PIPE_VBLANK;
630 reg = GEN8_DE_PIPE_ISR(pipe);
631 } else if (INTEL_INFO(dev)->gen >= 7) {
632 status = DE_PIPE_VBLANK_IVB(pipe);
635 status = DE_PIPE_VBLANK(pipe);
639 return __raw_i915_read32(dev_priv, reg) & status;
642 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
643 unsigned int flags, int *vpos, int *hpos,
644 ktime_t *stime, ktime_t *etime)
646 struct drm_i915_private *dev_priv = dev->dev_private;
647 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
649 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
651 int vbl_start, vbl_end, htotal, vtotal;
654 unsigned long irqflags;
656 if (!intel_crtc->active) {
657 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
658 "pipe %c\n", pipe_name(pipe));
662 htotal = mode->crtc_htotal;
663 vtotal = mode->crtc_vtotal;
664 vbl_start = mode->crtc_vblank_start;
665 vbl_end = mode->crtc_vblank_end;
667 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
668 vbl_start = DIV_ROUND_UP(vbl_start, 2);
673 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
676 * Lock uncore.lock, as we will do multiple timing critical raw
677 * register reads, potentially with preemption disabled, so the
678 * following code must not block on uncore.lock.
680 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
682 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
684 /* Get optional system timestamp before query. */
686 *stime = ktime_get();
688 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
689 /* No obvious pixelcount register. Only query vertical
690 * scanout position from Display scan line register.
693 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
695 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
699 * On HSW HDMI outputs there seems to be a 2 line
700 * difference, whereas eDP has the normal 1 line
701 * difference that earlier platforms have. External
702 * DP is unknown. For now just check for the 2 line
703 * difference case on all output types on HSW+.
705 * This might misinterpret the scanline counter being
706 * one line too far along on eDP, but that's less
707 * dangerous than the alternative since that would lead
708 * the vblank timestamp code astray when it sees a
709 * scanline count before vblank_start during a vblank
712 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
713 if ((in_vbl && (position == vbl_start - 2 ||
714 position == vbl_start - 1)) ||
715 (!in_vbl && (position == vbl_end - 2 ||
716 position == vbl_end - 1)))
717 position = (position + 2) % vtotal;
718 } else if (HAS_PCH_SPLIT(dev)) {
720 * The scanline counter increments at the leading edge
721 * of hsync, ie. it completely misses the active portion
722 * of the line. Fix up the counter at both edges of vblank
723 * to get a more accurate picture whether we're in vblank
726 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
727 if ((in_vbl && position == vbl_start - 1) ||
728 (!in_vbl && position == vbl_end - 1))
729 position = (position + 1) % vtotal;
732 * ISR vblank status bits don't work the way we'd want
733 * them to work on non-PCH platforms (for
734 * ilk_pipe_in_vblank_locked()), and there doesn't
735 * appear any other way to determine if we're currently
738 * Instead let's assume that we're already in vblank if
739 * we got called from the vblank interrupt and the
740 * scanline counter value indicates that we're on the
741 * line just prior to vblank start. This should result
742 * in the correct answer, unless the vblank interrupt
743 * delivery really got delayed for almost exactly one
746 if (flags & DRM_CALLED_FROM_VBLIRQ &&
747 position == vbl_start - 1) {
748 position = (position + 1) % vtotal;
750 /* Signal this correction as "applied". */
755 /* Have access to pixelcount since start of frame.
756 * We can split this into vertical and horizontal
759 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
761 /* convert to pixel counts */
767 /* Get optional system timestamp after query. */
769 *etime = ktime_get();
771 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
773 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
775 in_vbl = position >= vbl_start && position < vbl_end;
778 * While in vblank, position will be negative
779 * counting up towards 0 at vbl_end. And outside
780 * vblank, position will be positive counting
783 if (position >= vbl_start)
786 position += vtotal - vbl_end;
788 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
792 *vpos = position / htotal;
793 *hpos = position - (*vpos * htotal);
798 ret |= DRM_SCANOUTPOS_INVBL;
803 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
805 struct timeval *vblank_time,
808 struct drm_crtc *crtc;
810 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
811 DRM_ERROR("Invalid crtc %d\n", pipe);
815 /* Get drm_crtc to timestamp: */
816 crtc = intel_get_crtc_for_pipe(dev, pipe);
818 DRM_ERROR("Invalid crtc %d\n", pipe);
822 if (!crtc->enabled) {
823 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
827 /* Helper routine in DRM core does all the work: */
828 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
831 &to_intel_crtc(crtc)->config.adjusted_mode);
834 static bool intel_hpd_irq_event(struct drm_device *dev,
835 struct drm_connector *connector)
837 enum drm_connector_status old_status;
839 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
840 old_status = connector->status;
842 connector->status = connector->funcs->detect(connector, false);
843 if (old_status == connector->status)
846 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
848 drm_get_connector_name(connector),
849 drm_get_connector_status_name(old_status),
850 drm_get_connector_status_name(connector->status));
856 * Handle hotplug events outside the interrupt handler proper.
858 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
860 static void i915_hotplug_work_func(struct work_struct *work)
862 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
864 struct drm_device *dev = dev_priv->dev;
865 struct drm_mode_config *mode_config = &dev->mode_config;
866 struct intel_connector *intel_connector;
867 struct intel_encoder *intel_encoder;
868 struct drm_connector *connector;
869 unsigned long irqflags;
870 bool hpd_disabled = false;
871 bool changed = false;
874 /* HPD irq before everything is fully set up. */
875 if (!dev_priv->enable_hotplug_processing)
878 mutex_lock(&mode_config->mutex);
879 DRM_DEBUG_KMS("running encoder hotplug functions\n");
881 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
883 hpd_event_bits = dev_priv->hpd_event_bits;
884 dev_priv->hpd_event_bits = 0;
885 list_for_each_entry(connector, &mode_config->connector_list, head) {
886 intel_connector = to_intel_connector(connector);
887 intel_encoder = intel_connector->encoder;
888 if (intel_encoder->hpd_pin > HPD_NONE &&
889 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
890 connector->polled == DRM_CONNECTOR_POLL_HPD) {
891 DRM_INFO("HPD interrupt storm detected on connector %s: "
892 "switching from hotplug detection to polling\n",
893 drm_get_connector_name(connector));
894 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
895 connector->polled = DRM_CONNECTOR_POLL_CONNECT
896 | DRM_CONNECTOR_POLL_DISCONNECT;
899 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
900 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
901 drm_get_connector_name(connector), intel_encoder->hpd_pin);
904 /* if there were no outputs to poll, poll was disabled,
905 * therefore make sure it's enabled when disabling HPD on
908 drm_kms_helper_poll_enable(dev);
909 mod_timer(&dev_priv->hotplug_reenable_timer,
910 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
913 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
915 list_for_each_entry(connector, &mode_config->connector_list, head) {
916 intel_connector = to_intel_connector(connector);
917 intel_encoder = intel_connector->encoder;
918 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
919 if (intel_encoder->hot_plug)
920 intel_encoder->hot_plug(intel_encoder);
921 if (intel_hpd_irq_event(dev, connector))
925 mutex_unlock(&mode_config->mutex);
928 drm_kms_helper_hotplug_event(dev);
931 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
933 drm_i915_private_t *dev_priv = dev->dev_private;
934 u32 busy_up, busy_down, max_avg, min_avg;
937 spin_lock(&mchdev_lock);
939 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
941 new_delay = dev_priv->ips.cur_delay;
943 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
944 busy_up = I915_READ(RCPREVBSYTUPAVG);
945 busy_down = I915_READ(RCPREVBSYTDNAVG);
946 max_avg = I915_READ(RCBMAXAVG);
947 min_avg = I915_READ(RCBMINAVG);
949 /* Handle RCS change request from hw */
950 if (busy_up > max_avg) {
951 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
952 new_delay = dev_priv->ips.cur_delay - 1;
953 if (new_delay < dev_priv->ips.max_delay)
954 new_delay = dev_priv->ips.max_delay;
955 } else if (busy_down < min_avg) {
956 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
957 new_delay = dev_priv->ips.cur_delay + 1;
958 if (new_delay > dev_priv->ips.min_delay)
959 new_delay = dev_priv->ips.min_delay;
962 if (ironlake_set_drps(dev, new_delay))
963 dev_priv->ips.cur_delay = new_delay;
965 spin_unlock(&mchdev_lock);
970 static void notify_ring(struct drm_device *dev,
971 struct intel_ring_buffer *ring)
973 if (ring->obj == NULL)
976 trace_i915_gem_request_complete(ring);
978 wake_up_all(&ring->irq_queue);
979 i915_queue_hangcheck(dev);
982 static void gen6_pm_rps_work(struct work_struct *work)
984 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
989 spin_lock_irq(&dev_priv->irq_lock);
990 pm_iir = dev_priv->rps.pm_iir;
991 dev_priv->rps.pm_iir = 0;
992 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
993 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
994 spin_unlock_irq(&dev_priv->irq_lock);
996 /* Make sure we didn't queue anything we're not going to process. */
997 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
999 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1002 mutex_lock(&dev_priv->rps.hw_lock);
1004 adj = dev_priv->rps.last_adj;
1005 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1010 new_delay = dev_priv->rps.cur_delay + adj;
1013 * For better performance, jump directly
1014 * to RPe if we're below it.
1016 if (new_delay < dev_priv->rps.rpe_delay)
1017 new_delay = dev_priv->rps.rpe_delay;
1018 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1019 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1020 new_delay = dev_priv->rps.rpe_delay;
1022 new_delay = dev_priv->rps.min_delay;
1024 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1029 new_delay = dev_priv->rps.cur_delay + adj;
1030 } else { /* unknown event */
1031 new_delay = dev_priv->rps.cur_delay;
1034 /* sysfs frequency interfaces may have snuck in while servicing the
1037 new_delay = clamp_t(int, new_delay,
1038 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1039 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1041 if (IS_VALLEYVIEW(dev_priv->dev))
1042 valleyview_set_rps(dev_priv->dev, new_delay);
1044 gen6_set_rps(dev_priv->dev, new_delay);
1046 mutex_unlock(&dev_priv->rps.hw_lock);
1051 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1053 * @work: workqueue struct
1055 * Doesn't actually do anything except notify userspace. As a consequence of
1056 * this event, userspace should try to remap the bad rows since statistically
1057 * it is likely the same row is more likely to go bad again.
1059 static void ivybridge_parity_work(struct work_struct *work)
1061 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1062 l3_parity.error_work);
1063 u32 error_status, row, bank, subbank;
1064 char *parity_event[6];
1066 unsigned long flags;
1069 /* We must turn off DOP level clock gating to access the L3 registers.
1070 * In order to prevent a get/put style interface, acquire struct mutex
1071 * any time we access those registers.
1073 mutex_lock(&dev_priv->dev->struct_mutex);
1075 /* If we've screwed up tracking, just let the interrupt fire again */
1076 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1079 misccpctl = I915_READ(GEN7_MISCCPCTL);
1080 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1081 POSTING_READ(GEN7_MISCCPCTL);
1083 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1087 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1090 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1092 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1094 error_status = I915_READ(reg);
1095 row = GEN7_PARITY_ERROR_ROW(error_status);
1096 bank = GEN7_PARITY_ERROR_BANK(error_status);
1097 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1099 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1102 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1103 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1104 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1105 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1106 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1107 parity_event[5] = NULL;
1109 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1110 KOBJ_CHANGE, parity_event);
1112 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1113 slice, row, bank, subbank);
1115 kfree(parity_event[4]);
1116 kfree(parity_event[3]);
1117 kfree(parity_event[2]);
1118 kfree(parity_event[1]);
1121 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1124 WARN_ON(dev_priv->l3_parity.which_slice);
1125 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1126 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1127 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1129 mutex_unlock(&dev_priv->dev->struct_mutex);
1132 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1136 if (!HAS_L3_DPF(dev))
1139 spin_lock(&dev_priv->irq_lock);
1140 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1141 spin_unlock(&dev_priv->irq_lock);
1143 iir &= GT_PARITY_ERROR(dev);
1144 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1145 dev_priv->l3_parity.which_slice |= 1 << 1;
1147 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1148 dev_priv->l3_parity.which_slice |= 1 << 0;
1150 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1153 static void ilk_gt_irq_handler(struct drm_device *dev,
1154 struct drm_i915_private *dev_priv,
1158 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1159 notify_ring(dev, &dev_priv->ring[RCS]);
1160 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1161 notify_ring(dev, &dev_priv->ring[VCS]);
1164 static void snb_gt_irq_handler(struct drm_device *dev,
1165 struct drm_i915_private *dev_priv,
1170 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1171 notify_ring(dev, &dev_priv->ring[RCS]);
1172 if (gt_iir & GT_BSD_USER_INTERRUPT)
1173 notify_ring(dev, &dev_priv->ring[VCS]);
1174 if (gt_iir & GT_BLT_USER_INTERRUPT)
1175 notify_ring(dev, &dev_priv->ring[BCS]);
1177 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1178 GT_BSD_CS_ERROR_INTERRUPT |
1179 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1180 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1181 i915_handle_error(dev, false);
1184 if (gt_iir & GT_PARITY_ERROR(dev))
1185 ivybridge_parity_error_irq_handler(dev, gt_iir);
1188 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1189 struct drm_i915_private *dev_priv,
1194 irqreturn_t ret = IRQ_NONE;
1196 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1197 tmp = I915_READ(GEN8_GT_IIR(0));
1200 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1201 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1202 if (rcs & GT_RENDER_USER_INTERRUPT)
1203 notify_ring(dev, &dev_priv->ring[RCS]);
1204 if (bcs & GT_RENDER_USER_INTERRUPT)
1205 notify_ring(dev, &dev_priv->ring[BCS]);
1206 I915_WRITE(GEN8_GT_IIR(0), tmp);
1208 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1211 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1212 tmp = I915_READ(GEN8_GT_IIR(1));
1215 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1216 if (vcs & GT_RENDER_USER_INTERRUPT)
1217 notify_ring(dev, &dev_priv->ring[VCS]);
1218 I915_WRITE(GEN8_GT_IIR(1), tmp);
1220 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1223 if (master_ctl & GEN8_GT_VECS_IRQ) {
1224 tmp = I915_READ(GEN8_GT_IIR(3));
1227 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1228 if (vcs & GT_RENDER_USER_INTERRUPT)
1229 notify_ring(dev, &dev_priv->ring[VECS]);
1230 I915_WRITE(GEN8_GT_IIR(3), tmp);
1232 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1238 #define HPD_STORM_DETECT_PERIOD 1000
1239 #define HPD_STORM_THRESHOLD 5
1241 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1242 u32 hotplug_trigger,
1245 drm_i915_private_t *dev_priv = dev->dev_private;
1247 bool storm_detected = false;
1249 if (!hotplug_trigger)
1252 spin_lock(&dev_priv->irq_lock);
1253 for (i = 1; i < HPD_NUM_PINS; i++) {
1255 if (hpd[i] & hotplug_trigger &&
1256 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1258 * On GMCH platforms the interrupt mask bits only
1259 * prevent irq generation, not the setting of the
1260 * hotplug bits itself. So only WARN about unexpected
1261 * interrupts on saner platforms.
1263 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1264 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1265 hotplug_trigger, i, hpd[i]);
1270 if (!(hpd[i] & hotplug_trigger) ||
1271 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1274 dev_priv->hpd_event_bits |= (1 << i);
1275 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1276 dev_priv->hpd_stats[i].hpd_last_jiffies
1277 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1278 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1279 dev_priv->hpd_stats[i].hpd_cnt = 0;
1280 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1281 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1282 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1283 dev_priv->hpd_event_bits &= ~(1 << i);
1284 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1285 storm_detected = true;
1287 dev_priv->hpd_stats[i].hpd_cnt++;
1288 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1289 dev_priv->hpd_stats[i].hpd_cnt);
1294 dev_priv->display.hpd_irq_setup(dev);
1295 spin_unlock(&dev_priv->irq_lock);
1298 * Our hotplug handler can grab modeset locks (by calling down into the
1299 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1300 * queue for otherwise the flush_work in the pageflip code will
1303 schedule_work(&dev_priv->hotplug_work);
1306 static void gmbus_irq_handler(struct drm_device *dev)
1308 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1310 wake_up_all(&dev_priv->gmbus_wait_queue);
1313 static void dp_aux_irq_handler(struct drm_device *dev)
1315 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1317 wake_up_all(&dev_priv->gmbus_wait_queue);
1320 #if defined(CONFIG_DEBUG_FS)
1321 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1322 uint32_t crc0, uint32_t crc1,
1323 uint32_t crc2, uint32_t crc3,
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1328 struct intel_pipe_crc_entry *entry;
1331 spin_lock(&pipe_crc->lock);
1333 if (!pipe_crc->entries) {
1334 spin_unlock(&pipe_crc->lock);
1335 DRM_ERROR("spurious interrupt\n");
1339 head = pipe_crc->head;
1340 tail = pipe_crc->tail;
1342 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1343 spin_unlock(&pipe_crc->lock);
1344 DRM_ERROR("CRC buffer overflowing\n");
1348 entry = &pipe_crc->entries[head];
1350 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1351 entry->crc[0] = crc0;
1352 entry->crc[1] = crc1;
1353 entry->crc[2] = crc2;
1354 entry->crc[3] = crc3;
1355 entry->crc[4] = crc4;
1357 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1358 pipe_crc->head = head;
1360 spin_unlock(&pipe_crc->lock);
1362 wake_up_interruptible(&pipe_crc->wq);
1366 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1367 uint32_t crc0, uint32_t crc1,
1368 uint32_t crc2, uint32_t crc3,
1373 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1377 display_pipe_crc_irq_handler(dev, pipe,
1378 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1382 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1386 display_pipe_crc_irq_handler(dev, pipe,
1387 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1388 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1389 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1390 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1391 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1394 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 uint32_t res1, res2;
1399 if (INTEL_INFO(dev)->gen >= 3)
1400 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1404 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1405 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1409 display_pipe_crc_irq_handler(dev, pipe,
1410 I915_READ(PIPE_CRC_RES_RED(pipe)),
1411 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1412 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1416 /* The RPS events need forcewake, so we add them to a work queue and mask their
1417 * IMR bits until the work is done. Other interrupts can be processed without
1418 * the work queue. */
1419 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1421 if (pm_iir & GEN6_PM_RPS_EVENTS) {
1422 spin_lock(&dev_priv->irq_lock);
1423 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1424 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1425 spin_unlock(&dev_priv->irq_lock);
1427 queue_work(dev_priv->wq, &dev_priv->rps.work);
1430 if (HAS_VEBOX(dev_priv->dev)) {
1431 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1432 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1434 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1435 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1436 i915_handle_error(dev_priv->dev, false);
1441 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1443 struct drm_device *dev = (struct drm_device *) arg;
1444 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1445 u32 iir, gt_iir, pm_iir;
1446 irqreturn_t ret = IRQ_NONE;
1447 unsigned long irqflags;
1449 u32 pipe_stats[I915_MAX_PIPES];
1451 atomic_inc(&dev_priv->irq_received);
1454 iir = I915_READ(VLV_IIR);
1455 gt_iir = I915_READ(GTIIR);
1456 pm_iir = I915_READ(GEN6_PMIIR);
1458 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1463 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1465 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1466 for_each_pipe(pipe) {
1467 int reg = PIPESTAT(pipe);
1468 pipe_stats[pipe] = I915_READ(reg);
1471 * Clear the PIPE*STAT regs before the IIR
1473 if (pipe_stats[pipe] & 0x8000ffff) {
1474 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1475 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1477 I915_WRITE(reg, pipe_stats[pipe]);
1480 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1482 for_each_pipe(pipe) {
1483 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1484 drm_handle_vblank(dev, pipe);
1486 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1487 intel_prepare_page_flip(dev, pipe);
1488 intel_finish_page_flip(dev, pipe);
1491 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1492 i9xx_pipe_crc_irq_handler(dev, pipe);
1495 /* Consume port. Then clear IIR or we'll miss events */
1496 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1497 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1498 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1500 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1503 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1505 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1506 dp_aux_irq_handler(dev);
1508 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1509 I915_READ(PORT_HOTPLUG_STAT);
1512 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1513 gmbus_irq_handler(dev);
1516 gen6_rps_irq_handler(dev_priv, pm_iir);
1518 I915_WRITE(GTIIR, gt_iir);
1519 I915_WRITE(GEN6_PMIIR, pm_iir);
1520 I915_WRITE(VLV_IIR, iir);
1527 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1529 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1531 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1533 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1535 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1536 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1537 SDE_AUDIO_POWER_SHIFT);
1538 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1542 if (pch_iir & SDE_AUX_MASK)
1543 dp_aux_irq_handler(dev);
1545 if (pch_iir & SDE_GMBUS)
1546 gmbus_irq_handler(dev);
1548 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1549 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1551 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1552 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1554 if (pch_iir & SDE_POISON)
1555 DRM_ERROR("PCH poison interrupt\n");
1557 if (pch_iir & SDE_FDI_MASK)
1559 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1561 I915_READ(FDI_RX_IIR(pipe)));
1563 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1564 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1566 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1567 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1569 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1570 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1572 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1574 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1575 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1577 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1580 static void ivb_err_int_handler(struct drm_device *dev)
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 u32 err_int = I915_READ(GEN7_ERR_INT);
1586 if (err_int & ERR_INT_POISON)
1587 DRM_ERROR("Poison interrupt\n");
1589 for_each_pipe(pipe) {
1590 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1591 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1593 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1597 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1598 if (IS_IVYBRIDGE(dev))
1599 ivb_pipe_crc_irq_handler(dev, pipe);
1601 hsw_pipe_crc_irq_handler(dev, pipe);
1605 I915_WRITE(GEN7_ERR_INT, err_int);
1608 static void cpt_serr_int_handler(struct drm_device *dev)
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 u32 serr_int = I915_READ(SERR_INT);
1613 if (serr_int & SERR_INT_POISON)
1614 DRM_ERROR("PCH poison interrupt\n");
1616 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1617 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1619 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1621 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1622 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1624 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1626 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1627 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1629 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1631 I915_WRITE(SERR_INT, serr_int);
1634 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1636 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1638 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1640 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1642 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1643 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1644 SDE_AUDIO_POWER_SHIFT_CPT);
1645 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1649 if (pch_iir & SDE_AUX_MASK_CPT)
1650 dp_aux_irq_handler(dev);
1652 if (pch_iir & SDE_GMBUS_CPT)
1653 gmbus_irq_handler(dev);
1655 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1656 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1658 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1659 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1661 if (pch_iir & SDE_FDI_MASK_CPT)
1663 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1665 I915_READ(FDI_RX_IIR(pipe)));
1667 if (pch_iir & SDE_ERROR_CPT)
1668 cpt_serr_int_handler(dev);
1671 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1676 if (de_iir & DE_AUX_CHANNEL_A)
1677 dp_aux_irq_handler(dev);
1679 if (de_iir & DE_GSE)
1680 intel_opregion_asle_intr(dev);
1682 if (de_iir & DE_POISON)
1683 DRM_ERROR("Poison interrupt\n");
1685 for_each_pipe(pipe) {
1686 if (de_iir & DE_PIPE_VBLANK(pipe))
1687 drm_handle_vblank(dev, pipe);
1689 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1690 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1691 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1694 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1695 i9xx_pipe_crc_irq_handler(dev, pipe);
1697 /* plane/pipes map 1:1 on ilk+ */
1698 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1699 intel_prepare_page_flip(dev, pipe);
1700 intel_finish_page_flip_plane(dev, pipe);
1704 /* check event from PCH */
1705 if (de_iir & DE_PCH_EVENT) {
1706 u32 pch_iir = I915_READ(SDEIIR);
1708 if (HAS_PCH_CPT(dev))
1709 cpt_irq_handler(dev, pch_iir);
1711 ibx_irq_handler(dev, pch_iir);
1713 /* should clear PCH hotplug event before clear CPU irq */
1714 I915_WRITE(SDEIIR, pch_iir);
1717 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1718 ironlake_rps_change_irq_handler(dev);
1721 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1726 if (de_iir & DE_ERR_INT_IVB)
1727 ivb_err_int_handler(dev);
1729 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1730 dp_aux_irq_handler(dev);
1732 if (de_iir & DE_GSE_IVB)
1733 intel_opregion_asle_intr(dev);
1736 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1737 drm_handle_vblank(dev, i);
1739 /* plane/pipes map 1:1 on ilk+ */
1740 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1741 intel_prepare_page_flip(dev, i);
1742 intel_finish_page_flip_plane(dev, i);
1746 /* check event from PCH */
1747 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1748 u32 pch_iir = I915_READ(SDEIIR);
1750 cpt_irq_handler(dev, pch_iir);
1752 /* clear PCH hotplug event before clear CPU irq */
1753 I915_WRITE(SDEIIR, pch_iir);
1757 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1759 struct drm_device *dev = (struct drm_device *) arg;
1760 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1761 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1762 irqreturn_t ret = IRQ_NONE;
1764 atomic_inc(&dev_priv->irq_received);
1766 /* We get interrupts on unclaimed registers, so check for this before we
1767 * do any I915_{READ,WRITE}. */
1768 intel_uncore_check_errors(dev);
1770 /* disable master interrupt before clearing iir */
1771 de_ier = I915_READ(DEIER);
1772 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1773 POSTING_READ(DEIER);
1775 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1776 * interrupts will will be stored on its back queue, and then we'll be
1777 * able to process them after we restore SDEIER (as soon as we restore
1778 * it, we'll get an interrupt if SDEIIR still has something to process
1779 * due to its back queue). */
1780 if (!HAS_PCH_NOP(dev)) {
1781 sde_ier = I915_READ(SDEIER);
1782 I915_WRITE(SDEIER, 0);
1783 POSTING_READ(SDEIER);
1786 gt_iir = I915_READ(GTIIR);
1788 if (INTEL_INFO(dev)->gen >= 6)
1789 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1791 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1792 I915_WRITE(GTIIR, gt_iir);
1796 de_iir = I915_READ(DEIIR);
1798 if (INTEL_INFO(dev)->gen >= 7)
1799 ivb_display_irq_handler(dev, de_iir);
1801 ilk_display_irq_handler(dev, de_iir);
1802 I915_WRITE(DEIIR, de_iir);
1806 if (INTEL_INFO(dev)->gen >= 6) {
1807 u32 pm_iir = I915_READ(GEN6_PMIIR);
1809 gen6_rps_irq_handler(dev_priv, pm_iir);
1810 I915_WRITE(GEN6_PMIIR, pm_iir);
1815 I915_WRITE(DEIER, de_ier);
1816 POSTING_READ(DEIER);
1817 if (!HAS_PCH_NOP(dev)) {
1818 I915_WRITE(SDEIER, sde_ier);
1819 POSTING_READ(SDEIER);
1825 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1827 struct drm_device *dev = arg;
1828 struct drm_i915_private *dev_priv = dev->dev_private;
1830 irqreturn_t ret = IRQ_NONE;
1834 atomic_inc(&dev_priv->irq_received);
1836 master_ctl = I915_READ(GEN8_MASTER_IRQ);
1837 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1841 I915_WRITE(GEN8_MASTER_IRQ, 0);
1842 POSTING_READ(GEN8_MASTER_IRQ);
1844 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1846 if (master_ctl & GEN8_DE_MISC_IRQ) {
1847 tmp = I915_READ(GEN8_DE_MISC_IIR);
1848 if (tmp & GEN8_DE_MISC_GSE)
1849 intel_opregion_asle_intr(dev);
1851 DRM_ERROR("Unexpected DE Misc interrupt\n");
1853 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1856 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1861 if (master_ctl & GEN8_DE_PORT_IRQ) {
1862 tmp = I915_READ(GEN8_DE_PORT_IIR);
1863 if (tmp & GEN8_AUX_CHANNEL_A)
1864 dp_aux_irq_handler(dev);
1866 DRM_ERROR("Unexpected DE Port interrupt\n");
1868 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1871 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1876 for_each_pipe(pipe) {
1879 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1882 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1883 if (pipe_iir & GEN8_PIPE_VBLANK)
1884 drm_handle_vblank(dev, pipe);
1886 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1887 intel_prepare_page_flip(dev, pipe);
1888 intel_finish_page_flip_plane(dev, pipe);
1891 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1892 hsw_pipe_crc_irq_handler(dev, pipe);
1894 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1895 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1897 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1901 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1902 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1904 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1909 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1911 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1914 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1916 * FIXME(BDW): Assume for now that the new interrupt handling
1917 * scheme also closed the SDE interrupt handling race we've seen
1918 * on older pch-split platforms. But this needs testing.
1920 u32 pch_iir = I915_READ(SDEIIR);
1922 cpt_irq_handler(dev, pch_iir);
1925 I915_WRITE(SDEIIR, pch_iir);
1930 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1931 POSTING_READ(GEN8_MASTER_IRQ);
1936 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1937 bool reset_completed)
1939 struct intel_ring_buffer *ring;
1943 * Notify all waiters for GPU completion events that reset state has
1944 * been changed, and that they need to restart their wait after
1945 * checking for potential errors (and bail out to drop locks if there is
1946 * a gpu reset pending so that i915_error_work_func can acquire them).
1949 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1950 for_each_ring(ring, dev_priv, i)
1951 wake_up_all(&ring->irq_queue);
1953 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1954 wake_up_all(&dev_priv->pending_flip_queue);
1957 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1958 * reset state is cleared.
1960 if (reset_completed)
1961 wake_up_all(&dev_priv->gpu_error.reset_queue);
1965 * i915_error_work_func - do process context error handling work
1966 * @work: work struct
1968 * Fire an error uevent so userspace can see that a hang or error
1971 static void i915_error_work_func(struct work_struct *work)
1973 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1975 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1977 struct drm_device *dev = dev_priv->dev;
1978 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1979 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1980 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1983 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
1986 * Note that there's only one work item which does gpu resets, so we
1987 * need not worry about concurrent gpu resets potentially incrementing
1988 * error->reset_counter twice. We only need to take care of another
1989 * racing irq/hangcheck declaring the gpu dead for a second time. A
1990 * quick check for that is good enough: schedule_work ensures the
1991 * correct ordering between hang detection and this work item, and since
1992 * the reset in-progress bit is only ever set by code outside of this
1993 * work we don't need to worry about any other races.
1995 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1996 DRM_DEBUG_DRIVER("resetting chip\n");
1997 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2001 * All state reset _must_ be completed before we update the
2002 * reset counter, for otherwise waiters might miss the reset
2003 * pending state and not properly drop locks, resulting in
2004 * deadlocks with the reset work.
2006 ret = i915_reset(dev);
2008 intel_display_handle_reset(dev);
2012 * After all the gem state is reset, increment the reset
2013 * counter and wake up everyone waiting for the reset to
2016 * Since unlock operations are a one-sided barrier only,
2017 * we need to insert a barrier here to order any seqno
2019 * the counter increment.
2021 smp_mb__before_atomic_inc();
2022 atomic_inc(&dev_priv->gpu_error.reset_counter);
2024 kobject_uevent_env(&dev->primary->kdev->kobj,
2025 KOBJ_CHANGE, reset_done_event);
2027 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2031 * Note: The wake_up also serves as a memory barrier so that
2032 * waiters see the update value of the reset counter atomic_t.
2034 i915_error_wake_up(dev_priv, true);
2038 static void i915_report_and_clear_eir(struct drm_device *dev)
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 uint32_t instdone[I915_NUM_INSTDONE_REG];
2042 u32 eir = I915_READ(EIR);
2048 pr_err("render error detected, EIR: 0x%08x\n", eir);
2050 i915_get_extra_instdone(dev, instdone);
2053 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2054 u32 ipeir = I915_READ(IPEIR_I965);
2056 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2057 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2058 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2059 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2060 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2061 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2062 I915_WRITE(IPEIR_I965, ipeir);
2063 POSTING_READ(IPEIR_I965);
2065 if (eir & GM45_ERROR_PAGE_TABLE) {
2066 u32 pgtbl_err = I915_READ(PGTBL_ER);
2067 pr_err("page table error\n");
2068 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2069 I915_WRITE(PGTBL_ER, pgtbl_err);
2070 POSTING_READ(PGTBL_ER);
2074 if (!IS_GEN2(dev)) {
2075 if (eir & I915_ERROR_PAGE_TABLE) {
2076 u32 pgtbl_err = I915_READ(PGTBL_ER);
2077 pr_err("page table error\n");
2078 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2079 I915_WRITE(PGTBL_ER, pgtbl_err);
2080 POSTING_READ(PGTBL_ER);
2084 if (eir & I915_ERROR_MEMORY_REFRESH) {
2085 pr_err("memory refresh error:\n");
2087 pr_err("pipe %c stat: 0x%08x\n",
2088 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2089 /* pipestat has already been acked */
2091 if (eir & I915_ERROR_INSTRUCTION) {
2092 pr_err("instruction error\n");
2093 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2094 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2095 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2096 if (INTEL_INFO(dev)->gen < 4) {
2097 u32 ipeir = I915_READ(IPEIR);
2099 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2100 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2101 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2102 I915_WRITE(IPEIR, ipeir);
2103 POSTING_READ(IPEIR);
2105 u32 ipeir = I915_READ(IPEIR_I965);
2107 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2108 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2109 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2110 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2111 I915_WRITE(IPEIR_I965, ipeir);
2112 POSTING_READ(IPEIR_I965);
2116 I915_WRITE(EIR, eir);
2118 eir = I915_READ(EIR);
2121 * some errors might have become stuck,
2124 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2125 I915_WRITE(EMR, I915_READ(EMR) | eir);
2126 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2131 * i915_handle_error - handle an error interrupt
2134 * Do some basic checking of regsiter state at error interrupt time and
2135 * dump it to the syslog. Also call i915_capture_error_state() to make
2136 * sure we get a record and make it available in debugfs. Fire a uevent
2137 * so userspace knows something bad happened (should trigger collection
2138 * of a ring dump etc.).
2140 void i915_handle_error(struct drm_device *dev, bool wedged)
2142 struct drm_i915_private *dev_priv = dev->dev_private;
2144 i915_capture_error_state(dev);
2145 i915_report_and_clear_eir(dev);
2148 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2149 &dev_priv->gpu_error.reset_counter);
2152 * Wakeup waiting processes so that the reset work function
2153 * i915_error_work_func doesn't deadlock trying to grab various
2154 * locks. By bumping the reset counter first, the woken
2155 * processes will see a reset in progress and back off,
2156 * releasing their locks and then wait for the reset completion.
2157 * We must do this for _all_ gpu waiters that might hold locks
2158 * that the reset work needs to acquire.
2160 * Note: The wake_up serves as the required memory barrier to
2161 * ensure that the waiters see the updated value of the reset
2164 i915_error_wake_up(dev_priv, false);
2168 * Our reset work can grab modeset locks (since it needs to reset the
2169 * state of outstanding pagelips). Hence it must not be run on our own
2170 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2171 * code will deadlock.
2173 schedule_work(&dev_priv->gpu_error.work);
2176 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2178 drm_i915_private_t *dev_priv = dev->dev_private;
2179 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 struct drm_i915_gem_object *obj;
2182 struct intel_unpin_work *work;
2183 unsigned long flags;
2184 bool stall_detected;
2186 /* Ignore early vblank irqs */
2187 if (intel_crtc == NULL)
2190 spin_lock_irqsave(&dev->event_lock, flags);
2191 work = intel_crtc->unpin_work;
2194 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2195 !work->enable_stall_check) {
2196 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2197 spin_unlock_irqrestore(&dev->event_lock, flags);
2201 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2202 obj = work->pending_flip_obj;
2203 if (INTEL_INFO(dev)->gen >= 4) {
2204 int dspsurf = DSPSURF(intel_crtc->plane);
2205 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2206 i915_gem_obj_ggtt_offset(obj);
2208 int dspaddr = DSPADDR(intel_crtc->plane);
2209 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2210 crtc->y * crtc->fb->pitches[0] +
2211 crtc->x * crtc->fb->bits_per_pixel/8);
2214 spin_unlock_irqrestore(&dev->event_lock, flags);
2216 if (stall_detected) {
2217 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2218 intel_prepare_page_flip(dev, intel_crtc->plane);
2222 /* Called from drm generic code, passed 'crtc' which
2223 * we use as a pipe index
2225 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2227 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2228 unsigned long irqflags;
2230 if (!i915_pipe_enabled(dev, pipe))
2233 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2234 if (INTEL_INFO(dev)->gen >= 4)
2235 i915_enable_pipestat(dev_priv, pipe,
2236 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2238 i915_enable_pipestat(dev_priv, pipe,
2239 PIPE_VBLANK_INTERRUPT_ENABLE);
2241 /* maintain vblank delivery even in deep C-states */
2242 if (dev_priv->info->gen == 3)
2243 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2244 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2249 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2251 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2252 unsigned long irqflags;
2253 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2254 DE_PIPE_VBLANK(pipe);
2256 if (!i915_pipe_enabled(dev, pipe))
2259 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2260 ironlake_enable_display_irq(dev_priv, bit);
2261 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2266 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2268 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2269 unsigned long irqflags;
2272 if (!i915_pipe_enabled(dev, pipe))
2275 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2276 imr = I915_READ(VLV_IMR);
2278 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2280 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2281 I915_WRITE(VLV_IMR, imr);
2282 i915_enable_pipestat(dev_priv, pipe,
2283 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2284 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2289 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292 unsigned long irqflags;
2294 if (!i915_pipe_enabled(dev, pipe))
2297 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2298 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2299 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2300 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2301 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2305 /* Called from drm generic code, passed 'crtc' which
2306 * we use as a pipe index
2308 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2311 unsigned long irqflags;
2313 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2314 if (dev_priv->info->gen == 3)
2315 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2317 i915_disable_pipestat(dev_priv, pipe,
2318 PIPE_VBLANK_INTERRUPT_ENABLE |
2319 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2320 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2323 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2325 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2326 unsigned long irqflags;
2327 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2328 DE_PIPE_VBLANK(pipe);
2330 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2331 ironlake_disable_display_irq(dev_priv, bit);
2332 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2335 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2337 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2338 unsigned long irqflags;
2341 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2342 i915_disable_pipestat(dev_priv, pipe,
2343 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2344 imr = I915_READ(VLV_IMR);
2346 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2348 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2349 I915_WRITE(VLV_IMR, imr);
2350 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2353 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 unsigned long irqflags;
2358 if (!i915_pipe_enabled(dev, pipe))
2361 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2362 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2363 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2364 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2365 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2369 ring_last_seqno(struct intel_ring_buffer *ring)
2371 return list_entry(ring->request_list.prev,
2372 struct drm_i915_gem_request, list)->seqno;
2376 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2378 return (list_empty(&ring->request_list) ||
2379 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2382 static struct intel_ring_buffer *
2383 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2385 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2386 u32 cmd, ipehr, acthd, acthd_min;
2388 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2389 if ((ipehr & ~(0x3 << 16)) !=
2390 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2393 /* ACTHD is likely pointing to the dword after the actual command,
2394 * so scan backwards until we find the MBOX.
2396 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2397 acthd_min = max((int)acthd - 3 * 4, 0);
2399 cmd = ioread32(ring->virtual_start + acthd);
2404 if (acthd < acthd_min)
2408 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2409 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2412 static int semaphore_passed(struct intel_ring_buffer *ring)
2414 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2415 struct intel_ring_buffer *signaller;
2418 ring->hangcheck.deadlock = true;
2420 signaller = semaphore_waits_for(ring, &seqno);
2421 if (signaller == NULL || signaller->hangcheck.deadlock)
2424 /* cursory check for an unkickable deadlock */
2425 ctl = I915_READ_CTL(signaller);
2426 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2429 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2432 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2434 struct intel_ring_buffer *ring;
2437 for_each_ring(ring, dev_priv, i)
2438 ring->hangcheck.deadlock = false;
2441 static enum intel_ring_hangcheck_action
2442 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2444 struct drm_device *dev = ring->dev;
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2448 if (ring->hangcheck.acthd != acthd)
2449 return HANGCHECK_ACTIVE;
2452 return HANGCHECK_HUNG;
2454 /* Is the chip hanging on a WAIT_FOR_EVENT?
2455 * If so we can simply poke the RB_WAIT bit
2456 * and break the hang. This should work on
2457 * all but the second generation chipsets.
2459 tmp = I915_READ_CTL(ring);
2460 if (tmp & RING_WAIT) {
2461 DRM_ERROR("Kicking stuck wait on %s\n",
2463 i915_handle_error(dev, false);
2464 I915_WRITE_CTL(ring, tmp);
2465 return HANGCHECK_KICK;
2468 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2469 switch (semaphore_passed(ring)) {
2471 return HANGCHECK_HUNG;
2473 DRM_ERROR("Kicking stuck semaphore on %s\n",
2475 i915_handle_error(dev, false);
2476 I915_WRITE_CTL(ring, tmp);
2477 return HANGCHECK_KICK;
2479 return HANGCHECK_WAIT;
2483 return HANGCHECK_HUNG;
2487 * This is called when the chip hasn't reported back with completed
2488 * batchbuffers in a long time. We keep track per ring seqno progress and
2489 * if there are no progress, hangcheck score for that ring is increased.
2490 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2491 * we kick the ring. If we see no progress on three subsequent calls
2492 * we assume chip is wedged and try to fix it by resetting the chip.
2494 static void i915_hangcheck_elapsed(unsigned long data)
2496 struct drm_device *dev = (struct drm_device *)data;
2497 drm_i915_private_t *dev_priv = dev->dev_private;
2498 struct intel_ring_buffer *ring;
2500 int busy_count = 0, rings_hung = 0;
2501 bool stuck[I915_NUM_RINGS] = { 0 };
2507 if (!i915_enable_hangcheck)
2510 for_each_ring(ring, dev_priv, i) {
2514 semaphore_clear_deadlocks(dev_priv);
2516 seqno = ring->get_seqno(ring, false);
2517 acthd = intel_ring_get_active_head(ring);
2519 if (ring->hangcheck.seqno == seqno) {
2520 if (ring_idle(ring, seqno)) {
2521 ring->hangcheck.action = HANGCHECK_IDLE;
2523 if (waitqueue_active(&ring->irq_queue)) {
2524 /* Issue a wake-up to catch stuck h/w. */
2525 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2526 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2527 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2530 DRM_INFO("Fake missed irq on %s\n",
2532 wake_up_all(&ring->irq_queue);
2534 /* Safeguard against driver failure */
2535 ring->hangcheck.score += BUSY;
2539 /* We always increment the hangcheck score
2540 * if the ring is busy and still processing
2541 * the same request, so that no single request
2542 * can run indefinitely (such as a chain of
2543 * batches). The only time we do not increment
2544 * the hangcheck score on this ring, if this
2545 * ring is in a legitimate wait for another
2546 * ring. In that case the waiting ring is a
2547 * victim and we want to be sure we catch the
2548 * right culprit. Then every time we do kick
2549 * the ring, add a small increment to the
2550 * score so that we can catch a batch that is
2551 * being repeatedly kicked and so responsible
2552 * for stalling the machine.
2554 ring->hangcheck.action = ring_stuck(ring,
2557 switch (ring->hangcheck.action) {
2558 case HANGCHECK_IDLE:
2559 case HANGCHECK_WAIT:
2561 case HANGCHECK_ACTIVE:
2562 ring->hangcheck.score += BUSY;
2564 case HANGCHECK_KICK:
2565 ring->hangcheck.score += KICK;
2567 case HANGCHECK_HUNG:
2568 ring->hangcheck.score += HUNG;
2574 ring->hangcheck.action = HANGCHECK_ACTIVE;
2576 /* Gradually reduce the count so that we catch DoS
2577 * attempts across multiple batches.
2579 if (ring->hangcheck.score > 0)
2580 ring->hangcheck.score--;
2583 ring->hangcheck.seqno = seqno;
2584 ring->hangcheck.acthd = acthd;
2588 for_each_ring(ring, dev_priv, i) {
2589 if (ring->hangcheck.score > FIRE) {
2590 DRM_INFO("%s on %s\n",
2591 stuck[i] ? "stuck" : "no progress",
2598 return i915_handle_error(dev, true);
2601 /* Reset timer case chip hangs without another request
2603 i915_queue_hangcheck(dev);
2606 void i915_queue_hangcheck(struct drm_device *dev)
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 if (!i915_enable_hangcheck)
2612 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2613 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2616 static void ibx_irq_preinstall(struct drm_device *dev)
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2620 if (HAS_PCH_NOP(dev))
2623 /* south display irq */
2624 I915_WRITE(SDEIMR, 0xffffffff);
2626 * SDEIER is also touched by the interrupt handler to work around missed
2627 * PCH interrupts. Hence we can't update it after the interrupt handler
2628 * is enabled - instead we unconditionally enable all PCH interrupt
2629 * sources here, but then only unmask them as needed with SDEIMR.
2631 I915_WRITE(SDEIER, 0xffffffff);
2632 POSTING_READ(SDEIER);
2635 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2637 struct drm_i915_private *dev_priv = dev->dev_private;
2640 I915_WRITE(GTIMR, 0xffffffff);
2641 I915_WRITE(GTIER, 0x0);
2642 POSTING_READ(GTIER);
2644 if (INTEL_INFO(dev)->gen >= 6) {
2646 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2647 I915_WRITE(GEN6_PMIER, 0x0);
2648 POSTING_READ(GEN6_PMIER);
2654 static void ironlake_irq_preinstall(struct drm_device *dev)
2656 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2658 atomic_set(&dev_priv->irq_received, 0);
2660 I915_WRITE(HWSTAM, 0xeffe);
2662 I915_WRITE(DEIMR, 0xffffffff);
2663 I915_WRITE(DEIER, 0x0);
2664 POSTING_READ(DEIER);
2666 gen5_gt_irq_preinstall(dev);
2668 ibx_irq_preinstall(dev);
2671 static void valleyview_irq_preinstall(struct drm_device *dev)
2673 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2676 atomic_set(&dev_priv->irq_received, 0);
2679 I915_WRITE(VLV_IMR, 0);
2680 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2681 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2682 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2685 I915_WRITE(GTIIR, I915_READ(GTIIR));
2686 I915_WRITE(GTIIR, I915_READ(GTIIR));
2688 gen5_gt_irq_preinstall(dev);
2690 I915_WRITE(DPINVGTT, 0xff);
2692 I915_WRITE(PORT_HOTPLUG_EN, 0);
2693 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2695 I915_WRITE(PIPESTAT(pipe), 0xffff);
2696 I915_WRITE(VLV_IIR, 0xffffffff);
2697 I915_WRITE(VLV_IMR, 0xffffffff);
2698 I915_WRITE(VLV_IER, 0x0);
2699 POSTING_READ(VLV_IER);
2702 static void gen8_irq_preinstall(struct drm_device *dev)
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2707 atomic_set(&dev_priv->irq_received, 0);
2709 I915_WRITE(GEN8_MASTER_IRQ, 0);
2710 POSTING_READ(GEN8_MASTER_IRQ);
2712 /* IIR can theoretically queue up two events. Be paranoid */
2713 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2714 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2715 POSTING_READ(GEN8_##type##_IMR(which)); \
2716 I915_WRITE(GEN8_##type##_IER(which), 0); \
2717 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2718 POSTING_READ(GEN8_##type##_IIR(which)); \
2719 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2722 #define GEN8_IRQ_INIT(type) do { \
2723 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2724 POSTING_READ(GEN8_##type##_IMR); \
2725 I915_WRITE(GEN8_##type##_IER, 0); \
2726 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2727 POSTING_READ(GEN8_##type##_IIR); \
2728 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2731 GEN8_IRQ_INIT_NDX(GT, 0);
2732 GEN8_IRQ_INIT_NDX(GT, 1);
2733 GEN8_IRQ_INIT_NDX(GT, 2);
2734 GEN8_IRQ_INIT_NDX(GT, 3);
2736 for_each_pipe(pipe) {
2737 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2740 GEN8_IRQ_INIT(DE_PORT);
2741 GEN8_IRQ_INIT(DE_MISC);
2743 #undef GEN8_IRQ_INIT
2744 #undef GEN8_IRQ_INIT_NDX
2746 POSTING_READ(GEN8_PCU_IIR);
2748 ibx_irq_preinstall(dev);
2751 static void ibx_hpd_irq_setup(struct drm_device *dev)
2753 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2754 struct drm_mode_config *mode_config = &dev->mode_config;
2755 struct intel_encoder *intel_encoder;
2756 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2758 if (HAS_PCH_IBX(dev)) {
2759 hotplug_irqs = SDE_HOTPLUG_MASK;
2760 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2761 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2762 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2764 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2765 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2766 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2767 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2770 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2773 * Enable digital hotplug on the PCH, and configure the DP short pulse
2774 * duration to 2ms (which is the minimum in the Display Port spec)
2776 * This register is the same on all known PCH chips.
2778 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2779 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2780 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2781 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2782 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2783 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2786 static void ibx_irq_postinstall(struct drm_device *dev)
2788 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2791 if (HAS_PCH_NOP(dev))
2794 if (HAS_PCH_IBX(dev)) {
2795 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
2797 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2799 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2802 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2803 I915_WRITE(SDEIMR, ~mask);
2806 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 u32 pm_irqs, gt_irqs;
2811 pm_irqs = gt_irqs = 0;
2813 dev_priv->gt_irq_mask = ~0;
2814 if (HAS_L3_DPF(dev)) {
2815 /* L3 parity interrupt is always unmasked. */
2816 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2817 gt_irqs |= GT_PARITY_ERROR(dev);
2820 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2822 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2823 ILK_BSD_USER_INTERRUPT;
2825 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2828 I915_WRITE(GTIIR, I915_READ(GTIIR));
2829 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2830 I915_WRITE(GTIER, gt_irqs);
2831 POSTING_READ(GTIER);
2833 if (INTEL_INFO(dev)->gen >= 6) {
2834 pm_irqs |= GEN6_PM_RPS_EVENTS;
2837 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2839 dev_priv->pm_irq_mask = 0xffffffff;
2840 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2841 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2842 I915_WRITE(GEN6_PMIER, pm_irqs);
2843 POSTING_READ(GEN6_PMIER);
2847 static int ironlake_irq_postinstall(struct drm_device *dev)
2849 unsigned long irqflags;
2850 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2851 u32 display_mask, extra_mask;
2853 if (INTEL_INFO(dev)->gen >= 7) {
2854 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2855 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2856 DE_PLANEB_FLIP_DONE_IVB |
2857 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
2858 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2859 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
2861 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2863 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2864 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2866 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2868 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
2869 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
2872 dev_priv->irq_mask = ~display_mask;
2874 /* should always can generate irq */
2875 I915_WRITE(DEIIR, I915_READ(DEIIR));
2876 I915_WRITE(DEIMR, dev_priv->irq_mask);
2877 I915_WRITE(DEIER, display_mask | extra_mask);
2878 POSTING_READ(DEIER);
2880 gen5_gt_irq_postinstall(dev);
2882 ibx_irq_postinstall(dev);
2884 if (IS_IRONLAKE_M(dev)) {
2885 /* Enable PCU event interrupts
2887 * spinlocking not required here for correctness since interrupt
2888 * setup is guaranteed to run in single-threaded context. But we
2889 * need it to make the assert_spin_locked happy. */
2890 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2891 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2892 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2898 static int valleyview_irq_postinstall(struct drm_device *dev)
2900 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2902 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2903 PIPE_CRC_DONE_ENABLE;
2904 unsigned long irqflags;
2906 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2907 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2908 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2909 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2910 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2913 *Leave vblank interrupts masked initially. enable/disable will
2914 * toggle them based on usage.
2916 dev_priv->irq_mask = (~enable_mask) |
2917 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2918 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2920 I915_WRITE(PORT_HOTPLUG_EN, 0);
2921 POSTING_READ(PORT_HOTPLUG_EN);
2923 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2924 I915_WRITE(VLV_IER, enable_mask);
2925 I915_WRITE(VLV_IIR, 0xffffffff);
2926 I915_WRITE(PIPESTAT(0), 0xffff);
2927 I915_WRITE(PIPESTAT(1), 0xffff);
2928 POSTING_READ(VLV_IER);
2930 /* Interrupt setup is already guaranteed to be single-threaded, this is
2931 * just to make the assert_spin_locked check happy. */
2932 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2933 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2934 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2935 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2936 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2938 I915_WRITE(VLV_IIR, 0xffffffff);
2939 I915_WRITE(VLV_IIR, 0xffffffff);
2941 gen5_gt_irq_postinstall(dev);
2943 /* ack & enable invalid PTE error interrupts */
2944 #if 0 /* FIXME: add support to irq handler for checking these bits */
2945 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2946 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2949 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2954 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2958 /* These are interrupts we'll toggle with the ring mask register */
2959 uint32_t gt_interrupts[] = {
2960 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2961 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2962 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2963 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2964 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2966 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2969 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2970 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2972 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2974 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2975 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2977 POSTING_READ(GEN8_GT_IER(0));
2980 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2982 struct drm_device *dev = dev_priv->dev;
2983 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2984 GEN8_PIPE_CDCLK_CRC_DONE |
2985 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2986 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
2987 GEN8_PIPE_FIFO_UNDERRUN;
2989 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2990 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2991 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
2993 for_each_pipe(pipe) {
2994 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2996 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2998 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2999 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3001 POSTING_READ(GEN8_DE_PIPE_ISR(0));
3003 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3004 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3005 POSTING_READ(GEN8_DE_PORT_IER);
3008 static int gen8_irq_postinstall(struct drm_device *dev)
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3012 gen8_gt_irq_postinstall(dev_priv);
3013 gen8_de_irq_postinstall(dev_priv);
3015 ibx_irq_postinstall(dev);
3017 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3018 POSTING_READ(GEN8_MASTER_IRQ);
3023 static void gen8_irq_uninstall(struct drm_device *dev)
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3031 atomic_set(&dev_priv->irq_received, 0);
3033 I915_WRITE(GEN8_MASTER_IRQ, 0);
3035 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3036 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3037 I915_WRITE(GEN8_##type##_IER(which), 0); \
3038 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3041 #define GEN8_IRQ_FINI(type) do { \
3042 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3043 I915_WRITE(GEN8_##type##_IER, 0); \
3044 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3047 GEN8_IRQ_FINI_NDX(GT, 0);
3048 GEN8_IRQ_FINI_NDX(GT, 1);
3049 GEN8_IRQ_FINI_NDX(GT, 2);
3050 GEN8_IRQ_FINI_NDX(GT, 3);
3052 for_each_pipe(pipe) {
3053 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3056 GEN8_IRQ_FINI(DE_PORT);
3057 GEN8_IRQ_FINI(DE_MISC);
3059 #undef GEN8_IRQ_FINI
3060 #undef GEN8_IRQ_FINI_NDX
3062 POSTING_READ(GEN8_PCU_IIR);
3065 static void valleyview_irq_uninstall(struct drm_device *dev)
3067 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3073 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3076 I915_WRITE(PIPESTAT(pipe), 0xffff);
3078 I915_WRITE(HWSTAM, 0xffffffff);
3079 I915_WRITE(PORT_HOTPLUG_EN, 0);
3080 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3082 I915_WRITE(PIPESTAT(pipe), 0xffff);
3083 I915_WRITE(VLV_IIR, 0xffffffff);
3084 I915_WRITE(VLV_IMR, 0xffffffff);
3085 I915_WRITE(VLV_IER, 0x0);
3086 POSTING_READ(VLV_IER);
3089 static void ironlake_irq_uninstall(struct drm_device *dev)
3091 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3096 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3098 I915_WRITE(HWSTAM, 0xffffffff);
3100 I915_WRITE(DEIMR, 0xffffffff);
3101 I915_WRITE(DEIER, 0x0);
3102 I915_WRITE(DEIIR, I915_READ(DEIIR));
3104 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3106 I915_WRITE(GTIMR, 0xffffffff);
3107 I915_WRITE(GTIER, 0x0);
3108 I915_WRITE(GTIIR, I915_READ(GTIIR));
3110 if (HAS_PCH_NOP(dev))
3113 I915_WRITE(SDEIMR, 0xffffffff);
3114 I915_WRITE(SDEIER, 0x0);
3115 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3116 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3117 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3120 static void i8xx_irq_preinstall(struct drm_device * dev)
3122 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3125 atomic_set(&dev_priv->irq_received, 0);
3128 I915_WRITE(PIPESTAT(pipe), 0);
3129 I915_WRITE16(IMR, 0xffff);
3130 I915_WRITE16(IER, 0x0);
3131 POSTING_READ16(IER);
3134 static int i8xx_irq_postinstall(struct drm_device *dev)
3136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3137 unsigned long irqflags;
3140 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3142 /* Unmask the interrupts that we always want on. */
3143 dev_priv->irq_mask =
3144 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3145 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3146 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3147 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3148 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3149 I915_WRITE16(IMR, dev_priv->irq_mask);
3152 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3153 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3154 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3155 I915_USER_INTERRUPT);
3156 POSTING_READ16(IER);
3158 /* Interrupt setup is already guaranteed to be single-threaded, this is
3159 * just to make the assert_spin_locked check happy. */
3160 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3161 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3162 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3163 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3169 * Returns true when a page flip has completed.
3171 static bool i8xx_handle_vblank(struct drm_device *dev,
3172 int plane, int pipe, u32 iir)
3174 drm_i915_private_t *dev_priv = dev->dev_private;
3175 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3177 if (!drm_handle_vblank(dev, pipe))
3180 if ((iir & flip_pending) == 0)
3183 intel_prepare_page_flip(dev, plane);
3185 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3186 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3187 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3188 * the flip is completed (no longer pending). Since this doesn't raise
3189 * an interrupt per se, we watch for the change at vblank.
3191 if (I915_READ16(ISR) & flip_pending)
3194 intel_finish_page_flip(dev, pipe);
3199 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3201 struct drm_device *dev = (struct drm_device *) arg;
3202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3205 unsigned long irqflags;
3208 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3209 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3211 atomic_inc(&dev_priv->irq_received);
3213 iir = I915_READ16(IIR);
3217 while (iir & ~flip_mask) {
3218 /* Can't rely on pipestat interrupt bit in iir as it might
3219 * have been cleared after the pipestat interrupt was received.
3220 * It doesn't set the bit in iir again, but it still produces
3221 * interrupts (for non-MSI).
3223 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3224 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3225 i915_handle_error(dev, false);
3227 for_each_pipe(pipe) {
3228 int reg = PIPESTAT(pipe);
3229 pipe_stats[pipe] = I915_READ(reg);
3232 * Clear the PIPE*STAT regs before the IIR
3234 if (pipe_stats[pipe] & 0x8000ffff) {
3235 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3236 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3238 I915_WRITE(reg, pipe_stats[pipe]);
3241 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3243 I915_WRITE16(IIR, iir & ~flip_mask);
3244 new_iir = I915_READ16(IIR); /* Flush posted writes */
3246 i915_update_dri1_breadcrumb(dev);
3248 if (iir & I915_USER_INTERRUPT)
3249 notify_ring(dev, &dev_priv->ring[RCS]);
3251 for_each_pipe(pipe) {
3256 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3257 i8xx_handle_vblank(dev, plane, pipe, iir))
3258 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3260 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3261 i9xx_pipe_crc_irq_handler(dev, pipe);
3270 static void i8xx_irq_uninstall(struct drm_device * dev)
3272 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3275 for_each_pipe(pipe) {
3276 /* Clear enable bits; then clear status bits */
3277 I915_WRITE(PIPESTAT(pipe), 0);
3278 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3280 I915_WRITE16(IMR, 0xffff);
3281 I915_WRITE16(IER, 0x0);
3282 I915_WRITE16(IIR, I915_READ16(IIR));
3285 static void i915_irq_preinstall(struct drm_device * dev)
3287 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3290 atomic_set(&dev_priv->irq_received, 0);
3292 if (I915_HAS_HOTPLUG(dev)) {
3293 I915_WRITE(PORT_HOTPLUG_EN, 0);
3294 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3297 I915_WRITE16(HWSTAM, 0xeffe);
3299 I915_WRITE(PIPESTAT(pipe), 0);
3300 I915_WRITE(IMR, 0xffffffff);
3301 I915_WRITE(IER, 0x0);
3305 static int i915_irq_postinstall(struct drm_device *dev)
3307 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3309 unsigned long irqflags;
3311 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3313 /* Unmask the interrupts that we always want on. */
3314 dev_priv->irq_mask =
3315 ~(I915_ASLE_INTERRUPT |
3316 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3317 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3318 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3319 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3320 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3323 I915_ASLE_INTERRUPT |
3324 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3325 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3326 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3327 I915_USER_INTERRUPT;
3329 if (I915_HAS_HOTPLUG(dev)) {
3330 I915_WRITE(PORT_HOTPLUG_EN, 0);
3331 POSTING_READ(PORT_HOTPLUG_EN);
3333 /* Enable in IER... */
3334 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3335 /* and unmask in IMR */
3336 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3339 I915_WRITE(IMR, dev_priv->irq_mask);
3340 I915_WRITE(IER, enable_mask);
3343 i915_enable_asle_pipestat(dev);
3345 /* Interrupt setup is already guaranteed to be single-threaded, this is
3346 * just to make the assert_spin_locked check happy. */
3347 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3348 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3349 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3350 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3356 * Returns true when a page flip has completed.
3358 static bool i915_handle_vblank(struct drm_device *dev,
3359 int plane, int pipe, u32 iir)
3361 drm_i915_private_t *dev_priv = dev->dev_private;
3362 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3364 if (!drm_handle_vblank(dev, pipe))
3367 if ((iir & flip_pending) == 0)
3370 intel_prepare_page_flip(dev, plane);
3372 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3373 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3374 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3375 * the flip is completed (no longer pending). Since this doesn't raise
3376 * an interrupt per se, we watch for the change at vblank.
3378 if (I915_READ(ISR) & flip_pending)
3381 intel_finish_page_flip(dev, pipe);
3386 static irqreturn_t i915_irq_handler(int irq, void *arg)
3388 struct drm_device *dev = (struct drm_device *) arg;
3389 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3390 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3391 unsigned long irqflags;
3393 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3394 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3395 int pipe, ret = IRQ_NONE;
3397 atomic_inc(&dev_priv->irq_received);
3399 iir = I915_READ(IIR);
3401 bool irq_received = (iir & ~flip_mask) != 0;
3402 bool blc_event = false;
3404 /* Can't rely on pipestat interrupt bit in iir as it might
3405 * have been cleared after the pipestat interrupt was received.
3406 * It doesn't set the bit in iir again, but it still produces
3407 * interrupts (for non-MSI).
3409 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3410 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3411 i915_handle_error(dev, false);
3413 for_each_pipe(pipe) {
3414 int reg = PIPESTAT(pipe);
3415 pipe_stats[pipe] = I915_READ(reg);
3417 /* Clear the PIPE*STAT regs before the IIR */
3418 if (pipe_stats[pipe] & 0x8000ffff) {
3419 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3420 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3422 I915_WRITE(reg, pipe_stats[pipe]);
3423 irq_received = true;
3426 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3431 /* Consume port. Then clear IIR or we'll miss events */
3432 if ((I915_HAS_HOTPLUG(dev)) &&
3433 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3434 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3435 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3437 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3440 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3442 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3443 POSTING_READ(PORT_HOTPLUG_STAT);
3446 I915_WRITE(IIR, iir & ~flip_mask);
3447 new_iir = I915_READ(IIR); /* Flush posted writes */
3449 if (iir & I915_USER_INTERRUPT)
3450 notify_ring(dev, &dev_priv->ring[RCS]);
3452 for_each_pipe(pipe) {
3457 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3458 i915_handle_vblank(dev, plane, pipe, iir))
3459 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3461 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3464 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3465 i9xx_pipe_crc_irq_handler(dev, pipe);
3468 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3469 intel_opregion_asle_intr(dev);
3471 /* With MSI, interrupts are only generated when iir
3472 * transitions from zero to nonzero. If another bit got
3473 * set while we were handling the existing iir bits, then
3474 * we would never get another interrupt.
3476 * This is fine on non-MSI as well, as if we hit this path
3477 * we avoid exiting the interrupt handler only to generate
3480 * Note that for MSI this could cause a stray interrupt report
3481 * if an interrupt landed in the time between writing IIR and
3482 * the posting read. This should be rare enough to never
3483 * trigger the 99% of 100,000 interrupts test for disabling
3488 } while (iir & ~flip_mask);
3490 i915_update_dri1_breadcrumb(dev);
3495 static void i915_irq_uninstall(struct drm_device * dev)
3497 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3500 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3502 if (I915_HAS_HOTPLUG(dev)) {
3503 I915_WRITE(PORT_HOTPLUG_EN, 0);
3504 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3507 I915_WRITE16(HWSTAM, 0xffff);
3508 for_each_pipe(pipe) {
3509 /* Clear enable bits; then clear status bits */
3510 I915_WRITE(PIPESTAT(pipe), 0);
3511 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3513 I915_WRITE(IMR, 0xffffffff);
3514 I915_WRITE(IER, 0x0);
3516 I915_WRITE(IIR, I915_READ(IIR));
3519 static void i965_irq_preinstall(struct drm_device * dev)
3521 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3524 atomic_set(&dev_priv->irq_received, 0);
3526 I915_WRITE(PORT_HOTPLUG_EN, 0);
3527 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3529 I915_WRITE(HWSTAM, 0xeffe);
3531 I915_WRITE(PIPESTAT(pipe), 0);
3532 I915_WRITE(IMR, 0xffffffff);
3533 I915_WRITE(IER, 0x0);
3537 static int i965_irq_postinstall(struct drm_device *dev)
3539 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3542 unsigned long irqflags;
3544 /* Unmask the interrupts that we always want on. */
3545 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3546 I915_DISPLAY_PORT_INTERRUPT |
3547 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3548 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3549 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3550 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3551 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3553 enable_mask = ~dev_priv->irq_mask;
3554 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3555 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3556 enable_mask |= I915_USER_INTERRUPT;
3559 enable_mask |= I915_BSD_USER_INTERRUPT;
3561 /* Interrupt setup is already guaranteed to be single-threaded, this is
3562 * just to make the assert_spin_locked check happy. */
3563 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3564 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3565 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3566 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3567 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3570 * Enable some error detection, note the instruction error mask
3571 * bit is reserved, so we leave it masked.
3574 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3575 GM45_ERROR_MEM_PRIV |
3576 GM45_ERROR_CP_PRIV |
3577 I915_ERROR_MEMORY_REFRESH);
3579 error_mask = ~(I915_ERROR_PAGE_TABLE |
3580 I915_ERROR_MEMORY_REFRESH);
3582 I915_WRITE(EMR, error_mask);
3584 I915_WRITE(IMR, dev_priv->irq_mask);
3585 I915_WRITE(IER, enable_mask);
3588 I915_WRITE(PORT_HOTPLUG_EN, 0);
3589 POSTING_READ(PORT_HOTPLUG_EN);
3591 i915_enable_asle_pipestat(dev);
3596 static void i915_hpd_irq_setup(struct drm_device *dev)
3598 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3599 struct drm_mode_config *mode_config = &dev->mode_config;
3600 struct intel_encoder *intel_encoder;
3603 assert_spin_locked(&dev_priv->irq_lock);
3605 if (I915_HAS_HOTPLUG(dev)) {
3606 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3607 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3608 /* Note HDMI and DP share hotplug bits */
3609 /* enable bits are the same for all generations */
3610 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3611 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3612 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3613 /* Programming the CRT detection parameters tends
3614 to generate a spurious hotplug event about three
3615 seconds later. So just do it once.
3618 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3619 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3620 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3622 /* Ignore TV since it's buggy */
3623 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3627 static irqreturn_t i965_irq_handler(int irq, void *arg)
3629 struct drm_device *dev = (struct drm_device *) arg;
3630 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3632 u32 pipe_stats[I915_MAX_PIPES];
3633 unsigned long irqflags;
3635 int ret = IRQ_NONE, pipe;
3637 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3638 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3640 atomic_inc(&dev_priv->irq_received);
3642 iir = I915_READ(IIR);
3645 bool blc_event = false;
3647 irq_received = (iir & ~flip_mask) != 0;
3649 /* Can't rely on pipestat interrupt bit in iir as it might
3650 * have been cleared after the pipestat interrupt was received.
3651 * It doesn't set the bit in iir again, but it still produces
3652 * interrupts (for non-MSI).
3654 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3655 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3656 i915_handle_error(dev, false);
3658 for_each_pipe(pipe) {
3659 int reg = PIPESTAT(pipe);
3660 pipe_stats[pipe] = I915_READ(reg);
3663 * Clear the PIPE*STAT regs before the IIR
3665 if (pipe_stats[pipe] & 0x8000ffff) {
3666 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3667 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3669 I915_WRITE(reg, pipe_stats[pipe]);
3673 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3680 /* Consume port. Then clear IIR or we'll miss events */
3681 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3682 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3683 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3684 HOTPLUG_INT_STATUS_G4X :
3685 HOTPLUG_INT_STATUS_I915);
3687 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3690 intel_hpd_irq_handler(dev, hotplug_trigger,
3691 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3694 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3695 dp_aux_irq_handler(dev);
3697 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3698 I915_READ(PORT_HOTPLUG_STAT);
3701 I915_WRITE(IIR, iir & ~flip_mask);
3702 new_iir = I915_READ(IIR); /* Flush posted writes */
3704 if (iir & I915_USER_INTERRUPT)
3705 notify_ring(dev, &dev_priv->ring[RCS]);
3706 if (iir & I915_BSD_USER_INTERRUPT)
3707 notify_ring(dev, &dev_priv->ring[VCS]);
3709 for_each_pipe(pipe) {
3710 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3711 i915_handle_vblank(dev, pipe, pipe, iir))
3712 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3714 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3717 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3718 i9xx_pipe_crc_irq_handler(dev, pipe);
3722 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3723 intel_opregion_asle_intr(dev);
3725 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3726 gmbus_irq_handler(dev);
3728 /* With MSI, interrupts are only generated when iir
3729 * transitions from zero to nonzero. If another bit got
3730 * set while we were handling the existing iir bits, then
3731 * we would never get another interrupt.
3733 * This is fine on non-MSI as well, as if we hit this path
3734 * we avoid exiting the interrupt handler only to generate
3737 * Note that for MSI this could cause a stray interrupt report
3738 * if an interrupt landed in the time between writing IIR and
3739 * the posting read. This should be rare enough to never
3740 * trigger the 99% of 100,000 interrupts test for disabling
3746 i915_update_dri1_breadcrumb(dev);
3751 static void i965_irq_uninstall(struct drm_device * dev)
3753 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3759 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3761 I915_WRITE(PORT_HOTPLUG_EN, 0);
3762 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3764 I915_WRITE(HWSTAM, 0xffffffff);
3766 I915_WRITE(PIPESTAT(pipe), 0);
3767 I915_WRITE(IMR, 0xffffffff);
3768 I915_WRITE(IER, 0x0);
3771 I915_WRITE(PIPESTAT(pipe),
3772 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3773 I915_WRITE(IIR, I915_READ(IIR));
3776 static void i915_reenable_hotplug_timer_func(unsigned long data)
3778 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3779 struct drm_device *dev = dev_priv->dev;
3780 struct drm_mode_config *mode_config = &dev->mode_config;
3781 unsigned long irqflags;
3784 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3785 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3786 struct drm_connector *connector;
3788 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3791 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3793 list_for_each_entry(connector, &mode_config->connector_list, head) {
3794 struct intel_connector *intel_connector = to_intel_connector(connector);
3796 if (intel_connector->encoder->hpd_pin == i) {
3797 if (connector->polled != intel_connector->polled)
3798 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3799 drm_get_connector_name(connector));
3800 connector->polled = intel_connector->polled;
3801 if (!connector->polled)
3802 connector->polled = DRM_CONNECTOR_POLL_HPD;
3806 if (dev_priv->display.hpd_irq_setup)
3807 dev_priv->display.hpd_irq_setup(dev);
3808 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3811 void intel_irq_init(struct drm_device *dev)
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3815 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3816 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3817 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3818 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3820 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3821 i915_hangcheck_elapsed,
3822 (unsigned long) dev);
3823 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3824 (unsigned long) dev_priv);
3826 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3829 dev->max_vblank_count = 0;
3830 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3831 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3832 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3833 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3835 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3836 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3839 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3840 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3841 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3844 if (IS_VALLEYVIEW(dev)) {
3845 dev->driver->irq_handler = valleyview_irq_handler;
3846 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3847 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3848 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3849 dev->driver->enable_vblank = valleyview_enable_vblank;
3850 dev->driver->disable_vblank = valleyview_disable_vblank;
3851 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3852 } else if (IS_GEN8(dev)) {
3853 dev->driver->irq_handler = gen8_irq_handler;
3854 dev->driver->irq_preinstall = gen8_irq_preinstall;
3855 dev->driver->irq_postinstall = gen8_irq_postinstall;
3856 dev->driver->irq_uninstall = gen8_irq_uninstall;
3857 dev->driver->enable_vblank = gen8_enable_vblank;
3858 dev->driver->disable_vblank = gen8_disable_vblank;
3859 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3860 } else if (HAS_PCH_SPLIT(dev)) {
3861 dev->driver->irq_handler = ironlake_irq_handler;
3862 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3863 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3864 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3865 dev->driver->enable_vblank = ironlake_enable_vblank;
3866 dev->driver->disable_vblank = ironlake_disable_vblank;
3867 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3869 if (INTEL_INFO(dev)->gen == 2) {
3870 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3871 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3872 dev->driver->irq_handler = i8xx_irq_handler;
3873 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3874 } else if (INTEL_INFO(dev)->gen == 3) {
3875 dev->driver->irq_preinstall = i915_irq_preinstall;
3876 dev->driver->irq_postinstall = i915_irq_postinstall;
3877 dev->driver->irq_uninstall = i915_irq_uninstall;
3878 dev->driver->irq_handler = i915_irq_handler;
3879 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3881 dev->driver->irq_preinstall = i965_irq_preinstall;
3882 dev->driver->irq_postinstall = i965_irq_postinstall;
3883 dev->driver->irq_uninstall = i965_irq_uninstall;
3884 dev->driver->irq_handler = i965_irq_handler;
3885 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3887 dev->driver->enable_vblank = i915_enable_vblank;
3888 dev->driver->disable_vblank = i915_disable_vblank;
3892 void intel_hpd_init(struct drm_device *dev)
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 struct drm_mode_config *mode_config = &dev->mode_config;
3896 struct drm_connector *connector;
3897 unsigned long irqflags;
3900 for (i = 1; i < HPD_NUM_PINS; i++) {
3901 dev_priv->hpd_stats[i].hpd_cnt = 0;
3902 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3904 list_for_each_entry(connector, &mode_config->connector_list, head) {
3905 struct intel_connector *intel_connector = to_intel_connector(connector);
3906 connector->polled = intel_connector->polled;
3907 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3908 connector->polled = DRM_CONNECTOR_POLL_HPD;
3911 /* Interrupt setup is already guaranteed to be single-threaded, this is
3912 * just to make the assert_spin_locked checks happy. */
3913 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3914 if (dev_priv->display.hpd_irq_setup)
3915 dev_priv->display.hpd_irq_setup(dev);
3916 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3919 /* Disable interrupts so we can allow Package C8+. */
3920 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3922 struct drm_i915_private *dev_priv = dev->dev_private;
3923 unsigned long irqflags;
3925 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3927 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3928 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3929 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3930 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3931 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3933 ironlake_disable_display_irq(dev_priv, 0xffffffff);
3934 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3935 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3936 snb_disable_pm_irq(dev_priv, 0xffffffff);
3938 dev_priv->pc8.irqs_disabled = true;
3940 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3943 /* Restore interrupts so we can recover from Package C8+. */
3944 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 unsigned long irqflags;
3950 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3952 val = I915_READ(DEIMR);
3953 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3955 val = I915_READ(SDEIMR);
3956 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3958 val = I915_READ(GTIMR);
3959 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3961 val = I915_READ(GEN6_PMIMR);
3962 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3964 dev_priv->pc8.irqs_disabled = false;
3966 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3967 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3968 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3969 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3970 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3972 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);