drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_gen4[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pc8.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pc8.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pc8.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pc8.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pc8.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pc8.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 236                                                  enum pipe pipe, bool enable)
 237 {
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 240                                           DE_PIPEB_FIFO_UNDERRUN;
 241
 242         if (enable)
 243                 ironlake_enable_display_irq(dev_priv, bit);
 244         else
 245                 ironlake_disable_display_irq(dev_priv, bit);
 246 }
 247
 248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 249                                                   enum pipe pipe, bool enable)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         if (enable) {
 253                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 254
 255                 if (!ivb_can_enable_err_int(dev))
 256                         return;
 257
 258                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 259         } else {
 260                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 261
 262                 /* Change the state _after_ we've read out the current one. */
 263                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 264
 265                 if (!was_enabled &&
 266                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 267                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 268                                       pipe_name(pipe));
 269                 }
 270         }
 271 }
 272
 273 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 274                                                   enum pipe pipe, bool enable)
 275 {
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277
 278         assert_spin_locked(&dev_priv->irq_lock);
 279
 280         if (enable)
 281                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 282         else
 283                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 284         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 285         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 286 }
 287
 288 /**
 289  * ibx_display_interrupt_update - update SDEIMR
 290  * @dev_priv: driver private
 291  * @interrupt_mask: mask of interrupt bits to update
 292  * @enabled_irq_mask: mask of interrupt bits to enable
 293  */
 294 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 295                                          uint32_t interrupt_mask,
 296                                          uint32_t enabled_irq_mask)
 297 {
 298         uint32_t sdeimr = I915_READ(SDEIMR);
 299         sdeimr &= ~interrupt_mask;
 300         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 301
 302         assert_spin_locked(&dev_priv->irq_lock);
 303
 304         if (dev_priv->pc8.irqs_disabled &&
 305             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 306                 WARN(1, "IRQs disabled\n");
 307                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 308                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 309                                                  interrupt_mask);
 310                 return;
 311         }
 312
 313         I915_WRITE(SDEIMR, sdeimr);
 314         POSTING_READ(SDEIMR);
 315 }
 316 #define ibx_enable_display_interrupt(dev_priv, bits) \
 317         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 318 #define ibx_disable_display_interrupt(dev_priv, bits) \
 319         ibx_display_interrupt_update((dev_priv), (bits), 0)
 320
 321 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 322                                             enum transcoder pch_transcoder,
 323                                             bool enable)
 324 {
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 327                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 328
 329         if (enable)
 330                 ibx_enable_display_interrupt(dev_priv, bit);
 331         else
 332                 ibx_disable_display_interrupt(dev_priv, bit);
 333 }
 334
 335 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 336                                             enum transcoder pch_transcoder,
 337                                             bool enable)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         if (enable) {
 342                 I915_WRITE(SERR_INT,
 343                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 344
 345                 if (!cpt_can_enable_serr_int(dev))
 346                         return;
 347
 348                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 349         } else {
 350                 uint32_t tmp = I915_READ(SERR_INT);
 351                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 352
 353                 /* Change the state _after_ we've read out the current one. */
 354                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 355
 356                 if (!was_enabled &&
 357                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 358                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 359                                       transcoder_name(pch_transcoder));
 360                 }
 361         }
 362 }
 363
 364 /**
 365  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 366  * @dev: drm device
 367  * @pipe: pipe
 368  * @enable: true if we want to report FIFO underrun errors, false otherwise
 369  *
 370  * This function makes us disable or enable CPU fifo underruns for a specific
 371  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 372  * reporting for one pipe may also disable all the other CPU error interruts for
 373  * the other pipes, due to the fact that there's just one interrupt mask/enable
 374  * bit for all the pipes.
 375  *
 376  * Returns the previous state of underrun reporting.
 377  */
 378 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 379                                            enum pipe pipe, bool enable)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 384         unsigned long flags;
 385         bool ret;
 386
 387         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 388
 389         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 390
 391         if (enable == ret)
 392                 goto done;
 393
 394         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 395
 396         if (IS_GEN5(dev) || IS_GEN6(dev))
 397                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 398         else if (IS_GEN7(dev))
 399                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 400         else if (IS_GEN8(dev))
 401                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 402
 403 done:
 404         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 405         return ret;
 406 }
 407
 408 /**
 409  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 410  * @dev: drm device
 411  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 412  * @enable: true if we want to report FIFO underrun errors, false otherwise
 413  *
 414  * This function makes us disable or enable PCH fifo underruns for a specific
 415  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 416  * underrun reporting for one transcoder may also disable all the other PCH
 417  * error interruts for the other transcoders, due to the fact that there's just
 418  * one interrupt mask/enable bit for all the transcoders.
 419  *
 420  * Returns the previous state of underrun reporting.
 421  */
 422 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 423                                            enum transcoder pch_transcoder,
 424                                            bool enable)
 425 {
 426         struct drm_i915_private *dev_priv = dev->dev_private;
 427         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 429         unsigned long flags;
 430         bool ret;
 431
 432         /*
 433          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 434          * has only one pch transcoder A that all pipes can use. To avoid racy
 435          * pch transcoder -> pipe lookups from interrupt code simply store the
 436          * underrun statistics in crtc A. Since we never expose this anywhere
 437          * nor use it outside of the fifo underrun code here using the "wrong"
 438          * crtc on LPT won't cause issues.
 439          */
 440
 441         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 442
 443         ret = !intel_crtc->pch_fifo_underrun_disabled;
 444
 445         if (enable == ret)
 446                 goto done;
 447
 448         intel_crtc->pch_fifo_underrun_disabled = !enable;
 449
 450         if (HAS_PCH_IBX(dev))
 451                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 452         else
 453                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 454
 455 done:
 456         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 457         return ret;
 458 }
 459
 460
 461 void
 462 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 463 {
 464         u32 reg = PIPESTAT(pipe);
 465         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 466
 467         assert_spin_locked(&dev_priv->irq_lock);
 468
 469         if ((pipestat & mask) == mask)
 470                 return;
 471
 472         /* Enable the interrupt, clear any pending status */
 473         pipestat |= mask | (mask >> 16);
 474         I915_WRITE(reg, pipestat);
 475         POSTING_READ(reg);
 476 }
 477
 478 void
 479 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 480 {
 481         u32 reg = PIPESTAT(pipe);
 482         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 483
 484         assert_spin_locked(&dev_priv->irq_lock);
 485
 486         if ((pipestat & mask) == 0)
 487                 return;
 488
 489         pipestat &= ~mask;
 490         I915_WRITE(reg, pipestat);
 491         POSTING_READ(reg);
 492 }
 493
 494 /**
 495  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 496  */
 497 static void i915_enable_asle_pipestat(struct drm_device *dev)
 498 {
 499         drm_i915_private_t *dev_priv = dev->dev_private;
 500         unsigned long irqflags;
 501
 502         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 503                 return;
 504
 505         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 506
 507         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
 508         if (INTEL_INFO(dev)->gen >= 4)
 509                 i915_enable_pipestat(dev_priv, PIPE_A,
 510                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 511
 512         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 513 }
 514
 515 /**
 516  * i915_pipe_enabled - check if a pipe is enabled
 517  * @dev: DRM device
 518  * @pipe: pipe to check
 519  *
 520  * Reading certain registers when the pipe is disabled can hang the chip.
 521  * Use this routine to make sure the PLL is running and the pipe is active
 522  * before reading such registers if unsure.
 523  */
 524 static int
 525 i915_pipe_enabled(struct drm_device *dev, int pipe)
 526 {
 527         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 528
 529         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 530                 /* Locking is horribly broken here, but whatever. */
 531                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 532                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 533
 534                 return intel_crtc->active;
 535         } else {
 536                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 537         }
 538 }
 539
 540 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 541 {
 542         /* Gen2 doesn't have a hardware frame counter */
 543         return 0;
 544 }
 545
 546 /* Called from drm generic code, passed a 'crtc', which
 547  * we use as a pipe index
 548  */
 549 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 550 {
 551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 552         unsigned long high_frame;
 553         unsigned long low_frame;
 554         u32 high1, high2, low, pixel, vbl_start;
 555
 556         if (!i915_pipe_enabled(dev, pipe)) {
 557                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 558                                 "pipe %c\n", pipe_name(pipe));
 559                 return 0;
 560         }
 561
 562         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 563                 struct intel_crtc *intel_crtc =
 564                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 565                 const struct drm_display_mode *mode =
 566                         &intel_crtc->config.adjusted_mode;
 567
 568                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 569         } else {
 570                 enum transcoder cpu_transcoder =
 571                         intel_pipe_to_cpu_transcoder(dev_priv, pipe);
 572                 u32 htotal;
 573
 574                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 575                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 576
 577                 vbl_start *= htotal;
 578         }
 579
 580         high_frame = PIPEFRAME(pipe);
 581         low_frame = PIPEFRAMEPIXEL(pipe);
 582
 583         /*
 584          * High & low register fields aren't synchronized, so make sure
 585          * we get a low value that's stable across two reads of the high
 586          * register.
 587          */
 588         do {
 589                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 590                 low   = I915_READ(low_frame);
 591                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 592         } while (high1 != high2);
 593
 594         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 595         pixel = low & PIPE_PIXEL_MASK;
 596         low >>= PIPE_FRAME_LOW_SHIFT;
 597
 598         /*
 599          * The frame counter increments at beginning of active.
 600          * Cook up a vblank counter by also checking the pixel
 601          * counter against vblank start.
 602          */
 603         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 604 }
 605
 606 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 607 {
 608         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 609         int reg = PIPE_FRMCOUNT_GM45(pipe);
 610
 611         if (!i915_pipe_enabled(dev, pipe)) {
 612                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 613                                  "pipe %c\n", pipe_name(pipe));
 614                 return 0;
 615         }
 616
 617         return I915_READ(reg);
 618 }
 619
 620 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 621 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 622 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
 623
 624 static bool intel_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         uint32_t status;
 628         int reg;
 629
 630         if (IS_VALLEYVIEW(dev)) {
 631                 status = pipe == PIPE_A ?
 632                         I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
 633                         I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 634
 635                 reg = VLV_ISR;
 636         } else if (IS_GEN2(dev)) {
 637                 status = pipe == PIPE_A ?
 638                         I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
 639                         I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 640
 641                 reg = ISR;
 642         } else if (INTEL_INFO(dev)->gen < 5) {
 643                 status = pipe == PIPE_A ?
 644                         I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
 645                         I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 646
 647                 reg = ISR;
 648         } else if (INTEL_INFO(dev)->gen < 7) {
 649                 status = pipe == PIPE_A ?
 650                         DE_PIPEA_VBLANK :
 651                         DE_PIPEB_VBLANK;
 652
 653                 reg = DEISR;
 654         } else {
 655                 switch (pipe) {
 656                 default:
 657                 case PIPE_A:
 658                         status = DE_PIPEA_VBLANK_IVB;
 659                         break;
 660                 case PIPE_B:
 661                         status = DE_PIPEB_VBLANK_IVB;
 662                         break;
 663                 case PIPE_C:
 664                         status = DE_PIPEC_VBLANK_IVB;
 665                         break;
 666                 }
 667
 668                 reg = DEISR;
 669         }
 670
 671         if (IS_GEN2(dev))
 672                 return __raw_i915_read16(dev_priv, reg) & status;
 673         else
 674                 return __raw_i915_read32(dev_priv, reg) & status;
 675 }
 676
 677 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 678                              int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
 679 {
 680         struct drm_i915_private *dev_priv = dev->dev_private;
 681         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 683         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 684         int position;
 685         int vbl_start, vbl_end, htotal, vtotal;
 686         bool in_vbl = true;
 687         int ret = 0;
 688         unsigned long irqflags;
 689
 690         if (!intel_crtc->active) {
 691                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 692                                  "pipe %c\n", pipe_name(pipe));
 693                 return 0;
 694         }
 695
 696         htotal = mode->crtc_htotal;
 697         vtotal = mode->crtc_vtotal;
 698         vbl_start = mode->crtc_vblank_start;
 699         vbl_end = mode->crtc_vblank_end;
 700
 701         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 702
 703         /*
 704          * Lock uncore.lock, as we will do multiple timing critical raw
 705          * register reads, potentially with preemption disabled, so the
 706          * following code must not block on uncore.lock.
 707          */
 708         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 709
 710         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 711
 712         /* Get optional system timestamp before query. */
 713         if (stime)
 714                 *stime = ktime_get();
 715
 716         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 717                 /* No obvious pixelcount register. Only query vertical
 718                  * scanout position from Display scan line register.
 719                  */
 720                 if (IS_GEN2(dev))
 721                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 722                 else
 723                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 724
 725                 /*
 726                  * The scanline counter increments at the leading edge
 727                  * of hsync, ie. it completely misses the active portion
 728                  * of the line. Fix up the counter at both edges of vblank
 729                  * to get a more accurate picture whether we're in vblank
 730                  * or not.
 731                  */
 732                 in_vbl = intel_pipe_in_vblank_locked(dev, pipe);
 733                 if ((in_vbl && position == vbl_start - 1) ||
 734                     (!in_vbl && position == vbl_end - 1))
 735                         position = (position + 1) % vtotal;
 736         } else {
 737                 /* Have access to pixelcount since start of frame.
 738                  * We can split this into vertical and horizontal
 739                  * scanout position.
 740                  */
 741                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 742
 743                 /* convert to pixel counts */
 744                 vbl_start *= htotal;
 745                 vbl_end *= htotal;
 746                 vtotal *= htotal;
 747         }
 748
 749         /* Get optional system timestamp after query. */
 750         if (etime)
 751                 *etime = ktime_get();
 752
 753         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 754
 755         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 756
 757         in_vbl = position >= vbl_start && position < vbl_end;
 758
 759         /*
 760          * While in vblank, position will be negative
 761          * counting up towards 0 at vbl_end. And outside
 762          * vblank, position will be positive counting
 763          * up since vbl_end.
 764          */
 765         if (position >= vbl_start)
 766                 position -= vbl_end;
 767         else
 768                 position += vtotal - vbl_end;
 769
 770         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 771                 *vpos = position;
 772                 *hpos = 0;
 773         } else {
 774                 *vpos = position / htotal;
 775                 *hpos = position - (*vpos * htotal);
 776         }
 777
 778         /* In vblank? */
 779         if (in_vbl)
 780                 ret |= DRM_SCANOUTPOS_INVBL;
 781
 782         return ret;
 783 }
 784
 785 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 786                               int *max_error,
 787                               struct timeval *vblank_time,
 788                               unsigned flags)
 789 {
 790         struct drm_crtc *crtc;
 791
 792         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 793                 DRM_ERROR("Invalid crtc %d\n", pipe);
 794                 return -EINVAL;
 795         }
 796
 797         /* Get drm_crtc to timestamp: */
 798         crtc = intel_get_crtc_for_pipe(dev, pipe);
 799         if (crtc == NULL) {
 800                 DRM_ERROR("Invalid crtc %d\n", pipe);
 801                 return -EINVAL;
 802         }
 803
 804         if (!crtc->enabled) {
 805                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 806                 return -EBUSY;
 807         }
 808
 809         /* Helper routine in DRM core does all the work: */
 810         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 811                                                      vblank_time, flags,
 812                                                      crtc);
 813 }
 814
 815 static bool intel_hpd_irq_event(struct drm_device *dev,
 816                                 struct drm_connector *connector)
 817 {
 818         enum drm_connector_status old_status;
 819
 820         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 821         old_status = connector->status;
 822
 823         connector->status = connector->funcs->detect(connector, false);
 824         if (old_status == connector->status)
 825                 return false;
 826
 827         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 828                       connector->base.id,
 829                       drm_get_connector_name(connector),
 830                       drm_get_connector_status_name(old_status),
 831                       drm_get_connector_status_name(connector->status));
 832
 833         return true;
 834 }
 835
 836 /*
 837  * Handle hotplug events outside the interrupt handler proper.
 838  */
 839 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 840
 841 static void i915_hotplug_work_func(struct work_struct *work)
 842 {
 843         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 844                                                     hotplug_work);
 845         struct drm_device *dev = dev_priv->dev;
 846         struct drm_mode_config *mode_config = &dev->mode_config;
 847         struct intel_connector *intel_connector;
 848         struct intel_encoder *intel_encoder;
 849         struct drm_connector *connector;
 850         unsigned long irqflags;
 851         bool hpd_disabled = false;
 852         bool changed = false;
 853         u32 hpd_event_bits;
 854
 855         /* HPD irq before everything is fully set up. */
 856         if (!dev_priv->enable_hotplug_processing)
 857                 return;
 858
 859         mutex_lock(&mode_config->mutex);
 860         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 861
 862         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 863
 864         hpd_event_bits = dev_priv->hpd_event_bits;
 865         dev_priv->hpd_event_bits = 0;
 866         list_for_each_entry(connector, &mode_config->connector_list, head) {
 867                 intel_connector = to_intel_connector(connector);
 868                 intel_encoder = intel_connector->encoder;
 869                 if (intel_encoder->hpd_pin > HPD_NONE &&
 870                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 871                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 872                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 873                                  "switching from hotplug detection to polling\n",
 874                                 drm_get_connector_name(connector));
 875                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 876                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 877                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 878                         hpd_disabled = true;
 879                 }
 880                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 881                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 882                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 883                 }
 884         }
 885          /* if there were no outputs to poll, poll was disabled,
 886           * therefore make sure it's enabled when disabling HPD on
 887           * some connectors */
 888         if (hpd_disabled) {
 889                 drm_kms_helper_poll_enable(dev);
 890                 mod_timer(&dev_priv->hotplug_reenable_timer,
 891                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 892         }
 893
 894         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 895
 896         list_for_each_entry(connector, &mode_config->connector_list, head) {
 897                 intel_connector = to_intel_connector(connector);
 898                 intel_encoder = intel_connector->encoder;
 899                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 900                         if (intel_encoder->hot_plug)
 901                                 intel_encoder->hot_plug(intel_encoder);
 902                         if (intel_hpd_irq_event(dev, connector))
 903                                 changed = true;
 904                 }
 905         }
 906         mutex_unlock(&mode_config->mutex);
 907
 908         if (changed)
 909                 drm_kms_helper_hotplug_event(dev);
 910 }
 911
 912 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 913 {
 914         drm_i915_private_t *dev_priv = dev->dev_private;
 915         u32 busy_up, busy_down, max_avg, min_avg;
 916         u8 new_delay;
 917
 918         spin_lock(&mchdev_lock);
 919
 920         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 921
 922         new_delay = dev_priv->ips.cur_delay;
 923
 924         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 925         busy_up = I915_READ(RCPREVBSYTUPAVG);
 926         busy_down = I915_READ(RCPREVBSYTDNAVG);
 927         max_avg = I915_READ(RCBMAXAVG);
 928         min_avg = I915_READ(RCBMINAVG);
 929
 930         /* Handle RCS change request from hw */
 931         if (busy_up > max_avg) {
 932                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 933                         new_delay = dev_priv->ips.cur_delay - 1;
 934                 if (new_delay < dev_priv->ips.max_delay)
 935                         new_delay = dev_priv->ips.max_delay;
 936         } else if (busy_down < min_avg) {
 937                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 938                         new_delay = dev_priv->ips.cur_delay + 1;
 939                 if (new_delay > dev_priv->ips.min_delay)
 940                         new_delay = dev_priv->ips.min_delay;
 941         }
 942
 943         if (ironlake_set_drps(dev, new_delay))
 944                 dev_priv->ips.cur_delay = new_delay;
 945
 946         spin_unlock(&mchdev_lock);
 947
 948         return;
 949 }
 950
 951 static void notify_ring(struct drm_device *dev,
 952                         struct intel_ring_buffer *ring)
 953 {
 954         if (ring->obj == NULL)
 955                 return;
 956
 957         trace_i915_gem_request_complete(ring);
 958
 959         wake_up_all(&ring->irq_queue);
 960         i915_queue_hangcheck(dev);
 961 }
 962
 963 static void gen6_pm_rps_work(struct work_struct *work)
 964 {
 965         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 966                                                     rps.work);
 967         u32 pm_iir;
 968         int new_delay, adj;
 969
 970         spin_lock_irq(&dev_priv->irq_lock);
 971         pm_iir = dev_priv->rps.pm_iir;
 972         dev_priv->rps.pm_iir = 0;
 973         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
 974         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
 975         spin_unlock_irq(&dev_priv->irq_lock);
 976
 977         /* Make sure we didn't queue anything we're not going to process. */
 978         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
 979
 980         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
 981                 return;
 982
 983         mutex_lock(&dev_priv->rps.hw_lock);
 984
 985         adj = dev_priv->rps.last_adj;
 986         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 987                 if (adj > 0)
 988                         adj *= 2;
 989                 else
 990                         adj = 1;
 991                 new_delay = dev_priv->rps.cur_delay + adj;
 992
 993                 /*
 994                  * For better performance, jump directly
 995                  * to RPe if we're below it.
 996                  */
 997                 if (new_delay < dev_priv->rps.rpe_delay)
 998                         new_delay = dev_priv->rps.rpe_delay;
 999         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1000                 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1001                         new_delay = dev_priv->rps.rpe_delay;
1002                 else
1003                         new_delay = dev_priv->rps.min_delay;
1004                 adj = 0;
1005         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1006                 if (adj < 0)
1007                         adj *= 2;
1008                 else
1009                         adj = -1;
1010                 new_delay = dev_priv->rps.cur_delay + adj;
1011         } else { /* unknown event */
1012                 new_delay = dev_priv->rps.cur_delay;
1013         }
1014
1015         /* sysfs frequency interfaces may have snuck in while servicing the
1016          * interrupt
1017          */
1018         new_delay = clamp_t(int, new_delay,
1019                             dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1020         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1021
1022         if (IS_VALLEYVIEW(dev_priv->dev))
1023                 valleyview_set_rps(dev_priv->dev, new_delay);
1024         else
1025                 gen6_set_rps(dev_priv->dev, new_delay);
1026
1027         mutex_unlock(&dev_priv->rps.hw_lock);
1028 }
1029
1030
1031 /**
1032  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1033  * occurred.
1034  * @work: workqueue struct
1035  *
1036  * Doesn't actually do anything except notify userspace. As a consequence of
1037  * this event, userspace should try to remap the bad rows since statistically
1038  * it is likely the same row is more likely to go bad again.
1039  */
1040 static void ivybridge_parity_work(struct work_struct *work)
1041 {
1042         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1043                                                     l3_parity.error_work);
1044         u32 error_status, row, bank, subbank;
1045         char *parity_event[6];
1046         uint32_t misccpctl;
1047         unsigned long flags;
1048         uint8_t slice = 0;
1049
1050         /* We must turn off DOP level clock gating to access the L3 registers.
1051          * In order to prevent a get/put style interface, acquire struct mutex
1052          * any time we access those registers.
1053          */
1054         mutex_lock(&dev_priv->dev->struct_mutex);
1055
1056         /* If we've screwed up tracking, just let the interrupt fire again */
1057         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1058                 goto out;
1059
1060         misccpctl = I915_READ(GEN7_MISCCPCTL);
1061         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1062         POSTING_READ(GEN7_MISCCPCTL);
1063
1064         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1065                 u32 reg;
1066
1067                 slice--;
1068                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1069                         break;
1070
1071                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1072
1073                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1074
1075                 error_status = I915_READ(reg);
1076                 row = GEN7_PARITY_ERROR_ROW(error_status);
1077                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1078                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1079
1080                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1081                 POSTING_READ(reg);
1082
1083                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1084                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1085                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1086                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1087                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1088                 parity_event[5] = NULL;
1089
1090                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1091                                    KOBJ_CHANGE, parity_event);
1092
1093                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1094                           slice, row, bank, subbank);
1095
1096                 kfree(parity_event[4]);
1097                 kfree(parity_event[3]);
1098                 kfree(parity_event[2]);
1099                 kfree(parity_event[1]);
1100         }
1101
1102         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1103
1104 out:
1105         WARN_ON(dev_priv->l3_parity.which_slice);
1106         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1107         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1108         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1109
1110         mutex_unlock(&dev_priv->dev->struct_mutex);
1111 }
1112
1113 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1114 {
1115         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1116
1117         if (!HAS_L3_DPF(dev))
1118                 return;
1119
1120         spin_lock(&dev_priv->irq_lock);
1121         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1122         spin_unlock(&dev_priv->irq_lock);
1123
1124         iir &= GT_PARITY_ERROR(dev);
1125         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1126                 dev_priv->l3_parity.which_slice |= 1 << 1;
1127
1128         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1129                 dev_priv->l3_parity.which_slice |= 1 << 0;
1130
1131         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1132 }
1133
1134 static void ilk_gt_irq_handler(struct drm_device *dev,
1135                                struct drm_i915_private *dev_priv,
1136                                u32 gt_iir)
1137 {
1138         if (gt_iir &
1139             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1140                 notify_ring(dev, &dev_priv->ring[RCS]);
1141         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1142                 notify_ring(dev, &dev_priv->ring[VCS]);
1143 }
1144
1145 static void snb_gt_irq_handler(struct drm_device *dev,
1146                                struct drm_i915_private *dev_priv,
1147                                u32 gt_iir)
1148 {
1149
1150         if (gt_iir &
1151             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1152                 notify_ring(dev, &dev_priv->ring[RCS]);
1153         if (gt_iir & GT_BSD_USER_INTERRUPT)
1154                 notify_ring(dev, &dev_priv->ring[VCS]);
1155         if (gt_iir & GT_BLT_USER_INTERRUPT)
1156                 notify_ring(dev, &dev_priv->ring[BCS]);
1157
1158         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1159                       GT_BSD_CS_ERROR_INTERRUPT |
1160                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1161                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1162                 i915_handle_error(dev, false);
1163         }
1164
1165         if (gt_iir & GT_PARITY_ERROR(dev))
1166                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1167 }
1168
1169 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1170                                        struct drm_i915_private *dev_priv,
1171                                        u32 master_ctl)
1172 {
1173         u32 rcs, bcs, vcs;
1174         uint32_t tmp = 0;
1175         irqreturn_t ret = IRQ_NONE;
1176
1177         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1178                 tmp = I915_READ(GEN8_GT_IIR(0));
1179                 if (tmp) {
1180                         ret = IRQ_HANDLED;
1181                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1182                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1183                         if (rcs & GT_RENDER_USER_INTERRUPT)
1184                                 notify_ring(dev, &dev_priv->ring[RCS]);
1185                         if (bcs & GT_RENDER_USER_INTERRUPT)
1186                                 notify_ring(dev, &dev_priv->ring[BCS]);
1187                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1188                 } else
1189                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1190         }
1191
1192         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1193                 tmp = I915_READ(GEN8_GT_IIR(1));
1194                 if (tmp) {
1195                         ret = IRQ_HANDLED;
1196                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1197                         if (vcs & GT_RENDER_USER_INTERRUPT)
1198                                 notify_ring(dev, &dev_priv->ring[VCS]);
1199                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1200                 } else
1201                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1202         }
1203
1204         if (master_ctl & GEN8_GT_VECS_IRQ) {
1205                 tmp = I915_READ(GEN8_GT_IIR(3));
1206                 if (tmp) {
1207                         ret = IRQ_HANDLED;
1208                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1209                         if (vcs & GT_RENDER_USER_INTERRUPT)
1210                                 notify_ring(dev, &dev_priv->ring[VECS]);
1211                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1212                 } else
1213                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1214         }
1215
1216         return ret;
1217 }
1218
1219 #define HPD_STORM_DETECT_PERIOD 1000
1220 #define HPD_STORM_THRESHOLD 5
1221
1222 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1223                                          u32 hotplug_trigger,
1224                                          const u32 *hpd)
1225 {
1226         drm_i915_private_t *dev_priv = dev->dev_private;
1227         int i;
1228         bool storm_detected = false;
1229
1230         if (!hotplug_trigger)
1231                 return;
1232
1233         spin_lock(&dev_priv->irq_lock);
1234         for (i = 1; i < HPD_NUM_PINS; i++) {
1235
1236                 WARN(((hpd[i] & hotplug_trigger) &&
1237                       dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1238                      "Received HPD interrupt although disabled\n");
1239
1240                 if (!(hpd[i] & hotplug_trigger) ||
1241                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1242                         continue;
1243
1244                 dev_priv->hpd_event_bits |= (1 << i);
1245                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1246                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1247                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1248                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1249                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1250                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1251                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1252                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1253                         dev_priv->hpd_event_bits &= ~(1 << i);
1254                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1255                         storm_detected = true;
1256                 } else {
1257                         dev_priv->hpd_stats[i].hpd_cnt++;
1258                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1259                                       dev_priv->hpd_stats[i].hpd_cnt);
1260                 }
1261         }
1262
1263         if (storm_detected)
1264                 dev_priv->display.hpd_irq_setup(dev);
1265         spin_unlock(&dev_priv->irq_lock);
1266
1267         /*
1268          * Our hotplug handler can grab modeset locks (by calling down into the
1269          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1270          * queue for otherwise the flush_work in the pageflip code will
1271          * deadlock.
1272          */
1273         schedule_work(&dev_priv->hotplug_work);
1274 }
1275
1276 static void gmbus_irq_handler(struct drm_device *dev)
1277 {
1278         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1279
1280         wake_up_all(&dev_priv->gmbus_wait_queue);
1281 }
1282
1283 static void dp_aux_irq_handler(struct drm_device *dev)
1284 {
1285         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1286
1287         wake_up_all(&dev_priv->gmbus_wait_queue);
1288 }
1289
1290 #if defined(CONFIG_DEBUG_FS)
1291 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1292                                          uint32_t crc0, uint32_t crc1,
1293                                          uint32_t crc2, uint32_t crc3,
1294                                          uint32_t crc4)
1295 {
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1298         struct intel_pipe_crc_entry *entry;
1299         int head, tail;
1300
1301         spin_lock(&pipe_crc->lock);
1302
1303         if (!pipe_crc->entries) {
1304                 spin_unlock(&pipe_crc->lock);
1305                 DRM_ERROR("spurious interrupt\n");
1306                 return;
1307         }
1308
1309         head = pipe_crc->head;
1310         tail = pipe_crc->tail;
1311
1312         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1313                 spin_unlock(&pipe_crc->lock);
1314                 DRM_ERROR("CRC buffer overflowing\n");
1315                 return;
1316         }
1317
1318         entry = &pipe_crc->entries[head];
1319
1320         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1321         entry->crc[0] = crc0;
1322         entry->crc[1] = crc1;
1323         entry->crc[2] = crc2;
1324         entry->crc[3] = crc3;
1325         entry->crc[4] = crc4;
1326
1327         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1328         pipe_crc->head = head;
1329
1330         spin_unlock(&pipe_crc->lock);
1331
1332         wake_up_interruptible(&pipe_crc->wq);
1333 }
1334 #else
1335 static inline void
1336 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1337                              uint32_t crc0, uint32_t crc1,
1338                              uint32_t crc2, uint32_t crc3,
1339                              uint32_t crc4) {}
1340 #endif
1341
1342
1343 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1344 {
1345         struct drm_i915_private *dev_priv = dev->dev_private;
1346
1347         display_pipe_crc_irq_handler(dev, pipe,
1348                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1349                                      0, 0, 0, 0);
1350 }
1351
1352 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1353 {
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355
1356         display_pipe_crc_irq_handler(dev, pipe,
1357                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1358                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1359                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1360                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1361                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1362 }
1363
1364 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1365 {
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         uint32_t res1, res2;
1368
1369         if (INTEL_INFO(dev)->gen >= 3)
1370                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1371         else
1372                 res1 = 0;
1373
1374         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1375                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1376         else
1377                 res2 = 0;
1378
1379         display_pipe_crc_irq_handler(dev, pipe,
1380                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1381                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1382                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1383                                      res1, res2);
1384 }
1385
1386 /* The RPS events need forcewake, so we add them to a work queue and mask their
1387  * IMR bits until the work is done. Other interrupts can be processed without
1388  * the work queue. */
1389 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1390 {
1391         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1392                 spin_lock(&dev_priv->irq_lock);
1393                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1394                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1395                 spin_unlock(&dev_priv->irq_lock);
1396
1397                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1398         }
1399
1400         if (HAS_VEBOX(dev_priv->dev)) {
1401                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1402                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1403
1404                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1405                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1406                         i915_handle_error(dev_priv->dev, false);
1407                 }
1408         }
1409 }
1410
1411 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1412 {
1413         struct drm_device *dev = (struct drm_device *) arg;
1414         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1415         u32 iir, gt_iir, pm_iir;
1416         irqreturn_t ret = IRQ_NONE;
1417         unsigned long irqflags;
1418         int pipe;
1419         u32 pipe_stats[I915_MAX_PIPES];
1420
1421         atomic_inc(&dev_priv->irq_received);
1422
1423         while (true) {
1424                 iir = I915_READ(VLV_IIR);
1425                 gt_iir = I915_READ(GTIIR);
1426                 pm_iir = I915_READ(GEN6_PMIIR);
1427
1428                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1429                         goto out;
1430
1431                 ret = IRQ_HANDLED;
1432
1433                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1434
1435                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1436                 for_each_pipe(pipe) {
1437                         int reg = PIPESTAT(pipe);
1438                         pipe_stats[pipe] = I915_READ(reg);
1439
1440                         /*
1441                          * Clear the PIPE*STAT regs before the IIR
1442                          */
1443                         if (pipe_stats[pipe] & 0x8000ffff) {
1444                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1445                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1446                                                          pipe_name(pipe));
1447                                 I915_WRITE(reg, pipe_stats[pipe]);
1448                         }
1449                 }
1450                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1451
1452                 for_each_pipe(pipe) {
1453                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1454                                 drm_handle_vblank(dev, pipe);
1455
1456                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1457                                 intel_prepare_page_flip(dev, pipe);
1458                                 intel_finish_page_flip(dev, pipe);
1459                         }
1460
1461                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1462                                 i9xx_pipe_crc_irq_handler(dev, pipe);
1463                 }
1464
1465                 /* Consume port.  Then clear IIR or we'll miss events */
1466                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1467                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1468                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1469
1470                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1471                                          hotplug_status);
1472
1473                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1474
1475                         if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1476                                 dp_aux_irq_handler(dev);
1477
1478                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1479                         I915_READ(PORT_HOTPLUG_STAT);
1480                 }
1481
1482                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1483                         gmbus_irq_handler(dev);
1484
1485                 if (pm_iir)
1486                         gen6_rps_irq_handler(dev_priv, pm_iir);
1487
1488                 I915_WRITE(GTIIR, gt_iir);
1489                 I915_WRITE(GEN6_PMIIR, pm_iir);
1490                 I915_WRITE(VLV_IIR, iir);
1491         }
1492
1493 out:
1494         return ret;
1495 }
1496
1497 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1498 {
1499         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500         int pipe;
1501         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1502
1503         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1504
1505         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1506                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1507                                SDE_AUDIO_POWER_SHIFT);
1508                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1509                                  port_name(port));
1510         }
1511
1512         if (pch_iir & SDE_AUX_MASK)
1513                 dp_aux_irq_handler(dev);
1514
1515         if (pch_iir & SDE_GMBUS)
1516                 gmbus_irq_handler(dev);
1517
1518         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1519                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1520
1521         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1522                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1523
1524         if (pch_iir & SDE_POISON)
1525                 DRM_ERROR("PCH poison interrupt\n");
1526
1527         if (pch_iir & SDE_FDI_MASK)
1528                 for_each_pipe(pipe)
1529                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1530                                          pipe_name(pipe),
1531                                          I915_READ(FDI_RX_IIR(pipe)));
1532
1533         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1534                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1535
1536         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1537                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1538
1539         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1540                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1541                                                           false))
1542                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1543
1544         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1545                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1546                                                           false))
1547                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1548 }
1549
1550 static void ivb_err_int_handler(struct drm_device *dev)
1551 {
1552         struct drm_i915_private *dev_priv = dev->dev_private;
1553         u32 err_int = I915_READ(GEN7_ERR_INT);
1554         enum pipe pipe;
1555
1556         if (err_int & ERR_INT_POISON)
1557                 DRM_ERROR("Poison interrupt\n");
1558
1559         for_each_pipe(pipe) {
1560                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1561                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1562                                                                   false))
1563                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1564                                                  pipe_name(pipe));
1565                 }
1566
1567                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1568                         if (IS_IVYBRIDGE(dev))
1569                                 ivb_pipe_crc_irq_handler(dev, pipe);
1570                         else
1571                                 hsw_pipe_crc_irq_handler(dev, pipe);
1572                 }
1573         }
1574
1575         I915_WRITE(GEN7_ERR_INT, err_int);
1576 }
1577
1578 static void cpt_serr_int_handler(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         u32 serr_int = I915_READ(SERR_INT);
1582
1583         if (serr_int & SERR_INT_POISON)
1584                 DRM_ERROR("PCH poison interrupt\n");
1585
1586         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1587                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1588                                                           false))
1589                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1590
1591         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1592                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1593                                                           false))
1594                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1595
1596         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1597                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1598                                                           false))
1599                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1600
1601         I915_WRITE(SERR_INT, serr_int);
1602 }
1603
1604 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1605 {
1606         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1607         int pipe;
1608         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1609
1610         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1611
1612         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1613                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1614                                SDE_AUDIO_POWER_SHIFT_CPT);
1615                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1616                                  port_name(port));
1617         }
1618
1619         if (pch_iir & SDE_AUX_MASK_CPT)
1620                 dp_aux_irq_handler(dev);
1621
1622         if (pch_iir & SDE_GMBUS_CPT)
1623                 gmbus_irq_handler(dev);
1624
1625         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1626                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1627
1628         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1629                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1630
1631         if (pch_iir & SDE_FDI_MASK_CPT)
1632                 for_each_pipe(pipe)
1633                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1634                                          pipe_name(pipe),
1635                                          I915_READ(FDI_RX_IIR(pipe)));
1636
1637         if (pch_iir & SDE_ERROR_CPT)
1638                 cpt_serr_int_handler(dev);
1639 }
1640
1641 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1642 {
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         enum pipe pipe;
1645
1646         if (de_iir & DE_AUX_CHANNEL_A)
1647                 dp_aux_irq_handler(dev);
1648
1649         if (de_iir & DE_GSE)
1650                 intel_opregion_asle_intr(dev);
1651
1652         if (de_iir & DE_POISON)
1653                 DRM_ERROR("Poison interrupt\n");
1654
1655         for_each_pipe(pipe) {
1656                 if (de_iir & DE_PIPE_VBLANK(pipe))
1657                         drm_handle_vblank(dev, pipe);
1658
1659                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1660                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1661                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1662                                                  pipe_name(pipe));
1663
1664                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1665                         i9xx_pipe_crc_irq_handler(dev, pipe);
1666
1667                 /* plane/pipes map 1:1 on ilk+ */
1668                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1669                         intel_prepare_page_flip(dev, pipe);
1670                         intel_finish_page_flip_plane(dev, pipe);
1671                 }
1672         }
1673
1674         /* check event from PCH */
1675         if (de_iir & DE_PCH_EVENT) {
1676                 u32 pch_iir = I915_READ(SDEIIR);
1677
1678                 if (HAS_PCH_CPT(dev))
1679                         cpt_irq_handler(dev, pch_iir);
1680                 else
1681                         ibx_irq_handler(dev, pch_iir);
1682
1683                 /* should clear PCH hotplug event before clear CPU irq */
1684                 I915_WRITE(SDEIIR, pch_iir);
1685         }
1686
1687         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1688                 ironlake_rps_change_irq_handler(dev);
1689 }
1690
1691 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1692 {
1693         struct drm_i915_private *dev_priv = dev->dev_private;
1694         enum pipe i;
1695
1696         if (de_iir & DE_ERR_INT_IVB)
1697                 ivb_err_int_handler(dev);
1698
1699         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1700                 dp_aux_irq_handler(dev);
1701
1702         if (de_iir & DE_GSE_IVB)
1703                 intel_opregion_asle_intr(dev);
1704
1705         for_each_pipe(i) {
1706                 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1707                         drm_handle_vblank(dev, i);
1708
1709                 /* plane/pipes map 1:1 on ilk+ */
1710                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1711                         intel_prepare_page_flip(dev, i);
1712                         intel_finish_page_flip_plane(dev, i);
1713                 }
1714         }
1715
1716         /* check event from PCH */
1717         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1718                 u32 pch_iir = I915_READ(SDEIIR);
1719
1720                 cpt_irq_handler(dev, pch_iir);
1721
1722                 /* clear PCH hotplug event before clear CPU irq */
1723                 I915_WRITE(SDEIIR, pch_iir);
1724         }
1725 }
1726
1727 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1728 {
1729         struct drm_device *dev = (struct drm_device *) arg;
1730         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1731         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1732         irqreturn_t ret = IRQ_NONE;
1733
1734         atomic_inc(&dev_priv->irq_received);
1735
1736         /* We get interrupts on unclaimed registers, so check for this before we
1737          * do any I915_{READ,WRITE}. */
1738         intel_uncore_check_errors(dev);
1739
1740         /* disable master interrupt before clearing iir  */
1741         de_ier = I915_READ(DEIER);
1742         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1743         POSTING_READ(DEIER);
1744
1745         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1746          * interrupts will will be stored on its back queue, and then we'll be
1747          * able to process them after we restore SDEIER (as soon as we restore
1748          * it, we'll get an interrupt if SDEIIR still has something to process
1749          * due to its back queue). */
1750         if (!HAS_PCH_NOP(dev)) {
1751                 sde_ier = I915_READ(SDEIER);
1752                 I915_WRITE(SDEIER, 0);
1753                 POSTING_READ(SDEIER);
1754         }
1755
1756         gt_iir = I915_READ(GTIIR);
1757         if (gt_iir) {
1758                 if (INTEL_INFO(dev)->gen >= 6)
1759                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1760                 else
1761                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1762                 I915_WRITE(GTIIR, gt_iir);
1763                 ret = IRQ_HANDLED;
1764         }
1765
1766         de_iir = I915_READ(DEIIR);
1767         if (de_iir) {
1768                 if (INTEL_INFO(dev)->gen >= 7)
1769                         ivb_display_irq_handler(dev, de_iir);
1770                 else
1771                         ilk_display_irq_handler(dev, de_iir);
1772                 I915_WRITE(DEIIR, de_iir);
1773                 ret = IRQ_HANDLED;
1774         }
1775
1776         if (INTEL_INFO(dev)->gen >= 6) {
1777                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1778                 if (pm_iir) {
1779                         gen6_rps_irq_handler(dev_priv, pm_iir);
1780                         I915_WRITE(GEN6_PMIIR, pm_iir);
1781                         ret = IRQ_HANDLED;
1782                 }
1783         }
1784
1785         I915_WRITE(DEIER, de_ier);
1786         POSTING_READ(DEIER);
1787         if (!HAS_PCH_NOP(dev)) {
1788                 I915_WRITE(SDEIER, sde_ier);
1789                 POSTING_READ(SDEIER);
1790         }
1791
1792         return ret;
1793 }
1794
1795 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1796 {
1797         struct drm_device *dev = arg;
1798         struct drm_i915_private *dev_priv = dev->dev_private;
1799         u32 master_ctl;
1800         irqreturn_t ret = IRQ_NONE;
1801         uint32_t tmp = 0;
1802         enum pipe pipe;
1803
1804         atomic_inc(&dev_priv->irq_received);
1805
1806         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1807         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1808         if (!master_ctl)
1809                 return IRQ_NONE;
1810
1811         I915_WRITE(GEN8_MASTER_IRQ, 0);
1812         POSTING_READ(GEN8_MASTER_IRQ);
1813
1814         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1815
1816         if (master_ctl & GEN8_DE_MISC_IRQ) {
1817                 tmp = I915_READ(GEN8_DE_MISC_IIR);
1818                 if (tmp & GEN8_DE_MISC_GSE)
1819                         intel_opregion_asle_intr(dev);
1820                 else if (tmp)
1821                         DRM_ERROR("Unexpected DE Misc interrupt\n");
1822                 else
1823                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1824
1825                 if (tmp) {
1826                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1827                         ret = IRQ_HANDLED;
1828                 }
1829         }
1830
1831         if (master_ctl & GEN8_DE_PORT_IRQ) {
1832                 tmp = I915_READ(GEN8_DE_PORT_IIR);
1833                 if (tmp & GEN8_AUX_CHANNEL_A)
1834                         dp_aux_irq_handler(dev);
1835                 else if (tmp)
1836                         DRM_ERROR("Unexpected DE Port interrupt\n");
1837                 else
1838                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1839
1840                 if (tmp) {
1841                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1842                         ret = IRQ_HANDLED;
1843                 }
1844         }
1845
1846         for_each_pipe(pipe) {
1847                 uint32_t pipe_iir;
1848
1849                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1850                         continue;
1851
1852                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1853                 if (pipe_iir & GEN8_PIPE_VBLANK)
1854                         drm_handle_vblank(dev, pipe);
1855
1856                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1857                         intel_prepare_page_flip(dev, pipe);
1858                         intel_finish_page_flip_plane(dev, pipe);
1859                 }
1860
1861                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1862                         hsw_pipe_crc_irq_handler(dev, pipe);
1863
1864                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1865                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1866                                                                   false))
1867                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1868                                                  pipe_name(pipe));
1869                 }
1870
1871                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1872                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1873                                   pipe_name(pipe),
1874                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1875                 }
1876
1877                 if (pipe_iir) {
1878                         ret = IRQ_HANDLED;
1879                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1880                 } else
1881                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1882         }
1883
1884         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1885                 /*
1886                  * FIXME(BDW): Assume for now that the new interrupt handling
1887                  * scheme also closed the SDE interrupt handling race we've seen
1888                  * on older pch-split platforms. But this needs testing.
1889                  */
1890                 u32 pch_iir = I915_READ(SDEIIR);
1891
1892                 cpt_irq_handler(dev, pch_iir);
1893
1894                 if (pch_iir) {
1895                         I915_WRITE(SDEIIR, pch_iir);
1896                         ret = IRQ_HANDLED;
1897                 }
1898         }
1899
1900         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1901         POSTING_READ(GEN8_MASTER_IRQ);
1902
1903         return ret;
1904 }
1905
1906 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1907                                bool reset_completed)
1908 {
1909         struct intel_ring_buffer *ring;
1910         int i;
1911
1912         /*
1913          * Notify all waiters for GPU completion events that reset state has
1914          * been changed, and that they need to restart their wait after
1915          * checking for potential errors (and bail out to drop locks if there is
1916          * a gpu reset pending so that i915_error_work_func can acquire them).
1917          */
1918
1919         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1920         for_each_ring(ring, dev_priv, i)
1921                 wake_up_all(&ring->irq_queue);
1922
1923         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1924         wake_up_all(&dev_priv->pending_flip_queue);
1925
1926         /*
1927          * Signal tasks blocked in i915_gem_wait_for_error that the pending
1928          * reset state is cleared.
1929          */
1930         if (reset_completed)
1931                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1932 }
1933
1934 /**
1935  * i915_error_work_func - do process context error handling work
1936  * @work: work struct
1937  *
1938  * Fire an error uevent so userspace can see that a hang or error
1939  * was detected.
1940  */
1941 static void i915_error_work_func(struct work_struct *work)
1942 {
1943         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1944                                                     work);
1945         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1946                                                     gpu_error);
1947         struct drm_device *dev = dev_priv->dev;
1948         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1949         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1950         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1951         int ret;
1952
1953         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
1954
1955         /*
1956          * Note that there's only one work item which does gpu resets, so we
1957          * need not worry about concurrent gpu resets potentially incrementing
1958          * error->reset_counter twice. We only need to take care of another
1959          * racing irq/hangcheck declaring the gpu dead for a second time. A
1960          * quick check for that is good enough: schedule_work ensures the
1961          * correct ordering between hang detection and this work item, and since
1962          * the reset in-progress bit is only ever set by code outside of this
1963          * work we don't need to worry about any other races.
1964          */
1965         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1966                 DRM_DEBUG_DRIVER("resetting chip\n");
1967                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
1968                                    reset_event);
1969
1970                 /*
1971                  * All state reset _must_ be completed before we update the
1972                  * reset counter, for otherwise waiters might miss the reset
1973                  * pending state and not properly drop locks, resulting in
1974                  * deadlocks with the reset work.
1975                  */
1976                 ret = i915_reset(dev);
1977
1978                 intel_display_handle_reset(dev);
1979
1980                 if (ret == 0) {
1981                         /*
1982                          * After all the gem state is reset, increment the reset
1983                          * counter and wake up everyone waiting for the reset to
1984                          * complete.
1985                          *
1986                          * Since unlock operations are a one-sided barrier only,
1987                          * we need to insert a barrier here to order any seqno
1988                          * updates before
1989                          * the counter increment.
1990                          */
1991                         smp_mb__before_atomic_inc();
1992                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1993
1994                         kobject_uevent_env(&dev->primary->kdev->kobj,
1995                                            KOBJ_CHANGE, reset_done_event);
1996                 } else {
1997                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
1998                 }
1999
2000                 /*
2001                  * Note: The wake_up also serves as a memory barrier so that
2002                  * waiters see the update value of the reset counter atomic_t.
2003                  */
2004                 i915_error_wake_up(dev_priv, true);
2005         }
2006 }
2007
2008 static void i915_report_and_clear_eir(struct drm_device *dev)
2009 {
2010         struct drm_i915_private *dev_priv = dev->dev_private;
2011         uint32_t instdone[I915_NUM_INSTDONE_REG];
2012         u32 eir = I915_READ(EIR);
2013         int pipe, i;
2014
2015         if (!eir)
2016                 return;
2017
2018         pr_err("render error detected, EIR: 0x%08x\n", eir);
2019
2020         i915_get_extra_instdone(dev, instdone);
2021
2022         if (IS_G4X(dev)) {
2023                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2024                         u32 ipeir = I915_READ(IPEIR_I965);
2025
2026                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2027                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2028                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2029                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2030                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2031                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2032                         I915_WRITE(IPEIR_I965, ipeir);
2033                         POSTING_READ(IPEIR_I965);
2034                 }
2035                 if (eir & GM45_ERROR_PAGE_TABLE) {
2036                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2037                         pr_err("page table error\n");
2038                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2039                         I915_WRITE(PGTBL_ER, pgtbl_err);
2040                         POSTING_READ(PGTBL_ER);
2041                 }
2042         }
2043
2044         if (!IS_GEN2(dev)) {
2045                 if (eir & I915_ERROR_PAGE_TABLE) {
2046                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2047                         pr_err("page table error\n");
2048                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2049                         I915_WRITE(PGTBL_ER, pgtbl_err);
2050                         POSTING_READ(PGTBL_ER);
2051                 }
2052         }
2053
2054         if (eir & I915_ERROR_MEMORY_REFRESH) {
2055                 pr_err("memory refresh error:\n");
2056                 for_each_pipe(pipe)
2057                         pr_err("pipe %c stat: 0x%08x\n",
2058                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2059                 /* pipestat has already been acked */
2060         }
2061         if (eir & I915_ERROR_INSTRUCTION) {
2062                 pr_err("instruction error\n");
2063                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2064                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2065                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2066                 if (INTEL_INFO(dev)->gen < 4) {
2067                         u32 ipeir = I915_READ(IPEIR);
2068
2069                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2070                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2071                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2072                         I915_WRITE(IPEIR, ipeir);
2073                         POSTING_READ(IPEIR);
2074                 } else {
2075                         u32 ipeir = I915_READ(IPEIR_I965);
2076
2077                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2078                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2079                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2080                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2081                         I915_WRITE(IPEIR_I965, ipeir);
2082                         POSTING_READ(IPEIR_I965);
2083                 }
2084         }
2085
2086         I915_WRITE(EIR, eir);
2087         POSTING_READ(EIR);
2088         eir = I915_READ(EIR);
2089         if (eir) {
2090                 /*
2091                  * some errors might have become stuck,
2092                  * mask them.
2093                  */
2094                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2095                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2096                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2097         }
2098 }
2099
2100 /**
2101  * i915_handle_error - handle an error interrupt
2102  * @dev: drm device
2103  *
2104  * Do some basic checking of regsiter state at error interrupt time and
2105  * dump it to the syslog.  Also call i915_capture_error_state() to make
2106  * sure we get a record and make it available in debugfs.  Fire a uevent
2107  * so userspace knows something bad happened (should trigger collection
2108  * of a ring dump etc.).
2109  */
2110 void i915_handle_error(struct drm_device *dev, bool wedged)
2111 {
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113
2114         i915_capture_error_state(dev);
2115         i915_report_and_clear_eir(dev);
2116
2117         if (wedged) {
2118                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2119                                 &dev_priv->gpu_error.reset_counter);
2120
2121                 /*
2122                  * Wakeup waiting processes so that the reset work function
2123                  * i915_error_work_func doesn't deadlock trying to grab various
2124                  * locks. By bumping the reset counter first, the woken
2125                  * processes will see a reset in progress and back off,
2126                  * releasing their locks and then wait for the reset completion.
2127                  * We must do this for _all_ gpu waiters that might hold locks
2128                  * that the reset work needs to acquire.
2129                  *
2130                  * Note: The wake_up serves as the required memory barrier to
2131                  * ensure that the waiters see the updated value of the reset
2132                  * counter atomic_t.
2133                  */
2134                 i915_error_wake_up(dev_priv, false);
2135         }
2136
2137         /*
2138          * Our reset work can grab modeset locks (since it needs to reset the
2139          * state of outstanding pagelips). Hence it must not be run on our own
2140          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2141          * code will deadlock.
2142          */
2143         schedule_work(&dev_priv->gpu_error.work);
2144 }
2145
2146 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2147 {
2148         drm_i915_private_t *dev_priv = dev->dev_private;
2149         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151         struct drm_i915_gem_object *obj;
2152         struct intel_unpin_work *work;
2153         unsigned long flags;
2154         bool stall_detected;
2155
2156         /* Ignore early vblank irqs */
2157         if (intel_crtc == NULL)
2158                 return;
2159
2160         spin_lock_irqsave(&dev->event_lock, flags);
2161         work = intel_crtc->unpin_work;
2162
2163         if (work == NULL ||
2164             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2165             !work->enable_stall_check) {
2166                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2167                 spin_unlock_irqrestore(&dev->event_lock, flags);
2168                 return;
2169         }
2170
2171         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2172         obj = work->pending_flip_obj;
2173         if (INTEL_INFO(dev)->gen >= 4) {
2174                 int dspsurf = DSPSURF(intel_crtc->plane);
2175                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2176                                         i915_gem_obj_ggtt_offset(obj);
2177         } else {
2178                 int dspaddr = DSPADDR(intel_crtc->plane);
2179                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2180                                                         crtc->y * crtc->fb->pitches[0] +
2181                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2182         }
2183
2184         spin_unlock_irqrestore(&dev->event_lock, flags);
2185
2186         if (stall_detected) {
2187                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2188                 intel_prepare_page_flip(dev, intel_crtc->plane);
2189         }
2190 }
2191
2192 /* Called from drm generic code, passed 'crtc' which
2193  * we use as a pipe index
2194  */
2195 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2196 {
2197         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2198         unsigned long irqflags;
2199
2200         if (!i915_pipe_enabled(dev, pipe))
2201                 return -EINVAL;
2202
2203         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2204         if (INTEL_INFO(dev)->gen >= 4)
2205                 i915_enable_pipestat(dev_priv, pipe,
2206                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
2207         else
2208                 i915_enable_pipestat(dev_priv, pipe,
2209                                      PIPE_VBLANK_INTERRUPT_ENABLE);
2210
2211         /* maintain vblank delivery even in deep C-states */
2212         if (dev_priv->info->gen == 3)
2213                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2214         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2215
2216         return 0;
2217 }
2218
2219 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2220 {
2221         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2222         unsigned long irqflags;
2223         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2224                                                      DE_PIPE_VBLANK(pipe);
2225
2226         if (!i915_pipe_enabled(dev, pipe))
2227                 return -EINVAL;
2228
2229         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2230         ironlake_enable_display_irq(dev_priv, bit);
2231         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2232
2233         return 0;
2234 }
2235
2236 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2237 {
2238         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2239         unsigned long irqflags;
2240         u32 imr;
2241
2242         if (!i915_pipe_enabled(dev, pipe))
2243                 return -EINVAL;
2244
2245         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2246         imr = I915_READ(VLV_IMR);
2247         if (pipe == PIPE_A)
2248                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2249         else
2250                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2251         I915_WRITE(VLV_IMR, imr);
2252         i915_enable_pipestat(dev_priv, pipe,
2253                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
2254         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2255
2256         return 0;
2257 }
2258
2259 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2260 {
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         unsigned long irqflags;
2263
2264         if (!i915_pipe_enabled(dev, pipe))
2265                 return -EINVAL;
2266
2267         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2268         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2269         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2270         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2271         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2272         return 0;
2273 }
2274
2275 /* Called from drm generic code, passed 'crtc' which
2276  * we use as a pipe index
2277  */
2278 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2279 {
2280         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2281         unsigned long irqflags;
2282
2283         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2284         if (dev_priv->info->gen == 3)
2285                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2286
2287         i915_disable_pipestat(dev_priv, pipe,
2288                               PIPE_VBLANK_INTERRUPT_ENABLE |
2289                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2290         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2291 }
2292
2293 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2294 {
2295         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2296         unsigned long irqflags;
2297         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2298                                                      DE_PIPE_VBLANK(pipe);
2299
2300         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2301         ironlake_disable_display_irq(dev_priv, bit);
2302         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2303 }
2304
2305 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2306 {
2307         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2308         unsigned long irqflags;
2309         u32 imr;
2310
2311         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2312         i915_disable_pipestat(dev_priv, pipe,
2313                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2314         imr = I915_READ(VLV_IMR);
2315         if (pipe == PIPE_A)
2316                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2317         else
2318                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2319         I915_WRITE(VLV_IMR, imr);
2320         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2321 }
2322
2323 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2324 {
2325         struct drm_i915_private *dev_priv = dev->dev_private;
2326         unsigned long irqflags;
2327
2328         if (!i915_pipe_enabled(dev, pipe))
2329                 return;
2330
2331         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2332         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2333         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2334         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2335         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2336 }
2337
2338 static u32
2339 ring_last_seqno(struct intel_ring_buffer *ring)
2340 {
2341         return list_entry(ring->request_list.prev,
2342                           struct drm_i915_gem_request, list)->seqno;
2343 }
2344
2345 static bool
2346 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2347 {
2348         return (list_empty(&ring->request_list) ||
2349                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2350 }
2351
2352 static struct intel_ring_buffer *
2353 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2354 {
2355         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2356         u32 cmd, ipehr, acthd, acthd_min;
2357
2358         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2359         if ((ipehr & ~(0x3 << 16)) !=
2360             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2361                 return NULL;
2362
2363         /* ACTHD is likely pointing to the dword after the actual command,
2364          * so scan backwards until we find the MBOX.
2365          */
2366         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2367         acthd_min = max((int)acthd - 3 * 4, 0);
2368         do {
2369                 cmd = ioread32(ring->virtual_start + acthd);
2370                 if (cmd == ipehr)
2371                         break;
2372
2373                 acthd -= 4;
2374                 if (acthd < acthd_min)
2375                         return NULL;
2376         } while (1);
2377
2378         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2379         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2380 }
2381
2382 static int semaphore_passed(struct intel_ring_buffer *ring)
2383 {
2384         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2385         struct intel_ring_buffer *signaller;
2386         u32 seqno, ctl;
2387
2388         ring->hangcheck.deadlock = true;
2389
2390         signaller = semaphore_waits_for(ring, &seqno);
2391         if (signaller == NULL || signaller->hangcheck.deadlock)
2392                 return -1;
2393
2394         /* cursory check for an unkickable deadlock */
2395         ctl = I915_READ_CTL(signaller);
2396         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2397                 return -1;
2398
2399         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2400 }
2401
2402 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2403 {
2404         struct intel_ring_buffer *ring;
2405         int i;
2406
2407         for_each_ring(ring, dev_priv, i)
2408                 ring->hangcheck.deadlock = false;
2409 }
2410
2411 static enum intel_ring_hangcheck_action
2412 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2413 {
2414         struct drm_device *dev = ring->dev;
2415         struct drm_i915_private *dev_priv = dev->dev_private;
2416         u32 tmp;
2417
2418         if (ring->hangcheck.acthd != acthd)
2419                 return HANGCHECK_ACTIVE;
2420
2421         if (IS_GEN2(dev))
2422                 return HANGCHECK_HUNG;
2423
2424         /* Is the chip hanging on a WAIT_FOR_EVENT?
2425          * If so we can simply poke the RB_WAIT bit
2426          * and break the hang. This should work on
2427          * all but the second generation chipsets.
2428          */
2429         tmp = I915_READ_CTL(ring);
2430         if (tmp & RING_WAIT) {
2431                 DRM_ERROR("Kicking stuck wait on %s\n",
2432                           ring->name);
2433                 i915_handle_error(dev, false);
2434                 I915_WRITE_CTL(ring, tmp);
2435                 return HANGCHECK_KICK;
2436         }
2437
2438         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2439                 switch (semaphore_passed(ring)) {
2440                 default:
2441                         return HANGCHECK_HUNG;
2442                 case 1:
2443                         DRM_ERROR("Kicking stuck semaphore on %s\n",
2444                                   ring->name);
2445                         i915_handle_error(dev, false);
2446                         I915_WRITE_CTL(ring, tmp);
2447                         return HANGCHECK_KICK;
2448                 case 0:
2449                         return HANGCHECK_WAIT;
2450                 }
2451         }
2452
2453         return HANGCHECK_HUNG;
2454 }
2455
2456 /**
2457  * This is called when the chip hasn't reported back with completed
2458  * batchbuffers in a long time. We keep track per ring seqno progress and
2459  * if there are no progress, hangcheck score for that ring is increased.
2460  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2461  * we kick the ring. If we see no progress on three subsequent calls
2462  * we assume chip is wedged and try to fix it by resetting the chip.
2463  */
2464 static void i915_hangcheck_elapsed(unsigned long data)
2465 {
2466         struct drm_device *dev = (struct drm_device *)data;
2467         drm_i915_private_t *dev_priv = dev->dev_private;
2468         struct intel_ring_buffer *ring;
2469         int i;
2470         int busy_count = 0, rings_hung = 0;
2471         bool stuck[I915_NUM_RINGS] = { 0 };
2472 #define BUSY 1
2473 #define KICK 5
2474 #define HUNG 20
2475 #define FIRE 30
2476
2477         if (!i915_enable_hangcheck)
2478                 return;
2479
2480         for_each_ring(ring, dev_priv, i) {
2481                 u32 seqno, acthd;
2482                 bool busy = true;
2483
2484                 semaphore_clear_deadlocks(dev_priv);
2485
2486                 seqno = ring->get_seqno(ring, false);
2487                 acthd = intel_ring_get_active_head(ring);
2488
2489                 if (ring->hangcheck.seqno == seqno) {
2490                         if (ring_idle(ring, seqno)) {
2491                                 ring->hangcheck.action = HANGCHECK_IDLE;
2492
2493                                 if (waitqueue_active(&ring->irq_queue)) {
2494                                         /* Issue a wake-up to catch stuck h/w. */
2495                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2496                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2497                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2498                                                                   ring->name);
2499                                                 else
2500                                                         DRM_INFO("Fake missed irq on %s\n",
2501                                                                  ring->name);
2502                                                 wake_up_all(&ring->irq_queue);
2503                                         }
2504                                         /* Safeguard against driver failure */
2505                                         ring->hangcheck.score += BUSY;
2506                                 } else
2507                                         busy = false;
2508                         } else {
2509                                 /* We always increment the hangcheck score
2510                                  * if the ring is busy and still processing
2511                                  * the same request, so that no single request
2512                                  * can run indefinitely (such as a chain of
2513                                  * batches). The only time we do not increment
2514                                  * the hangcheck score on this ring, if this
2515                                  * ring is in a legitimate wait for another
2516                                  * ring. In that case the waiting ring is a
2517                                  * victim and we want to be sure we catch the
2518                                  * right culprit. Then every time we do kick
2519                                  * the ring, add a small increment to the
2520                                  * score so that we can catch a batch that is
2521                                  * being repeatedly kicked and so responsible
2522                                  * for stalling the machine.
2523                                  */
2524                                 ring->hangcheck.action = ring_stuck(ring,
2525                                                                     acthd);
2526
2527                                 switch (ring->hangcheck.action) {
2528                                 case HANGCHECK_IDLE:
2529                                 case HANGCHECK_WAIT:
2530                                         break;
2531                                 case HANGCHECK_ACTIVE:
2532                                         ring->hangcheck.score += BUSY;
2533                                         break;
2534                                 case HANGCHECK_KICK:
2535                                         ring->hangcheck.score += KICK;
2536                                         break;
2537                                 case HANGCHECK_HUNG:
2538                                         ring->hangcheck.score += HUNG;
2539                                         stuck[i] = true;
2540                                         break;
2541                                 }
2542                         }
2543                 } else {
2544                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2545
2546                         /* Gradually reduce the count so that we catch DoS
2547                          * attempts across multiple batches.
2548                          */
2549                         if (ring->hangcheck.score > 0)
2550                                 ring->hangcheck.score--;
2551                 }
2552
2553                 ring->hangcheck.seqno = seqno;
2554                 ring->hangcheck.acthd = acthd;
2555                 busy_count += busy;
2556         }
2557
2558         for_each_ring(ring, dev_priv, i) {
2559                 if (ring->hangcheck.score > FIRE) {
2560                         DRM_INFO("%s on %s\n",
2561                                  stuck[i] ? "stuck" : "no progress",
2562                                  ring->name);
2563                         rings_hung++;
2564                 }
2565         }
2566
2567         if (rings_hung)
2568                 return i915_handle_error(dev, true);
2569
2570         if (busy_count)
2571                 /* Reset timer case chip hangs without another request
2572                  * being added */
2573                 i915_queue_hangcheck(dev);
2574 }
2575
2576 void i915_queue_hangcheck(struct drm_device *dev)
2577 {
2578         struct drm_i915_private *dev_priv = dev->dev_private;
2579         if (!i915_enable_hangcheck)
2580                 return;
2581
2582         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2583                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2584 }
2585
2586 static void ibx_irq_preinstall(struct drm_device *dev)
2587 {
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589
2590         if (HAS_PCH_NOP(dev))
2591                 return;
2592
2593         /* south display irq */
2594         I915_WRITE(SDEIMR, 0xffffffff);
2595         /*
2596          * SDEIER is also touched by the interrupt handler to work around missed
2597          * PCH interrupts. Hence we can't update it after the interrupt handler
2598          * is enabled - instead we unconditionally enable all PCH interrupt
2599          * sources here, but then only unmask them as needed with SDEIMR.
2600          */
2601         I915_WRITE(SDEIER, 0xffffffff);
2602         POSTING_READ(SDEIER);
2603 }
2604
2605 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2606 {
2607         struct drm_i915_private *dev_priv = dev->dev_private;
2608
2609         /* and GT */
2610         I915_WRITE(GTIMR, 0xffffffff);
2611         I915_WRITE(GTIER, 0x0);
2612         POSTING_READ(GTIER);
2613
2614         if (INTEL_INFO(dev)->gen >= 6) {
2615                 /* and PM */
2616                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2617                 I915_WRITE(GEN6_PMIER, 0x0);
2618                 POSTING_READ(GEN6_PMIER);
2619         }
2620 }
2621
2622 /* drm_dma.h hooks
2623 */
2624 static void ironlake_irq_preinstall(struct drm_device *dev)
2625 {
2626         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2627
2628         atomic_set(&dev_priv->irq_received, 0);
2629
2630         I915_WRITE(HWSTAM, 0xeffe);
2631
2632         I915_WRITE(DEIMR, 0xffffffff);
2633         I915_WRITE(DEIER, 0x0);
2634         POSTING_READ(DEIER);
2635
2636         gen5_gt_irq_preinstall(dev);
2637
2638         ibx_irq_preinstall(dev);
2639 }
2640
2641 static void valleyview_irq_preinstall(struct drm_device *dev)
2642 {
2643         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2644         int pipe;
2645
2646         atomic_set(&dev_priv->irq_received, 0);
2647
2648         /* VLV magic */
2649         I915_WRITE(VLV_IMR, 0);
2650         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2651         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2652         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2653
2654         /* and GT */
2655         I915_WRITE(GTIIR, I915_READ(GTIIR));
2656         I915_WRITE(GTIIR, I915_READ(GTIIR));
2657
2658         gen5_gt_irq_preinstall(dev);
2659
2660         I915_WRITE(DPINVGTT, 0xff);
2661
2662         I915_WRITE(PORT_HOTPLUG_EN, 0);
2663         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2664         for_each_pipe(pipe)
2665                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2666         I915_WRITE(VLV_IIR, 0xffffffff);
2667         I915_WRITE(VLV_IMR, 0xffffffff);
2668         I915_WRITE(VLV_IER, 0x0);
2669         POSTING_READ(VLV_IER);
2670 }
2671
2672 static void gen8_irq_preinstall(struct drm_device *dev)
2673 {
2674         struct drm_i915_private *dev_priv = dev->dev_private;
2675         int pipe;
2676
2677         atomic_set(&dev_priv->irq_received, 0);
2678
2679         I915_WRITE(GEN8_MASTER_IRQ, 0);
2680         POSTING_READ(GEN8_MASTER_IRQ);
2681
2682         /* IIR can theoretically queue up two events. Be paranoid */
2683 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2684                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2685                 POSTING_READ(GEN8_##type##_IMR(which)); \
2686                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2687                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2688                 POSTING_READ(GEN8_##type##_IIR(which)); \
2689                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2690         } while (0)
2691
2692 #define GEN8_IRQ_INIT(type) do { \
2693                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2694                 POSTING_READ(GEN8_##type##_IMR); \
2695                 I915_WRITE(GEN8_##type##_IER, 0); \
2696                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2697                 POSTING_READ(GEN8_##type##_IIR); \
2698                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2699         } while (0)
2700
2701         GEN8_IRQ_INIT_NDX(GT, 0);
2702         GEN8_IRQ_INIT_NDX(GT, 1);
2703         GEN8_IRQ_INIT_NDX(GT, 2);
2704         GEN8_IRQ_INIT_NDX(GT, 3);
2705
2706         for_each_pipe(pipe) {
2707                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2708         }
2709
2710         GEN8_IRQ_INIT(DE_PORT);
2711         GEN8_IRQ_INIT(DE_MISC);
2712         GEN8_IRQ_INIT(PCU);
2713 #undef GEN8_IRQ_INIT
2714 #undef GEN8_IRQ_INIT_NDX
2715
2716         POSTING_READ(GEN8_PCU_IIR);
2717 }
2718
2719 static void ibx_hpd_irq_setup(struct drm_device *dev)
2720 {
2721         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2722         struct drm_mode_config *mode_config = &dev->mode_config;
2723         struct intel_encoder *intel_encoder;
2724         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2725
2726         if (HAS_PCH_IBX(dev)) {
2727                 hotplug_irqs = SDE_HOTPLUG_MASK;
2728                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2729                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2730                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2731         } else {
2732                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2733                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2734                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2735                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2736         }
2737
2738         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2739
2740         /*
2741          * Enable digital hotplug on the PCH, and configure the DP short pulse
2742          * duration to 2ms (which is the minimum in the Display Port spec)
2743          *
2744          * This register is the same on all known PCH chips.
2745          */
2746         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2747         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2748         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2749         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2750         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2751         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2752 }
2753
2754 static void ibx_irq_postinstall(struct drm_device *dev)
2755 {
2756         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2757         u32 mask;
2758
2759         if (HAS_PCH_NOP(dev))
2760                 return;
2761
2762         if (HAS_PCH_IBX(dev)) {
2763                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2764                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2765         } else {
2766                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2767
2768                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2769         }
2770
2771         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2772         I915_WRITE(SDEIMR, ~mask);
2773 }
2774
2775 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2776 {
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778         u32 pm_irqs, gt_irqs;
2779
2780         pm_irqs = gt_irqs = 0;
2781
2782         dev_priv->gt_irq_mask = ~0;
2783         if (HAS_L3_DPF(dev)) {
2784                 /* L3 parity interrupt is always unmasked. */
2785                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2786                 gt_irqs |= GT_PARITY_ERROR(dev);
2787         }
2788
2789         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2790         if (IS_GEN5(dev)) {
2791                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2792                            ILK_BSD_USER_INTERRUPT;
2793         } else {
2794                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2795         }
2796
2797         I915_WRITE(GTIIR, I915_READ(GTIIR));
2798         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2799         I915_WRITE(GTIER, gt_irqs);
2800         POSTING_READ(GTIER);
2801
2802         if (INTEL_INFO(dev)->gen >= 6) {
2803                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2804
2805                 if (HAS_VEBOX(dev))
2806                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2807
2808                 dev_priv->pm_irq_mask = 0xffffffff;
2809                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2810                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2811                 I915_WRITE(GEN6_PMIER, pm_irqs);
2812                 POSTING_READ(GEN6_PMIER);
2813         }
2814 }
2815
2816 static int ironlake_irq_postinstall(struct drm_device *dev)
2817 {
2818         unsigned long irqflags;
2819         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2820         u32 display_mask, extra_mask;
2821
2822         if (INTEL_INFO(dev)->gen >= 7) {
2823                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2824                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2825                                 DE_PLANEB_FLIP_DONE_IVB |
2826                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2827                                 DE_ERR_INT_IVB);
2828                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2829                               DE_PIPEA_VBLANK_IVB);
2830
2831                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2832         } else {
2833                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2834                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2835                                 DE_AUX_CHANNEL_A |
2836                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2837                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2838                                 DE_POISON);
2839                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2840         }
2841
2842         dev_priv->irq_mask = ~display_mask;
2843
2844         /* should always can generate irq */
2845         I915_WRITE(DEIIR, I915_READ(DEIIR));
2846         I915_WRITE(DEIMR, dev_priv->irq_mask);
2847         I915_WRITE(DEIER, display_mask | extra_mask);
2848         POSTING_READ(DEIER);
2849
2850         gen5_gt_irq_postinstall(dev);
2851
2852         ibx_irq_postinstall(dev);
2853
2854         if (IS_IRONLAKE_M(dev)) {
2855                 /* Enable PCU event interrupts
2856                  *
2857                  * spinlocking not required here for correctness since interrupt
2858                  * setup is guaranteed to run in single-threaded context. But we
2859                  * need it to make the assert_spin_locked happy. */
2860                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2861                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2862                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2863         }
2864
2865         return 0;
2866 }
2867
2868 static int valleyview_irq_postinstall(struct drm_device *dev)
2869 {
2870         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2871         u32 enable_mask;
2872         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2873                 PIPE_CRC_DONE_ENABLE;
2874         unsigned long irqflags;
2875
2876         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2877         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2878                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2879                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2880                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2881
2882         /*
2883          *Leave vblank interrupts masked initially.  enable/disable will
2884          * toggle them based on usage.
2885          */
2886         dev_priv->irq_mask = (~enable_mask) |
2887                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2888                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2889
2890         I915_WRITE(PORT_HOTPLUG_EN, 0);
2891         POSTING_READ(PORT_HOTPLUG_EN);
2892
2893         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2894         I915_WRITE(VLV_IER, enable_mask);
2895         I915_WRITE(VLV_IIR, 0xffffffff);
2896         I915_WRITE(PIPESTAT(0), 0xffff);
2897         I915_WRITE(PIPESTAT(1), 0xffff);
2898         POSTING_READ(VLV_IER);
2899
2900         /* Interrupt setup is already guaranteed to be single-threaded, this is
2901          * just to make the assert_spin_locked check happy. */
2902         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2903         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2904         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2905         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2906         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2907
2908         I915_WRITE(VLV_IIR, 0xffffffff);
2909         I915_WRITE(VLV_IIR, 0xffffffff);
2910
2911         gen5_gt_irq_postinstall(dev);
2912
2913         /* ack & enable invalid PTE error interrupts */
2914 #if 0 /* FIXME: add support to irq handler for checking these bits */
2915         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2916         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2917 #endif
2918
2919         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2920
2921         return 0;
2922 }
2923
2924 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2925 {
2926         int i;
2927
2928         /* These are interrupts we'll toggle with the ring mask register */
2929         uint32_t gt_interrupts[] = {
2930                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2931                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2932                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2933                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2934                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2935                 0,
2936                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2937                 };
2938
2939         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2940                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2941                 if (tmp)
2942                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2943                                   i, tmp);
2944                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2945                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2946         }
2947         POSTING_READ(GEN8_GT_IER(0));
2948 }
2949
2950 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2951 {
2952         struct drm_device *dev = dev_priv->dev;
2953         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2954                 GEN8_PIPE_CDCLK_CRC_DONE |
2955                 GEN8_PIPE_FIFO_UNDERRUN |
2956                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2957         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
2958         int pipe;
2959         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2960         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2961         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
2962
2963         for_each_pipe(pipe) {
2964                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2965                 if (tmp)
2966                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2967                                   pipe, tmp);
2968                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2969                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
2970         }
2971         POSTING_READ(GEN8_DE_PIPE_ISR(0));
2972
2973         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
2974         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
2975         POSTING_READ(GEN8_DE_PORT_IER);
2976 }
2977
2978 static int gen8_irq_postinstall(struct drm_device *dev)
2979 {
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981
2982         gen8_gt_irq_postinstall(dev_priv);
2983         gen8_de_irq_postinstall(dev_priv);
2984
2985         ibx_irq_postinstall(dev);
2986
2987         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
2988         POSTING_READ(GEN8_MASTER_IRQ);
2989
2990         return 0;
2991 }
2992
2993 static void gen8_irq_uninstall(struct drm_device *dev)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         int pipe;
2997
2998         if (!dev_priv)
2999                 return;
3000
3001         atomic_set(&dev_priv->irq_received, 0);
3002
3003         I915_WRITE(GEN8_MASTER_IRQ, 0);
3004
3005 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3006                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3007                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3008                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3009         } while (0)
3010
3011 #define GEN8_IRQ_FINI(type) do { \
3012                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3013                 I915_WRITE(GEN8_##type##_IER, 0); \
3014                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3015         } while (0)
3016
3017         GEN8_IRQ_FINI_NDX(GT, 0);
3018         GEN8_IRQ_FINI_NDX(GT, 1);
3019         GEN8_IRQ_FINI_NDX(GT, 2);
3020         GEN8_IRQ_FINI_NDX(GT, 3);
3021
3022         for_each_pipe(pipe) {
3023                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3024         }
3025
3026         GEN8_IRQ_FINI(DE_PORT);
3027         GEN8_IRQ_FINI(DE_MISC);
3028         GEN8_IRQ_FINI(PCU);
3029 #undef GEN8_IRQ_FINI
3030 #undef GEN8_IRQ_FINI_NDX
3031
3032         POSTING_READ(GEN8_PCU_IIR);
3033 }
3034
3035 static void valleyview_irq_uninstall(struct drm_device *dev)
3036 {
3037         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3038         int pipe;
3039
3040         if (!dev_priv)
3041                 return;
3042
3043         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3044
3045         for_each_pipe(pipe)
3046                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3047
3048         I915_WRITE(HWSTAM, 0xffffffff);
3049         I915_WRITE(PORT_HOTPLUG_EN, 0);
3050         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3051         for_each_pipe(pipe)
3052                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3053         I915_WRITE(VLV_IIR, 0xffffffff);
3054         I915_WRITE(VLV_IMR, 0xffffffff);
3055         I915_WRITE(VLV_IER, 0x0);
3056         POSTING_READ(VLV_IER);
3057 }
3058
3059 static void ironlake_irq_uninstall(struct drm_device *dev)
3060 {
3061         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3062
3063         if (!dev_priv)
3064                 return;
3065
3066         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3067
3068         I915_WRITE(HWSTAM, 0xffffffff);
3069
3070         I915_WRITE(DEIMR, 0xffffffff);
3071         I915_WRITE(DEIER, 0x0);
3072         I915_WRITE(DEIIR, I915_READ(DEIIR));
3073         if (IS_GEN7(dev))
3074                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3075
3076         I915_WRITE(GTIMR, 0xffffffff);
3077         I915_WRITE(GTIER, 0x0);
3078         I915_WRITE(GTIIR, I915_READ(GTIIR));
3079
3080         if (HAS_PCH_NOP(dev))
3081                 return;
3082
3083         I915_WRITE(SDEIMR, 0xffffffff);
3084         I915_WRITE(SDEIER, 0x0);
3085         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3086         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3087                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3088 }
3089
3090 static void i8xx_irq_preinstall(struct drm_device * dev)
3091 {
3092         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3093         int pipe;
3094
3095         atomic_set(&dev_priv->irq_received, 0);
3096
3097         for_each_pipe(pipe)
3098                 I915_WRITE(PIPESTAT(pipe), 0);
3099         I915_WRITE16(IMR, 0xffff);
3100         I915_WRITE16(IER, 0x0);
3101         POSTING_READ16(IER);
3102 }
3103
3104 static int i8xx_irq_postinstall(struct drm_device *dev)
3105 {
3106         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3107         unsigned long irqflags;
3108
3109         I915_WRITE16(EMR,
3110                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3111
3112         /* Unmask the interrupts that we always want on. */
3113         dev_priv->irq_mask =
3114                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3115                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3116                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3117                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3118                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3119         I915_WRITE16(IMR, dev_priv->irq_mask);
3120
3121         I915_WRITE16(IER,
3122                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3123                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3124                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3125                      I915_USER_INTERRUPT);
3126         POSTING_READ16(IER);
3127
3128         /* Interrupt setup is already guaranteed to be single-threaded, this is
3129          * just to make the assert_spin_locked check happy. */
3130         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3131         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3132         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3133         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3134
3135         return 0;
3136 }
3137
3138 /*
3139  * Returns true when a page flip has completed.
3140  */
3141 static bool i8xx_handle_vblank(struct drm_device *dev,
3142                                int plane, int pipe, u32 iir)
3143 {
3144         drm_i915_private_t *dev_priv = dev->dev_private;
3145         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3146
3147         if (!drm_handle_vblank(dev, pipe))
3148                 return false;
3149
3150         if ((iir & flip_pending) == 0)
3151                 return false;
3152
3153         intel_prepare_page_flip(dev, plane);
3154
3155         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3156          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3157          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3158          * the flip is completed (no longer pending). Since this doesn't raise
3159          * an interrupt per se, we watch for the change at vblank.
3160          */
3161         if (I915_READ16(ISR) & flip_pending)
3162                 return false;
3163
3164         intel_finish_page_flip(dev, pipe);
3165
3166         return true;
3167 }
3168
3169 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3170 {
3171         struct drm_device *dev = (struct drm_device *) arg;
3172         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3173         u16 iir, new_iir;
3174         u32 pipe_stats[2];
3175         unsigned long irqflags;
3176         int pipe;
3177         u16 flip_mask =
3178                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3179                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3180
3181         atomic_inc(&dev_priv->irq_received);
3182
3183         iir = I915_READ16(IIR);
3184         if (iir == 0)
3185                 return IRQ_NONE;
3186
3187         while (iir & ~flip_mask) {
3188                 /* Can't rely on pipestat interrupt bit in iir as it might
3189                  * have been cleared after the pipestat interrupt was received.
3190                  * It doesn't set the bit in iir again, but it still produces
3191                  * interrupts (for non-MSI).
3192                  */
3193                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3194                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3195                         i915_handle_error(dev, false);
3196
3197                 for_each_pipe(pipe) {
3198                         int reg = PIPESTAT(pipe);
3199                         pipe_stats[pipe] = I915_READ(reg);
3200
3201                         /*
3202                          * Clear the PIPE*STAT regs before the IIR
3203                          */
3204                         if (pipe_stats[pipe] & 0x8000ffff) {
3205                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3206                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3207                                                          pipe_name(pipe));
3208                                 I915_WRITE(reg, pipe_stats[pipe]);
3209                         }
3210                 }
3211                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3212
3213                 I915_WRITE16(IIR, iir & ~flip_mask);
3214                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3215
3216                 i915_update_dri1_breadcrumb(dev);
3217
3218                 if (iir & I915_USER_INTERRUPT)
3219                         notify_ring(dev, &dev_priv->ring[RCS]);
3220
3221                 for_each_pipe(pipe) {
3222                         int plane = pipe;
3223                         if (IS_MOBILE(dev))
3224                                 plane = !plane;
3225
3226                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3227                             i8xx_handle_vblank(dev, plane, pipe, iir))
3228                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3229
3230                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3231                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3232                 }
3233
3234                 iir = new_iir;
3235         }
3236
3237         return IRQ_HANDLED;
3238 }
3239
3240 static void i8xx_irq_uninstall(struct drm_device * dev)
3241 {
3242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3243         int pipe;
3244
3245         for_each_pipe(pipe) {
3246                 /* Clear enable bits; then clear status bits */
3247                 I915_WRITE(PIPESTAT(pipe), 0);
3248                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3249         }
3250         I915_WRITE16(IMR, 0xffff);
3251         I915_WRITE16(IER, 0x0);
3252         I915_WRITE16(IIR, I915_READ16(IIR));
3253 }
3254
3255 static void i915_irq_preinstall(struct drm_device * dev)
3256 {
3257         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3258         int pipe;
3259
3260         atomic_set(&dev_priv->irq_received, 0);
3261
3262         if (I915_HAS_HOTPLUG(dev)) {
3263                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3264                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3265         }
3266
3267         I915_WRITE16(HWSTAM, 0xeffe);
3268         for_each_pipe(pipe)
3269                 I915_WRITE(PIPESTAT(pipe), 0);
3270         I915_WRITE(IMR, 0xffffffff);
3271         I915_WRITE(IER, 0x0);
3272         POSTING_READ(IER);
3273 }
3274
3275 static int i915_irq_postinstall(struct drm_device *dev)
3276 {
3277         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3278         u32 enable_mask;
3279         unsigned long irqflags;
3280
3281         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3282
3283         /* Unmask the interrupts that we always want on. */
3284         dev_priv->irq_mask =
3285                 ~(I915_ASLE_INTERRUPT |
3286                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3287                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3288                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3289                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3290                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3291
3292         enable_mask =
3293                 I915_ASLE_INTERRUPT |
3294                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3295                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3296                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3297                 I915_USER_INTERRUPT;
3298
3299         if (I915_HAS_HOTPLUG(dev)) {
3300                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3301                 POSTING_READ(PORT_HOTPLUG_EN);
3302
3303                 /* Enable in IER... */
3304                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3305                 /* and unmask in IMR */
3306                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3307         }
3308
3309         I915_WRITE(IMR, dev_priv->irq_mask);
3310         I915_WRITE(IER, enable_mask);
3311         POSTING_READ(IER);
3312
3313         i915_enable_asle_pipestat(dev);
3314
3315         /* Interrupt setup is already guaranteed to be single-threaded, this is
3316          * just to make the assert_spin_locked check happy. */
3317         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3318         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3319         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3320         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3321
3322         return 0;
3323 }
3324
3325 /*
3326  * Returns true when a page flip has completed.
3327  */
3328 static bool i915_handle_vblank(struct drm_device *dev,
3329                                int plane, int pipe, u32 iir)
3330 {
3331         drm_i915_private_t *dev_priv = dev->dev_private;
3332         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3333
3334         if (!drm_handle_vblank(dev, pipe))
3335                 return false;
3336
3337         if ((iir & flip_pending) == 0)
3338                 return false;
3339
3340         intel_prepare_page_flip(dev, plane);
3341
3342         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3343          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3344          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3345          * the flip is completed (no longer pending). Since this doesn't raise
3346          * an interrupt per se, we watch for the change at vblank.
3347          */
3348         if (I915_READ(ISR) & flip_pending)
3349                 return false;
3350
3351         intel_finish_page_flip(dev, pipe);
3352
3353         return true;
3354 }
3355
3356 static irqreturn_t i915_irq_handler(int irq, void *arg)
3357 {
3358         struct drm_device *dev = (struct drm_device *) arg;
3359         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3360         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3361         unsigned long irqflags;
3362         u32 flip_mask =
3363                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3364                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3365         int pipe, ret = IRQ_NONE;
3366
3367         atomic_inc(&dev_priv->irq_received);
3368
3369         iir = I915_READ(IIR);
3370         do {
3371                 bool irq_received = (iir & ~flip_mask) != 0;
3372                 bool blc_event = false;
3373
3374                 /* Can't rely on pipestat interrupt bit in iir as it might
3375                  * have been cleared after the pipestat interrupt was received.
3376                  * It doesn't set the bit in iir again, but it still produces
3377                  * interrupts (for non-MSI).
3378                  */
3379                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3380                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3381                         i915_handle_error(dev, false);
3382
3383                 for_each_pipe(pipe) {
3384                         int reg = PIPESTAT(pipe);
3385                         pipe_stats[pipe] = I915_READ(reg);
3386
3387                         /* Clear the PIPE*STAT regs before the IIR */
3388                         if (pipe_stats[pipe] & 0x8000ffff) {
3389                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3390                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3391                                                          pipe_name(pipe));
3392                                 I915_WRITE(reg, pipe_stats[pipe]);
3393                                 irq_received = true;
3394                         }
3395                 }
3396                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3397
3398                 if (!irq_received)
3399                         break;
3400
3401                 /* Consume port.  Then clear IIR or we'll miss events */
3402                 if ((I915_HAS_HOTPLUG(dev)) &&
3403                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3404                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3405                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3406
3407                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3408                                   hotplug_status);
3409
3410                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3411
3412                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3413                         POSTING_READ(PORT_HOTPLUG_STAT);
3414                 }
3415
3416                 I915_WRITE(IIR, iir & ~flip_mask);
3417                 new_iir = I915_READ(IIR); /* Flush posted writes */
3418
3419                 if (iir & I915_USER_INTERRUPT)
3420                         notify_ring(dev, &dev_priv->ring[RCS]);
3421
3422                 for_each_pipe(pipe) {
3423                         int plane = pipe;
3424                         if (IS_MOBILE(dev))
3425                                 plane = !plane;
3426
3427                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3428                             i915_handle_vblank(dev, plane, pipe, iir))
3429                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3430
3431                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3432                                 blc_event = true;
3433
3434                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3435                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3436                 }
3437
3438                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3439                         intel_opregion_asle_intr(dev);
3440
3441                 /* With MSI, interrupts are only generated when iir
3442                  * transitions from zero to nonzero.  If another bit got
3443                  * set while we were handling the existing iir bits, then
3444                  * we would never get another interrupt.
3445                  *
3446                  * This is fine on non-MSI as well, as if we hit this path
3447                  * we avoid exiting the interrupt handler only to generate
3448                  * another one.
3449                  *
3450                  * Note that for MSI this could cause a stray interrupt report
3451                  * if an interrupt landed in the time between writing IIR and
3452                  * the posting read.  This should be rare enough to never
3453                  * trigger the 99% of 100,000 interrupts test for disabling
3454                  * stray interrupts.
3455                  */
3456                 ret = IRQ_HANDLED;
3457                 iir = new_iir;
3458         } while (iir & ~flip_mask);
3459
3460         i915_update_dri1_breadcrumb(dev);
3461
3462         return ret;
3463 }
3464
3465 static void i915_irq_uninstall(struct drm_device * dev)
3466 {
3467         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3468         int pipe;
3469
3470         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3471
3472         if (I915_HAS_HOTPLUG(dev)) {
3473                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3474                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3475         }
3476
3477         I915_WRITE16(HWSTAM, 0xffff);
3478         for_each_pipe(pipe) {
3479                 /* Clear enable bits; then clear status bits */
3480                 I915_WRITE(PIPESTAT(pipe), 0);
3481                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3482         }
3483         I915_WRITE(IMR, 0xffffffff);
3484         I915_WRITE(IER, 0x0);
3485
3486         I915_WRITE(IIR, I915_READ(IIR));
3487 }
3488
3489 static void i965_irq_preinstall(struct drm_device * dev)
3490 {
3491         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3492         int pipe;
3493
3494         atomic_set(&dev_priv->irq_received, 0);
3495
3496         I915_WRITE(PORT_HOTPLUG_EN, 0);
3497         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3498
3499         I915_WRITE(HWSTAM, 0xeffe);
3500         for_each_pipe(pipe)
3501                 I915_WRITE(PIPESTAT(pipe), 0);
3502         I915_WRITE(IMR, 0xffffffff);
3503         I915_WRITE(IER, 0x0);
3504         POSTING_READ(IER);
3505 }
3506
3507 static int i965_irq_postinstall(struct drm_device *dev)
3508 {
3509         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3510         u32 enable_mask;
3511         u32 error_mask;
3512         unsigned long irqflags;
3513
3514         /* Unmask the interrupts that we always want on. */
3515         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3516                                I915_DISPLAY_PORT_INTERRUPT |
3517                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3518                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3519                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3520                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3521                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3522
3523         enable_mask = ~dev_priv->irq_mask;
3524         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3525                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3526         enable_mask |= I915_USER_INTERRUPT;
3527
3528         if (IS_G4X(dev))
3529                 enable_mask |= I915_BSD_USER_INTERRUPT;
3530
3531         /* Interrupt setup is already guaranteed to be single-threaded, this is
3532          * just to make the assert_spin_locked check happy. */
3533         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3534         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3535         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3536         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3537         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3538
3539         /*
3540          * Enable some error detection, note the instruction error mask
3541          * bit is reserved, so we leave it masked.
3542          */
3543         if (IS_G4X(dev)) {
3544                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3545                                GM45_ERROR_MEM_PRIV |
3546                                GM45_ERROR_CP_PRIV |
3547                                I915_ERROR_MEMORY_REFRESH);
3548         } else {
3549                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3550                                I915_ERROR_MEMORY_REFRESH);
3551         }
3552         I915_WRITE(EMR, error_mask);
3553
3554         I915_WRITE(IMR, dev_priv->irq_mask);
3555         I915_WRITE(IER, enable_mask);
3556         POSTING_READ(IER);
3557
3558         I915_WRITE(PORT_HOTPLUG_EN, 0);
3559         POSTING_READ(PORT_HOTPLUG_EN);
3560
3561         i915_enable_asle_pipestat(dev);
3562
3563         return 0;
3564 }
3565
3566 static void i915_hpd_irq_setup(struct drm_device *dev)
3567 {
3568         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3569         struct drm_mode_config *mode_config = &dev->mode_config;
3570         struct intel_encoder *intel_encoder;
3571         u32 hotplug_en;
3572
3573         assert_spin_locked(&dev_priv->irq_lock);
3574
3575         if (I915_HAS_HOTPLUG(dev)) {
3576                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3577                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3578                 /* Note HDMI and DP share hotplug bits */
3579                 /* enable bits are the same for all generations */
3580                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3581                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3582                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3583                 /* Programming the CRT detection parameters tends
3584                    to generate a spurious hotplug event about three
3585                    seconds later.  So just do it once.
3586                 */
3587                 if (IS_G4X(dev))
3588                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3589                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3590                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3591
3592                 /* Ignore TV since it's buggy */
3593                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3594         }
3595 }
3596
3597 static irqreturn_t i965_irq_handler(int irq, void *arg)
3598 {
3599         struct drm_device *dev = (struct drm_device *) arg;
3600         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3601         u32 iir, new_iir;
3602         u32 pipe_stats[I915_MAX_PIPES];
3603         unsigned long irqflags;
3604         int irq_received;
3605         int ret = IRQ_NONE, pipe;
3606         u32 flip_mask =
3607                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3608                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3609
3610         atomic_inc(&dev_priv->irq_received);
3611
3612         iir = I915_READ(IIR);
3613
3614         for (;;) {
3615                 bool blc_event = false;
3616
3617                 irq_received = (iir & ~flip_mask) != 0;
3618
3619                 /* Can't rely on pipestat interrupt bit in iir as it might
3620                  * have been cleared after the pipestat interrupt was received.
3621                  * It doesn't set the bit in iir again, but it still produces
3622                  * interrupts (for non-MSI).
3623                  */
3624                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3625                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3626                         i915_handle_error(dev, false);
3627
3628                 for_each_pipe(pipe) {
3629                         int reg = PIPESTAT(pipe);
3630                         pipe_stats[pipe] = I915_READ(reg);
3631
3632                         /*
3633                          * Clear the PIPE*STAT regs before the IIR
3634                          */
3635                         if (pipe_stats[pipe] & 0x8000ffff) {
3636                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3637                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3638                                                          pipe_name(pipe));
3639                                 I915_WRITE(reg, pipe_stats[pipe]);
3640                                 irq_received = 1;
3641                         }
3642                 }
3643                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3644
3645                 if (!irq_received)
3646                         break;
3647
3648                 ret = IRQ_HANDLED;
3649
3650                 /* Consume port.  Then clear IIR or we'll miss events */
3651                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3652                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3653                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3654                                                                   HOTPLUG_INT_STATUS_G4X :
3655                                                                   HOTPLUG_INT_STATUS_I915);
3656
3657                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3658                                   hotplug_status);
3659
3660                         intel_hpd_irq_handler(dev, hotplug_trigger,
3661                                               IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3662
3663                         if (IS_G4X(dev) &&
3664                             (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3665                                 dp_aux_irq_handler(dev);
3666
3667                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3668                         I915_READ(PORT_HOTPLUG_STAT);
3669                 }
3670
3671                 I915_WRITE(IIR, iir & ~flip_mask);
3672                 new_iir = I915_READ(IIR); /* Flush posted writes */
3673
3674                 if (iir & I915_USER_INTERRUPT)
3675                         notify_ring(dev, &dev_priv->ring[RCS]);
3676                 if (iir & I915_BSD_USER_INTERRUPT)
3677                         notify_ring(dev, &dev_priv->ring[VCS]);
3678
3679                 for_each_pipe(pipe) {
3680                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3681                             i915_handle_vblank(dev, pipe, pipe, iir))
3682                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3683
3684                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3685                                 blc_event = true;
3686
3687                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3688                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3689                 }
3690
3691
3692                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3693                         intel_opregion_asle_intr(dev);
3694
3695                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3696                         gmbus_irq_handler(dev);
3697
3698                 /* With MSI, interrupts are only generated when iir
3699                  * transitions from zero to nonzero.  If another bit got
3700                  * set while we were handling the existing iir bits, then
3701                  * we would never get another interrupt.
3702                  *
3703                  * This is fine on non-MSI as well, as if we hit this path
3704                  * we avoid exiting the interrupt handler only to generate
3705                  * another one.
3706                  *
3707                  * Note that for MSI this could cause a stray interrupt report
3708                  * if an interrupt landed in the time between writing IIR and
3709                  * the posting read.  This should be rare enough to never
3710                  * trigger the 99% of 100,000 interrupts test for disabling
3711                  * stray interrupts.
3712                  */
3713                 iir = new_iir;
3714         }
3715
3716         i915_update_dri1_breadcrumb(dev);
3717
3718         return ret;
3719 }
3720
3721 static void i965_irq_uninstall(struct drm_device * dev)
3722 {
3723         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3724         int pipe;
3725
3726         if (!dev_priv)
3727                 return;
3728
3729         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3730
3731         I915_WRITE(PORT_HOTPLUG_EN, 0);
3732         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3733
3734         I915_WRITE(HWSTAM, 0xffffffff);
3735         for_each_pipe(pipe)
3736                 I915_WRITE(PIPESTAT(pipe), 0);
3737         I915_WRITE(IMR, 0xffffffff);
3738         I915_WRITE(IER, 0x0);
3739
3740         for_each_pipe(pipe)
3741                 I915_WRITE(PIPESTAT(pipe),
3742                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3743         I915_WRITE(IIR, I915_READ(IIR));
3744 }
3745
3746 static void i915_reenable_hotplug_timer_func(unsigned long data)
3747 {
3748         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3749         struct drm_device *dev = dev_priv->dev;
3750         struct drm_mode_config *mode_config = &dev->mode_config;
3751         unsigned long irqflags;
3752         int i;
3753
3754         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3755         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3756                 struct drm_connector *connector;
3757
3758                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3759                         continue;
3760
3761                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3762
3763                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3764                         struct intel_connector *intel_connector = to_intel_connector(connector);
3765
3766                         if (intel_connector->encoder->hpd_pin == i) {
3767                                 if (connector->polled != intel_connector->polled)
3768                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3769                                                          drm_get_connector_name(connector));
3770                                 connector->polled = intel_connector->polled;
3771                                 if (!connector->polled)
3772                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3773                         }
3774                 }
3775         }
3776         if (dev_priv->display.hpd_irq_setup)
3777                 dev_priv->display.hpd_irq_setup(dev);
3778         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3779 }
3780
3781 void intel_irq_init(struct drm_device *dev)
3782 {
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784
3785         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3786         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3787         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3788         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3789
3790         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3791                     i915_hangcheck_elapsed,
3792                     (unsigned long) dev);
3793         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3794                     (unsigned long) dev_priv);
3795
3796         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3797
3798         if (IS_GEN2(dev)) {
3799                 dev->max_vblank_count = 0;
3800                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3801         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3802                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3803                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3804         } else {
3805                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3806                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3807         }
3808
3809         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3810                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3811                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3812         }
3813
3814         if (IS_VALLEYVIEW(dev)) {
3815                 dev->driver->irq_handler = valleyview_irq_handler;
3816                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3817                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3818                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3819                 dev->driver->enable_vblank = valleyview_enable_vblank;
3820                 dev->driver->disable_vblank = valleyview_disable_vblank;
3821                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3822         } else if (IS_GEN8(dev)) {
3823                 dev->driver->irq_handler = gen8_irq_handler;
3824                 dev->driver->irq_preinstall = gen8_irq_preinstall;
3825                 dev->driver->irq_postinstall = gen8_irq_postinstall;
3826                 dev->driver->irq_uninstall = gen8_irq_uninstall;
3827                 dev->driver->enable_vblank = gen8_enable_vblank;
3828                 dev->driver->disable_vblank = gen8_disable_vblank;
3829                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3830         } else if (HAS_PCH_SPLIT(dev)) {
3831                 dev->driver->irq_handler = ironlake_irq_handler;
3832                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3833                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3834                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3835                 dev->driver->enable_vblank = ironlake_enable_vblank;
3836                 dev->driver->disable_vblank = ironlake_disable_vblank;
3837                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3838         } else {
3839                 if (INTEL_INFO(dev)->gen == 2) {
3840                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3841                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3842                         dev->driver->irq_handler = i8xx_irq_handler;
3843                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3844                 } else if (INTEL_INFO(dev)->gen == 3) {
3845                         dev->driver->irq_preinstall = i915_irq_preinstall;
3846                         dev->driver->irq_postinstall = i915_irq_postinstall;
3847                         dev->driver->irq_uninstall = i915_irq_uninstall;
3848                         dev->driver->irq_handler = i915_irq_handler;
3849                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3850                 } else {
3851                         dev->driver->irq_preinstall = i965_irq_preinstall;
3852                         dev->driver->irq_postinstall = i965_irq_postinstall;
3853                         dev->driver->irq_uninstall = i965_irq_uninstall;
3854                         dev->driver->irq_handler = i965_irq_handler;
3855                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3856                 }
3857                 dev->driver->enable_vblank = i915_enable_vblank;
3858                 dev->driver->disable_vblank = i915_disable_vblank;
3859         }
3860 }
3861
3862 void intel_hpd_init(struct drm_device *dev)
3863 {
3864         struct drm_i915_private *dev_priv = dev->dev_private;
3865         struct drm_mode_config *mode_config = &dev->mode_config;
3866         struct drm_connector *connector;
3867         unsigned long irqflags;
3868         int i;
3869
3870         for (i = 1; i < HPD_NUM_PINS; i++) {
3871                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3872                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3873         }
3874         list_for_each_entry(connector, &mode_config->connector_list, head) {
3875                 struct intel_connector *intel_connector = to_intel_connector(connector);
3876                 connector->polled = intel_connector->polled;
3877                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3878                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3879         }
3880
3881         /* Interrupt setup is already guaranteed to be single-threaded, this is
3882          * just to make the assert_spin_locked checks happy. */
3883         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3884         if (dev_priv->display.hpd_irq_setup)
3885                 dev_priv->display.hpd_irq_setup(dev);
3886         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3887 }
3888
3889 /* Disable interrupts so we can allow Package C8+. */
3890 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3891 {
3892         struct drm_i915_private *dev_priv = dev->dev_private;
3893         unsigned long irqflags;
3894
3895         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3896
3897         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3898         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3899         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3900         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3901         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3902
3903         ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3904         ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3905         ilk_disable_gt_irq(dev_priv, 0xffffffff);
3906         snb_disable_pm_irq(dev_priv, 0xffffffff);
3907
3908         dev_priv->pc8.irqs_disabled = true;
3909
3910         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3911 }
3912
3913 /* Restore interrupts so we can recover from Package C8+. */
3914 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3915 {
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         unsigned long irqflags;
3918         uint32_t val, expected;
3919
3920         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3921
3922         val = I915_READ(DEIMR);
3923         expected = ~DE_PCH_EVENT_IVB;
3924         WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3925
3926         val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3927         expected = ~SDE_HOTPLUG_MASK_CPT;
3928         WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3929              val, expected);
3930
3931         val = I915_READ(GTIMR);
3932         expected = 0xffffffff;
3933         WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3934
3935         val = I915_READ(GEN6_PMIMR);
3936         expected = 0xffffffff;
3937         WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3938              expected);
3939
3940         dev_priv->pc8.irqs_disabled = false;
3941
3942         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3943         ibx_enable_display_interrupt(dev_priv,
3944                                      ~dev_priv->pc8.regsave.sdeimr &
3945                                      ~SDE_HOTPLUG_MASK_CPT);
3946         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3947         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3948         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3949
3950         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3951 }