drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 void
  89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92                 u32 reg = PIPESTAT(pipe);
  93
  94                 dev_priv->pipestat[pipe] |= mask;
  95                 /* Enable the interrupt, clear any pending status */
  96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97                 POSTING_READ(reg);
  98         }
  99 }
 100
 101 void
 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = PIPESTAT(pipe);
 106
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109                 POSTING_READ(reg);
 110         }
 111 }
 112
 113 /**
 114  * intel_enable_asle - enable ASLE interrupt for OpRegion
 115  */
 116 void intel_enable_asle(struct drm_device *dev)
 117 {
 118         drm_i915_private_t *dev_priv = dev->dev_private;
 119         unsigned long irqflags;
 120
 121         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 125         else {
 126                 i915_enable_pipestat(dev_priv, 1,
 127                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 128                 if (INTEL_INFO(dev)->gen >= 4)
 129                         i915_enable_pipestat(dev_priv, 0,
 130                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 131         }
 132
 133         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 134 }
 135
 136 /**
 137  * i915_pipe_enabled - check if a pipe is enabled
 138  * @dev: DRM device
 139  * @pipe: pipe to check
 140  *
 141  * Reading certain registers when the pipe is disabled can hang the chip.
 142  * Use this routine to make sure the PLL is running and the pipe is active
 143  * before reading such registers if unsure.
 144  */
 145 static int
 146 i915_pipe_enabled(struct drm_device *dev, int pipe)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 150 }
 151
 152 /* Called from drm generic code, passed a 'crtc', which
 153  * we use as a pipe index
 154  */
 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156 {
 157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158         unsigned long high_frame;
 159         unsigned long low_frame;
 160         u32 high1, high2, low;
 161
 162         if (!i915_pipe_enabled(dev, pipe)) {
 163                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 164                                 "pipe %c\n", pipe_name(pipe));
 165                 return 0;
 166         }
 167
 168         high_frame = PIPEFRAME(pipe);
 169         low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171         /*
 172          * High & low register fields aren't synchronized, so make sure
 173          * we get a low value that's stable across two reads of the high
 174          * register.
 175          */
 176         do {
 177                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180         } while (high1 != high2);
 181
 182         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 183         low >>= PIPE_FRAME_LOW_SHIFT;
 184         return (high1 << 8) | low;
 185 }
 186
 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         int reg = PIPE_FRMCOUNT_GM45(pipe);
 191
 192         if (!i915_pipe_enabled(dev, pipe)) {
 193                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 194                                  "pipe %c\n", pipe_name(pipe));
 195                 return 0;
 196         }
 197
 198         return I915_READ(reg);
 199 }
 200
 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 202                              int *vpos, int *hpos)
 203 {
 204         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205         u32 vbl = 0, position = 0;
 206         int vbl_start, vbl_end, htotal, vtotal;
 207         bool in_vbl = true;
 208         int ret = 0;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 212                                  "pipe %c\n", pipe_name(pipe));
 213                 return 0;
 214         }
 215
 216         /* Get vtotal. */
 217         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 218
 219         if (INTEL_INFO(dev)->gen >= 4) {
 220                 /* No obvious pixelcount register. Only query vertical
 221                  * scanout position from Display scan line register.
 222                  */
 223                 position = I915_READ(PIPEDSL(pipe));
 224
 225                 /* Decode into vertical scanout position. Don't have
 226                  * horizontal scanout position.
 227                  */
 228                 *vpos = position & 0x1fff;
 229                 *hpos = 0;
 230         } else {
 231                 /* Have access to pixelcount since start of frame.
 232                  * We can split this into vertical and horizontal
 233                  * scanout position.
 234                  */
 235                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 236
 237                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 238                 *vpos = position / htotal;
 239                 *hpos = position - (*vpos * htotal);
 240         }
 241
 242         /* Query vblank area. */
 243         vbl = I915_READ(VBLANK(pipe));
 244
 245         /* Test position against vblank region. */
 246         vbl_start = vbl & 0x1fff;
 247         vbl_end = (vbl >> 16) & 0x1fff;
 248
 249         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 250                 in_vbl = false;
 251
 252         /* Inside "upper part" of vblank area? Apply corrective offset: */
 253         if (in_vbl && (*vpos >= vbl_start))
 254                 *vpos = *vpos - vtotal;
 255
 256         /* Readouts valid? */
 257         if (vbl > 0)
 258                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 259
 260         /* In vblank? */
 261         if (in_vbl)
 262                 ret |= DRM_SCANOUTPOS_INVBL;
 263
 264         return ret;
 265 }
 266
 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 268                               int *max_error,
 269                               struct timeval *vblank_time,
 270                               unsigned flags)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         struct drm_crtc *crtc;
 274
 275         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 276                 DRM_ERROR("Invalid crtc %d\n", pipe);
 277                 return -EINVAL;
 278         }
 279
 280         /* Get drm_crtc to timestamp: */
 281         crtc = intel_get_crtc_for_pipe(dev, pipe);
 282         if (crtc == NULL) {
 283                 DRM_ERROR("Invalid crtc %d\n", pipe);
 284                 return -EINVAL;
 285         }
 286
 287         if (!crtc->enabled) {
 288                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 289                 return -EBUSY;
 290         }
 291
 292         /* Helper routine in DRM core does all the work: */
 293         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 294                                                      vblank_time, flags,
 295                                                      crtc);
 296 }
 297
 298 /*
 299  * Handle hotplug events outside the interrupt handler proper.
 300  */
 301 static void i915_hotplug_work_func(struct work_struct *work)
 302 {
 303         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 304                                                     hotplug_work);
 305         struct drm_device *dev = dev_priv->dev;
 306         struct drm_mode_config *mode_config = &dev->mode_config;
 307         struct intel_encoder *encoder;
 308
 309         mutex_lock(&mode_config->mutex);
 310         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 311
 312         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 313                 if (encoder->hot_plug)
 314                         encoder->hot_plug(encoder);
 315
 316         mutex_unlock(&mode_config->mutex);
 317
 318         /* Just fire off a uevent and let userspace tell us what to do */
 319         drm_helper_hpd_irq_event(dev);
 320 }
 321
 322 static void i915_handle_rps_change(struct drm_device *dev)
 323 {
 324         drm_i915_private_t *dev_priv = dev->dev_private;
 325         u32 busy_up, busy_down, max_avg, min_avg;
 326         u8 new_delay = dev_priv->cur_delay;
 327
 328         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 329         busy_up = I915_READ(RCPREVBSYTUPAVG);
 330         busy_down = I915_READ(RCPREVBSYTDNAVG);
 331         max_avg = I915_READ(RCBMAXAVG);
 332         min_avg = I915_READ(RCBMINAVG);
 333
 334         /* Handle RCS change request from hw */
 335         if (busy_up > max_avg) {
 336                 if (dev_priv->cur_delay != dev_priv->max_delay)
 337                         new_delay = dev_priv->cur_delay - 1;
 338                 if (new_delay < dev_priv->max_delay)
 339                         new_delay = dev_priv->max_delay;
 340         } else if (busy_down < min_avg) {
 341                 if (dev_priv->cur_delay != dev_priv->min_delay)
 342                         new_delay = dev_priv->cur_delay + 1;
 343                 if (new_delay > dev_priv->min_delay)
 344                         new_delay = dev_priv->min_delay;
 345         }
 346
 347         if (ironlake_set_drps(dev, new_delay))
 348                 dev_priv->cur_delay = new_delay;
 349
 350         return;
 351 }
 352
 353 static void notify_ring(struct drm_device *dev,
 354                         struct intel_ring_buffer *ring)
 355 {
 356         struct drm_i915_private *dev_priv = dev->dev_private;
 357         u32 seqno;
 358
 359         if (ring->obj == NULL)
 360                 return;
 361
 362         seqno = ring->get_seqno(ring);
 363         trace_i915_gem_request_complete(ring, seqno);
 364
 365         ring->irq_seqno = seqno;
 366         wake_up_all(&ring->irq_queue);
 367         if (i915_enable_hangcheck) {
 368                 dev_priv->hangcheck_count = 0;
 369                 mod_timer(&dev_priv->hangcheck_timer,
 370                           jiffies +
 371                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 372         }
 373 }
 374
 375 static void gen6_pm_rps_work(struct work_struct *work)
 376 {
 377         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 378                                                     rps_work);
 379         u8 new_delay = dev_priv->cur_delay;
 380         u32 pm_iir, pm_imr;
 381
 382         spin_lock_irq(&dev_priv->rps_lock);
 383         pm_iir = dev_priv->pm_iir;
 384         dev_priv->pm_iir = 0;
 385         pm_imr = I915_READ(GEN6_PMIMR);
 386         I915_WRITE(GEN6_PMIMR, 0);
 387         spin_unlock_irq(&dev_priv->rps_lock);
 388
 389         if (!pm_iir)
 390                 return;
 391
 392         mutex_lock(&dev_priv->dev->struct_mutex);
 393         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 394                 if (dev_priv->cur_delay != dev_priv->max_delay)
 395                         new_delay = dev_priv->cur_delay + 1;
 396                 if (new_delay > dev_priv->max_delay)
 397                         new_delay = dev_priv->max_delay;
 398         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 399                 gen6_gt_force_wake_get(dev_priv);
 400                 if (dev_priv->cur_delay != dev_priv->min_delay)
 401                         new_delay = dev_priv->cur_delay - 1;
 402                 if (new_delay < dev_priv->min_delay) {
 403                         new_delay = dev_priv->min_delay;
 404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 406                                    ((new_delay << 16) & 0x3f0000));
 407                 } else {
 408                         /* Make sure we continue to get down interrupts
 409                          * until we hit the minimum frequency */
 410                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 411                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 412                 }
 413                 gen6_gt_force_wake_put(dev_priv);
 414         }
 415
 416         gen6_set_rps(dev_priv->dev, new_delay);
 417         dev_priv->cur_delay = new_delay;
 418
 419         /*
 420          * rps_lock not held here because clearing is non-destructive. There is
 421          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 422          * by holding struct_mutex for the duration of the write.
 423          */
 424         mutex_unlock(&dev_priv->dev->struct_mutex);
 425 }
 426
 427 static void pch_irq_handler(struct drm_device *dev)
 428 {
 429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 430         u32 pch_iir;
 431         int pipe;
 432
 433         pch_iir = I915_READ(SDEIIR);
 434
 435         if (pch_iir & SDE_AUDIO_POWER_MASK)
 436                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 437                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 438                                  SDE_AUDIO_POWER_SHIFT);
 439
 440         if (pch_iir & SDE_GMBUS)
 441                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 442
 443         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 444                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 445
 446         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 447                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 448
 449         if (pch_iir & SDE_POISON)
 450                 DRM_ERROR("PCH poison interrupt\n");
 451
 452         if (pch_iir & SDE_FDI_MASK)
 453                 for_each_pipe(pipe)
 454                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 455                                          pipe_name(pipe),
 456                                          I915_READ(FDI_RX_IIR(pipe)));
 457
 458         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 459                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 460
 461         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 462                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 463
 464         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 465                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 466         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 467                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 468 }
 469
 470 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 471 {
 472         struct drm_device *dev = (struct drm_device *) arg;
 473         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 474         int ret = IRQ_NONE;
 475         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 476         struct drm_i915_master_private *master_priv;
 477
 478         atomic_inc(&dev_priv->irq_received);
 479
 480         /* disable master interrupt before clearing iir  */
 481         de_ier = I915_READ(DEIER);
 482         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 483         POSTING_READ(DEIER);
 484
 485         de_iir = I915_READ(DEIIR);
 486         gt_iir = I915_READ(GTIIR);
 487         pch_iir = I915_READ(SDEIIR);
 488         pm_iir = I915_READ(GEN6_PMIIR);
 489
 490         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 491                 goto done;
 492
 493         ret = IRQ_HANDLED;
 494
 495         if (dev->primary->master) {
 496                 master_priv = dev->primary->master->driver_priv;
 497                 if (master_priv->sarea_priv)
 498                         master_priv->sarea_priv->last_dispatch =
 499                                 READ_BREADCRUMB(dev_priv);
 500         }
 501
 502         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 503                 notify_ring(dev, &dev_priv->ring[RCS]);
 504         if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 505                 notify_ring(dev, &dev_priv->ring[VCS]);
 506         if (gt_iir & GT_BLT_USER_INTERRUPT)
 507                 notify_ring(dev, &dev_priv->ring[BCS]);
 508
 509         if (de_iir & DE_GSE_IVB)
 510                 intel_opregion_gse_intr(dev);
 511
 512         if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 513                 intel_prepare_page_flip(dev, 0);
 514                 intel_finish_page_flip_plane(dev, 0);
 515         }
 516
 517         if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 518                 intel_prepare_page_flip(dev, 1);
 519                 intel_finish_page_flip_plane(dev, 1);
 520         }
 521
 522         if (de_iir & DE_PIPEA_VBLANK_IVB)
 523                 drm_handle_vblank(dev, 0);
 524
 525         if (de_iir & DE_PIPEB_VBLANK_IVB)
 526                 drm_handle_vblank(dev, 1);
 527
 528         /* check event from PCH */
 529         if (de_iir & DE_PCH_EVENT_IVB) {
 530                 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 531                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 532                 pch_irq_handler(dev);
 533         }
 534
 535         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 536                 unsigned long flags;
 537                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 538                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 539                 dev_priv->pm_iir |= pm_iir;
 540                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 541                 POSTING_READ(GEN6_PMIMR);
 542                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 543                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 544         }
 545
 546         /* should clear PCH hotplug event before clear CPU irq */
 547         I915_WRITE(SDEIIR, pch_iir);
 548         I915_WRITE(GTIIR, gt_iir);
 549         I915_WRITE(DEIIR, de_iir);
 550         I915_WRITE(GEN6_PMIIR, pm_iir);
 551
 552 done:
 553         I915_WRITE(DEIER, de_ier);
 554         POSTING_READ(DEIER);
 555
 556         return ret;
 557 }
 558
 559 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 560 {
 561         struct drm_device *dev = (struct drm_device *) arg;
 562         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 563         int ret = IRQ_NONE;
 564         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 565         u32 hotplug_mask;
 566         struct drm_i915_master_private *master_priv;
 567         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 568
 569         atomic_inc(&dev_priv->irq_received);
 570
 571         if (IS_GEN6(dev))
 572                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 573
 574         /* disable master interrupt before clearing iir  */
 575         de_ier = I915_READ(DEIER);
 576         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 577         POSTING_READ(DEIER);
 578
 579         de_iir = I915_READ(DEIIR);
 580         gt_iir = I915_READ(GTIIR);
 581         pch_iir = I915_READ(SDEIIR);
 582         pm_iir = I915_READ(GEN6_PMIIR);
 583
 584         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 585             (!IS_GEN6(dev) || pm_iir == 0))
 586                 goto done;
 587
 588         if (HAS_PCH_CPT(dev))
 589                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 590         else
 591                 hotplug_mask = SDE_HOTPLUG_MASK;
 592
 593         ret = IRQ_HANDLED;
 594
 595         if (dev->primary->master) {
 596                 master_priv = dev->primary->master->driver_priv;
 597                 if (master_priv->sarea_priv)
 598                         master_priv->sarea_priv->last_dispatch =
 599                                 READ_BREADCRUMB(dev_priv);
 600         }
 601
 602         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 603                 notify_ring(dev, &dev_priv->ring[RCS]);
 604         if (gt_iir & bsd_usr_interrupt)
 605                 notify_ring(dev, &dev_priv->ring[VCS]);
 606         if (gt_iir & GT_BLT_USER_INTERRUPT)
 607                 notify_ring(dev, &dev_priv->ring[BCS]);
 608
 609         if (de_iir & DE_GSE)
 610                 intel_opregion_gse_intr(dev);
 611
 612         if (de_iir & DE_PLANEA_FLIP_DONE) {
 613                 intel_prepare_page_flip(dev, 0);
 614                 intel_finish_page_flip_plane(dev, 0);
 615         }
 616
 617         if (de_iir & DE_PLANEB_FLIP_DONE) {
 618                 intel_prepare_page_flip(dev, 1);
 619                 intel_finish_page_flip_plane(dev, 1);
 620         }
 621
 622         if (de_iir & DE_PIPEA_VBLANK)
 623                 drm_handle_vblank(dev, 0);
 624
 625         if (de_iir & DE_PIPEB_VBLANK)
 626                 drm_handle_vblank(dev, 1);
 627
 628         /* check event from PCH */
 629         if (de_iir & DE_PCH_EVENT) {
 630                 if (pch_iir & hotplug_mask)
 631                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 632                 pch_irq_handler(dev);
 633         }
 634
 635         if (de_iir & DE_PCU_EVENT) {
 636                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 637                 i915_handle_rps_change(dev);
 638         }
 639
 640         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 641                 /*
 642                  * IIR bits should never already be set because IMR should
 643                  * prevent an interrupt from being shown in IIR. The warning
 644                  * displays a case where we've unsafely cleared
 645                  * dev_priv->pm_iir. Although missing an interrupt of the same
 646                  * type is not a problem, it displays a problem in the logic.
 647                  *
 648                  * The mask bit in IMR is cleared by rps_work.
 649                  */
 650                 unsigned long flags;
 651                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 652                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 653                 dev_priv->pm_iir |= pm_iir;
 654                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 655                 POSTING_READ(GEN6_PMIMR);
 656                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 657                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 658         }
 659
 660         /* should clear PCH hotplug event before clear CPU irq */
 661         I915_WRITE(SDEIIR, pch_iir);
 662         I915_WRITE(GTIIR, gt_iir);
 663         I915_WRITE(DEIIR, de_iir);
 664         I915_WRITE(GEN6_PMIIR, pm_iir);
 665
 666 done:
 667         I915_WRITE(DEIER, de_ier);
 668         POSTING_READ(DEIER);
 669
 670         return ret;
 671 }
 672
 673 /**
 674  * i915_error_work_func - do process context error handling work
 675  * @work: work struct
 676  *
 677  * Fire an error uevent so userspace can see that a hang or error
 678  * was detected.
 679  */
 680 static void i915_error_work_func(struct work_struct *work)
 681 {
 682         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 683                                                     error_work);
 684         struct drm_device *dev = dev_priv->dev;
 685         char *error_event[] = { "ERROR=1", NULL };
 686         char *reset_event[] = { "RESET=1", NULL };
 687         char *reset_done_event[] = { "ERROR=0", NULL };
 688
 689         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 690
 691         if (atomic_read(&dev_priv->mm.wedged)) {
 692                 DRM_DEBUG_DRIVER("resetting chip\n");
 693                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 694                 if (!i915_reset(dev, GRDOM_RENDER)) {
 695                         atomic_set(&dev_priv->mm.wedged, 0);
 696                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 697                 }
 698                 complete_all(&dev_priv->error_completion);
 699         }
 700 }
 701
 702 #ifdef CONFIG_DEBUG_FS
 703 static struct drm_i915_error_object *
 704 i915_error_object_create(struct drm_i915_private *dev_priv,
 705                          struct drm_i915_gem_object *src)
 706 {
 707         struct drm_i915_error_object *dst;
 708         int page, page_count;
 709         u32 reloc_offset;
 710
 711         if (src == NULL || src->pages == NULL)
 712                 return NULL;
 713
 714         page_count = src->base.size / PAGE_SIZE;
 715
 716         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 717         if (dst == NULL)
 718                 return NULL;
 719
 720         reloc_offset = src->gtt_offset;
 721         for (page = 0; page < page_count; page++) {
 722                 unsigned long flags;
 723                 void __iomem *s;
 724                 void *d;
 725
 726                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 727                 if (d == NULL)
 728                         goto unwind;
 729
 730                 local_irq_save(flags);
 731                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 732                                              reloc_offset);
 733                 memcpy_fromio(d, s, PAGE_SIZE);
 734                 io_mapping_unmap_atomic(s);
 735                 local_irq_restore(flags);
 736
 737                 dst->pages[page] = d;
 738
 739                 reloc_offset += PAGE_SIZE;
 740         }
 741         dst->page_count = page_count;
 742         dst->gtt_offset = src->gtt_offset;
 743
 744         return dst;
 745
 746 unwind:
 747         while (page--)
 748                 kfree(dst->pages[page]);
 749         kfree(dst);
 750         return NULL;
 751 }
 752
 753 static void
 754 i915_error_object_free(struct drm_i915_error_object *obj)
 755 {
 756         int page;
 757
 758         if (obj == NULL)
 759                 return;
 760
 761         for (page = 0; page < obj->page_count; page++)
 762                 kfree(obj->pages[page]);
 763
 764         kfree(obj);
 765 }
 766
 767 static void
 768 i915_error_state_free(struct drm_device *dev,
 769                       struct drm_i915_error_state *error)
 770 {
 771         int i;
 772
 773         for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 774                 i915_error_object_free(error->batchbuffer[i]);
 775
 776         for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 777                 i915_error_object_free(error->ringbuffer[i]);
 778
 779         kfree(error->active_bo);
 780         kfree(error->overlay);
 781         kfree(error);
 782 }
 783
 784 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 785                            int count,
 786                            struct list_head *head)
 787 {
 788         struct drm_i915_gem_object *obj;
 789         int i = 0;
 790
 791         list_for_each_entry(obj, head, mm_list) {
 792                 err->size = obj->base.size;
 793                 err->name = obj->base.name;
 794                 err->seqno = obj->last_rendering_seqno;
 795                 err->gtt_offset = obj->gtt_offset;
 796                 err->read_domains = obj->base.read_domains;
 797                 err->write_domain = obj->base.write_domain;
 798                 err->fence_reg = obj->fence_reg;
 799                 err->pinned = 0;
 800                 if (obj->pin_count > 0)
 801                         err->pinned = 1;
 802                 if (obj->user_pin_count > 0)
 803                         err->pinned = -1;
 804                 err->tiling = obj->tiling_mode;
 805                 err->dirty = obj->dirty;
 806                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 807                 err->ring = obj->ring ? obj->ring->id : -1;
 808                 err->cache_level = obj->cache_level;
 809
 810                 if (++i == count)
 811                         break;
 812
 813                 err++;
 814         }
 815
 816         return i;
 817 }
 818
 819 static void i915_gem_record_fences(struct drm_device *dev,
 820                                    struct drm_i915_error_state *error)
 821 {
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823         int i;
 824
 825         /* Fences */
 826         switch (INTEL_INFO(dev)->gen) {
 827         case 7:
 828         case 6:
 829                 for (i = 0; i < 16; i++)
 830                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 831                 break;
 832         case 5:
 833         case 4:
 834                 for (i = 0; i < 16; i++)
 835                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 836                 break;
 837         case 3:
 838                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 839                         for (i = 0; i < 8; i++)
 840                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 841         case 2:
 842                 for (i = 0; i < 8; i++)
 843                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 844                 break;
 845
 846         }
 847 }
 848
 849 static struct drm_i915_error_object *
 850 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 851                              struct intel_ring_buffer *ring)
 852 {
 853         struct drm_i915_gem_object *obj;
 854         u32 seqno;
 855
 856         if (!ring->get_seqno)
 857                 return NULL;
 858
 859         seqno = ring->get_seqno(ring);
 860         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 861                 if (obj->ring != ring)
 862                         continue;
 863
 864                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 865                         continue;
 866
 867                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 868                         continue;
 869
 870                 /* We need to copy these to an anonymous buffer as the simplest
 871                  * method to avoid being overwritten by userspace.
 872                  */
 873                 return i915_error_object_create(dev_priv, obj);
 874         }
 875
 876         return NULL;
 877 }
 878
 879 static void i915_record_ring_state(struct drm_device *dev,
 880                                    struct drm_i915_error_state *error,
 881                                    struct intel_ring_buffer *ring)
 882 {
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884
 885         if (INTEL_INFO(dev)->gen >= 6) {
 886                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
 887                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
 888         }
 889
 890         if (INTEL_INFO(dev)->gen >= 4) {
 891                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
 892                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
 893                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
 894                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
 895                 if (ring->id == RCS) {
 896                         error->instdone1 = I915_READ(INSTDONE1);
 897                         error->bbaddr = I915_READ64(BB_ADDR);
 898                 }
 899         } else {
 900                 error->ipeir[ring->id] = I915_READ(IPEIR);
 901                 error->ipehr[ring->id] = I915_READ(IPEHR);
 902                 error->instdone[ring->id] = I915_READ(INSTDONE);
 903         }
 904
 905         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
 906         error->seqno[ring->id] = ring->get_seqno(ring);
 907         error->acthd[ring->id] = intel_ring_get_active_head(ring);
 908         error->head[ring->id] = I915_READ_HEAD(ring);
 909         error->tail[ring->id] = I915_READ_TAIL(ring);
 910 }
 911
 912 /**
 913  * i915_capture_error_state - capture an error record for later analysis
 914  * @dev: drm device
 915  *
 916  * Should be called when an error is detected (either a hang or an error
 917  * interrupt) to capture error state from the time of the error.  Fills
 918  * out a structure which becomes available in debugfs for user level tools
 919  * to pick up.
 920  */
 921 static void i915_capture_error_state(struct drm_device *dev)
 922 {
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924         struct drm_i915_gem_object *obj;
 925         struct drm_i915_error_state *error;
 926         unsigned long flags;
 927         int i, pipe;
 928
 929         spin_lock_irqsave(&dev_priv->error_lock, flags);
 930         error = dev_priv->first_error;
 931         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 932         if (error)
 933                 return;
 934
 935         /* Account for pipe specific data like PIPE*STAT */
 936         error = kzalloc(sizeof(*error), GFP_ATOMIC);
 937         if (!error) {
 938                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 939                 return;
 940         }
 941
 942         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 943                  dev->primary->index);
 944
 945         error->eir = I915_READ(EIR);
 946         error->pgtbl_er = I915_READ(PGTBL_ER);
 947         for_each_pipe(pipe)
 948                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 949
 950         if (INTEL_INFO(dev)->gen >= 6) {
 951                 error->error = I915_READ(ERROR_GEN6);
 952                 error->done_reg = I915_READ(DONE_REG);
 953         }
 954
 955         i915_record_ring_state(dev, error, &dev_priv->ring[RCS]);
 956         if (HAS_BLT(dev))
 957                 i915_record_ring_state(dev, error, &dev_priv->ring[BCS]);
 958         if (HAS_BSD(dev))
 959                 i915_record_ring_state(dev, error, &dev_priv->ring[VCS]);
 960
 961         i915_gem_record_fences(dev, error);
 962
 963         /* Record the active batch and ring buffers */
 964         for (i = 0; i < I915_NUM_RINGS; i++) {
 965                 error->batchbuffer[i] =
 966                         i915_error_first_batchbuffer(dev_priv,
 967                                                      &dev_priv->ring[i]);
 968
 969                 error->ringbuffer[i] =
 970                         i915_error_object_create(dev_priv,
 971                                                  dev_priv->ring[i].obj);
 972         }
 973
 974         /* Record buffers on the active and pinned lists. */
 975         error->active_bo = NULL;
 976         error->pinned_bo = NULL;
 977
 978         i = 0;
 979         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 980                 i++;
 981         error->active_bo_count = i;
 982         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 983                 i++;
 984         error->pinned_bo_count = i - error->active_bo_count;
 985
 986         error->active_bo = NULL;
 987         error->pinned_bo = NULL;
 988         if (i) {
 989                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 990                                            GFP_ATOMIC);
 991                 if (error->active_bo)
 992                         error->pinned_bo =
 993                                 error->active_bo + error->active_bo_count;
 994         }
 995
 996         if (error->active_bo)
 997                 error->active_bo_count =
 998                         capture_bo_list(error->active_bo,
 999                                         error->active_bo_count,
1000                                         &dev_priv->mm.active_list);
1001
1002         if (error->pinned_bo)
1003                 error->pinned_bo_count =
1004                         capture_bo_list(error->pinned_bo,
1005                                         error->pinned_bo_count,
1006                                         &dev_priv->mm.pinned_list);
1007
1008         do_gettimeofday(&error->time);
1009
1010         error->overlay = intel_overlay_capture_error_state(dev);
1011         error->display = intel_display_capture_error_state(dev);
1012
1013         spin_lock_irqsave(&dev_priv->error_lock, flags);
1014         if (dev_priv->first_error == NULL) {
1015                 dev_priv->first_error = error;
1016                 error = NULL;
1017         }
1018         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1019
1020         if (error)
1021                 i915_error_state_free(dev, error);
1022 }
1023
1024 void i915_destroy_error_state(struct drm_device *dev)
1025 {
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027         struct drm_i915_error_state *error;
1028         unsigned long flags;
1029
1030         spin_lock_irqsave(&dev_priv->error_lock, flags);
1031         error = dev_priv->first_error;
1032         dev_priv->first_error = NULL;
1033         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1034
1035         if (error)
1036                 i915_error_state_free(dev, error);
1037 }
1038 #else
1039 #define i915_capture_error_state(x)
1040 #endif
1041
1042 static void i915_report_and_clear_eir(struct drm_device *dev)
1043 {
1044         struct drm_i915_private *dev_priv = dev->dev_private;
1045         u32 eir = I915_READ(EIR);
1046         int pipe;
1047
1048         if (!eir)
1049                 return;
1050
1051         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1052                eir);
1053
1054         if (IS_G4X(dev)) {
1055                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1056                         u32 ipeir = I915_READ(IPEIR_I965);
1057
1058                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1059                                I915_READ(IPEIR_I965));
1060                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1061                                I915_READ(IPEHR_I965));
1062                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1063                                I915_READ(INSTDONE_I965));
1064                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1065                                I915_READ(INSTPS));
1066                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1067                                I915_READ(INSTDONE1));
1068                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1069                                I915_READ(ACTHD_I965));
1070                         I915_WRITE(IPEIR_I965, ipeir);
1071                         POSTING_READ(IPEIR_I965);
1072                 }
1073                 if (eir & GM45_ERROR_PAGE_TABLE) {
1074                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1075                         printk(KERN_ERR "page table error\n");
1076                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1077                                pgtbl_err);
1078                         I915_WRITE(PGTBL_ER, pgtbl_err);
1079                         POSTING_READ(PGTBL_ER);
1080                 }
1081         }
1082
1083         if (!IS_GEN2(dev)) {
1084                 if (eir & I915_ERROR_PAGE_TABLE) {
1085                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1086                         printk(KERN_ERR "page table error\n");
1087                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1088                                pgtbl_err);
1089                         I915_WRITE(PGTBL_ER, pgtbl_err);
1090                         POSTING_READ(PGTBL_ER);
1091                 }
1092         }
1093
1094         if (eir & I915_ERROR_MEMORY_REFRESH) {
1095                 printk(KERN_ERR "memory refresh error:\n");
1096                 for_each_pipe(pipe)
1097                         printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1098                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1099                 /* pipestat has already been acked */
1100         }
1101         if (eir & I915_ERROR_INSTRUCTION) {
1102                 printk(KERN_ERR "instruction error\n");
1103                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
1104                        I915_READ(INSTPM));
1105                 if (INTEL_INFO(dev)->gen < 4) {
1106                         u32 ipeir = I915_READ(IPEIR);
1107
1108                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1109                                I915_READ(IPEIR));
1110                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1111                                I915_READ(IPEHR));
1112                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1113                                I915_READ(INSTDONE));
1114                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1115                                I915_READ(ACTHD));
1116                         I915_WRITE(IPEIR, ipeir);
1117                         POSTING_READ(IPEIR);
1118                 } else {
1119                         u32 ipeir = I915_READ(IPEIR_I965);
1120
1121                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1122                                I915_READ(IPEIR_I965));
1123                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1124                                I915_READ(IPEHR_I965));
1125                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1126                                I915_READ(INSTDONE_I965));
1127                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1128                                I915_READ(INSTPS));
1129                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1130                                I915_READ(INSTDONE1));
1131                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1132                                I915_READ(ACTHD_I965));
1133                         I915_WRITE(IPEIR_I965, ipeir);
1134                         POSTING_READ(IPEIR_I965);
1135                 }
1136         }
1137
1138         I915_WRITE(EIR, eir);
1139         POSTING_READ(EIR);
1140         eir = I915_READ(EIR);
1141         if (eir) {
1142                 /*
1143                  * some errors might have become stuck,
1144                  * mask them.
1145                  */
1146                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1147                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1148                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1149         }
1150 }
1151
1152 /**
1153  * i915_handle_error - handle an error interrupt
1154  * @dev: drm device
1155  *
1156  * Do some basic checking of regsiter state at error interrupt time and
1157  * dump it to the syslog.  Also call i915_capture_error_state() to make
1158  * sure we get a record and make it available in debugfs.  Fire a uevent
1159  * so userspace knows something bad happened (should trigger collection
1160  * of a ring dump etc.).
1161  */
1162 void i915_handle_error(struct drm_device *dev, bool wedged)
1163 {
1164         struct drm_i915_private *dev_priv = dev->dev_private;
1165
1166         i915_capture_error_state(dev);
1167         i915_report_and_clear_eir(dev);
1168
1169         if (wedged) {
1170                 INIT_COMPLETION(dev_priv->error_completion);
1171                 atomic_set(&dev_priv->mm.wedged, 1);
1172
1173                 /*
1174                  * Wakeup waiting processes so they don't hang
1175                  */
1176                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1177                 if (HAS_BSD(dev))
1178                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1179                 if (HAS_BLT(dev))
1180                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1181         }
1182
1183         queue_work(dev_priv->wq, &dev_priv->error_work);
1184 }
1185
1186 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1187 {
1188         drm_i915_private_t *dev_priv = dev->dev_private;
1189         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1191         struct drm_i915_gem_object *obj;
1192         struct intel_unpin_work *work;
1193         unsigned long flags;
1194         bool stall_detected;
1195
1196         /* Ignore early vblank irqs */
1197         if (intel_crtc == NULL)
1198                 return;
1199
1200         spin_lock_irqsave(&dev->event_lock, flags);
1201         work = intel_crtc->unpin_work;
1202
1203         if (work == NULL || work->pending || !work->enable_stall_check) {
1204                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1205                 spin_unlock_irqrestore(&dev->event_lock, flags);
1206                 return;
1207         }
1208
1209         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1210         obj = work->pending_flip_obj;
1211         if (INTEL_INFO(dev)->gen >= 4) {
1212                 int dspsurf = DSPSURF(intel_crtc->plane);
1213                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1214         } else {
1215                 int dspaddr = DSPADDR(intel_crtc->plane);
1216                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1217                                                         crtc->y * crtc->fb->pitches[0] +
1218                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1219         }
1220
1221         spin_unlock_irqrestore(&dev->event_lock, flags);
1222
1223         if (stall_detected) {
1224                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1225                 intel_prepare_page_flip(dev, intel_crtc->plane);
1226         }
1227 }
1228
1229 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1230 {
1231         struct drm_device *dev = (struct drm_device *) arg;
1232         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1233         struct drm_i915_master_private *master_priv;
1234         u32 iir, new_iir;
1235         u32 pipe_stats[I915_MAX_PIPES];
1236         u32 vblank_status;
1237         int vblank = 0;
1238         unsigned long irqflags;
1239         int irq_received;
1240         int ret = IRQ_NONE, pipe;
1241         bool blc_event = false;
1242
1243         atomic_inc(&dev_priv->irq_received);
1244
1245         iir = I915_READ(IIR);
1246
1247         if (INTEL_INFO(dev)->gen >= 4)
1248                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1249         else
1250                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1251
1252         for (;;) {
1253                 irq_received = iir != 0;
1254
1255                 /* Can't rely on pipestat interrupt bit in iir as it might
1256                  * have been cleared after the pipestat interrupt was received.
1257                  * It doesn't set the bit in iir again, but it still produces
1258                  * interrupts (for non-MSI).
1259                  */
1260                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1261                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1262                         i915_handle_error(dev, false);
1263
1264                 for_each_pipe(pipe) {
1265                         int reg = PIPESTAT(pipe);
1266                         pipe_stats[pipe] = I915_READ(reg);
1267
1268                         /*
1269                          * Clear the PIPE*STAT regs before the IIR
1270                          */
1271                         if (pipe_stats[pipe] & 0x8000ffff) {
1272                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1273                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1274                                                          pipe_name(pipe));
1275                                 I915_WRITE(reg, pipe_stats[pipe]);
1276                                 irq_received = 1;
1277                         }
1278                 }
1279                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1280
1281                 if (!irq_received)
1282                         break;
1283
1284                 ret = IRQ_HANDLED;
1285
1286                 /* Consume port.  Then clear IIR or we'll miss events */
1287                 if ((I915_HAS_HOTPLUG(dev)) &&
1288                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1289                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1290
1291                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1292                                   hotplug_status);
1293                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1294                                 queue_work(dev_priv->wq,
1295                                            &dev_priv->hotplug_work);
1296
1297                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1298                         I915_READ(PORT_HOTPLUG_STAT);
1299                 }
1300
1301                 I915_WRITE(IIR, iir);
1302                 new_iir = I915_READ(IIR); /* Flush posted writes */
1303
1304                 if (dev->primary->master) {
1305                         master_priv = dev->primary->master->driver_priv;
1306                         if (master_priv->sarea_priv)
1307                                 master_priv->sarea_priv->last_dispatch =
1308                                         READ_BREADCRUMB(dev_priv);
1309                 }
1310
1311                 if (iir & I915_USER_INTERRUPT)
1312                         notify_ring(dev, &dev_priv->ring[RCS]);
1313                 if (iir & I915_BSD_USER_INTERRUPT)
1314                         notify_ring(dev, &dev_priv->ring[VCS]);
1315
1316                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1317                         intel_prepare_page_flip(dev, 0);
1318                         if (dev_priv->flip_pending_is_done)
1319                                 intel_finish_page_flip_plane(dev, 0);
1320                 }
1321
1322                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1323                         intel_prepare_page_flip(dev, 1);
1324                         if (dev_priv->flip_pending_is_done)
1325                                 intel_finish_page_flip_plane(dev, 1);
1326                 }
1327
1328                 for_each_pipe(pipe) {
1329                         if (pipe_stats[pipe] & vblank_status &&
1330                             drm_handle_vblank(dev, pipe)) {
1331                                 vblank++;
1332                                 if (!dev_priv->flip_pending_is_done) {
1333                                         i915_pageflip_stall_check(dev, pipe);
1334                                         intel_finish_page_flip(dev, pipe);
1335                                 }
1336                         }
1337
1338                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1339                                 blc_event = true;
1340                 }
1341
1342
1343                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1344                         intel_opregion_asle_intr(dev);
1345
1346                 /* With MSI, interrupts are only generated when iir
1347                  * transitions from zero to nonzero.  If another bit got
1348                  * set while we were handling the existing iir bits, then
1349                  * we would never get another interrupt.
1350                  *
1351                  * This is fine on non-MSI as well, as if we hit this path
1352                  * we avoid exiting the interrupt handler only to generate
1353                  * another one.
1354                  *
1355                  * Note that for MSI this could cause a stray interrupt report
1356                  * if an interrupt landed in the time between writing IIR and
1357                  * the posting read.  This should be rare enough to never
1358                  * trigger the 99% of 100,000 interrupts test for disabling
1359                  * stray interrupts.
1360                  */
1361                 iir = new_iir;
1362         }
1363
1364         return ret;
1365 }
1366
1367 static int i915_emit_irq(struct drm_device * dev)
1368 {
1369         drm_i915_private_t *dev_priv = dev->dev_private;
1370         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1371
1372         i915_kernel_lost_context(dev);
1373
1374         DRM_DEBUG_DRIVER("\n");
1375
1376         dev_priv->counter++;
1377         if (dev_priv->counter > 0x7FFFFFFFUL)
1378                 dev_priv->counter = 1;
1379         if (master_priv->sarea_priv)
1380                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1381
1382         if (BEGIN_LP_RING(4) == 0) {
1383                 OUT_RING(MI_STORE_DWORD_INDEX);
1384                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1385                 OUT_RING(dev_priv->counter);
1386                 OUT_RING(MI_USER_INTERRUPT);
1387                 ADVANCE_LP_RING();
1388         }
1389
1390         return dev_priv->counter;
1391 }
1392
1393 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1394 {
1395         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1396         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1397         int ret = 0;
1398         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1399
1400         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1401                   READ_BREADCRUMB(dev_priv));
1402
1403         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1404                 if (master_priv->sarea_priv)
1405                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1406                 return 0;
1407         }
1408
1409         if (master_priv->sarea_priv)
1410                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1411
1412         if (ring->irq_get(ring)) {
1413                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1414                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1415                 ring->irq_put(ring);
1416         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1417                 ret = -EBUSY;
1418
1419         if (ret == -EBUSY) {
1420                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1421                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1422         }
1423
1424         return ret;
1425 }
1426
1427 /* Needs the lock as it touches the ring.
1428  */
1429 int i915_irq_emit(struct drm_device *dev, void *data,
1430                          struct drm_file *file_priv)
1431 {
1432         drm_i915_private_t *dev_priv = dev->dev_private;
1433         drm_i915_irq_emit_t *emit = data;
1434         int result;
1435
1436         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1437                 DRM_ERROR("called with no initialization\n");
1438                 return -EINVAL;
1439         }
1440
1441         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1442
1443         mutex_lock(&dev->struct_mutex);
1444         result = i915_emit_irq(dev);
1445         mutex_unlock(&dev->struct_mutex);
1446
1447         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1448                 DRM_ERROR("copy_to_user\n");
1449                 return -EFAULT;
1450         }
1451
1452         return 0;
1453 }
1454
1455 /* Doesn't need the hardware lock.
1456  */
1457 int i915_irq_wait(struct drm_device *dev, void *data,
1458                          struct drm_file *file_priv)
1459 {
1460         drm_i915_private_t *dev_priv = dev->dev_private;
1461         drm_i915_irq_wait_t *irqwait = data;
1462
1463         if (!dev_priv) {
1464                 DRM_ERROR("called with no initialization\n");
1465                 return -EINVAL;
1466         }
1467
1468         return i915_wait_irq(dev, irqwait->irq_seq);
1469 }
1470
1471 /* Called from drm generic code, passed 'crtc' which
1472  * we use as a pipe index
1473  */
1474 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1475 {
1476         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1477         unsigned long irqflags;
1478
1479         if (!i915_pipe_enabled(dev, pipe))
1480                 return -EINVAL;
1481
1482         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1483         if (INTEL_INFO(dev)->gen >= 4)
1484                 i915_enable_pipestat(dev_priv, pipe,
1485                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1486         else
1487                 i915_enable_pipestat(dev_priv, pipe,
1488                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1489
1490         /* maintain vblank delivery even in deep C-states */
1491         if (dev_priv->info->gen == 3)
1492                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1493         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1494
1495         return 0;
1496 }
1497
1498 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1499 {
1500         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1501         unsigned long irqflags;
1502
1503         if (!i915_pipe_enabled(dev, pipe))
1504                 return -EINVAL;
1505
1506         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1507         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1508                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1509         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1510
1511         return 0;
1512 }
1513
1514 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1515 {
1516         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1517         unsigned long irqflags;
1518
1519         if (!i915_pipe_enabled(dev, pipe))
1520                 return -EINVAL;
1521
1522         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1523         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1524                                     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1525         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1526
1527         return 0;
1528 }
1529
1530 /* Called from drm generic code, passed 'crtc' which
1531  * we use as a pipe index
1532  */
1533 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1534 {
1535         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1536         unsigned long irqflags;
1537
1538         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1539         if (dev_priv->info->gen == 3)
1540                 I915_WRITE(INSTPM,
1541                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1542
1543         i915_disable_pipestat(dev_priv, pipe,
1544                               PIPE_VBLANK_INTERRUPT_ENABLE |
1545                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1546         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1547 }
1548
1549 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1550 {
1551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1552         unsigned long irqflags;
1553
1554         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1555         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1556                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1557         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1558 }
1559
1560 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1561 {
1562         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1563         unsigned long irqflags;
1564
1565         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1566         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1567                                      DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1568         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1569 }
1570
1571 /* Set the vblank monitor pipe
1572  */
1573 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1574                          struct drm_file *file_priv)
1575 {
1576         drm_i915_private_t *dev_priv = dev->dev_private;
1577
1578         if (!dev_priv) {
1579                 DRM_ERROR("called with no initialization\n");
1580                 return -EINVAL;
1581         }
1582
1583         return 0;
1584 }
1585
1586 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1587                          struct drm_file *file_priv)
1588 {
1589         drm_i915_private_t *dev_priv = dev->dev_private;
1590         drm_i915_vblank_pipe_t *pipe = data;
1591
1592         if (!dev_priv) {
1593                 DRM_ERROR("called with no initialization\n");
1594                 return -EINVAL;
1595         }
1596
1597         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1598
1599         return 0;
1600 }
1601
1602 /**
1603  * Schedule buffer swap at given vertical blank.
1604  */
1605 int i915_vblank_swap(struct drm_device *dev, void *data,
1606                      struct drm_file *file_priv)
1607 {
1608         /* The delayed swap mechanism was fundamentally racy, and has been
1609          * removed.  The model was that the client requested a delayed flip/swap
1610          * from the kernel, then waited for vblank before continuing to perform
1611          * rendering.  The problem was that the kernel might wake the client
1612          * up before it dispatched the vblank swap (since the lock has to be
1613          * held while touching the ringbuffer), in which case the client would
1614          * clear and start the next frame before the swap occurred, and
1615          * flicker would occur in addition to likely missing the vblank.
1616          *
1617          * In the absence of this ioctl, userland falls back to a correct path
1618          * of waiting for a vblank, then dispatching the swap on its own.
1619          * Context switching to userland and back is plenty fast enough for
1620          * meeting the requirements of vblank swapping.
1621          */
1622         return -EINVAL;
1623 }
1624
1625 static u32
1626 ring_last_seqno(struct intel_ring_buffer *ring)
1627 {
1628         return list_entry(ring->request_list.prev,
1629                           struct drm_i915_gem_request, list)->seqno;
1630 }
1631
1632 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1633 {
1634         if (list_empty(&ring->request_list) ||
1635             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1636                 /* Issue a wake-up to catch stuck h/w. */
1637                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1638                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1639                                   ring->name,
1640                                   ring->waiting_seqno,
1641                                   ring->get_seqno(ring));
1642                         wake_up_all(&ring->irq_queue);
1643                         *err = true;
1644                 }
1645                 return true;
1646         }
1647         return false;
1648 }
1649
1650 static bool kick_ring(struct intel_ring_buffer *ring)
1651 {
1652         struct drm_device *dev = ring->dev;
1653         struct drm_i915_private *dev_priv = dev->dev_private;
1654         u32 tmp = I915_READ_CTL(ring);
1655         if (tmp & RING_WAIT) {
1656                 DRM_ERROR("Kicking stuck wait on %s\n",
1657                           ring->name);
1658                 I915_WRITE_CTL(ring, tmp);
1659                 return true;
1660         }
1661         return false;
1662 }
1663
1664 /**
1665  * This is called when the chip hasn't reported back with completed
1666  * batchbuffers in a long time. The first time this is called we simply record
1667  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1668  * again, we assume the chip is wedged and try to fix it.
1669  */
1670 void i915_hangcheck_elapsed(unsigned long data)
1671 {
1672         struct drm_device *dev = (struct drm_device *)data;
1673         drm_i915_private_t *dev_priv = dev->dev_private;
1674         uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1675         bool err = false;
1676
1677         if (!i915_enable_hangcheck)
1678                 return;
1679
1680         /* If all work is done then ACTHD clearly hasn't advanced. */
1681         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1682             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1683             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1684                 dev_priv->hangcheck_count = 0;
1685                 if (err)
1686                         goto repeat;
1687                 return;
1688         }
1689
1690         if (INTEL_INFO(dev)->gen < 4) {
1691                 instdone = I915_READ(INSTDONE);
1692                 instdone1 = 0;
1693         } else {
1694                 instdone = I915_READ(INSTDONE_I965);
1695                 instdone1 = I915_READ(INSTDONE1);
1696         }
1697         acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1698         acthd_bsd = HAS_BSD(dev) ?
1699                 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1700         acthd_blt = HAS_BLT(dev) ?
1701                 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1702
1703         if (dev_priv->last_acthd == acthd &&
1704             dev_priv->last_acthd_bsd == acthd_bsd &&
1705             dev_priv->last_acthd_blt == acthd_blt &&
1706             dev_priv->last_instdone == instdone &&
1707             dev_priv->last_instdone1 == instdone1) {
1708                 if (dev_priv->hangcheck_count++ > 1) {
1709                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1710                         i915_handle_error(dev, true);
1711
1712                         if (!IS_GEN2(dev)) {
1713                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1714                                  * If so we can simply poke the RB_WAIT bit
1715                                  * and break the hang. This should work on
1716                                  * all but the second generation chipsets.
1717                                  */
1718                                 if (kick_ring(&dev_priv->ring[RCS]))
1719                                         goto repeat;
1720
1721                                 if (HAS_BSD(dev) &&
1722                                     kick_ring(&dev_priv->ring[VCS]))
1723                                         goto repeat;
1724
1725                                 if (HAS_BLT(dev) &&
1726                                     kick_ring(&dev_priv->ring[BCS]))
1727                                         goto repeat;
1728                         }
1729
1730                         return;
1731                 }
1732         } else {
1733                 dev_priv->hangcheck_count = 0;
1734
1735                 dev_priv->last_acthd = acthd;
1736                 dev_priv->last_acthd_bsd = acthd_bsd;
1737                 dev_priv->last_acthd_blt = acthd_blt;
1738                 dev_priv->last_instdone = instdone;
1739                 dev_priv->last_instdone1 = instdone1;
1740         }
1741
1742 repeat:
1743         /* Reset timer case chip hangs without another request being added */
1744         mod_timer(&dev_priv->hangcheck_timer,
1745                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1746 }
1747
1748 /* drm_dma.h hooks
1749 */
1750 static void ironlake_irq_preinstall(struct drm_device *dev)
1751 {
1752         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1753
1754         atomic_set(&dev_priv->irq_received, 0);
1755
1756         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1757         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1758         if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1759                 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1760
1761         I915_WRITE(HWSTAM, 0xeffe);
1762         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1763                 /* Workaround stalls observed on Sandy Bridge GPUs by
1764                  * making the blitter command streamer generate a
1765                  * write to the Hardware Status Page for
1766                  * MI_USER_INTERRUPT.  This appears to serialize the
1767                  * previous seqno write out before the interrupt
1768                  * happens.
1769                  */
1770                 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1771                 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1772         }
1773
1774         /* XXX hotplug from PCH */
1775
1776         I915_WRITE(DEIMR, 0xffffffff);
1777         I915_WRITE(DEIER, 0x0);
1778         POSTING_READ(DEIER);
1779
1780         /* and GT */
1781         I915_WRITE(GTIMR, 0xffffffff);
1782         I915_WRITE(GTIER, 0x0);
1783         POSTING_READ(GTIER);
1784
1785         /* south display irq */
1786         I915_WRITE(SDEIMR, 0xffffffff);
1787         I915_WRITE(SDEIER, 0x0);
1788         POSTING_READ(SDEIER);
1789 }
1790
1791 /*
1792  * Enable digital hotplug on the PCH, and configure the DP short pulse
1793  * duration to 2ms (which is the minimum in the Display Port spec)
1794  *
1795  * This register is the same on all known PCH chips.
1796  */
1797
1798 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1799 {
1800         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1801         u32     hotplug;
1802
1803         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1804         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1805         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1806         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1807         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1808         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1809 }
1810
1811 static int ironlake_irq_postinstall(struct drm_device *dev)
1812 {
1813         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1814         /* enable kind of interrupts always enabled */
1815         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1816                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1817         u32 render_irqs;
1818         u32 hotplug_mask;
1819
1820         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1821         if (HAS_BSD(dev))
1822                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1823         if (HAS_BLT(dev))
1824                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1825
1826         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1827         dev_priv->irq_mask = ~display_mask;
1828
1829         /* should always can generate irq */
1830         I915_WRITE(DEIIR, I915_READ(DEIIR));
1831         I915_WRITE(DEIMR, dev_priv->irq_mask);
1832         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1833         POSTING_READ(DEIER);
1834
1835         dev_priv->gt_irq_mask = ~0;
1836
1837         I915_WRITE(GTIIR, I915_READ(GTIIR));
1838         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1839
1840         if (IS_GEN6(dev))
1841                 render_irqs =
1842                         GT_USER_INTERRUPT |
1843                         GT_GEN6_BSD_USER_INTERRUPT |
1844                         GT_BLT_USER_INTERRUPT;
1845         else
1846                 render_irqs =
1847                         GT_USER_INTERRUPT |
1848                         GT_PIPE_NOTIFY |
1849                         GT_BSD_USER_INTERRUPT;
1850         I915_WRITE(GTIER, render_irqs);
1851         POSTING_READ(GTIER);
1852
1853         if (HAS_PCH_CPT(dev)) {
1854                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1855                                 SDE_PORTB_HOTPLUG_CPT |
1856                                 SDE_PORTC_HOTPLUG_CPT |
1857                                 SDE_PORTD_HOTPLUG_CPT);
1858         } else {
1859                 hotplug_mask = (SDE_CRT_HOTPLUG |
1860                                 SDE_PORTB_HOTPLUG |
1861                                 SDE_PORTC_HOTPLUG |
1862                                 SDE_PORTD_HOTPLUG |
1863                                 SDE_AUX_MASK);
1864         }
1865
1866         dev_priv->pch_irq_mask = ~hotplug_mask;
1867
1868         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1869         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1870         I915_WRITE(SDEIER, hotplug_mask);
1871         POSTING_READ(SDEIER);
1872
1873         ironlake_enable_pch_hotplug(dev);
1874
1875         if (IS_IRONLAKE_M(dev)) {
1876                 /* Clear & enable PCU event interrupts */
1877                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1878                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1879                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1880         }
1881
1882         return 0;
1883 }
1884
1885 static int ivybridge_irq_postinstall(struct drm_device *dev)
1886 {
1887         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1888         /* enable kind of interrupts always enabled */
1889         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1890                 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1891                 DE_PLANEB_FLIP_DONE_IVB;
1892         u32 render_irqs;
1893         u32 hotplug_mask;
1894
1895         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1896         if (HAS_BSD(dev))
1897                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1898         if (HAS_BLT(dev))
1899                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1900
1901         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1902         dev_priv->irq_mask = ~display_mask;
1903
1904         /* should always can generate irq */
1905         I915_WRITE(DEIIR, I915_READ(DEIIR));
1906         I915_WRITE(DEIMR, dev_priv->irq_mask);
1907         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1908                    DE_PIPEB_VBLANK_IVB);
1909         POSTING_READ(DEIER);
1910
1911         dev_priv->gt_irq_mask = ~0;
1912
1913         I915_WRITE(GTIIR, I915_READ(GTIIR));
1914         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1915
1916         render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1917                 GT_BLT_USER_INTERRUPT;
1918         I915_WRITE(GTIER, render_irqs);
1919         POSTING_READ(GTIER);
1920
1921         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1922                         SDE_PORTB_HOTPLUG_CPT |
1923                         SDE_PORTC_HOTPLUG_CPT |
1924                         SDE_PORTD_HOTPLUG_CPT);
1925         dev_priv->pch_irq_mask = ~hotplug_mask;
1926
1927         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1928         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1929         I915_WRITE(SDEIER, hotplug_mask);
1930         POSTING_READ(SDEIER);
1931
1932         ironlake_enable_pch_hotplug(dev);
1933
1934         return 0;
1935 }
1936
1937 static void i915_driver_irq_preinstall(struct drm_device * dev)
1938 {
1939         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1940         int pipe;
1941
1942         atomic_set(&dev_priv->irq_received, 0);
1943
1944         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1945         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1946
1947         if (I915_HAS_HOTPLUG(dev)) {
1948                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1949                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1950         }
1951
1952         I915_WRITE(HWSTAM, 0xeffe);
1953         for_each_pipe(pipe)
1954                 I915_WRITE(PIPESTAT(pipe), 0);
1955         I915_WRITE(IMR, 0xffffffff);
1956         I915_WRITE(IER, 0x0);
1957         POSTING_READ(IER);
1958 }
1959
1960 /*
1961  * Must be called after intel_modeset_init or hotplug interrupts won't be
1962  * enabled correctly.
1963  */
1964 static int i915_driver_irq_postinstall(struct drm_device *dev)
1965 {
1966         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1967         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1968         u32 error_mask;
1969
1970         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1971
1972         /* Unmask the interrupts that we always want on. */
1973         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1974
1975         dev_priv->pipestat[0] = 0;
1976         dev_priv->pipestat[1] = 0;
1977
1978         if (I915_HAS_HOTPLUG(dev)) {
1979                 /* Enable in IER... */
1980                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1981                 /* and unmask in IMR */
1982                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1983         }
1984
1985         /*
1986          * Enable some error detection, note the instruction error mask
1987          * bit is reserved, so we leave it masked.
1988          */
1989         if (IS_G4X(dev)) {
1990                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1991                                GM45_ERROR_MEM_PRIV |
1992                                GM45_ERROR_CP_PRIV |
1993                                I915_ERROR_MEMORY_REFRESH);
1994         } else {
1995                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1996                                I915_ERROR_MEMORY_REFRESH);
1997         }
1998         I915_WRITE(EMR, error_mask);
1999
2000         I915_WRITE(IMR, dev_priv->irq_mask);
2001         I915_WRITE(IER, enable_mask);
2002         POSTING_READ(IER);
2003
2004         if (I915_HAS_HOTPLUG(dev)) {
2005                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2006
2007                 /* Note HDMI and DP share bits */
2008                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2009                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2010                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2011                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2012                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2013                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2014                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2015                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2016                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2017                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2018                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2019                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2020
2021                         /* Programming the CRT detection parameters tends
2022                            to generate a spurious hotplug event about three
2023                            seconds later.  So just do it once.
2024                         */
2025                         if (IS_G4X(dev))
2026                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2027                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2028                 }
2029
2030                 /* Ignore TV since it's buggy */
2031
2032                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2033         }
2034
2035         intel_opregion_enable_asle(dev);
2036
2037         return 0;
2038 }
2039
2040 static void ironlake_irq_uninstall(struct drm_device *dev)
2041 {
2042         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2043
2044         if (!dev_priv)
2045                 return;
2046
2047         dev_priv->vblank_pipe = 0;
2048
2049         I915_WRITE(HWSTAM, 0xffffffff);
2050
2051         I915_WRITE(DEIMR, 0xffffffff);
2052         I915_WRITE(DEIER, 0x0);
2053         I915_WRITE(DEIIR, I915_READ(DEIIR));
2054
2055         I915_WRITE(GTIMR, 0xffffffff);
2056         I915_WRITE(GTIER, 0x0);
2057         I915_WRITE(GTIIR, I915_READ(GTIIR));
2058
2059         I915_WRITE(SDEIMR, 0xffffffff);
2060         I915_WRITE(SDEIER, 0x0);
2061         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2062 }
2063
2064 static void i915_driver_irq_uninstall(struct drm_device * dev)
2065 {
2066         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2067         int pipe;
2068
2069         if (!dev_priv)
2070                 return;
2071
2072         dev_priv->vblank_pipe = 0;
2073
2074         if (I915_HAS_HOTPLUG(dev)) {
2075                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2076                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2077         }
2078
2079         I915_WRITE(HWSTAM, 0xffffffff);
2080         for_each_pipe(pipe)
2081                 I915_WRITE(PIPESTAT(pipe), 0);
2082         I915_WRITE(IMR, 0xffffffff);
2083         I915_WRITE(IER, 0x0);
2084
2085         for_each_pipe(pipe)
2086                 I915_WRITE(PIPESTAT(pipe),
2087                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2088         I915_WRITE(IIR, I915_READ(IIR));
2089 }
2090
2091 void intel_irq_init(struct drm_device *dev)
2092 {
2093         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2094         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2095         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2096                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2097                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2098         }
2099
2100         if (drm_core_check_feature(dev, DRIVER_MODESET))
2101                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2102         else
2103                 dev->driver->get_vblank_timestamp = NULL;
2104         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2105
2106         if (IS_IVYBRIDGE(dev)) {
2107                 /* Share pre & uninstall handlers with ILK/SNB */
2108                 dev->driver->irq_handler = ivybridge_irq_handler;
2109                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2110                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2111                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2112                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2113                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2114         } else if (HAS_PCH_SPLIT(dev)) {
2115                 dev->driver->irq_handler = ironlake_irq_handler;
2116                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2117                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2118                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2119                 dev->driver->enable_vblank = ironlake_enable_vblank;
2120                 dev->driver->disable_vblank = ironlake_disable_vblank;
2121         } else {
2122                 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2123                 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2124                 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2125                 dev->driver->irq_handler = i915_driver_irq_handler;
2126                 dev->driver->enable_vblank = i915_enable_vblank;
2127                 dev->driver->disable_vblank = i915_disable_vblank;
2128         }
2129 }