drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pc8.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pc8.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pc8.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pc8.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pc8.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pc8.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 236                                                  enum pipe pipe, bool enable)
 237 {
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 240                                           DE_PIPEB_FIFO_UNDERRUN;
 241
 242         if (enable)
 243                 ironlake_enable_display_irq(dev_priv, bit);
 244         else
 245                 ironlake_disable_display_irq(dev_priv, bit);
 246 }
 247
 248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 249                                                   enum pipe pipe, bool enable)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         if (enable) {
 253                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 254
 255                 if (!ivb_can_enable_err_int(dev))
 256                         return;
 257
 258                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 259         } else {
 260                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 261
 262                 /* Change the state _after_ we've read out the current one. */
 263                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 264
 265                 if (!was_enabled &&
 266                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 267                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 268                                       pipe_name(pipe));
 269                 }
 270         }
 271 }
 272
 273 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 274                                                   enum pipe pipe, bool enable)
 275 {
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277
 278         assert_spin_locked(&dev_priv->irq_lock);
 279
 280         if (enable)
 281                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 282         else
 283                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 284         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 285         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 286 }
 287
 288 /**
 289  * ibx_display_interrupt_update - update SDEIMR
 290  * @dev_priv: driver private
 291  * @interrupt_mask: mask of interrupt bits to update
 292  * @enabled_irq_mask: mask of interrupt bits to enable
 293  */
 294 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 295                                          uint32_t interrupt_mask,
 296                                          uint32_t enabled_irq_mask)
 297 {
 298         uint32_t sdeimr = I915_READ(SDEIMR);
 299         sdeimr &= ~interrupt_mask;
 300         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 301
 302         assert_spin_locked(&dev_priv->irq_lock);
 303
 304         if (dev_priv->pc8.irqs_disabled &&
 305             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 306                 WARN(1, "IRQs disabled\n");
 307                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 308                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 309                                                  interrupt_mask);
 310                 return;
 311         }
 312
 313         I915_WRITE(SDEIMR, sdeimr);
 314         POSTING_READ(SDEIMR);
 315 }
 316 #define ibx_enable_display_interrupt(dev_priv, bits) \
 317         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 318 #define ibx_disable_display_interrupt(dev_priv, bits) \
 319         ibx_display_interrupt_update((dev_priv), (bits), 0)
 320
 321 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 322                                             enum transcoder pch_transcoder,
 323                                             bool enable)
 324 {
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 327                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 328
 329         if (enable)
 330                 ibx_enable_display_interrupt(dev_priv, bit);
 331         else
 332                 ibx_disable_display_interrupt(dev_priv, bit);
 333 }
 334
 335 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 336                                             enum transcoder pch_transcoder,
 337                                             bool enable)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         if (enable) {
 342                 I915_WRITE(SERR_INT,
 343                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 344
 345                 if (!cpt_can_enable_serr_int(dev))
 346                         return;
 347
 348                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 349         } else {
 350                 uint32_t tmp = I915_READ(SERR_INT);
 351                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 352
 353                 /* Change the state _after_ we've read out the current one. */
 354                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 355
 356                 if (!was_enabled &&
 357                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 358                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 359                                       transcoder_name(pch_transcoder));
 360                 }
 361         }
 362 }
 363
 364 /**
 365  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 366  * @dev: drm device
 367  * @pipe: pipe
 368  * @enable: true if we want to report FIFO underrun errors, false otherwise
 369  *
 370  * This function makes us disable or enable CPU fifo underruns for a specific
 371  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 372  * reporting for one pipe may also disable all the other CPU error interruts for
 373  * the other pipes, due to the fact that there's just one interrupt mask/enable
 374  * bit for all the pipes.
 375  *
 376  * Returns the previous state of underrun reporting.
 377  */
 378 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 379                                            enum pipe pipe, bool enable)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 384         unsigned long flags;
 385         bool ret;
 386
 387         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 388
 389         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 390
 391         if (enable == ret)
 392                 goto done;
 393
 394         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 395
 396         if (IS_GEN5(dev) || IS_GEN6(dev))
 397                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 398         else if (IS_GEN7(dev))
 399                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 400         else if (IS_GEN8(dev))
 401                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 402
 403 done:
 404         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 405         return ret;
 406 }
 407
 408 /**
 409  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 410  * @dev: drm device
 411  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 412  * @enable: true if we want to report FIFO underrun errors, false otherwise
 413  *
 414  * This function makes us disable or enable PCH fifo underruns for a specific
 415  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 416  * underrun reporting for one transcoder may also disable all the other PCH
 417  * error interruts for the other transcoders, due to the fact that there's just
 418  * one interrupt mask/enable bit for all the transcoders.
 419  *
 420  * Returns the previous state of underrun reporting.
 421  */
 422 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 423                                            enum transcoder pch_transcoder,
 424                                            bool enable)
 425 {
 426         struct drm_i915_private *dev_priv = dev->dev_private;
 427         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 429         unsigned long flags;
 430         bool ret;
 431
 432         /*
 433          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 434          * has only one pch transcoder A that all pipes can use. To avoid racy
 435          * pch transcoder -> pipe lookups from interrupt code simply store the
 436          * underrun statistics in crtc A. Since we never expose this anywhere
 437          * nor use it outside of the fifo underrun code here using the "wrong"
 438          * crtc on LPT won't cause issues.
 439          */
 440
 441         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 442
 443         ret = !intel_crtc->pch_fifo_underrun_disabled;
 444
 445         if (enable == ret)
 446                 goto done;
 447
 448         intel_crtc->pch_fifo_underrun_disabled = !enable;
 449
 450         if (HAS_PCH_IBX(dev))
 451                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 452         else
 453                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 454
 455 done:
 456         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 457         return ret;
 458 }
 459
 460
 461 void
 462 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 463 {
 464         u32 reg = PIPESTAT(pipe);
 465         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 466
 467         assert_spin_locked(&dev_priv->irq_lock);
 468
 469         if ((pipestat & mask) == mask)
 470                 return;
 471
 472         /* Enable the interrupt, clear any pending status */
 473         pipestat |= mask | (mask >> 16);
 474         I915_WRITE(reg, pipestat);
 475         POSTING_READ(reg);
 476 }
 477
 478 void
 479 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 480 {
 481         u32 reg = PIPESTAT(pipe);
 482         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 483
 484         assert_spin_locked(&dev_priv->irq_lock);
 485
 486         if ((pipestat & mask) == 0)
 487                 return;
 488
 489         pipestat &= ~mask;
 490         I915_WRITE(reg, pipestat);
 491         POSTING_READ(reg);
 492 }
 493
 494 /**
 495  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 496  */
 497 static void i915_enable_asle_pipestat(struct drm_device *dev)
 498 {
 499         drm_i915_private_t *dev_priv = dev->dev_private;
 500         unsigned long irqflags;
 501
 502         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 503                 return;
 504
 505         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 506
 507         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
 508         if (INTEL_INFO(dev)->gen >= 4)
 509                 i915_enable_pipestat(dev_priv, PIPE_A,
 510                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 511
 512         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 513 }
 514
 515 /**
 516  * i915_pipe_enabled - check if a pipe is enabled
 517  * @dev: DRM device
 518  * @pipe: pipe to check
 519  *
 520  * Reading certain registers when the pipe is disabled can hang the chip.
 521  * Use this routine to make sure the PLL is running and the pipe is active
 522  * before reading such registers if unsure.
 523  */
 524 static int
 525 i915_pipe_enabled(struct drm_device *dev, int pipe)
 526 {
 527         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 528
 529         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 530                 /* Locking is horribly broken here, but whatever. */
 531                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 532                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 533
 534                 return intel_crtc->active;
 535         } else {
 536                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 537         }
 538 }
 539
 540 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 541 {
 542         /* Gen2 doesn't have a hardware frame counter */
 543         return 0;
 544 }
 545
 546 /* Called from drm generic code, passed a 'crtc', which
 547  * we use as a pipe index
 548  */
 549 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 550 {
 551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 552         unsigned long high_frame;
 553         unsigned long low_frame;
 554         u32 high1, high2, low, pixel, vbl_start;
 555
 556         if (!i915_pipe_enabled(dev, pipe)) {
 557                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 558                                 "pipe %c\n", pipe_name(pipe));
 559                 return 0;
 560         }
 561
 562         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 563                 struct intel_crtc *intel_crtc =
 564                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 565                 const struct drm_display_mode *mode =
 566                         &intel_crtc->config.adjusted_mode;
 567
 568                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 569         } else {
 570                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 571                 u32 htotal;
 572
 573                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 574                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 575
 576                 vbl_start *= htotal;
 577         }
 578
 579         high_frame = PIPEFRAME(pipe);
 580         low_frame = PIPEFRAMEPIXEL(pipe);
 581
 582         /*
 583          * High & low register fields aren't synchronized, so make sure
 584          * we get a low value that's stable across two reads of the high
 585          * register.
 586          */
 587         do {
 588                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 589                 low   = I915_READ(low_frame);
 590                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 591         } while (high1 != high2);
 592
 593         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 594         pixel = low & PIPE_PIXEL_MASK;
 595         low >>= PIPE_FRAME_LOW_SHIFT;
 596
 597         /*
 598          * The frame counter increments at beginning of active.
 599          * Cook up a vblank counter by also checking the pixel
 600          * counter against vblank start.
 601          */
 602         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 603 }
 604
 605 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 606 {
 607         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 608         int reg = PIPE_FRMCOUNT_GM45(pipe);
 609
 610         if (!i915_pipe_enabled(dev, pipe)) {
 611                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 612                                  "pipe %c\n", pipe_name(pipe));
 613                 return 0;
 614         }
 615
 616         return I915_READ(reg);
 617 }
 618
 619 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 620 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 621
 622 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 623 {
 624         struct drm_i915_private *dev_priv = dev->dev_private;
 625         uint32_t status;
 626         int reg;
 627
 628         if (INTEL_INFO(dev)->gen >= 8) {
 629                 status = GEN8_PIPE_VBLANK;
 630                 reg = GEN8_DE_PIPE_ISR(pipe);
 631         } else if (INTEL_INFO(dev)->gen >= 7) {
 632                 status = DE_PIPE_VBLANK_IVB(pipe);
 633                 reg = DEISR;
 634         } else {
 635                 status = DE_PIPE_VBLANK(pipe);
 636                 reg = DEISR;
 637         }
 638
 639         return __raw_i915_read32(dev_priv, reg) & status;
 640 }
 641
 642 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 643                                     unsigned int flags, int *vpos, int *hpos,
 644                                     ktime_t *stime, ktime_t *etime)
 645 {
 646         struct drm_i915_private *dev_priv = dev->dev_private;
 647         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 649         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 650         int position;
 651         int vbl_start, vbl_end, htotal, vtotal;
 652         bool in_vbl = true;
 653         int ret = 0;
 654         unsigned long irqflags;
 655
 656         if (!intel_crtc->active) {
 657                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 658                                  "pipe %c\n", pipe_name(pipe));
 659                 return 0;
 660         }
 661
 662         htotal = mode->crtc_htotal;
 663         vtotal = mode->crtc_vtotal;
 664         vbl_start = mode->crtc_vblank_start;
 665         vbl_end = mode->crtc_vblank_end;
 666
 667         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 668                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 669                 vbl_end /= 2;
 670                 vtotal /= 2;
 671         }
 672
 673         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 674
 675         /*
 676          * Lock uncore.lock, as we will do multiple timing critical raw
 677          * register reads, potentially with preemption disabled, so the
 678          * following code must not block on uncore.lock.
 679          */
 680         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 681
 682         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 683
 684         /* Get optional system timestamp before query. */
 685         if (stime)
 686                 *stime = ktime_get();
 687
 688         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 689                 /* No obvious pixelcount register. Only query vertical
 690                  * scanout position from Display scan line register.
 691                  */
 692                 if (IS_GEN2(dev))
 693                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 694                 else
 695                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 696
 697                 if (HAS_DDI(dev)) {
 698                         /*
 699                          * On HSW HDMI outputs there seems to be a 2 line
 700                          * difference, whereas eDP has the normal 1 line
 701                          * difference that earlier platforms have. External
 702                          * DP is unknown. For now just check for the 2 line
 703                          * difference case on all output types on HSW+.
 704                          *
 705                          * This might misinterpret the scanline counter being
 706                          * one line too far along on eDP, but that's less
 707                          * dangerous than the alternative since that would lead
 708                          * the vblank timestamp code astray when it sees a
 709                          * scanline count before vblank_start during a vblank
 710                          * interrupt.
 711                          */
 712                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 713                         if ((in_vbl && (position == vbl_start - 2 ||
 714                                         position == vbl_start - 1)) ||
 715                             (!in_vbl && (position == vbl_end - 2 ||
 716                                          position == vbl_end - 1)))
 717                                 position = (position + 2) % vtotal;
 718                 } else if (HAS_PCH_SPLIT(dev)) {
 719                         /*
 720                          * The scanline counter increments at the leading edge
 721                          * of hsync, ie. it completely misses the active portion
 722                          * of the line. Fix up the counter at both edges of vblank
 723                          * to get a more accurate picture whether we're in vblank
 724                          * or not.
 725                          */
 726                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 727                         if ((in_vbl && position == vbl_start - 1) ||
 728                             (!in_vbl && position == vbl_end - 1))
 729                                 position = (position + 1) % vtotal;
 730                 } else {
 731                         /*
 732                          * ISR vblank status bits don't work the way we'd want
 733                          * them to work on non-PCH platforms (for
 734                          * ilk_pipe_in_vblank_locked()), and there doesn't
 735                          * appear any other way to determine if we're currently
 736                          * in vblank.
 737                          *
 738                          * Instead let's assume that we're already in vblank if
 739                          * we got called from the vblank interrupt and the
 740                          * scanline counter value indicates that we're on the
 741                          * line just prior to vblank start. This should result
 742                          * in the correct answer, unless the vblank interrupt
 743                          * delivery really got delayed for almost exactly one
 744                          * full frame/field.
 745                          */
 746                         if (flags & DRM_CALLED_FROM_VBLIRQ &&
 747                             position == vbl_start - 1) {
 748                                 position = (position + 1) % vtotal;
 749
 750                                 /* Signal this correction as "applied". */
 751                                 ret |= 0x8;
 752                         }
 753                 }
 754         } else {
 755                 /* Have access to pixelcount since start of frame.
 756                  * We can split this into vertical and horizontal
 757                  * scanout position.
 758                  */
 759                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 760
 761                 /* convert to pixel counts */
 762                 vbl_start *= htotal;
 763                 vbl_end *= htotal;
 764                 vtotal *= htotal;
 765         }
 766
 767         /* Get optional system timestamp after query. */
 768         if (etime)
 769                 *etime = ktime_get();
 770
 771         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 772
 773         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 774
 775         in_vbl = position >= vbl_start && position < vbl_end;
 776
 777         /*
 778          * While in vblank, position will be negative
 779          * counting up towards 0 at vbl_end. And outside
 780          * vblank, position will be positive counting
 781          * up since vbl_end.
 782          */
 783         if (position >= vbl_start)
 784                 position -= vbl_end;
 785         else
 786                 position += vtotal - vbl_end;
 787
 788         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 789                 *vpos = position;
 790                 *hpos = 0;
 791         } else {
 792                 *vpos = position / htotal;
 793                 *hpos = position - (*vpos * htotal);
 794         }
 795
 796         /* In vblank? */
 797         if (in_vbl)
 798                 ret |= DRM_SCANOUTPOS_INVBL;
 799
 800         return ret;
 801 }
 802
 803 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 804                               int *max_error,
 805                               struct timeval *vblank_time,
 806                               unsigned flags)
 807 {
 808         struct drm_crtc *crtc;
 809
 810         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 811                 DRM_ERROR("Invalid crtc %d\n", pipe);
 812                 return -EINVAL;
 813         }
 814
 815         /* Get drm_crtc to timestamp: */
 816         crtc = intel_get_crtc_for_pipe(dev, pipe);
 817         if (crtc == NULL) {
 818                 DRM_ERROR("Invalid crtc %d\n", pipe);
 819                 return -EINVAL;
 820         }
 821
 822         if (!crtc->enabled) {
 823                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 824                 return -EBUSY;
 825         }
 826
 827         /* Helper routine in DRM core does all the work: */
 828         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 829                                                      vblank_time, flags,
 830                                                      crtc,
 831                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 832 }
 833
 834 static bool intel_hpd_irq_event(struct drm_device *dev,
 835                                 struct drm_connector *connector)
 836 {
 837         enum drm_connector_status old_status;
 838
 839         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 840         old_status = connector->status;
 841
 842         connector->status = connector->funcs->detect(connector, false);
 843         if (old_status == connector->status)
 844                 return false;
 845
 846         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 847                       connector->base.id,
 848                       drm_get_connector_name(connector),
 849                       drm_get_connector_status_name(old_status),
 850                       drm_get_connector_status_name(connector->status));
 851
 852         return true;
 853 }
 854
 855 /*
 856  * Handle hotplug events outside the interrupt handler proper.
 857  */
 858 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 859
 860 static void i915_hotplug_work_func(struct work_struct *work)
 861 {
 862         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 863                                                     hotplug_work);
 864         struct drm_device *dev = dev_priv->dev;
 865         struct drm_mode_config *mode_config = &dev->mode_config;
 866         struct intel_connector *intel_connector;
 867         struct intel_encoder *intel_encoder;
 868         struct drm_connector *connector;
 869         unsigned long irqflags;
 870         bool hpd_disabled = false;
 871         bool changed = false;
 872         u32 hpd_event_bits;
 873
 874         /* HPD irq before everything is fully set up. */
 875         if (!dev_priv->enable_hotplug_processing)
 876                 return;
 877
 878         mutex_lock(&mode_config->mutex);
 879         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 880
 881         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 882
 883         hpd_event_bits = dev_priv->hpd_event_bits;
 884         dev_priv->hpd_event_bits = 0;
 885         list_for_each_entry(connector, &mode_config->connector_list, head) {
 886                 intel_connector = to_intel_connector(connector);
 887                 intel_encoder = intel_connector->encoder;
 888                 if (intel_encoder->hpd_pin > HPD_NONE &&
 889                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 890                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 891                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 892                                  "switching from hotplug detection to polling\n",
 893                                 drm_get_connector_name(connector));
 894                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 895                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 896                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 897                         hpd_disabled = true;
 898                 }
 899                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 900                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 901                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 902                 }
 903         }
 904          /* if there were no outputs to poll, poll was disabled,
 905           * therefore make sure it's enabled when disabling HPD on
 906           * some connectors */
 907         if (hpd_disabled) {
 908                 drm_kms_helper_poll_enable(dev);
 909                 mod_timer(&dev_priv->hotplug_reenable_timer,
 910                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 911         }
 912
 913         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 914
 915         list_for_each_entry(connector, &mode_config->connector_list, head) {
 916                 intel_connector = to_intel_connector(connector);
 917                 intel_encoder = intel_connector->encoder;
 918                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 919                         if (intel_encoder->hot_plug)
 920                                 intel_encoder->hot_plug(intel_encoder);
 921                         if (intel_hpd_irq_event(dev, connector))
 922                                 changed = true;
 923                 }
 924         }
 925         mutex_unlock(&mode_config->mutex);
 926
 927         if (changed)
 928                 drm_kms_helper_hotplug_event(dev);
 929 }
 930
 931 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 932 {
 933         drm_i915_private_t *dev_priv = dev->dev_private;
 934         u32 busy_up, busy_down, max_avg, min_avg;
 935         u8 new_delay;
 936
 937         spin_lock(&mchdev_lock);
 938
 939         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 940
 941         new_delay = dev_priv->ips.cur_delay;
 942
 943         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 944         busy_up = I915_READ(RCPREVBSYTUPAVG);
 945         busy_down = I915_READ(RCPREVBSYTDNAVG);
 946         max_avg = I915_READ(RCBMAXAVG);
 947         min_avg = I915_READ(RCBMINAVG);
 948
 949         /* Handle RCS change request from hw */
 950         if (busy_up > max_avg) {
 951                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 952                         new_delay = dev_priv->ips.cur_delay - 1;
 953                 if (new_delay < dev_priv->ips.max_delay)
 954                         new_delay = dev_priv->ips.max_delay;
 955         } else if (busy_down < min_avg) {
 956                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 957                         new_delay = dev_priv->ips.cur_delay + 1;
 958                 if (new_delay > dev_priv->ips.min_delay)
 959                         new_delay = dev_priv->ips.min_delay;
 960         }
 961
 962         if (ironlake_set_drps(dev, new_delay))
 963                 dev_priv->ips.cur_delay = new_delay;
 964
 965         spin_unlock(&mchdev_lock);
 966
 967         return;
 968 }
 969
 970 static void notify_ring(struct drm_device *dev,
 971                         struct intel_ring_buffer *ring)
 972 {
 973         if (ring->obj == NULL)
 974                 return;
 975
 976         trace_i915_gem_request_complete(ring);
 977
 978         wake_up_all(&ring->irq_queue);
 979         i915_queue_hangcheck(dev);
 980 }
 981
 982 static void gen6_pm_rps_work(struct work_struct *work)
 983 {
 984         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 985                                                     rps.work);
 986         u32 pm_iir;
 987         int new_delay, adj;
 988
 989         spin_lock_irq(&dev_priv->irq_lock);
 990         pm_iir = dev_priv->rps.pm_iir;
 991         dev_priv->rps.pm_iir = 0;
 992         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
 993         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
 994         spin_unlock_irq(&dev_priv->irq_lock);
 995
 996         /* Make sure we didn't queue anything we're not going to process. */
 997         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
 998
 999         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1000                 return;
1001
1002         mutex_lock(&dev_priv->rps.hw_lock);
1003
1004         adj = dev_priv->rps.last_adj;
1005         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1006                 if (adj > 0)
1007                         adj *= 2;
1008                 else
1009                         adj = 1;
1010                 new_delay = dev_priv->rps.cur_delay + adj;
1011
1012                 /*
1013                  * For better performance, jump directly
1014                  * to RPe if we're below it.
1015                  */
1016                 if (new_delay < dev_priv->rps.rpe_delay)
1017                         new_delay = dev_priv->rps.rpe_delay;
1018         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1019                 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1020                         new_delay = dev_priv->rps.rpe_delay;
1021                 else
1022                         new_delay = dev_priv->rps.min_delay;
1023                 adj = 0;
1024         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1025                 if (adj < 0)
1026                         adj *= 2;
1027                 else
1028                         adj = -1;
1029                 new_delay = dev_priv->rps.cur_delay + adj;
1030         } else { /* unknown event */
1031                 new_delay = dev_priv->rps.cur_delay;
1032         }
1033
1034         /* sysfs frequency interfaces may have snuck in while servicing the
1035          * interrupt
1036          */
1037         new_delay = clamp_t(int, new_delay,
1038                             dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1039         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1040
1041         if (IS_VALLEYVIEW(dev_priv->dev))
1042                 valleyview_set_rps(dev_priv->dev, new_delay);
1043         else
1044                 gen6_set_rps(dev_priv->dev, new_delay);
1045
1046         mutex_unlock(&dev_priv->rps.hw_lock);
1047 }
1048
1049
1050 /**
1051  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1052  * occurred.
1053  * @work: workqueue struct
1054  *
1055  * Doesn't actually do anything except notify userspace. As a consequence of
1056  * this event, userspace should try to remap the bad rows since statistically
1057  * it is likely the same row is more likely to go bad again.
1058  */
1059 static void ivybridge_parity_work(struct work_struct *work)
1060 {
1061         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1062                                                     l3_parity.error_work);
1063         u32 error_status, row, bank, subbank;
1064         char *parity_event[6];
1065         uint32_t misccpctl;
1066         unsigned long flags;
1067         uint8_t slice = 0;
1068
1069         /* We must turn off DOP level clock gating to access the L3 registers.
1070          * In order to prevent a get/put style interface, acquire struct mutex
1071          * any time we access those registers.
1072          */
1073         mutex_lock(&dev_priv->dev->struct_mutex);
1074
1075         /* If we've screwed up tracking, just let the interrupt fire again */
1076         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1077                 goto out;
1078
1079         misccpctl = I915_READ(GEN7_MISCCPCTL);
1080         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1081         POSTING_READ(GEN7_MISCCPCTL);
1082
1083         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1084                 u32 reg;
1085
1086                 slice--;
1087                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1088                         break;
1089
1090                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1091
1092                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1093
1094                 error_status = I915_READ(reg);
1095                 row = GEN7_PARITY_ERROR_ROW(error_status);
1096                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1097                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1098
1099                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1100                 POSTING_READ(reg);
1101
1102                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1103                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1104                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1105                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1106                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1107                 parity_event[5] = NULL;
1108
1109                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1110                                    KOBJ_CHANGE, parity_event);
1111
1112                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1113                           slice, row, bank, subbank);
1114
1115                 kfree(parity_event[4]);
1116                 kfree(parity_event[3]);
1117                 kfree(parity_event[2]);
1118                 kfree(parity_event[1]);
1119         }
1120
1121         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1122
1123 out:
1124         WARN_ON(dev_priv->l3_parity.which_slice);
1125         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1126         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1127         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1128
1129         mutex_unlock(&dev_priv->dev->struct_mutex);
1130 }
1131
1132 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1133 {
1134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1135
1136         if (!HAS_L3_DPF(dev))
1137                 return;
1138
1139         spin_lock(&dev_priv->irq_lock);
1140         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1141         spin_unlock(&dev_priv->irq_lock);
1142
1143         iir &= GT_PARITY_ERROR(dev);
1144         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1145                 dev_priv->l3_parity.which_slice |= 1 << 1;
1146
1147         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1148                 dev_priv->l3_parity.which_slice |= 1 << 0;
1149
1150         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1151 }
1152
1153 static void ilk_gt_irq_handler(struct drm_device *dev,
1154                                struct drm_i915_private *dev_priv,
1155                                u32 gt_iir)
1156 {
1157         if (gt_iir &
1158             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1159                 notify_ring(dev, &dev_priv->ring[RCS]);
1160         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1161                 notify_ring(dev, &dev_priv->ring[VCS]);
1162 }
1163
1164 static void snb_gt_irq_handler(struct drm_device *dev,
1165                                struct drm_i915_private *dev_priv,
1166                                u32 gt_iir)
1167 {
1168
1169         if (gt_iir &
1170             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1171                 notify_ring(dev, &dev_priv->ring[RCS]);
1172         if (gt_iir & GT_BSD_USER_INTERRUPT)
1173                 notify_ring(dev, &dev_priv->ring[VCS]);
1174         if (gt_iir & GT_BLT_USER_INTERRUPT)
1175                 notify_ring(dev, &dev_priv->ring[BCS]);
1176
1177         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1178                       GT_BSD_CS_ERROR_INTERRUPT |
1179                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1180                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1181                 i915_handle_error(dev, false);
1182         }
1183
1184         if (gt_iir & GT_PARITY_ERROR(dev))
1185                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1186 }
1187
1188 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1189                                        struct drm_i915_private *dev_priv,
1190                                        u32 master_ctl)
1191 {
1192         u32 rcs, bcs, vcs;
1193         uint32_t tmp = 0;
1194         irqreturn_t ret = IRQ_NONE;
1195
1196         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1197                 tmp = I915_READ(GEN8_GT_IIR(0));
1198                 if (tmp) {
1199                         ret = IRQ_HANDLED;
1200                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1201                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1202                         if (rcs & GT_RENDER_USER_INTERRUPT)
1203                                 notify_ring(dev, &dev_priv->ring[RCS]);
1204                         if (bcs & GT_RENDER_USER_INTERRUPT)
1205                                 notify_ring(dev, &dev_priv->ring[BCS]);
1206                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1207                 } else
1208                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1209         }
1210
1211         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1212                 tmp = I915_READ(GEN8_GT_IIR(1));
1213                 if (tmp) {
1214                         ret = IRQ_HANDLED;
1215                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1216                         if (vcs & GT_RENDER_USER_INTERRUPT)
1217                                 notify_ring(dev, &dev_priv->ring[VCS]);
1218                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1219                 } else
1220                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1221         }
1222
1223         if (master_ctl & GEN8_GT_VECS_IRQ) {
1224                 tmp = I915_READ(GEN8_GT_IIR(3));
1225                 if (tmp) {
1226                         ret = IRQ_HANDLED;
1227                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1228                         if (vcs & GT_RENDER_USER_INTERRUPT)
1229                                 notify_ring(dev, &dev_priv->ring[VECS]);
1230                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1231                 } else
1232                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1233         }
1234
1235         return ret;
1236 }
1237
1238 #define HPD_STORM_DETECT_PERIOD 1000
1239 #define HPD_STORM_THRESHOLD 5
1240
1241 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1242                                          u32 hotplug_trigger,
1243                                          const u32 *hpd)
1244 {
1245         drm_i915_private_t *dev_priv = dev->dev_private;
1246         int i;
1247         bool storm_detected = false;
1248
1249         if (!hotplug_trigger)
1250                 return;
1251
1252         spin_lock(&dev_priv->irq_lock);
1253         for (i = 1; i < HPD_NUM_PINS; i++) {
1254
1255                 if (hpd[i] & hotplug_trigger &&
1256                     dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1257                         /*
1258                          * On GMCH platforms the interrupt mask bits only
1259                          * prevent irq generation, not the setting of the
1260                          * hotplug bits itself. So only WARN about unexpected
1261                          * interrupts on saner platforms.
1262                          */
1263                         WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1264                                   "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1265                                   hotplug_trigger, i, hpd[i]);
1266
1267                         continue;
1268                 }
1269
1270                 if (!(hpd[i] & hotplug_trigger) ||
1271                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1272                         continue;
1273
1274                 dev_priv->hpd_event_bits |= (1 << i);
1275                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1276                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1277                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1278                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1279                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1280                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1281                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1282                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1283                         dev_priv->hpd_event_bits &= ~(1 << i);
1284                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1285                         storm_detected = true;
1286                 } else {
1287                         dev_priv->hpd_stats[i].hpd_cnt++;
1288                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1289                                       dev_priv->hpd_stats[i].hpd_cnt);
1290                 }
1291         }
1292
1293         if (storm_detected)
1294                 dev_priv->display.hpd_irq_setup(dev);
1295         spin_unlock(&dev_priv->irq_lock);
1296
1297         /*
1298          * Our hotplug handler can grab modeset locks (by calling down into the
1299          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1300          * queue for otherwise the flush_work in the pageflip code will
1301          * deadlock.
1302          */
1303         schedule_work(&dev_priv->hotplug_work);
1304 }
1305
1306 static void gmbus_irq_handler(struct drm_device *dev)
1307 {
1308         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1309
1310         wake_up_all(&dev_priv->gmbus_wait_queue);
1311 }
1312
1313 static void dp_aux_irq_handler(struct drm_device *dev)
1314 {
1315         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1316
1317         wake_up_all(&dev_priv->gmbus_wait_queue);
1318 }
1319
1320 #if defined(CONFIG_DEBUG_FS)
1321 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1322                                          uint32_t crc0, uint32_t crc1,
1323                                          uint32_t crc2, uint32_t crc3,
1324                                          uint32_t crc4)
1325 {
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1328         struct intel_pipe_crc_entry *entry;
1329         int head, tail;
1330
1331         spin_lock(&pipe_crc->lock);
1332
1333         if (!pipe_crc->entries) {
1334                 spin_unlock(&pipe_crc->lock);
1335                 DRM_ERROR("spurious interrupt\n");
1336                 return;
1337         }
1338
1339         head = pipe_crc->head;
1340         tail = pipe_crc->tail;
1341
1342         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1343                 spin_unlock(&pipe_crc->lock);
1344                 DRM_ERROR("CRC buffer overflowing\n");
1345                 return;
1346         }
1347
1348         entry = &pipe_crc->entries[head];
1349
1350         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1351         entry->crc[0] = crc0;
1352         entry->crc[1] = crc1;
1353         entry->crc[2] = crc2;
1354         entry->crc[3] = crc3;
1355         entry->crc[4] = crc4;
1356
1357         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1358         pipe_crc->head = head;
1359
1360         spin_unlock(&pipe_crc->lock);
1361
1362         wake_up_interruptible(&pipe_crc->wq);
1363 }
1364 #else
1365 static inline void
1366 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1367                              uint32_t crc0, uint32_t crc1,
1368                              uint32_t crc2, uint32_t crc3,
1369                              uint32_t crc4) {}
1370 #endif
1371
1372
1373 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377         display_pipe_crc_irq_handler(dev, pipe,
1378                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1379                                      0, 0, 0, 0);
1380 }
1381
1382 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1383 {
1384         struct drm_i915_private *dev_priv = dev->dev_private;
1385
1386         display_pipe_crc_irq_handler(dev, pipe,
1387                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1388                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1389                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1390                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1391                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1392 }
1393
1394 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1395 {
1396         struct drm_i915_private *dev_priv = dev->dev_private;
1397         uint32_t res1, res2;
1398
1399         if (INTEL_INFO(dev)->gen >= 3)
1400                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1401         else
1402                 res1 = 0;
1403
1404         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1405                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1406         else
1407                 res2 = 0;
1408
1409         display_pipe_crc_irq_handler(dev, pipe,
1410                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1411                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1412                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1413                                      res1, res2);
1414 }
1415
1416 /* The RPS events need forcewake, so we add them to a work queue and mask their
1417  * IMR bits until the work is done. Other interrupts can be processed without
1418  * the work queue. */
1419 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1420 {
1421         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1422                 spin_lock(&dev_priv->irq_lock);
1423                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1424                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1425                 spin_unlock(&dev_priv->irq_lock);
1426
1427                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1428         }
1429
1430         if (HAS_VEBOX(dev_priv->dev)) {
1431                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1432                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1433
1434                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1435                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1436                         i915_handle_error(dev_priv->dev, false);
1437                 }
1438         }
1439 }
1440
1441 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1442 {
1443         struct drm_device *dev = (struct drm_device *) arg;
1444         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1445         u32 iir, gt_iir, pm_iir;
1446         irqreturn_t ret = IRQ_NONE;
1447         unsigned long irqflags;
1448         int pipe;
1449         u32 pipe_stats[I915_MAX_PIPES];
1450
1451         atomic_inc(&dev_priv->irq_received);
1452
1453         while (true) {
1454                 iir = I915_READ(VLV_IIR);
1455                 gt_iir = I915_READ(GTIIR);
1456                 pm_iir = I915_READ(GEN6_PMIIR);
1457
1458                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1459                         goto out;
1460
1461                 ret = IRQ_HANDLED;
1462
1463                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1464
1465                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1466                 for_each_pipe(pipe) {
1467                         int reg = PIPESTAT(pipe);
1468                         pipe_stats[pipe] = I915_READ(reg);
1469
1470                         /*
1471                          * Clear the PIPE*STAT regs before the IIR
1472                          */
1473                         if (pipe_stats[pipe] & 0x8000ffff) {
1474                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1475                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1476                                                          pipe_name(pipe));
1477                                 I915_WRITE(reg, pipe_stats[pipe]);
1478                         }
1479                 }
1480                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1481
1482                 for_each_pipe(pipe) {
1483                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1484                                 drm_handle_vblank(dev, pipe);
1485
1486                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1487                                 intel_prepare_page_flip(dev, pipe);
1488                                 intel_finish_page_flip(dev, pipe);
1489                         }
1490
1491                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1492                                 i9xx_pipe_crc_irq_handler(dev, pipe);
1493                 }
1494
1495                 /* Consume port.  Then clear IIR or we'll miss events */
1496                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1497                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1498                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1499
1500                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1501                                          hotplug_status);
1502
1503                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1504
1505                         if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1506                                 dp_aux_irq_handler(dev);
1507
1508                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1509                         I915_READ(PORT_HOTPLUG_STAT);
1510                 }
1511
1512                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1513                         gmbus_irq_handler(dev);
1514
1515                 if (pm_iir)
1516                         gen6_rps_irq_handler(dev_priv, pm_iir);
1517
1518                 I915_WRITE(GTIIR, gt_iir);
1519                 I915_WRITE(GEN6_PMIIR, pm_iir);
1520                 I915_WRITE(VLV_IIR, iir);
1521         }
1522
1523 out:
1524         return ret;
1525 }
1526
1527 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1528 {
1529         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1530         int pipe;
1531         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1532
1533         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1534
1535         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1536                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1537                                SDE_AUDIO_POWER_SHIFT);
1538                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1539                                  port_name(port));
1540         }
1541
1542         if (pch_iir & SDE_AUX_MASK)
1543                 dp_aux_irq_handler(dev);
1544
1545         if (pch_iir & SDE_GMBUS)
1546                 gmbus_irq_handler(dev);
1547
1548         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1549                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1550
1551         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1552                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1553
1554         if (pch_iir & SDE_POISON)
1555                 DRM_ERROR("PCH poison interrupt\n");
1556
1557         if (pch_iir & SDE_FDI_MASK)
1558                 for_each_pipe(pipe)
1559                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1560                                          pipe_name(pipe),
1561                                          I915_READ(FDI_RX_IIR(pipe)));
1562
1563         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1564                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1565
1566         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1567                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1568
1569         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1570                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1571                                                           false))
1572                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1573
1574         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1575                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1576                                                           false))
1577                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1578 }
1579
1580 static void ivb_err_int_handler(struct drm_device *dev)
1581 {
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         u32 err_int = I915_READ(GEN7_ERR_INT);
1584         enum pipe pipe;
1585
1586         if (err_int & ERR_INT_POISON)
1587                 DRM_ERROR("Poison interrupt\n");
1588
1589         for_each_pipe(pipe) {
1590                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1591                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1592                                                                   false))
1593                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1594                                                  pipe_name(pipe));
1595                 }
1596
1597                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1598                         if (IS_IVYBRIDGE(dev))
1599                                 ivb_pipe_crc_irq_handler(dev, pipe);
1600                         else
1601                                 hsw_pipe_crc_irq_handler(dev, pipe);
1602                 }
1603         }
1604
1605         I915_WRITE(GEN7_ERR_INT, err_int);
1606 }
1607
1608 static void cpt_serr_int_handler(struct drm_device *dev)
1609 {
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         u32 serr_int = I915_READ(SERR_INT);
1612
1613         if (serr_int & SERR_INT_POISON)
1614                 DRM_ERROR("PCH poison interrupt\n");
1615
1616         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1617                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1618                                                           false))
1619                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1620
1621         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1622                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1623                                                           false))
1624                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1625
1626         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1627                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1628                                                           false))
1629                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1630
1631         I915_WRITE(SERR_INT, serr_int);
1632 }
1633
1634 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1635 {
1636         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1637         int pipe;
1638         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1639
1640         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1641
1642         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1643                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1644                                SDE_AUDIO_POWER_SHIFT_CPT);
1645                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1646                                  port_name(port));
1647         }
1648
1649         if (pch_iir & SDE_AUX_MASK_CPT)
1650                 dp_aux_irq_handler(dev);
1651
1652         if (pch_iir & SDE_GMBUS_CPT)
1653                 gmbus_irq_handler(dev);
1654
1655         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1656                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1657
1658         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1659                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1660
1661         if (pch_iir & SDE_FDI_MASK_CPT)
1662                 for_each_pipe(pipe)
1663                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1664                                          pipe_name(pipe),
1665                                          I915_READ(FDI_RX_IIR(pipe)));
1666
1667         if (pch_iir & SDE_ERROR_CPT)
1668                 cpt_serr_int_handler(dev);
1669 }
1670
1671 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1672 {
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         enum pipe pipe;
1675
1676         if (de_iir & DE_AUX_CHANNEL_A)
1677                 dp_aux_irq_handler(dev);
1678
1679         if (de_iir & DE_GSE)
1680                 intel_opregion_asle_intr(dev);
1681
1682         if (de_iir & DE_POISON)
1683                 DRM_ERROR("Poison interrupt\n");
1684
1685         for_each_pipe(pipe) {
1686                 if (de_iir & DE_PIPE_VBLANK(pipe))
1687                         drm_handle_vblank(dev, pipe);
1688
1689                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1690                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1691                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1692                                                  pipe_name(pipe));
1693
1694                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1695                         i9xx_pipe_crc_irq_handler(dev, pipe);
1696
1697                 /* plane/pipes map 1:1 on ilk+ */
1698                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1699                         intel_prepare_page_flip(dev, pipe);
1700                         intel_finish_page_flip_plane(dev, pipe);
1701                 }
1702         }
1703
1704         /* check event from PCH */
1705         if (de_iir & DE_PCH_EVENT) {
1706                 u32 pch_iir = I915_READ(SDEIIR);
1707
1708                 if (HAS_PCH_CPT(dev))
1709                         cpt_irq_handler(dev, pch_iir);
1710                 else
1711                         ibx_irq_handler(dev, pch_iir);
1712
1713                 /* should clear PCH hotplug event before clear CPU irq */
1714                 I915_WRITE(SDEIIR, pch_iir);
1715         }
1716
1717         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1718                 ironlake_rps_change_irq_handler(dev);
1719 }
1720
1721 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1722 {
1723         struct drm_i915_private *dev_priv = dev->dev_private;
1724         enum pipe i;
1725
1726         if (de_iir & DE_ERR_INT_IVB)
1727                 ivb_err_int_handler(dev);
1728
1729         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1730                 dp_aux_irq_handler(dev);
1731
1732         if (de_iir & DE_GSE_IVB)
1733                 intel_opregion_asle_intr(dev);
1734
1735         for_each_pipe(i) {
1736                 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1737                         drm_handle_vblank(dev, i);
1738
1739                 /* plane/pipes map 1:1 on ilk+ */
1740                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1741                         intel_prepare_page_flip(dev, i);
1742                         intel_finish_page_flip_plane(dev, i);
1743                 }
1744         }
1745
1746         /* check event from PCH */
1747         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1748                 u32 pch_iir = I915_READ(SDEIIR);
1749
1750                 cpt_irq_handler(dev, pch_iir);
1751
1752                 /* clear PCH hotplug event before clear CPU irq */
1753                 I915_WRITE(SDEIIR, pch_iir);
1754         }
1755 }
1756
1757 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1758 {
1759         struct drm_device *dev = (struct drm_device *) arg;
1760         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1761         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1762         irqreturn_t ret = IRQ_NONE;
1763
1764         atomic_inc(&dev_priv->irq_received);
1765
1766         /* We get interrupts on unclaimed registers, so check for this before we
1767          * do any I915_{READ,WRITE}. */
1768         intel_uncore_check_errors(dev);
1769
1770         /* disable master interrupt before clearing iir  */
1771         de_ier = I915_READ(DEIER);
1772         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1773         POSTING_READ(DEIER);
1774
1775         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1776          * interrupts will will be stored on its back queue, and then we'll be
1777          * able to process them after we restore SDEIER (as soon as we restore
1778          * it, we'll get an interrupt if SDEIIR still has something to process
1779          * due to its back queue). */
1780         if (!HAS_PCH_NOP(dev)) {
1781                 sde_ier = I915_READ(SDEIER);
1782                 I915_WRITE(SDEIER, 0);
1783                 POSTING_READ(SDEIER);
1784         }
1785
1786         gt_iir = I915_READ(GTIIR);
1787         if (gt_iir) {
1788                 if (INTEL_INFO(dev)->gen >= 6)
1789                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1790                 else
1791                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1792                 I915_WRITE(GTIIR, gt_iir);
1793                 ret = IRQ_HANDLED;
1794         }
1795
1796         de_iir = I915_READ(DEIIR);
1797         if (de_iir) {
1798                 if (INTEL_INFO(dev)->gen >= 7)
1799                         ivb_display_irq_handler(dev, de_iir);
1800                 else
1801                         ilk_display_irq_handler(dev, de_iir);
1802                 I915_WRITE(DEIIR, de_iir);
1803                 ret = IRQ_HANDLED;
1804         }
1805
1806         if (INTEL_INFO(dev)->gen >= 6) {
1807                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1808                 if (pm_iir) {
1809                         gen6_rps_irq_handler(dev_priv, pm_iir);
1810                         I915_WRITE(GEN6_PMIIR, pm_iir);
1811                         ret = IRQ_HANDLED;
1812                 }
1813         }
1814
1815         I915_WRITE(DEIER, de_ier);
1816         POSTING_READ(DEIER);
1817         if (!HAS_PCH_NOP(dev)) {
1818                 I915_WRITE(SDEIER, sde_ier);
1819                 POSTING_READ(SDEIER);
1820         }
1821
1822         return ret;
1823 }
1824
1825 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1826 {
1827         struct drm_device *dev = arg;
1828         struct drm_i915_private *dev_priv = dev->dev_private;
1829         u32 master_ctl;
1830         irqreturn_t ret = IRQ_NONE;
1831         uint32_t tmp = 0;
1832         enum pipe pipe;
1833
1834         atomic_inc(&dev_priv->irq_received);
1835
1836         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1837         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1838         if (!master_ctl)
1839                 return IRQ_NONE;
1840
1841         I915_WRITE(GEN8_MASTER_IRQ, 0);
1842         POSTING_READ(GEN8_MASTER_IRQ);
1843
1844         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1845
1846         if (master_ctl & GEN8_DE_MISC_IRQ) {
1847                 tmp = I915_READ(GEN8_DE_MISC_IIR);
1848                 if (tmp & GEN8_DE_MISC_GSE)
1849                         intel_opregion_asle_intr(dev);
1850                 else if (tmp)
1851                         DRM_ERROR("Unexpected DE Misc interrupt\n");
1852                 else
1853                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1854
1855                 if (tmp) {
1856                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1857                         ret = IRQ_HANDLED;
1858                 }
1859         }
1860
1861         if (master_ctl & GEN8_DE_PORT_IRQ) {
1862                 tmp = I915_READ(GEN8_DE_PORT_IIR);
1863                 if (tmp & GEN8_AUX_CHANNEL_A)
1864                         dp_aux_irq_handler(dev);
1865                 else if (tmp)
1866                         DRM_ERROR("Unexpected DE Port interrupt\n");
1867                 else
1868                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1869
1870                 if (tmp) {
1871                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1872                         ret = IRQ_HANDLED;
1873                 }
1874         }
1875
1876         for_each_pipe(pipe) {
1877                 uint32_t pipe_iir;
1878
1879                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1880                         continue;
1881
1882                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1883                 if (pipe_iir & GEN8_PIPE_VBLANK)
1884                         drm_handle_vblank(dev, pipe);
1885
1886                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1887                         intel_prepare_page_flip(dev, pipe);
1888                         intel_finish_page_flip_plane(dev, pipe);
1889                 }
1890
1891                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1892                         hsw_pipe_crc_irq_handler(dev, pipe);
1893
1894                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1895                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1896                                                                   false))
1897                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1898                                                  pipe_name(pipe));
1899                 }
1900
1901                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1902                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1903                                   pipe_name(pipe),
1904                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1905                 }
1906
1907                 if (pipe_iir) {
1908                         ret = IRQ_HANDLED;
1909                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1910                 } else
1911                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1912         }
1913
1914         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1915                 /*
1916                  * FIXME(BDW): Assume for now that the new interrupt handling
1917                  * scheme also closed the SDE interrupt handling race we've seen
1918                  * on older pch-split platforms. But this needs testing.
1919                  */
1920                 u32 pch_iir = I915_READ(SDEIIR);
1921
1922                 cpt_irq_handler(dev, pch_iir);
1923
1924                 if (pch_iir) {
1925                         I915_WRITE(SDEIIR, pch_iir);
1926                         ret = IRQ_HANDLED;
1927                 }
1928         }
1929
1930         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1931         POSTING_READ(GEN8_MASTER_IRQ);
1932
1933         return ret;
1934 }
1935
1936 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1937                                bool reset_completed)
1938 {
1939         struct intel_ring_buffer *ring;
1940         int i;
1941
1942         /*
1943          * Notify all waiters for GPU completion events that reset state has
1944          * been changed, and that they need to restart their wait after
1945          * checking for potential errors (and bail out to drop locks if there is
1946          * a gpu reset pending so that i915_error_work_func can acquire them).
1947          */
1948
1949         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1950         for_each_ring(ring, dev_priv, i)
1951                 wake_up_all(&ring->irq_queue);
1952
1953         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1954         wake_up_all(&dev_priv->pending_flip_queue);
1955
1956         /*
1957          * Signal tasks blocked in i915_gem_wait_for_error that the pending
1958          * reset state is cleared.
1959          */
1960         if (reset_completed)
1961                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1962 }
1963
1964 /**
1965  * i915_error_work_func - do process context error handling work
1966  * @work: work struct
1967  *
1968  * Fire an error uevent so userspace can see that a hang or error
1969  * was detected.
1970  */
1971 static void i915_error_work_func(struct work_struct *work)
1972 {
1973         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1974                                                     work);
1975         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1976                                                     gpu_error);
1977         struct drm_device *dev = dev_priv->dev;
1978         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1979         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1980         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1981         int ret;
1982
1983         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
1984
1985         /*
1986          * Note that there's only one work item which does gpu resets, so we
1987          * need not worry about concurrent gpu resets potentially incrementing
1988          * error->reset_counter twice. We only need to take care of another
1989          * racing irq/hangcheck declaring the gpu dead for a second time. A
1990          * quick check for that is good enough: schedule_work ensures the
1991          * correct ordering between hang detection and this work item, and since
1992          * the reset in-progress bit is only ever set by code outside of this
1993          * work we don't need to worry about any other races.
1994          */
1995         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1996                 DRM_DEBUG_DRIVER("resetting chip\n");
1997                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
1998                                    reset_event);
1999
2000                 /*
2001                  * All state reset _must_ be completed before we update the
2002                  * reset counter, for otherwise waiters might miss the reset
2003                  * pending state and not properly drop locks, resulting in
2004                  * deadlocks with the reset work.
2005                  */
2006                 ret = i915_reset(dev);
2007
2008                 intel_display_handle_reset(dev);
2009
2010                 if (ret == 0) {
2011                         /*
2012                          * After all the gem state is reset, increment the reset
2013                          * counter and wake up everyone waiting for the reset to
2014                          * complete.
2015                          *
2016                          * Since unlock operations are a one-sided barrier only,
2017                          * we need to insert a barrier here to order any seqno
2018                          * updates before
2019                          * the counter increment.
2020                          */
2021                         smp_mb__before_atomic_inc();
2022                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2023
2024                         kobject_uevent_env(&dev->primary->kdev->kobj,
2025                                            KOBJ_CHANGE, reset_done_event);
2026                 } else {
2027                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2028                 }
2029
2030                 /*
2031                  * Note: The wake_up also serves as a memory barrier so that
2032                  * waiters see the update value of the reset counter atomic_t.
2033                  */
2034                 i915_error_wake_up(dev_priv, true);
2035         }
2036 }
2037
2038 static void i915_report_and_clear_eir(struct drm_device *dev)
2039 {
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         uint32_t instdone[I915_NUM_INSTDONE_REG];
2042         u32 eir = I915_READ(EIR);
2043         int pipe, i;
2044
2045         if (!eir)
2046                 return;
2047
2048         pr_err("render error detected, EIR: 0x%08x\n", eir);
2049
2050         i915_get_extra_instdone(dev, instdone);
2051
2052         if (IS_G4X(dev)) {
2053                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2054                         u32 ipeir = I915_READ(IPEIR_I965);
2055
2056                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2057                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2058                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2059                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2060                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2061                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2062                         I915_WRITE(IPEIR_I965, ipeir);
2063                         POSTING_READ(IPEIR_I965);
2064                 }
2065                 if (eir & GM45_ERROR_PAGE_TABLE) {
2066                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2067                         pr_err("page table error\n");
2068                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2069                         I915_WRITE(PGTBL_ER, pgtbl_err);
2070                         POSTING_READ(PGTBL_ER);
2071                 }
2072         }
2073
2074         if (!IS_GEN2(dev)) {
2075                 if (eir & I915_ERROR_PAGE_TABLE) {
2076                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2077                         pr_err("page table error\n");
2078                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2079                         I915_WRITE(PGTBL_ER, pgtbl_err);
2080                         POSTING_READ(PGTBL_ER);
2081                 }
2082         }
2083
2084         if (eir & I915_ERROR_MEMORY_REFRESH) {
2085                 pr_err("memory refresh error:\n");
2086                 for_each_pipe(pipe)
2087                         pr_err("pipe %c stat: 0x%08x\n",
2088                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2089                 /* pipestat has already been acked */
2090         }
2091         if (eir & I915_ERROR_INSTRUCTION) {
2092                 pr_err("instruction error\n");
2093                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2094                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2095                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2096                 if (INTEL_INFO(dev)->gen < 4) {
2097                         u32 ipeir = I915_READ(IPEIR);
2098
2099                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2100                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2101                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2102                         I915_WRITE(IPEIR, ipeir);
2103                         POSTING_READ(IPEIR);
2104                 } else {
2105                         u32 ipeir = I915_READ(IPEIR_I965);
2106
2107                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2108                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2109                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2110                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2111                         I915_WRITE(IPEIR_I965, ipeir);
2112                         POSTING_READ(IPEIR_I965);
2113                 }
2114         }
2115
2116         I915_WRITE(EIR, eir);
2117         POSTING_READ(EIR);
2118         eir = I915_READ(EIR);
2119         if (eir) {
2120                 /*
2121                  * some errors might have become stuck,
2122                  * mask them.
2123                  */
2124                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2125                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2126                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2127         }
2128 }
2129
2130 /**
2131  * i915_handle_error - handle an error interrupt
2132  * @dev: drm device
2133  *
2134  * Do some basic checking of regsiter state at error interrupt time and
2135  * dump it to the syslog.  Also call i915_capture_error_state() to make
2136  * sure we get a record and make it available in debugfs.  Fire a uevent
2137  * so userspace knows something bad happened (should trigger collection
2138  * of a ring dump etc.).
2139  */
2140 void i915_handle_error(struct drm_device *dev, bool wedged)
2141 {
2142         struct drm_i915_private *dev_priv = dev->dev_private;
2143
2144         i915_capture_error_state(dev);
2145         i915_report_and_clear_eir(dev);
2146
2147         if (wedged) {
2148                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2149                                 &dev_priv->gpu_error.reset_counter);
2150
2151                 /*
2152                  * Wakeup waiting processes so that the reset work function
2153                  * i915_error_work_func doesn't deadlock trying to grab various
2154                  * locks. By bumping the reset counter first, the woken
2155                  * processes will see a reset in progress and back off,
2156                  * releasing their locks and then wait for the reset completion.
2157                  * We must do this for _all_ gpu waiters that might hold locks
2158                  * that the reset work needs to acquire.
2159                  *
2160                  * Note: The wake_up serves as the required memory barrier to
2161                  * ensure that the waiters see the updated value of the reset
2162                  * counter atomic_t.
2163                  */
2164                 i915_error_wake_up(dev_priv, false);
2165         }
2166
2167         /*
2168          * Our reset work can grab modeset locks (since it needs to reset the
2169          * state of outstanding pagelips). Hence it must not be run on our own
2170          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2171          * code will deadlock.
2172          */
2173         schedule_work(&dev_priv->gpu_error.work);
2174 }
2175
2176 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2177 {
2178         drm_i915_private_t *dev_priv = dev->dev_private;
2179         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181         struct drm_i915_gem_object *obj;
2182         struct intel_unpin_work *work;
2183         unsigned long flags;
2184         bool stall_detected;
2185
2186         /* Ignore early vblank irqs */
2187         if (intel_crtc == NULL)
2188                 return;
2189
2190         spin_lock_irqsave(&dev->event_lock, flags);
2191         work = intel_crtc->unpin_work;
2192
2193         if (work == NULL ||
2194             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2195             !work->enable_stall_check) {
2196                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2197                 spin_unlock_irqrestore(&dev->event_lock, flags);
2198                 return;
2199         }
2200
2201         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2202         obj = work->pending_flip_obj;
2203         if (INTEL_INFO(dev)->gen >= 4) {
2204                 int dspsurf = DSPSURF(intel_crtc->plane);
2205                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2206                                         i915_gem_obj_ggtt_offset(obj);
2207         } else {
2208                 int dspaddr = DSPADDR(intel_crtc->plane);
2209                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2210                                                         crtc->y * crtc->fb->pitches[0] +
2211                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2212         }
2213
2214         spin_unlock_irqrestore(&dev->event_lock, flags);
2215
2216         if (stall_detected) {
2217                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2218                 intel_prepare_page_flip(dev, intel_crtc->plane);
2219         }
2220 }
2221
2222 /* Called from drm generic code, passed 'crtc' which
2223  * we use as a pipe index
2224  */
2225 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2226 {
2227         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2228         unsigned long irqflags;
2229
2230         if (!i915_pipe_enabled(dev, pipe))
2231                 return -EINVAL;
2232
2233         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2234         if (INTEL_INFO(dev)->gen >= 4)
2235                 i915_enable_pipestat(dev_priv, pipe,
2236                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
2237         else
2238                 i915_enable_pipestat(dev_priv, pipe,
2239                                      PIPE_VBLANK_INTERRUPT_ENABLE);
2240
2241         /* maintain vblank delivery even in deep C-states */
2242         if (dev_priv->info->gen == 3)
2243                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2244         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2245
2246         return 0;
2247 }
2248
2249 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2250 {
2251         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2252         unsigned long irqflags;
2253         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2254                                                      DE_PIPE_VBLANK(pipe);
2255
2256         if (!i915_pipe_enabled(dev, pipe))
2257                 return -EINVAL;
2258
2259         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2260         ironlake_enable_display_irq(dev_priv, bit);
2261         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2262
2263         return 0;
2264 }
2265
2266 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2267 {
2268         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2269         unsigned long irqflags;
2270         u32 imr;
2271
2272         if (!i915_pipe_enabled(dev, pipe))
2273                 return -EINVAL;
2274
2275         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2276         imr = I915_READ(VLV_IMR);
2277         if (pipe == PIPE_A)
2278                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2279         else
2280                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2281         I915_WRITE(VLV_IMR, imr);
2282         i915_enable_pipestat(dev_priv, pipe,
2283                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
2284         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2285
2286         return 0;
2287 }
2288
2289 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2290 {
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292         unsigned long irqflags;
2293
2294         if (!i915_pipe_enabled(dev, pipe))
2295                 return -EINVAL;
2296
2297         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2298         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2299         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2300         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2301         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2302         return 0;
2303 }
2304
2305 /* Called from drm generic code, passed 'crtc' which
2306  * we use as a pipe index
2307  */
2308 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2309 {
2310         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2311         unsigned long irqflags;
2312
2313         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2314         if (dev_priv->info->gen == 3)
2315                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2316
2317         i915_disable_pipestat(dev_priv, pipe,
2318                               PIPE_VBLANK_INTERRUPT_ENABLE |
2319                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2320         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2321 }
2322
2323 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2324 {
2325         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2326         unsigned long irqflags;
2327         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2328                                                      DE_PIPE_VBLANK(pipe);
2329
2330         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2331         ironlake_disable_display_irq(dev_priv, bit);
2332         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2333 }
2334
2335 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2336 {
2337         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2338         unsigned long irqflags;
2339         u32 imr;
2340
2341         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2342         i915_disable_pipestat(dev_priv, pipe,
2343                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2344         imr = I915_READ(VLV_IMR);
2345         if (pipe == PIPE_A)
2346                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2347         else
2348                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2349         I915_WRITE(VLV_IMR, imr);
2350         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2351 }
2352
2353 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2354 {
2355         struct drm_i915_private *dev_priv = dev->dev_private;
2356         unsigned long irqflags;
2357
2358         if (!i915_pipe_enabled(dev, pipe))
2359                 return;
2360
2361         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2362         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2363         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2364         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2365         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2366 }
2367
2368 static u32
2369 ring_last_seqno(struct intel_ring_buffer *ring)
2370 {
2371         return list_entry(ring->request_list.prev,
2372                           struct drm_i915_gem_request, list)->seqno;
2373 }
2374
2375 static bool
2376 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2377 {
2378         return (list_empty(&ring->request_list) ||
2379                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2380 }
2381
2382 static struct intel_ring_buffer *
2383 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2384 {
2385         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2386         u32 cmd, ipehr, acthd, acthd_min;
2387
2388         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2389         if ((ipehr & ~(0x3 << 16)) !=
2390             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2391                 return NULL;
2392
2393         /* ACTHD is likely pointing to the dword after the actual command,
2394          * so scan backwards until we find the MBOX.
2395          */
2396         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2397         acthd_min = max((int)acthd - 3 * 4, 0);
2398         do {
2399                 cmd = ioread32(ring->virtual_start + acthd);
2400                 if (cmd == ipehr)
2401                         break;
2402
2403                 acthd -= 4;
2404                 if (acthd < acthd_min)
2405                         return NULL;
2406         } while (1);
2407
2408         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2409         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2410 }
2411
2412 static int semaphore_passed(struct intel_ring_buffer *ring)
2413 {
2414         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2415         struct intel_ring_buffer *signaller;
2416         u32 seqno, ctl;
2417
2418         ring->hangcheck.deadlock = true;
2419
2420         signaller = semaphore_waits_for(ring, &seqno);
2421         if (signaller == NULL || signaller->hangcheck.deadlock)
2422                 return -1;
2423
2424         /* cursory check for an unkickable deadlock */
2425         ctl = I915_READ_CTL(signaller);
2426         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2427                 return -1;
2428
2429         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2430 }
2431
2432 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2433 {
2434         struct intel_ring_buffer *ring;
2435         int i;
2436
2437         for_each_ring(ring, dev_priv, i)
2438                 ring->hangcheck.deadlock = false;
2439 }
2440
2441 static enum intel_ring_hangcheck_action
2442 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2443 {
2444         struct drm_device *dev = ring->dev;
2445         struct drm_i915_private *dev_priv = dev->dev_private;
2446         u32 tmp;
2447
2448         if (ring->hangcheck.acthd != acthd)
2449                 return HANGCHECK_ACTIVE;
2450
2451         if (IS_GEN2(dev))
2452                 return HANGCHECK_HUNG;
2453
2454         /* Is the chip hanging on a WAIT_FOR_EVENT?
2455          * If so we can simply poke the RB_WAIT bit
2456          * and break the hang. This should work on
2457          * all but the second generation chipsets.
2458          */
2459         tmp = I915_READ_CTL(ring);
2460         if (tmp & RING_WAIT) {
2461                 DRM_ERROR("Kicking stuck wait on %s\n",
2462                           ring->name);
2463                 i915_handle_error(dev, false);
2464                 I915_WRITE_CTL(ring, tmp);
2465                 return HANGCHECK_KICK;
2466         }
2467
2468         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2469                 switch (semaphore_passed(ring)) {
2470                 default:
2471                         return HANGCHECK_HUNG;
2472                 case 1:
2473                         DRM_ERROR("Kicking stuck semaphore on %s\n",
2474                                   ring->name);
2475                         i915_handle_error(dev, false);
2476                         I915_WRITE_CTL(ring, tmp);
2477                         return HANGCHECK_KICK;
2478                 case 0:
2479                         return HANGCHECK_WAIT;
2480                 }
2481         }
2482
2483         return HANGCHECK_HUNG;
2484 }
2485
2486 /**
2487  * This is called when the chip hasn't reported back with completed
2488  * batchbuffers in a long time. We keep track per ring seqno progress and
2489  * if there are no progress, hangcheck score for that ring is increased.
2490  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2491  * we kick the ring. If we see no progress on three subsequent calls
2492  * we assume chip is wedged and try to fix it by resetting the chip.
2493  */
2494 static void i915_hangcheck_elapsed(unsigned long data)
2495 {
2496         struct drm_device *dev = (struct drm_device *)data;
2497         drm_i915_private_t *dev_priv = dev->dev_private;
2498         struct intel_ring_buffer *ring;
2499         int i;
2500         int busy_count = 0, rings_hung = 0;
2501         bool stuck[I915_NUM_RINGS] = { 0 };
2502 #define BUSY 1
2503 #define KICK 5
2504 #define HUNG 20
2505 #define FIRE 30
2506
2507         if (!i915_enable_hangcheck)
2508                 return;
2509
2510         for_each_ring(ring, dev_priv, i) {
2511                 u32 seqno, acthd;
2512                 bool busy = true;
2513
2514                 semaphore_clear_deadlocks(dev_priv);
2515
2516                 seqno = ring->get_seqno(ring, false);
2517                 acthd = intel_ring_get_active_head(ring);
2518
2519                 if (ring->hangcheck.seqno == seqno) {
2520                         if (ring_idle(ring, seqno)) {
2521                                 ring->hangcheck.action = HANGCHECK_IDLE;
2522
2523                                 if (waitqueue_active(&ring->irq_queue)) {
2524                                         /* Issue a wake-up to catch stuck h/w. */
2525                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2526                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2527                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2528                                                                   ring->name);
2529                                                 else
2530                                                         DRM_INFO("Fake missed irq on %s\n",
2531                                                                  ring->name);
2532                                                 wake_up_all(&ring->irq_queue);
2533                                         }
2534                                         /* Safeguard against driver failure */
2535                                         ring->hangcheck.score += BUSY;
2536                                 } else
2537                                         busy = false;
2538                         } else {
2539                                 /* We always increment the hangcheck score
2540                                  * if the ring is busy and still processing
2541                                  * the same request, so that no single request
2542                                  * can run indefinitely (such as a chain of
2543                                  * batches). The only time we do not increment
2544                                  * the hangcheck score on this ring, if this
2545                                  * ring is in a legitimate wait for another
2546                                  * ring. In that case the waiting ring is a
2547                                  * victim and we want to be sure we catch the
2548                                  * right culprit. Then every time we do kick
2549                                  * the ring, add a small increment to the
2550                                  * score so that we can catch a batch that is
2551                                  * being repeatedly kicked and so responsible
2552                                  * for stalling the machine.
2553                                  */
2554                                 ring->hangcheck.action = ring_stuck(ring,
2555                                                                     acthd);
2556
2557                                 switch (ring->hangcheck.action) {
2558                                 case HANGCHECK_IDLE:
2559                                 case HANGCHECK_WAIT:
2560                                         break;
2561                                 case HANGCHECK_ACTIVE:
2562                                         ring->hangcheck.score += BUSY;
2563                                         break;
2564                                 case HANGCHECK_KICK:
2565                                         ring->hangcheck.score += KICK;
2566                                         break;
2567                                 case HANGCHECK_HUNG:
2568                                         ring->hangcheck.score += HUNG;
2569                                         stuck[i] = true;
2570                                         break;
2571                                 }
2572                         }
2573                 } else {
2574                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2575
2576                         /* Gradually reduce the count so that we catch DoS
2577                          * attempts across multiple batches.
2578                          */
2579                         if (ring->hangcheck.score > 0)
2580                                 ring->hangcheck.score--;
2581                 }
2582
2583                 ring->hangcheck.seqno = seqno;
2584                 ring->hangcheck.acthd = acthd;
2585                 busy_count += busy;
2586         }
2587
2588         for_each_ring(ring, dev_priv, i) {
2589                 if (ring->hangcheck.score > FIRE) {
2590                         DRM_INFO("%s on %s\n",
2591                                  stuck[i] ? "stuck" : "no progress",
2592                                  ring->name);
2593                         rings_hung++;
2594                 }
2595         }
2596
2597         if (rings_hung)
2598                 return i915_handle_error(dev, true);
2599
2600         if (busy_count)
2601                 /* Reset timer case chip hangs without another request
2602                  * being added */
2603                 i915_queue_hangcheck(dev);
2604 }
2605
2606 void i915_queue_hangcheck(struct drm_device *dev)
2607 {
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         if (!i915_enable_hangcheck)
2610                 return;
2611
2612         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2613                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2614 }
2615
2616 static void ibx_irq_preinstall(struct drm_device *dev)
2617 {
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619
2620         if (HAS_PCH_NOP(dev))
2621                 return;
2622
2623         /* south display irq */
2624         I915_WRITE(SDEIMR, 0xffffffff);
2625         /*
2626          * SDEIER is also touched by the interrupt handler to work around missed
2627          * PCH interrupts. Hence we can't update it after the interrupt handler
2628          * is enabled - instead we unconditionally enable all PCH interrupt
2629          * sources here, but then only unmask them as needed with SDEIMR.
2630          */
2631         I915_WRITE(SDEIER, 0xffffffff);
2632         POSTING_READ(SDEIER);
2633 }
2634
2635 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2636 {
2637         struct drm_i915_private *dev_priv = dev->dev_private;
2638
2639         /* and GT */
2640         I915_WRITE(GTIMR, 0xffffffff);
2641         I915_WRITE(GTIER, 0x0);
2642         POSTING_READ(GTIER);
2643
2644         if (INTEL_INFO(dev)->gen >= 6) {
2645                 /* and PM */
2646                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2647                 I915_WRITE(GEN6_PMIER, 0x0);
2648                 POSTING_READ(GEN6_PMIER);
2649         }
2650 }
2651
2652 /* drm_dma.h hooks
2653 */
2654 static void ironlake_irq_preinstall(struct drm_device *dev)
2655 {
2656         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2657
2658         atomic_set(&dev_priv->irq_received, 0);
2659
2660         I915_WRITE(HWSTAM, 0xeffe);
2661
2662         I915_WRITE(DEIMR, 0xffffffff);
2663         I915_WRITE(DEIER, 0x0);
2664         POSTING_READ(DEIER);
2665
2666         gen5_gt_irq_preinstall(dev);
2667
2668         ibx_irq_preinstall(dev);
2669 }
2670
2671 static void valleyview_irq_preinstall(struct drm_device *dev)
2672 {
2673         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2674         int pipe;
2675
2676         atomic_set(&dev_priv->irq_received, 0);
2677
2678         /* VLV magic */
2679         I915_WRITE(VLV_IMR, 0);
2680         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2681         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2682         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2683
2684         /* and GT */
2685         I915_WRITE(GTIIR, I915_READ(GTIIR));
2686         I915_WRITE(GTIIR, I915_READ(GTIIR));
2687
2688         gen5_gt_irq_preinstall(dev);
2689
2690         I915_WRITE(DPINVGTT, 0xff);
2691
2692         I915_WRITE(PORT_HOTPLUG_EN, 0);
2693         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2694         for_each_pipe(pipe)
2695                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2696         I915_WRITE(VLV_IIR, 0xffffffff);
2697         I915_WRITE(VLV_IMR, 0xffffffff);
2698         I915_WRITE(VLV_IER, 0x0);
2699         POSTING_READ(VLV_IER);
2700 }
2701
2702 static void gen8_irq_preinstall(struct drm_device *dev)
2703 {
2704         struct drm_i915_private *dev_priv = dev->dev_private;
2705         int pipe;
2706
2707         atomic_set(&dev_priv->irq_received, 0);
2708
2709         I915_WRITE(GEN8_MASTER_IRQ, 0);
2710         POSTING_READ(GEN8_MASTER_IRQ);
2711
2712         /* IIR can theoretically queue up two events. Be paranoid */
2713 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2714                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2715                 POSTING_READ(GEN8_##type##_IMR(which)); \
2716                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2717                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2718                 POSTING_READ(GEN8_##type##_IIR(which)); \
2719                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2720         } while (0)
2721
2722 #define GEN8_IRQ_INIT(type) do { \
2723                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2724                 POSTING_READ(GEN8_##type##_IMR); \
2725                 I915_WRITE(GEN8_##type##_IER, 0); \
2726                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2727                 POSTING_READ(GEN8_##type##_IIR); \
2728                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2729         } while (0)
2730
2731         GEN8_IRQ_INIT_NDX(GT, 0);
2732         GEN8_IRQ_INIT_NDX(GT, 1);
2733         GEN8_IRQ_INIT_NDX(GT, 2);
2734         GEN8_IRQ_INIT_NDX(GT, 3);
2735
2736         for_each_pipe(pipe) {
2737                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2738         }
2739
2740         GEN8_IRQ_INIT(DE_PORT);
2741         GEN8_IRQ_INIT(DE_MISC);
2742         GEN8_IRQ_INIT(PCU);
2743 #undef GEN8_IRQ_INIT
2744 #undef GEN8_IRQ_INIT_NDX
2745
2746         POSTING_READ(GEN8_PCU_IIR);
2747
2748         ibx_irq_preinstall(dev);
2749 }
2750
2751 static void ibx_hpd_irq_setup(struct drm_device *dev)
2752 {
2753         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2754         struct drm_mode_config *mode_config = &dev->mode_config;
2755         struct intel_encoder *intel_encoder;
2756         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2757
2758         if (HAS_PCH_IBX(dev)) {
2759                 hotplug_irqs = SDE_HOTPLUG_MASK;
2760                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2761                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2762                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2763         } else {
2764                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2765                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2766                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2767                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2768         }
2769
2770         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2771
2772         /*
2773          * Enable digital hotplug on the PCH, and configure the DP short pulse
2774          * duration to 2ms (which is the minimum in the Display Port spec)
2775          *
2776          * This register is the same on all known PCH chips.
2777          */
2778         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2779         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2780         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2781         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2782         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2783         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2784 }
2785
2786 static void ibx_irq_postinstall(struct drm_device *dev)
2787 {
2788         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2789         u32 mask;
2790
2791         if (HAS_PCH_NOP(dev))
2792                 return;
2793
2794         if (HAS_PCH_IBX(dev)) {
2795                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
2796         } else {
2797                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2798
2799                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2800         }
2801
2802         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2803         I915_WRITE(SDEIMR, ~mask);
2804 }
2805
2806 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2807 {
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         u32 pm_irqs, gt_irqs;
2810
2811         pm_irqs = gt_irqs = 0;
2812
2813         dev_priv->gt_irq_mask = ~0;
2814         if (HAS_L3_DPF(dev)) {
2815                 /* L3 parity interrupt is always unmasked. */
2816                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2817                 gt_irqs |= GT_PARITY_ERROR(dev);
2818         }
2819
2820         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2821         if (IS_GEN5(dev)) {
2822                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2823                            ILK_BSD_USER_INTERRUPT;
2824         } else {
2825                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2826         }
2827
2828         I915_WRITE(GTIIR, I915_READ(GTIIR));
2829         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2830         I915_WRITE(GTIER, gt_irqs);
2831         POSTING_READ(GTIER);
2832
2833         if (INTEL_INFO(dev)->gen >= 6) {
2834                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2835
2836                 if (HAS_VEBOX(dev))
2837                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2838
2839                 dev_priv->pm_irq_mask = 0xffffffff;
2840                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2841                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2842                 I915_WRITE(GEN6_PMIER, pm_irqs);
2843                 POSTING_READ(GEN6_PMIER);
2844         }
2845 }
2846
2847 static int ironlake_irq_postinstall(struct drm_device *dev)
2848 {
2849         unsigned long irqflags;
2850         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2851         u32 display_mask, extra_mask;
2852
2853         if (INTEL_INFO(dev)->gen >= 7) {
2854                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2855                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2856                                 DE_PLANEB_FLIP_DONE_IVB |
2857                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
2858                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2859                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
2860
2861                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2862         } else {
2863                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2864                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2865                                 DE_AUX_CHANNEL_A |
2866                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2867                                 DE_POISON);
2868                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
2869                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
2870         }
2871
2872         dev_priv->irq_mask = ~display_mask;
2873
2874         /* should always can generate irq */
2875         I915_WRITE(DEIIR, I915_READ(DEIIR));
2876         I915_WRITE(DEIMR, dev_priv->irq_mask);
2877         I915_WRITE(DEIER, display_mask | extra_mask);
2878         POSTING_READ(DEIER);
2879
2880         gen5_gt_irq_postinstall(dev);
2881
2882         ibx_irq_postinstall(dev);
2883
2884         if (IS_IRONLAKE_M(dev)) {
2885                 /* Enable PCU event interrupts
2886                  *
2887                  * spinlocking not required here for correctness since interrupt
2888                  * setup is guaranteed to run in single-threaded context. But we
2889                  * need it to make the assert_spin_locked happy. */
2890                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2891                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2892                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2893         }
2894
2895         return 0;
2896 }
2897
2898 static int valleyview_irq_postinstall(struct drm_device *dev)
2899 {
2900         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2901         u32 enable_mask;
2902         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2903                 PIPE_CRC_DONE_ENABLE;
2904         unsigned long irqflags;
2905
2906         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2907         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2908                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2909                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2910                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2911
2912         /*
2913          *Leave vblank interrupts masked initially.  enable/disable will
2914          * toggle them based on usage.
2915          */
2916         dev_priv->irq_mask = (~enable_mask) |
2917                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2918                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2919
2920         I915_WRITE(PORT_HOTPLUG_EN, 0);
2921         POSTING_READ(PORT_HOTPLUG_EN);
2922
2923         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2924         I915_WRITE(VLV_IER, enable_mask);
2925         I915_WRITE(VLV_IIR, 0xffffffff);
2926         I915_WRITE(PIPESTAT(0), 0xffff);
2927         I915_WRITE(PIPESTAT(1), 0xffff);
2928         POSTING_READ(VLV_IER);
2929
2930         /* Interrupt setup is already guaranteed to be single-threaded, this is
2931          * just to make the assert_spin_locked check happy. */
2932         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2933         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2934         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2935         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2936         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2937
2938         I915_WRITE(VLV_IIR, 0xffffffff);
2939         I915_WRITE(VLV_IIR, 0xffffffff);
2940
2941         gen5_gt_irq_postinstall(dev);
2942
2943         /* ack & enable invalid PTE error interrupts */
2944 #if 0 /* FIXME: add support to irq handler for checking these bits */
2945         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2946         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2947 #endif
2948
2949         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2950
2951         return 0;
2952 }
2953
2954 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2955 {
2956         int i;
2957
2958         /* These are interrupts we'll toggle with the ring mask register */
2959         uint32_t gt_interrupts[] = {
2960                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2961                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2962                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2963                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2964                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2965                 0,
2966                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2967                 };
2968
2969         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2970                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2971                 if (tmp)
2972                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2973                                   i, tmp);
2974                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2975                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2976         }
2977         POSTING_READ(GEN8_GT_IER(0));
2978 }
2979
2980 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2981 {
2982         struct drm_device *dev = dev_priv->dev;
2983         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2984                 GEN8_PIPE_CDCLK_CRC_DONE |
2985                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2986         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
2987                 GEN8_PIPE_FIFO_UNDERRUN;
2988         int pipe;
2989         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2990         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2991         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
2992
2993         for_each_pipe(pipe) {
2994                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2995                 if (tmp)
2996                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2997                                   pipe, tmp);
2998                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2999                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3000         }
3001         POSTING_READ(GEN8_DE_PIPE_ISR(0));
3002
3003         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3004         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3005         POSTING_READ(GEN8_DE_PORT_IER);
3006 }
3007
3008 static int gen8_irq_postinstall(struct drm_device *dev)
3009 {
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011
3012         gen8_gt_irq_postinstall(dev_priv);
3013         gen8_de_irq_postinstall(dev_priv);
3014
3015         ibx_irq_postinstall(dev);
3016
3017         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3018         POSTING_READ(GEN8_MASTER_IRQ);
3019
3020         return 0;
3021 }
3022
3023 static void gen8_irq_uninstall(struct drm_device *dev)
3024 {
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         int pipe;
3027
3028         if (!dev_priv)
3029                 return;
3030
3031         atomic_set(&dev_priv->irq_received, 0);
3032
3033         I915_WRITE(GEN8_MASTER_IRQ, 0);
3034
3035 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3036                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3037                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3038                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3039         } while (0)
3040
3041 #define GEN8_IRQ_FINI(type) do { \
3042                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3043                 I915_WRITE(GEN8_##type##_IER, 0); \
3044                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3045         } while (0)
3046
3047         GEN8_IRQ_FINI_NDX(GT, 0);
3048         GEN8_IRQ_FINI_NDX(GT, 1);
3049         GEN8_IRQ_FINI_NDX(GT, 2);
3050         GEN8_IRQ_FINI_NDX(GT, 3);
3051
3052         for_each_pipe(pipe) {
3053                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3054         }
3055
3056         GEN8_IRQ_FINI(DE_PORT);
3057         GEN8_IRQ_FINI(DE_MISC);
3058         GEN8_IRQ_FINI(PCU);
3059 #undef GEN8_IRQ_FINI
3060 #undef GEN8_IRQ_FINI_NDX
3061
3062         POSTING_READ(GEN8_PCU_IIR);
3063 }
3064
3065 static void valleyview_irq_uninstall(struct drm_device *dev)
3066 {
3067         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3068         int pipe;
3069
3070         if (!dev_priv)
3071                 return;
3072
3073         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3074
3075         for_each_pipe(pipe)
3076                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3077
3078         I915_WRITE(HWSTAM, 0xffffffff);
3079         I915_WRITE(PORT_HOTPLUG_EN, 0);
3080         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3081         for_each_pipe(pipe)
3082                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3083         I915_WRITE(VLV_IIR, 0xffffffff);
3084         I915_WRITE(VLV_IMR, 0xffffffff);
3085         I915_WRITE(VLV_IER, 0x0);
3086         POSTING_READ(VLV_IER);
3087 }
3088
3089 static void ironlake_irq_uninstall(struct drm_device *dev)
3090 {
3091         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3092
3093         if (!dev_priv)
3094                 return;
3095
3096         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3097
3098         I915_WRITE(HWSTAM, 0xffffffff);
3099
3100         I915_WRITE(DEIMR, 0xffffffff);
3101         I915_WRITE(DEIER, 0x0);
3102         I915_WRITE(DEIIR, I915_READ(DEIIR));
3103         if (IS_GEN7(dev))
3104                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3105
3106         I915_WRITE(GTIMR, 0xffffffff);
3107         I915_WRITE(GTIER, 0x0);
3108         I915_WRITE(GTIIR, I915_READ(GTIIR));
3109
3110         if (HAS_PCH_NOP(dev))
3111                 return;
3112
3113         I915_WRITE(SDEIMR, 0xffffffff);
3114         I915_WRITE(SDEIER, 0x0);
3115         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3116         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3117                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3118 }
3119
3120 static void i8xx_irq_preinstall(struct drm_device * dev)
3121 {
3122         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3123         int pipe;
3124
3125         atomic_set(&dev_priv->irq_received, 0);
3126
3127         for_each_pipe(pipe)
3128                 I915_WRITE(PIPESTAT(pipe), 0);
3129         I915_WRITE16(IMR, 0xffff);
3130         I915_WRITE16(IER, 0x0);
3131         POSTING_READ16(IER);
3132 }
3133
3134 static int i8xx_irq_postinstall(struct drm_device *dev)
3135 {
3136         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3137         unsigned long irqflags;
3138
3139         I915_WRITE16(EMR,
3140                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3141
3142         /* Unmask the interrupts that we always want on. */
3143         dev_priv->irq_mask =
3144                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3145                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3146                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3147                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3148                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3149         I915_WRITE16(IMR, dev_priv->irq_mask);
3150
3151         I915_WRITE16(IER,
3152                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3153                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3154                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3155                      I915_USER_INTERRUPT);
3156         POSTING_READ16(IER);
3157
3158         /* Interrupt setup is already guaranteed to be single-threaded, this is
3159          * just to make the assert_spin_locked check happy. */
3160         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3161         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3162         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3163         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3164
3165         return 0;
3166 }
3167
3168 /*
3169  * Returns true when a page flip has completed.
3170  */
3171 static bool i8xx_handle_vblank(struct drm_device *dev,
3172                                int plane, int pipe, u32 iir)
3173 {
3174         drm_i915_private_t *dev_priv = dev->dev_private;
3175         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3176
3177         if (!drm_handle_vblank(dev, pipe))
3178                 return false;
3179
3180         if ((iir & flip_pending) == 0)
3181                 return false;
3182
3183         intel_prepare_page_flip(dev, plane);
3184
3185         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3186          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3187          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3188          * the flip is completed (no longer pending). Since this doesn't raise
3189          * an interrupt per se, we watch for the change at vblank.
3190          */
3191         if (I915_READ16(ISR) & flip_pending)
3192                 return false;
3193
3194         intel_finish_page_flip(dev, pipe);
3195
3196         return true;
3197 }
3198
3199 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3200 {
3201         struct drm_device *dev = (struct drm_device *) arg;
3202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3203         u16 iir, new_iir;
3204         u32 pipe_stats[2];
3205         unsigned long irqflags;
3206         int pipe;
3207         u16 flip_mask =
3208                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3209                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3210
3211         atomic_inc(&dev_priv->irq_received);
3212
3213         iir = I915_READ16(IIR);
3214         if (iir == 0)
3215                 return IRQ_NONE;
3216
3217         while (iir & ~flip_mask) {
3218                 /* Can't rely on pipestat interrupt bit in iir as it might
3219                  * have been cleared after the pipestat interrupt was received.
3220                  * It doesn't set the bit in iir again, but it still produces
3221                  * interrupts (for non-MSI).
3222                  */
3223                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3224                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3225                         i915_handle_error(dev, false);
3226
3227                 for_each_pipe(pipe) {
3228                         int reg = PIPESTAT(pipe);
3229                         pipe_stats[pipe] = I915_READ(reg);
3230
3231                         /*
3232                          * Clear the PIPE*STAT regs before the IIR
3233                          */
3234                         if (pipe_stats[pipe] & 0x8000ffff) {
3235                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3236                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3237                                                          pipe_name(pipe));
3238                                 I915_WRITE(reg, pipe_stats[pipe]);
3239                         }
3240                 }
3241                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3242
3243                 I915_WRITE16(IIR, iir & ~flip_mask);
3244                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3245
3246                 i915_update_dri1_breadcrumb(dev);
3247
3248                 if (iir & I915_USER_INTERRUPT)
3249                         notify_ring(dev, &dev_priv->ring[RCS]);
3250
3251                 for_each_pipe(pipe) {
3252                         int plane = pipe;
3253                         if (HAS_FBC(dev))
3254                                 plane = !plane;
3255
3256                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3257                             i8xx_handle_vblank(dev, plane, pipe, iir))
3258                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3259
3260                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3261                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3262                 }
3263
3264                 iir = new_iir;
3265         }
3266
3267         return IRQ_HANDLED;
3268 }
3269
3270 static void i8xx_irq_uninstall(struct drm_device * dev)
3271 {
3272         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3273         int pipe;
3274
3275         for_each_pipe(pipe) {
3276                 /* Clear enable bits; then clear status bits */
3277                 I915_WRITE(PIPESTAT(pipe), 0);
3278                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3279         }
3280         I915_WRITE16(IMR, 0xffff);
3281         I915_WRITE16(IER, 0x0);
3282         I915_WRITE16(IIR, I915_READ16(IIR));
3283 }
3284
3285 static void i915_irq_preinstall(struct drm_device * dev)
3286 {
3287         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3288         int pipe;
3289
3290         atomic_set(&dev_priv->irq_received, 0);
3291
3292         if (I915_HAS_HOTPLUG(dev)) {
3293                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3294                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3295         }
3296
3297         I915_WRITE16(HWSTAM, 0xeffe);
3298         for_each_pipe(pipe)
3299                 I915_WRITE(PIPESTAT(pipe), 0);
3300         I915_WRITE(IMR, 0xffffffff);
3301         I915_WRITE(IER, 0x0);
3302         POSTING_READ(IER);
3303 }
3304
3305 static int i915_irq_postinstall(struct drm_device *dev)
3306 {
3307         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3308         u32 enable_mask;
3309         unsigned long irqflags;
3310
3311         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3312
3313         /* Unmask the interrupts that we always want on. */
3314         dev_priv->irq_mask =
3315                 ~(I915_ASLE_INTERRUPT |
3316                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3317                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3318                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3319                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3320                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3321
3322         enable_mask =
3323                 I915_ASLE_INTERRUPT |
3324                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3325                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3326                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3327                 I915_USER_INTERRUPT;
3328
3329         if (I915_HAS_HOTPLUG(dev)) {
3330                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3331                 POSTING_READ(PORT_HOTPLUG_EN);
3332
3333                 /* Enable in IER... */
3334                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3335                 /* and unmask in IMR */
3336                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3337         }
3338
3339         I915_WRITE(IMR, dev_priv->irq_mask);
3340         I915_WRITE(IER, enable_mask);
3341         POSTING_READ(IER);
3342
3343         i915_enable_asle_pipestat(dev);
3344
3345         /* Interrupt setup is already guaranteed to be single-threaded, this is
3346          * just to make the assert_spin_locked check happy. */
3347         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3348         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3349         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3350         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3351
3352         return 0;
3353 }
3354
3355 /*
3356  * Returns true when a page flip has completed.
3357  */
3358 static bool i915_handle_vblank(struct drm_device *dev,
3359                                int plane, int pipe, u32 iir)
3360 {
3361         drm_i915_private_t *dev_priv = dev->dev_private;
3362         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3363
3364         if (!drm_handle_vblank(dev, pipe))
3365                 return false;
3366
3367         if ((iir & flip_pending) == 0)
3368                 return false;
3369
3370         intel_prepare_page_flip(dev, plane);
3371
3372         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3373          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3374          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3375          * the flip is completed (no longer pending). Since this doesn't raise
3376          * an interrupt per se, we watch for the change at vblank.
3377          */
3378         if (I915_READ(ISR) & flip_pending)
3379                 return false;
3380
3381         intel_finish_page_flip(dev, pipe);
3382
3383         return true;
3384 }
3385
3386 static irqreturn_t i915_irq_handler(int irq, void *arg)
3387 {
3388         struct drm_device *dev = (struct drm_device *) arg;
3389         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3390         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3391         unsigned long irqflags;
3392         u32 flip_mask =
3393                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3394                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3395         int pipe, ret = IRQ_NONE;
3396
3397         atomic_inc(&dev_priv->irq_received);
3398
3399         iir = I915_READ(IIR);
3400         do {
3401                 bool irq_received = (iir & ~flip_mask) != 0;
3402                 bool blc_event = false;
3403
3404                 /* Can't rely on pipestat interrupt bit in iir as it might
3405                  * have been cleared after the pipestat interrupt was received.
3406                  * It doesn't set the bit in iir again, but it still produces
3407                  * interrupts (for non-MSI).
3408                  */
3409                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3410                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3411                         i915_handle_error(dev, false);
3412
3413                 for_each_pipe(pipe) {
3414                         int reg = PIPESTAT(pipe);
3415                         pipe_stats[pipe] = I915_READ(reg);
3416
3417                         /* Clear the PIPE*STAT regs before the IIR */
3418                         if (pipe_stats[pipe] & 0x8000ffff) {
3419                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3420                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3421                                                          pipe_name(pipe));
3422                                 I915_WRITE(reg, pipe_stats[pipe]);
3423                                 irq_received = true;
3424                         }
3425                 }
3426                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3427
3428                 if (!irq_received)
3429                         break;
3430
3431                 /* Consume port.  Then clear IIR or we'll miss events */
3432                 if ((I915_HAS_HOTPLUG(dev)) &&
3433                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3434                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3435                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3436
3437                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3438                                   hotplug_status);
3439
3440                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3441
3442                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3443                         POSTING_READ(PORT_HOTPLUG_STAT);
3444                 }
3445
3446                 I915_WRITE(IIR, iir & ~flip_mask);
3447                 new_iir = I915_READ(IIR); /* Flush posted writes */
3448
3449                 if (iir & I915_USER_INTERRUPT)
3450                         notify_ring(dev, &dev_priv->ring[RCS]);
3451
3452                 for_each_pipe(pipe) {
3453                         int plane = pipe;
3454                         if (HAS_FBC(dev))
3455                                 plane = !plane;
3456
3457                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3458                             i915_handle_vblank(dev, plane, pipe, iir))
3459                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3460
3461                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3462                                 blc_event = true;
3463
3464                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3465                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3466                 }
3467
3468                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3469                         intel_opregion_asle_intr(dev);
3470
3471                 /* With MSI, interrupts are only generated when iir
3472                  * transitions from zero to nonzero.  If another bit got
3473                  * set while we were handling the existing iir bits, then
3474                  * we would never get another interrupt.
3475                  *
3476                  * This is fine on non-MSI as well, as if we hit this path
3477                  * we avoid exiting the interrupt handler only to generate
3478                  * another one.
3479                  *
3480                  * Note that for MSI this could cause a stray interrupt report
3481                  * if an interrupt landed in the time between writing IIR and
3482                  * the posting read.  This should be rare enough to never
3483                  * trigger the 99% of 100,000 interrupts test for disabling
3484                  * stray interrupts.
3485                  */
3486                 ret = IRQ_HANDLED;
3487                 iir = new_iir;
3488         } while (iir & ~flip_mask);
3489
3490         i915_update_dri1_breadcrumb(dev);
3491
3492         return ret;
3493 }
3494
3495 static void i915_irq_uninstall(struct drm_device * dev)
3496 {
3497         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3498         int pipe;
3499
3500         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3501
3502         if (I915_HAS_HOTPLUG(dev)) {
3503                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3504                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3505         }
3506
3507         I915_WRITE16(HWSTAM, 0xffff);
3508         for_each_pipe(pipe) {
3509                 /* Clear enable bits; then clear status bits */
3510                 I915_WRITE(PIPESTAT(pipe), 0);
3511                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3512         }
3513         I915_WRITE(IMR, 0xffffffff);
3514         I915_WRITE(IER, 0x0);
3515
3516         I915_WRITE(IIR, I915_READ(IIR));
3517 }
3518
3519 static void i965_irq_preinstall(struct drm_device * dev)
3520 {
3521         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3522         int pipe;
3523
3524         atomic_set(&dev_priv->irq_received, 0);
3525
3526         I915_WRITE(PORT_HOTPLUG_EN, 0);
3527         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3528
3529         I915_WRITE(HWSTAM, 0xeffe);
3530         for_each_pipe(pipe)
3531                 I915_WRITE(PIPESTAT(pipe), 0);
3532         I915_WRITE(IMR, 0xffffffff);
3533         I915_WRITE(IER, 0x0);
3534         POSTING_READ(IER);
3535 }
3536
3537 static int i965_irq_postinstall(struct drm_device *dev)
3538 {
3539         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3540         u32 enable_mask;
3541         u32 error_mask;
3542         unsigned long irqflags;
3543
3544         /* Unmask the interrupts that we always want on. */
3545         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3546                                I915_DISPLAY_PORT_INTERRUPT |
3547                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3548                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3549                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3550                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3551                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3552
3553         enable_mask = ~dev_priv->irq_mask;
3554         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3555                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3556         enable_mask |= I915_USER_INTERRUPT;
3557
3558         if (IS_G4X(dev))
3559                 enable_mask |= I915_BSD_USER_INTERRUPT;
3560
3561         /* Interrupt setup is already guaranteed to be single-threaded, this is
3562          * just to make the assert_spin_locked check happy. */
3563         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3564         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3565         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3566         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3567         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3568
3569         /*
3570          * Enable some error detection, note the instruction error mask
3571          * bit is reserved, so we leave it masked.
3572          */
3573         if (IS_G4X(dev)) {
3574                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3575                                GM45_ERROR_MEM_PRIV |
3576                                GM45_ERROR_CP_PRIV |
3577                                I915_ERROR_MEMORY_REFRESH);
3578         } else {
3579                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3580                                I915_ERROR_MEMORY_REFRESH);
3581         }
3582         I915_WRITE(EMR, error_mask);
3583
3584         I915_WRITE(IMR, dev_priv->irq_mask);
3585         I915_WRITE(IER, enable_mask);
3586         POSTING_READ(IER);
3587
3588         I915_WRITE(PORT_HOTPLUG_EN, 0);
3589         POSTING_READ(PORT_HOTPLUG_EN);
3590
3591         i915_enable_asle_pipestat(dev);
3592
3593         return 0;
3594 }
3595
3596 static void i915_hpd_irq_setup(struct drm_device *dev)
3597 {
3598         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3599         struct drm_mode_config *mode_config = &dev->mode_config;
3600         struct intel_encoder *intel_encoder;
3601         u32 hotplug_en;
3602
3603         assert_spin_locked(&dev_priv->irq_lock);
3604
3605         if (I915_HAS_HOTPLUG(dev)) {
3606                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3607                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3608                 /* Note HDMI and DP share hotplug bits */
3609                 /* enable bits are the same for all generations */
3610                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3611                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3612                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3613                 /* Programming the CRT detection parameters tends
3614                    to generate a spurious hotplug event about three
3615                    seconds later.  So just do it once.
3616                 */
3617                 if (IS_G4X(dev))
3618                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3619                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3620                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3621
3622                 /* Ignore TV since it's buggy */
3623                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3624         }
3625 }
3626
3627 static irqreturn_t i965_irq_handler(int irq, void *arg)
3628 {
3629         struct drm_device *dev = (struct drm_device *) arg;
3630         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3631         u32 iir, new_iir;
3632         u32 pipe_stats[I915_MAX_PIPES];
3633         unsigned long irqflags;
3634         int irq_received;
3635         int ret = IRQ_NONE, pipe;
3636         u32 flip_mask =
3637                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3638                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3639
3640         atomic_inc(&dev_priv->irq_received);
3641
3642         iir = I915_READ(IIR);
3643
3644         for (;;) {
3645                 bool blc_event = false;
3646
3647                 irq_received = (iir & ~flip_mask) != 0;
3648
3649                 /* Can't rely on pipestat interrupt bit in iir as it might
3650                  * have been cleared after the pipestat interrupt was received.
3651                  * It doesn't set the bit in iir again, but it still produces
3652                  * interrupts (for non-MSI).
3653                  */
3654                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3655                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3656                         i915_handle_error(dev, false);
3657
3658                 for_each_pipe(pipe) {
3659                         int reg = PIPESTAT(pipe);
3660                         pipe_stats[pipe] = I915_READ(reg);
3661
3662                         /*
3663                          * Clear the PIPE*STAT regs before the IIR
3664                          */
3665                         if (pipe_stats[pipe] & 0x8000ffff) {
3666                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3667                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3668                                                          pipe_name(pipe));
3669                                 I915_WRITE(reg, pipe_stats[pipe]);
3670                                 irq_received = 1;
3671                         }
3672                 }
3673                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3674
3675                 if (!irq_received)
3676                         break;
3677
3678                 ret = IRQ_HANDLED;
3679
3680                 /* Consume port.  Then clear IIR or we'll miss events */
3681                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3682                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3683                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3684                                                                   HOTPLUG_INT_STATUS_G4X :
3685                                                                   HOTPLUG_INT_STATUS_I915);
3686
3687                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3688                                   hotplug_status);
3689
3690                         intel_hpd_irq_handler(dev, hotplug_trigger,
3691                                               IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3692
3693                         if (IS_G4X(dev) &&
3694                             (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3695                                 dp_aux_irq_handler(dev);
3696
3697                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3698                         I915_READ(PORT_HOTPLUG_STAT);
3699                 }
3700
3701                 I915_WRITE(IIR, iir & ~flip_mask);
3702                 new_iir = I915_READ(IIR); /* Flush posted writes */
3703
3704                 if (iir & I915_USER_INTERRUPT)
3705                         notify_ring(dev, &dev_priv->ring[RCS]);
3706                 if (iir & I915_BSD_USER_INTERRUPT)
3707                         notify_ring(dev, &dev_priv->ring[VCS]);
3708
3709                 for_each_pipe(pipe) {
3710                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3711                             i915_handle_vblank(dev, pipe, pipe, iir))
3712                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3713
3714                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3715                                 blc_event = true;
3716
3717                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3718                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3719                 }
3720
3721
3722                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3723                         intel_opregion_asle_intr(dev);
3724
3725                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3726                         gmbus_irq_handler(dev);
3727
3728                 /* With MSI, interrupts are only generated when iir
3729                  * transitions from zero to nonzero.  If another bit got
3730                  * set while we were handling the existing iir bits, then
3731                  * we would never get another interrupt.
3732                  *
3733                  * This is fine on non-MSI as well, as if we hit this path
3734                  * we avoid exiting the interrupt handler only to generate
3735                  * another one.
3736                  *
3737                  * Note that for MSI this could cause a stray interrupt report
3738                  * if an interrupt landed in the time between writing IIR and
3739                  * the posting read.  This should be rare enough to never
3740                  * trigger the 99% of 100,000 interrupts test for disabling
3741                  * stray interrupts.
3742                  */
3743                 iir = new_iir;
3744         }
3745
3746         i915_update_dri1_breadcrumb(dev);
3747
3748         return ret;
3749 }
3750
3751 static void i965_irq_uninstall(struct drm_device * dev)
3752 {
3753         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3754         int pipe;
3755
3756         if (!dev_priv)
3757                 return;
3758
3759         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3760
3761         I915_WRITE(PORT_HOTPLUG_EN, 0);
3762         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3763
3764         I915_WRITE(HWSTAM, 0xffffffff);
3765         for_each_pipe(pipe)
3766                 I915_WRITE(PIPESTAT(pipe), 0);
3767         I915_WRITE(IMR, 0xffffffff);
3768         I915_WRITE(IER, 0x0);
3769
3770         for_each_pipe(pipe)
3771                 I915_WRITE(PIPESTAT(pipe),
3772                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3773         I915_WRITE(IIR, I915_READ(IIR));
3774 }
3775
3776 static void i915_reenable_hotplug_timer_func(unsigned long data)
3777 {
3778         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3779         struct drm_device *dev = dev_priv->dev;
3780         struct drm_mode_config *mode_config = &dev->mode_config;
3781         unsigned long irqflags;
3782         int i;
3783
3784         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3785         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3786                 struct drm_connector *connector;
3787
3788                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3789                         continue;
3790
3791                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3792
3793                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3794                         struct intel_connector *intel_connector = to_intel_connector(connector);
3795
3796                         if (intel_connector->encoder->hpd_pin == i) {
3797                                 if (connector->polled != intel_connector->polled)
3798                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3799                                                          drm_get_connector_name(connector));
3800                                 connector->polled = intel_connector->polled;
3801                                 if (!connector->polled)
3802                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3803                         }
3804                 }
3805         }
3806         if (dev_priv->display.hpd_irq_setup)
3807                 dev_priv->display.hpd_irq_setup(dev);
3808         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3809 }
3810
3811 void intel_irq_init(struct drm_device *dev)
3812 {
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814
3815         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3816         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3817         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3818         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3819
3820         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3821                     i915_hangcheck_elapsed,
3822                     (unsigned long) dev);
3823         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3824                     (unsigned long) dev_priv);
3825
3826         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3827
3828         if (IS_GEN2(dev)) {
3829                 dev->max_vblank_count = 0;
3830                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3831         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3832                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3833                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3834         } else {
3835                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3836                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3837         }
3838
3839         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3840                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3841                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3842         }
3843
3844         if (IS_VALLEYVIEW(dev)) {
3845                 dev->driver->irq_handler = valleyview_irq_handler;
3846                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3847                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3848                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3849                 dev->driver->enable_vblank = valleyview_enable_vblank;
3850                 dev->driver->disable_vblank = valleyview_disable_vblank;
3851                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3852         } else if (IS_GEN8(dev)) {
3853                 dev->driver->irq_handler = gen8_irq_handler;
3854                 dev->driver->irq_preinstall = gen8_irq_preinstall;
3855                 dev->driver->irq_postinstall = gen8_irq_postinstall;
3856                 dev->driver->irq_uninstall = gen8_irq_uninstall;
3857                 dev->driver->enable_vblank = gen8_enable_vblank;
3858                 dev->driver->disable_vblank = gen8_disable_vblank;
3859                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3860         } else if (HAS_PCH_SPLIT(dev)) {
3861                 dev->driver->irq_handler = ironlake_irq_handler;
3862                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3863                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3864                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3865                 dev->driver->enable_vblank = ironlake_enable_vblank;
3866                 dev->driver->disable_vblank = ironlake_disable_vblank;
3867                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3868         } else {
3869                 if (INTEL_INFO(dev)->gen == 2) {
3870                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3871                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3872                         dev->driver->irq_handler = i8xx_irq_handler;
3873                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3874                 } else if (INTEL_INFO(dev)->gen == 3) {
3875                         dev->driver->irq_preinstall = i915_irq_preinstall;
3876                         dev->driver->irq_postinstall = i915_irq_postinstall;
3877                         dev->driver->irq_uninstall = i915_irq_uninstall;
3878                         dev->driver->irq_handler = i915_irq_handler;
3879                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3880                 } else {
3881                         dev->driver->irq_preinstall = i965_irq_preinstall;
3882                         dev->driver->irq_postinstall = i965_irq_postinstall;
3883                         dev->driver->irq_uninstall = i965_irq_uninstall;
3884                         dev->driver->irq_handler = i965_irq_handler;
3885                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3886                 }
3887                 dev->driver->enable_vblank = i915_enable_vblank;
3888                 dev->driver->disable_vblank = i915_disable_vblank;
3889         }
3890 }
3891
3892 void intel_hpd_init(struct drm_device *dev)
3893 {
3894         struct drm_i915_private *dev_priv = dev->dev_private;
3895         struct drm_mode_config *mode_config = &dev->mode_config;
3896         struct drm_connector *connector;
3897         unsigned long irqflags;
3898         int i;
3899
3900         for (i = 1; i < HPD_NUM_PINS; i++) {
3901                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3902                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3903         }
3904         list_for_each_entry(connector, &mode_config->connector_list, head) {
3905                 struct intel_connector *intel_connector = to_intel_connector(connector);
3906                 connector->polled = intel_connector->polled;
3907                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3908                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3909         }
3910
3911         /* Interrupt setup is already guaranteed to be single-threaded, this is
3912          * just to make the assert_spin_locked checks happy. */
3913         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3914         if (dev_priv->display.hpd_irq_setup)
3915                 dev_priv->display.hpd_irq_setup(dev);
3916         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3917 }
3918
3919 /* Disable interrupts so we can allow Package C8+. */
3920 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3921 {
3922         struct drm_i915_private *dev_priv = dev->dev_private;
3923         unsigned long irqflags;
3924
3925         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3926
3927         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3928         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3929         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3930         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3931         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3932
3933         ironlake_disable_display_irq(dev_priv, 0xffffffff);
3934         ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3935         ilk_disable_gt_irq(dev_priv, 0xffffffff);
3936         snb_disable_pm_irq(dev_priv, 0xffffffff);
3937
3938         dev_priv->pc8.irqs_disabled = true;
3939
3940         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3941 }
3942
3943 /* Restore interrupts so we can recover from Package C8+. */
3944 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3945 {
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         unsigned long irqflags;
3948         uint32_t val;
3949
3950         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3951
3952         val = I915_READ(DEIMR);
3953         WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3954
3955         val = I915_READ(SDEIMR);
3956         WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3957
3958         val = I915_READ(GTIMR);
3959         WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3960
3961         val = I915_READ(GEN6_PMIMR);
3962         WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3963
3964         dev_priv->pc8.irqs_disabled = false;
3965
3966         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3967         ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3968         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3969         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3970         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3971
3972         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3973 }