drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 void
  89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92                 u32 reg = PIPESTAT(pipe);
  93
  94                 dev_priv->pipestat[pipe] |= mask;
  95                 /* Enable the interrupt, clear any pending status */
  96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97                 POSTING_READ(reg);
  98         }
  99 }
 100
 101 void
 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = PIPESTAT(pipe);
 106
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109                 POSTING_READ(reg);
 110         }
 111 }
 112
 113 /**
 114  * intel_enable_asle - enable ASLE interrupt for OpRegion
 115  */
 116 void intel_enable_asle(struct drm_device *dev)
 117 {
 118         drm_i915_private_t *dev_priv = dev->dev_private;
 119         unsigned long irqflags;
 120
 121         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 125         else {
 126                 i915_enable_pipestat(dev_priv, 1,
 127                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 128                 if (INTEL_INFO(dev)->gen >= 4)
 129                         i915_enable_pipestat(dev_priv, 0,
 130                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 131         }
 132
 133         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 134 }
 135
 136 /**
 137  * i915_pipe_enabled - check if a pipe is enabled
 138  * @dev: DRM device
 139  * @pipe: pipe to check
 140  *
 141  * Reading certain registers when the pipe is disabled can hang the chip.
 142  * Use this routine to make sure the PLL is running and the pipe is active
 143  * before reading such registers if unsure.
 144  */
 145 static int
 146 i915_pipe_enabled(struct drm_device *dev, int pipe)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 150 }
 151
 152 /* Called from drm generic code, passed a 'crtc', which
 153  * we use as a pipe index
 154  */
 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156 {
 157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158         unsigned long high_frame;
 159         unsigned long low_frame;
 160         u32 high1, high2, low;
 161
 162         if (!i915_pipe_enabled(dev, pipe)) {
 163                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 164                                 "pipe %c\n", pipe_name(pipe));
 165                 return 0;
 166         }
 167
 168         high_frame = PIPEFRAME(pipe);
 169         low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171         /*
 172          * High & low register fields aren't synchronized, so make sure
 173          * we get a low value that's stable across two reads of the high
 174          * register.
 175          */
 176         do {
 177                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180         } while (high1 != high2);
 181
 182         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 183         low >>= PIPE_FRAME_LOW_SHIFT;
 184         return (high1 << 8) | low;
 185 }
 186
 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         int reg = PIPE_FRMCOUNT_GM45(pipe);
 191
 192         if (!i915_pipe_enabled(dev, pipe)) {
 193                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 194                                  "pipe %c\n", pipe_name(pipe));
 195                 return 0;
 196         }
 197
 198         return I915_READ(reg);
 199 }
 200
 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 202                              int *vpos, int *hpos)
 203 {
 204         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205         u32 vbl = 0, position = 0;
 206         int vbl_start, vbl_end, htotal, vtotal;
 207         bool in_vbl = true;
 208         int ret = 0;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 212                                  "pipe %c\n", pipe_name(pipe));
 213                 return 0;
 214         }
 215
 216         /* Get vtotal. */
 217         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 218
 219         if (INTEL_INFO(dev)->gen >= 4) {
 220                 /* No obvious pixelcount register. Only query vertical
 221                  * scanout position from Display scan line register.
 222                  */
 223                 position = I915_READ(PIPEDSL(pipe));
 224
 225                 /* Decode into vertical scanout position. Don't have
 226                  * horizontal scanout position.
 227                  */
 228                 *vpos = position & 0x1fff;
 229                 *hpos = 0;
 230         } else {
 231                 /* Have access to pixelcount since start of frame.
 232                  * We can split this into vertical and horizontal
 233                  * scanout position.
 234                  */
 235                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 236
 237                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 238                 *vpos = position / htotal;
 239                 *hpos = position - (*vpos * htotal);
 240         }
 241
 242         /* Query vblank area. */
 243         vbl = I915_READ(VBLANK(pipe));
 244
 245         /* Test position against vblank region. */
 246         vbl_start = vbl & 0x1fff;
 247         vbl_end = (vbl >> 16) & 0x1fff;
 248
 249         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 250                 in_vbl = false;
 251
 252         /* Inside "upper part" of vblank area? Apply corrective offset: */
 253         if (in_vbl && (*vpos >= vbl_start))
 254                 *vpos = *vpos - vtotal;
 255
 256         /* Readouts valid? */
 257         if (vbl > 0)
 258                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 259
 260         /* In vblank? */
 261         if (in_vbl)
 262                 ret |= DRM_SCANOUTPOS_INVBL;
 263
 264         return ret;
 265 }
 266
 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 268                               int *max_error,
 269                               struct timeval *vblank_time,
 270                               unsigned flags)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         struct drm_crtc *crtc;
 274
 275         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 276                 DRM_ERROR("Invalid crtc %d\n", pipe);
 277                 return -EINVAL;
 278         }
 279
 280         /* Get drm_crtc to timestamp: */
 281         crtc = intel_get_crtc_for_pipe(dev, pipe);
 282         if (crtc == NULL) {
 283                 DRM_ERROR("Invalid crtc %d\n", pipe);
 284                 return -EINVAL;
 285         }
 286
 287         if (!crtc->enabled) {
 288                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 289                 return -EBUSY;
 290         }
 291
 292         /* Helper routine in DRM core does all the work: */
 293         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 294                                                      vblank_time, flags,
 295                                                      crtc);
 296 }
 297
 298 /*
 299  * Handle hotplug events outside the interrupt handler proper.
 300  */
 301 static void i915_hotplug_work_func(struct work_struct *work)
 302 {
 303         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 304                                                     hotplug_work);
 305         struct drm_device *dev = dev_priv->dev;
 306         struct drm_mode_config *mode_config = &dev->mode_config;
 307         struct intel_encoder *encoder;
 308
 309         mutex_lock(&mode_config->mutex);
 310         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 311
 312         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 313                 if (encoder->hot_plug)
 314                         encoder->hot_plug(encoder);
 315
 316         mutex_unlock(&mode_config->mutex);
 317
 318         /* Just fire off a uevent and let userspace tell us what to do */
 319         drm_helper_hpd_irq_event(dev);
 320 }
 321
 322 static void i915_handle_rps_change(struct drm_device *dev)
 323 {
 324         drm_i915_private_t *dev_priv = dev->dev_private;
 325         u32 busy_up, busy_down, max_avg, min_avg;
 326         u8 new_delay = dev_priv->cur_delay;
 327
 328         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 329         busy_up = I915_READ(RCPREVBSYTUPAVG);
 330         busy_down = I915_READ(RCPREVBSYTDNAVG);
 331         max_avg = I915_READ(RCBMAXAVG);
 332         min_avg = I915_READ(RCBMINAVG);
 333
 334         /* Handle RCS change request from hw */
 335         if (busy_up > max_avg) {
 336                 if (dev_priv->cur_delay != dev_priv->max_delay)
 337                         new_delay = dev_priv->cur_delay - 1;
 338                 if (new_delay < dev_priv->max_delay)
 339                         new_delay = dev_priv->max_delay;
 340         } else if (busy_down < min_avg) {
 341                 if (dev_priv->cur_delay != dev_priv->min_delay)
 342                         new_delay = dev_priv->cur_delay + 1;
 343                 if (new_delay > dev_priv->min_delay)
 344                         new_delay = dev_priv->min_delay;
 345         }
 346
 347         if (ironlake_set_drps(dev, new_delay))
 348                 dev_priv->cur_delay = new_delay;
 349
 350         return;
 351 }
 352
 353 static void notify_ring(struct drm_device *dev,
 354                         struct intel_ring_buffer *ring)
 355 {
 356         struct drm_i915_private *dev_priv = dev->dev_private;
 357         u32 seqno;
 358
 359         if (ring->obj == NULL)
 360                 return;
 361
 362         seqno = ring->get_seqno(ring);
 363         trace_i915_gem_request_complete(ring, seqno);
 364
 365         ring->irq_seqno = seqno;
 366         wake_up_all(&ring->irq_queue);
 367         if (i915_enable_hangcheck) {
 368                 dev_priv->hangcheck_count = 0;
 369                 mod_timer(&dev_priv->hangcheck_timer,
 370                           jiffies +
 371                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 372         }
 373 }
 374
 375 static void gen6_pm_rps_work(struct work_struct *work)
 376 {
 377         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 378                                                     rps_work);
 379         u8 new_delay = dev_priv->cur_delay;
 380         u32 pm_iir, pm_imr;
 381
 382         spin_lock_irq(&dev_priv->rps_lock);
 383         pm_iir = dev_priv->pm_iir;
 384         dev_priv->pm_iir = 0;
 385         pm_imr = I915_READ(GEN6_PMIMR);
 386         I915_WRITE(GEN6_PMIMR, 0);
 387         spin_unlock_irq(&dev_priv->rps_lock);
 388
 389         if (!pm_iir)
 390                 return;
 391
 392         mutex_lock(&dev_priv->dev->struct_mutex);
 393         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 394                 if (dev_priv->cur_delay != dev_priv->max_delay)
 395                         new_delay = dev_priv->cur_delay + 1;
 396                 if (new_delay > dev_priv->max_delay)
 397                         new_delay = dev_priv->max_delay;
 398         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 399                 gen6_gt_force_wake_get(dev_priv);
 400                 if (dev_priv->cur_delay != dev_priv->min_delay)
 401                         new_delay = dev_priv->cur_delay - 1;
 402                 if (new_delay < dev_priv->min_delay) {
 403                         new_delay = dev_priv->min_delay;
 404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 406                                    ((new_delay << 16) & 0x3f0000));
 407                 } else {
 408                         /* Make sure we continue to get down interrupts
 409                          * until we hit the minimum frequency */
 410                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 411                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 412                 }
 413                 gen6_gt_force_wake_put(dev_priv);
 414         }
 415
 416         gen6_set_rps(dev_priv->dev, new_delay);
 417         dev_priv->cur_delay = new_delay;
 418
 419         /*
 420          * rps_lock not held here because clearing is non-destructive. There is
 421          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 422          * by holding struct_mutex for the duration of the write.
 423          */
 424         mutex_unlock(&dev_priv->dev->struct_mutex);
 425 }
 426
 427 static void pch_irq_handler(struct drm_device *dev)
 428 {
 429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 430         u32 pch_iir;
 431         int pipe;
 432
 433         pch_iir = I915_READ(SDEIIR);
 434
 435         if (pch_iir & SDE_AUDIO_POWER_MASK)
 436                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 437                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 438                                  SDE_AUDIO_POWER_SHIFT);
 439
 440         if (pch_iir & SDE_GMBUS)
 441                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 442
 443         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 444                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 445
 446         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 447                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 448
 449         if (pch_iir & SDE_POISON)
 450                 DRM_ERROR("PCH poison interrupt\n");
 451
 452         if (pch_iir & SDE_FDI_MASK)
 453                 for_each_pipe(pipe)
 454                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 455                                          pipe_name(pipe),
 456                                          I915_READ(FDI_RX_IIR(pipe)));
 457
 458         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 459                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 460
 461         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 462                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 463
 464         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 465                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 466         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 467                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 468 }
 469
 470 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 471 {
 472         struct drm_device *dev = (struct drm_device *) arg;
 473         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 474         int ret = IRQ_NONE;
 475         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 476         struct drm_i915_master_private *master_priv;
 477
 478         atomic_inc(&dev_priv->irq_received);
 479
 480         /* disable master interrupt before clearing iir  */
 481         de_ier = I915_READ(DEIER);
 482         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 483         POSTING_READ(DEIER);
 484
 485         de_iir = I915_READ(DEIIR);
 486         gt_iir = I915_READ(GTIIR);
 487         pch_iir = I915_READ(SDEIIR);
 488         pm_iir = I915_READ(GEN6_PMIIR);
 489
 490         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 491                 goto done;
 492
 493         ret = IRQ_HANDLED;
 494
 495         if (dev->primary->master) {
 496                 master_priv = dev->primary->master->driver_priv;
 497                 if (master_priv->sarea_priv)
 498                         master_priv->sarea_priv->last_dispatch =
 499                                 READ_BREADCRUMB(dev_priv);
 500         }
 501
 502         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 503                 notify_ring(dev, &dev_priv->ring[RCS]);
 504         if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 505                 notify_ring(dev, &dev_priv->ring[VCS]);
 506         if (gt_iir & GT_BLT_USER_INTERRUPT)
 507                 notify_ring(dev, &dev_priv->ring[BCS]);
 508
 509         if (de_iir & DE_GSE_IVB)
 510                 intel_opregion_gse_intr(dev);
 511
 512         if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 513                 intel_prepare_page_flip(dev, 0);
 514                 intel_finish_page_flip_plane(dev, 0);
 515         }
 516
 517         if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 518                 intel_prepare_page_flip(dev, 1);
 519                 intel_finish_page_flip_plane(dev, 1);
 520         }
 521
 522         if (de_iir & DE_PIPEA_VBLANK_IVB)
 523                 drm_handle_vblank(dev, 0);
 524
 525         if (de_iir & DE_PIPEB_VBLANK_IVB)
 526                 drm_handle_vblank(dev, 1);
 527
 528         /* check event from PCH */
 529         if (de_iir & DE_PCH_EVENT_IVB) {
 530                 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 531                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 532                 pch_irq_handler(dev);
 533         }
 534
 535         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 536                 unsigned long flags;
 537                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 538                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 539                 dev_priv->pm_iir |= pm_iir;
 540                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 541                 POSTING_READ(GEN6_PMIMR);
 542                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 543                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 544         }
 545
 546         /* should clear PCH hotplug event before clear CPU irq */
 547         I915_WRITE(SDEIIR, pch_iir);
 548         I915_WRITE(GTIIR, gt_iir);
 549         I915_WRITE(DEIIR, de_iir);
 550         I915_WRITE(GEN6_PMIIR, pm_iir);
 551
 552 done:
 553         I915_WRITE(DEIER, de_ier);
 554         POSTING_READ(DEIER);
 555
 556         return ret;
 557 }
 558
 559 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 560 {
 561         struct drm_device *dev = (struct drm_device *) arg;
 562         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 563         int ret = IRQ_NONE;
 564         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 565         u32 hotplug_mask;
 566         struct drm_i915_master_private *master_priv;
 567         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 568
 569         atomic_inc(&dev_priv->irq_received);
 570
 571         if (IS_GEN6(dev))
 572                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 573
 574         /* disable master interrupt before clearing iir  */
 575         de_ier = I915_READ(DEIER);
 576         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 577         POSTING_READ(DEIER);
 578
 579         de_iir = I915_READ(DEIIR);
 580         gt_iir = I915_READ(GTIIR);
 581         pch_iir = I915_READ(SDEIIR);
 582         pm_iir = I915_READ(GEN6_PMIIR);
 583
 584         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 585             (!IS_GEN6(dev) || pm_iir == 0))
 586                 goto done;
 587
 588         if (HAS_PCH_CPT(dev))
 589                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 590         else
 591                 hotplug_mask = SDE_HOTPLUG_MASK;
 592
 593         ret = IRQ_HANDLED;
 594
 595         if (dev->primary->master) {
 596                 master_priv = dev->primary->master->driver_priv;
 597                 if (master_priv->sarea_priv)
 598                         master_priv->sarea_priv->last_dispatch =
 599                                 READ_BREADCRUMB(dev_priv);
 600         }
 601
 602         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 603                 notify_ring(dev, &dev_priv->ring[RCS]);
 604         if (gt_iir & bsd_usr_interrupt)
 605                 notify_ring(dev, &dev_priv->ring[VCS]);
 606         if (gt_iir & GT_BLT_USER_INTERRUPT)
 607                 notify_ring(dev, &dev_priv->ring[BCS]);
 608
 609         if (de_iir & DE_GSE)
 610                 intel_opregion_gse_intr(dev);
 611
 612         if (de_iir & DE_PLANEA_FLIP_DONE) {
 613                 intel_prepare_page_flip(dev, 0);
 614                 intel_finish_page_flip_plane(dev, 0);
 615         }
 616
 617         if (de_iir & DE_PLANEB_FLIP_DONE) {
 618                 intel_prepare_page_flip(dev, 1);
 619                 intel_finish_page_flip_plane(dev, 1);
 620         }
 621
 622         if (de_iir & DE_PIPEA_VBLANK)
 623                 drm_handle_vblank(dev, 0);
 624
 625         if (de_iir & DE_PIPEB_VBLANK)
 626                 drm_handle_vblank(dev, 1);
 627
 628         /* check event from PCH */
 629         if (de_iir & DE_PCH_EVENT) {
 630                 if (pch_iir & hotplug_mask)
 631                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 632                 pch_irq_handler(dev);
 633         }
 634
 635         if (de_iir & DE_PCU_EVENT) {
 636                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 637                 i915_handle_rps_change(dev);
 638         }
 639
 640         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 641                 /*
 642                  * IIR bits should never already be set because IMR should
 643                  * prevent an interrupt from being shown in IIR. The warning
 644                  * displays a case where we've unsafely cleared
 645                  * dev_priv->pm_iir. Although missing an interrupt of the same
 646                  * type is not a problem, it displays a problem in the logic.
 647                  *
 648                  * The mask bit in IMR is cleared by rps_work.
 649                  */
 650                 unsigned long flags;
 651                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 652                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 653                 dev_priv->pm_iir |= pm_iir;
 654                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 655                 POSTING_READ(GEN6_PMIMR);
 656                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 657                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 658         }
 659
 660         /* should clear PCH hotplug event before clear CPU irq */
 661         I915_WRITE(SDEIIR, pch_iir);
 662         I915_WRITE(GTIIR, gt_iir);
 663         I915_WRITE(DEIIR, de_iir);
 664         I915_WRITE(GEN6_PMIIR, pm_iir);
 665
 666 done:
 667         I915_WRITE(DEIER, de_ier);
 668         POSTING_READ(DEIER);
 669
 670         return ret;
 671 }
 672
 673 /**
 674  * i915_error_work_func - do process context error handling work
 675  * @work: work struct
 676  *
 677  * Fire an error uevent so userspace can see that a hang or error
 678  * was detected.
 679  */
 680 static void i915_error_work_func(struct work_struct *work)
 681 {
 682         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 683                                                     error_work);
 684         struct drm_device *dev = dev_priv->dev;
 685         char *error_event[] = { "ERROR=1", NULL };
 686         char *reset_event[] = { "RESET=1", NULL };
 687         char *reset_done_event[] = { "ERROR=0", NULL };
 688
 689         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 690
 691         if (atomic_read(&dev_priv->mm.wedged)) {
 692                 DRM_DEBUG_DRIVER("resetting chip\n");
 693                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 694                 if (!i915_reset(dev, GRDOM_RENDER)) {
 695                         atomic_set(&dev_priv->mm.wedged, 0);
 696                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 697                 }
 698                 complete_all(&dev_priv->error_completion);
 699         }
 700 }
 701
 702 #ifdef CONFIG_DEBUG_FS
 703 static struct drm_i915_error_object *
 704 i915_error_object_create(struct drm_i915_private *dev_priv,
 705                          struct drm_i915_gem_object *src)
 706 {
 707         struct drm_i915_error_object *dst;
 708         int page, page_count;
 709         u32 reloc_offset;
 710
 711         if (src == NULL || src->pages == NULL)
 712                 return NULL;
 713
 714         page_count = src->base.size / PAGE_SIZE;
 715
 716         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 717         if (dst == NULL)
 718                 return NULL;
 719
 720         reloc_offset = src->gtt_offset;
 721         for (page = 0; page < page_count; page++) {
 722                 unsigned long flags;
 723                 void *d;
 724
 725                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 726                 if (d == NULL)
 727                         goto unwind;
 728
 729                 local_irq_save(flags);
 730                 if (reloc_offset < dev_priv->mm.gtt_mappable_end) {
 731                         void __iomem *s;
 732
 733                         /* Simply ignore tiling or any overlapping fence.
 734                          * It's part of the error state, and this hopefully
 735                          * captures what the GPU read.
 736                          */
 737
 738                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 739                                                      reloc_offset);
 740                         memcpy_fromio(d, s, PAGE_SIZE);
 741                         io_mapping_unmap_atomic(s);
 742                 } else {
 743                         void *s;
 744
 745                         drm_clflush_pages(&src->pages[page], 1);
 746
 747                         s = kmap_atomic(src->pages[page]);
 748                         memcpy(d, s, PAGE_SIZE);
 749                         kunmap_atomic(s);
 750
 751                         drm_clflush_pages(&src->pages[page], 1);
 752                 }
 753                 local_irq_restore(flags);
 754
 755                 dst->pages[page] = d;
 756
 757                 reloc_offset += PAGE_SIZE;
 758         }
 759         dst->page_count = page_count;
 760         dst->gtt_offset = src->gtt_offset;
 761
 762         return dst;
 763
 764 unwind:
 765         while (page--)
 766                 kfree(dst->pages[page]);
 767         kfree(dst);
 768         return NULL;
 769 }
 770
 771 static void
 772 i915_error_object_free(struct drm_i915_error_object *obj)
 773 {
 774         int page;
 775
 776         if (obj == NULL)
 777                 return;
 778
 779         for (page = 0; page < obj->page_count; page++)
 780                 kfree(obj->pages[page]);
 781
 782         kfree(obj);
 783 }
 784
 785 static void
 786 i915_error_state_free(struct drm_device *dev,
 787                       struct drm_i915_error_state *error)
 788 {
 789         int i;
 790
 791         for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 792                 i915_error_object_free(error->batchbuffer[i]);
 793
 794         for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 795                 i915_error_object_free(error->ringbuffer[i]);
 796
 797         kfree(error->active_bo);
 798         kfree(error->overlay);
 799         kfree(error);
 800 }
 801
 802 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 803                            int count,
 804                            struct list_head *head)
 805 {
 806         struct drm_i915_gem_object *obj;
 807         int i = 0;
 808
 809         list_for_each_entry(obj, head, mm_list) {
 810                 err->size = obj->base.size;
 811                 err->name = obj->base.name;
 812                 err->seqno = obj->last_rendering_seqno;
 813                 err->gtt_offset = obj->gtt_offset;
 814                 err->read_domains = obj->base.read_domains;
 815                 err->write_domain = obj->base.write_domain;
 816                 err->fence_reg = obj->fence_reg;
 817                 err->pinned = 0;
 818                 if (obj->pin_count > 0)
 819                         err->pinned = 1;
 820                 if (obj->user_pin_count > 0)
 821                         err->pinned = -1;
 822                 err->tiling = obj->tiling_mode;
 823                 err->dirty = obj->dirty;
 824                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 825                 err->ring = obj->ring ? obj->ring->id : -1;
 826                 err->cache_level = obj->cache_level;
 827
 828                 if (++i == count)
 829                         break;
 830
 831                 err++;
 832         }
 833
 834         return i;
 835 }
 836
 837 static void i915_gem_record_fences(struct drm_device *dev,
 838                                    struct drm_i915_error_state *error)
 839 {
 840         struct drm_i915_private *dev_priv = dev->dev_private;
 841         int i;
 842
 843         /* Fences */
 844         switch (INTEL_INFO(dev)->gen) {
 845         case 7:
 846         case 6:
 847                 for (i = 0; i < 16; i++)
 848                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 849                 break;
 850         case 5:
 851         case 4:
 852                 for (i = 0; i < 16; i++)
 853                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 854                 break;
 855         case 3:
 856                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 857                         for (i = 0; i < 8; i++)
 858                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 859         case 2:
 860                 for (i = 0; i < 8; i++)
 861                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 862                 break;
 863
 864         }
 865 }
 866
 867 static struct drm_i915_error_object *
 868 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 869                              struct intel_ring_buffer *ring)
 870 {
 871         struct drm_i915_gem_object *obj;
 872         u32 seqno;
 873
 874         if (!ring->get_seqno)
 875                 return NULL;
 876
 877         seqno = ring->get_seqno(ring);
 878         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 879                 if (obj->ring != ring)
 880                         continue;
 881
 882                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 883                         continue;
 884
 885                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 886                         continue;
 887
 888                 /* We need to copy these to an anonymous buffer as the simplest
 889                  * method to avoid being overwritten by userspace.
 890                  */
 891                 return i915_error_object_create(dev_priv, obj);
 892         }
 893
 894         return NULL;
 895 }
 896
 897 static void i915_record_ring_state(struct drm_device *dev,
 898                                    struct drm_i915_error_state *error,
 899                                    struct intel_ring_buffer *ring)
 900 {
 901         struct drm_i915_private *dev_priv = dev->dev_private;
 902
 903         if (INTEL_INFO(dev)->gen >= 6) {
 904                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
 905                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
 906                 error->semaphore_mboxes[ring->id][0]
 907                         = I915_READ(RING_SYNC_0(ring->mmio_base));
 908                 error->semaphore_mboxes[ring->id][1]
 909                         = I915_READ(RING_SYNC_1(ring->mmio_base));
 910         }
 911
 912         if (INTEL_INFO(dev)->gen >= 4) {
 913                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
 914                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
 915                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
 916                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
 917                 if (ring->id == RCS) {
 918                         error->instdone1 = I915_READ(INSTDONE1);
 919                         error->bbaddr = I915_READ64(BB_ADDR);
 920                 }
 921         } else {
 922                 error->ipeir[ring->id] = I915_READ(IPEIR);
 923                 error->ipehr[ring->id] = I915_READ(IPEHR);
 924                 error->instdone[ring->id] = I915_READ(INSTDONE);
 925         }
 926
 927         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
 928         error->seqno[ring->id] = ring->get_seqno(ring);
 929         error->acthd[ring->id] = intel_ring_get_active_head(ring);
 930         error->head[ring->id] = I915_READ_HEAD(ring);
 931         error->tail[ring->id] = I915_READ_TAIL(ring);
 932
 933         error->cpu_ring_head[ring->id] = ring->head;
 934         error->cpu_ring_tail[ring->id] = ring->tail;
 935 }
 936
 937 /**
 938  * i915_capture_error_state - capture an error record for later analysis
 939  * @dev: drm device
 940  *
 941  * Should be called when an error is detected (either a hang or an error
 942  * interrupt) to capture error state from the time of the error.  Fills
 943  * out a structure which becomes available in debugfs for user level tools
 944  * to pick up.
 945  */
 946 static void i915_capture_error_state(struct drm_device *dev)
 947 {
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         struct drm_i915_gem_object *obj;
 950         struct drm_i915_error_state *error;
 951         unsigned long flags;
 952         int i, pipe;
 953
 954         spin_lock_irqsave(&dev_priv->error_lock, flags);
 955         error = dev_priv->first_error;
 956         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 957         if (error)
 958                 return;
 959
 960         /* Account for pipe specific data like PIPE*STAT */
 961         error = kzalloc(sizeof(*error), GFP_ATOMIC);
 962         if (!error) {
 963                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 964                 return;
 965         }
 966
 967         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 968                  dev->primary->index);
 969
 970         error->eir = I915_READ(EIR);
 971         error->pgtbl_er = I915_READ(PGTBL_ER);
 972         for_each_pipe(pipe)
 973                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 974
 975         if (INTEL_INFO(dev)->gen >= 6) {
 976                 error->error = I915_READ(ERROR_GEN6);
 977                 error->done_reg = I915_READ(DONE_REG);
 978         }
 979
 980         i915_record_ring_state(dev, error, &dev_priv->ring[RCS]);
 981         if (HAS_BLT(dev))
 982                 i915_record_ring_state(dev, error, &dev_priv->ring[BCS]);
 983         if (HAS_BSD(dev))
 984                 i915_record_ring_state(dev, error, &dev_priv->ring[VCS]);
 985
 986         i915_gem_record_fences(dev, error);
 987
 988         /* Record the active batch and ring buffers */
 989         for (i = 0; i < I915_NUM_RINGS; i++) {
 990                 error->batchbuffer[i] =
 991                         i915_error_first_batchbuffer(dev_priv,
 992                                                      &dev_priv->ring[i]);
 993
 994                 error->ringbuffer[i] =
 995                         i915_error_object_create(dev_priv,
 996                                                  dev_priv->ring[i].obj);
 997         }
 998
 999         /* Record buffers on the active and pinned lists. */
1000         error->active_bo = NULL;
1001         error->pinned_bo = NULL;
1002
1003         i = 0;
1004         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1005                 i++;
1006         error->active_bo_count = i;
1007         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
1008                 i++;
1009         error->pinned_bo_count = i - error->active_bo_count;
1010
1011         error->active_bo = NULL;
1012         error->pinned_bo = NULL;
1013         if (i) {
1014                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1015                                            GFP_ATOMIC);
1016                 if (error->active_bo)
1017                         error->pinned_bo =
1018                                 error->active_bo + error->active_bo_count;
1019         }
1020
1021         if (error->active_bo)
1022                 error->active_bo_count =
1023                         capture_bo_list(error->active_bo,
1024                                         error->active_bo_count,
1025                                         &dev_priv->mm.active_list);
1026
1027         if (error->pinned_bo)
1028                 error->pinned_bo_count =
1029                         capture_bo_list(error->pinned_bo,
1030                                         error->pinned_bo_count,
1031                                         &dev_priv->mm.pinned_list);
1032
1033         do_gettimeofday(&error->time);
1034
1035         error->overlay = intel_overlay_capture_error_state(dev);
1036         error->display = intel_display_capture_error_state(dev);
1037
1038         spin_lock_irqsave(&dev_priv->error_lock, flags);
1039         if (dev_priv->first_error == NULL) {
1040                 dev_priv->first_error = error;
1041                 error = NULL;
1042         }
1043         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1044
1045         if (error)
1046                 i915_error_state_free(dev, error);
1047 }
1048
1049 void i915_destroy_error_state(struct drm_device *dev)
1050 {
1051         struct drm_i915_private *dev_priv = dev->dev_private;
1052         struct drm_i915_error_state *error;
1053         unsigned long flags;
1054
1055         spin_lock_irqsave(&dev_priv->error_lock, flags);
1056         error = dev_priv->first_error;
1057         dev_priv->first_error = NULL;
1058         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1059
1060         if (error)
1061                 i915_error_state_free(dev, error);
1062 }
1063 #else
1064 #define i915_capture_error_state(x)
1065 #endif
1066
1067 static void i915_report_and_clear_eir(struct drm_device *dev)
1068 {
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         u32 eir = I915_READ(EIR);
1071         int pipe;
1072
1073         if (!eir)
1074                 return;
1075
1076         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1077                eir);
1078
1079         if (IS_G4X(dev)) {
1080                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1081                         u32 ipeir = I915_READ(IPEIR_I965);
1082
1083                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1084                                I915_READ(IPEIR_I965));
1085                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1086                                I915_READ(IPEHR_I965));
1087                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1088                                I915_READ(INSTDONE_I965));
1089                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1090                                I915_READ(INSTPS));
1091                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1092                                I915_READ(INSTDONE1));
1093                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1094                                I915_READ(ACTHD_I965));
1095                         I915_WRITE(IPEIR_I965, ipeir);
1096                         POSTING_READ(IPEIR_I965);
1097                 }
1098                 if (eir & GM45_ERROR_PAGE_TABLE) {
1099                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1100                         printk(KERN_ERR "page table error\n");
1101                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1102                                pgtbl_err);
1103                         I915_WRITE(PGTBL_ER, pgtbl_err);
1104                         POSTING_READ(PGTBL_ER);
1105                 }
1106         }
1107
1108         if (!IS_GEN2(dev)) {
1109                 if (eir & I915_ERROR_PAGE_TABLE) {
1110                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1111                         printk(KERN_ERR "page table error\n");
1112                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1113                                pgtbl_err);
1114                         I915_WRITE(PGTBL_ER, pgtbl_err);
1115                         POSTING_READ(PGTBL_ER);
1116                 }
1117         }
1118
1119         if (eir & I915_ERROR_MEMORY_REFRESH) {
1120                 printk(KERN_ERR "memory refresh error:\n");
1121                 for_each_pipe(pipe)
1122                         printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1123                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1124                 /* pipestat has already been acked */
1125         }
1126         if (eir & I915_ERROR_INSTRUCTION) {
1127                 printk(KERN_ERR "instruction error\n");
1128                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
1129                        I915_READ(INSTPM));
1130                 if (INTEL_INFO(dev)->gen < 4) {
1131                         u32 ipeir = I915_READ(IPEIR);
1132
1133                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1134                                I915_READ(IPEIR));
1135                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1136                                I915_READ(IPEHR));
1137                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1138                                I915_READ(INSTDONE));
1139                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1140                                I915_READ(ACTHD));
1141                         I915_WRITE(IPEIR, ipeir);
1142                         POSTING_READ(IPEIR);
1143                 } else {
1144                         u32 ipeir = I915_READ(IPEIR_I965);
1145
1146                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1147                                I915_READ(IPEIR_I965));
1148                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1149                                I915_READ(IPEHR_I965));
1150                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1151                                I915_READ(INSTDONE_I965));
1152                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1153                                I915_READ(INSTPS));
1154                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1155                                I915_READ(INSTDONE1));
1156                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1157                                I915_READ(ACTHD_I965));
1158                         I915_WRITE(IPEIR_I965, ipeir);
1159                         POSTING_READ(IPEIR_I965);
1160                 }
1161         }
1162
1163         I915_WRITE(EIR, eir);
1164         POSTING_READ(EIR);
1165         eir = I915_READ(EIR);
1166         if (eir) {
1167                 /*
1168                  * some errors might have become stuck,
1169                  * mask them.
1170                  */
1171                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1172                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1173                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1174         }
1175 }
1176
1177 /**
1178  * i915_handle_error - handle an error interrupt
1179  * @dev: drm device
1180  *
1181  * Do some basic checking of regsiter state at error interrupt time and
1182  * dump it to the syslog.  Also call i915_capture_error_state() to make
1183  * sure we get a record and make it available in debugfs.  Fire a uevent
1184  * so userspace knows something bad happened (should trigger collection
1185  * of a ring dump etc.).
1186  */
1187 void i915_handle_error(struct drm_device *dev, bool wedged)
1188 {
1189         struct drm_i915_private *dev_priv = dev->dev_private;
1190
1191         i915_capture_error_state(dev);
1192         i915_report_and_clear_eir(dev);
1193
1194         if (wedged) {
1195                 INIT_COMPLETION(dev_priv->error_completion);
1196                 atomic_set(&dev_priv->mm.wedged, 1);
1197
1198                 /*
1199                  * Wakeup waiting processes so they don't hang
1200                  */
1201                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1202                 if (HAS_BSD(dev))
1203                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1204                 if (HAS_BLT(dev))
1205                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1206         }
1207
1208         queue_work(dev_priv->wq, &dev_priv->error_work);
1209 }
1210
1211 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1212 {
1213         drm_i915_private_t *dev_priv = dev->dev_private;
1214         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1216         struct drm_i915_gem_object *obj;
1217         struct intel_unpin_work *work;
1218         unsigned long flags;
1219         bool stall_detected;
1220
1221         /* Ignore early vblank irqs */
1222         if (intel_crtc == NULL)
1223                 return;
1224
1225         spin_lock_irqsave(&dev->event_lock, flags);
1226         work = intel_crtc->unpin_work;
1227
1228         if (work == NULL || work->pending || !work->enable_stall_check) {
1229                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1230                 spin_unlock_irqrestore(&dev->event_lock, flags);
1231                 return;
1232         }
1233
1234         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1235         obj = work->pending_flip_obj;
1236         if (INTEL_INFO(dev)->gen >= 4) {
1237                 int dspsurf = DSPSURF(intel_crtc->plane);
1238                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1239         } else {
1240                 int dspaddr = DSPADDR(intel_crtc->plane);
1241                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1242                                                         crtc->y * crtc->fb->pitches[0] +
1243                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1244         }
1245
1246         spin_unlock_irqrestore(&dev->event_lock, flags);
1247
1248         if (stall_detected) {
1249                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1250                 intel_prepare_page_flip(dev, intel_crtc->plane);
1251         }
1252 }
1253
1254 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1255 {
1256         struct drm_device *dev = (struct drm_device *) arg;
1257         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1258         struct drm_i915_master_private *master_priv;
1259         u32 iir, new_iir;
1260         u32 pipe_stats[I915_MAX_PIPES];
1261         u32 vblank_status;
1262         int vblank = 0;
1263         unsigned long irqflags;
1264         int irq_received;
1265         int ret = IRQ_NONE, pipe;
1266         bool blc_event = false;
1267
1268         atomic_inc(&dev_priv->irq_received);
1269
1270         iir = I915_READ(IIR);
1271
1272         if (INTEL_INFO(dev)->gen >= 4)
1273                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1274         else
1275                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1276
1277         for (;;) {
1278                 irq_received = iir != 0;
1279
1280                 /* Can't rely on pipestat interrupt bit in iir as it might
1281                  * have been cleared after the pipestat interrupt was received.
1282                  * It doesn't set the bit in iir again, but it still produces
1283                  * interrupts (for non-MSI).
1284                  */
1285                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1286                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1287                         i915_handle_error(dev, false);
1288
1289                 for_each_pipe(pipe) {
1290                         int reg = PIPESTAT(pipe);
1291                         pipe_stats[pipe] = I915_READ(reg);
1292
1293                         /*
1294                          * Clear the PIPE*STAT regs before the IIR
1295                          */
1296                         if (pipe_stats[pipe] & 0x8000ffff) {
1297                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1298                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1299                                                          pipe_name(pipe));
1300                                 I915_WRITE(reg, pipe_stats[pipe]);
1301                                 irq_received = 1;
1302                         }
1303                 }
1304                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1305
1306                 if (!irq_received)
1307                         break;
1308
1309                 ret = IRQ_HANDLED;
1310
1311                 /* Consume port.  Then clear IIR or we'll miss events */
1312                 if ((I915_HAS_HOTPLUG(dev)) &&
1313                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1314                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1315
1316                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1317                                   hotplug_status);
1318                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1319                                 queue_work(dev_priv->wq,
1320                                            &dev_priv->hotplug_work);
1321
1322                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1323                         I915_READ(PORT_HOTPLUG_STAT);
1324                 }
1325
1326                 I915_WRITE(IIR, iir);
1327                 new_iir = I915_READ(IIR); /* Flush posted writes */
1328
1329                 if (dev->primary->master) {
1330                         master_priv = dev->primary->master->driver_priv;
1331                         if (master_priv->sarea_priv)
1332                                 master_priv->sarea_priv->last_dispatch =
1333                                         READ_BREADCRUMB(dev_priv);
1334                 }
1335
1336                 if (iir & I915_USER_INTERRUPT)
1337                         notify_ring(dev, &dev_priv->ring[RCS]);
1338                 if (iir & I915_BSD_USER_INTERRUPT)
1339                         notify_ring(dev, &dev_priv->ring[VCS]);
1340
1341                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1342                         intel_prepare_page_flip(dev, 0);
1343                         if (dev_priv->flip_pending_is_done)
1344                                 intel_finish_page_flip_plane(dev, 0);
1345                 }
1346
1347                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1348                         intel_prepare_page_flip(dev, 1);
1349                         if (dev_priv->flip_pending_is_done)
1350                                 intel_finish_page_flip_plane(dev, 1);
1351                 }
1352
1353                 for_each_pipe(pipe) {
1354                         if (pipe_stats[pipe] & vblank_status &&
1355                             drm_handle_vblank(dev, pipe)) {
1356                                 vblank++;
1357                                 if (!dev_priv->flip_pending_is_done) {
1358                                         i915_pageflip_stall_check(dev, pipe);
1359                                         intel_finish_page_flip(dev, pipe);
1360                                 }
1361                         }
1362
1363                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1364                                 blc_event = true;
1365                 }
1366
1367
1368                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1369                         intel_opregion_asle_intr(dev);
1370
1371                 /* With MSI, interrupts are only generated when iir
1372                  * transitions from zero to nonzero.  If another bit got
1373                  * set while we were handling the existing iir bits, then
1374                  * we would never get another interrupt.
1375                  *
1376                  * This is fine on non-MSI as well, as if we hit this path
1377                  * we avoid exiting the interrupt handler only to generate
1378                  * another one.
1379                  *
1380                  * Note that for MSI this could cause a stray interrupt report
1381                  * if an interrupt landed in the time between writing IIR and
1382                  * the posting read.  This should be rare enough to never
1383                  * trigger the 99% of 100,000 interrupts test for disabling
1384                  * stray interrupts.
1385                  */
1386                 iir = new_iir;
1387         }
1388
1389         return ret;
1390 }
1391
1392 static int i915_emit_irq(struct drm_device * dev)
1393 {
1394         drm_i915_private_t *dev_priv = dev->dev_private;
1395         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1396
1397         i915_kernel_lost_context(dev);
1398
1399         DRM_DEBUG_DRIVER("\n");
1400
1401         dev_priv->counter++;
1402         if (dev_priv->counter > 0x7FFFFFFFUL)
1403                 dev_priv->counter = 1;
1404         if (master_priv->sarea_priv)
1405                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1406
1407         if (BEGIN_LP_RING(4) == 0) {
1408                 OUT_RING(MI_STORE_DWORD_INDEX);
1409                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1410                 OUT_RING(dev_priv->counter);
1411                 OUT_RING(MI_USER_INTERRUPT);
1412                 ADVANCE_LP_RING();
1413         }
1414
1415         return dev_priv->counter;
1416 }
1417
1418 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1419 {
1420         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1421         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1422         int ret = 0;
1423         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1424
1425         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1426                   READ_BREADCRUMB(dev_priv));
1427
1428         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1429                 if (master_priv->sarea_priv)
1430                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1431                 return 0;
1432         }
1433
1434         if (master_priv->sarea_priv)
1435                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1436
1437         if (ring->irq_get(ring)) {
1438                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1439                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1440                 ring->irq_put(ring);
1441         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1442                 ret = -EBUSY;
1443
1444         if (ret == -EBUSY) {
1445                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1446                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1447         }
1448
1449         return ret;
1450 }
1451
1452 /* Needs the lock as it touches the ring.
1453  */
1454 int i915_irq_emit(struct drm_device *dev, void *data,
1455                          struct drm_file *file_priv)
1456 {
1457         drm_i915_private_t *dev_priv = dev->dev_private;
1458         drm_i915_irq_emit_t *emit = data;
1459         int result;
1460
1461         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1462                 DRM_ERROR("called with no initialization\n");
1463                 return -EINVAL;
1464         }
1465
1466         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1467
1468         mutex_lock(&dev->struct_mutex);
1469         result = i915_emit_irq(dev);
1470         mutex_unlock(&dev->struct_mutex);
1471
1472         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1473                 DRM_ERROR("copy_to_user\n");
1474                 return -EFAULT;
1475         }
1476
1477         return 0;
1478 }
1479
1480 /* Doesn't need the hardware lock.
1481  */
1482 int i915_irq_wait(struct drm_device *dev, void *data,
1483                          struct drm_file *file_priv)
1484 {
1485         drm_i915_private_t *dev_priv = dev->dev_private;
1486         drm_i915_irq_wait_t *irqwait = data;
1487
1488         if (!dev_priv) {
1489                 DRM_ERROR("called with no initialization\n");
1490                 return -EINVAL;
1491         }
1492
1493         return i915_wait_irq(dev, irqwait->irq_seq);
1494 }
1495
1496 /* Called from drm generic code, passed 'crtc' which
1497  * we use as a pipe index
1498  */
1499 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1500 {
1501         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1502         unsigned long irqflags;
1503
1504         if (!i915_pipe_enabled(dev, pipe))
1505                 return -EINVAL;
1506
1507         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1508         if (INTEL_INFO(dev)->gen >= 4)
1509                 i915_enable_pipestat(dev_priv, pipe,
1510                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1511         else
1512                 i915_enable_pipestat(dev_priv, pipe,
1513                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1514
1515         /* maintain vblank delivery even in deep C-states */
1516         if (dev_priv->info->gen == 3)
1517                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1518         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1519
1520         return 0;
1521 }
1522
1523 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1524 {
1525         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1526         unsigned long irqflags;
1527
1528         if (!i915_pipe_enabled(dev, pipe))
1529                 return -EINVAL;
1530
1531         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1532         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1533                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1534         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1535
1536         return 0;
1537 }
1538
1539 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1540 {
1541         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1542         unsigned long irqflags;
1543
1544         if (!i915_pipe_enabled(dev, pipe))
1545                 return -EINVAL;
1546
1547         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1548         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1549                                     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1550         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1551
1552         return 0;
1553 }
1554
1555 /* Called from drm generic code, passed 'crtc' which
1556  * we use as a pipe index
1557  */
1558 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1559 {
1560         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1561         unsigned long irqflags;
1562
1563         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1564         if (dev_priv->info->gen == 3)
1565                 I915_WRITE(INSTPM,
1566                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1567
1568         i915_disable_pipestat(dev_priv, pipe,
1569                               PIPE_VBLANK_INTERRUPT_ENABLE |
1570                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1571         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1572 }
1573
1574 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1575 {
1576         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1577         unsigned long irqflags;
1578
1579         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1580         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1581                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1582         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1583 }
1584
1585 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1586 {
1587         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1588         unsigned long irqflags;
1589
1590         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1591         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1592                                      DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1593         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1594 }
1595
1596 /* Set the vblank monitor pipe
1597  */
1598 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1599                          struct drm_file *file_priv)
1600 {
1601         drm_i915_private_t *dev_priv = dev->dev_private;
1602
1603         if (!dev_priv) {
1604                 DRM_ERROR("called with no initialization\n");
1605                 return -EINVAL;
1606         }
1607
1608         return 0;
1609 }
1610
1611 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1612                          struct drm_file *file_priv)
1613 {
1614         drm_i915_private_t *dev_priv = dev->dev_private;
1615         drm_i915_vblank_pipe_t *pipe = data;
1616
1617         if (!dev_priv) {
1618                 DRM_ERROR("called with no initialization\n");
1619                 return -EINVAL;
1620         }
1621
1622         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1623
1624         return 0;
1625 }
1626
1627 /**
1628  * Schedule buffer swap at given vertical blank.
1629  */
1630 int i915_vblank_swap(struct drm_device *dev, void *data,
1631                      struct drm_file *file_priv)
1632 {
1633         /* The delayed swap mechanism was fundamentally racy, and has been
1634          * removed.  The model was that the client requested a delayed flip/swap
1635          * from the kernel, then waited for vblank before continuing to perform
1636          * rendering.  The problem was that the kernel might wake the client
1637          * up before it dispatched the vblank swap (since the lock has to be
1638          * held while touching the ringbuffer), in which case the client would
1639          * clear and start the next frame before the swap occurred, and
1640          * flicker would occur in addition to likely missing the vblank.
1641          *
1642          * In the absence of this ioctl, userland falls back to a correct path
1643          * of waiting for a vblank, then dispatching the swap on its own.
1644          * Context switching to userland and back is plenty fast enough for
1645          * meeting the requirements of vblank swapping.
1646          */
1647         return -EINVAL;
1648 }
1649
1650 static u32
1651 ring_last_seqno(struct intel_ring_buffer *ring)
1652 {
1653         return list_entry(ring->request_list.prev,
1654                           struct drm_i915_gem_request, list)->seqno;
1655 }
1656
1657 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1658 {
1659         if (list_empty(&ring->request_list) ||
1660             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1661                 /* Issue a wake-up to catch stuck h/w. */
1662                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1663                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1664                                   ring->name,
1665                                   ring->waiting_seqno,
1666                                   ring->get_seqno(ring));
1667                         wake_up_all(&ring->irq_queue);
1668                         *err = true;
1669                 }
1670                 return true;
1671         }
1672         return false;
1673 }
1674
1675 static bool kick_ring(struct intel_ring_buffer *ring)
1676 {
1677         struct drm_device *dev = ring->dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         u32 tmp = I915_READ_CTL(ring);
1680         if (tmp & RING_WAIT) {
1681                 DRM_ERROR("Kicking stuck wait on %s\n",
1682                           ring->name);
1683                 I915_WRITE_CTL(ring, tmp);
1684                 return true;
1685         }
1686         return false;
1687 }
1688
1689 /**
1690  * This is called when the chip hasn't reported back with completed
1691  * batchbuffers in a long time. The first time this is called we simply record
1692  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1693  * again, we assume the chip is wedged and try to fix it.
1694  */
1695 void i915_hangcheck_elapsed(unsigned long data)
1696 {
1697         struct drm_device *dev = (struct drm_device *)data;
1698         drm_i915_private_t *dev_priv = dev->dev_private;
1699         uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1700         bool err = false;
1701
1702         if (!i915_enable_hangcheck)
1703                 return;
1704
1705         /* If all work is done then ACTHD clearly hasn't advanced. */
1706         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1707             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1708             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1709                 dev_priv->hangcheck_count = 0;
1710                 if (err)
1711                         goto repeat;
1712                 return;
1713         }
1714
1715         if (INTEL_INFO(dev)->gen < 4) {
1716                 instdone = I915_READ(INSTDONE);
1717                 instdone1 = 0;
1718         } else {
1719                 instdone = I915_READ(INSTDONE_I965);
1720                 instdone1 = I915_READ(INSTDONE1);
1721         }
1722         acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1723         acthd_bsd = HAS_BSD(dev) ?
1724                 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1725         acthd_blt = HAS_BLT(dev) ?
1726                 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1727
1728         if (dev_priv->last_acthd == acthd &&
1729             dev_priv->last_acthd_bsd == acthd_bsd &&
1730             dev_priv->last_acthd_blt == acthd_blt &&
1731             dev_priv->last_instdone == instdone &&
1732             dev_priv->last_instdone1 == instdone1) {
1733                 if (dev_priv->hangcheck_count++ > 1) {
1734                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1735                         i915_handle_error(dev, true);
1736
1737                         if (!IS_GEN2(dev)) {
1738                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1739                                  * If so we can simply poke the RB_WAIT bit
1740                                  * and break the hang. This should work on
1741                                  * all but the second generation chipsets.
1742                                  */
1743                                 if (kick_ring(&dev_priv->ring[RCS]))
1744                                         goto repeat;
1745
1746                                 if (HAS_BSD(dev) &&
1747                                     kick_ring(&dev_priv->ring[VCS]))
1748                                         goto repeat;
1749
1750                                 if (HAS_BLT(dev) &&
1751                                     kick_ring(&dev_priv->ring[BCS]))
1752                                         goto repeat;
1753                         }
1754
1755                         return;
1756                 }
1757         } else {
1758                 dev_priv->hangcheck_count = 0;
1759
1760                 dev_priv->last_acthd = acthd;
1761                 dev_priv->last_acthd_bsd = acthd_bsd;
1762                 dev_priv->last_acthd_blt = acthd_blt;
1763                 dev_priv->last_instdone = instdone;
1764                 dev_priv->last_instdone1 = instdone1;
1765         }
1766
1767 repeat:
1768         /* Reset timer case chip hangs without another request being added */
1769         mod_timer(&dev_priv->hangcheck_timer,
1770                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1771 }
1772
1773 /* drm_dma.h hooks
1774 */
1775 static void ironlake_irq_preinstall(struct drm_device *dev)
1776 {
1777         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1778
1779         atomic_set(&dev_priv->irq_received, 0);
1780
1781         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1782         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1783         if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1784                 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1785
1786         I915_WRITE(HWSTAM, 0xeffe);
1787
1788         if (IS_GEN6(dev)) {
1789                 /* Workaround stalls observed on Sandy Bridge GPUs by
1790                  * making the blitter command streamer generate a
1791                  * write to the Hardware Status Page for
1792                  * MI_USER_INTERRUPT.  This appears to serialize the
1793                  * previous seqno write out before the interrupt
1794                  * happens.
1795                  */
1796                 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1797                 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1798         }
1799
1800         /* XXX hotplug from PCH */
1801
1802         I915_WRITE(DEIMR, 0xffffffff);
1803         I915_WRITE(DEIER, 0x0);
1804         POSTING_READ(DEIER);
1805
1806         /* and GT */
1807         I915_WRITE(GTIMR, 0xffffffff);
1808         I915_WRITE(GTIER, 0x0);
1809         POSTING_READ(GTIER);
1810
1811         /* south display irq */
1812         I915_WRITE(SDEIMR, 0xffffffff);
1813         I915_WRITE(SDEIER, 0x0);
1814         POSTING_READ(SDEIER);
1815 }
1816
1817 /*
1818  * Enable digital hotplug on the PCH, and configure the DP short pulse
1819  * duration to 2ms (which is the minimum in the Display Port spec)
1820  *
1821  * This register is the same on all known PCH chips.
1822  */
1823
1824 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1825 {
1826         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1827         u32     hotplug;
1828
1829         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1830         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1831         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1832         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1833         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1834         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1835 }
1836
1837 static int ironlake_irq_postinstall(struct drm_device *dev)
1838 {
1839         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1840         /* enable kind of interrupts always enabled */
1841         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1842                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1843         u32 render_irqs;
1844         u32 hotplug_mask;
1845
1846         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1847         if (HAS_BSD(dev))
1848                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1849         if (HAS_BLT(dev))
1850                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1851
1852         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1853         dev_priv->irq_mask = ~display_mask;
1854
1855         /* should always can generate irq */
1856         I915_WRITE(DEIIR, I915_READ(DEIIR));
1857         I915_WRITE(DEIMR, dev_priv->irq_mask);
1858         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1859         POSTING_READ(DEIER);
1860
1861         dev_priv->gt_irq_mask = ~0;
1862
1863         I915_WRITE(GTIIR, I915_READ(GTIIR));
1864         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1865
1866         if (IS_GEN6(dev))
1867                 render_irqs =
1868                         GT_USER_INTERRUPT |
1869                         GT_GEN6_BSD_USER_INTERRUPT |
1870                         GT_BLT_USER_INTERRUPT;
1871         else
1872                 render_irqs =
1873                         GT_USER_INTERRUPT |
1874                         GT_PIPE_NOTIFY |
1875                         GT_BSD_USER_INTERRUPT;
1876         I915_WRITE(GTIER, render_irqs);
1877         POSTING_READ(GTIER);
1878
1879         if (HAS_PCH_CPT(dev)) {
1880                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1881                                 SDE_PORTB_HOTPLUG_CPT |
1882                                 SDE_PORTC_HOTPLUG_CPT |
1883                                 SDE_PORTD_HOTPLUG_CPT);
1884         } else {
1885                 hotplug_mask = (SDE_CRT_HOTPLUG |
1886                                 SDE_PORTB_HOTPLUG |
1887                                 SDE_PORTC_HOTPLUG |
1888                                 SDE_PORTD_HOTPLUG |
1889                                 SDE_AUX_MASK);
1890         }
1891
1892         dev_priv->pch_irq_mask = ~hotplug_mask;
1893
1894         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1895         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1896         I915_WRITE(SDEIER, hotplug_mask);
1897         POSTING_READ(SDEIER);
1898
1899         ironlake_enable_pch_hotplug(dev);
1900
1901         if (IS_IRONLAKE_M(dev)) {
1902                 /* Clear & enable PCU event interrupts */
1903                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1904                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1905                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1906         }
1907
1908         return 0;
1909 }
1910
1911 static int ivybridge_irq_postinstall(struct drm_device *dev)
1912 {
1913         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1914         /* enable kind of interrupts always enabled */
1915         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1916                 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1917                 DE_PLANEB_FLIP_DONE_IVB;
1918         u32 render_irqs;
1919         u32 hotplug_mask;
1920
1921         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1922         if (HAS_BSD(dev))
1923                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1924         if (HAS_BLT(dev))
1925                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1926
1927         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1928         dev_priv->irq_mask = ~display_mask;
1929
1930         /* should always can generate irq */
1931         I915_WRITE(DEIIR, I915_READ(DEIIR));
1932         I915_WRITE(DEIMR, dev_priv->irq_mask);
1933         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1934                    DE_PIPEB_VBLANK_IVB);
1935         POSTING_READ(DEIER);
1936
1937         dev_priv->gt_irq_mask = ~0;
1938
1939         I915_WRITE(GTIIR, I915_READ(GTIIR));
1940         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1941
1942         render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1943                 GT_BLT_USER_INTERRUPT;
1944         I915_WRITE(GTIER, render_irqs);
1945         POSTING_READ(GTIER);
1946
1947         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1948                         SDE_PORTB_HOTPLUG_CPT |
1949                         SDE_PORTC_HOTPLUG_CPT |
1950                         SDE_PORTD_HOTPLUG_CPT);
1951         dev_priv->pch_irq_mask = ~hotplug_mask;
1952
1953         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1954         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1955         I915_WRITE(SDEIER, hotplug_mask);
1956         POSTING_READ(SDEIER);
1957
1958         ironlake_enable_pch_hotplug(dev);
1959
1960         return 0;
1961 }
1962
1963 static void i915_driver_irq_preinstall(struct drm_device * dev)
1964 {
1965         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1966         int pipe;
1967
1968         atomic_set(&dev_priv->irq_received, 0);
1969
1970         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1971         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1972
1973         if (I915_HAS_HOTPLUG(dev)) {
1974                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1975                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1976         }
1977
1978         I915_WRITE(HWSTAM, 0xeffe);
1979         for_each_pipe(pipe)
1980                 I915_WRITE(PIPESTAT(pipe), 0);
1981         I915_WRITE(IMR, 0xffffffff);
1982         I915_WRITE(IER, 0x0);
1983         POSTING_READ(IER);
1984 }
1985
1986 /*
1987  * Must be called after intel_modeset_init or hotplug interrupts won't be
1988  * enabled correctly.
1989  */
1990 static int i915_driver_irq_postinstall(struct drm_device *dev)
1991 {
1992         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1993         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1994         u32 error_mask;
1995
1996         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1997
1998         /* Unmask the interrupts that we always want on. */
1999         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
2000
2001         dev_priv->pipestat[0] = 0;
2002         dev_priv->pipestat[1] = 0;
2003
2004         if (I915_HAS_HOTPLUG(dev)) {
2005                 /* Enable in IER... */
2006                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2007                 /* and unmask in IMR */
2008                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2009         }
2010
2011         /*
2012          * Enable some error detection, note the instruction error mask
2013          * bit is reserved, so we leave it masked.
2014          */
2015         if (IS_G4X(dev)) {
2016                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2017                                GM45_ERROR_MEM_PRIV |
2018                                GM45_ERROR_CP_PRIV |
2019                                I915_ERROR_MEMORY_REFRESH);
2020         } else {
2021                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2022                                I915_ERROR_MEMORY_REFRESH);
2023         }
2024         I915_WRITE(EMR, error_mask);
2025
2026         I915_WRITE(IMR, dev_priv->irq_mask);
2027         I915_WRITE(IER, enable_mask);
2028         POSTING_READ(IER);
2029
2030         if (I915_HAS_HOTPLUG(dev)) {
2031                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2032
2033                 /* Note HDMI and DP share bits */
2034                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2035                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2036                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2037                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2038                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2039                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2040                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2041                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2042                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2043                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2044                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2045                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2046
2047                         /* Programming the CRT detection parameters tends
2048                            to generate a spurious hotplug event about three
2049                            seconds later.  So just do it once.
2050                         */
2051                         if (IS_G4X(dev))
2052                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2053                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2054                 }
2055
2056                 /* Ignore TV since it's buggy */
2057
2058                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2059         }
2060
2061         intel_opregion_enable_asle(dev);
2062
2063         return 0;
2064 }
2065
2066 static void ironlake_irq_uninstall(struct drm_device *dev)
2067 {
2068         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2069
2070         if (!dev_priv)
2071                 return;
2072
2073         dev_priv->vblank_pipe = 0;
2074
2075         I915_WRITE(HWSTAM, 0xffffffff);
2076
2077         I915_WRITE(DEIMR, 0xffffffff);
2078         I915_WRITE(DEIER, 0x0);
2079         I915_WRITE(DEIIR, I915_READ(DEIIR));
2080
2081         I915_WRITE(GTIMR, 0xffffffff);
2082         I915_WRITE(GTIER, 0x0);
2083         I915_WRITE(GTIIR, I915_READ(GTIIR));
2084
2085         I915_WRITE(SDEIMR, 0xffffffff);
2086         I915_WRITE(SDEIER, 0x0);
2087         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2088 }
2089
2090 static void i915_driver_irq_uninstall(struct drm_device * dev)
2091 {
2092         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2093         int pipe;
2094
2095         if (!dev_priv)
2096                 return;
2097
2098         dev_priv->vblank_pipe = 0;
2099
2100         if (I915_HAS_HOTPLUG(dev)) {
2101                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2102                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2103         }
2104
2105         I915_WRITE(HWSTAM, 0xffffffff);
2106         for_each_pipe(pipe)
2107                 I915_WRITE(PIPESTAT(pipe), 0);
2108         I915_WRITE(IMR, 0xffffffff);
2109         I915_WRITE(IER, 0x0);
2110
2111         for_each_pipe(pipe)
2112                 I915_WRITE(PIPESTAT(pipe),
2113                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2114         I915_WRITE(IIR, I915_READ(IIR));
2115 }
2116
2117 void intel_irq_init(struct drm_device *dev)
2118 {
2119         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2120         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2121         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2122                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2123                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2124         }
2125
2126         if (drm_core_check_feature(dev, DRIVER_MODESET))
2127                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2128         else
2129                 dev->driver->get_vblank_timestamp = NULL;
2130         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2131
2132         if (IS_IVYBRIDGE(dev)) {
2133                 /* Share pre & uninstall handlers with ILK/SNB */
2134                 dev->driver->irq_handler = ivybridge_irq_handler;
2135                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2136                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2137                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2138                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2139                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2140         } else if (HAS_PCH_SPLIT(dev)) {
2141                 dev->driver->irq_handler = ironlake_irq_handler;
2142                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2143                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2144                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2145                 dev->driver->enable_vblank = ironlake_enable_vblank;
2146                 dev->driver->disable_vblank = ironlake_disable_vblank;
2147         } else {
2148                 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2149                 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2150                 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2151                 dev->driver->irq_handler = i915_driver_irq_handler;
2152                 dev->driver->enable_vblank = i915_enable_vblank;
2153                 dev->driver->disable_vblank = i915_disable_vblank;
2154         }
2155 }