drivers/gpu/drm/i915/i915_gem_tiling.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <linux/string.h>
  29 #include <linux/bitops.h>
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33
  34 /** @file i915_gem_tiling.c
  35  *
  36  * Support for managing tiling state of buffer objects.
  37  *
  38  * The idea behind tiling is to increase cache hit rates by rearranging
  39  * pixel data so that a group of pixel accesses are in the same cacheline.
  40  * Performance improvement from doing this on the back/depth buffer are on
  41  * the order of 30%.
  42  *
  43  * Intel architectures make this somewhat more complicated, though, by
  44  * adjustments made to addressing of data when the memory is in interleaved
  45  * mode (matched pairs of DIMMS) to improve memory bandwidth.
  46  * For interleaved memory, the CPU sends every sequential 64 bytes
  47  * to an alternate memory channel so it can get the bandwidth from both.
  48  *
  49  * The GPU also rearranges its accesses for increased bandwidth to interleaved
  50  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
  51  * it does it a little differently, since one walks addresses not just in the
  52  * X direction but also Y.  So, along with alternating channels when bit
  53  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
  54  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
  55  * are common to both the 915 and 965-class hardware.
  56  *
  57  * The CPU also sometimes XORs in higher bits as well, to improve
  58  * bandwidth doing strided access like we do so frequently in graphics.  This
  59  * is called "Channel XOR Randomization" in the MCH documentation.  The result
  60  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
  61  * decode.
  62  *
  63  * All of this bit 6 XORing has an effect on our memory management,
  64  * as we need to make sure that the 3d driver can correctly address object
  65  * contents.
  66  *
  67  * If we don't have interleaved memory, all tiling is safe and no swizzling is
  68  * required.
  69  *
  70  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
  71  * 17 is not just a page offset, so as we page an objet out and back in,
  72  * individual pages in it will have different bit 17 addresses, resulting in
  73  * each 64 bytes being swapped with its neighbor!
  74  *
  75  * Otherwise, if interleaved, we have to tell the 3d driver what the address
  76  * swizzling it needs to do is, since it's writing with the CPU to the pages
  77  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
  78  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
  79  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
  80  * to match what the GPU expects.
  81  */
  82
  83 /**
  84  * Detects bit 6 swizzling of address lookup between IGD access and CPU
  85  * access through main memory.
  86  */
  87 void
  88 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
  89 {
  90         drm_i915_private_t *dev_priv = dev->dev_private;
  91         uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
  92         uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
  93
  94         if (IS_VALLEYVIEW(dev)) {
  95                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
  96                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
  97         } else if (INTEL_INFO(dev)->gen >= 6) {
  98                 uint32_t dimm_c0, dimm_c1;
  99                 dimm_c0 = I915_READ(MAD_DIMM_C0);
 100                 dimm_c1 = I915_READ(MAD_DIMM_C1);
 101                 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 102                 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 103                 /* Enable swizzling when the channels are populated with
 104                  * identically sized dimms. We don't need to check the 3rd
 105                  * channel because no cpu with gpu attached ships in that
 106                  * configuration. Also, swizzling only makes sense for 2
 107                  * channels anyway. */
 108                 if (dimm_c0 == dimm_c1) {
 109                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 110                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 111                 } else {
 112                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 113                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 114                 }
 115         } else if (IS_GEN5(dev)) {
 116                 /* On Ironlake whatever DRAM config, GPU always do
 117                  * same swizzling setup.
 118                  */
 119                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 120                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 121         } else if (IS_GEN2(dev)) {
 122                 /* As far as we know, the 865 doesn't have these bit 6
 123                  * swizzling issues.
 124                  */
 125                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 126                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 127         } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
 128                 uint32_t dcc;
 129
 130                 /* On 9xx chipsets, channel interleave by the CPU is
 131                  * determined by DCC.  For single-channel, neither the CPU
 132                  * nor the GPU do swizzling.  For dual channel interleaved,
 133                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
 134                  * 9 for Y tiled.  The CPU's interleave is independent, and
 135                  * can be based on either bit 11 (haven't seen this yet) or
 136                  * bit 17 (common).
 137                  */
 138                 dcc = I915_READ(DCC);
 139                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 140                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 141                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 142                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 143                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 144                         break;
 145                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 146                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
 147                                 /* This is the base swizzling by the GPU for
 148                                  * tiled buffers.
 149                                  */
 150                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 151                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 152                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
 153                                 /* Bit 11 swizzling by the CPU in addition. */
 154                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 155                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 156                         } else {
 157                                 /* Bit 17 swizzling by the CPU in addition. */
 158                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 159                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 160                         }
 161                         break;
 162                 }
 163                 if (dcc == 0xffffffff) {
 164                         DRM_ERROR("Couldn't read from MCHBAR.  "
 165                                   "Disabling tiling.\n");
 166                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 167                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 168                 }
 169         } else {
 170                 /* The 965, G33, and newer, have a very flexible memory
 171                  * configuration.  It will enable dual-channel mode
 172                  * (interleaving) on as much memory as it can, and the GPU
 173                  * will additionally sometimes enable different bit 6
 174                  * swizzling for tiled objects from the CPU.
 175                  *
 176                  * Here's what I found on the G965:
 177                  *    slot fill         memory size  swizzling
 178                  * 0A   0B   1A   1B    1-ch   2-ch
 179                  * 512  0    0    0     512    0     O
 180                  * 512  0    512  0     16     1008  X
 181                  * 512  0    0    512   16     1008  X
 182                  * 0    512  0    512   16     1008  X
 183                  * 1024 1024 1024 0     2048   1024  O
 184                  *
 185                  * We could probably detect this based on either the DRB
 186                  * matching, which was the case for the swizzling required in
 187                  * the table above, or from the 1-ch value being less than
 188                  * the minimum size of a rank.
 189                  */
 190                 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
 191                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 192                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 193                 } else {
 194                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 195                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 196                 }
 197         }
 198
 199         dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 200         dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 201 }
 202
 203 /* Check pitch constriants for all chips & tiling formats */
 204 static bool
 205 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 206 {
 207         int tile_width;
 208
 209         /* Linear is always fine */
 210         if (tiling_mode == I915_TILING_NONE)
 211                 return true;
 212
 213         if (IS_GEN2(dev) ||
 214             (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
 215                 tile_width = 128;
 216         else
 217                 tile_width = 512;
 218
 219         /* check maximum stride & object size */
 220         if (INTEL_INFO(dev)->gen >= 4) {
 221                 /* i965 stores the end address of the gtt mapping in the fence
 222                  * reg, so dont bother to check the size */
 223                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
 224                         return false;
 225         } else {
 226                 if (stride > 8192)
 227                         return false;
 228
 229                 if (IS_GEN3(dev)) {
 230                         if (size > I830_FENCE_MAX_SIZE_VAL << 20)
 231                                 return false;
 232                 } else {
 233                         if (size > I830_FENCE_MAX_SIZE_VAL << 19)
 234                                 return false;
 235                 }
 236         }
 237
 238         /* 965+ just needs multiples of tile width */
 239         if (INTEL_INFO(dev)->gen >= 4) {
 240                 if (stride & (tile_width - 1))
 241                         return false;
 242                 return true;
 243         }
 244
 245         /* Pre-965 needs power of two tile widths */
 246         if (stride < tile_width)
 247                 return false;
 248
 249         if (stride & (stride - 1))
 250                 return false;
 251
 252         return true;
 253 }
 254
 255 /* Is the current GTT allocation valid for the change in tiling? */
 256 static bool
 257 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
 258 {
 259         u32 size;
 260
 261         if (tiling_mode == I915_TILING_NONE)
 262                 return true;
 263
 264         if (INTEL_INFO(obj->base.dev)->gen >= 4)
 265                 return true;
 266
 267         if (INTEL_INFO(obj->base.dev)->gen == 3) {
 268                 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
 269                         return false;
 270         } else {
 271                 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
 272                         return false;
 273         }
 274
 275         /*
 276          * Previous chips need to be aligned to the size of the smallest
 277          * fence register that can contain the object.
 278          */
 279         if (INTEL_INFO(obj->base.dev)->gen == 3)
 280                 size = 1024*1024;
 281         else
 282                 size = 512*1024;
 283
 284         while (size < obj->base.size)
 285                 size <<= 1;
 286
 287         if (obj->gtt_space->size != size)
 288                 return false;
 289
 290         if (obj->gtt_offset & (size - 1))
 291                 return false;
 292
 293         return true;
 294 }
 295
 296 /**
 297  * Sets the tiling mode of an object, returning the required swizzling of
 298  * bit 6 of addresses in the object.
 299  */
 300 int
 301 i915_gem_set_tiling(struct drm_device *dev, void *data,
 302                    struct drm_file *file)
 303 {
 304         struct drm_i915_gem_set_tiling *args = data;
 305         drm_i915_private_t *dev_priv = dev->dev_private;
 306         struct drm_i915_gem_object *obj;
 307         int ret = 0;
 308
 309         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 310         if (&obj->base == NULL)
 311                 return -ENOENT;
 312
 313         if (!i915_tiling_ok(dev,
 314                             args->stride, obj->base.size, args->tiling_mode)) {
 315                 drm_gem_object_unreference_unlocked(&obj->base);
 316                 return -EINVAL;
 317         }
 318
 319         if (obj->pin_count) {
 320                 drm_gem_object_unreference_unlocked(&obj->base);
 321                 return -EBUSY;
 322         }
 323
 324         if (args->tiling_mode == I915_TILING_NONE) {
 325                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 326                 args->stride = 0;
 327         } else {
 328                 if (args->tiling_mode == I915_TILING_X)
 329                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 330                 else
 331                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 332
 333                 /* Hide bit 17 swizzling from the user.  This prevents old Mesa
 334                  * from aborting the application on sw fallbacks to bit 17,
 335                  * and we use the pread/pwrite bit17 paths to swizzle for it.
 336                  * If there was a user that was relying on the swizzle
 337                  * information for drm_intel_bo_map()ed reads/writes this would
 338                  * break it, but we don't have any of those.
 339                  */
 340                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 341                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 342                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 343                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 344
 345                 /* If we can't handle the swizzling, make it untiled. */
 346                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
 347                         args->tiling_mode = I915_TILING_NONE;
 348                         args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 349                         args->stride = 0;
 350                 }
 351         }
 352
 353         mutex_lock(&dev->struct_mutex);
 354         if (args->tiling_mode != obj->tiling_mode ||
 355             args->stride != obj->stride) {
 356                 /* We need to rebind the object if its current allocation
 357                  * no longer meets the alignment restrictions for its new
 358                  * tiling mode. Otherwise we can just leave it alone, but
 359                  * need to ensure that any fence register is updated before
 360                  * the next fenced (either through the GTT or by the BLT unit
 361                  * on older GPUs) access.
 362                  *
 363                  * After updating the tiling parameters, we then flag whether
 364                  * we need to update an associated fence register. Note this
 365                  * has to also include the unfenced register the GPU uses
 366                  * whilst executing a fenced command for an untiled object.
 367                  */
 368
 369                 obj->map_and_fenceable =
 370                         obj->gtt_space == NULL ||
 371                         (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
 372                          i915_gem_object_fence_ok(obj, args->tiling_mode));
 373
 374                 /* Rebind if we need a change of alignment */
 375                 if (!obj->map_and_fenceable) {
 376                         u32 unfenced_alignment =
 377                                 i915_gem_get_gtt_alignment(dev, obj->base.size,
 378                                                             args->tiling_mode,
 379                                                             false);
 380                         if (obj->gtt_offset & (unfenced_alignment - 1))
 381                                 ret = i915_gem_object_unbind(obj);
 382                 }
 383
 384                 if (ret == 0) {
 385                         obj->fence_dirty =
 386                                 obj->fenced_gpu_access ||
 387                                 obj->fence_reg != I915_FENCE_REG_NONE;
 388
 389                         obj->tiling_mode = args->tiling_mode;
 390                         obj->stride = args->stride;
 391
 392                         /* Force the fence to be reacquired for GTT access */
 393                         i915_gem_release_mmap(obj);
 394                 }
 395         }
 396         /* we have to maintain this existing ABI... */
 397         args->stride = obj->stride;
 398         args->tiling_mode = obj->tiling_mode;
 399
 400         /* Try to preallocate memory required to save swizzling on put-pages */
 401         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 402                 if (obj->bit_17 == NULL) {
 403                         obj->bit_17 = kmalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT) *
 404                                               sizeof(long), GFP_KERNEL);
 405                 }
 406         } else {
 407                 kfree(obj->bit_17);
 408                 obj->bit_17 = NULL;
 409         }
 410
 411         drm_gem_object_unreference(&obj->base);
 412         mutex_unlock(&dev->struct_mutex);
 413
 414         return ret;
 415 }
 416
 417 /**
 418  * Returns the current tiling mode and required bit 6 swizzling for the object.
 419  */
 420 int
 421 i915_gem_get_tiling(struct drm_device *dev, void *data,
 422                    struct drm_file *file)
 423 {
 424         struct drm_i915_gem_get_tiling *args = data;
 425         drm_i915_private_t *dev_priv = dev->dev_private;
 426         struct drm_i915_gem_object *obj;
 427
 428         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 429         if (&obj->base == NULL)
 430                 return -ENOENT;
 431
 432         mutex_lock(&dev->struct_mutex);
 433
 434         args->tiling_mode = obj->tiling_mode;
 435         switch (obj->tiling_mode) {
 436         case I915_TILING_X:
 437                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 438                 break;
 439         case I915_TILING_Y:
 440                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 441                 break;
 442         case I915_TILING_NONE:
 443                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 444                 break;
 445         default:
 446                 DRM_ERROR("unknown tiling mode\n");
 447         }
 448
 449         /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
 450         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 451                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 452         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 453                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 454
 455         drm_gem_object_unreference(&obj->base);
 456         mutex_unlock(&dev->struct_mutex);
 457
 458         return 0;
 459 }
 460
 461 /**
 462  * Swap every 64 bytes of this page around, to account for it having a new
 463  * bit 17 of its physical address and therefore being interpreted differently
 464  * by the GPU.
 465  */
 466 static void
 467 i915_gem_swizzle_page(struct page *page)
 468 {
 469         char temp[64];
 470         char *vaddr;
 471         int i;
 472
 473         vaddr = kmap(page);
 474
 475         for (i = 0; i < PAGE_SIZE; i += 128) {
 476                 memcpy(temp, &vaddr[i], 64);
 477                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
 478                 memcpy(&vaddr[i + 64], temp, 64);
 479         }
 480
 481         kunmap(page);
 482 }
 483
 484 void
 485 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
 486 {
 487         struct scatterlist *sg;
 488         int page_count = obj->base.size >> PAGE_SHIFT;
 489         int i;
 490
 491         if (obj->bit_17 == NULL)
 492                 return;
 493
 494         for_each_sg(obj->pages->sgl, sg, page_count, i) {
 495                 struct page *page = sg_page(sg);
 496                 char new_bit_17 = page_to_phys(page) >> 17;
 497                 if ((new_bit_17 & 0x1) !=
 498                     (test_bit(i, obj->bit_17) != 0)) {
 499                         i915_gem_swizzle_page(page);
 500                         set_page_dirty(page);
 501                 }
 502         }
 503 }
 504
 505 void
 506 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
 507 {
 508         struct scatterlist *sg;
 509         int page_count = obj->base.size >> PAGE_SHIFT;
 510         int i;
 511
 512         if (obj->bit_17 == NULL) {
 513                 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
 514                                            sizeof(long), GFP_KERNEL);
 515                 if (obj->bit_17 == NULL) {
 516                         DRM_ERROR("Failed to allocate memory for bit 17 "
 517                                   "record\n");
 518                         return;
 519                 }
 520         }
 521
 522         for_each_sg(obj->pages->sgl, sg, page_count, i) {
 523                 struct page *page = sg_page(sg);
 524                 if (page_to_phys(page) & (1 << 17))
 525                         __set_bit(i, obj->bit_17);
 526                 else
 527                         __clear_bit(i, obj->bit_17);
 528         }
 529 }