drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 typedef uint32_t gtt_pte_t;
  32
  33 /* PPGTT stuff */
  34 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  35
  36 #define GEN6_PDE_VALID                  (1 << 0)
  37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  38 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  39
  40 #define GEN6_PTE_VALID                  (1 << 0)
  41 #define GEN6_PTE_UNCACHED               (1 << 1)
  42 #define HSW_PTE_UNCACHED                (0)
  43 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  44 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  45 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  46
  47 static inline gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  48                                         dma_addr_t addr,
  49                                         enum i915_cache_level level)
  50 {
  51         gtt_pte_t pte = GEN6_PTE_VALID;
  52         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  53
  54         switch (level) {
  55         case I915_CACHE_LLC_MLC:
  56                 /* Haswell doesn't set L3 this way */
  57                 if (IS_HASWELL(dev))
  58                         pte |= GEN6_PTE_CACHE_LLC;
  59                 else
  60                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  61                 break;
  62         case I915_CACHE_LLC:
  63                 pte |= GEN6_PTE_CACHE_LLC;
  64                 break;
  65         case I915_CACHE_NONE:
  66                 if (IS_HASWELL(dev))
  67                         pte |= HSW_PTE_UNCACHED;
  68                 else
  69                         pte |= GEN6_PTE_UNCACHED;
  70                 break;
  71         default:
  72                 BUG();
  73         }
  74
  75
  76         return pte;
  77 }
  78
  79 /* PPGTT support for Sandybdrige/Gen6 and later */
  80 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
  81                                    unsigned first_entry,
  82                                    unsigned num_entries)
  83 {
  84         gtt_pte_t *pt_vaddr;
  85         gtt_pte_t scratch_pte;
  86         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
  87         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
  88         unsigned last_pte, i;
  89
  90         scratch_pte = gen6_pte_encode(ppgtt->dev,
  91                                       ppgtt->scratch_page_dma_addr,
  92                                       I915_CACHE_LLC);
  93
  94         while (num_entries) {
  95                 last_pte = first_pte + num_entries;
  96                 if (last_pte > I915_PPGTT_PT_ENTRIES)
  97                         last_pte = I915_PPGTT_PT_ENTRIES;
  98
  99                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 100
 101                 for (i = first_pte; i < last_pte; i++)
 102                         pt_vaddr[i] = scratch_pte;
 103
 104                 kunmap_atomic(pt_vaddr);
 105
 106                 num_entries -= last_pte - first_pte;
 107                 first_pte = 0;
 108                 act_pt++;
 109         }
 110 }
 111
 112 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 113                                       struct sg_table *pages,
 114                                       unsigned first_entry,
 115                                       enum i915_cache_level cache_level)
 116 {
 117         gtt_pte_t *pt_vaddr;
 118         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 119         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 120         struct sg_page_iter sg_iter;
 121
 122         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 123         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 124                 dma_addr_t page_addr;
 125
 126                 page_addr = sg_dma_address(sg_iter.sg) +
 127                                 (sg_iter.sg_pgoffset << PAGE_SHIFT);
 128                 pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
 129                                                     cache_level);
 130                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 131                         kunmap_atomic(pt_vaddr);
 132                         act_pt++;
 133                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 134                         act_pte = 0;
 135
 136                 }
 137         }
 138         kunmap_atomic(pt_vaddr);
 139 }
 140
 141 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 142 {
 143         int i;
 144
 145         if (ppgtt->pt_dma_addr) {
 146                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 147                         pci_unmap_page(ppgtt->dev->pdev,
 148                                        ppgtt->pt_dma_addr[i],
 149                                        4096, PCI_DMA_BIDIRECTIONAL);
 150         }
 151
 152         kfree(ppgtt->pt_dma_addr);
 153         for (i = 0; i < ppgtt->num_pd_entries; i++)
 154                 __free_page(ppgtt->pt_pages[i]);
 155         kfree(ppgtt->pt_pages);
 156         kfree(ppgtt);
 157 }
 158
 159 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 160 {
 161         struct drm_device *dev = ppgtt->dev;
 162         struct drm_i915_private *dev_priv = dev->dev_private;
 163         unsigned first_pd_entry_in_global_pt;
 164         int i;
 165         int ret = -ENOMEM;
 166
 167         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 168          * entries. For aliasing ppgtt support we just steal them at the end for
 169          * now. */
 170         first_pd_entry_in_global_pt =
 171                 gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 172
 173         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 174         ppgtt->clear_range = gen6_ppgtt_clear_range;
 175         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 176         ppgtt->cleanup = gen6_ppgtt_cleanup;
 177         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 178                                   GFP_KERNEL);
 179         if (!ppgtt->pt_pages)
 180                 return -ENOMEM;
 181
 182         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 183                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 184                 if (!ppgtt->pt_pages[i])
 185                         goto err_pt_alloc;
 186         }
 187
 188         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 189                                      GFP_KERNEL);
 190         if (!ppgtt->pt_dma_addr)
 191                 goto err_pt_alloc;
 192
 193         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 194                 dma_addr_t pt_addr;
 195
 196                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 197                                        PCI_DMA_BIDIRECTIONAL);
 198
 199                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 200                         ret = -EIO;
 201                         goto err_pd_pin;
 202
 203                 }
 204                 ppgtt->pt_dma_addr[i] = pt_addr;
 205         }
 206
 207         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 208
 209         ppgtt->clear_range(ppgtt, 0,
 210                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 211
 212         ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
 213
 214         return 0;
 215
 216 err_pd_pin:
 217         if (ppgtt->pt_dma_addr) {
 218                 for (i--; i >= 0; i--)
 219                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 220                                        4096, PCI_DMA_BIDIRECTIONAL);
 221         }
 222 err_pt_alloc:
 223         kfree(ppgtt->pt_dma_addr);
 224         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 225                 if (ppgtt->pt_pages[i])
 226                         __free_page(ppgtt->pt_pages[i]);
 227         }
 228         kfree(ppgtt->pt_pages);
 229
 230         return ret;
 231 }
 232
 233 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 234 {
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         struct i915_hw_ppgtt *ppgtt;
 237         int ret;
 238
 239         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 240         if (!ppgtt)
 241                 return -ENOMEM;
 242
 243         ppgtt->dev = dev;
 244
 245         ret = gen6_ppgtt_init(ppgtt);
 246         if (ret)
 247                 kfree(ppgtt);
 248         else
 249                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 250
 251         return ret;
 252 }
 253
 254 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 258
 259         if (!ppgtt)
 260                 return;
 261
 262         ppgtt->cleanup(ppgtt);
 263 }
 264
 265 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 266                             struct drm_i915_gem_object *obj,
 267                             enum i915_cache_level cache_level)
 268 {
 269         ppgtt->insert_entries(ppgtt, obj->pages,
 270                               obj->gtt_space->start >> PAGE_SHIFT,
 271                               cache_level);
 272 }
 273
 274 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 275                               struct drm_i915_gem_object *obj)
 276 {
 277         ppgtt->clear_range(ppgtt,
 278                            obj->gtt_space->start >> PAGE_SHIFT,
 279                            obj->base.size >> PAGE_SHIFT);
 280 }
 281
 282 void i915_gem_init_ppgtt(struct drm_device *dev)
 283 {
 284         drm_i915_private_t *dev_priv = dev->dev_private;
 285         uint32_t pd_offset;
 286         struct intel_ring_buffer *ring;
 287         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 288         gtt_pte_t __iomem *pd_addr;
 289         uint32_t pd_entry;
 290         int i;
 291
 292         if (!dev_priv->mm.aliasing_ppgtt)
 293                 return;
 294
 295
 296         pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
 297         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 298                 dma_addr_t pt_addr;
 299
 300                 pt_addr = ppgtt->pt_dma_addr[i];
 301                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 302                 pd_entry |= GEN6_PDE_VALID;
 303
 304                 writel(pd_entry, pd_addr + i);
 305         }
 306         readl(pd_addr);
 307
 308         pd_offset = ppgtt->pd_offset;
 309         pd_offset /= 64; /* in cachelines, */
 310         pd_offset <<= 16;
 311
 312         if (INTEL_INFO(dev)->gen == 6) {
 313                 uint32_t ecochk, gab_ctl, ecobits;
 314
 315                 ecobits = I915_READ(GAC_ECO_BITS);
 316                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 317
 318                 gab_ctl = I915_READ(GAB_CTL);
 319                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 320
 321                 ecochk = I915_READ(GAM_ECOCHK);
 322                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 323                                        ECOCHK_PPGTT_CACHE64B);
 324                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 325         } else if (INTEL_INFO(dev)->gen >= 7) {
 326                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 327                 /* GFX_MODE is per-ring on gen7+ */
 328         }
 329
 330         for_each_ring(ring, dev_priv, i) {
 331                 if (INTEL_INFO(dev)->gen >= 7)
 332                         I915_WRITE(RING_MODE_GEN7(ring),
 333                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 334
 335                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 336                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 337         }
 338 }
 339
 340 extern int intel_iommu_gfx_mapped;
 341 /* Certain Gen5 chipsets require require idling the GPU before
 342  * unmapping anything from the GTT when VT-d is enabled.
 343  */
 344 static inline bool needs_idle_maps(struct drm_device *dev)
 345 {
 346 #ifdef CONFIG_INTEL_IOMMU
 347         /* Query intel_iommu to see if we need the workaround. Presumably that
 348          * was loaded first.
 349          */
 350         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 351                 return true;
 352 #endif
 353         return false;
 354 }
 355
 356 static bool do_idling(struct drm_i915_private *dev_priv)
 357 {
 358         bool ret = dev_priv->mm.interruptible;
 359
 360         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 361                 dev_priv->mm.interruptible = false;
 362                 if (i915_gpu_idle(dev_priv->dev)) {
 363                         DRM_ERROR("Couldn't idle GPU\n");
 364                         /* Wait a bit, in hopes it avoids the hang */
 365                         udelay(10);
 366                 }
 367         }
 368
 369         return ret;
 370 }
 371
 372 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 373 {
 374         if (unlikely(dev_priv->gtt.do_idle_maps))
 375                 dev_priv->mm.interruptible = interruptible;
 376 }
 377
 378 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 379 {
 380         struct drm_i915_private *dev_priv = dev->dev_private;
 381         struct drm_i915_gem_object *obj;
 382
 383         /* First fill our portion of the GTT with scratch pages */
 384         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 385                                       dev_priv->gtt.total / PAGE_SIZE);
 386
 387         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 388                 i915_gem_clflush_object(obj);
 389                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 390         }
 391
 392         i915_gem_chipset_flush(dev);
 393 }
 394
 395 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 396 {
 397         if (obj->has_dma_mapping)
 398                 return 0;
 399
 400         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 401                         obj->pages->sgl, obj->pages->nents,
 402                         PCI_DMA_BIDIRECTIONAL))
 403                 return -ENOSPC;
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Binds an object into the global gtt with the specified cache level. The object
 410  * will be accessible to the GPU via commands whose operands reference offsets
 411  * within the global GTT as well as accessible by the GPU through the GMADR
 412  * mapped BAR (dev_priv->mm.gtt->gtt).
 413  */
 414 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 415                                      struct sg_table *st,
 416                                      unsigned int first_entry,
 417                                      enum i915_cache_level level)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420         gtt_pte_t __iomem *gtt_entries =
 421                 (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 422         int i = 0;
 423         struct sg_page_iter sg_iter;
 424         dma_addr_t addr;
 425
 426         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 427                 addr = sg_dma_address(sg_iter.sg) +
 428                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
 429                 iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]);
 430                 i++;
 431         }
 432
 433         /* XXX: This serves as a posting read to make sure that the PTE has
 434          * actually been updated. There is some concern that even though
 435          * registers and PTEs are within the same BAR that they are potentially
 436          * of NUMA access patterns. Therefore, even with the way we assume
 437          * hardware should work, we must keep this posting read for paranoia.
 438          */
 439         if (i != 0)
 440                 WARN_ON(readl(&gtt_entries[i-1])
 441                         != gen6_pte_encode(dev, addr, level));
 442
 443         /* This next bit makes the above posting read even more important. We
 444          * want to flush the TLBs only after we're certain all the PTE updates
 445          * have finished.
 446          */
 447         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 448         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 449 }
 450
 451 static void gen6_ggtt_clear_range(struct drm_device *dev,
 452                                   unsigned int first_entry,
 453                                   unsigned int num_entries)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         gtt_pte_t scratch_pte;
 457         gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 458         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 459         int i;
 460
 461         if (WARN(num_entries > max_entries,
 462                  "First entry = %d; Num entries = %d (max=%d)\n",
 463                  first_entry, num_entries, max_entries))
 464                 num_entries = max_entries;
 465
 466         scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
 467                                       I915_CACHE_LLC);
 468         for (i = 0; i < num_entries; i++)
 469                 iowrite32(scratch_pte, &gtt_base[i]);
 470         readl(gtt_base);
 471 }
 472
 473
 474 static void i915_ggtt_insert_entries(struct drm_device *dev,
 475                                      struct sg_table *st,
 476                                      unsigned int pg_start,
 477                                      enum i915_cache_level cache_level)
 478 {
 479         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 480                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 481
 482         intel_gtt_insert_sg_entries(st, pg_start, flags);
 483
 484 }
 485
 486 static void i915_ggtt_clear_range(struct drm_device *dev,
 487                                   unsigned int first_entry,
 488                                   unsigned int num_entries)
 489 {
 490         intel_gtt_clear_range(first_entry, num_entries);
 491 }
 492
 493
 494 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 495                               enum i915_cache_level cache_level)
 496 {
 497         struct drm_device *dev = obj->base.dev;
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499
 500         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 501                                          obj->gtt_space->start >> PAGE_SHIFT,
 502                                          cache_level);
 503
 504         obj->has_global_gtt_mapping = 1;
 505 }
 506
 507 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 508 {
 509         struct drm_device *dev = obj->base.dev;
 510         struct drm_i915_private *dev_priv = dev->dev_private;
 511
 512         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 513                                       obj->gtt_space->start >> PAGE_SHIFT,
 514                                       obj->base.size >> PAGE_SHIFT);
 515
 516         obj->has_global_gtt_mapping = 0;
 517 }
 518
 519 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 520 {
 521         struct drm_device *dev = obj->base.dev;
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         bool interruptible;
 524
 525         interruptible = do_idling(dev_priv);
 526
 527         if (!obj->has_dma_mapping)
 528                 dma_unmap_sg(&dev->pdev->dev,
 529                              obj->pages->sgl, obj->pages->nents,
 530                              PCI_DMA_BIDIRECTIONAL);
 531
 532         undo_idling(dev_priv, interruptible);
 533 }
 534
 535 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 536                                   unsigned long color,
 537                                   unsigned long *start,
 538                                   unsigned long *end)
 539 {
 540         if (node->color != color)
 541                 *start += 4096;
 542
 543         if (!list_empty(&node->node_list)) {
 544                 node = list_entry(node->node_list.next,
 545                                   struct drm_mm_node,
 546                                   node_list);
 547                 if (node->allocated && node->color != color)
 548                         *end -= 4096;
 549         }
 550 }
 551 void i915_gem_setup_global_gtt(struct drm_device *dev,
 552                                unsigned long start,
 553                                unsigned long mappable_end,
 554                                unsigned long end)
 555 {
 556         /* Let GEM Manage all of the aperture.
 557          *
 558          * However, leave one page at the end still bound to the scratch page.
 559          * There are a number of places where the hardware apparently prefetches
 560          * past the end of the object, and we've seen multiple hangs with the
 561          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 562          * aperture.  One page should be enough to keep any prefetching inside
 563          * of the aperture.
 564          */
 565         drm_i915_private_t *dev_priv = dev->dev_private;
 566         struct drm_mm_node *entry;
 567         struct drm_i915_gem_object *obj;
 568         unsigned long hole_start, hole_end;
 569
 570         BUG_ON(mappable_end > end);
 571
 572         /* Subtract the guard page ... */
 573         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 574         if (!HAS_LLC(dev))
 575                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 576
 577         /* Mark any preallocated objects as occupied */
 578         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 579                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 580                               obj->gtt_offset, obj->base.size);
 581
 582                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 583                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 584                                                      obj->gtt_offset,
 585                                                      obj->base.size,
 586                                                      false);
 587                 obj->has_global_gtt_mapping = 1;
 588         }
 589
 590         dev_priv->gtt.start = start;
 591         dev_priv->gtt.total = end - start;
 592
 593         /* Clear any non-preallocated blocks */
 594         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 595                              hole_start, hole_end) {
 596                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 597                               hole_start, hole_end);
 598                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 599                                               (hole_end-hole_start) / PAGE_SIZE);
 600         }
 601
 602         /* And finally clear the reserved guard page */
 603         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 604 }
 605
 606 static bool
 607 intel_enable_ppgtt(struct drm_device *dev)
 608 {
 609         if (i915_enable_ppgtt >= 0)
 610                 return i915_enable_ppgtt;
 611
 612 #ifdef CONFIG_INTEL_IOMMU
 613         /* Disable ppgtt on SNB if VT-d is on. */
 614         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 615                 return false;
 616 #endif
 617
 618         return true;
 619 }
 620
 621 void i915_gem_init_global_gtt(struct drm_device *dev)
 622 {
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624         unsigned long gtt_size, mappable_size;
 625
 626         gtt_size = dev_priv->gtt.total;
 627         mappable_size = dev_priv->gtt.mappable_end;
 628
 629         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 630                 int ret;
 631                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 632                  * aperture accordingly when using aliasing ppgtt. */
 633                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 634
 635                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 636
 637                 ret = i915_gem_init_aliasing_ppgtt(dev);
 638                 if (!ret)
 639                         return;
 640
 641                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 642                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 643                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 644         }
 645         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 646 }
 647
 648 static int setup_scratch_page(struct drm_device *dev)
 649 {
 650         struct drm_i915_private *dev_priv = dev->dev_private;
 651         struct page *page;
 652         dma_addr_t dma_addr;
 653
 654         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 655         if (page == NULL)
 656                 return -ENOMEM;
 657         get_page(page);
 658         set_pages_uc(page, 1);
 659
 660 #ifdef CONFIG_INTEL_IOMMU
 661         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 662                                 PCI_DMA_BIDIRECTIONAL);
 663         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 664                 return -EINVAL;
 665 #else
 666         dma_addr = page_to_phys(page);
 667 #endif
 668         dev_priv->gtt.scratch_page = page;
 669         dev_priv->gtt.scratch_page_dma = dma_addr;
 670
 671         return 0;
 672 }
 673
 674 static void teardown_scratch_page(struct drm_device *dev)
 675 {
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 678         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 679                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 680         put_page(dev_priv->gtt.scratch_page);
 681         __free_page(dev_priv->gtt.scratch_page);
 682 }
 683
 684 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 685 {
 686         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 687         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 688         return snb_gmch_ctl << 20;
 689 }
 690
 691 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 692 {
 693         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 694         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 695         return snb_gmch_ctl << 25; /* 32 MB units */
 696 }
 697
 698 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 699 {
 700         static const int stolen_decoder[] = {
 701                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 702         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 703         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 704         return stolen_decoder[snb_gmch_ctl] << 20;
 705 }
 706
 707 static int gen6_gmch_probe(struct drm_device *dev,
 708                            size_t *gtt_total,
 709                            size_t *stolen,
 710                            phys_addr_t *mappable_base,
 711                            unsigned long *mappable_end)
 712 {
 713         struct drm_i915_private *dev_priv = dev->dev_private;
 714         phys_addr_t gtt_bus_addr;
 715         unsigned int gtt_size;
 716         u16 snb_gmch_ctl;
 717         int ret;
 718
 719         *mappable_base = pci_resource_start(dev->pdev, 2);
 720         *mappable_end = pci_resource_len(dev->pdev, 2);
 721
 722         /* 64/512MB is the current min/max we actually know of, but this is just
 723          * a coarse sanity check.
 724          */
 725         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 726                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 727                           dev_priv->gtt.mappable_end);
 728                 return -ENXIO;
 729         }
 730
 731         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 732                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 733         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 734         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 735
 736         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 737                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 738         else
 739                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 740
 741         *gtt_total = (gtt_size / sizeof(gtt_pte_t)) << PAGE_SHIFT;
 742
 743         /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
 744         gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
 745         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 746         if (!dev_priv->gtt.gsm) {
 747                 DRM_ERROR("Failed to map the gtt page table\n");
 748                 return -ENOMEM;
 749         }
 750
 751         ret = setup_scratch_page(dev);
 752         if (ret)
 753                 DRM_ERROR("Scratch setup failed\n");
 754
 755         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 756         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 757
 758         return ret;
 759 }
 760
 761 static void gen6_gmch_remove(struct drm_device *dev)
 762 {
 763         struct drm_i915_private *dev_priv = dev->dev_private;
 764         iounmap(dev_priv->gtt.gsm);
 765         teardown_scratch_page(dev_priv->dev);
 766 }
 767
 768 static int i915_gmch_probe(struct drm_device *dev,
 769                            size_t *gtt_total,
 770                            size_t *stolen,
 771                            phys_addr_t *mappable_base,
 772                            unsigned long *mappable_end)
 773 {
 774         struct drm_i915_private *dev_priv = dev->dev_private;
 775         int ret;
 776
 777         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 778         if (!ret) {
 779                 DRM_ERROR("failed to set up gmch\n");
 780                 return -EIO;
 781         }
 782
 783         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 784
 785         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 786         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 787         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 788
 789         return 0;
 790 }
 791
 792 static void i915_gmch_remove(struct drm_device *dev)
 793 {
 794         intel_gmch_remove();
 795 }
 796
 797 int i915_gem_gtt_init(struct drm_device *dev)
 798 {
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         struct i915_gtt *gtt = &dev_priv->gtt;
 801         unsigned long gtt_size;
 802         int ret;
 803
 804         if (INTEL_INFO(dev)->gen <= 5) {
 805                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 806                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 807         } else {
 808                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 809                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 810         }
 811
 812         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 813                                      &dev_priv->gtt.stolen_size,
 814                                      &gtt->mappable_base,
 815                                      &gtt->mappable_end);
 816         if (ret)
 817                 return ret;
 818
 819         gtt_size = (dev_priv->gtt.total >> PAGE_SHIFT) * sizeof(gtt_pte_t);
 820
 821         /* GMADR is the PCI mmio aperture into the global GTT. */
 822         DRM_INFO("Memory usable by graphics device = %zdM\n",
 823                  dev_priv->gtt.total >> 20);
 824         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 825                          dev_priv->gtt.mappable_end >> 20);
 826         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 827                          dev_priv->gtt.stolen_size >> 20);
 828
 829         return 0;
 830 }