drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 #define GEN6_PPGTT_PD_ENTRIES 512
  32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  33
  34 /* PPGTT stuff */
  35 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  36 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  37
  38 #define GEN6_PDE_VALID                  (1 << 0)
  39 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  40 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  41
  42 #define GEN6_PTE_VALID                  (1 << 0)
  43 #define GEN6_PTE_UNCACHED               (1 << 1)
  44 #define HSW_PTE_UNCACHED                (0)
  45 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  46 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  47 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  48 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  49
  50 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
  51  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  52  */
  53 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  54                                          (((bits) & 0x8) << (11 - 3)))
  55 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  56 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  57 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  58 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  59
  60 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
  61                                      enum i915_cache_level level,
  62                                      bool valid)
  63 {
  64         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
  65         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  66
  67         switch (level) {
  68         case I915_CACHE_L3_LLC:
  69         case I915_CACHE_LLC:
  70                 pte |= GEN6_PTE_CACHE_LLC;
  71                 break;
  72         case I915_CACHE_NONE:
  73                 pte |= GEN6_PTE_UNCACHED;
  74                 break;
  75         default:
  76                 WARN_ON(1);
  77         }
  78
  79         return pte;
  80 }
  81
  82 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
  83                                      enum i915_cache_level level,
  84                                      bool valid)
  85 {
  86         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
  87         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  88
  89         switch (level) {
  90         case I915_CACHE_L3_LLC:
  91                 pte |= GEN7_PTE_CACHE_L3_LLC;
  92                 break;
  93         case I915_CACHE_LLC:
  94                 pte |= GEN6_PTE_CACHE_LLC;
  95                 break;
  96         case I915_CACHE_NONE:
  97                 pte |= GEN6_PTE_UNCACHED;
  98                 break;
  99         default:
 100                 WARN_ON(1);
 101         }
 102
 103         return pte;
 104 }
 105
 106 #define BYT_PTE_WRITEABLE               (1 << 1)
 107 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
 108
 109 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 110                                      enum i915_cache_level level,
 111                                      bool valid)
 112 {
 113         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 114         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 115
 116         /* Mark the page as writeable.  Other platforms don't have a
 117          * setting for read-only/writable, so this matches that behavior.
 118          */
 119         pte |= BYT_PTE_WRITEABLE;
 120
 121         if (level != I915_CACHE_NONE)
 122                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 123
 124         return pte;
 125 }
 126
 127 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 128                                      enum i915_cache_level level,
 129                                      bool valid)
 130 {
 131         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 132         pte |= HSW_PTE_ADDR_ENCODE(addr);
 133
 134         if (level != I915_CACHE_NONE)
 135                 pte |= HSW_WB_LLC_AGE3;
 136
 137         return pte;
 138 }
 139
 140 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 141                                       enum i915_cache_level level,
 142                                       bool valid)
 143 {
 144         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 145         pte |= HSW_PTE_ADDR_ENCODE(addr);
 146
 147         switch (level) {
 148         case I915_CACHE_NONE:
 149                 break;
 150         case I915_CACHE_WT:
 151                 pte |= HSW_WT_ELLC_LLC_AGE0;
 152                 break;
 153         default:
 154                 pte |= HSW_WB_ELLC_LLC_AGE0;
 155                 break;
 156         }
 157
 158         return pte;
 159 }
 160
 161 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 162 {
 163         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 164         gen6_gtt_pte_t __iomem *pd_addr;
 165         uint32_t pd_entry;
 166         int i;
 167
 168         WARN_ON(ppgtt->pd_offset & 0x3f);
 169         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 170                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 171         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 172                 dma_addr_t pt_addr;
 173
 174                 pt_addr = ppgtt->pt_dma_addr[i];
 175                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 176                 pd_entry |= GEN6_PDE_VALID;
 177
 178                 writel(pd_entry, pd_addr + i);
 179         }
 180         readl(pd_addr);
 181 }
 182
 183 static int gen6_ppgtt_enable(struct drm_device *dev)
 184 {
 185         drm_i915_private_t *dev_priv = dev->dev_private;
 186         uint32_t pd_offset;
 187         struct intel_ring_buffer *ring;
 188         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 189         int i;
 190
 191         BUG_ON(ppgtt->pd_offset & 0x3f);
 192
 193         gen6_write_pdes(ppgtt);
 194
 195         pd_offset = ppgtt->pd_offset;
 196         pd_offset /= 64; /* in cachelines, */
 197         pd_offset <<= 16;
 198
 199         if (INTEL_INFO(dev)->gen == 6) {
 200                 uint32_t ecochk, gab_ctl, ecobits;
 201
 202                 ecobits = I915_READ(GAC_ECO_BITS);
 203                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 204                                          ECOBITS_PPGTT_CACHE64B);
 205
 206                 gab_ctl = I915_READ(GAB_CTL);
 207                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 208
 209                 ecochk = I915_READ(GAM_ECOCHK);
 210                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 211                                        ECOCHK_PPGTT_CACHE64B);
 212                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 213         } else if (INTEL_INFO(dev)->gen >= 7) {
 214                 uint32_t ecochk, ecobits;
 215
 216                 ecobits = I915_READ(GAC_ECO_BITS);
 217                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 218
 219                 ecochk = I915_READ(GAM_ECOCHK);
 220                 if (IS_HASWELL(dev)) {
 221                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 222                 } else {
 223                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 224                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 225                 }
 226                 I915_WRITE(GAM_ECOCHK, ecochk);
 227                 /* GFX_MODE is per-ring on gen7+ */
 228         }
 229
 230         for_each_ring(ring, dev_priv, i) {
 231                 if (INTEL_INFO(dev)->gen >= 7)
 232                         I915_WRITE(RING_MODE_GEN7(ring),
 233                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 234
 235                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 236                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 237         }
 238         return 0;
 239 }
 240
 241 /* PPGTT support for Sandybdrige/Gen6 and later */
 242 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 243                                    unsigned first_entry,
 244                                    unsigned num_entries)
 245 {
 246         struct i915_hw_ppgtt *ppgtt =
 247                 container_of(vm, struct i915_hw_ppgtt, base);
 248         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 249         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 250         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 251         unsigned last_pte, i;
 252
 253         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 254
 255         while (num_entries) {
 256                 last_pte = first_pte + num_entries;
 257                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 258                         last_pte = I915_PPGTT_PT_ENTRIES;
 259
 260                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 261
 262                 for (i = first_pte; i < last_pte; i++)
 263                         pt_vaddr[i] = scratch_pte;
 264
 265                 kunmap_atomic(pt_vaddr);
 266
 267                 num_entries -= last_pte - first_pte;
 268                 first_pte = 0;
 269                 act_pt++;
 270         }
 271 }
 272
 273 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 274                                       struct sg_table *pages,
 275                                       unsigned first_entry,
 276                                       enum i915_cache_level cache_level)
 277 {
 278         struct i915_hw_ppgtt *ppgtt =
 279                 container_of(vm, struct i915_hw_ppgtt, base);
 280         gen6_gtt_pte_t *pt_vaddr;
 281         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 282         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 283         struct sg_page_iter sg_iter;
 284
 285         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 286         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 287                 dma_addr_t page_addr;
 288
 289                 page_addr = sg_page_iter_dma_address(&sg_iter);
 290                 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
 291                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 292                         kunmap_atomic(pt_vaddr);
 293                         act_pt++;
 294                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 295                         act_pte = 0;
 296
 297                 }
 298         }
 299         kunmap_atomic(pt_vaddr);
 300 }
 301
 302 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 303 {
 304         struct i915_hw_ppgtt *ppgtt =
 305                 container_of(vm, struct i915_hw_ppgtt, base);
 306         int i;
 307
 308         drm_mm_takedown(&ppgtt->base.mm);
 309
 310         if (ppgtt->pt_dma_addr) {
 311                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 312                         pci_unmap_page(ppgtt->base.dev->pdev,
 313                                        ppgtt->pt_dma_addr[i],
 314                                        4096, PCI_DMA_BIDIRECTIONAL);
 315         }
 316
 317         kfree(ppgtt->pt_dma_addr);
 318         for (i = 0; i < ppgtt->num_pd_entries; i++)
 319                 __free_page(ppgtt->pt_pages[i]);
 320         kfree(ppgtt->pt_pages);
 321         kfree(ppgtt);
 322 }
 323
 324 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 325 {
 326         struct drm_device *dev = ppgtt->base.dev;
 327         struct drm_i915_private *dev_priv = dev->dev_private;
 328         unsigned first_pd_entry_in_global_pt;
 329         int i;
 330         int ret = -ENOMEM;
 331
 332         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 333          * entries. For aliasing ppgtt support we just steal them at the end for
 334          * now. */
 335         first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
 336
 337         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
 338         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 339         ppgtt->enable = gen6_ppgtt_enable;
 340         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 341         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
 342         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 343         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 344         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 345                                   GFP_KERNEL);
 346         if (!ppgtt->pt_pages)
 347                 return -ENOMEM;
 348
 349         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 350                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 351                 if (!ppgtt->pt_pages[i])
 352                         goto err_pt_alloc;
 353         }
 354
 355         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 356                                      GFP_KERNEL);
 357         if (!ppgtt->pt_dma_addr)
 358                 goto err_pt_alloc;
 359
 360         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 361                 dma_addr_t pt_addr;
 362
 363                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 364                                        PCI_DMA_BIDIRECTIONAL);
 365
 366                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 367                         ret = -EIO;
 368                         goto err_pd_pin;
 369
 370                 }
 371                 ppgtt->pt_dma_addr[i] = pt_addr;
 372         }
 373
 374         ppgtt->base.clear_range(&ppgtt->base, 0,
 375                                 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES);
 376
 377         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 378
 379         return 0;
 380
 381 err_pd_pin:
 382         if (ppgtt->pt_dma_addr) {
 383                 for (i--; i >= 0; i--)
 384                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 385                                        4096, PCI_DMA_BIDIRECTIONAL);
 386         }
 387 err_pt_alloc:
 388         kfree(ppgtt->pt_dma_addr);
 389         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 390                 if (ppgtt->pt_pages[i])
 391                         __free_page(ppgtt->pt_pages[i]);
 392         }
 393         kfree(ppgtt->pt_pages);
 394
 395         return ret;
 396 }
 397
 398 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         struct i915_hw_ppgtt *ppgtt;
 402         int ret;
 403
 404         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 405         if (!ppgtt)
 406                 return -ENOMEM;
 407
 408         ppgtt->base.dev = dev;
 409
 410         if (INTEL_INFO(dev)->gen < 8)
 411                 ret = gen6_ppgtt_init(ppgtt);
 412         else
 413                 BUG();
 414
 415         if (ret)
 416                 kfree(ppgtt);
 417         else {
 418                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 419                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
 420                             ppgtt->base.total);
 421         }
 422
 423         return ret;
 424 }
 425
 426 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 427 {
 428         struct drm_i915_private *dev_priv = dev->dev_private;
 429         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 430
 431         if (!ppgtt)
 432                 return;
 433
 434         ppgtt->base.cleanup(&ppgtt->base);
 435         dev_priv->mm.aliasing_ppgtt = NULL;
 436 }
 437
 438 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 439                             struct drm_i915_gem_object *obj,
 440                             enum i915_cache_level cache_level)
 441 {
 442         ppgtt->base.insert_entries(&ppgtt->base, obj->pages,
 443                                    i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
 444                                    cache_level);
 445 }
 446
 447 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 448                               struct drm_i915_gem_object *obj)
 449 {
 450         ppgtt->base.clear_range(&ppgtt->base,
 451                                 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
 452                                 obj->base.size >> PAGE_SHIFT);
 453 }
 454
 455 extern int intel_iommu_gfx_mapped;
 456 /* Certain Gen5 chipsets require require idling the GPU before
 457  * unmapping anything from the GTT when VT-d is enabled.
 458  */
 459 static inline bool needs_idle_maps(struct drm_device *dev)
 460 {
 461 #ifdef CONFIG_INTEL_IOMMU
 462         /* Query intel_iommu to see if we need the workaround. Presumably that
 463          * was loaded first.
 464          */
 465         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 466                 return true;
 467 #endif
 468         return false;
 469 }
 470
 471 static bool do_idling(struct drm_i915_private *dev_priv)
 472 {
 473         bool ret = dev_priv->mm.interruptible;
 474
 475         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 476                 dev_priv->mm.interruptible = false;
 477                 if (i915_gpu_idle(dev_priv->dev)) {
 478                         DRM_ERROR("Couldn't idle GPU\n");
 479                         /* Wait a bit, in hopes it avoids the hang */
 480                         udelay(10);
 481                 }
 482         }
 483
 484         return ret;
 485 }
 486
 487 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 488 {
 489         if (unlikely(dev_priv->gtt.do_idle_maps))
 490                 dev_priv->mm.interruptible = interruptible;
 491 }
 492
 493 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 494 {
 495         struct drm_i915_private *dev_priv = dev->dev_private;
 496         struct drm_i915_gem_object *obj;
 497
 498         /* First fill our portion of the GTT with scratch pages */
 499         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 500                                        dev_priv->gtt.base.start / PAGE_SIZE,
 501                                        dev_priv->gtt.base.total / PAGE_SIZE);
 502
 503         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 504                 i915_gem_clflush_object(obj, obj->pin_display);
 505                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 506         }
 507
 508         i915_gem_chipset_flush(dev);
 509 }
 510
 511 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 512 {
 513         if (obj->has_dma_mapping)
 514                 return 0;
 515
 516         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 517                         obj->pages->sgl, obj->pages->nents,
 518                         PCI_DMA_BIDIRECTIONAL))
 519                 return -ENOSPC;
 520
 521         return 0;
 522 }
 523
 524 /*
 525  * Binds an object into the global gtt with the specified cache level. The object
 526  * will be accessible to the GPU via commands whose operands reference offsets
 527  * within the global GTT as well as accessible by the GPU through the GMADR
 528  * mapped BAR (dev_priv->mm.gtt->gtt).
 529  */
 530 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 531                                      struct sg_table *st,
 532                                      unsigned int first_entry,
 533                                      enum i915_cache_level level)
 534 {
 535         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 536         gen6_gtt_pte_t __iomem *gtt_entries =
 537                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 538         int i = 0;
 539         struct sg_page_iter sg_iter;
 540         dma_addr_t addr;
 541
 542         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 543                 addr = sg_page_iter_dma_address(&sg_iter);
 544                 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
 545                 i++;
 546         }
 547
 548         /* XXX: This serves as a posting read to make sure that the PTE has
 549          * actually been updated. There is some concern that even though
 550          * registers and PTEs are within the same BAR that they are potentially
 551          * of NUMA access patterns. Therefore, even with the way we assume
 552          * hardware should work, we must keep this posting read for paranoia.
 553          */
 554         if (i != 0)
 555                 WARN_ON(readl(&gtt_entries[i-1]) !=
 556                         vm->pte_encode(addr, level, true));
 557
 558         /* This next bit makes the above posting read even more important. We
 559          * want to flush the TLBs only after we're certain all the PTE updates
 560          * have finished.
 561          */
 562         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 563         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 564 }
 565
 566 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 567                                   unsigned int first_entry,
 568                                   unsigned int num_entries)
 569 {
 570         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 571         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 572                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 573         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 574         int i;
 575
 576         if (WARN(num_entries > max_entries,
 577                  "First entry = %d; Num entries = %d (max=%d)\n",
 578                  first_entry, num_entries, max_entries))
 579                 num_entries = max_entries;
 580
 581         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 582         for (i = 0; i < num_entries; i++)
 583                 iowrite32(scratch_pte, &gtt_base[i]);
 584         readl(gtt_base);
 585 }
 586
 587
 588 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 589                                      struct sg_table *st,
 590                                      unsigned int pg_start,
 591                                      enum i915_cache_level cache_level)
 592 {
 593         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 594                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 595
 596         intel_gtt_insert_sg_entries(st, pg_start, flags);
 597
 598 }
 599
 600 static void i915_ggtt_clear_range(struct i915_address_space *vm,
 601                                   unsigned int first_entry,
 602                                   unsigned int num_entries)
 603 {
 604         intel_gtt_clear_range(first_entry, num_entries);
 605 }
 606
 607
 608 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 609                               enum i915_cache_level cache_level)
 610 {
 611         struct drm_device *dev = obj->base.dev;
 612         struct drm_i915_private *dev_priv = dev->dev_private;
 613         const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
 614
 615         dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages,
 616                                           entry,
 617                                           cache_level);
 618
 619         obj->has_global_gtt_mapping = 1;
 620 }
 621
 622 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 623 {
 624         struct drm_device *dev = obj->base.dev;
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626         const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
 627
 628         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 629                                        entry,
 630                                        obj->base.size >> PAGE_SHIFT);
 631
 632         obj->has_global_gtt_mapping = 0;
 633 }
 634
 635 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 636 {
 637         struct drm_device *dev = obj->base.dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         bool interruptible;
 640
 641         interruptible = do_idling(dev_priv);
 642
 643         if (!obj->has_dma_mapping)
 644                 dma_unmap_sg(&dev->pdev->dev,
 645                              obj->pages->sgl, obj->pages->nents,
 646                              PCI_DMA_BIDIRECTIONAL);
 647
 648         undo_idling(dev_priv, interruptible);
 649 }
 650
 651 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 652                                   unsigned long color,
 653                                   unsigned long *start,
 654                                   unsigned long *end)
 655 {
 656         if (node->color != color)
 657                 *start += 4096;
 658
 659         if (!list_empty(&node->node_list)) {
 660                 node = list_entry(node->node_list.next,
 661                                   struct drm_mm_node,
 662                                   node_list);
 663                 if (node->allocated && node->color != color)
 664                         *end -= 4096;
 665         }
 666 }
 667 void i915_gem_setup_global_gtt(struct drm_device *dev,
 668                                unsigned long start,
 669                                unsigned long mappable_end,
 670                                unsigned long end)
 671 {
 672         /* Let GEM Manage all of the aperture.
 673          *
 674          * However, leave one page at the end still bound to the scratch page.
 675          * There are a number of places where the hardware apparently prefetches
 676          * past the end of the object, and we've seen multiple hangs with the
 677          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 678          * aperture.  One page should be enough to keep any prefetching inside
 679          * of the aperture.
 680          */
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
 683         struct drm_mm_node *entry;
 684         struct drm_i915_gem_object *obj;
 685         unsigned long hole_start, hole_end;
 686
 687         BUG_ON(mappable_end > end);
 688
 689         /* Subtract the guard page ... */
 690         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
 691         if (!HAS_LLC(dev))
 692                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
 693
 694         /* Mark any preallocated objects as occupied */
 695         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 696                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
 697                 int ret;
 698                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
 699                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
 700
 701                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
 702                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
 703                 if (ret)
 704                         DRM_DEBUG_KMS("Reservation failed\n");
 705                 obj->has_global_gtt_mapping = 1;
 706                 list_add(&vma->vma_link, &obj->vma_list);
 707         }
 708
 709         dev_priv->gtt.base.start = start;
 710         dev_priv->gtt.base.total = end - start;
 711
 712         /* Clear any non-preallocated blocks */
 713         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
 714                 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
 715                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 716                               hole_start, hole_end);
 717                 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count);
 718         }
 719
 720         /* And finally clear the reserved guard page */
 721         ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1);
 722 }
 723
 724 static bool
 725 intel_enable_ppgtt(struct drm_device *dev)
 726 {
 727         if (i915_enable_ppgtt >= 0)
 728                 return i915_enable_ppgtt;
 729
 730 #ifdef CONFIG_INTEL_IOMMU
 731         /* Disable ppgtt on SNB if VT-d is on. */
 732         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 733                 return false;
 734 #endif
 735
 736         return true;
 737 }
 738
 739 void i915_gem_init_global_gtt(struct drm_device *dev)
 740 {
 741         struct drm_i915_private *dev_priv = dev->dev_private;
 742         unsigned long gtt_size, mappable_size;
 743
 744         gtt_size = dev_priv->gtt.base.total;
 745         mappable_size = dev_priv->gtt.mappable_end;
 746
 747         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 748                 int ret;
 749
 750                 if (INTEL_INFO(dev)->gen <= 7) {
 751                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 752                          * aperture accordingly when using aliasing ppgtt. */
 753                         gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
 754                 }
 755
 756                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 757
 758                 ret = i915_gem_init_aliasing_ppgtt(dev);
 759                 if (!ret)
 760                         return;
 761
 762                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 763                 drm_mm_takedown(&dev_priv->gtt.base.mm);
 764                 gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
 765         }
 766         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 767 }
 768
 769 static int setup_scratch_page(struct drm_device *dev)
 770 {
 771         struct drm_i915_private *dev_priv = dev->dev_private;
 772         struct page *page;
 773         dma_addr_t dma_addr;
 774
 775         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 776         if (page == NULL)
 777                 return -ENOMEM;
 778         get_page(page);
 779         set_pages_uc(page, 1);
 780
 781 #ifdef CONFIG_INTEL_IOMMU
 782         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 783                                 PCI_DMA_BIDIRECTIONAL);
 784         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 785                 return -EINVAL;
 786 #else
 787         dma_addr = page_to_phys(page);
 788 #endif
 789         dev_priv->gtt.base.scratch.page = page;
 790         dev_priv->gtt.base.scratch.addr = dma_addr;
 791
 792         return 0;
 793 }
 794
 795 static void teardown_scratch_page(struct drm_device *dev)
 796 {
 797         struct drm_i915_private *dev_priv = dev->dev_private;
 798         struct page *page = dev_priv->gtt.base.scratch.page;
 799
 800         set_pages_wb(page, 1);
 801         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
 802                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 803         put_page(page);
 804         __free_page(page);
 805 }
 806
 807 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 808 {
 809         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 810         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 811         return snb_gmch_ctl << 20;
 812 }
 813
 814 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 815 {
 816         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 817         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 818         return snb_gmch_ctl << 25; /* 32 MB units */
 819 }
 820
 821 static int gen6_gmch_probe(struct drm_device *dev,
 822                            size_t *gtt_total,
 823                            size_t *stolen,
 824                            phys_addr_t *mappable_base,
 825                            unsigned long *mappable_end)
 826 {
 827         struct drm_i915_private *dev_priv = dev->dev_private;
 828         phys_addr_t gtt_bus_addr;
 829         unsigned int gtt_size;
 830         u16 snb_gmch_ctl;
 831         int ret;
 832
 833         *mappable_base = pci_resource_start(dev->pdev, 2);
 834         *mappable_end = pci_resource_len(dev->pdev, 2);
 835
 836         /* 64/512MB is the current min/max we actually know of, but this is just
 837          * a coarse sanity check.
 838          */
 839         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 840                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 841                           dev_priv->gtt.mappable_end);
 842                 return -ENXIO;
 843         }
 844
 845         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 846                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 847         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 848         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 849
 850         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 851         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 852
 853         /* For Modern GENs the PTEs and register space are split in the BAR */
 854         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 855                 (pci_resource_len(dev->pdev, 0) / 2);
 856
 857         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 858         if (!dev_priv->gtt.gsm) {
 859                 DRM_ERROR("Failed to map the gtt page table\n");
 860                 return -ENOMEM;
 861         }
 862
 863         ret = setup_scratch_page(dev);
 864         if (ret)
 865                 DRM_ERROR("Scratch setup failed\n");
 866
 867         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
 868         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
 869
 870         return ret;
 871 }
 872
 873 static void gen6_gmch_remove(struct i915_address_space *vm)
 874 {
 875
 876         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
 877         iounmap(gtt->gsm);
 878         teardown_scratch_page(vm->dev);
 879 }
 880
 881 static int i915_gmch_probe(struct drm_device *dev,
 882                            size_t *gtt_total,
 883                            size_t *stolen,
 884                            phys_addr_t *mappable_base,
 885                            unsigned long *mappable_end)
 886 {
 887         struct drm_i915_private *dev_priv = dev->dev_private;
 888         int ret;
 889
 890         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 891         if (!ret) {
 892                 DRM_ERROR("failed to set up gmch\n");
 893                 return -EIO;
 894         }
 895
 896         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 897
 898         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 899         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
 900         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
 901
 902         return 0;
 903 }
 904
 905 static void i915_gmch_remove(struct i915_address_space *vm)
 906 {
 907         intel_gmch_remove();
 908 }
 909
 910 int i915_gem_gtt_init(struct drm_device *dev)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         struct i915_gtt *gtt = &dev_priv->gtt;
 914         int ret;
 915
 916         if (INTEL_INFO(dev)->gen <= 5) {
 917                 gtt->gtt_probe = i915_gmch_probe;
 918                 gtt->base.cleanup = i915_gmch_remove;
 919         } else {
 920                 gtt->gtt_probe = gen6_gmch_probe;
 921                 gtt->base.cleanup = gen6_gmch_remove;
 922                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
 923                         gtt->base.pte_encode = iris_pte_encode;
 924                 else if (IS_HASWELL(dev))
 925                         gtt->base.pte_encode = hsw_pte_encode;
 926                 else if (IS_VALLEYVIEW(dev))
 927                         gtt->base.pte_encode = byt_pte_encode;
 928                 else if (INTEL_INFO(dev)->gen >= 7)
 929                         gtt->base.pte_encode = ivb_pte_encode;
 930                 else
 931                         gtt->base.pte_encode = snb_pte_encode;
 932         }
 933
 934         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
 935                              &gtt->mappable_base, &gtt->mappable_end);
 936         if (ret)
 937                 return ret;
 938
 939         gtt->base.dev = dev;
 940
 941         /* GMADR is the PCI mmio aperture into the global GTT. */
 942         DRM_INFO("Memory usable by graphics device = %zdM\n",
 943                  gtt->base.total >> 20);
 944         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
 945         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
 946
 947         return 0;
 948 }