2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35 #include <linux/uaccess.h>
37 #define __EXEC_OBJECT_HAS_PIN (1<<31)
38 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
39 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
40 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
42 #define BATCH_OFFSET_BIAS (256*1024)
45 struct list_head vmas;
48 struct i915_vma *lut[0];
49 struct hlist_head buckets[0];
53 static struct eb_vmas *
54 eb_create(struct drm_i915_gem_execbuffer2 *args)
56 struct eb_vmas *eb = NULL;
58 if (args->flags & I915_EXEC_HANDLE_LUT) {
59 unsigned size = args->buffer_count;
60 size *= sizeof(struct i915_vma *);
61 size += sizeof(struct eb_vmas);
62 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
66 unsigned size = args->buffer_count;
67 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
68 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
69 while (count > 2*size)
71 eb = kzalloc(count*sizeof(struct hlist_head) +
72 sizeof(struct eb_vmas),
79 eb->and = -args->buffer_count;
81 INIT_LIST_HEAD(&eb->vmas);
86 eb_reset(struct eb_vmas *eb)
89 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
93 eb_lookup_vmas(struct eb_vmas *eb,
94 struct drm_i915_gem_exec_object2 *exec,
95 const struct drm_i915_gem_execbuffer2 *args,
96 struct i915_address_space *vm,
97 struct drm_file *file)
99 struct drm_i915_gem_object *obj;
100 struct list_head objects;
103 INIT_LIST_HEAD(&objects);
104 spin_lock(&file->table_lock);
105 /* Grab a reference to the object and release the lock so we can lookup
106 * or create the VMA without using GFP_ATOMIC */
107 for (i = 0; i < args->buffer_count; i++) {
108 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
110 spin_unlock(&file->table_lock);
111 DRM_DEBUG("Invalid object handle %d at index %d\n",
117 if (!list_empty(&obj->obj_exec_link)) {
118 spin_unlock(&file->table_lock);
119 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
120 obj, exec[i].handle, i);
125 drm_gem_object_reference(&obj->base);
126 list_add_tail(&obj->obj_exec_link, &objects);
128 spin_unlock(&file->table_lock);
131 while (!list_empty(&objects)) {
132 struct i915_vma *vma;
134 obj = list_first_entry(&objects,
135 struct drm_i915_gem_object,
139 * NOTE: We can leak any vmas created here when something fails
140 * later on. But that's no issue since vma_unbind can deal with
141 * vmas which are not actually bound. And since only
142 * lookup_or_create exists as an interface to get at the vma
143 * from the (obj, vm) we don't run the risk of creating
144 * duplicated vmas for the same vm.
146 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
148 DRM_DEBUG("Failed to lookup VMA\n");
153 /* Transfer ownership from the objects list to the vmas list. */
154 list_add_tail(&vma->exec_list, &eb->vmas);
155 list_del_init(&obj->obj_exec_link);
157 vma->exec_entry = &exec[i];
161 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
162 vma->exec_handle = handle;
163 hlist_add_head(&vma->exec_node,
164 &eb->buckets[handle & eb->and]);
173 while (!list_empty(&objects)) {
174 obj = list_first_entry(&objects,
175 struct drm_i915_gem_object,
177 list_del_init(&obj->obj_exec_link);
178 drm_gem_object_unreference(&obj->base);
181 * Objects already transfered to the vmas list will be unreferenced by
188 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
191 if (handle >= -eb->and)
193 return eb->lut[handle];
195 struct hlist_head *head;
196 struct i915_vma *vma;
198 head = &eb->buckets[handle & eb->and];
199 hlist_for_each_entry(vma, head, exec_node) {
200 if (vma->exec_handle == handle)
208 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
210 struct drm_i915_gem_exec_object2 *entry;
211 struct drm_i915_gem_object *obj = vma->obj;
213 if (!drm_mm_node_allocated(&vma->node))
216 entry = vma->exec_entry;
218 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
219 i915_gem_object_unpin_fence(obj);
221 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
224 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
227 static void eb_destroy(struct eb_vmas *eb)
229 while (!list_empty(&eb->vmas)) {
230 struct i915_vma *vma;
232 vma = list_first_entry(&eb->vmas,
235 list_del_init(&vma->exec_list);
236 i915_gem_execbuffer_unreserve_vma(vma);
237 drm_gem_object_unreference(&vma->obj->base);
242 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
244 return (HAS_LLC(obj->base.dev) ||
245 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
246 obj->cache_level != I915_CACHE_NONE);
249 /* Used to convert any address to canonical form.
250 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
251 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
252 * addresses to be in a canonical form:
253 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
254 * canonical form [63:48] == [47]."
256 #define GEN8_HIGH_ADDRESS_BIT 47
257 static inline uint64_t gen8_canonical_addr(uint64_t address)
259 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
262 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
264 return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
267 static inline uint64_t
268 relocation_target(struct drm_i915_gem_relocation_entry *reloc,
269 uint64_t target_offset)
271 return gen8_canonical_addr((int)reloc->delta + target_offset);
275 relocate_entry_cpu(struct drm_i915_gem_object *obj,
276 struct drm_i915_gem_relocation_entry *reloc,
277 uint64_t target_offset)
279 struct drm_device *dev = obj->base.dev;
280 uint32_t page_offset = offset_in_page(reloc->offset);
281 uint64_t delta = relocation_target(reloc, target_offset);
285 ret = i915_gem_object_set_to_cpu_domain(obj, true);
289 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
290 reloc->offset >> PAGE_SHIFT));
291 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
293 if (INTEL_INFO(dev)->gen >= 8) {
294 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
296 if (page_offset == 0) {
297 kunmap_atomic(vaddr);
298 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
299 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
302 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
305 kunmap_atomic(vaddr);
311 relocate_entry_gtt(struct drm_i915_gem_object *obj,
312 struct drm_i915_gem_relocation_entry *reloc,
313 uint64_t target_offset)
315 struct drm_device *dev = obj->base.dev;
316 struct drm_i915_private *dev_priv = to_i915(dev);
317 struct i915_ggtt *ggtt = &dev_priv->ggtt;
318 uint64_t delta = relocation_target(reloc, target_offset);
320 void __iomem *reloc_page;
323 ret = i915_gem_object_set_to_gtt_domain(obj, true);
327 ret = i915_gem_object_put_fence(obj);
331 /* Map the page containing the relocation we're going to perform. */
332 offset = i915_gem_obj_ggtt_offset(obj);
333 offset += reloc->offset;
334 reloc_page = io_mapping_map_atomic_wc(ggtt->mappable,
336 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
338 if (INTEL_INFO(dev)->gen >= 8) {
339 offset += sizeof(uint32_t);
341 if (offset_in_page(offset) == 0) {
342 io_mapping_unmap_atomic(reloc_page);
344 io_mapping_map_atomic_wc(ggtt->mappable,
348 iowrite32(upper_32_bits(delta),
349 reloc_page + offset_in_page(offset));
352 io_mapping_unmap_atomic(reloc_page);
358 clflush_write32(void *addr, uint32_t value)
360 /* This is not a fast path, so KISS. */
361 drm_clflush_virt_range(addr, sizeof(uint32_t));
362 *(uint32_t *)addr = value;
363 drm_clflush_virt_range(addr, sizeof(uint32_t));
367 relocate_entry_clflush(struct drm_i915_gem_object *obj,
368 struct drm_i915_gem_relocation_entry *reloc,
369 uint64_t target_offset)
371 struct drm_device *dev = obj->base.dev;
372 uint32_t page_offset = offset_in_page(reloc->offset);
373 uint64_t delta = relocation_target(reloc, target_offset);
377 ret = i915_gem_object_set_to_gtt_domain(obj, true);
381 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
382 reloc->offset >> PAGE_SHIFT));
383 clflush_write32(vaddr + page_offset, lower_32_bits(delta));
385 if (INTEL_INFO(dev)->gen >= 8) {
386 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
388 if (page_offset == 0) {
389 kunmap_atomic(vaddr);
390 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
391 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
394 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
397 kunmap_atomic(vaddr);
403 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
405 struct drm_i915_gem_relocation_entry *reloc)
407 struct drm_device *dev = obj->base.dev;
408 struct drm_gem_object *target_obj;
409 struct drm_i915_gem_object *target_i915_obj;
410 struct i915_vma *target_vma;
411 uint64_t target_offset;
414 /* we've already hold a reference to all valid objects */
415 target_vma = eb_get_vma(eb, reloc->target_handle);
416 if (unlikely(target_vma == NULL))
418 target_i915_obj = target_vma->obj;
419 target_obj = &target_vma->obj->base;
421 target_offset = gen8_canonical_addr(target_vma->node.start);
423 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
424 * pipe_control writes because the gpu doesn't properly redirect them
425 * through the ppgtt for non_secure batchbuffers. */
426 if (unlikely(IS_GEN6(dev) &&
427 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
428 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
430 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
434 /* Validate that the target is in a valid r/w GPU domain */
435 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
436 DRM_DEBUG("reloc with multiple write domains: "
437 "obj %p target %d offset %d "
438 "read %08x write %08x",
439 obj, reloc->target_handle,
442 reloc->write_domain);
445 if (unlikely((reloc->write_domain | reloc->read_domains)
446 & ~I915_GEM_GPU_DOMAINS)) {
447 DRM_DEBUG("reloc with read/write non-GPU domains: "
448 "obj %p target %d offset %d "
449 "read %08x write %08x",
450 obj, reloc->target_handle,
453 reloc->write_domain);
457 target_obj->pending_read_domains |= reloc->read_domains;
458 target_obj->pending_write_domain |= reloc->write_domain;
460 /* If the relocation already has the right value in it, no
461 * more work needs to be done.
463 if (target_offset == reloc->presumed_offset)
466 /* Check that the relocation address is valid... */
467 if (unlikely(reloc->offset >
468 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
469 DRM_DEBUG("Relocation beyond object bounds: "
470 "obj %p target %d offset %d size %d.\n",
471 obj, reloc->target_handle,
473 (int) obj->base.size);
476 if (unlikely(reloc->offset & 3)) {
477 DRM_DEBUG("Relocation not 4-byte aligned: "
478 "obj %p target %d offset %d.\n",
479 obj, reloc->target_handle,
480 (int) reloc->offset);
484 /* We can't wait for rendering with pagefaults disabled */
485 if (obj->active && pagefault_disabled())
488 if (use_cpu_reloc(obj))
489 ret = relocate_entry_cpu(obj, reloc, target_offset);
490 else if (obj->map_and_fenceable)
491 ret = relocate_entry_gtt(obj, reloc, target_offset);
492 else if (cpu_has_clflush)
493 ret = relocate_entry_clflush(obj, reloc, target_offset);
495 WARN_ONCE(1, "Impossible case in relocation handling\n");
502 /* and update the user's relocation entry */
503 reloc->presumed_offset = target_offset;
509 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
512 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
513 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
514 struct drm_i915_gem_relocation_entry __user *user_relocs;
515 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
518 user_relocs = to_user_ptr(entry->relocs_ptr);
520 remain = entry->relocation_count;
522 struct drm_i915_gem_relocation_entry *r = stack_reloc;
524 if (count > ARRAY_SIZE(stack_reloc))
525 count = ARRAY_SIZE(stack_reloc);
528 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
532 u64 offset = r->presumed_offset;
534 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
538 if (r->presumed_offset != offset &&
539 __copy_to_user_inatomic(&user_relocs->presumed_offset,
541 sizeof(r->presumed_offset))) {
555 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
557 struct drm_i915_gem_relocation_entry *relocs)
559 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
562 for (i = 0; i < entry->relocation_count; i++) {
563 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
572 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
574 struct i915_vma *vma;
577 /* This is the fast path and we cannot handle a pagefault whilst
578 * holding the struct mutex lest the user pass in the relocations
579 * contained within a mmaped bo. For in such a case we, the page
580 * fault handler would call i915_gem_fault() and we would try to
581 * acquire the struct mutex again. Obviously this is bad and so
582 * lockdep complains vehemently.
585 list_for_each_entry(vma, &eb->vmas, exec_list) {
586 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
595 static bool only_mappable_for_reloc(unsigned int flags)
597 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
598 __EXEC_OBJECT_NEEDS_MAP;
602 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
603 struct intel_engine_cs *engine,
606 struct drm_i915_gem_object *obj = vma->obj;
607 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
612 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
615 if (!drm_mm_node_allocated(&vma->node)) {
616 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
617 * limit address to the first 4GBs for unflagged objects.
619 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
620 flags |= PIN_ZONE_4G;
621 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
622 flags |= PIN_GLOBAL | PIN_MAPPABLE;
623 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
624 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
625 if (entry->flags & EXEC_OBJECT_PINNED)
626 flags |= entry->offset | PIN_OFFSET_FIXED;
627 if ((flags & PIN_MAPPABLE) == 0)
631 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
632 if ((ret == -ENOSPC || ret == -E2BIG) &&
633 only_mappable_for_reloc(entry->flags))
634 ret = i915_gem_object_pin(obj, vma->vm,
636 flags & ~PIN_MAPPABLE);
640 entry->flags |= __EXEC_OBJECT_HAS_PIN;
642 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
643 ret = i915_gem_object_get_fence(obj);
647 if (i915_gem_object_pin_fence(obj))
648 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
651 if (entry->offset != vma->node.start) {
652 entry->offset = vma->node.start;
656 if (entry->flags & EXEC_OBJECT_WRITE) {
657 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
658 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
665 need_reloc_mappable(struct i915_vma *vma)
667 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
669 if (entry->relocation_count == 0)
675 /* See also use_cpu_reloc() */
676 if (HAS_LLC(vma->obj->base.dev))
679 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
686 eb_vma_misplaced(struct i915_vma *vma)
688 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
689 struct drm_i915_gem_object *obj = vma->obj;
691 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt);
693 if (entry->alignment &&
694 vma->node.start & (entry->alignment - 1))
697 if (entry->flags & EXEC_OBJECT_PINNED &&
698 vma->node.start != entry->offset)
701 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
702 vma->node.start < BATCH_OFFSET_BIAS)
705 /* avoid costly ping-pong once a batch bo ended up non-mappable */
706 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
707 return !only_mappable_for_reloc(entry->flags);
709 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
710 (vma->node.start + vma->node.size - 1) >> 32)
717 i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
718 struct list_head *vmas,
719 struct intel_context *ctx,
722 struct drm_i915_gem_object *obj;
723 struct i915_vma *vma;
724 struct i915_address_space *vm;
725 struct list_head ordered_vmas;
726 struct list_head pinned_vmas;
727 bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4;
730 i915_gem_retire_requests_ring(engine);
732 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
734 INIT_LIST_HEAD(&ordered_vmas);
735 INIT_LIST_HEAD(&pinned_vmas);
736 while (!list_empty(vmas)) {
737 struct drm_i915_gem_exec_object2 *entry;
738 bool need_fence, need_mappable;
740 vma = list_first_entry(vmas, struct i915_vma, exec_list);
742 entry = vma->exec_entry;
744 if (ctx->flags & CONTEXT_NO_ZEROMAP)
745 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
747 if (!has_fenced_gpu_access)
748 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
750 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
751 obj->tiling_mode != I915_TILING_NONE;
752 need_mappable = need_fence || need_reloc_mappable(vma);
754 if (entry->flags & EXEC_OBJECT_PINNED)
755 list_move_tail(&vma->exec_list, &pinned_vmas);
756 else if (need_mappable) {
757 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
758 list_move(&vma->exec_list, &ordered_vmas);
760 list_move_tail(&vma->exec_list, &ordered_vmas);
762 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
763 obj->base.pending_write_domain = 0;
765 list_splice(&ordered_vmas, vmas);
766 list_splice(&pinned_vmas, vmas);
768 /* Attempt to pin all of the buffers into the GTT.
769 * This is done in 3 phases:
771 * 1a. Unbind all objects that do not match the GTT constraints for
772 * the execbuffer (fenceable, mappable, alignment etc).
773 * 1b. Increment pin count for already bound objects.
774 * 2. Bind new objects.
775 * 3. Decrement pin count.
777 * This avoid unnecessary unbinding of later objects in order to make
778 * room for the earlier objects *unless* we need to defragment.
784 /* Unbind any ill-fitting objects or pin. */
785 list_for_each_entry(vma, vmas, exec_list) {
786 if (!drm_mm_node_allocated(&vma->node))
789 if (eb_vma_misplaced(vma))
790 ret = i915_vma_unbind(vma);
792 ret = i915_gem_execbuffer_reserve_vma(vma,
799 /* Bind fresh objects */
800 list_for_each_entry(vma, vmas, exec_list) {
801 if (drm_mm_node_allocated(&vma->node))
804 ret = i915_gem_execbuffer_reserve_vma(vma, engine,
811 if (ret != -ENOSPC || retry++)
814 /* Decrement pin count for bound objects */
815 list_for_each_entry(vma, vmas, exec_list)
816 i915_gem_execbuffer_unreserve_vma(vma);
818 ret = i915_gem_evict_vm(vm, true);
825 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
826 struct drm_i915_gem_execbuffer2 *args,
827 struct drm_file *file,
828 struct intel_engine_cs *engine,
830 struct drm_i915_gem_exec_object2 *exec,
831 struct intel_context *ctx)
833 struct drm_i915_gem_relocation_entry *reloc;
834 struct i915_address_space *vm;
835 struct i915_vma *vma;
839 unsigned count = args->buffer_count;
841 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
843 /* We may process another execbuffer during the unlock... */
844 while (!list_empty(&eb->vmas)) {
845 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
846 list_del_init(&vma->exec_list);
847 i915_gem_execbuffer_unreserve_vma(vma);
848 drm_gem_object_unreference(&vma->obj->base);
851 mutex_unlock(&dev->struct_mutex);
854 for (i = 0; i < count; i++)
855 total += exec[i].relocation_count;
857 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
858 reloc = drm_malloc_ab(total, sizeof(*reloc));
859 if (reloc == NULL || reloc_offset == NULL) {
860 drm_free_large(reloc);
861 drm_free_large(reloc_offset);
862 mutex_lock(&dev->struct_mutex);
867 for (i = 0; i < count; i++) {
868 struct drm_i915_gem_relocation_entry __user *user_relocs;
869 u64 invalid_offset = (u64)-1;
872 user_relocs = to_user_ptr(exec[i].relocs_ptr);
874 if (copy_from_user(reloc+total, user_relocs,
875 exec[i].relocation_count * sizeof(*reloc))) {
877 mutex_lock(&dev->struct_mutex);
881 /* As we do not update the known relocation offsets after
882 * relocating (due to the complexities in lock handling),
883 * we need to mark them as invalid now so that we force the
884 * relocation processing next time. Just in case the target
885 * object is evicted and then rebound into its old
886 * presumed_offset before the next execbuffer - if that
887 * happened we would make the mistake of assuming that the
888 * relocations were valid.
890 for (j = 0; j < exec[i].relocation_count; j++) {
891 if (__copy_to_user(&user_relocs[j].presumed_offset,
893 sizeof(invalid_offset))) {
895 mutex_lock(&dev->struct_mutex);
900 reloc_offset[i] = total;
901 total += exec[i].relocation_count;
904 ret = i915_mutex_lock_interruptible(dev);
906 mutex_lock(&dev->struct_mutex);
910 /* reacquire the objects */
912 ret = eb_lookup_vmas(eb, exec, args, vm, file);
916 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
917 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
922 list_for_each_entry(vma, &eb->vmas, exec_list) {
923 int offset = vma->exec_entry - exec;
924 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
925 reloc + reloc_offset[offset]);
930 /* Leave the user relocations as are, this is the painfully slow path,
931 * and we want to avoid the complication of dropping the lock whilst
932 * having buffers reserved in the aperture and so causing spurious
933 * ENOSPC for random operations.
937 drm_free_large(reloc);
938 drm_free_large(reloc_offset);
943 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
944 struct list_head *vmas)
946 const unsigned other_rings = ~intel_engine_flag(req->engine);
947 struct i915_vma *vma;
948 uint32_t flush_domains = 0;
949 bool flush_chipset = false;
952 list_for_each_entry(vma, vmas, exec_list) {
953 struct drm_i915_gem_object *obj = vma->obj;
955 if (obj->active & other_rings) {
956 ret = i915_gem_object_sync(obj, req->engine, &req);
961 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
962 flush_chipset |= i915_gem_clflush_object(obj, false);
964 flush_domains |= obj->base.write_domain;
968 i915_gem_chipset_flush(req->engine->dev);
970 if (flush_domains & I915_GEM_DOMAIN_GTT)
973 /* Unconditionally invalidate gpu caches and ensure that we do flush
974 * any residual writes from the previous batch.
976 return intel_ring_invalidate_all_caches(req);
980 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
982 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
985 /* Kernel clipping was a DRI1 misfeature */
986 if (exec->num_cliprects || exec->cliprects_ptr)
989 if (exec->DR4 == 0xffffffff) {
990 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
993 if (exec->DR1 || exec->DR4)
996 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1003 validate_exec_list(struct drm_device *dev,
1004 struct drm_i915_gem_exec_object2 *exec,
1007 unsigned relocs_total = 0;
1008 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1009 unsigned invalid_flags;
1012 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1013 if (USES_FULL_PPGTT(dev))
1014 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1016 for (i = 0; i < count; i++) {
1017 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
1018 int length; /* limited by fault_in_pages_readable() */
1020 if (exec[i].flags & invalid_flags)
1023 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1024 * any non-page-aligned or non-canonical addresses.
1026 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1027 if (exec[i].offset !=
1028 gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1031 /* From drm_mm perspective address space is continuous,
1032 * so from this point we're always using non-canonical
1035 exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1038 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1041 /* First check for malicious input causing overflow in
1042 * the worst case where we need to allocate the entire
1043 * relocation tree as a single array.
1045 if (exec[i].relocation_count > relocs_max - relocs_total)
1047 relocs_total += exec[i].relocation_count;
1049 length = exec[i].relocation_count *
1050 sizeof(struct drm_i915_gem_relocation_entry);
1052 * We must check that the entire relocation array is safe
1053 * to read, but since we may need to update the presumed
1054 * offsets during execution, check for full write access.
1056 if (!access_ok(VERIFY_WRITE, ptr, length))
1059 if (likely(!i915.prefault_disable)) {
1060 if (fault_in_multipages_readable(ptr, length))
1068 static struct intel_context *
1069 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1070 struct intel_engine_cs *engine, const u32 ctx_id)
1072 struct intel_context *ctx = NULL;
1073 struct i915_ctx_hang_stats *hs;
1075 if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
1076 return ERR_PTR(-EINVAL);
1078 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
1082 hs = &ctx->hang_stats;
1084 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1085 return ERR_PTR(-EIO);
1088 if (i915.enable_execlists && !ctx->engine[engine->id].state) {
1089 int ret = intel_lr_context_deferred_alloc(ctx, engine);
1091 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
1092 return ERR_PTR(ret);
1100 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1101 struct drm_i915_gem_request *req)
1103 struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1104 struct i915_vma *vma;
1106 list_for_each_entry(vma, vmas, exec_list) {
1107 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1108 struct drm_i915_gem_object *obj = vma->obj;
1109 u32 old_read = obj->base.read_domains;
1110 u32 old_write = obj->base.write_domain;
1112 obj->dirty = 1; /* be paranoid */
1113 obj->base.write_domain = obj->base.pending_write_domain;
1114 if (obj->base.write_domain == 0)
1115 obj->base.pending_read_domains |= obj->base.read_domains;
1116 obj->base.read_domains = obj->base.pending_read_domains;
1118 i915_vma_move_to_active(vma, req);
1119 if (obj->base.write_domain) {
1120 i915_gem_request_assign(&obj->last_write_req, req);
1122 intel_fb_obj_invalidate(obj, ORIGIN_CS);
1124 /* update for the implicit flush after a batch */
1125 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1127 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1128 i915_gem_request_assign(&obj->last_fenced_req, req);
1129 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1130 struct drm_i915_private *dev_priv = to_i915(engine->dev);
1131 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1132 &dev_priv->mm.fence_list);
1136 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1141 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
1143 /* Unconditionally force add_request to emit a full flush. */
1144 params->engine->gpu_caches_dirty = true;
1146 /* Add a breadcrumb for the completion of the batch buffer */
1147 __i915_add_request(params->request, params->batch_obj, true);
1151 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1152 struct drm_i915_gem_request *req)
1154 struct intel_engine_cs *engine = req->engine;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1158 if (!IS_GEN7(dev) || engine != &dev_priv->engine[RCS]) {
1159 DRM_DEBUG("sol reset is gen7/rcs only\n");
1163 ret = intel_ring_begin(req, 4 * 3);
1167 for (i = 0; i < 4; i++) {
1168 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
1169 intel_ring_emit_reg(engine, GEN7_SO_WRITE_OFFSET(i));
1170 intel_ring_emit(engine, 0);
1173 intel_ring_advance(engine);
1178 static struct drm_i915_gem_object*
1179 i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1180 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1182 struct drm_i915_gem_object *batch_obj,
1183 u32 batch_start_offset,
1187 struct drm_i915_gem_object *shadow_batch_obj;
1188 struct i915_vma *vma;
1191 shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1192 PAGE_ALIGN(batch_len));
1193 if (IS_ERR(shadow_batch_obj))
1194 return shadow_batch_obj;
1196 ret = i915_parse_cmds(engine,
1205 ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1209 i915_gem_object_unpin_pages(shadow_batch_obj);
1211 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1213 vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1214 vma->exec_entry = shadow_exec_entry;
1215 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1216 drm_gem_object_reference(&shadow_batch_obj->base);
1217 list_add_tail(&vma->exec_list, &eb->vmas);
1219 shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1221 return shadow_batch_obj;
1224 i915_gem_object_unpin_pages(shadow_batch_obj);
1225 if (ret == -EACCES) /* unhandled chained batch */
1228 return ERR_PTR(ret);
1232 i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
1233 struct drm_i915_gem_execbuffer2 *args,
1234 struct list_head *vmas)
1236 struct drm_device *dev = params->dev;
1237 struct intel_engine_cs *engine = params->engine;
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 u64 exec_start, exec_len;
1244 ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1248 ret = i915_switch_context(params->request);
1252 WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<engine->id),
1253 "%s didn't clear reload\n", engine->name);
1255 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1256 instp_mask = I915_EXEC_CONSTANTS_MASK;
1257 switch (instp_mode) {
1258 case I915_EXEC_CONSTANTS_REL_GENERAL:
1259 case I915_EXEC_CONSTANTS_ABSOLUTE:
1260 case I915_EXEC_CONSTANTS_REL_SURFACE:
1261 if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
1262 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1266 if (instp_mode != dev_priv->relative_constants_mode) {
1267 if (INTEL_INFO(dev)->gen < 4) {
1268 DRM_DEBUG("no rel constants on pre-gen4\n");
1272 if (INTEL_INFO(dev)->gen > 5 &&
1273 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1274 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1278 /* The HW changed the meaning on this bit on gen6 */
1279 if (INTEL_INFO(dev)->gen >= 6)
1280 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1284 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1288 if (engine == &dev_priv->engine[RCS] &&
1289 instp_mode != dev_priv->relative_constants_mode) {
1290 ret = intel_ring_begin(params->request, 4);
1294 intel_ring_emit(engine, MI_NOOP);
1295 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
1296 intel_ring_emit_reg(engine, INSTPM);
1297 intel_ring_emit(engine, instp_mask << 16 | instp_mode);
1298 intel_ring_advance(engine);
1300 dev_priv->relative_constants_mode = instp_mode;
1303 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1304 ret = i915_reset_gen7_sol_offsets(dev, params->request);
1309 exec_len = args->batch_len;
1310 exec_start = params->batch_obj_vm_offset +
1311 params->args_batch_start_offset;
1314 exec_len = params->batch_obj->base.size;
1316 ret = engine->dispatch_execbuffer(params->request,
1317 exec_start, exec_len,
1318 params->dispatch_flags);
1322 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1324 i915_gem_execbuffer_move_to_active(vmas, params->request);
1325 i915_gem_execbuffer_retire_commands(params);
1331 * Find one BSD ring to dispatch the corresponding BSD command.
1332 * The ring index is returned.
1335 gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file *file)
1337 struct drm_i915_file_private *file_priv = file->driver_priv;
1339 /* Check whether the file_priv has already selected one ring. */
1340 if ((int)file_priv->bsd_ring < 0) {
1341 /* If not, use the ping-pong mechanism to select one. */
1342 mutex_lock(&dev_priv->dev->struct_mutex);
1343 file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index;
1344 dev_priv->mm.bsd_ring_dispatch_index ^= 1;
1345 mutex_unlock(&dev_priv->dev->struct_mutex);
1348 return file_priv->bsd_ring;
1351 static struct drm_i915_gem_object *
1352 eb_get_batch(struct eb_vmas *eb)
1354 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1357 * SNA is doing fancy tricks with compressing batch buffers, which leads
1358 * to negative relocation deltas. Usually that works out ok since the
1359 * relocate address is still positive, except when the batch is placed
1360 * very low in the GTT. Ensure this doesn't happen.
1362 * Note that actual hangs have only been observed on gen7, but for
1363 * paranoia do it everywhere.
1365 if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
1366 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1371 #define I915_USER_RINGS (4)
1373 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1374 [I915_EXEC_DEFAULT] = RCS,
1375 [I915_EXEC_RENDER] = RCS,
1376 [I915_EXEC_BLT] = BCS,
1377 [I915_EXEC_BSD] = VCS,
1378 [I915_EXEC_VEBOX] = VECS
1382 eb_select_ring(struct drm_i915_private *dev_priv,
1383 struct drm_file *file,
1384 struct drm_i915_gem_execbuffer2 *args,
1385 struct intel_engine_cs **ring)
1387 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1389 if (user_ring_id > I915_USER_RINGS) {
1390 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1394 if ((user_ring_id != I915_EXEC_BSD) &&
1395 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1396 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1397 "bsd dispatch flags: %d\n", (int)(args->flags));
1401 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1402 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1404 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1405 bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file);
1406 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1407 bsd_idx <= I915_EXEC_BSD_RING2) {
1408 bsd_idx >>= I915_EXEC_BSD_SHIFT;
1411 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1416 *ring = &dev_priv->engine[_VCS(bsd_idx)];
1418 *ring = &dev_priv->engine[user_ring_map[user_ring_id]];
1421 if (!intel_engine_initialized(*ring)) {
1422 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1430 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1431 struct drm_file *file,
1432 struct drm_i915_gem_execbuffer2 *args,
1433 struct drm_i915_gem_exec_object2 *exec)
1435 struct drm_i915_private *dev_priv = to_i915(dev);
1436 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1437 struct drm_i915_gem_request *req = NULL;
1439 struct drm_i915_gem_object *batch_obj;
1440 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1441 struct intel_engine_cs *engine;
1442 struct intel_context *ctx;
1443 struct i915_address_space *vm;
1444 struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1445 struct i915_execbuffer_params *params = ¶ms_master;
1446 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1451 if (!i915_gem_check_execbuffer(args))
1454 ret = validate_exec_list(dev, exec, args->buffer_count);
1459 if (args->flags & I915_EXEC_SECURE) {
1460 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1463 dispatch_flags |= I915_DISPATCH_SECURE;
1465 if (args->flags & I915_EXEC_IS_PINNED)
1466 dispatch_flags |= I915_DISPATCH_PINNED;
1468 ret = eb_select_ring(dev_priv, file, args, &engine);
1472 if (args->buffer_count < 1) {
1473 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1477 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1478 if (!HAS_RESOURCE_STREAMER(dev)) {
1479 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1482 if (engine->id != RCS) {
1483 DRM_DEBUG("RS is not available on %s\n",
1488 dispatch_flags |= I915_DISPATCH_RS;
1491 intel_runtime_pm_get(dev_priv);
1493 ret = i915_mutex_lock_interruptible(dev);
1497 ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1499 mutex_unlock(&dev->struct_mutex);
1504 i915_gem_context_reference(ctx);
1507 vm = &ctx->ppgtt->base;
1511 memset(¶ms_master, 0x00, sizeof(params_master));
1513 eb = eb_create(args);
1515 i915_gem_context_unreference(ctx);
1516 mutex_unlock(&dev->struct_mutex);
1521 /* Look up object handles */
1522 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1526 /* take note of the batch buffer before we might reorder the lists */
1527 batch_obj = eb_get_batch(eb);
1529 /* Move the objects en-masse into the GTT, evicting if necessary. */
1530 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1531 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1536 /* The objects are in their final locations, apply the relocations. */
1538 ret = i915_gem_execbuffer_relocate(eb);
1540 if (ret == -EFAULT) {
1541 ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1544 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1550 /* Set the pending read domains for the batch buffer to COMMAND */
1551 if (batch_obj->base.pending_write_domain) {
1552 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1557 params->args_batch_start_offset = args->batch_start_offset;
1558 if (i915_needs_cmd_parser(engine) && args->batch_len) {
1559 struct drm_i915_gem_object *parsed_batch_obj;
1561 parsed_batch_obj = i915_gem_execbuffer_parse(engine,
1565 args->batch_start_offset,
1568 if (IS_ERR(parsed_batch_obj)) {
1569 ret = PTR_ERR(parsed_batch_obj);
1574 * parsed_batch_obj == batch_obj means batch not fully parsed:
1575 * Accept, but don't promote to secure.
1578 if (parsed_batch_obj != batch_obj) {
1580 * Batch parsed and accepted:
1582 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1583 * bit from MI_BATCH_BUFFER_START commands issued in
1584 * the dispatch_execbuffer implementations. We
1585 * specifically don't want that set on batches the
1586 * command parser has accepted.
1588 dispatch_flags |= I915_DISPATCH_SECURE;
1589 params->args_batch_start_offset = 0;
1590 batch_obj = parsed_batch_obj;
1594 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1596 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1597 * batch" bit. Hence we need to pin secure batches into the global gtt.
1598 * hsw should have this fixed, but bdw mucks it up again. */
1599 if (dispatch_flags & I915_DISPATCH_SECURE) {
1601 * So on first glance it looks freaky that we pin the batch here
1602 * outside of the reservation loop. But:
1603 * - The batch is already pinned into the relevant ppgtt, so we
1604 * already have the backing storage fully allocated.
1605 * - No other BO uses the global gtt (well contexts, but meh),
1606 * so we don't really have issues with multiple objects not
1607 * fitting due to fragmentation.
1608 * So this is actually safe.
1610 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1614 params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
1616 params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
1618 /* Allocate a request for this batch buffer nice and early. */
1619 req = i915_gem_request_alloc(engine, ctx);
1622 goto err_batch_unpin;
1625 ret = i915_gem_request_add_to_client(req, file);
1627 goto err_batch_unpin;
1630 * Save assorted stuff away to pass through to *_submission().
1631 * NB: This data should be 'persistent' and not local as it will
1632 * kept around beyond the duration of the IOCTL once the GPU
1633 * scheduler arrives.
1636 params->file = file;
1637 params->engine = engine;
1638 params->dispatch_flags = dispatch_flags;
1639 params->batch_obj = batch_obj;
1641 params->request = req;
1643 ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
1647 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1648 * batch vma for correctness. For less ugly and less fragility this
1649 * needs to be adjusted to also track the ggtt batch vma properly as
1652 if (dispatch_flags & I915_DISPATCH_SECURE)
1653 i915_gem_object_ggtt_unpin(batch_obj);
1656 /* the request owns the ref now */
1657 i915_gem_context_unreference(ctx);
1661 * If the request was created but not successfully submitted then it
1662 * must be freed again. If it was submitted then it is being tracked
1663 * on the active request list and no clean up is required here.
1665 if (ret && !IS_ERR_OR_NULL(req))
1666 i915_gem_request_cancel(req);
1668 mutex_unlock(&dev->struct_mutex);
1671 /* intel_gpu_busy should also get a ref, so it will free when the device
1672 * is really idle. */
1673 intel_runtime_pm_put(dev_priv);
1678 * Legacy execbuffer just creates an exec2 list from the original exec object
1679 * list array and passes it to the real function.
1682 i915_gem_execbuffer(struct drm_device *dev, void *data,
1683 struct drm_file *file)
1685 struct drm_i915_gem_execbuffer *args = data;
1686 struct drm_i915_gem_execbuffer2 exec2;
1687 struct drm_i915_gem_exec_object *exec_list = NULL;
1688 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1691 if (args->buffer_count < 1) {
1692 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1696 /* Copy in the exec list from userland */
1697 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1698 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1699 if (exec_list == NULL || exec2_list == NULL) {
1700 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1701 args->buffer_count);
1702 drm_free_large(exec_list);
1703 drm_free_large(exec2_list);
1706 ret = copy_from_user(exec_list,
1707 to_user_ptr(args->buffers_ptr),
1708 sizeof(*exec_list) * args->buffer_count);
1710 DRM_DEBUG("copy %d exec entries failed %d\n",
1711 args->buffer_count, ret);
1712 drm_free_large(exec_list);
1713 drm_free_large(exec2_list);
1717 for (i = 0; i < args->buffer_count; i++) {
1718 exec2_list[i].handle = exec_list[i].handle;
1719 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1720 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1721 exec2_list[i].alignment = exec_list[i].alignment;
1722 exec2_list[i].offset = exec_list[i].offset;
1723 if (INTEL_INFO(dev)->gen < 4)
1724 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1726 exec2_list[i].flags = 0;
1729 exec2.buffers_ptr = args->buffers_ptr;
1730 exec2.buffer_count = args->buffer_count;
1731 exec2.batch_start_offset = args->batch_start_offset;
1732 exec2.batch_len = args->batch_len;
1733 exec2.DR1 = args->DR1;
1734 exec2.DR4 = args->DR4;
1735 exec2.num_cliprects = args->num_cliprects;
1736 exec2.cliprects_ptr = args->cliprects_ptr;
1737 exec2.flags = I915_EXEC_RENDER;
1738 i915_execbuffer2_set_context_id(exec2, 0);
1740 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1742 struct drm_i915_gem_exec_object __user *user_exec_list =
1743 to_user_ptr(args->buffers_ptr);
1745 /* Copy the new buffer offsets back to the user's exec list. */
1746 for (i = 0; i < args->buffer_count; i++) {
1747 exec2_list[i].offset =
1748 gen8_canonical_addr(exec2_list[i].offset);
1749 ret = __copy_to_user(&user_exec_list[i].offset,
1750 &exec2_list[i].offset,
1751 sizeof(user_exec_list[i].offset));
1754 DRM_DEBUG("failed to copy %d exec entries "
1755 "back to user (%d)\n",
1756 args->buffer_count, ret);
1762 drm_free_large(exec_list);
1763 drm_free_large(exec2_list);
1768 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1769 struct drm_file *file)
1771 struct drm_i915_gem_execbuffer2 *args = data;
1772 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1775 if (args->buffer_count < 1 ||
1776 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1777 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1781 if (args->rsvd2 != 0) {
1782 DRM_DEBUG("dirty rvsd2 field\n");
1786 exec2_list = drm_malloc_gfp(args->buffer_count,
1787 sizeof(*exec2_list),
1789 if (exec2_list == NULL) {
1790 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1791 args->buffer_count);
1794 ret = copy_from_user(exec2_list,
1795 to_user_ptr(args->buffers_ptr),
1796 sizeof(*exec2_list) * args->buffer_count);
1798 DRM_DEBUG("copy %d exec entries failed %d\n",
1799 args->buffer_count, ret);
1800 drm_free_large(exec2_list);
1804 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1806 /* Copy the new buffer offsets back to the user's exec list. */
1807 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1808 to_user_ptr(args->buffers_ptr);
1811 for (i = 0; i < args->buffer_count; i++) {
1812 exec2_list[i].offset =
1813 gen8_canonical_addr(exec2_list[i].offset);
1814 ret = __copy_to_user(&user_exec_list[i].offset,
1815 &exec2_list[i].offset,
1816 sizeof(user_exec_list[i].offset));
1819 DRM_DEBUG("failed to copy %d exec entries "
1821 args->buffer_count);
1827 drm_free_large(exec2_list);