2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 static int get_context_size(struct drm_i915_private *dev_priv)
100 switch (INTEL_GEN(dev_priv)) {
102 reg = I915_READ(CXT_SIZE);
103 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
106 reg = I915_READ(GEN7_CXT_SIZE);
107 if (IS_HASWELL(dev_priv))
108 ret = HSW_CXT_TOTAL_SIZE;
110 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
113 ret = GEN8_CXT_TOTAL_SIZE;
122 void i915_gem_context_free(struct kref *ctx_ref)
124 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
127 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
128 trace_i915_context_free(ctx);
129 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
131 i915_ppgtt_put(ctx->ppgtt);
133 for (i = 0; i < I915_NUM_ENGINES; i++) {
134 struct intel_context *ce = &ctx->engine[i];
139 WARN_ON(ce->pin_count);
141 intel_ring_free(ce->ring);
143 __i915_gem_object_release_unless_active(ce->state->obj);
148 list_del(&ctx->link);
150 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
154 static struct drm_i915_gem_object *
155 alloc_context_obj(struct drm_i915_private *dev_priv, u64 size)
157 struct drm_i915_gem_object *obj;
160 lockdep_assert_held(&dev_priv->drm.struct_mutex);
162 obj = i915_gem_object_create(dev_priv, size);
167 * Try to make the context utilize L3 as well as LLC.
169 * On VLV we don't have L3 controls in the PTEs so we
170 * shouldn't touch the cache level, especially as that
171 * would make the object snooped which might have a
172 * negative performance impact.
174 * Snooping is required on non-llc platforms in execlist
175 * mode, but since all GGTT accesses use PAT entry 0 we
176 * get snooping anyway regardless of cache_level.
178 * This is only applicable for Ivy Bridge devices since
179 * later platforms don't have L3 control bits in the PTE.
181 if (IS_IVYBRIDGE(dev_priv)) {
182 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
183 /* Failure shouldn't ever happen this early */
185 i915_gem_object_put(obj);
193 static void context_close(struct i915_gem_context *ctx)
195 i915_gem_context_set_closed(ctx);
197 i915_ppgtt_close(&ctx->ppgtt->base);
198 ctx->file_priv = ERR_PTR(-EBADF);
199 i915_gem_context_put(ctx);
202 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
206 ret = ida_simple_get(&dev_priv->context_hw_ida,
207 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
209 /* Contexts are only released when no longer active.
210 * Flush any pending retires to hopefully release some
211 * stale contexts and try again.
213 i915_gem_retire_requests(dev_priv);
214 ret = ida_simple_get(&dev_priv->context_hw_ida,
215 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
224 static u32 default_desc_template(const struct drm_i915_private *i915,
225 const struct i915_hw_ppgtt *ppgtt)
230 desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
232 address_mode = INTEL_LEGACY_32B_CONTEXT;
233 if (ppgtt && i915_vm_is_48bit(&ppgtt->base))
234 address_mode = INTEL_LEGACY_64B_CONTEXT;
235 desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
238 desc |= GEN8_CTX_L3LLC_COHERENT;
240 /* TODO: WaDisableLiteRestore when we start using semaphore
241 * signalling between Command Streamers
242 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
248 static struct i915_gem_context *
249 __create_hw_context(struct drm_i915_private *dev_priv,
250 struct drm_i915_file_private *file_priv)
252 struct i915_gem_context *ctx;
255 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
257 return ERR_PTR(-ENOMEM);
259 ret = assign_hw_id(dev_priv, &ctx->hw_id);
265 kref_init(&ctx->ref);
266 list_add_tail(&ctx->link, &dev_priv->context_list);
267 ctx->i915 = dev_priv;
269 if (dev_priv->hw_context_size) {
270 struct drm_i915_gem_object *obj;
271 struct i915_vma *vma;
273 obj = alloc_context_obj(dev_priv, dev_priv->hw_context_size);
279 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
281 i915_gem_object_put(obj);
286 ctx->engine[RCS].state = vma;
289 /* Default context will never have a file_priv */
290 ret = DEFAULT_CONTEXT_HANDLE;
292 ret = idr_alloc(&file_priv->context_idr, ctx,
293 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
297 ctx->user_handle = ret;
299 ctx->file_priv = file_priv;
301 ctx->pid = get_task_pid(current, PIDTYPE_PID);
302 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
312 /* NB: Mark all slices as needing a remap so that when the context first
313 * loads it will restore whatever remap state already exists. If there
314 * is no remap info, it will be a NOP. */
315 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
317 i915_gem_context_set_bannable(ctx);
318 ctx->ring_size = 4 * PAGE_SIZE;
320 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
321 ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
323 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
324 * present or not in use we still need a small bias as ring wraparound
325 * at offset 0 sometimes hangs. No idea why.
327 if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
328 ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
330 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
336 idr_remove(&file_priv->context_idr, ctx->user_handle);
342 static void __destroy_hw_context(struct i915_gem_context *ctx,
343 struct drm_i915_file_private *file_priv)
345 idr_remove(&file_priv->context_idr, ctx->user_handle);
350 * The default context needs to exist per ring that uses contexts. It stores the
351 * context state of the GPU for applications that don't utilize HW contexts, as
352 * well as an idle case.
354 static struct i915_gem_context *
355 i915_gem_create_context(struct drm_i915_private *dev_priv,
356 struct drm_i915_file_private *file_priv)
358 struct i915_gem_context *ctx;
360 lockdep_assert_held(&dev_priv->drm.struct_mutex);
362 ctx = __create_hw_context(dev_priv, file_priv);
366 if (USES_FULL_PPGTT(dev_priv)) {
367 struct i915_hw_ppgtt *ppgtt;
369 ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name);
371 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
373 __destroy_hw_context(ctx, file_priv);
374 return ERR_CAST(ppgtt);
378 ctx->desc_template = default_desc_template(dev_priv, ppgtt);
381 trace_i915_context_create(ctx);
387 * i915_gem_context_create_gvt - create a GVT GEM context
390 * This function is used to create a GVT specific GEM context.
393 * pointer to i915_gem_context on success, error pointer if failed
396 struct i915_gem_context *
397 i915_gem_context_create_gvt(struct drm_device *dev)
399 struct i915_gem_context *ctx;
402 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
403 return ERR_PTR(-ENODEV);
405 ret = i915_mutex_lock_interruptible(dev);
409 ctx = __create_hw_context(to_i915(dev), NULL);
413 ctx->file_priv = ERR_PTR(-EBADF);
414 i915_gem_context_set_closed(ctx); /* not user accessible */
415 i915_gem_context_clear_bannable(ctx);
416 i915_gem_context_set_force_single_submission(ctx);
417 if (!i915.enable_guc_submission)
418 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
420 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
422 mutex_unlock(&dev->struct_mutex);
426 int i915_gem_context_init(struct drm_i915_private *dev_priv)
428 struct i915_gem_context *ctx;
430 /* Init should only be called once per module load. Eventually the
431 * restriction on the context_disabled check can be loosened. */
432 if (WARN_ON(dev_priv->kernel_context))
435 if (intel_vgpu_active(dev_priv) &&
436 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
437 if (!i915.enable_execlists) {
438 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
443 /* Using the simple ida interface, the max is limited by sizeof(int) */
444 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
445 ida_init(&dev_priv->context_hw_ida);
447 if (i915.enable_execlists) {
448 /* NB: intentionally left blank. We will allocate our own
449 * backing objects as we need them, thank you very much */
450 dev_priv->hw_context_size = 0;
451 } else if (HAS_HW_CONTEXTS(dev_priv)) {
452 dev_priv->hw_context_size =
453 round_up(get_context_size(dev_priv),
455 if (dev_priv->hw_context_size > (1<<20)) {
456 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
457 dev_priv->hw_context_size);
458 dev_priv->hw_context_size = 0;
462 ctx = i915_gem_create_context(dev_priv, NULL);
464 DRM_ERROR("Failed to create default global context (error %ld)\n",
469 /* For easy recognisablity, we want the kernel context to be 0 and then
470 * all user contexts will have non-zero hw_id.
472 GEM_BUG_ON(ctx->hw_id);
474 i915_gem_context_clear_bannable(ctx);
475 ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
476 dev_priv->kernel_context = ctx;
478 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
480 DRM_DEBUG_DRIVER("%s context support initialized\n",
481 i915.enable_execlists ? "LR" :
482 dev_priv->hw_context_size ? "HW" : "fake");
486 void i915_gem_context_lost(struct drm_i915_private *dev_priv)
488 struct intel_engine_cs *engine;
489 enum intel_engine_id id;
491 lockdep_assert_held(&dev_priv->drm.struct_mutex);
493 for_each_engine(engine, dev_priv, id) {
494 engine->legacy_active_context = NULL;
496 if (!engine->last_retired_context)
499 engine->context_unpin(engine, engine->last_retired_context);
500 engine->last_retired_context = NULL;
503 /* Force the GPU state to be restored on enabling */
504 if (!i915.enable_execlists) {
505 struct i915_gem_context *ctx;
507 list_for_each_entry(ctx, &dev_priv->context_list, link) {
508 if (!i915_gem_context_is_default(ctx))
511 for_each_engine(engine, dev_priv, id)
512 ctx->engine[engine->id].initialised = false;
514 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
517 for_each_engine(engine, dev_priv, id) {
518 struct intel_context *kce =
519 &dev_priv->kernel_context->engine[engine->id];
521 kce->initialised = true;
526 void i915_gem_context_fini(struct drm_i915_private *dev_priv)
528 struct i915_gem_context *dctx = dev_priv->kernel_context;
530 lockdep_assert_held(&dev_priv->drm.struct_mutex);
532 GEM_BUG_ON(!i915_gem_context_is_kernel(dctx));
535 dev_priv->kernel_context = NULL;
537 ida_destroy(&dev_priv->context_hw_ida);
540 static int context_idr_cleanup(int id, void *p, void *data)
542 struct i915_gem_context *ctx = p;
548 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
550 struct drm_i915_file_private *file_priv = file->driver_priv;
551 struct i915_gem_context *ctx;
553 idr_init(&file_priv->context_idr);
555 mutex_lock(&dev->struct_mutex);
556 ctx = i915_gem_create_context(to_i915(dev), file_priv);
557 mutex_unlock(&dev->struct_mutex);
559 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
562 idr_destroy(&file_priv->context_idr);
569 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
571 struct drm_i915_file_private *file_priv = file->driver_priv;
573 lockdep_assert_held(&dev->struct_mutex);
575 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
576 idr_destroy(&file_priv->context_idr);
580 mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
582 struct drm_i915_private *dev_priv = req->i915;
583 struct intel_engine_cs *engine = req->engine;
584 enum intel_engine_id id;
585 u32 *cs, flags = hw_flags | MI_MM_SPACE_GTT;
586 const int num_rings =
587 /* Use an extended w/a on ivb+ if signalling from other rings */
589 INTEL_INFO(dev_priv)->num_rings - 1 :
593 /* These flags are for resource streamer on HSW+ */
594 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
595 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
596 else if (INTEL_GEN(dev_priv) < 8)
597 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
601 if (INTEL_GEN(dev_priv) >= 7)
602 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
604 cs = intel_ring_begin(req, len);
608 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
609 if (INTEL_GEN(dev_priv) >= 7) {
610 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
612 struct intel_engine_cs *signaller;
614 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
615 for_each_engine(signaller, dev_priv, id) {
616 if (signaller == engine)
619 *cs++ = i915_mmio_reg_offset(
620 RING_PSMI_CTL(signaller->mmio_base));
621 *cs++ = _MASKED_BIT_ENABLE(
622 GEN6_PSMI_SLEEP_MSG_DISABLE);
628 *cs++ = MI_SET_CONTEXT;
629 *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
631 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
632 * WaMiSetContext_Hang:snb,ivb,vlv
636 if (INTEL_GEN(dev_priv) >= 7) {
638 struct intel_engine_cs *signaller;
639 i915_reg_t last_reg = {}; /* keep gcc quiet */
641 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
642 for_each_engine(signaller, dev_priv, id) {
643 if (signaller == engine)
646 last_reg = RING_PSMI_CTL(signaller->mmio_base);
647 *cs++ = i915_mmio_reg_offset(last_reg);
648 *cs++ = _MASKED_BIT_DISABLE(
649 GEN6_PSMI_SLEEP_MSG_DISABLE);
652 /* Insert a delay before the next switch! */
653 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
654 *cs++ = i915_mmio_reg_offset(last_reg);
655 *cs++ = i915_ggtt_offset(engine->scratch);
658 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
661 intel_ring_advance(req, cs);
666 static int remap_l3(struct drm_i915_gem_request *req, int slice)
668 u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
674 cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
679 * Note: We do not worry about the concurrent register cacheline hang
680 * here because no other code should access these registers other than
681 * at initialization time.
683 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
684 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
685 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
686 *cs++ = remap_info[i];
689 intel_ring_advance(req, cs);
694 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
695 struct intel_engine_cs *engine,
696 struct i915_gem_context *to)
701 if (!to->engine[RCS].initialised)
704 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
707 return to == engine->legacy_active_context;
711 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
712 struct intel_engine_cs *engine,
713 struct i915_gem_context *to)
718 /* Always load the ppgtt on first use */
719 if (!engine->legacy_active_context)
722 /* Same context without new entries, skip */
723 if (engine->legacy_active_context == to &&
724 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
727 if (engine->id != RCS)
730 if (INTEL_GEN(engine->i915) < 8)
737 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
738 struct i915_gem_context *to,
744 if (!IS_GEN8(to->i915))
747 if (hw_flags & MI_RESTORE_INHIBIT)
753 static int do_rcs_switch(struct drm_i915_gem_request *req)
755 struct i915_gem_context *to = req->ctx;
756 struct intel_engine_cs *engine = req->engine;
757 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
758 struct i915_gem_context *from = engine->legacy_active_context;
762 GEM_BUG_ON(engine->id != RCS);
764 if (skip_rcs_switch(ppgtt, engine, to))
767 if (needs_pd_load_pre(ppgtt, engine, to)) {
768 /* Older GENs and non render rings still want the load first,
769 * "PP_DCLV followed by PP_DIR_BASE register through Load
770 * Register Immediate commands in Ring Buffer before submitting
772 trace_switch_mm(engine, to);
773 ret = ppgtt->switch_mm(ppgtt, req);
778 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
779 /* NB: If we inhibit the restore, the context is not allowed to
780 * die because future work may end up depending on valid address
781 * space. This means we must enforce that a page table load
782 * occur when this occurs. */
783 hw_flags = MI_RESTORE_INHIBIT;
784 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
785 hw_flags = MI_FORCE_RESTORE;
789 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
790 ret = mi_set_context(req, hw_flags);
794 engine->legacy_active_context = to;
797 /* GEN8 does *not* require an explicit reload if the PDPs have been
798 * setup, and we do not wish to move them.
800 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
801 trace_switch_mm(engine, to);
802 ret = ppgtt->switch_mm(ppgtt, req);
803 /* The hardware context switch is emitted, but we haven't
804 * actually changed the state - so it's probably safe to bail
805 * here. Still, let the user know something dangerous has
813 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
815 for (i = 0; i < MAX_L3_SLICES; i++) {
816 if (!(to->remap_slice & (1<<i)))
819 ret = remap_l3(req, i);
823 to->remap_slice &= ~(1<<i);
826 if (!to->engine[RCS].initialised) {
827 if (engine->init_context) {
828 ret = engine->init_context(req);
832 to->engine[RCS].initialised = true;
839 * i915_switch_context() - perform a GPU context switch.
840 * @req: request for which we'll execute the context switch
842 * The context life cycle is simple. The context refcount is incremented and
843 * decremented by 1 and create and destroy. If the context is in use by the GPU,
844 * it will have a refcount > 1. This allows us to destroy the context abstract
845 * object while letting the normal object tracking destroy the backing BO.
847 * This function should not be used in execlists mode. Instead the context is
848 * switched by writing to the ELSP and requests keep a reference to their
851 int i915_switch_context(struct drm_i915_gem_request *req)
853 struct intel_engine_cs *engine = req->engine;
855 lockdep_assert_held(&req->i915->drm.struct_mutex);
856 if (i915.enable_execlists)
859 if (!req->ctx->engine[engine->id].state) {
860 struct i915_gem_context *to = req->ctx;
861 struct i915_hw_ppgtt *ppgtt =
862 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
864 if (needs_pd_load_pre(ppgtt, engine, to)) {
867 trace_switch_mm(engine, to);
868 ret = ppgtt->switch_mm(ppgtt, req);
872 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
878 return do_rcs_switch(req);
881 static bool engine_has_kernel_context(struct intel_engine_cs *engine)
883 struct i915_gem_timeline *timeline;
885 list_for_each_entry(timeline, &engine->i915->gt.timelines, link) {
886 struct intel_timeline *tl;
888 if (timeline == &engine->i915->gt.global_timeline)
891 tl = &timeline->engine[engine->id];
892 if (i915_gem_active_peek(&tl->last_request,
893 &engine->i915->drm.struct_mutex))
897 return (!engine->last_retired_context ||
898 i915_gem_context_is_kernel(engine->last_retired_context));
901 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
903 struct intel_engine_cs *engine;
904 struct i915_gem_timeline *timeline;
905 enum intel_engine_id id;
907 lockdep_assert_held(&dev_priv->drm.struct_mutex);
909 i915_gem_retire_requests(dev_priv);
911 for_each_engine(engine, dev_priv, id) {
912 struct drm_i915_gem_request *req;
915 if (engine_has_kernel_context(engine))
918 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
922 /* Queue this switch after all other activity */
923 list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
924 struct drm_i915_gem_request *prev;
925 struct intel_timeline *tl;
927 tl = &timeline->engine[engine->id];
928 prev = i915_gem_active_raw(&tl->last_request,
929 &dev_priv->drm.struct_mutex);
931 i915_sw_fence_await_sw_fence_gfp(&req->submit,
936 ret = i915_switch_context(req);
937 i915_add_request_no_flush(req);
945 static bool contexts_enabled(struct drm_device *dev)
947 return i915.enable_execlists || to_i915(dev)->hw_context_size;
950 static bool client_is_banned(struct drm_i915_file_private *file_priv)
952 return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS;
955 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
956 struct drm_file *file)
958 struct drm_i915_gem_context_create *args = data;
959 struct drm_i915_file_private *file_priv = file->driver_priv;
960 struct i915_gem_context *ctx;
963 if (!contexts_enabled(dev))
969 if (client_is_banned(file_priv)) {
970 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
972 pid_nr(get_task_pid(current, PIDTYPE_PID)));
977 ret = i915_mutex_lock_interruptible(dev);
981 ctx = i915_gem_create_context(to_i915(dev), file_priv);
982 mutex_unlock(&dev->struct_mutex);
986 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
988 args->ctx_id = ctx->user_handle;
989 DRM_DEBUG("HW context %d created\n", args->ctx_id);
994 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
995 struct drm_file *file)
997 struct drm_i915_gem_context_destroy *args = data;
998 struct drm_i915_file_private *file_priv = file->driver_priv;
999 struct i915_gem_context *ctx;
1005 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
1008 ret = i915_mutex_lock_interruptible(dev);
1012 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1014 mutex_unlock(&dev->struct_mutex);
1015 return PTR_ERR(ctx);
1018 __destroy_hw_context(ctx, file_priv);
1019 mutex_unlock(&dev->struct_mutex);
1021 DRM_DEBUG("HW context %d destroyed\n", args->ctx_id);
1025 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1026 struct drm_file *file)
1028 struct drm_i915_file_private *file_priv = file->driver_priv;
1029 struct drm_i915_gem_context_param *args = data;
1030 struct i915_gem_context *ctx;
1033 ret = i915_mutex_lock_interruptible(dev);
1037 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1039 mutex_unlock(&dev->struct_mutex);
1040 return PTR_ERR(ctx);
1044 switch (args->param) {
1045 case I915_CONTEXT_PARAM_BAN_PERIOD:
1048 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1049 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1051 case I915_CONTEXT_PARAM_GTT_SIZE:
1053 args->value = ctx->ppgtt->base.total;
1054 else if (to_i915(dev)->mm.aliasing_ppgtt)
1055 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1057 args->value = to_i915(dev)->ggtt.base.total;
1059 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1060 args->value = i915_gem_context_no_error_capture(ctx);
1062 case I915_CONTEXT_PARAM_BANNABLE:
1063 args->value = i915_gem_context_is_bannable(ctx);
1069 mutex_unlock(&dev->struct_mutex);
1074 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *file)
1077 struct drm_i915_file_private *file_priv = file->driver_priv;
1078 struct drm_i915_gem_context_param *args = data;
1079 struct i915_gem_context *ctx;
1082 ret = i915_mutex_lock_interruptible(dev);
1086 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1088 mutex_unlock(&dev->struct_mutex);
1089 return PTR_ERR(ctx);
1092 switch (args->param) {
1093 case I915_CONTEXT_PARAM_BAN_PERIOD:
1096 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1100 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1101 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1104 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1107 else if (args->value)
1108 i915_gem_context_set_no_error_capture(ctx);
1110 i915_gem_context_clear_no_error_capture(ctx);
1112 case I915_CONTEXT_PARAM_BANNABLE:
1115 else if (!capable(CAP_SYS_ADMIN) && !args->value)
1117 else if (args->value)
1118 i915_gem_context_set_bannable(ctx);
1120 i915_gem_context_clear_bannable(ctx);
1126 mutex_unlock(&dev->struct_mutex);
1131 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1132 void *data, struct drm_file *file)
1134 struct drm_i915_private *dev_priv = to_i915(dev);
1135 struct drm_i915_reset_stats *args = data;
1136 struct i915_gem_context *ctx;
1139 if (args->flags || args->pad)
1142 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1145 ret = i915_mutex_lock_interruptible(dev);
1149 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1151 mutex_unlock(&dev->struct_mutex);
1152 return PTR_ERR(ctx);
1155 if (capable(CAP_SYS_ADMIN))
1156 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1158 args->reset_count = 0;
1160 args->batch_active = ctx->guilty_count;
1161 args->batch_pending = ctx->active_count;
1163 mutex_unlock(&dev->struct_mutex);
1168 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1169 #include "selftests/mock_context.c"
1170 #include "selftests/i915_gem_context.c"