2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 bool map_and_fenceable,
46 static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
51 static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
57 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
58 struct shrink_control *sc);
59 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
60 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
61 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
63 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
66 i915_gem_release_mmap(obj);
68 /* As we do not have an associated fence register, we will force
69 * a tiling change if we ever need to acquire one.
71 obj->fence_dirty = false;
72 obj->fence_reg = I915_FENCE_REG_NONE;
75 /* some bookkeeping */
76 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
79 dev_priv->mm.object_count++;
80 dev_priv->mm.object_memory += size;
83 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
86 dev_priv->mm.object_count--;
87 dev_priv->mm.object_memory -= size;
91 i915_gem_wait_for_error(struct drm_device *dev)
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 struct completion *x = &dev_priv->error_completion;
98 if (!atomic_read(&dev_priv->mm.wedged))
102 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
103 * userspace. If it takes that long something really bad is going on and
104 * we should simply try to bail out and fail as gracefully as possible.
106 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
114 if (atomic_read(&dev_priv->mm.wedged)) {
115 /* GPU is hung, bump the completion count to account for
116 * the token we just consumed so that we never hit zero and
117 * end up waiting upon a subsequent completion event that
120 spin_lock_irqsave(&x->wait.lock, flags);
122 spin_unlock_irqrestore(&x->wait.lock, flags);
127 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 ret = i915_gem_wait_for_error(dev);
135 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 WARN_ON(i915_verify_lists(dev));
144 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
146 return obj->gtt_space && !obj->active;
150 i915_gem_init_ioctl(struct drm_device *dev, void *data,
151 struct drm_file *file)
153 struct drm_i915_gem_init *args = data;
155 if (drm_core_check_feature(dev, DRIVER_MODESET))
158 if (args->gtt_start >= args->gtt_end ||
159 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
162 /* GEM with user mode setting was never supported on ilk and later. */
163 if (INTEL_INFO(dev)->gen >= 5)
166 mutex_lock(&dev->struct_mutex);
167 i915_gem_init_global_gtt(dev, args->gtt_start,
168 args->gtt_end, args->gtt_end);
169 mutex_unlock(&dev->struct_mutex);
175 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
176 struct drm_file *file)
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 struct drm_i915_gem_get_aperture *args = data;
180 struct drm_i915_gem_object *obj;
184 mutex_lock(&dev->struct_mutex);
185 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
187 pinned += obj->gtt_space->size;
188 mutex_unlock(&dev->struct_mutex);
190 args->aper_size = dev_priv->mm.gtt_total;
191 args->aper_available_size = args->aper_size - pinned;
197 i915_gem_create(struct drm_file *file,
198 struct drm_device *dev,
202 struct drm_i915_gem_object *obj;
206 size = roundup(size, PAGE_SIZE);
210 /* Allocate the new object */
211 obj = i915_gem_alloc_object(dev, size);
215 ret = drm_gem_handle_create(file, &obj->base, &handle);
217 drm_gem_object_release(&obj->base);
218 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
223 /* drop reference from allocate - handle holds it now */
224 drm_gem_object_unreference(&obj->base);
225 trace_i915_gem_object_create(obj);
232 i915_gem_dumb_create(struct drm_file *file,
233 struct drm_device *dev,
234 struct drm_mode_create_dumb *args)
236 /* have to work out size/pitch and return them */
237 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
238 args->size = args->pitch * args->height;
239 return i915_gem_create(file, dev,
240 args->size, &args->handle);
243 int i915_gem_dumb_destroy(struct drm_file *file,
244 struct drm_device *dev,
247 return drm_gem_handle_delete(file, handle);
251 * Creates a new mm object and returns a handle to it.
254 i915_gem_create_ioctl(struct drm_device *dev, void *data,
255 struct drm_file *file)
257 struct drm_i915_gem_create *args = data;
259 return i915_gem_create(file, dev,
260 args->size, &args->handle);
263 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
265 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
267 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
268 obj->tiling_mode != I915_TILING_NONE;
272 __copy_to_user_swizzled(char __user *cpu_vaddr,
273 const char *gpu_vaddr, int gpu_offset,
276 int ret, cpu_offset = 0;
279 int cacheline_end = ALIGN(gpu_offset + 1, 64);
280 int this_length = min(cacheline_end - gpu_offset, length);
281 int swizzled_gpu_offset = gpu_offset ^ 64;
283 ret = __copy_to_user(cpu_vaddr + cpu_offset,
284 gpu_vaddr + swizzled_gpu_offset,
289 cpu_offset += this_length;
290 gpu_offset += this_length;
291 length -= this_length;
298 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
299 const char __user *cpu_vaddr,
302 int ret, cpu_offset = 0;
305 int cacheline_end = ALIGN(gpu_offset + 1, 64);
306 int this_length = min(cacheline_end - gpu_offset, length);
307 int swizzled_gpu_offset = gpu_offset ^ 64;
309 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
310 cpu_vaddr + cpu_offset,
315 cpu_offset += this_length;
316 gpu_offset += this_length;
317 length -= this_length;
323 /* Per-page copy function for the shmem pread fastpath.
324 * Flushes invalid cachelines before reading the target if
325 * needs_clflush is set. */
327 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
328 char __user *user_data,
329 bool page_do_bit17_swizzling, bool needs_clflush)
334 if (unlikely(page_do_bit17_swizzling))
337 vaddr = kmap_atomic(page);
339 drm_clflush_virt_range(vaddr + shmem_page_offset,
341 ret = __copy_to_user_inatomic(user_data,
342 vaddr + shmem_page_offset,
344 kunmap_atomic(vaddr);
346 return ret ? -EFAULT : 0;
350 shmem_clflush_swizzled_range(char *addr, unsigned long length,
353 if (unlikely(swizzled)) {
354 unsigned long start = (unsigned long) addr;
355 unsigned long end = (unsigned long) addr + length;
357 /* For swizzling simply ensure that we always flush both
358 * channels. Lame, but simple and it works. Swizzled
359 * pwrite/pread is far from a hotpath - current userspace
360 * doesn't use it at all. */
361 start = round_down(start, 128);
362 end = round_up(end, 128);
364 drm_clflush_virt_range((void *)start, end - start);
366 drm_clflush_virt_range(addr, length);
371 /* Only difference to the fast-path function is that this can handle bit17
372 * and uses non-atomic copy and kmap functions. */
374 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
375 char __user *user_data,
376 bool page_do_bit17_swizzling, bool needs_clflush)
383 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
385 page_do_bit17_swizzling);
387 if (page_do_bit17_swizzling)
388 ret = __copy_to_user_swizzled(user_data,
389 vaddr, shmem_page_offset,
392 ret = __copy_to_user(user_data,
393 vaddr + shmem_page_offset,
397 return ret ? - EFAULT : 0;
401 i915_gem_shmem_pread(struct drm_device *dev,
402 struct drm_i915_gem_object *obj,
403 struct drm_i915_gem_pread *args,
404 struct drm_file *file)
406 char __user *user_data;
409 int shmem_page_offset, page_length, ret = 0;
410 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
411 int hit_slowpath = 0;
413 int needs_clflush = 0;
414 struct scatterlist *sg;
417 user_data = (char __user *) (uintptr_t) args->data_ptr;
420 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
422 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
423 /* If we're not in the cpu read domain, set ourself into the gtt
424 * read domain and manually flush cachelines (if required). This
425 * optimizes for the case when the gpu will dirty the data
426 * anyway again before the next pread happens. */
427 if (obj->cache_level == I915_CACHE_NONE)
429 if (obj->gtt_space) {
430 ret = i915_gem_object_set_to_gtt_domain(obj, false);
436 ret = i915_gem_object_get_pages(obj);
440 i915_gem_object_pin_pages(obj);
442 offset = args->offset;
444 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
447 if (i < offset >> PAGE_SHIFT)
453 /* Operation in this page
455 * shmem_page_offset = offset within page in shmem file
456 * page_length = bytes to copy for this page
458 shmem_page_offset = offset_in_page(offset);
459 page_length = remain;
460 if ((shmem_page_offset + page_length) > PAGE_SIZE)
461 page_length = PAGE_SIZE - shmem_page_offset;
464 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
465 (page_to_phys(page) & (1 << 17)) != 0;
467 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
468 user_data, page_do_bit17_swizzling,
474 mutex_unlock(&dev->struct_mutex);
477 ret = fault_in_multipages_writeable(user_data, remain);
478 /* Userspace is tricking us, but we've already clobbered
479 * its pages with the prefault and promised to write the
480 * data up to the first fault. Hence ignore any errors
481 * and just continue. */
486 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
487 user_data, page_do_bit17_swizzling,
490 mutex_lock(&dev->struct_mutex);
493 mark_page_accessed(page);
498 remain -= page_length;
499 user_data += page_length;
500 offset += page_length;
504 i915_gem_object_unpin_pages(obj);
507 /* Fixup: Kill any reinstated backing storage pages */
508 if (obj->madv == __I915_MADV_PURGED)
509 i915_gem_object_truncate(obj);
516 * Reads data from the object referenced by handle.
518 * On error, the contents of *data are undefined.
521 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
522 struct drm_file *file)
524 struct drm_i915_gem_pread *args = data;
525 struct drm_i915_gem_object *obj;
531 if (!access_ok(VERIFY_WRITE,
532 (char __user *)(uintptr_t)args->data_ptr,
536 ret = i915_mutex_lock_interruptible(dev);
540 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
541 if (&obj->base == NULL) {
546 /* Bounds check source. */
547 if (args->offset > obj->base.size ||
548 args->size > obj->base.size - args->offset) {
553 /* prime objects have no backing filp to GEM pread/pwrite
556 if (!obj->base.filp) {
561 trace_i915_gem_object_pread(obj, args->offset, args->size);
563 ret = i915_gem_shmem_pread(dev, obj, args, file);
566 drm_gem_object_unreference(&obj->base);
568 mutex_unlock(&dev->struct_mutex);
572 /* This is the fast write path which cannot handle
573 * page faults in the source data
577 fast_user_write(struct io_mapping *mapping,
578 loff_t page_base, int page_offset,
579 char __user *user_data,
582 void __iomem *vaddr_atomic;
584 unsigned long unwritten;
586 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
587 /* We can use the cpu mem copy function because this is X86. */
588 vaddr = (void __force*)vaddr_atomic + page_offset;
589 unwritten = __copy_from_user_inatomic_nocache(vaddr,
591 io_mapping_unmap_atomic(vaddr_atomic);
596 * This is the fast pwrite path, where we copy the data directly from the
597 * user into the GTT, uncached.
600 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
601 struct drm_i915_gem_object *obj,
602 struct drm_i915_gem_pwrite *args,
603 struct drm_file *file)
605 drm_i915_private_t *dev_priv = dev->dev_private;
607 loff_t offset, page_base;
608 char __user *user_data;
609 int page_offset, page_length, ret;
611 ret = i915_gem_object_pin(obj, 0, true, true);
615 ret = i915_gem_object_set_to_gtt_domain(obj, true);
619 ret = i915_gem_object_put_fence(obj);
623 user_data = (char __user *) (uintptr_t) args->data_ptr;
626 offset = obj->gtt_offset + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = offset & PAGE_MASK;
636 page_offset = offset_in_page(offset);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 /* If we get a fault while copying data, then (presumably) our
642 * source page isn't available. Return the error and we'll
643 * retry in the slow path.
645 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
646 page_offset, user_data, page_length)) {
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
662 /* Per-page copy function for the shmem pwrite fastpath.
663 * Flushes invalid cachelines before writing to the target if
664 * needs_clflush_before is set and flushes out any written cachelines after
665 * writing if needs_clflush is set. */
667 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
668 char __user *user_data,
669 bool page_do_bit17_swizzling,
670 bool needs_clflush_before,
671 bool needs_clflush_after)
676 if (unlikely(page_do_bit17_swizzling))
679 vaddr = kmap_atomic(page);
680 if (needs_clflush_before)
681 drm_clflush_virt_range(vaddr + shmem_page_offset,
683 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
686 if (needs_clflush_after)
687 drm_clflush_virt_range(vaddr + shmem_page_offset,
689 kunmap_atomic(vaddr);
691 return ret ? -EFAULT : 0;
694 /* Only difference to the fast-path function is that this can handle bit17
695 * and uses non-atomic copy and kmap functions. */
697 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
698 char __user *user_data,
699 bool page_do_bit17_swizzling,
700 bool needs_clflush_before,
701 bool needs_clflush_after)
707 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
708 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
710 page_do_bit17_swizzling);
711 if (page_do_bit17_swizzling)
712 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
716 ret = __copy_from_user(vaddr + shmem_page_offset,
719 if (needs_clflush_after)
720 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
722 page_do_bit17_swizzling);
725 return ret ? -EFAULT : 0;
729 i915_gem_shmem_pwrite(struct drm_device *dev,
730 struct drm_i915_gem_object *obj,
731 struct drm_i915_gem_pwrite *args,
732 struct drm_file *file)
736 char __user *user_data;
737 int shmem_page_offset, page_length, ret = 0;
738 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
739 int hit_slowpath = 0;
740 int needs_clflush_after = 0;
741 int needs_clflush_before = 0;
743 struct scatterlist *sg;
745 user_data = (char __user *) (uintptr_t) args->data_ptr;
748 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
750 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
751 /* If we're not in the cpu write domain, set ourself into the gtt
752 * write domain and manually flush cachelines (if required). This
753 * optimizes for the case when the gpu will use the data
754 * right away and we therefore have to clflush anyway. */
755 if (obj->cache_level == I915_CACHE_NONE)
756 needs_clflush_after = 1;
757 if (obj->gtt_space) {
758 ret = i915_gem_object_set_to_gtt_domain(obj, true);
763 /* Same trick applies for invalidate partially written cachelines before
765 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
766 && obj->cache_level == I915_CACHE_NONE)
767 needs_clflush_before = 1;
769 ret = i915_gem_object_get_pages(obj);
773 i915_gem_object_pin_pages(obj);
775 offset = args->offset;
778 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
780 int partial_cacheline_write;
782 if (i < offset >> PAGE_SHIFT)
788 /* Operation in this page
790 * shmem_page_offset = offset within page in shmem file
791 * page_length = bytes to copy for this page
793 shmem_page_offset = offset_in_page(offset);
795 page_length = remain;
796 if ((shmem_page_offset + page_length) > PAGE_SIZE)
797 page_length = PAGE_SIZE - shmem_page_offset;
799 /* If we don't overwrite a cacheline completely we need to be
800 * careful to have up-to-date data by first clflushing. Don't
801 * overcomplicate things and flush the entire patch. */
802 partial_cacheline_write = needs_clflush_before &&
803 ((shmem_page_offset | page_length)
804 & (boot_cpu_data.x86_clflush_size - 1));
807 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
808 (page_to_phys(page) & (1 << 17)) != 0;
810 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
811 user_data, page_do_bit17_swizzling,
812 partial_cacheline_write,
813 needs_clflush_after);
818 mutex_unlock(&dev->struct_mutex);
819 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
820 user_data, page_do_bit17_swizzling,
821 partial_cacheline_write,
822 needs_clflush_after);
824 mutex_lock(&dev->struct_mutex);
827 set_page_dirty(page);
828 mark_page_accessed(page);
833 remain -= page_length;
834 user_data += page_length;
835 offset += page_length;
839 i915_gem_object_unpin_pages(obj);
842 /* Fixup: Kill any reinstated backing storage pages */
843 if (obj->madv == __I915_MADV_PURGED)
844 i915_gem_object_truncate(obj);
845 /* and flush dirty cachelines in case the object isn't in the cpu write
847 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
848 i915_gem_clflush_object(obj);
849 intel_gtt_chipset_flush();
853 if (needs_clflush_after)
854 intel_gtt_chipset_flush();
860 * Writes data to the object referenced by handle.
862 * On error, the contents of the buffer that were to be modified are undefined.
865 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
866 struct drm_file *file)
868 struct drm_i915_gem_pwrite *args = data;
869 struct drm_i915_gem_object *obj;
875 if (!access_ok(VERIFY_READ,
876 (char __user *)(uintptr_t)args->data_ptr,
880 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
885 ret = i915_mutex_lock_interruptible(dev);
889 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
890 if (&obj->base == NULL) {
895 /* Bounds check destination. */
896 if (args->offset > obj->base.size ||
897 args->size > obj->base.size - args->offset) {
902 /* prime objects have no backing filp to GEM pread/pwrite
905 if (!obj->base.filp) {
910 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
913 /* We can only do the GTT pwrite on untiled buffers, as otherwise
914 * it would end up going through the fenced access, and we'll get
915 * different detiling behavior between reading and writing.
916 * pread/pwrite currently are reading and writing from the CPU
917 * perspective, requiring manual detiling by the client.
920 ret = i915_gem_phys_pwrite(dev, obj, args, file);
924 if (obj->cache_level == I915_CACHE_NONE &&
925 obj->tiling_mode == I915_TILING_NONE &&
926 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
927 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
928 /* Note that the gtt paths might fail with non-page-backed user
929 * pointers (e.g. gtt mappings when moving data between
930 * textures). Fallback to the shmem path in that case. */
933 if (ret == -EFAULT || ret == -ENOSPC)
934 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
937 drm_gem_object_unreference(&obj->base);
939 mutex_unlock(&dev->struct_mutex);
944 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
947 if (atomic_read(&dev_priv->mm.wedged)) {
948 struct completion *x = &dev_priv->error_completion;
949 bool recovery_complete;
952 /* Give the error handler a chance to run. */
953 spin_lock_irqsave(&x->wait.lock, flags);
954 recovery_complete = x->done > 0;
955 spin_unlock_irqrestore(&x->wait.lock, flags);
957 /* Non-interruptible callers can't handle -EAGAIN, hence return
958 * -EIO unconditionally for these. */
962 /* Recovery complete, but still wedged means reset failure. */
963 if (recovery_complete)
973 * Compare seqno against outstanding lazy request. Emit a request if they are
977 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
981 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
984 if (seqno == ring->outstanding_lazy_request)
985 ret = i915_add_request(ring, NULL, NULL);
991 * __wait_seqno - wait until execution of seqno has finished
992 * @ring: the ring expected to report seqno
994 * @interruptible: do an interruptible wait (normally yes)
995 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
997 * Returns 0 if the seqno was found within the alloted time. Else returns the
998 * errno with remaining time filled in timeout argument.
1000 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1001 bool interruptible, struct timespec *timeout)
1003 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1004 struct timespec before, now, wait_time={1,0};
1005 unsigned long timeout_jiffies;
1007 bool wait_forever = true;
1010 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1013 trace_i915_gem_request_wait_begin(ring, seqno);
1015 if (timeout != NULL) {
1016 wait_time = *timeout;
1017 wait_forever = false;
1020 timeout_jiffies = timespec_to_jiffies(&wait_time);
1022 if (WARN_ON(!ring->irq_get(ring)))
1025 /* Record current time in case interrupted by signal, or wedged * */
1026 getrawmonotonic(&before);
1029 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1030 atomic_read(&dev_priv->mm.wedged))
1033 end = wait_event_interruptible_timeout(ring->irq_queue,
1037 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1040 ret = i915_gem_check_wedge(dev_priv, interruptible);
1043 } while (end == 0 && wait_forever);
1045 getrawmonotonic(&now);
1047 ring->irq_put(ring);
1048 trace_i915_gem_request_wait_end(ring, seqno);
1052 struct timespec sleep_time = timespec_sub(now, before);
1053 *timeout = timespec_sub(*timeout, sleep_time);
1058 case -EAGAIN: /* Wedged */
1059 case -ERESTARTSYS: /* Signal */
1061 case 0: /* Timeout */
1063 set_normalized_timespec(timeout, 0, 0);
1065 default: /* Completed */
1066 WARN_ON(end < 0); /* We're not aware of other errors */
1072 * Waits for a sequence number to be signaled, and cleans up the
1073 * request and object lists appropriately for that event.
1076 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1078 struct drm_device *dev = ring->dev;
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 bool interruptible = dev_priv->mm.interruptible;
1083 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1086 ret = i915_gem_check_wedge(dev_priv, interruptible);
1090 ret = i915_gem_check_olr(ring, seqno);
1094 return __wait_seqno(ring, seqno, interruptible, NULL);
1098 * Ensures that all rendering to the object has completed and the object is
1099 * safe to unbind from the GTT or access from the CPU.
1101 static __must_check int
1102 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1105 struct intel_ring_buffer *ring = obj->ring;
1109 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1113 ret = i915_wait_seqno(ring, seqno);
1117 i915_gem_retire_requests_ring(ring);
1119 /* Manually manage the write flush as we may have not yet
1120 * retired the buffer.
1122 if (obj->last_write_seqno &&
1123 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1124 obj->last_write_seqno = 0;
1125 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1131 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1132 * as the object state may change during this call.
1134 static __must_check int
1135 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1138 struct drm_device *dev = obj->base.dev;
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 struct intel_ring_buffer *ring = obj->ring;
1144 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1145 BUG_ON(!dev_priv->mm.interruptible);
1147 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1151 ret = i915_gem_check_wedge(dev_priv, true);
1155 ret = i915_gem_check_olr(ring, seqno);
1159 mutex_unlock(&dev->struct_mutex);
1160 ret = __wait_seqno(ring, seqno, true, NULL);
1161 mutex_lock(&dev->struct_mutex);
1163 i915_gem_retire_requests_ring(ring);
1165 /* Manually manage the write flush as we may have not yet
1166 * retired the buffer.
1168 if (obj->last_write_seqno &&
1169 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1170 obj->last_write_seqno = 0;
1171 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1178 * Called when user space prepares to use an object with the CPU, either
1179 * through the mmap ioctl's mapping or a GTT mapping.
1182 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1183 struct drm_file *file)
1185 struct drm_i915_gem_set_domain *args = data;
1186 struct drm_i915_gem_object *obj;
1187 uint32_t read_domains = args->read_domains;
1188 uint32_t write_domain = args->write_domain;
1191 /* Only handle setting domains to types used by the CPU. */
1192 if (write_domain & I915_GEM_GPU_DOMAINS)
1195 if (read_domains & I915_GEM_GPU_DOMAINS)
1198 /* Having something in the write domain implies it's in the read
1199 * domain, and only that read domain. Enforce that in the request.
1201 if (write_domain != 0 && read_domains != write_domain)
1204 ret = i915_mutex_lock_interruptible(dev);
1208 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1209 if (&obj->base == NULL) {
1214 /* Try to flush the object off the GPU without holding the lock.
1215 * We will repeat the flush holding the lock in the normal manner
1216 * to catch cases where we are gazumped.
1218 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1222 if (read_domains & I915_GEM_DOMAIN_GTT) {
1223 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1225 /* Silently promote "you're not bound, there was nothing to do"
1226 * to success, since the client was just asking us to
1227 * make sure everything was done.
1232 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1236 drm_gem_object_unreference(&obj->base);
1238 mutex_unlock(&dev->struct_mutex);
1243 * Called when user space has done writes to this buffer
1246 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1247 struct drm_file *file)
1249 struct drm_i915_gem_sw_finish *args = data;
1250 struct drm_i915_gem_object *obj;
1253 ret = i915_mutex_lock_interruptible(dev);
1257 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1258 if (&obj->base == NULL) {
1263 /* Pinned buffers may be scanout, so flush the cache */
1265 i915_gem_object_flush_cpu_write_domain(obj);
1267 drm_gem_object_unreference(&obj->base);
1269 mutex_unlock(&dev->struct_mutex);
1274 * Maps the contents of an object, returning the address it is mapped
1277 * While the mapping holds a reference on the contents of the object, it doesn't
1278 * imply a ref on the object itself.
1281 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1282 struct drm_file *file)
1284 struct drm_i915_gem_mmap *args = data;
1285 struct drm_gem_object *obj;
1288 obj = drm_gem_object_lookup(dev, file, args->handle);
1292 /* prime objects have no backing filp to GEM mmap
1296 drm_gem_object_unreference_unlocked(obj);
1300 addr = vm_mmap(obj->filp, 0, args->size,
1301 PROT_READ | PROT_WRITE, MAP_SHARED,
1303 drm_gem_object_unreference_unlocked(obj);
1304 if (IS_ERR((void *)addr))
1307 args->addr_ptr = (uint64_t) addr;
1313 * i915_gem_fault - fault a page into the GTT
1314 * vma: VMA in question
1317 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1318 * from userspace. The fault handler takes care of binding the object to
1319 * the GTT (if needed), allocating and programming a fence register (again,
1320 * only if needed based on whether the old reg is still valid or the object
1321 * is tiled) and inserting a new PTE into the faulting process.
1323 * Note that the faulting process may involve evicting existing objects
1324 * from the GTT and/or fence registers to make room. So performance may
1325 * suffer if the GTT working set is large or there are few fence registers
1328 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1330 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1331 struct drm_device *dev = obj->base.dev;
1332 drm_i915_private_t *dev_priv = dev->dev_private;
1333 pgoff_t page_offset;
1336 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1338 /* We don't use vmf->pgoff since that has the fake offset */
1339 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1342 ret = i915_mutex_lock_interruptible(dev);
1346 trace_i915_gem_object_fault(obj, page_offset, true, write);
1348 /* Now bind it into the GTT if needed */
1349 if (!obj->map_and_fenceable) {
1350 ret = i915_gem_object_unbind(obj);
1354 if (!obj->gtt_space) {
1355 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1359 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1364 if (!obj->has_global_gtt_mapping)
1365 i915_gem_gtt_bind_object(obj, obj->cache_level);
1367 ret = i915_gem_object_get_fence(obj);
1371 if (i915_gem_object_is_inactive(obj))
1372 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1374 obj->fault_mappable = true;
1376 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1379 /* Finally, remap it using the new GTT offset */
1380 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1382 mutex_unlock(&dev->struct_mutex);
1386 /* If this -EIO is due to a gpu hang, give the reset code a
1387 * chance to clean up the mess. Otherwise return the proper
1389 if (!atomic_read(&dev_priv->mm.wedged))
1390 return VM_FAULT_SIGBUS;
1392 /* Give the error handler a chance to run and move the
1393 * objects off the GPU active list. Next time we service the
1394 * fault, we should be able to transition the page into the
1395 * GTT without touching the GPU (and so avoid further
1396 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1397 * with coherency, just lost writes.
1405 * EBUSY is ok: this just means that another thread
1406 * already did the job.
1408 return VM_FAULT_NOPAGE;
1410 return VM_FAULT_OOM;
1412 return VM_FAULT_SIGBUS;
1414 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1415 return VM_FAULT_SIGBUS;
1420 * i915_gem_release_mmap - remove physical page mappings
1421 * @obj: obj in question
1423 * Preserve the reservation of the mmapping with the DRM core code, but
1424 * relinquish ownership of the pages back to the system.
1426 * It is vital that we remove the page mapping if we have mapped a tiled
1427 * object through the GTT and then lose the fence register due to
1428 * resource pressure. Similarly if the object has been moved out of the
1429 * aperture, than pages mapped into userspace must be revoked. Removing the
1430 * mapping will then trigger a page fault on the next user access, allowing
1431 * fixup by i915_gem_fault().
1434 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1436 if (!obj->fault_mappable)
1439 if (obj->base.dev->dev_mapping)
1440 unmap_mapping_range(obj->base.dev->dev_mapping,
1441 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1444 obj->fault_mappable = false;
1448 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1452 if (INTEL_INFO(dev)->gen >= 4 ||
1453 tiling_mode == I915_TILING_NONE)
1456 /* Previous chips need a power-of-two fence region when tiling */
1457 if (INTEL_INFO(dev)->gen == 3)
1458 gtt_size = 1024*1024;
1460 gtt_size = 512*1024;
1462 while (gtt_size < size)
1469 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1470 * @obj: object to check
1472 * Return the required GTT alignment for an object, taking into account
1473 * potential fence register mapping.
1476 i915_gem_get_gtt_alignment(struct drm_device *dev,
1481 * Minimum alignment is 4k (GTT page size), but might be greater
1482 * if a fence register is needed for the object.
1484 if (INTEL_INFO(dev)->gen >= 4 ||
1485 tiling_mode == I915_TILING_NONE)
1489 * Previous chips need to be aligned to the size of the smallest
1490 * fence register that can contain the object.
1492 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1496 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1499 * @size: size of the object
1500 * @tiling_mode: tiling mode of the object
1502 * Return the required GTT alignment for an object, only taking into account
1503 * unfenced tiled surface requirements.
1506 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1511 * Minimum alignment is 4k (GTT page size) for sane hw.
1513 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1514 tiling_mode == I915_TILING_NONE)
1517 /* Previous hardware however needs to be aligned to a power-of-two
1518 * tile height. The simplest method for determining this is to reuse
1519 * the power-of-tile object size.
1521 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1524 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1526 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1529 if (obj->base.map_list.map)
1532 ret = drm_gem_create_mmap_offset(&obj->base);
1536 /* Badly fragmented mmap space? The only way we can recover
1537 * space is by destroying unwanted objects. We can't randomly release
1538 * mmap_offsets as userspace expects them to be persistent for the
1539 * lifetime of the objects. The closest we can is to release the
1540 * offsets on purgeable objects by truncating it and marking it purged,
1541 * which prevents userspace from ever using that object again.
1543 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1544 ret = drm_gem_create_mmap_offset(&obj->base);
1548 i915_gem_shrink_all(dev_priv);
1549 return drm_gem_create_mmap_offset(&obj->base);
1552 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1554 if (!obj->base.map_list.map)
1557 drm_gem_free_mmap_offset(&obj->base);
1561 i915_gem_mmap_gtt(struct drm_file *file,
1562 struct drm_device *dev,
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 struct drm_i915_gem_object *obj;
1570 ret = i915_mutex_lock_interruptible(dev);
1574 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1575 if (&obj->base == NULL) {
1580 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1585 if (obj->madv != I915_MADV_WILLNEED) {
1586 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1591 ret = i915_gem_object_create_mmap_offset(obj);
1595 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1598 drm_gem_object_unreference(&obj->base);
1600 mutex_unlock(&dev->struct_mutex);
1605 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1607 * @data: GTT mapping ioctl data
1608 * @file: GEM object info
1610 * Simply returns the fake offset to userspace so it can mmap it.
1611 * The mmap call will end up in drm_gem_mmap(), which will set things
1612 * up so we can get faults in the handler above.
1614 * The fault handler will take care of binding the object into the GTT
1615 * (since it may have been evicted to make room for something), allocating
1616 * a fence register, and mapping the appropriate aperture address into
1620 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1621 struct drm_file *file)
1623 struct drm_i915_gem_mmap_gtt *args = data;
1625 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1628 /* Immediately discard the backing storage */
1630 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1632 struct inode *inode;
1634 i915_gem_object_free_mmap_offset(obj);
1636 if (obj->base.filp == NULL)
1639 /* Our goal here is to return as much of the memory as
1640 * is possible back to the system as we are called from OOM.
1641 * To do this we must instruct the shmfs to drop all of its
1642 * backing pages, *now*.
1644 inode = obj->base.filp->f_path.dentry->d_inode;
1645 shmem_truncate_range(inode, 0, (loff_t)-1);
1647 obj->madv = __I915_MADV_PURGED;
1651 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1653 return obj->madv == I915_MADV_DONTNEED;
1657 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1659 int page_count = obj->base.size / PAGE_SIZE;
1660 struct scatterlist *sg;
1663 BUG_ON(obj->madv == __I915_MADV_PURGED);
1665 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1667 /* In the event of a disaster, abandon all caches and
1668 * hope for the best.
1670 WARN_ON(ret != -EIO);
1671 i915_gem_clflush_object(obj);
1672 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1675 if (i915_gem_object_needs_bit17_swizzle(obj))
1676 i915_gem_object_save_bit_17_swizzle(obj);
1678 if (obj->madv == I915_MADV_DONTNEED)
1681 for_each_sg(obj->pages->sgl, sg, page_count, i) {
1682 struct page *page = sg_page(sg);
1685 set_page_dirty(page);
1687 if (obj->madv == I915_MADV_WILLNEED)
1688 mark_page_accessed(page);
1690 page_cache_release(page);
1694 sg_free_table(obj->pages);
1699 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1701 const struct drm_i915_gem_object_ops *ops = obj->ops;
1703 if (obj->pages == NULL)
1706 BUG_ON(obj->gtt_space);
1708 if (obj->pages_pin_count)
1711 ops->put_pages(obj);
1714 list_del(&obj->gtt_list);
1715 if (i915_gem_object_is_purgeable(obj))
1716 i915_gem_object_truncate(obj);
1722 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1724 struct drm_i915_gem_object *obj, *next;
1727 list_for_each_entry_safe(obj, next,
1728 &dev_priv->mm.unbound_list,
1730 if (i915_gem_object_is_purgeable(obj) &&
1731 i915_gem_object_put_pages(obj) == 0) {
1732 count += obj->base.size >> PAGE_SHIFT;
1733 if (count >= target)
1738 list_for_each_entry_safe(obj, next,
1739 &dev_priv->mm.inactive_list,
1741 if (i915_gem_object_is_purgeable(obj) &&
1742 i915_gem_object_unbind(obj) == 0 &&
1743 i915_gem_object_put_pages(obj) == 0) {
1744 count += obj->base.size >> PAGE_SHIFT;
1745 if (count >= target)
1754 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1756 struct drm_i915_gem_object *obj, *next;
1758 i915_gem_evict_everything(dev_priv->dev);
1760 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1761 i915_gem_object_put_pages(obj);
1765 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1767 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1769 struct address_space *mapping;
1770 struct sg_table *st;
1771 struct scatterlist *sg;
1775 /* Assert that the object is not currently in any GPU domain. As it
1776 * wasn't in the GTT, there shouldn't be any way it could have been in
1779 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1780 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1782 st = kmalloc(sizeof(*st), GFP_KERNEL);
1786 page_count = obj->base.size / PAGE_SIZE;
1787 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1793 /* Get the list of pages out of our struct file. They'll be pinned
1794 * at this point until we release them.
1796 * Fail silently without starting the shrinker
1798 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1799 gfp = mapping_gfp_mask(mapping);
1800 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1801 gfp &= ~(__GFP_IO | __GFP_WAIT);
1802 for_each_sg(st->sgl, sg, page_count, i) {
1803 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1805 i915_gem_purge(dev_priv, page_count);
1806 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1809 /* We've tried hard to allocate the memory by reaping
1810 * our own buffer, now let the real VM do its job and
1811 * go down in flames if truly OOM.
1813 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1814 gfp |= __GFP_IO | __GFP_WAIT;
1816 i915_gem_shrink_all(dev_priv);
1817 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1821 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1822 gfp &= ~(__GFP_IO | __GFP_WAIT);
1825 sg_set_page(sg, page, PAGE_SIZE, 0);
1830 if (i915_gem_object_needs_bit17_swizzle(obj))
1831 i915_gem_object_do_bit_17_swizzle(obj);
1836 for_each_sg(st->sgl, sg, i, page_count)
1837 page_cache_release(sg_page(sg));
1840 return PTR_ERR(page);
1843 /* Ensure that the associated pages are gathered from the backing storage
1844 * and pinned into our object. i915_gem_object_get_pages() may be called
1845 * multiple times before they are released by a single call to
1846 * i915_gem_object_put_pages() - once the pages are no longer referenced
1847 * either as a result of memory pressure (reaping pages under the shrinker)
1848 * or as the object is itself released.
1851 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1853 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1854 const struct drm_i915_gem_object_ops *ops = obj->ops;
1860 BUG_ON(obj->pages_pin_count);
1862 ret = ops->get_pages(obj);
1866 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1871 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1872 struct intel_ring_buffer *ring,
1875 struct drm_device *dev = obj->base.dev;
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1878 BUG_ON(ring == NULL);
1881 /* Add a reference if we're newly entering the active list. */
1883 drm_gem_object_reference(&obj->base);
1887 /* Move from whatever list we were on to the tail of execution. */
1888 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1889 list_move_tail(&obj->ring_list, &ring->active_list);
1891 obj->last_read_seqno = seqno;
1893 if (obj->fenced_gpu_access) {
1894 obj->last_fenced_seqno = seqno;
1896 /* Bump MRU to take account of the delayed flush */
1897 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1898 struct drm_i915_fence_reg *reg;
1900 reg = &dev_priv->fence_regs[obj->fence_reg];
1901 list_move_tail(®->lru_list,
1902 &dev_priv->mm.fence_list);
1908 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1910 struct drm_device *dev = obj->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1913 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1914 BUG_ON(!obj->active);
1916 if (obj->pin_count) /* are we a framebuffer? */
1917 intel_mark_fb_idle(obj);
1919 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1921 list_del_init(&obj->ring_list);
1924 obj->last_read_seqno = 0;
1925 obj->last_write_seqno = 0;
1926 obj->base.write_domain = 0;
1928 obj->last_fenced_seqno = 0;
1929 obj->fenced_gpu_access = false;
1932 drm_gem_object_unreference(&obj->base);
1934 WARN_ON(i915_verify_lists(dev));
1938 i915_gem_get_seqno(struct drm_device *dev)
1940 drm_i915_private_t *dev_priv = dev->dev_private;
1941 u32 seqno = dev_priv->next_seqno;
1943 /* reserve 0 for non-seqno */
1944 if (++dev_priv->next_seqno == 0)
1945 dev_priv->next_seqno = 1;
1951 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1953 if (ring->outstanding_lazy_request == 0)
1954 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1956 return ring->outstanding_lazy_request;
1960 i915_add_request(struct intel_ring_buffer *ring,
1961 struct drm_file *file,
1964 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1965 struct drm_i915_gem_request *request;
1966 u32 request_ring_position;
1972 * Emit any outstanding flushes - execbuf can fail to emit the flush
1973 * after having emitted the batchbuffer command. Hence we need to fix
1974 * things up similar to emitting the lazy request. The difference here
1975 * is that the flush _must_ happen before the next request, no matter
1978 ret = intel_ring_flush_all_caches(ring);
1982 request = kmalloc(sizeof(*request), GFP_KERNEL);
1983 if (request == NULL)
1986 seqno = i915_gem_next_request_seqno(ring);
1988 /* Record the position of the start of the request so that
1989 * should we detect the updated seqno part-way through the
1990 * GPU processing the request, we never over-estimate the
1991 * position of the head.
1993 request_ring_position = intel_ring_get_tail(ring);
1995 ret = ring->add_request(ring, &seqno);
2001 trace_i915_gem_request_add(ring, seqno);
2003 request->seqno = seqno;
2004 request->ring = ring;
2005 request->tail = request_ring_position;
2006 request->emitted_jiffies = jiffies;
2007 was_empty = list_empty(&ring->request_list);
2008 list_add_tail(&request->list, &ring->request_list);
2009 request->file_priv = NULL;
2012 struct drm_i915_file_private *file_priv = file->driver_priv;
2014 spin_lock(&file_priv->mm.lock);
2015 request->file_priv = file_priv;
2016 list_add_tail(&request->client_list,
2017 &file_priv->mm.request_list);
2018 spin_unlock(&file_priv->mm.lock);
2021 ring->outstanding_lazy_request = 0;
2023 if (!dev_priv->mm.suspended) {
2024 if (i915_enable_hangcheck) {
2025 mod_timer(&dev_priv->hangcheck_timer,
2027 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
2030 queue_delayed_work(dev_priv->wq,
2031 &dev_priv->mm.retire_work, HZ);
2032 intel_mark_busy(dev_priv->dev);
2042 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2044 struct drm_i915_file_private *file_priv = request->file_priv;
2049 spin_lock(&file_priv->mm.lock);
2050 if (request->file_priv) {
2051 list_del(&request->client_list);
2052 request->file_priv = NULL;
2054 spin_unlock(&file_priv->mm.lock);
2057 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2058 struct intel_ring_buffer *ring)
2060 while (!list_empty(&ring->request_list)) {
2061 struct drm_i915_gem_request *request;
2063 request = list_first_entry(&ring->request_list,
2064 struct drm_i915_gem_request,
2067 list_del(&request->list);
2068 i915_gem_request_remove_from_client(request);
2072 while (!list_empty(&ring->active_list)) {
2073 struct drm_i915_gem_object *obj;
2075 obj = list_first_entry(&ring->active_list,
2076 struct drm_i915_gem_object,
2079 i915_gem_object_move_to_inactive(obj);
2083 static void i915_gem_reset_fences(struct drm_device *dev)
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2088 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2089 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2091 i915_gem_write_fence(dev, i, NULL);
2094 i915_gem_object_fence_lost(reg->obj);
2098 INIT_LIST_HEAD(®->lru_list);
2101 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2104 void i915_gem_reset(struct drm_device *dev)
2106 struct drm_i915_private *dev_priv = dev->dev_private;
2107 struct drm_i915_gem_object *obj;
2108 struct intel_ring_buffer *ring;
2111 for_each_ring(ring, dev_priv, i)
2112 i915_gem_reset_ring_lists(dev_priv, ring);
2114 /* Move everything out of the GPU domains to ensure we do any
2115 * necessary invalidation upon reuse.
2117 list_for_each_entry(obj,
2118 &dev_priv->mm.inactive_list,
2121 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2124 /* The fence registers are invalidated so clear them out */
2125 i915_gem_reset_fences(dev);
2129 * This function clears the request list as sequence numbers are passed.
2132 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2137 if (list_empty(&ring->request_list))
2140 WARN_ON(i915_verify_lists(ring->dev));
2142 seqno = ring->get_seqno(ring, true);
2144 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
2145 if (seqno >= ring->sync_seqno[i])
2146 ring->sync_seqno[i] = 0;
2148 while (!list_empty(&ring->request_list)) {
2149 struct drm_i915_gem_request *request;
2151 request = list_first_entry(&ring->request_list,
2152 struct drm_i915_gem_request,
2155 if (!i915_seqno_passed(seqno, request->seqno))
2158 trace_i915_gem_request_retire(ring, request->seqno);
2159 /* We know the GPU must have read the request to have
2160 * sent us the seqno + interrupt, so use the position
2161 * of tail of the request to update the last known position
2164 ring->last_retired_head = request->tail;
2166 list_del(&request->list);
2167 i915_gem_request_remove_from_client(request);
2171 /* Move any buffers on the active list that are no longer referenced
2172 * by the ringbuffer to the flushing/inactive lists as appropriate.
2174 while (!list_empty(&ring->active_list)) {
2175 struct drm_i915_gem_object *obj;
2177 obj = list_first_entry(&ring->active_list,
2178 struct drm_i915_gem_object,
2181 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2184 i915_gem_object_move_to_inactive(obj);
2187 if (unlikely(ring->trace_irq_seqno &&
2188 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2189 ring->irq_put(ring);
2190 ring->trace_irq_seqno = 0;
2193 WARN_ON(i915_verify_lists(ring->dev));
2197 i915_gem_retire_requests(struct drm_device *dev)
2199 drm_i915_private_t *dev_priv = dev->dev_private;
2200 struct intel_ring_buffer *ring;
2203 for_each_ring(ring, dev_priv, i)
2204 i915_gem_retire_requests_ring(ring);
2208 i915_gem_retire_work_handler(struct work_struct *work)
2210 drm_i915_private_t *dev_priv;
2211 struct drm_device *dev;
2212 struct intel_ring_buffer *ring;
2216 dev_priv = container_of(work, drm_i915_private_t,
2217 mm.retire_work.work);
2218 dev = dev_priv->dev;
2220 /* Come back later if the device is busy... */
2221 if (!mutex_trylock(&dev->struct_mutex)) {
2222 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2226 i915_gem_retire_requests(dev);
2228 /* Send a periodic flush down the ring so we don't hold onto GEM
2229 * objects indefinitely.
2232 for_each_ring(ring, dev_priv, i) {
2233 if (ring->gpu_caches_dirty)
2234 i915_add_request(ring, NULL, NULL);
2236 idle &= list_empty(&ring->request_list);
2239 if (!dev_priv->mm.suspended && !idle)
2240 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2242 intel_mark_idle(dev);
2244 mutex_unlock(&dev->struct_mutex);
2248 * Ensures that an object will eventually get non-busy by flushing any required
2249 * write domains, emitting any outstanding lazy request and retiring and
2250 * completed requests.
2253 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2258 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2262 i915_gem_retire_requests_ring(obj->ring);
2269 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2270 * @DRM_IOCTL_ARGS: standard ioctl arguments
2272 * Returns 0 if successful, else an error is returned with the remaining time in
2273 * the timeout parameter.
2274 * -ETIME: object is still busy after timeout
2275 * -ERESTARTSYS: signal interrupted the wait
2276 * -ENONENT: object doesn't exist
2277 * Also possible, but rare:
2278 * -EAGAIN: GPU wedged
2280 * -ENODEV: Internal IRQ fail
2281 * -E?: The add request failed
2283 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2284 * non-zero timeout parameter the wait ioctl will wait for the given number of
2285 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2286 * without holding struct_mutex the object may become re-busied before this
2287 * function completes. A similar but shorter * race condition exists in the busy
2291 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2293 struct drm_i915_gem_wait *args = data;
2294 struct drm_i915_gem_object *obj;
2295 struct intel_ring_buffer *ring = NULL;
2296 struct timespec timeout_stack, *timeout = NULL;
2300 if (args->timeout_ns >= 0) {
2301 timeout_stack = ns_to_timespec(args->timeout_ns);
2302 timeout = &timeout_stack;
2305 ret = i915_mutex_lock_interruptible(dev);
2309 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2310 if (&obj->base == NULL) {
2311 mutex_unlock(&dev->struct_mutex);
2315 /* Need to make sure the object gets inactive eventually. */
2316 ret = i915_gem_object_flush_active(obj);
2321 seqno = obj->last_read_seqno;
2328 /* Do this after OLR check to make sure we make forward progress polling
2329 * on this IOCTL with a 0 timeout (like busy ioctl)
2331 if (!args->timeout_ns) {
2336 drm_gem_object_unreference(&obj->base);
2337 mutex_unlock(&dev->struct_mutex);
2339 ret = __wait_seqno(ring, seqno, true, timeout);
2341 WARN_ON(!timespec_valid(timeout));
2342 args->timeout_ns = timespec_to_ns(timeout);
2347 drm_gem_object_unreference(&obj->base);
2348 mutex_unlock(&dev->struct_mutex);
2353 * i915_gem_object_sync - sync an object to a ring.
2355 * @obj: object which may be in use on another ring.
2356 * @to: ring we wish to use the object on. May be NULL.
2358 * This code is meant to abstract object synchronization with the GPU.
2359 * Calling with NULL implies synchronizing the object with the CPU
2360 * rather than a particular GPU ring.
2362 * Returns 0 if successful, else propagates up the lower layer error.
2365 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2366 struct intel_ring_buffer *to)
2368 struct intel_ring_buffer *from = obj->ring;
2372 if (from == NULL || to == from)
2375 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2376 return i915_gem_object_wait_rendering(obj, false);
2378 idx = intel_ring_sync_index(from, to);
2380 seqno = obj->last_read_seqno;
2381 if (seqno <= from->sync_seqno[idx])
2384 ret = i915_gem_check_olr(obj->ring, seqno);
2388 ret = to->sync_to(to, from, seqno);
2390 from->sync_seqno[idx] = seqno;
2395 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2397 u32 old_write_domain, old_read_domains;
2399 /* Act a barrier for all accesses through the GTT */
2402 /* Force a pagefault for domain tracking on next user access */
2403 i915_gem_release_mmap(obj);
2405 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2408 old_read_domains = obj->base.read_domains;
2409 old_write_domain = obj->base.write_domain;
2411 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2412 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2414 trace_i915_gem_object_change_domain(obj,
2420 * Unbinds an object from the GTT aperture.
2423 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2425 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2428 if (obj->gtt_space == NULL)
2434 BUG_ON(obj->pages == NULL);
2436 ret = i915_gem_object_finish_gpu(obj);
2439 /* Continue on if we fail due to EIO, the GPU is hung so we
2440 * should be safe and we need to cleanup or else we might
2441 * cause memory corruption through use-after-free.
2444 i915_gem_object_finish_gtt(obj);
2446 /* release the fence reg _after_ flushing */
2447 ret = i915_gem_object_put_fence(obj);
2451 trace_i915_gem_object_unbind(obj);
2453 if (obj->has_global_gtt_mapping)
2454 i915_gem_gtt_unbind_object(obj);
2455 if (obj->has_aliasing_ppgtt_mapping) {
2456 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2457 obj->has_aliasing_ppgtt_mapping = 0;
2459 i915_gem_gtt_finish_object(obj);
2461 list_del(&obj->mm_list);
2462 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2463 /* Avoid an unnecessary call to unbind on rebind. */
2464 obj->map_and_fenceable = true;
2466 drm_mm_put_block(obj->gtt_space);
2467 obj->gtt_space = NULL;
2468 obj->gtt_offset = 0;
2473 static int i915_ring_idle(struct intel_ring_buffer *ring)
2475 if (list_empty(&ring->active_list))
2478 return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2481 int i915_gpu_idle(struct drm_device *dev)
2483 drm_i915_private_t *dev_priv = dev->dev_private;
2484 struct intel_ring_buffer *ring;
2487 /* Flush everything onto the inactive list. */
2488 for_each_ring(ring, dev_priv, i) {
2489 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2493 ret = i915_ring_idle(ring);
2501 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2502 struct drm_i915_gem_object *obj)
2504 drm_i915_private_t *dev_priv = dev->dev_private;
2508 u32 size = obj->gtt_space->size;
2510 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2512 val |= obj->gtt_offset & 0xfffff000;
2513 val |= (uint64_t)((obj->stride / 128) - 1) <<
2514 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2516 if (obj->tiling_mode == I915_TILING_Y)
2517 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2518 val |= I965_FENCE_REG_VALID;
2522 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2523 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2526 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2527 struct drm_i915_gem_object *obj)
2529 drm_i915_private_t *dev_priv = dev->dev_private;
2533 u32 size = obj->gtt_space->size;
2535 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2537 val |= obj->gtt_offset & 0xfffff000;
2538 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2539 if (obj->tiling_mode == I915_TILING_Y)
2540 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2541 val |= I965_FENCE_REG_VALID;
2545 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2546 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2549 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2550 struct drm_i915_gem_object *obj)
2552 drm_i915_private_t *dev_priv = dev->dev_private;
2556 u32 size = obj->gtt_space->size;
2560 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2561 (size & -size) != size ||
2562 (obj->gtt_offset & (size - 1)),
2563 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2564 obj->gtt_offset, obj->map_and_fenceable, size);
2566 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2571 /* Note: pitch better be a power of two tile widths */
2572 pitch_val = obj->stride / tile_width;
2573 pitch_val = ffs(pitch_val) - 1;
2575 val = obj->gtt_offset;
2576 if (obj->tiling_mode == I915_TILING_Y)
2577 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2578 val |= I915_FENCE_SIZE_BITS(size);
2579 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2580 val |= I830_FENCE_REG_VALID;
2585 reg = FENCE_REG_830_0 + reg * 4;
2587 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2589 I915_WRITE(reg, val);
2593 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2594 struct drm_i915_gem_object *obj)
2596 drm_i915_private_t *dev_priv = dev->dev_private;
2600 u32 size = obj->gtt_space->size;
2603 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2604 (size & -size) != size ||
2605 (obj->gtt_offset & (size - 1)),
2606 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2607 obj->gtt_offset, size);
2609 pitch_val = obj->stride / 128;
2610 pitch_val = ffs(pitch_val) - 1;
2612 val = obj->gtt_offset;
2613 if (obj->tiling_mode == I915_TILING_Y)
2614 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2615 val |= I830_FENCE_SIZE_BITS(size);
2616 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2617 val |= I830_FENCE_REG_VALID;
2621 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2622 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2625 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2626 struct drm_i915_gem_object *obj)
2628 switch (INTEL_INFO(dev)->gen) {
2630 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2632 case 4: i965_write_fence_reg(dev, reg, obj); break;
2633 case 3: i915_write_fence_reg(dev, reg, obj); break;
2634 case 2: i830_write_fence_reg(dev, reg, obj); break;
2639 static inline int fence_number(struct drm_i915_private *dev_priv,
2640 struct drm_i915_fence_reg *fence)
2642 return fence - dev_priv->fence_regs;
2645 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2646 struct drm_i915_fence_reg *fence,
2649 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2650 int reg = fence_number(dev_priv, fence);
2652 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2655 obj->fence_reg = reg;
2657 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2659 obj->fence_reg = I915_FENCE_REG_NONE;
2661 list_del_init(&fence->lru_list);
2666 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2668 if (obj->last_fenced_seqno) {
2669 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2673 obj->last_fenced_seqno = 0;
2676 /* Ensure that all CPU reads are completed before installing a fence
2677 * and all writes before removing the fence.
2679 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2682 obj->fenced_gpu_access = false;
2687 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2689 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2692 ret = i915_gem_object_flush_fence(obj);
2696 if (obj->fence_reg == I915_FENCE_REG_NONE)
2699 i915_gem_object_update_fence(obj,
2700 &dev_priv->fence_regs[obj->fence_reg],
2702 i915_gem_object_fence_lost(obj);
2707 static struct drm_i915_fence_reg *
2708 i915_find_fence_reg(struct drm_device *dev)
2710 struct drm_i915_private *dev_priv = dev->dev_private;
2711 struct drm_i915_fence_reg *reg, *avail;
2714 /* First try to find a free reg */
2716 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2717 reg = &dev_priv->fence_regs[i];
2721 if (!reg->pin_count)
2728 /* None available, try to steal one or wait for a user to finish */
2729 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2740 * i915_gem_object_get_fence - set up fencing for an object
2741 * @obj: object to map through a fence reg
2743 * When mapping objects through the GTT, userspace wants to be able to write
2744 * to them without having to worry about swizzling if the object is tiled.
2745 * This function walks the fence regs looking for a free one for @obj,
2746 * stealing one if it can't find any.
2748 * It then sets up the reg based on the object's properties: address, pitch
2749 * and tiling format.
2751 * For an untiled surface, this removes any existing fence.
2754 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2756 struct drm_device *dev = obj->base.dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 bool enable = obj->tiling_mode != I915_TILING_NONE;
2759 struct drm_i915_fence_reg *reg;
2762 /* Have we updated the tiling parameters upon the object and so
2763 * will need to serialise the write to the associated fence register?
2765 if (obj->fence_dirty) {
2766 ret = i915_gem_object_flush_fence(obj);
2771 /* Just update our place in the LRU if our fence is getting reused. */
2772 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2773 reg = &dev_priv->fence_regs[obj->fence_reg];
2774 if (!obj->fence_dirty) {
2775 list_move_tail(®->lru_list,
2776 &dev_priv->mm.fence_list);
2779 } else if (enable) {
2780 reg = i915_find_fence_reg(dev);
2785 struct drm_i915_gem_object *old = reg->obj;
2787 ret = i915_gem_object_flush_fence(old);
2791 i915_gem_object_fence_lost(old);
2796 i915_gem_object_update_fence(obj, reg, enable);
2797 obj->fence_dirty = false;
2802 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2803 struct drm_mm_node *gtt_space,
2804 unsigned long cache_level)
2806 struct drm_mm_node *other;
2808 /* On non-LLC machines we have to be careful when putting differing
2809 * types of snoopable memory together to avoid the prefetcher
2810 * crossing memory domains and dieing.
2815 if (gtt_space == NULL)
2818 if (list_empty(>t_space->node_list))
2821 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2822 if (other->allocated && !other->hole_follows && other->color != cache_level)
2825 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2826 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2832 static void i915_gem_verify_gtt(struct drm_device *dev)
2835 struct drm_i915_private *dev_priv = dev->dev_private;
2836 struct drm_i915_gem_object *obj;
2839 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2840 if (obj->gtt_space == NULL) {
2841 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2846 if (obj->cache_level != obj->gtt_space->color) {
2847 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2848 obj->gtt_space->start,
2849 obj->gtt_space->start + obj->gtt_space->size,
2851 obj->gtt_space->color);
2856 if (!i915_gem_valid_gtt_space(dev,
2858 obj->cache_level)) {
2859 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2860 obj->gtt_space->start,
2861 obj->gtt_space->start + obj->gtt_space->size,
2873 * Finds free space in the GTT aperture and binds the object there.
2876 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2878 bool map_and_fenceable,
2881 struct drm_device *dev = obj->base.dev;
2882 drm_i915_private_t *dev_priv = dev->dev_private;
2883 struct drm_mm_node *free_space;
2884 u32 size, fence_size, fence_alignment, unfenced_alignment;
2885 bool mappable, fenceable;
2888 if (obj->madv != I915_MADV_WILLNEED) {
2889 DRM_ERROR("Attempting to bind a purgeable object\n");
2893 fence_size = i915_gem_get_gtt_size(dev,
2896 fence_alignment = i915_gem_get_gtt_alignment(dev,
2899 unfenced_alignment =
2900 i915_gem_get_unfenced_gtt_alignment(dev,
2905 alignment = map_and_fenceable ? fence_alignment :
2907 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2908 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2912 size = map_and_fenceable ? fence_size : obj->base.size;
2914 /* If the object is bigger than the entire aperture, reject it early
2915 * before evicting everything in a vain attempt to find space.
2917 if (obj->base.size >
2918 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2919 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2923 ret = i915_gem_object_get_pages(obj);
2928 if (map_and_fenceable)
2930 drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2931 size, alignment, obj->cache_level,
2932 0, dev_priv->mm.gtt_mappable_end,
2935 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2936 size, alignment, obj->cache_level,
2939 if (free_space != NULL) {
2940 if (map_and_fenceable)
2942 drm_mm_get_block_range_generic(free_space,
2943 size, alignment, obj->cache_level,
2944 0, dev_priv->mm.gtt_mappable_end,
2948 drm_mm_get_block_generic(free_space,
2949 size, alignment, obj->cache_level,
2952 if (obj->gtt_space == NULL) {
2953 ret = i915_gem_evict_something(dev, size, alignment,
2962 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2964 obj->cache_level))) {
2965 drm_mm_put_block(obj->gtt_space);
2966 obj->gtt_space = NULL;
2971 ret = i915_gem_gtt_prepare_object(obj);
2973 drm_mm_put_block(obj->gtt_space);
2974 obj->gtt_space = NULL;
2978 if (!dev_priv->mm.aliasing_ppgtt)
2979 i915_gem_gtt_bind_object(obj, obj->cache_level);
2981 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2982 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2984 obj->gtt_offset = obj->gtt_space->start;
2987 obj->gtt_space->size == fence_size &&
2988 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2991 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2993 obj->map_and_fenceable = mappable && fenceable;
2995 trace_i915_gem_object_bind(obj, map_and_fenceable);
2996 i915_gem_verify_gtt(dev);
3001 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3003 /* If we don't have a page list set up, then we're not pinned
3004 * to GPU, and we can ignore the cache flush because it'll happen
3005 * again at bind time.
3007 if (obj->pages == NULL)
3010 /* If the GPU is snooping the contents of the CPU cache,
3011 * we do not need to manually clear the CPU cache lines. However,
3012 * the caches are only snooped when the render cache is
3013 * flushed/invalidated. As we always have to emit invalidations
3014 * and flushes when moving into and out of the RENDER domain, correct
3015 * snooping behaviour occurs naturally as the result of our domain
3018 if (obj->cache_level != I915_CACHE_NONE)
3021 trace_i915_gem_object_clflush(obj);
3023 drm_clflush_sg(obj->pages);
3026 /** Flushes the GTT write domain for the object if it's dirty. */
3028 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3030 uint32_t old_write_domain;
3032 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3035 /* No actual flushing is required for the GTT write domain. Writes
3036 * to it immediately go to main memory as far as we know, so there's
3037 * no chipset flush. It also doesn't land in render cache.
3039 * However, we do have to enforce the order so that all writes through
3040 * the GTT land before any writes to the device, such as updates to
3045 old_write_domain = obj->base.write_domain;
3046 obj->base.write_domain = 0;
3048 trace_i915_gem_object_change_domain(obj,
3049 obj->base.read_domains,
3053 /** Flushes the CPU write domain for the object if it's dirty. */
3055 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3057 uint32_t old_write_domain;
3059 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3062 i915_gem_clflush_object(obj);
3063 intel_gtt_chipset_flush();
3064 old_write_domain = obj->base.write_domain;
3065 obj->base.write_domain = 0;
3067 trace_i915_gem_object_change_domain(obj,
3068 obj->base.read_domains,
3073 * Moves a single object to the GTT read, and possibly write domain.
3075 * This function returns when the move is complete, including waiting on
3079 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3081 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3082 uint32_t old_write_domain, old_read_domains;
3085 /* Not valid to be called on unbound objects. */
3086 if (obj->gtt_space == NULL)
3089 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3092 ret = i915_gem_object_wait_rendering(obj, !write);
3096 i915_gem_object_flush_cpu_write_domain(obj);
3098 old_write_domain = obj->base.write_domain;
3099 old_read_domains = obj->base.read_domains;
3101 /* It should now be out of any other write domains, and we can update
3102 * the domain values for our changes.
3104 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3105 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3107 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3108 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3112 trace_i915_gem_object_change_domain(obj,
3116 /* And bump the LRU for this access */
3117 if (i915_gem_object_is_inactive(obj))
3118 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3123 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3124 enum i915_cache_level cache_level)
3126 struct drm_device *dev = obj->base.dev;
3127 drm_i915_private_t *dev_priv = dev->dev_private;
3130 if (obj->cache_level == cache_level)
3133 if (obj->pin_count) {
3134 DRM_DEBUG("can not change the cache level of pinned objects\n");
3138 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3139 ret = i915_gem_object_unbind(obj);
3144 if (obj->gtt_space) {
3145 ret = i915_gem_object_finish_gpu(obj);
3149 i915_gem_object_finish_gtt(obj);
3151 /* Before SandyBridge, you could not use tiling or fence
3152 * registers with snooped memory, so relinquish any fences
3153 * currently pointing to our region in the aperture.
3155 if (INTEL_INFO(dev)->gen < 6) {
3156 ret = i915_gem_object_put_fence(obj);
3161 if (obj->has_global_gtt_mapping)
3162 i915_gem_gtt_bind_object(obj, cache_level);
3163 if (obj->has_aliasing_ppgtt_mapping)
3164 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3167 obj->gtt_space->color = cache_level;
3170 if (cache_level == I915_CACHE_NONE) {
3171 u32 old_read_domains, old_write_domain;
3173 /* If we're coming from LLC cached, then we haven't
3174 * actually been tracking whether the data is in the
3175 * CPU cache or not, since we only allow one bit set
3176 * in obj->write_domain and have been skipping the clflushes.
3177 * Just set it to the CPU cache for now.
3179 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3180 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3182 old_read_domains = obj->base.read_domains;
3183 old_write_domain = obj->base.write_domain;
3185 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3186 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3188 trace_i915_gem_object_change_domain(obj,
3193 obj->cache_level = cache_level;
3194 i915_gem_verify_gtt(dev);
3198 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3199 struct drm_file *file)
3201 struct drm_i915_gem_caching *args = data;
3202 struct drm_i915_gem_object *obj;
3205 ret = i915_mutex_lock_interruptible(dev);
3209 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3210 if (&obj->base == NULL) {
3215 args->caching = obj->cache_level != I915_CACHE_NONE;
3217 drm_gem_object_unreference(&obj->base);
3219 mutex_unlock(&dev->struct_mutex);
3223 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3224 struct drm_file *file)
3226 struct drm_i915_gem_caching *args = data;
3227 struct drm_i915_gem_object *obj;
3228 enum i915_cache_level level;
3231 switch (args->caching) {
3232 case I915_CACHING_NONE:
3233 level = I915_CACHE_NONE;
3235 case I915_CACHING_CACHED:
3236 level = I915_CACHE_LLC;
3242 ret = i915_mutex_lock_interruptible(dev);
3246 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3247 if (&obj->base == NULL) {
3252 ret = i915_gem_object_set_cache_level(obj, level);
3254 drm_gem_object_unreference(&obj->base);
3256 mutex_unlock(&dev->struct_mutex);
3261 * Prepare buffer for display plane (scanout, cursors, etc).
3262 * Can be called from an uninterruptible phase (modesetting) and allows
3263 * any flushes to be pipelined (for pageflips).
3266 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3268 struct intel_ring_buffer *pipelined)
3270 u32 old_read_domains, old_write_domain;
3273 if (pipelined != obj->ring) {
3274 ret = i915_gem_object_sync(obj, pipelined);
3279 /* The display engine is not coherent with the LLC cache on gen6. As
3280 * a result, we make sure that the pinning that is about to occur is
3281 * done with uncached PTEs. This is lowest common denominator for all
3284 * However for gen6+, we could do better by using the GFDT bit instead
3285 * of uncaching, which would allow us to flush all the LLC-cached data
3286 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3288 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3292 /* As the user may map the buffer once pinned in the display plane
3293 * (e.g. libkms for the bootup splash), we have to ensure that we
3294 * always use map_and_fenceable for all scanout buffers.
3296 ret = i915_gem_object_pin(obj, alignment, true, false);
3300 i915_gem_object_flush_cpu_write_domain(obj);
3302 old_write_domain = obj->base.write_domain;
3303 old_read_domains = obj->base.read_domains;
3305 /* It should now be out of any other write domains, and we can update
3306 * the domain values for our changes.
3308 obj->base.write_domain = 0;
3309 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3311 trace_i915_gem_object_change_domain(obj,
3319 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3323 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3326 ret = i915_gem_object_wait_rendering(obj, false);
3330 /* Ensure that we invalidate the GPU's caches and TLBs. */
3331 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3336 * Moves a single object to the CPU read, and possibly write domain.
3338 * This function returns when the move is complete, including waiting on
3342 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3344 uint32_t old_write_domain, old_read_domains;
3347 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3350 ret = i915_gem_object_wait_rendering(obj, !write);
3354 i915_gem_object_flush_gtt_write_domain(obj);
3356 old_write_domain = obj->base.write_domain;
3357 old_read_domains = obj->base.read_domains;
3359 /* Flush the CPU cache if it's still invalid. */
3360 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3361 i915_gem_clflush_object(obj);
3363 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3366 /* It should now be out of any other write domains, and we can update
3367 * the domain values for our changes.
3369 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3371 /* If we're writing through the CPU, then the GPU read domains will
3372 * need to be invalidated at next use.
3375 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3376 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3379 trace_i915_gem_object_change_domain(obj,
3386 /* Throttle our rendering by waiting until the ring has completed our requests
3387 * emitted over 20 msec ago.
3389 * Note that if we were to use the current jiffies each time around the loop,
3390 * we wouldn't escape the function with any frames outstanding if the time to
3391 * render a frame was over 20ms.
3393 * This should get us reasonable parallelism between CPU and GPU but also
3394 * relatively low latency when blocking on a particular request to finish.
3397 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400 struct drm_i915_file_private *file_priv = file->driver_priv;
3401 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3402 struct drm_i915_gem_request *request;
3403 struct intel_ring_buffer *ring = NULL;
3407 if (atomic_read(&dev_priv->mm.wedged))
3410 spin_lock(&file_priv->mm.lock);
3411 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3412 if (time_after_eq(request->emitted_jiffies, recent_enough))
3415 ring = request->ring;
3416 seqno = request->seqno;
3418 spin_unlock(&file_priv->mm.lock);
3423 ret = __wait_seqno(ring, seqno, true, NULL);
3425 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3431 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3433 bool map_and_fenceable,
3438 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3441 if (obj->gtt_space != NULL) {
3442 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3443 (map_and_fenceable && !obj->map_and_fenceable)) {
3444 WARN(obj->pin_count,
3445 "bo is already pinned with incorrect alignment:"
3446 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3447 " obj->map_and_fenceable=%d\n",
3448 obj->gtt_offset, alignment,
3450 obj->map_and_fenceable);
3451 ret = i915_gem_object_unbind(obj);
3457 if (obj->gtt_space == NULL) {
3458 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3465 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3466 i915_gem_gtt_bind_object(obj, obj->cache_level);
3469 obj->pin_mappable |= map_and_fenceable;
3475 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3477 BUG_ON(obj->pin_count == 0);
3478 BUG_ON(obj->gtt_space == NULL);
3480 if (--obj->pin_count == 0)
3481 obj->pin_mappable = false;
3485 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3486 struct drm_file *file)
3488 struct drm_i915_gem_pin *args = data;
3489 struct drm_i915_gem_object *obj;
3492 ret = i915_mutex_lock_interruptible(dev);
3496 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3497 if (&obj->base == NULL) {
3502 if (obj->madv != I915_MADV_WILLNEED) {
3503 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3508 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3509 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3515 obj->user_pin_count++;
3516 obj->pin_filp = file;
3517 if (obj->user_pin_count == 1) {
3518 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3523 /* XXX - flush the CPU caches for pinned objects
3524 * as the X server doesn't manage domains yet
3526 i915_gem_object_flush_cpu_write_domain(obj);
3527 args->offset = obj->gtt_offset;
3529 drm_gem_object_unreference(&obj->base);
3531 mutex_unlock(&dev->struct_mutex);
3536 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3537 struct drm_file *file)
3539 struct drm_i915_gem_pin *args = data;
3540 struct drm_i915_gem_object *obj;
3543 ret = i915_mutex_lock_interruptible(dev);
3547 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3548 if (&obj->base == NULL) {
3553 if (obj->pin_filp != file) {
3554 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3559 obj->user_pin_count--;
3560 if (obj->user_pin_count == 0) {
3561 obj->pin_filp = NULL;
3562 i915_gem_object_unpin(obj);
3566 drm_gem_object_unreference(&obj->base);
3568 mutex_unlock(&dev->struct_mutex);
3573 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3574 struct drm_file *file)
3576 struct drm_i915_gem_busy *args = data;
3577 struct drm_i915_gem_object *obj;
3580 ret = i915_mutex_lock_interruptible(dev);
3584 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3585 if (&obj->base == NULL) {
3590 /* Count all active objects as busy, even if they are currently not used
3591 * by the gpu. Users of this interface expect objects to eventually
3592 * become non-busy without any further actions, therefore emit any
3593 * necessary flushes here.
3595 ret = i915_gem_object_flush_active(obj);
3597 args->busy = obj->active;
3599 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3600 args->busy |= intel_ring_flag(obj->ring) << 16;
3603 drm_gem_object_unreference(&obj->base);
3605 mutex_unlock(&dev->struct_mutex);
3610 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3611 struct drm_file *file_priv)
3613 return i915_gem_ring_throttle(dev, file_priv);
3617 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3618 struct drm_file *file_priv)
3620 struct drm_i915_gem_madvise *args = data;
3621 struct drm_i915_gem_object *obj;
3624 switch (args->madv) {
3625 case I915_MADV_DONTNEED:
3626 case I915_MADV_WILLNEED:
3632 ret = i915_mutex_lock_interruptible(dev);
3636 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3637 if (&obj->base == NULL) {
3642 if (obj->pin_count) {
3647 if (obj->madv != __I915_MADV_PURGED)
3648 obj->madv = args->madv;
3650 /* if the object is no longer attached, discard its backing storage */
3651 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3652 i915_gem_object_truncate(obj);
3654 args->retained = obj->madv != __I915_MADV_PURGED;
3657 drm_gem_object_unreference(&obj->base);
3659 mutex_unlock(&dev->struct_mutex);
3663 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3664 const struct drm_i915_gem_object_ops *ops)
3666 INIT_LIST_HEAD(&obj->mm_list);
3667 INIT_LIST_HEAD(&obj->gtt_list);
3668 INIT_LIST_HEAD(&obj->ring_list);
3669 INIT_LIST_HEAD(&obj->exec_list);
3673 obj->fence_reg = I915_FENCE_REG_NONE;
3674 obj->madv = I915_MADV_WILLNEED;
3675 /* Avoid an unnecessary call to unbind on the first bind. */
3676 obj->map_and_fenceable = true;
3678 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3681 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3682 .get_pages = i915_gem_object_get_pages_gtt,
3683 .put_pages = i915_gem_object_put_pages_gtt,
3686 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3689 struct drm_i915_gem_object *obj;
3690 struct address_space *mapping;
3693 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3697 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3702 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3703 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3704 /* 965gm cannot relocate objects above 4GiB. */
3705 mask &= ~__GFP_HIGHMEM;
3706 mask |= __GFP_DMA32;
3709 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3710 mapping_set_gfp_mask(mapping, mask);
3712 i915_gem_object_init(obj, &i915_gem_object_ops);
3714 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3715 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3718 /* On some devices, we can have the GPU use the LLC (the CPU
3719 * cache) for about a 10% performance improvement
3720 * compared to uncached. Graphics requests other than
3721 * display scanout are coherent with the CPU in
3722 * accessing this cache. This means in this mode we
3723 * don't need to clflush on the CPU side, and on the
3724 * GPU side we only need to flush internal caches to
3725 * get data visible to the CPU.
3727 * However, we maintain the display planes as UC, and so
3728 * need to rebind when first used as such.
3730 obj->cache_level = I915_CACHE_LLC;
3732 obj->cache_level = I915_CACHE_NONE;
3737 int i915_gem_init_object(struct drm_gem_object *obj)
3744 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3746 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3747 struct drm_device *dev = obj->base.dev;
3748 drm_i915_private_t *dev_priv = dev->dev_private;
3750 trace_i915_gem_object_destroy(obj);
3753 i915_gem_detach_phys_object(dev, obj);
3756 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3757 bool was_interruptible;
3759 was_interruptible = dev_priv->mm.interruptible;
3760 dev_priv->mm.interruptible = false;
3762 WARN_ON(i915_gem_object_unbind(obj));
3764 dev_priv->mm.interruptible = was_interruptible;
3767 obj->pages_pin_count = 0;
3768 i915_gem_object_put_pages(obj);
3769 i915_gem_object_free_mmap_offset(obj);
3773 if (obj->base.import_attach)
3774 drm_prime_gem_destroy(&obj->base, NULL);
3776 drm_gem_object_release(&obj->base);
3777 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3784 i915_gem_idle(struct drm_device *dev)
3786 drm_i915_private_t *dev_priv = dev->dev_private;
3789 mutex_lock(&dev->struct_mutex);
3791 if (dev_priv->mm.suspended) {
3792 mutex_unlock(&dev->struct_mutex);
3796 ret = i915_gpu_idle(dev);
3798 mutex_unlock(&dev->struct_mutex);
3801 i915_gem_retire_requests(dev);
3803 /* Under UMS, be paranoid and evict. */
3804 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3805 i915_gem_evict_everything(dev);
3807 i915_gem_reset_fences(dev);
3809 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3810 * We need to replace this with a semaphore, or something.
3811 * And not confound mm.suspended!
3813 dev_priv->mm.suspended = 1;
3814 del_timer_sync(&dev_priv->hangcheck_timer);
3816 i915_kernel_lost_context(dev);
3817 i915_gem_cleanup_ringbuffer(dev);
3819 mutex_unlock(&dev->struct_mutex);
3821 /* Cancel the retire work handler, which should be idle now. */
3822 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3827 void i915_gem_l3_remap(struct drm_device *dev)
3829 drm_i915_private_t *dev_priv = dev->dev_private;
3833 if (!IS_IVYBRIDGE(dev))
3836 if (!dev_priv->mm.l3_remap_info)
3839 misccpctl = I915_READ(GEN7_MISCCPCTL);
3840 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3841 POSTING_READ(GEN7_MISCCPCTL);
3843 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3844 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3845 if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
3846 DRM_DEBUG("0x%x was already programmed to %x\n",
3847 GEN7_L3LOG_BASE + i, remap);
3848 if (remap && !dev_priv->mm.l3_remap_info[i/4])
3849 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3850 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
3853 /* Make sure all the writes land before disabling dop clock gating */
3854 POSTING_READ(GEN7_L3LOG_BASE);
3856 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3859 void i915_gem_init_swizzling(struct drm_device *dev)
3861 drm_i915_private_t *dev_priv = dev->dev_private;
3863 if (INTEL_INFO(dev)->gen < 5 ||
3864 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3867 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3868 DISP_TILE_SURFACE_SWIZZLING);
3873 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3875 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3877 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3880 void i915_gem_init_ppgtt(struct drm_device *dev)
3882 drm_i915_private_t *dev_priv = dev->dev_private;
3884 struct intel_ring_buffer *ring;
3885 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3886 uint32_t __iomem *pd_addr;
3890 if (!dev_priv->mm.aliasing_ppgtt)
3894 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3895 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3898 if (dev_priv->mm.gtt->needs_dmar)
3899 pt_addr = ppgtt->pt_dma_addr[i];
3901 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3903 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3904 pd_entry |= GEN6_PDE_VALID;
3906 writel(pd_entry, pd_addr + i);
3910 pd_offset = ppgtt->pd_offset;
3911 pd_offset /= 64; /* in cachelines, */
3914 if (INTEL_INFO(dev)->gen == 6) {
3915 uint32_t ecochk, gab_ctl, ecobits;
3917 ecobits = I915_READ(GAC_ECO_BITS);
3918 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3920 gab_ctl = I915_READ(GAB_CTL);
3921 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3923 ecochk = I915_READ(GAM_ECOCHK);
3924 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3925 ECOCHK_PPGTT_CACHE64B);
3926 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3927 } else if (INTEL_INFO(dev)->gen >= 7) {
3928 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3929 /* GFX_MODE is per-ring on gen7+ */
3932 for_each_ring(ring, dev_priv, i) {
3933 if (INTEL_INFO(dev)->gen >= 7)
3934 I915_WRITE(RING_MODE_GEN7(ring),
3935 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3937 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3938 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3943 intel_enable_blt(struct drm_device *dev)
3948 /* The blitter was dysfunctional on early prototypes */
3949 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3950 DRM_INFO("BLT not supported on this pre-production hardware;"
3951 " graphics performance will be degraded.\n");
3959 i915_gem_init_hw(struct drm_device *dev)
3961 drm_i915_private_t *dev_priv = dev->dev_private;
3964 if (!intel_enable_gtt())
3967 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3968 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3970 i915_gem_l3_remap(dev);
3972 i915_gem_init_swizzling(dev);
3974 ret = intel_init_render_ring_buffer(dev);
3979 ret = intel_init_bsd_ring_buffer(dev);
3981 goto cleanup_render_ring;
3984 if (intel_enable_blt(dev)) {
3985 ret = intel_init_blt_ring_buffer(dev);
3987 goto cleanup_bsd_ring;
3990 dev_priv->next_seqno = 1;
3993 * XXX: There was some w/a described somewhere suggesting loading
3994 * contexts before PPGTT.
3996 i915_gem_context_init(dev);
3997 i915_gem_init_ppgtt(dev);
4002 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4003 cleanup_render_ring:
4004 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4009 intel_enable_ppgtt(struct drm_device *dev)
4011 if (i915_enable_ppgtt >= 0)
4012 return i915_enable_ppgtt;
4014 #ifdef CONFIG_INTEL_IOMMU
4015 /* Disable ppgtt on SNB if VT-d is on. */
4016 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
4023 int i915_gem_init(struct drm_device *dev)
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 unsigned long gtt_size, mappable_size;
4029 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
4030 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
4032 mutex_lock(&dev->struct_mutex);
4033 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
4034 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4035 * aperture accordingly when using aliasing ppgtt. */
4036 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4038 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4040 ret = i915_gem_init_aliasing_ppgtt(dev);
4042 mutex_unlock(&dev->struct_mutex);
4046 /* Let GEM Manage all of the aperture.
4048 * However, leave one page at the end still bound to the scratch
4049 * page. There are a number of places where the hardware
4050 * apparently prefetches past the end of the object, and we've
4051 * seen multiple hangs with the GPU head pointer stuck in a
4052 * batchbuffer bound at the last page of the aperture. One page
4053 * should be enough to keep any prefetching inside of the
4056 i915_gem_init_global_gtt(dev, 0, mappable_size,
4060 ret = i915_gem_init_hw(dev);
4061 mutex_unlock(&dev->struct_mutex);
4063 i915_gem_cleanup_aliasing_ppgtt(dev);
4067 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4068 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4069 dev_priv->dri1.allow_batchbuffer = 1;
4074 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4076 drm_i915_private_t *dev_priv = dev->dev_private;
4077 struct intel_ring_buffer *ring;
4080 for_each_ring(ring, dev_priv, i)
4081 intel_cleanup_ring_buffer(ring);
4085 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4086 struct drm_file *file_priv)
4088 drm_i915_private_t *dev_priv = dev->dev_private;
4091 if (drm_core_check_feature(dev, DRIVER_MODESET))
4094 if (atomic_read(&dev_priv->mm.wedged)) {
4095 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4096 atomic_set(&dev_priv->mm.wedged, 0);
4099 mutex_lock(&dev->struct_mutex);
4100 dev_priv->mm.suspended = 0;
4102 ret = i915_gem_init_hw(dev);
4104 mutex_unlock(&dev->struct_mutex);
4108 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4109 mutex_unlock(&dev->struct_mutex);
4111 ret = drm_irq_install(dev);
4113 goto cleanup_ringbuffer;
4118 mutex_lock(&dev->struct_mutex);
4119 i915_gem_cleanup_ringbuffer(dev);
4120 dev_priv->mm.suspended = 1;
4121 mutex_unlock(&dev->struct_mutex);
4127 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4128 struct drm_file *file_priv)
4130 if (drm_core_check_feature(dev, DRIVER_MODESET))
4133 drm_irq_uninstall(dev);
4134 return i915_gem_idle(dev);
4138 i915_gem_lastclose(struct drm_device *dev)
4142 if (drm_core_check_feature(dev, DRIVER_MODESET))
4145 ret = i915_gem_idle(dev);
4147 DRM_ERROR("failed to idle hardware: %d\n", ret);
4151 init_ring_lists(struct intel_ring_buffer *ring)
4153 INIT_LIST_HEAD(&ring->active_list);
4154 INIT_LIST_HEAD(&ring->request_list);
4158 i915_gem_load(struct drm_device *dev)
4161 drm_i915_private_t *dev_priv = dev->dev_private;
4163 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4164 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4165 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4166 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4167 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4168 for (i = 0; i < I915_NUM_RINGS; i++)
4169 init_ring_lists(&dev_priv->ring[i]);
4170 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4171 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4172 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4173 i915_gem_retire_work_handler);
4174 init_completion(&dev_priv->error_completion);
4176 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4178 I915_WRITE(MI_ARB_STATE,
4179 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4182 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4184 /* Old X drivers will take 0-2 for front, back, depth buffers */
4185 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4186 dev_priv->fence_reg_start = 3;
4188 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4189 dev_priv->num_fence_regs = 16;
4191 dev_priv->num_fence_regs = 8;
4193 /* Initialize fence registers to zero */
4194 i915_gem_reset_fences(dev);
4196 i915_gem_detect_bit_6_swizzle(dev);
4197 init_waitqueue_head(&dev_priv->pending_flip_queue);
4199 dev_priv->mm.interruptible = true;
4201 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4202 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4203 register_shrinker(&dev_priv->mm.inactive_shrinker);
4207 * Create a physically contiguous memory object for this object
4208 * e.g. for cursor + overlay regs
4210 static int i915_gem_init_phys_object(struct drm_device *dev,
4211 int id, int size, int align)
4213 drm_i915_private_t *dev_priv = dev->dev_private;
4214 struct drm_i915_gem_phys_object *phys_obj;
4217 if (dev_priv->mm.phys_objs[id - 1] || !size)
4220 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4226 phys_obj->handle = drm_pci_alloc(dev, size, align);
4227 if (!phys_obj->handle) {
4232 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4235 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4243 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4245 drm_i915_private_t *dev_priv = dev->dev_private;
4246 struct drm_i915_gem_phys_object *phys_obj;
4248 if (!dev_priv->mm.phys_objs[id - 1])
4251 phys_obj = dev_priv->mm.phys_objs[id - 1];
4252 if (phys_obj->cur_obj) {
4253 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4257 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4259 drm_pci_free(dev, phys_obj->handle);
4261 dev_priv->mm.phys_objs[id - 1] = NULL;
4264 void i915_gem_free_all_phys_object(struct drm_device *dev)
4268 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4269 i915_gem_free_phys_object(dev, i);
4272 void i915_gem_detach_phys_object(struct drm_device *dev,
4273 struct drm_i915_gem_object *obj)
4275 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4282 vaddr = obj->phys_obj->handle->vaddr;
4284 page_count = obj->base.size / PAGE_SIZE;
4285 for (i = 0; i < page_count; i++) {
4286 struct page *page = shmem_read_mapping_page(mapping, i);
4287 if (!IS_ERR(page)) {
4288 char *dst = kmap_atomic(page);
4289 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4292 drm_clflush_pages(&page, 1);
4294 set_page_dirty(page);
4295 mark_page_accessed(page);
4296 page_cache_release(page);
4299 intel_gtt_chipset_flush();
4301 obj->phys_obj->cur_obj = NULL;
4302 obj->phys_obj = NULL;
4306 i915_gem_attach_phys_object(struct drm_device *dev,
4307 struct drm_i915_gem_object *obj,
4311 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4312 drm_i915_private_t *dev_priv = dev->dev_private;
4317 if (id > I915_MAX_PHYS_OBJECT)
4320 if (obj->phys_obj) {
4321 if (obj->phys_obj->id == id)
4323 i915_gem_detach_phys_object(dev, obj);
4326 /* create a new object */
4327 if (!dev_priv->mm.phys_objs[id - 1]) {
4328 ret = i915_gem_init_phys_object(dev, id,
4329 obj->base.size, align);
4331 DRM_ERROR("failed to init phys object %d size: %zu\n",
4332 id, obj->base.size);
4337 /* bind to the object */
4338 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4339 obj->phys_obj->cur_obj = obj;
4341 page_count = obj->base.size / PAGE_SIZE;
4343 for (i = 0; i < page_count; i++) {
4347 page = shmem_read_mapping_page(mapping, i);
4349 return PTR_ERR(page);
4351 src = kmap_atomic(page);
4352 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4353 memcpy(dst, src, PAGE_SIZE);
4356 mark_page_accessed(page);
4357 page_cache_release(page);
4364 i915_gem_phys_pwrite(struct drm_device *dev,
4365 struct drm_i915_gem_object *obj,
4366 struct drm_i915_gem_pwrite *args,
4367 struct drm_file *file_priv)
4369 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4370 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4372 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4373 unsigned long unwritten;
4375 /* The physical object once assigned is fixed for the lifetime
4376 * of the obj, so we can safely drop the lock and continue
4379 mutex_unlock(&dev->struct_mutex);
4380 unwritten = copy_from_user(vaddr, user_data, args->size);
4381 mutex_lock(&dev->struct_mutex);
4386 intel_gtt_chipset_flush();
4390 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4392 struct drm_i915_file_private *file_priv = file->driver_priv;
4394 /* Clean up our request list when the client is going away, so that
4395 * later retire_requests won't dereference our soon-to-be-gone
4398 spin_lock(&file_priv->mm.lock);
4399 while (!list_empty(&file_priv->mm.request_list)) {
4400 struct drm_i915_gem_request *request;
4402 request = list_first_entry(&file_priv->mm.request_list,
4403 struct drm_i915_gem_request,
4405 list_del(&request->client_list);
4406 request->file_priv = NULL;
4408 spin_unlock(&file_priv->mm.lock);
4412 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4414 struct drm_i915_private *dev_priv =
4415 container_of(shrinker,
4416 struct drm_i915_private,
4417 mm.inactive_shrinker);
4418 struct drm_device *dev = dev_priv->dev;
4419 struct drm_i915_gem_object *obj;
4420 int nr_to_scan = sc->nr_to_scan;
4423 if (!mutex_trylock(&dev->struct_mutex))
4427 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4429 i915_gem_shrink_all(dev_priv);
4433 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4434 if (obj->pages_pin_count == 0)
4435 cnt += obj->base.size >> PAGE_SHIFT;
4436 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4437 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4438 cnt += obj->base.size >> PAGE_SHIFT;
4440 mutex_unlock(&dev->struct_mutex);